sparc.c revision 146895
1/* Subroutines for insn-output.c for SPARC. 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4 Contributed by Michael Tiemann (tiemann@cygnus.com) 5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 6 at Cygnus Support. 7 8This file is part of GCC. 9 10GCC is free software; you can redistribute it and/or modify 11it under the terms of the GNU General Public License as published by 12the Free Software Foundation; either version 2, or (at your option) 13any later version. 14 15GCC is distributed in the hope that it will be useful, 16but WITHOUT ANY WARRANTY; without even the implied warranty of 17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18GNU General Public License for more details. 19 20You should have received a copy of the GNU General Public License 21along with GCC; see the file COPYING. If not, write to 22the Free Software Foundation, 59 Temple Place - Suite 330, 23Boston, MA 02111-1307, USA. */ 24 25#include "config.h" 26#include "system.h" 27#include "coretypes.h" 28#include "tm.h" 29#include "tree.h" 30#include "rtl.h" 31#include "regs.h" 32#include "hard-reg-set.h" 33#include "real.h" 34#include "insn-config.h" 35#include "conditions.h" 36#include "output.h" 37#include "insn-attr.h" 38#include "flags.h" 39#include "function.h" 40#include "expr.h" 41#include "optabs.h" 42#include "recog.h" 43#include "toplev.h" 44#include "ggc.h" 45#include "tm_p.h" 46#include "debug.h" 47#include "target.h" 48#include "target-def.h" 49#include "cfglayout.h" 50 51/* 1 if the caller has placed an "unimp" insn immediately after the call. 52 This is used in v8 code when calling a function that returns a structure. 53 v9 doesn't have this. Be careful to have this test be the same as that 54 used on the call. */ 55 56#define SKIP_CALLERS_UNIMP_P \ 57(!TARGET_ARCH64 && current_function_returns_struct \ 58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ 59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ 60 == INTEGER_CST)) 61 62/* Global variables for machine-dependent things. */ 63 64/* Size of frame. Need to know this to emit return insns from leaf procedures. 65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the 66 reload pass. This is important as the value is later used in insn 67 scheduling (to see what can go in a delay slot). 68 APPARENT_FSIZE is the size of the stack less the register save area and less 69 the outgoing argument area. It is used when saving call preserved regs. */ 70static HOST_WIDE_INT apparent_fsize; 71static HOST_WIDE_INT actual_fsize; 72 73/* Number of live general or floating point registers needed to be 74 saved (as 4-byte quantities). */ 75static int num_gfregs; 76 77/* Save the operands last given to a compare for use when we 78 generate a scc or bcc insn. */ 79rtx sparc_compare_op0, sparc_compare_op1; 80 81/* Coordinate with the md file wrt special insns created by 82 sparc_nonflat_function_epilogue. */ 83bool sparc_emitting_epilogue; 84 85/* Vector to say how input registers are mapped to output registers. 86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to 87 eliminate it. You must use -fomit-frame-pointer to get that. */ 88char leaf_reg_remap[] = 89{ 0, 1, 2, 3, 4, 5, 6, 7, 90 -1, -1, -1, -1, -1, -1, 14, -1, 91 -1, -1, -1, -1, -1, -1, -1, -1, 92 8, 9, 10, 11, 12, 13, -1, 15, 93 94 32, 33, 34, 35, 36, 37, 38, 39, 95 40, 41, 42, 43, 44, 45, 46, 47, 96 48, 49, 50, 51, 52, 53, 54, 55, 97 56, 57, 58, 59, 60, 61, 62, 63, 98 64, 65, 66, 67, 68, 69, 70, 71, 99 72, 73, 74, 75, 76, 77, 78, 79, 100 80, 81, 82, 83, 84, 85, 86, 87, 101 88, 89, 90, 91, 92, 93, 94, 95, 102 96, 97, 98, 99, 100}; 103 104/* Vector, indexed by hard register number, which contains 1 105 for a register that is allowable in a candidate for leaf 106 function treatment. */ 107char sparc_leaf_regs[] = 108{ 1, 1, 1, 1, 1, 1, 1, 1, 109 0, 0, 0, 0, 0, 0, 1, 0, 110 0, 0, 0, 0, 0, 0, 0, 0, 111 1, 1, 1, 1, 1, 1, 0, 1, 112 1, 1, 1, 1, 1, 1, 1, 1, 113 1, 1, 1, 1, 1, 1, 1, 1, 114 1, 1, 1, 1, 1, 1, 1, 1, 115 1, 1, 1, 1, 1, 1, 1, 1, 116 1, 1, 1, 1, 1, 1, 1, 1, 117 1, 1, 1, 1, 1, 1, 1, 1, 118 1, 1, 1, 1, 1, 1, 1, 1, 119 1, 1, 1, 1, 1, 1, 1, 1, 120 1, 1, 1, 1, 1}; 121 122struct machine_function GTY(()) 123{ 124 /* Some local-dynamic TLS symbol name. */ 125 const char *some_ld_name; 126}; 127 128/* Name of where we pretend to think the frame pointer points. 129 Normally, this is "%fp", but if we are in a leaf procedure, 130 this is "%sp+something". We record "something" separately as it may be 131 too big for reg+constant addressing. */ 132 133static const char *frame_base_name; 134static HOST_WIDE_INT frame_base_offset; 135 136static void sparc_init_modes (void); 137static int save_regs (FILE *, int, int, const char *, int, int, HOST_WIDE_INT); 138static int restore_regs (FILE *, int, int, const char *, int, int); 139static void build_big_number (FILE *, HOST_WIDE_INT, const char *); 140static void scan_record_type (tree, int *, int *, int *); 141static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode, 142 tree, int, int, int *, int *); 143 144static int supersparc_adjust_cost (rtx, rtx, rtx, int); 145static int hypersparc_adjust_cost (rtx, rtx, rtx, int); 146 147static void sparc_output_addr_vec (rtx); 148static void sparc_output_addr_diff_vec (rtx); 149static void sparc_output_deferred_case_vectors (void); 150static int check_return_regs (rtx); 151static int epilogue_renumber (rtx *, int); 152static bool sparc_assemble_integer (rtx, unsigned int, int); 153static int set_extends (rtx); 154static void output_restore_regs (FILE *, int); 155static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT); 156static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT); 157static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT); 158static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT); 159static void sparc_flat_save_restore (FILE *, const char *, int, 160 unsigned long, unsigned long, 161 const char *, const char *, 162 HOST_WIDE_INT); 163static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int); 164static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int); 165#ifdef OBJECT_FORMAT_ELF 166static void sparc_elf_asm_named_section (const char *, unsigned int); 167#endif 168static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT) 169 ATTRIBUTE_UNUSED; 170static void sparc_aout_select_rtx_section (enum machine_mode, rtx, 171 unsigned HOST_WIDE_INT) 172 ATTRIBUTE_UNUSED; 173 174static int sparc_adjust_cost (rtx, rtx, rtx, int); 175static int sparc_issue_rate (void); 176static void sparc_sched_init (FILE *, int, int); 177static int sparc_use_dfa_pipeline_interface (void); 178static int sparc_use_sched_lookahead (void); 179 180static void emit_soft_tfmode_libcall (const char *, int, rtx *); 181static void emit_soft_tfmode_binop (enum rtx_code, rtx *); 182static void emit_soft_tfmode_unop (enum rtx_code, rtx *); 183static void emit_soft_tfmode_cvt (enum rtx_code, rtx *); 184static void emit_hard_tfmode_operation (enum rtx_code, rtx *); 185 186static bool sparc_function_ok_for_sibcall (tree, tree); 187static void sparc_init_libfuncs (void); 188static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, 189 HOST_WIDE_INT, tree); 190static bool sparc_can_output_mi_thunk (tree, HOST_WIDE_INT, 191 HOST_WIDE_INT, tree); 192static struct machine_function * sparc_init_machine_status (void); 193static bool sparc_cannot_force_const_mem (rtx); 194static rtx sparc_tls_get_addr (void); 195static rtx sparc_tls_got (void); 196static const char *get_some_local_dynamic_name (void); 197static int get_some_local_dynamic_name_1 (rtx *, void *); 198static bool sparc_rtx_costs (rtx, int, int, int *); 199 200/* Option handling. */ 201 202/* Code model option as passed by user. */ 203const char *sparc_cmodel_string; 204/* Parsed value. */ 205enum cmodel sparc_cmodel; 206 207char sparc_hard_reg_printed[8]; 208 209struct sparc_cpu_select sparc_select[] = 210{ 211 /* switch name, tune arch */ 212 { (char *)0, "default", 1, 1 }, 213 { (char *)0, "-mcpu=", 1, 1 }, 214 { (char *)0, "-mtune=", 1, 0 }, 215 { 0, 0, 0, 0 } 216}; 217 218/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ 219enum processor_type sparc_cpu; 220 221/* Initialize the GCC target structure. */ 222 223/* The sparc default is to use .half rather than .short for aligned 224 HI objects. Use .word instead of .long on non-ELF systems. */ 225#undef TARGET_ASM_ALIGNED_HI_OP 226#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 227#ifndef OBJECT_FORMAT_ELF 228#undef TARGET_ASM_ALIGNED_SI_OP 229#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 230#endif 231 232#undef TARGET_ASM_UNALIGNED_HI_OP 233#define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" 234#undef TARGET_ASM_UNALIGNED_SI_OP 235#define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" 236#undef TARGET_ASM_UNALIGNED_DI_OP 237#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" 238 239/* The target hook has to handle DI-mode values. */ 240#undef TARGET_ASM_INTEGER 241#define TARGET_ASM_INTEGER sparc_assemble_integer 242 243#undef TARGET_ASM_FUNCTION_PROLOGUE 244#define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue 245#undef TARGET_ASM_FUNCTION_EPILOGUE 246#define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue 247 248#undef TARGET_SCHED_ADJUST_COST 249#define TARGET_SCHED_ADJUST_COST sparc_adjust_cost 250#undef TARGET_SCHED_ISSUE_RATE 251#define TARGET_SCHED_ISSUE_RATE sparc_issue_rate 252#undef TARGET_SCHED_INIT 253#define TARGET_SCHED_INIT sparc_sched_init 254#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE 255#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface 256#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD 257#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead 258 259#undef TARGET_FUNCTION_OK_FOR_SIBCALL 260#define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall 261 262#undef TARGET_INIT_LIBFUNCS 263#define TARGET_INIT_LIBFUNCS sparc_init_libfuncs 264 265#ifdef HAVE_AS_TLS 266#undef TARGET_HAVE_TLS 267#define TARGET_HAVE_TLS true 268#endif 269#undef TARGET_CANNOT_FORCE_CONST_MEM 270#define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem 271 272#undef TARGET_ASM_OUTPUT_MI_THUNK 273#define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk 274#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 275#define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk 276 277#undef TARGET_RTX_COSTS 278#define TARGET_RTX_COSTS sparc_rtx_costs 279#undef TARGET_ADDRESS_COST 280#define TARGET_ADDRESS_COST hook_int_rtx_0 281 282struct gcc_target targetm = TARGET_INITIALIZER; 283 284/* Validate and override various options, and do some machine dependent 285 initialization. */ 286 287void 288sparc_override_options (void) 289{ 290 static struct code_model { 291 const char *const name; 292 const int value; 293 } const cmodels[] = { 294 { "32", CM_32 }, 295 { "medlow", CM_MEDLOW }, 296 { "medmid", CM_MEDMID }, 297 { "medany", CM_MEDANY }, 298 { "embmedany", CM_EMBMEDANY }, 299 { 0, 0 } 300 }; 301 const struct code_model *cmodel; 302 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ 303 static struct cpu_default { 304 const int cpu; 305 const char *const name; 306 } const cpu_default[] = { 307 /* There must be one entry here for each TARGET_CPU value. */ 308 { TARGET_CPU_sparc, "cypress" }, 309 { TARGET_CPU_sparclet, "tsc701" }, 310 { TARGET_CPU_sparclite, "f930" }, 311 { TARGET_CPU_v8, "v8" }, 312 { TARGET_CPU_hypersparc, "hypersparc" }, 313 { TARGET_CPU_sparclite86x, "sparclite86x" }, 314 { TARGET_CPU_supersparc, "supersparc" }, 315 { TARGET_CPU_v9, "v9" }, 316 { TARGET_CPU_ultrasparc, "ultrasparc" }, 317 { TARGET_CPU_ultrasparc3, "ultrasparc3" }, 318 { 0, 0 } 319 }; 320 const struct cpu_default *def; 321 /* Table of values for -m{cpu,tune}=. */ 322 static struct cpu_table { 323 const char *const name; 324 const enum processor_type processor; 325 const int disable; 326 const int enable; 327 } const cpu_table[] = { 328 { "v7", PROCESSOR_V7, MASK_ISA, 0 }, 329 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, 330 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, 331 /* TI TMS390Z55 supersparc */ 332 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, 333 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, 334 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. 335 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ 336 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, 337 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, 338 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, 339 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, 340 MASK_SPARCLITE }, 341 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, 342 /* TEMIC sparclet */ 343 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, 344 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, 345 /* TI ultrasparc I, II, IIi */ 346 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 347 /* Although insns using %y are deprecated, it is a clear win on current 348 ultrasparcs. */ 349 |MASK_DEPRECATED_V8_INSNS}, 350 /* TI ultrasparc III */ 351 /* ??? Check if %y issue still holds true in ultra3. */ 352 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, 353 { 0, 0, 0, 0 } 354 }; 355 const struct cpu_table *cpu; 356 const struct sparc_cpu_select *sel; 357 int fpu; 358 359#ifndef SPARC_BI_ARCH 360 /* Check for unsupported architecture size. */ 361 if (! TARGET_64BIT != DEFAULT_ARCH32_P) 362 error ("%s is not supported by this configuration", 363 DEFAULT_ARCH32_P ? "-m64" : "-m32"); 364#endif 365 366 /* We force all 64bit archs to use 128 bit long double */ 367 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) 368 { 369 error ("-mlong-double-64 not allowed with -m64"); 370 target_flags |= MASK_LONG_DOUBLE_128; 371 } 372 373 /* Code model selection. */ 374 sparc_cmodel = SPARC_DEFAULT_CMODEL; 375 376#ifdef SPARC_BI_ARCH 377 if (TARGET_ARCH32) 378 sparc_cmodel = CM_32; 379#endif 380 381 if (sparc_cmodel_string != NULL) 382 { 383 if (TARGET_ARCH64) 384 { 385 for (cmodel = &cmodels[0]; cmodel->name; cmodel++) 386 if (strcmp (sparc_cmodel_string, cmodel->name) == 0) 387 break; 388 if (cmodel->name == NULL) 389 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); 390 else 391 sparc_cmodel = cmodel->value; 392 } 393 else 394 error ("-mcmodel= is not supported on 32 bit systems"); 395 } 396 397 fpu = TARGET_FPU; /* save current -mfpu status */ 398 399 /* Set the default CPU. */ 400 for (def = &cpu_default[0]; def->name; ++def) 401 if (def->cpu == TARGET_CPU_DEFAULT) 402 break; 403 if (! def->name) 404 abort (); 405 sparc_select[0].string = def->name; 406 407 for (sel = &sparc_select[0]; sel->name; ++sel) 408 { 409 if (sel->string) 410 { 411 for (cpu = &cpu_table[0]; cpu->name; ++cpu) 412 if (! strcmp (sel->string, cpu->name)) 413 { 414 if (sel->set_tune_p) 415 sparc_cpu = cpu->processor; 416 417 if (sel->set_arch_p) 418 { 419 target_flags &= ~cpu->disable; 420 target_flags |= cpu->enable; 421 } 422 break; 423 } 424 425 if (! cpu->name) 426 error ("bad value (%s) for %s switch", sel->string, sel->name); 427 } 428 } 429 430 /* If -mfpu or -mno-fpu was explicitly used, don't override with 431 the processor default. Clear MASK_FPU_SET to avoid confusing 432 the reverse mapping from switch values to names. */ 433 if (TARGET_FPU_SET) 434 { 435 target_flags = (target_flags & ~MASK_FPU) | fpu; 436 target_flags &= ~MASK_FPU_SET; 437 } 438 439 /* Don't allow -mvis if FPU is disabled. */ 440 if (! TARGET_FPU) 441 target_flags &= ~MASK_VIS; 442 443 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions 444 are available. 445 -m64 also implies v9. */ 446 if (TARGET_VIS || TARGET_ARCH64) 447 { 448 target_flags |= MASK_V9; 449 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); 450 } 451 452 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ 453 if (TARGET_V9 && TARGET_ARCH32) 454 target_flags |= MASK_DEPRECATED_V8_INSNS; 455 456 /* V8PLUS requires V9, makes no sense in 64 bit mode. */ 457 if (! TARGET_V9 || TARGET_ARCH64) 458 target_flags &= ~MASK_V8PLUS; 459 460 /* Don't use stack biasing in 32 bit mode. */ 461 if (TARGET_ARCH32) 462 target_flags &= ~MASK_STACK_BIAS; 463 464 /* Supply a default value for align_functions. */ 465 if (align_functions == 0 466 && (sparc_cpu == PROCESSOR_ULTRASPARC 467 || sparc_cpu == PROCESSOR_ULTRASPARC3)) 468 align_functions = 32; 469 470 /* Validate PCC_STRUCT_RETURN. */ 471 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) 472 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); 473 474 /* Only use .uaxword when compiling for a 64-bit target. */ 475 if (!TARGET_ARCH64) 476 targetm.asm_out.unaligned_op.di = NULL; 477 478 /* Do various machine dependent initializations. */ 479 sparc_init_modes (); 480 481 /* Set up function hooks. */ 482 init_machine_status = sparc_init_machine_status; 483} 484 485/* Miscellaneous utilities. */ 486 487/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move 488 or branch on register contents instructions. */ 489 490int 491v9_regcmp_p (enum rtx_code code) 492{ 493 return (code == EQ || code == NE || code == GE || code == LT 494 || code == LE || code == GT); 495} 496 497 498/* Operand constraints. */ 499 500/* Return nonzero only if OP is a register of mode MODE, 501 or const0_rtx. */ 502 503int 504reg_or_0_operand (rtx op, enum machine_mode mode) 505{ 506 if (register_operand (op, mode)) 507 return 1; 508 if (op == const0_rtx) 509 return 1; 510 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE 511 && CONST_DOUBLE_HIGH (op) == 0 512 && CONST_DOUBLE_LOW (op) == 0) 513 return 1; 514 if (fp_zero_operand (op, mode)) 515 return 1; 516 return 0; 517} 518 519/* Return nonzero only if OP is const1_rtx. */ 520 521int 522const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 523{ 524 return op == const1_rtx; 525} 526 527/* Nonzero if OP is a floating point value with value 0.0. */ 528 529int 530fp_zero_operand (rtx op, enum machine_mode mode) 531{ 532 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT) 533 return 0; 534 return op == CONST0_RTX (mode); 535} 536 537/* Nonzero if OP is a register operand in floating point register. */ 538 539int 540fp_register_operand (rtx op, enum machine_mode mode) 541{ 542 if (! register_operand (op, mode)) 543 return 0; 544 if (GET_CODE (op) == SUBREG) 545 op = SUBREG_REG (op); 546 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op)); 547} 548 549/* Nonzero if OP is a floating point constant which can 550 be loaded into an integer register using a single 551 sethi instruction. */ 552 553int 554fp_sethi_p (rtx op) 555{ 556 if (GET_CODE (op) == CONST_DOUBLE) 557 { 558 REAL_VALUE_TYPE r; 559 long i; 560 561 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 562 if (REAL_VALUES_EQUAL (r, dconst0) && 563 ! REAL_VALUE_MINUS_ZERO (r)) 564 return 0; 565 REAL_VALUE_TO_TARGET_SINGLE (r, i); 566 if (SPARC_SETHI_P (i)) 567 return 1; 568 } 569 570 return 0; 571} 572 573/* Nonzero if OP is a floating point constant which can 574 be loaded into an integer register using a single 575 mov instruction. */ 576 577int 578fp_mov_p (rtx op) 579{ 580 if (GET_CODE (op) == CONST_DOUBLE) 581 { 582 REAL_VALUE_TYPE r; 583 long i; 584 585 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 586 if (REAL_VALUES_EQUAL (r, dconst0) && 587 ! REAL_VALUE_MINUS_ZERO (r)) 588 return 0; 589 REAL_VALUE_TO_TARGET_SINGLE (r, i); 590 if (SPARC_SIMM13_P (i)) 591 return 1; 592 } 593 594 return 0; 595} 596 597/* Nonzero if OP is a floating point constant which can 598 be loaded into an integer register using a high/losum 599 instruction sequence. */ 600 601int 602fp_high_losum_p (rtx op) 603{ 604 /* The constraints calling this should only be in 605 SFmode move insns, so any constant which cannot 606 be moved using a single insn will do. */ 607 if (GET_CODE (op) == CONST_DOUBLE) 608 { 609 REAL_VALUE_TYPE r; 610 long i; 611 612 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 613 if (REAL_VALUES_EQUAL (r, dconst0) && 614 ! REAL_VALUE_MINUS_ZERO (r)) 615 return 0; 616 REAL_VALUE_TO_TARGET_SINGLE (r, i); 617 if (! SPARC_SETHI_P (i) 618 && ! SPARC_SIMM13_P (i)) 619 return 1; 620 } 621 622 return 0; 623} 624 625/* Nonzero if OP is an integer register. */ 626 627int 628intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 629{ 630 return (register_operand (op, SImode) 631 || (TARGET_ARCH64 && register_operand (op, DImode))); 632} 633 634/* Nonzero if OP is a floating point condition code register. */ 635 636int 637fcc_reg_operand (rtx op, enum machine_mode mode) 638{ 639 /* This can happen when recog is called from combine. Op may be a MEM. 640 Fail instead of calling abort in this case. */ 641 if (GET_CODE (op) != REG) 642 return 0; 643 644 if (mode != VOIDmode && mode != GET_MODE (op)) 645 return 0; 646 if (mode == VOIDmode 647 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 648 return 0; 649 650#if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ 651 if (reg_renumber == 0) 652 return REGNO (op) >= FIRST_PSEUDO_REGISTER; 653 return REGNO_OK_FOR_CCFP_P (REGNO (op)); 654#else 655 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; 656#endif 657} 658 659/* Nonzero if OP is a floating point condition code fcc0 register. */ 660 661int 662fcc0_reg_operand (rtx op, enum machine_mode mode) 663{ 664 /* This can happen when recog is called from combine. Op may be a MEM. 665 Fail instead of calling abort in this case. */ 666 if (GET_CODE (op) != REG) 667 return 0; 668 669 if (mode != VOIDmode && mode != GET_MODE (op)) 670 return 0; 671 if (mode == VOIDmode 672 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 673 return 0; 674 675 return REGNO (op) == SPARC_FCC_REG; 676} 677 678/* Nonzero if OP is an integer or floating point condition code register. */ 679 680int 681icc_or_fcc_reg_operand (rtx op, enum machine_mode mode) 682{ 683 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) 684 { 685 if (mode != VOIDmode && mode != GET_MODE (op)) 686 return 0; 687 if (mode == VOIDmode 688 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) 689 return 0; 690 return 1; 691 } 692 693 return fcc_reg_operand (op, mode); 694} 695 696/* Nonzero if OP can appear as the dest of a RESTORE insn. */ 697int 698restore_operand (rtx op, enum machine_mode mode) 699{ 700 return (GET_CODE (op) == REG && GET_MODE (op) == mode 701 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); 702} 703 704/* Call insn on SPARC can take a PC-relative constant address, or any regular 705 memory address. */ 706 707int 708call_operand (rtx op, enum machine_mode mode) 709{ 710 if (GET_CODE (op) != MEM) 711 abort (); 712 op = XEXP (op, 0); 713 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); 714} 715 716int 717call_operand_address (rtx op, enum machine_mode mode) 718{ 719 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); 720} 721 722/* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode, 723 otherwise return 0. */ 724 725int 726tls_symbolic_operand (rtx op) 727{ 728 if (GET_CODE (op) != SYMBOL_REF) 729 return 0; 730 return SYMBOL_REF_TLS_MODEL (op); 731} 732 733int 734tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 735{ 736 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC; 737} 738 739int 740tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 741{ 742 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC; 743} 744 745int 746tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 747{ 748 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC; 749} 750 751int 752tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 753{ 754 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC; 755} 756 757/* Returns 1 if OP is either a symbol reference or a sum of a symbol 758 reference and a constant. */ 759 760int 761symbolic_operand (register rtx op, enum machine_mode mode) 762{ 763 enum machine_mode omode = GET_MODE (op); 764 765 if (omode != mode && omode != VOIDmode && mode != VOIDmode) 766 return 0; 767 768 switch (GET_CODE (op)) 769 { 770 case SYMBOL_REF: 771 return !SYMBOL_REF_TLS_MODEL (op); 772 773 case LABEL_REF: 774 return 1; 775 776 case CONST: 777 op = XEXP (op, 0); 778 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF 779 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0))) 780 || GET_CODE (XEXP (op, 0)) == LABEL_REF) 781 && GET_CODE (XEXP (op, 1)) == CONST_INT); 782 783 default: 784 return 0; 785 } 786} 787 788/* Return truth value of statement that OP is a symbolic memory 789 operand of mode MODE. */ 790 791int 792symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 793{ 794 if (GET_CODE (op) == SUBREG) 795 op = SUBREG_REG (op); 796 if (GET_CODE (op) != MEM) 797 return 0; 798 op = XEXP (op, 0); 799 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op)) 800 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH 801 || GET_CODE (op) == LABEL_REF); 802} 803 804/* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ 805 806int 807label_ref_operand (rtx op, enum machine_mode mode) 808{ 809 if (GET_CODE (op) != LABEL_REF) 810 return 0; 811 if (GET_MODE (op) != mode) 812 return 0; 813 return 1; 814} 815 816/* Return 1 if the operand is an argument used in generating pic references 817 in either the medium/low or medium/anywhere code models of sparc64. */ 818 819int 820sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 821{ 822 /* Check for (const (minus (symbol_ref:GOT) 823 (const (minus (label) (pc))))). */ 824 if (GET_CODE (op) != CONST) 825 return 0; 826 op = XEXP (op, 0); 827 if (GET_CODE (op) != MINUS) 828 return 0; 829 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) 830 return 0; 831 /* ??? Ensure symbol is GOT. */ 832 if (GET_CODE (XEXP (op, 1)) != CONST) 833 return 0; 834 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) 835 return 0; 836 return 1; 837} 838 839/* Return 1 if the operand is a data segment reference. This includes 840 the readonly data segment, or in other words anything but the text segment. 841 This is needed in the medium/anywhere code model on v9. These values 842 are accessed with EMBMEDANY_BASE_REG. */ 843 844int 845data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 846{ 847 switch (GET_CODE (op)) 848 { 849 case SYMBOL_REF : 850 return ! SYMBOL_REF_FUNCTION_P (op); 851 case PLUS : 852 /* Assume canonical format of symbol + constant. 853 Fall through. */ 854 case CONST : 855 return data_segment_operand (XEXP (op, 0), VOIDmode); 856 default : 857 return 0; 858 } 859} 860 861/* Return 1 if the operand is a text segment reference. 862 This is needed in the medium/anywhere code model on v9. */ 863 864int 865text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 866{ 867 switch (GET_CODE (op)) 868 { 869 case LABEL_REF : 870 return 1; 871 case SYMBOL_REF : 872 return SYMBOL_REF_FUNCTION_P (op); 873 case PLUS : 874 /* Assume canonical format of symbol + constant. 875 Fall through. */ 876 case CONST : 877 return text_segment_operand (XEXP (op, 0), VOIDmode); 878 default : 879 return 0; 880 } 881} 882 883/* Return 1 if the operand is either a register or a memory operand that is 884 not symbolic. */ 885 886int 887reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode) 888{ 889 if (register_operand (op, mode)) 890 return 1; 891 892 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) 893 return 1; 894 895 return 0; 896} 897 898int 899splittable_symbolic_memory_operand (rtx op, 900 enum machine_mode mode ATTRIBUTE_UNUSED) 901{ 902 if (GET_CODE (op) != MEM) 903 return 0; 904 if (! symbolic_operand (XEXP (op, 0), Pmode)) 905 return 0; 906 return 1; 907} 908 909int 910splittable_immediate_memory_operand (rtx op, 911 enum machine_mode mode ATTRIBUTE_UNUSED) 912{ 913 if (GET_CODE (op) != MEM) 914 return 0; 915 if (! immediate_operand (XEXP (op, 0), Pmode)) 916 return 0; 917 return 1; 918} 919 920/* Return truth value of whether OP is EQ or NE. */ 921 922int 923eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 924{ 925 return (GET_CODE (op) == EQ || GET_CODE (op) == NE); 926} 927 928/* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, 929 or LTU for non-floating-point. We handle those specially. */ 930 931int 932normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 933{ 934 enum rtx_code code = GET_CODE (op); 935 936 if (GET_RTX_CLASS (code) != '<') 937 return 0; 938 939 if (GET_MODE (XEXP (op, 0)) == CCFPmode 940 || GET_MODE (XEXP (op, 0)) == CCFPEmode) 941 return 1; 942 943 return (code != NE && code != EQ && code != GEU && code != LTU); 944} 945 946/* Return 1 if this is a comparison operator. This allows the use of 947 MATCH_OPERATOR to recognize all the branch insns. */ 948 949int 950noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 951{ 952 enum rtx_code code = GET_CODE (op); 953 954 if (GET_RTX_CLASS (code) != '<') 955 return 0; 956 957 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode 958 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 959 /* These are the only branches which work with CC_NOOVmode. */ 960 return (code == EQ || code == NE || code == GE || code == LT); 961 return 1; 962} 963 964/* Return 1 if this is a 64-bit comparison operator. This allows the use of 965 MATCH_OPERATOR to recognize all the branch insns. */ 966 967int 968noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 969{ 970 enum rtx_code code = GET_CODE (op); 971 972 if (! TARGET_V9) 973 return 0; 974 975 if (GET_RTX_CLASS (code) != '<') 976 return 0; 977 978 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 979 /* These are the only branches which work with CCX_NOOVmode. */ 980 return (code == EQ || code == NE || code == GE || code == LT); 981 return (GET_MODE (XEXP (op, 0)) == CCXmode); 982} 983 984/* Nonzero if OP is a comparison operator suitable for use in v9 985 conditional move or branch on register contents instructions. */ 986 987int 988v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 989{ 990 enum rtx_code code = GET_CODE (op); 991 992 if (GET_RTX_CLASS (code) != '<') 993 return 0; 994 995 return v9_regcmp_p (code); 996} 997 998/* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ 999 1000int 1001extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1002{ 1003 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; 1004} 1005 1006/* Return nonzero if OP is an operator of mode MODE which can set 1007 the condition codes explicitly. We do not include PLUS and MINUS 1008 because these require CC_NOOVmode, which we handle explicitly. */ 1009 1010int 1011cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1012{ 1013 if (GET_CODE (op) == AND 1014 || GET_CODE (op) == IOR 1015 || GET_CODE (op) == XOR) 1016 return 1; 1017 1018 return 0; 1019} 1020 1021/* Return nonzero if OP is an operator of mode MODE which can bitwise 1022 complement its second operand and set the condition codes explicitly. */ 1023 1024int 1025cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1026{ 1027 /* XOR is not here because combine canonicalizes (xor (not ...) ...) 1028 and (xor ... (not ...)) to (not (xor ...)). */ 1029 return (GET_CODE (op) == AND 1030 || GET_CODE (op) == IOR); 1031} 1032 1033/* Return true if OP is a register, or is a CONST_INT that can fit in a 1034 signed 13 bit immediate field. This is an acceptable SImode operand for 1035 most 3 address instructions. */ 1036 1037int 1038arith_operand (rtx op, enum machine_mode mode) 1039{ 1040 if (register_operand (op, mode)) 1041 return 1; 1042 if (GET_CODE (op) != CONST_INT) 1043 return 0; 1044 return SMALL_INT32 (op); 1045} 1046 1047/* Return true if OP is a constant 4096 */ 1048 1049int 1050arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1051{ 1052 if (GET_CODE (op) != CONST_INT) 1053 return 0; 1054 else 1055 return INTVAL (op) == 4096; 1056} 1057 1058/* Return true if OP is suitable as second operand for add/sub */ 1059 1060int 1061arith_add_operand (rtx op, enum machine_mode mode) 1062{ 1063 return arith_operand (op, mode) || arith_4096_operand (op, mode); 1064} 1065 1066/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the 1067 immediate field of OR and XOR instructions. Used for 64-bit 1068 constant formation patterns. */ 1069int 1070const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1071{ 1072 return ((GET_CODE (op) == CONST_INT 1073 && SPARC_SIMM13_P (INTVAL (op))) 1074#if HOST_BITS_PER_WIDE_INT != 64 1075 || (GET_CODE (op) == CONST_DOUBLE 1076 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) 1077 && (CONST_DOUBLE_HIGH (op) == 1078 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? 1079 (HOST_WIDE_INT)-1 : 0))) 1080#endif 1081 ); 1082} 1083 1084/* The same, but only for sethi instructions. */ 1085int 1086const64_high_operand (rtx op, enum machine_mode mode) 1087{ 1088 return ((GET_CODE (op) == CONST_INT 1089 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0 1090 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) 1091 ) 1092 || (GET_CODE (op) == CONST_DOUBLE 1093 && CONST_DOUBLE_HIGH (op) == 0 1094 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0 1095 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); 1096} 1097 1098/* Return true if OP is a register, or is a CONST_INT that can fit in a 1099 signed 11 bit immediate field. This is an acceptable SImode operand for 1100 the movcc instructions. */ 1101 1102int 1103arith11_operand (rtx op, enum machine_mode mode) 1104{ 1105 return (register_operand (op, mode) 1106 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); 1107} 1108 1109/* Return true if OP is a register, or is a CONST_INT that can fit in a 1110 signed 10 bit immediate field. This is an acceptable SImode operand for 1111 the movrcc instructions. */ 1112 1113int 1114arith10_operand (rtx op, enum machine_mode mode) 1115{ 1116 return (register_operand (op, mode) 1117 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); 1118} 1119 1120/* Return true if OP is a register, is a CONST_INT that fits in a 13 bit 1121 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit 1122 immediate field. 1123 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1124 can fit in a 13 bit immediate field. This is an acceptable DImode operand 1125 for most 3 address instructions. */ 1126 1127int 1128arith_double_operand (rtx op, enum machine_mode mode) 1129{ 1130 return (register_operand (op, mode) 1131 || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) 1132 || (! TARGET_ARCH64 1133 && GET_CODE (op) == CONST_DOUBLE 1134 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 1135 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) 1136 || (TARGET_ARCH64 1137 && GET_CODE (op) == CONST_DOUBLE 1138 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 1139 && ((CONST_DOUBLE_HIGH (op) == -1 1140 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) 1141 || (CONST_DOUBLE_HIGH (op) == 0 1142 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); 1143} 1144 1145/* Return true if OP is a constant 4096 for DImode on ARCH64 */ 1146 1147int 1148arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1149{ 1150 return (TARGET_ARCH64 && 1151 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || 1152 (GET_CODE (op) == CONST_DOUBLE && 1153 CONST_DOUBLE_LOW (op) == 4096 && 1154 CONST_DOUBLE_HIGH (op) == 0))); 1155} 1156 1157/* Return true if OP is suitable as second operand for add/sub in DImode */ 1158 1159int 1160arith_double_add_operand (rtx op, enum machine_mode mode) 1161{ 1162 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); 1163} 1164 1165/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1166 can fit in an 11 bit immediate field. This is an acceptable DImode 1167 operand for the movcc instructions. */ 1168/* ??? Replace with arith11_operand? */ 1169 1170int 1171arith11_double_operand (rtx op, enum machine_mode mode) 1172{ 1173 return (register_operand (op, mode) 1174 || (GET_CODE (op) == CONST_DOUBLE 1175 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1176 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 1177 && ((CONST_DOUBLE_HIGH (op) == -1 1178 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) 1179 || (CONST_DOUBLE_HIGH (op) == 0 1180 && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) 1181 || (GET_CODE (op) == CONST_INT 1182 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1183 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); 1184} 1185 1186/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1187 can fit in an 10 bit immediate field. This is an acceptable DImode 1188 operand for the movrcc instructions. */ 1189/* ??? Replace with arith10_operand? */ 1190 1191int 1192arith10_double_operand (rtx op, enum machine_mode mode) 1193{ 1194 return (register_operand (op, mode) 1195 || (GET_CODE (op) == CONST_DOUBLE 1196 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1197 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 1198 && ((CONST_DOUBLE_HIGH (op) == -1 1199 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) 1200 || (CONST_DOUBLE_HIGH (op) == 0 1201 && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) 1202 || (GET_CODE (op) == CONST_INT 1203 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1204 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); 1205} 1206 1207/* Return truth value of whether OP is an integer which fits the 1208 range constraining immediate operands in most three-address insns, 1209 which have a 13 bit immediate field. */ 1210 1211int 1212small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1213{ 1214 return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); 1215} 1216 1217int 1218small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1219{ 1220 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) 1221 || (GET_CODE (op) == CONST_DOUBLE 1222 && CONST_DOUBLE_HIGH (op) == 0 1223 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); 1224} 1225 1226/* Recognize operand values for the umul instruction. That instruction sign 1227 extends immediate values just like all other sparc instructions, but 1228 interprets the extended result as an unsigned number. */ 1229 1230int 1231uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1232{ 1233#if HOST_BITS_PER_WIDE_INT > 32 1234 /* All allowed constants will fit a CONST_INT. */ 1235 return (GET_CODE (op) == CONST_INT 1236 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) 1237 || (INTVAL (op) >= 0xFFFFF000 1238 && INTVAL (op) <= 0xFFFFFFFF))); 1239#else 1240 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) 1241 || (GET_CODE (op) == CONST_DOUBLE 1242 && CONST_DOUBLE_HIGH (op) == 0 1243 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); 1244#endif 1245} 1246 1247int 1248uns_arith_operand (rtx op, enum machine_mode mode) 1249{ 1250 return register_operand (op, mode) || uns_small_int (op, mode); 1251} 1252 1253/* Return truth value of statement that OP is a call-clobbered register. */ 1254int 1255clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 1256{ 1257 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); 1258} 1259 1260/* Return 1 if OP is a valid operand for the source of a move insn. */ 1261 1262int 1263input_operand (rtx op, enum machine_mode mode) 1264{ 1265 /* If both modes are non-void they must be the same. */ 1266 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) 1267 return 0; 1268 1269 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */ 1270 if (GET_CODE (op) == CONSTANT_P_RTX) 1271 return 1; 1272 1273 /* Allow any one instruction integer constant, and all CONST_INT 1274 variants when we are working in DImode and !arch64. */ 1275 if (GET_MODE_CLASS (mode) == MODE_INT 1276 && ((GET_CODE (op) == CONST_INT 1277 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) 1278 || SPARC_SIMM13_P (INTVAL (op)) 1279 || (mode == DImode 1280 && ! TARGET_ARCH64))) 1281 || (TARGET_ARCH64 1282 && GET_CODE (op) == CONST_DOUBLE 1283 && ((CONST_DOUBLE_HIGH (op) == 0 1284 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) 1285 || 1286#if HOST_BITS_PER_WIDE_INT == 64 1287 (CONST_DOUBLE_HIGH (op) == 0 1288 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) 1289#else 1290 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) 1291 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 1292 && CONST_DOUBLE_HIGH (op) == 0) 1293 || (CONST_DOUBLE_HIGH (op) == -1 1294 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0)) 1295#endif 1296 )))) 1297 return 1; 1298 1299 /* If !arch64 and this is a DImode const, allow it so that 1300 the splits can be generated. */ 1301 if (! TARGET_ARCH64 1302 && mode == DImode 1303 && GET_CODE (op) == CONST_DOUBLE) 1304 return 1; 1305 1306 if (register_operand (op, mode)) 1307 return 1; 1308 1309 if (GET_MODE_CLASS (mode) == MODE_FLOAT 1310 && GET_CODE (op) == CONST_DOUBLE) 1311 return 1; 1312 1313 /* If this is a SUBREG, look inside so that we handle 1314 paradoxical ones. */ 1315 if (GET_CODE (op) == SUBREG) 1316 op = SUBREG_REG (op); 1317 1318 /* Check for valid MEM forms. */ 1319 if (GET_CODE (op) == MEM) 1320 return memory_address_p (mode, XEXP (op, 0)); 1321 1322 return 0; 1323} 1324 1325/* Return 1 if OP is valid for the lhs of a compare insn. */ 1326 1327int 1328compare_operand (rtx op, enum machine_mode mode) 1329{ 1330 if (GET_CODE (op) == ZERO_EXTRACT) 1331 return (register_operand (XEXP (op, 0), mode) 1332 && small_int_or_double (XEXP (op, 1), mode) 1333 && small_int_or_double (XEXP (op, 2), mode) 1334 /* This matches cmp_zero_extract. */ 1335 && ((mode == SImode 1336 && ((GET_CODE (XEXP (op, 2)) == CONST_INT 1337 && INTVAL (XEXP (op, 2)) > 19) 1338 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE 1339 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19))) 1340 /* This matches cmp_zero_extract_sp64. */ 1341 || (mode == DImode 1342 && TARGET_ARCH64 1343 && ((GET_CODE (XEXP (op, 2)) == CONST_INT 1344 && INTVAL (XEXP (op, 2)) > 51) 1345 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE 1346 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51))))); 1347 else 1348 return register_operand (op, mode); 1349} 1350 1351 1352/* We know it can't be done in one insn when we get here, 1353 the movsi expander guarantees this. */ 1354void 1355sparc_emit_set_const32 (rtx op0, rtx op1) 1356{ 1357 enum machine_mode mode = GET_MODE (op0); 1358 rtx temp; 1359 1360 if (GET_CODE (op1) == CONST_INT) 1361 { 1362 HOST_WIDE_INT value = INTVAL (op1); 1363 1364 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode)) 1365 || SPARC_SIMM13_P (value)) 1366 abort (); 1367 } 1368 1369 /* Full 2-insn decomposition is needed. */ 1370 if (reload_in_progress || reload_completed) 1371 temp = op0; 1372 else 1373 temp = gen_reg_rtx (mode); 1374 1375 if (GET_CODE (op1) == CONST_INT) 1376 { 1377 /* Emit them as real moves instead of a HIGH/LO_SUM, 1378 this way CSE can see everything and reuse intermediate 1379 values if it wants. */ 1380 if (TARGET_ARCH64 1381 && HOST_BITS_PER_WIDE_INT != 64 1382 && (INTVAL (op1) & 0x80000000) != 0) 1383 emit_insn (gen_rtx_SET 1384 (VOIDmode, temp, 1385 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff, 1386 0, DImode))); 1387 else 1388 emit_insn (gen_rtx_SET (VOIDmode, temp, 1389 GEN_INT (INTVAL (op1) 1390 & ~(HOST_WIDE_INT)0x3ff))); 1391 1392 emit_insn (gen_rtx_SET (VOIDmode, 1393 op0, 1394 gen_rtx_IOR (mode, temp, 1395 GEN_INT (INTVAL (op1) & 0x3ff)))); 1396 } 1397 else 1398 { 1399 /* A symbol, emit in the traditional way. */ 1400 emit_insn (gen_rtx_SET (VOIDmode, temp, 1401 gen_rtx_HIGH (mode, op1))); 1402 emit_insn (gen_rtx_SET (VOIDmode, 1403 op0, gen_rtx_LO_SUM (mode, temp, op1))); 1404 1405 } 1406} 1407 1408 1409/* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register. 1410 If TEMP is non-zero, we are forbidden to use any other scratch 1411 registers. Otherwise, we are allowed to generate them as needed. 1412 1413 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY 1414 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */ 1415void 1416sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp) 1417{ 1418 rtx temp1, temp2, temp3, temp4, temp5; 1419 rtx ti_temp = 0; 1420 1421 if (temp && GET_MODE (temp) == TImode) 1422 { 1423 ti_temp = temp; 1424 temp = gen_rtx_REG (DImode, REGNO (temp)); 1425 } 1426 1427 /* SPARC-V9 code-model support. */ 1428 switch (sparc_cmodel) 1429 { 1430 case CM_MEDLOW: 1431 /* The range spanned by all instructions in the object is less 1432 than 2^31 bytes (2GB) and the distance from any instruction 1433 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1434 than 2^31 bytes (2GB). 1435 1436 The executable must be in the low 4TB of the virtual address 1437 space. 1438 1439 sethi %hi(symbol), %temp1 1440 or %temp1, %lo(symbol), %reg */ 1441 if (temp) 1442 temp1 = temp; /* op0 is allowed. */ 1443 else 1444 temp1 = gen_reg_rtx (DImode); 1445 1446 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); 1447 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); 1448 break; 1449 1450 case CM_MEDMID: 1451 /* The range spanned by all instructions in the object is less 1452 than 2^31 bytes (2GB) and the distance from any instruction 1453 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1454 than 2^31 bytes (2GB). 1455 1456 The executable must be in the low 16TB of the virtual address 1457 space. 1458 1459 sethi %h44(symbol), %temp1 1460 or %temp1, %m44(symbol), %temp2 1461 sllx %temp2, 12, %temp3 1462 or %temp3, %l44(symbol), %reg */ 1463 if (temp) 1464 { 1465 temp1 = op0; 1466 temp2 = op0; 1467 temp3 = temp; /* op0 is allowed. */ 1468 } 1469 else 1470 { 1471 temp1 = gen_reg_rtx (DImode); 1472 temp2 = gen_reg_rtx (DImode); 1473 temp3 = gen_reg_rtx (DImode); 1474 } 1475 1476 emit_insn (gen_seth44 (temp1, op1)); 1477 emit_insn (gen_setm44 (temp2, temp1, op1)); 1478 emit_insn (gen_rtx_SET (VOIDmode, temp3, 1479 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12)))); 1480 emit_insn (gen_setl44 (op0, temp3, op1)); 1481 break; 1482 1483 case CM_MEDANY: 1484 /* The range spanned by all instructions in the object is less 1485 than 2^31 bytes (2GB) and the distance from any instruction 1486 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1487 than 2^31 bytes (2GB). 1488 1489 The executable can be placed anywhere in the virtual address 1490 space. 1491 1492 sethi %hh(symbol), %temp1 1493 sethi %lm(symbol), %temp2 1494 or %temp1, %hm(symbol), %temp3 1495 sllx %temp3, 32, %temp4 1496 or %temp4, %temp2, %temp5 1497 or %temp5, %lo(symbol), %reg */ 1498 if (temp) 1499 { 1500 /* It is possible that one of the registers we got for operands[2] 1501 might coincide with that of operands[0] (which is why we made 1502 it TImode). Pick the other one to use as our scratch. */ 1503 if (rtx_equal_p (temp, op0)) 1504 { 1505 if (ti_temp) 1506 temp = gen_rtx_REG (DImode, REGNO (temp) + 1); 1507 else 1508 abort(); 1509 } 1510 temp1 = op0; 1511 temp2 = temp; /* op0 is _not_ allowed, see above. */ 1512 temp3 = op0; 1513 temp4 = op0; 1514 temp5 = op0; 1515 } 1516 else 1517 { 1518 temp1 = gen_reg_rtx (DImode); 1519 temp2 = gen_reg_rtx (DImode); 1520 temp3 = gen_reg_rtx (DImode); 1521 temp4 = gen_reg_rtx (DImode); 1522 temp5 = gen_reg_rtx (DImode); 1523 } 1524 1525 emit_insn (gen_sethh (temp1, op1)); 1526 emit_insn (gen_setlm (temp2, op1)); 1527 emit_insn (gen_sethm (temp3, temp1, op1)); 1528 emit_insn (gen_rtx_SET (VOIDmode, temp4, 1529 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32)))); 1530 emit_insn (gen_rtx_SET (VOIDmode, temp5, 1531 gen_rtx_PLUS (DImode, temp4, temp2))); 1532 emit_insn (gen_setlo (op0, temp5, op1)); 1533 break; 1534 1535 case CM_EMBMEDANY: 1536 /* Old old old backwards compatibility kruft here. 1537 Essentially it is MEDLOW with a fixed 64-bit 1538 virtual base added to all data segment addresses. 1539 Text-segment stuff is computed like MEDANY, we can't 1540 reuse the code above because the relocation knobs 1541 look different. 1542 1543 Data segment: sethi %hi(symbol), %temp1 1544 add %temp1, EMBMEDANY_BASE_REG, %temp2 1545 or %temp2, %lo(symbol), %reg */ 1546 if (data_segment_operand (op1, GET_MODE (op1))) 1547 { 1548 if (temp) 1549 { 1550 temp1 = temp; /* op0 is allowed. */ 1551 temp2 = op0; 1552 } 1553 else 1554 { 1555 temp1 = gen_reg_rtx (DImode); 1556 temp2 = gen_reg_rtx (DImode); 1557 } 1558 1559 emit_insn (gen_embmedany_sethi (temp1, op1)); 1560 emit_insn (gen_embmedany_brsum (temp2, temp1)); 1561 emit_insn (gen_embmedany_losum (op0, temp2, op1)); 1562 } 1563 1564 /* Text segment: sethi %uhi(symbol), %temp1 1565 sethi %hi(symbol), %temp2 1566 or %temp1, %ulo(symbol), %temp3 1567 sllx %temp3, 32, %temp4 1568 or %temp4, %temp2, %temp5 1569 or %temp5, %lo(symbol), %reg */ 1570 else 1571 { 1572 if (temp) 1573 { 1574 /* It is possible that one of the registers we got for operands[2] 1575 might coincide with that of operands[0] (which is why we made 1576 it TImode). Pick the other one to use as our scratch. */ 1577 if (rtx_equal_p (temp, op0)) 1578 { 1579 if (ti_temp) 1580 temp = gen_rtx_REG (DImode, REGNO (temp) + 1); 1581 else 1582 abort(); 1583 } 1584 temp1 = op0; 1585 temp2 = temp; /* op0 is _not_ allowed, see above. */ 1586 temp3 = op0; 1587 temp4 = op0; 1588 temp5 = op0; 1589 } 1590 else 1591 { 1592 temp1 = gen_reg_rtx (DImode); 1593 temp2 = gen_reg_rtx (DImode); 1594 temp3 = gen_reg_rtx (DImode); 1595 temp4 = gen_reg_rtx (DImode); 1596 temp5 = gen_reg_rtx (DImode); 1597 } 1598 1599 emit_insn (gen_embmedany_textuhi (temp1, op1)); 1600 emit_insn (gen_embmedany_texthi (temp2, op1)); 1601 emit_insn (gen_embmedany_textulo (temp3, temp1, op1)); 1602 emit_insn (gen_rtx_SET (VOIDmode, temp4, 1603 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32)))); 1604 emit_insn (gen_rtx_SET (VOIDmode, temp5, 1605 gen_rtx_PLUS (DImode, temp4, temp2))); 1606 emit_insn (gen_embmedany_textlo (op0, temp5, op1)); 1607 } 1608 break; 1609 1610 default: 1611 abort(); 1612 } 1613} 1614 1615/* These avoid problems when cross compiling. If we do not 1616 go through all this hair then the optimizer will see 1617 invalid REG_EQUAL notes or in some cases none at all. */ 1618static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT); 1619static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT); 1620static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT); 1621static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT); 1622 1623#if HOST_BITS_PER_WIDE_INT == 64 1624#define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff) 1625#define GEN_INT64(__x) GEN_INT (__x) 1626#else 1627#define GEN_HIGHINT64(__x) \ 1628 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode) 1629#define GEN_INT64(__x) \ 1630 immed_double_const ((__x) & 0xffffffff, \ 1631 ((__x) & 0x80000000 ? -1 : 0), DImode) 1632#endif 1633 1634/* The optimizer is not to assume anything about exactly 1635 which bits are set for a HIGH, they are unspecified. 1636 Unfortunately this leads to many missed optimizations 1637 during CSE. We mask out the non-HIGH bits, and matches 1638 a plain movdi, to alleviate this problem. */ 1639static void 1640sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val) 1641{ 1642 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); 1643} 1644 1645static rtx 1646gen_safe_SET64 (rtx dest, HOST_WIDE_INT val) 1647{ 1648 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); 1649} 1650 1651static rtx 1652gen_safe_OR64 (rtx src, HOST_WIDE_INT val) 1653{ 1654 return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); 1655} 1656 1657static rtx 1658gen_safe_XOR64 (rtx src, HOST_WIDE_INT val) 1659{ 1660 return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); 1661} 1662 1663/* Worker routines for 64-bit constant formation on arch64. 1664 One of the key things to be doing in these emissions is 1665 to create as many temp REGs as possible. This makes it 1666 possible for half-built constants to be used later when 1667 such values are similar to something required later on. 1668 Without doing this, the optimizer cannot see such 1669 opportunities. */ 1670 1671static void sparc_emit_set_const64_quick1 (rtx, rtx, 1672 unsigned HOST_WIDE_INT, int); 1673 1674static void 1675sparc_emit_set_const64_quick1 (rtx op0, rtx temp, 1676 unsigned HOST_WIDE_INT low_bits, int is_neg) 1677{ 1678 unsigned HOST_WIDE_INT high_bits; 1679 1680 if (is_neg) 1681 high_bits = (~low_bits) & 0xffffffff; 1682 else 1683 high_bits = low_bits; 1684 1685 sparc_emit_set_safe_HIGH64 (temp, high_bits); 1686 if (!is_neg) 1687 { 1688 emit_insn (gen_rtx_SET (VOIDmode, op0, 1689 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1690 } 1691 else 1692 { 1693 /* If we are XOR'ing with -1, then we should emit a one's complement 1694 instead. This way the combiner will notice logical operations 1695 such as ANDN later on and substitute. */ 1696 if ((low_bits & 0x3ff) == 0x3ff) 1697 { 1698 emit_insn (gen_rtx_SET (VOIDmode, op0, 1699 gen_rtx_NOT (DImode, temp))); 1700 } 1701 else 1702 { 1703 emit_insn (gen_rtx_SET (VOIDmode, op0, 1704 gen_safe_XOR64 (temp, 1705 (-(HOST_WIDE_INT)0x400 1706 | (low_bits & 0x3ff))))); 1707 } 1708 } 1709} 1710 1711static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT, 1712 unsigned HOST_WIDE_INT, int); 1713 1714static void 1715sparc_emit_set_const64_quick2 (rtx op0, rtx temp, 1716 unsigned HOST_WIDE_INT high_bits, 1717 unsigned HOST_WIDE_INT low_immediate, 1718 int shift_count) 1719{ 1720 rtx temp2 = op0; 1721 1722 if ((high_bits & 0xfffffc00) != 0) 1723 { 1724 sparc_emit_set_safe_HIGH64 (temp, high_bits); 1725 if ((high_bits & ~0xfffffc00) != 0) 1726 emit_insn (gen_rtx_SET (VOIDmode, op0, 1727 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1728 else 1729 temp2 = temp; 1730 } 1731 else 1732 { 1733 emit_insn (gen_safe_SET64 (temp, high_bits)); 1734 temp2 = temp; 1735 } 1736 1737 /* Now shift it up into place. */ 1738 emit_insn (gen_rtx_SET (VOIDmode, op0, 1739 gen_rtx_ASHIFT (DImode, temp2, 1740 GEN_INT (shift_count)))); 1741 1742 /* If there is a low immediate part piece, finish up by 1743 putting that in as well. */ 1744 if (low_immediate != 0) 1745 emit_insn (gen_rtx_SET (VOIDmode, op0, 1746 gen_safe_OR64 (op0, low_immediate))); 1747} 1748 1749static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT, 1750 unsigned HOST_WIDE_INT); 1751 1752/* Full 64-bit constant decomposition. Even though this is the 1753 'worst' case, we still optimize a few things away. */ 1754static void 1755sparc_emit_set_const64_longway (rtx op0, rtx temp, 1756 unsigned HOST_WIDE_INT high_bits, 1757 unsigned HOST_WIDE_INT low_bits) 1758{ 1759 rtx sub_temp; 1760 1761 if (reload_in_progress || reload_completed) 1762 sub_temp = op0; 1763 else 1764 sub_temp = gen_reg_rtx (DImode); 1765 1766 if ((high_bits & 0xfffffc00) != 0) 1767 { 1768 sparc_emit_set_safe_HIGH64 (temp, high_bits); 1769 if ((high_bits & ~0xfffffc00) != 0) 1770 emit_insn (gen_rtx_SET (VOIDmode, 1771 sub_temp, 1772 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1773 else 1774 sub_temp = temp; 1775 } 1776 else 1777 { 1778 emit_insn (gen_safe_SET64 (temp, high_bits)); 1779 sub_temp = temp; 1780 } 1781 1782 if (!reload_in_progress && !reload_completed) 1783 { 1784 rtx temp2 = gen_reg_rtx (DImode); 1785 rtx temp3 = gen_reg_rtx (DImode); 1786 rtx temp4 = gen_reg_rtx (DImode); 1787 1788 emit_insn (gen_rtx_SET (VOIDmode, temp4, 1789 gen_rtx_ASHIFT (DImode, sub_temp, 1790 GEN_INT (32)))); 1791 1792 sparc_emit_set_safe_HIGH64 (temp2, low_bits); 1793 if ((low_bits & ~0xfffffc00) != 0) 1794 { 1795 emit_insn (gen_rtx_SET (VOIDmode, temp3, 1796 gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); 1797 emit_insn (gen_rtx_SET (VOIDmode, op0, 1798 gen_rtx_PLUS (DImode, temp4, temp3))); 1799 } 1800 else 1801 { 1802 emit_insn (gen_rtx_SET (VOIDmode, op0, 1803 gen_rtx_PLUS (DImode, temp4, temp2))); 1804 } 1805 } 1806 else 1807 { 1808 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); 1809 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); 1810 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); 1811 int to_shift = 12; 1812 1813 /* We are in the middle of reload, so this is really 1814 painful. However we do still make an attempt to 1815 avoid emitting truly stupid code. */ 1816 if (low1 != const0_rtx) 1817 { 1818 emit_insn (gen_rtx_SET (VOIDmode, op0, 1819 gen_rtx_ASHIFT (DImode, sub_temp, 1820 GEN_INT (to_shift)))); 1821 emit_insn (gen_rtx_SET (VOIDmode, op0, 1822 gen_rtx_IOR (DImode, op0, low1))); 1823 sub_temp = op0; 1824 to_shift = 12; 1825 } 1826 else 1827 { 1828 to_shift += 12; 1829 } 1830 if (low2 != const0_rtx) 1831 { 1832 emit_insn (gen_rtx_SET (VOIDmode, op0, 1833 gen_rtx_ASHIFT (DImode, sub_temp, 1834 GEN_INT (to_shift)))); 1835 emit_insn (gen_rtx_SET (VOIDmode, op0, 1836 gen_rtx_IOR (DImode, op0, low2))); 1837 sub_temp = op0; 1838 to_shift = 8; 1839 } 1840 else 1841 { 1842 to_shift += 8; 1843 } 1844 emit_insn (gen_rtx_SET (VOIDmode, op0, 1845 gen_rtx_ASHIFT (DImode, sub_temp, 1846 GEN_INT (to_shift)))); 1847 if (low3 != const0_rtx) 1848 emit_insn (gen_rtx_SET (VOIDmode, op0, 1849 gen_rtx_IOR (DImode, op0, low3))); 1850 /* phew... */ 1851 } 1852} 1853 1854/* Analyze a 64-bit constant for certain properties. */ 1855static void analyze_64bit_constant (unsigned HOST_WIDE_INT, 1856 unsigned HOST_WIDE_INT, 1857 int *, int *, int *); 1858 1859static void 1860analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits, 1861 unsigned HOST_WIDE_INT low_bits, 1862 int *hbsp, int *lbsp, int *abbasp) 1863{ 1864 int lowest_bit_set, highest_bit_set, all_bits_between_are_set; 1865 int i; 1866 1867 lowest_bit_set = highest_bit_set = -1; 1868 i = 0; 1869 do 1870 { 1871 if ((lowest_bit_set == -1) 1872 && ((low_bits >> i) & 1)) 1873 lowest_bit_set = i; 1874 if ((highest_bit_set == -1) 1875 && ((high_bits >> (32 - i - 1)) & 1)) 1876 highest_bit_set = (64 - i - 1); 1877 } 1878 while (++i < 32 1879 && ((highest_bit_set == -1) 1880 || (lowest_bit_set == -1))); 1881 if (i == 32) 1882 { 1883 i = 0; 1884 do 1885 { 1886 if ((lowest_bit_set == -1) 1887 && ((high_bits >> i) & 1)) 1888 lowest_bit_set = i + 32; 1889 if ((highest_bit_set == -1) 1890 && ((low_bits >> (32 - i - 1)) & 1)) 1891 highest_bit_set = 32 - i - 1; 1892 } 1893 while (++i < 32 1894 && ((highest_bit_set == -1) 1895 || (lowest_bit_set == -1))); 1896 } 1897 /* If there are no bits set this should have gone out 1898 as one instruction! */ 1899 if (lowest_bit_set == -1 1900 || highest_bit_set == -1) 1901 abort (); 1902 all_bits_between_are_set = 1; 1903 for (i = lowest_bit_set; i <= highest_bit_set; i++) 1904 { 1905 if (i < 32) 1906 { 1907 if ((low_bits & (1 << i)) != 0) 1908 continue; 1909 } 1910 else 1911 { 1912 if ((high_bits & (1 << (i - 32))) != 0) 1913 continue; 1914 } 1915 all_bits_between_are_set = 0; 1916 break; 1917 } 1918 *hbsp = highest_bit_set; 1919 *lbsp = lowest_bit_set; 1920 *abbasp = all_bits_between_are_set; 1921} 1922 1923static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT); 1924 1925static int 1926const64_is_2insns (unsigned HOST_WIDE_INT high_bits, 1927 unsigned HOST_WIDE_INT low_bits) 1928{ 1929 int highest_bit_set, lowest_bit_set, all_bits_between_are_set; 1930 1931 if (high_bits == 0 1932 || high_bits == 0xffffffff) 1933 return 1; 1934 1935 analyze_64bit_constant (high_bits, low_bits, 1936 &highest_bit_set, &lowest_bit_set, 1937 &all_bits_between_are_set); 1938 1939 if ((highest_bit_set == 63 1940 || lowest_bit_set == 0) 1941 && all_bits_between_are_set != 0) 1942 return 1; 1943 1944 if ((highest_bit_set - lowest_bit_set) < 21) 1945 return 1; 1946 1947 return 0; 1948} 1949 1950static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT, 1951 unsigned HOST_WIDE_INT, 1952 int, int); 1953 1954static unsigned HOST_WIDE_INT 1955create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits, 1956 unsigned HOST_WIDE_INT low_bits, 1957 int lowest_bit_set, int shift) 1958{ 1959 HOST_WIDE_INT hi, lo; 1960 1961 if (lowest_bit_set < 32) 1962 { 1963 lo = (low_bits >> lowest_bit_set) << shift; 1964 hi = ((high_bits << (32 - lowest_bit_set)) << shift); 1965 } 1966 else 1967 { 1968 lo = 0; 1969 hi = ((high_bits >> (lowest_bit_set - 32)) << shift); 1970 } 1971 if (hi & lo) 1972 abort (); 1973 return (hi | lo); 1974} 1975 1976/* Here we are sure to be arch64 and this is an integer constant 1977 being loaded into a register. Emit the most efficient 1978 insn sequence possible. Detection of all the 1-insn cases 1979 has been done already. */ 1980void 1981sparc_emit_set_const64 (rtx op0, rtx op1) 1982{ 1983 unsigned HOST_WIDE_INT high_bits, low_bits; 1984 int lowest_bit_set, highest_bit_set; 1985 int all_bits_between_are_set; 1986 rtx temp = 0; 1987 1988 /* Sanity check that we know what we are working with. */ 1989 if (! TARGET_ARCH64) 1990 abort (); 1991 1992 if (GET_CODE (op0) != SUBREG) 1993 { 1994 if (GET_CODE (op0) != REG 1995 || (REGNO (op0) >= SPARC_FIRST_FP_REG 1996 && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) 1997 abort (); 1998 } 1999 2000 if (reload_in_progress || reload_completed) 2001 temp = op0; 2002 2003 if (GET_CODE (op1) != CONST_DOUBLE 2004 && GET_CODE (op1) != CONST_INT) 2005 { 2006 sparc_emit_set_symbolic_const64 (op0, op1, temp); 2007 return; 2008 } 2009 2010 if (! temp) 2011 temp = gen_reg_rtx (DImode); 2012 2013 if (GET_CODE (op1) == CONST_DOUBLE) 2014 { 2015#if HOST_BITS_PER_WIDE_INT == 64 2016 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; 2017 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; 2018#else 2019 high_bits = CONST_DOUBLE_HIGH (op1); 2020 low_bits = CONST_DOUBLE_LOW (op1); 2021#endif 2022 } 2023 else 2024 { 2025#if HOST_BITS_PER_WIDE_INT == 64 2026 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); 2027 low_bits = (INTVAL (op1) & 0xffffffff); 2028#else 2029 high_bits = ((INTVAL (op1) < 0) ? 2030 0xffffffff : 2031 0x00000000); 2032 low_bits = INTVAL (op1); 2033#endif 2034 } 2035 2036 /* low_bits bits 0 --> 31 2037 high_bits bits 32 --> 63 */ 2038 2039 analyze_64bit_constant (high_bits, low_bits, 2040 &highest_bit_set, &lowest_bit_set, 2041 &all_bits_between_are_set); 2042 2043 /* First try for a 2-insn sequence. */ 2044 2045 /* These situations are preferred because the optimizer can 2046 * do more things with them: 2047 * 1) mov -1, %reg 2048 * sllx %reg, shift, %reg 2049 * 2) mov -1, %reg 2050 * srlx %reg, shift, %reg 2051 * 3) mov some_small_const, %reg 2052 * sllx %reg, shift, %reg 2053 */ 2054 if (((highest_bit_set == 63 2055 || lowest_bit_set == 0) 2056 && all_bits_between_are_set != 0) 2057 || ((highest_bit_set - lowest_bit_set) < 12)) 2058 { 2059 HOST_WIDE_INT the_const = -1; 2060 int shift = lowest_bit_set; 2061 2062 if ((highest_bit_set != 63 2063 && lowest_bit_set != 0) 2064 || all_bits_between_are_set == 0) 2065 { 2066 the_const = 2067 create_simple_focus_bits (high_bits, low_bits, 2068 lowest_bit_set, 0); 2069 } 2070 else if (lowest_bit_set == 0) 2071 shift = -(63 - highest_bit_set); 2072 2073 if (! SPARC_SIMM13_P (the_const)) 2074 abort (); 2075 2076 emit_insn (gen_safe_SET64 (temp, the_const)); 2077 if (shift > 0) 2078 emit_insn (gen_rtx_SET (VOIDmode, 2079 op0, 2080 gen_rtx_ASHIFT (DImode, 2081 temp, 2082 GEN_INT (shift)))); 2083 else if (shift < 0) 2084 emit_insn (gen_rtx_SET (VOIDmode, 2085 op0, 2086 gen_rtx_LSHIFTRT (DImode, 2087 temp, 2088 GEN_INT (-shift)))); 2089 else 2090 abort (); 2091 return; 2092 } 2093 2094 /* Now a range of 22 or less bits set somewhere. 2095 * 1) sethi %hi(focus_bits), %reg 2096 * sllx %reg, shift, %reg 2097 * 2) sethi %hi(focus_bits), %reg 2098 * srlx %reg, shift, %reg 2099 */ 2100 if ((highest_bit_set - lowest_bit_set) < 21) 2101 { 2102 unsigned HOST_WIDE_INT focus_bits = 2103 create_simple_focus_bits (high_bits, low_bits, 2104 lowest_bit_set, 10); 2105 2106 if (! SPARC_SETHI_P (focus_bits)) 2107 abort (); 2108 2109 sparc_emit_set_safe_HIGH64 (temp, focus_bits); 2110 2111 /* If lowest_bit_set == 10 then a sethi alone could have done it. */ 2112 if (lowest_bit_set < 10) 2113 emit_insn (gen_rtx_SET (VOIDmode, 2114 op0, 2115 gen_rtx_LSHIFTRT (DImode, temp, 2116 GEN_INT (10 - lowest_bit_set)))); 2117 else if (lowest_bit_set > 10) 2118 emit_insn (gen_rtx_SET (VOIDmode, 2119 op0, 2120 gen_rtx_ASHIFT (DImode, temp, 2121 GEN_INT (lowest_bit_set - 10)))); 2122 else 2123 abort (); 2124 return; 2125 } 2126 2127 /* 1) sethi %hi(low_bits), %reg 2128 * or %reg, %lo(low_bits), %reg 2129 * 2) sethi %hi(~low_bits), %reg 2130 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg 2131 */ 2132 if (high_bits == 0 2133 || high_bits == 0xffffffff) 2134 { 2135 sparc_emit_set_const64_quick1 (op0, temp, low_bits, 2136 (high_bits == 0xffffffff)); 2137 return; 2138 } 2139 2140 /* Now, try 3-insn sequences. */ 2141 2142 /* 1) sethi %hi(high_bits), %reg 2143 * or %reg, %lo(high_bits), %reg 2144 * sllx %reg, 32, %reg 2145 */ 2146 if (low_bits == 0) 2147 { 2148 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); 2149 return; 2150 } 2151 2152 /* We may be able to do something quick 2153 when the constant is negated, so try that. */ 2154 if (const64_is_2insns ((~high_bits) & 0xffffffff, 2155 (~low_bits) & 0xfffffc00)) 2156 { 2157 /* NOTE: The trailing bits get XOR'd so we need the 2158 non-negated bits, not the negated ones. */ 2159 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; 2160 2161 if ((((~high_bits) & 0xffffffff) == 0 2162 && ((~low_bits) & 0x80000000) == 0) 2163 || (((~high_bits) & 0xffffffff) == 0xffffffff 2164 && ((~low_bits) & 0x80000000) != 0)) 2165 { 2166 int fast_int = (~low_bits & 0xffffffff); 2167 2168 if ((SPARC_SETHI_P (fast_int) 2169 && (~high_bits & 0xffffffff) == 0) 2170 || SPARC_SIMM13_P (fast_int)) 2171 emit_insn (gen_safe_SET64 (temp, fast_int)); 2172 else 2173 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); 2174 } 2175 else 2176 { 2177 rtx negated_const; 2178#if HOST_BITS_PER_WIDE_INT == 64 2179 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | 2180 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); 2181#else 2182 negated_const = immed_double_const ((~low_bits) & 0xfffffc00, 2183 (~high_bits) & 0xffffffff, 2184 DImode); 2185#endif 2186 sparc_emit_set_const64 (temp, negated_const); 2187 } 2188 2189 /* If we are XOR'ing with -1, then we should emit a one's complement 2190 instead. This way the combiner will notice logical operations 2191 such as ANDN later on and substitute. */ 2192 if (trailing_bits == 0x3ff) 2193 { 2194 emit_insn (gen_rtx_SET (VOIDmode, op0, 2195 gen_rtx_NOT (DImode, temp))); 2196 } 2197 else 2198 { 2199 emit_insn (gen_rtx_SET (VOIDmode, 2200 op0, 2201 gen_safe_XOR64 (temp, 2202 (-0x400 | trailing_bits)))); 2203 } 2204 return; 2205 } 2206 2207 /* 1) sethi %hi(xxx), %reg 2208 * or %reg, %lo(xxx), %reg 2209 * sllx %reg, yyy, %reg 2210 * 2211 * ??? This is just a generalized version of the low_bits==0 2212 * thing above, FIXME... 2213 */ 2214 if ((highest_bit_set - lowest_bit_set) < 32) 2215 { 2216 unsigned HOST_WIDE_INT focus_bits = 2217 create_simple_focus_bits (high_bits, low_bits, 2218 lowest_bit_set, 0); 2219 2220 /* We can't get here in this state. */ 2221 if (highest_bit_set < 32 2222 || lowest_bit_set >= 32) 2223 abort (); 2224 2225 /* So what we know is that the set bits straddle the 2226 middle of the 64-bit word. */ 2227 sparc_emit_set_const64_quick2 (op0, temp, 2228 focus_bits, 0, 2229 lowest_bit_set); 2230 return; 2231 } 2232 2233 /* 1) sethi %hi(high_bits), %reg 2234 * or %reg, %lo(high_bits), %reg 2235 * sllx %reg, 32, %reg 2236 * or %reg, low_bits, %reg 2237 */ 2238 if (SPARC_SIMM13_P(low_bits) 2239 && ((int)low_bits > 0)) 2240 { 2241 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); 2242 return; 2243 } 2244 2245 /* The easiest way when all else fails, is full decomposition. */ 2246#if 0 2247 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", 2248 high_bits, low_bits, ~high_bits, ~low_bits); 2249#endif 2250 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); 2251} 2252 2253/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2254 return the mode to be used for the comparison. For floating-point, 2255 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 2256 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 2257 processing is needed. */ 2258 2259enum machine_mode 2260select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED) 2261{ 2262 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2263 { 2264 switch (op) 2265 { 2266 case EQ: 2267 case NE: 2268 case UNORDERED: 2269 case ORDERED: 2270 case UNLT: 2271 case UNLE: 2272 case UNGT: 2273 case UNGE: 2274 case UNEQ: 2275 case LTGT: 2276 return CCFPmode; 2277 2278 case LT: 2279 case LE: 2280 case GT: 2281 case GE: 2282 return CCFPEmode; 2283 2284 default: 2285 abort (); 2286 } 2287 } 2288 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS 2289 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) 2290 { 2291 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 2292 return CCX_NOOVmode; 2293 else 2294 return CC_NOOVmode; 2295 } 2296 else 2297 { 2298 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 2299 return CCXmode; 2300 else 2301 return CCmode; 2302 } 2303} 2304 2305/* X and Y are two things to compare using CODE. Emit the compare insn and 2306 return the rtx for the cc reg in the proper mode. */ 2307 2308rtx 2309gen_compare_reg (enum rtx_code code, rtx x, rtx y) 2310{ 2311 enum machine_mode mode = SELECT_CC_MODE (code, x, y); 2312 rtx cc_reg; 2313 2314 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the 2315 fcc regs (cse can't tell they're really call clobbered regs and will 2316 remove a duplicate comparison even if there is an intervening function 2317 call - it will then try to reload the cc reg via an int reg which is why 2318 we need the movcc patterns). It is possible to provide the movcc 2319 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two 2320 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be 2321 to tell cse that CCFPE mode registers (even pseudos) are call 2322 clobbered. */ 2323 2324 /* ??? This is an experiment. Rather than making changes to cse which may 2325 or may not be easy/clean, we do our own cse. This is possible because 2326 we will generate hard registers. Cse knows they're call clobbered (it 2327 doesn't know the same thing about pseudos). If we guess wrong, no big 2328 deal, but if we win, great! */ 2329 2330 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2331#if 1 /* experiment */ 2332 { 2333 int reg; 2334 /* We cycle through the registers to ensure they're all exercised. */ 2335 static int next_fcc_reg = 0; 2336 /* Previous x,y for each fcc reg. */ 2337 static rtx prev_args[4][2]; 2338 2339 /* Scan prev_args for x,y. */ 2340 for (reg = 0; reg < 4; reg++) 2341 if (prev_args[reg][0] == x && prev_args[reg][1] == y) 2342 break; 2343 if (reg == 4) 2344 { 2345 reg = next_fcc_reg; 2346 prev_args[reg][0] = x; 2347 prev_args[reg][1] = y; 2348 next_fcc_reg = (next_fcc_reg + 1) & 3; 2349 } 2350 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); 2351 } 2352#else 2353 cc_reg = gen_reg_rtx (mode); 2354#endif /* ! experiment */ 2355 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2356 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); 2357 else 2358 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); 2359 2360 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, 2361 gen_rtx_COMPARE (mode, x, y))); 2362 2363 return cc_reg; 2364} 2365 2366/* This function is used for v9 only. 2367 CODE is the code for an Scc's comparison. 2368 OPERANDS[0] is the target of the Scc insn. 2369 OPERANDS[1] is the value we compare against const0_rtx (which hasn't 2370 been generated yet). 2371 2372 This function is needed to turn 2373 2374 (set (reg:SI 110) 2375 (gt (reg:CCX 100 %icc) 2376 (const_int 0))) 2377 into 2378 (set (reg:SI 110) 2379 (gt:DI (reg:CCX 100 %icc) 2380 (const_int 0))) 2381 2382 IE: The instruction recognizer needs to see the mode of the comparison to 2383 find the right instruction. We could use "gt:DI" right in the 2384 define_expand, but leaving it out allows us to handle DI, SI, etc. 2385 2386 We refer to the global sparc compare operands sparc_compare_op0 and 2387 sparc_compare_op1. */ 2388 2389int 2390gen_v9_scc (enum rtx_code compare_code, register rtx *operands) 2391{ 2392 rtx temp, op0, op1; 2393 2394 if (! TARGET_ARCH64 2395 && (GET_MODE (sparc_compare_op0) == DImode 2396 || GET_MODE (operands[0]) == DImode)) 2397 return 0; 2398 2399 op0 = sparc_compare_op0; 2400 op1 = sparc_compare_op1; 2401 2402 /* Try to use the movrCC insns. */ 2403 if (TARGET_ARCH64 2404 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 2405 && op1 == const0_rtx 2406 && v9_regcmp_p (compare_code)) 2407 { 2408 /* Special case for op0 != 0. This can be done with one instruction if 2409 operands[0] == sparc_compare_op0. */ 2410 2411 if (compare_code == NE 2412 && GET_MODE (operands[0]) == DImode 2413 && rtx_equal_p (op0, operands[0])) 2414 { 2415 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2416 gen_rtx_IF_THEN_ELSE (DImode, 2417 gen_rtx_fmt_ee (compare_code, DImode, 2418 op0, const0_rtx), 2419 const1_rtx, 2420 operands[0]))); 2421 return 1; 2422 } 2423 2424 if (reg_overlap_mentioned_p (operands[0], op0)) 2425 { 2426 /* Handle the case where operands[0] == sparc_compare_op0. 2427 We "early clobber" the result. */ 2428 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); 2429 emit_move_insn (op0, sparc_compare_op0); 2430 } 2431 2432 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); 2433 if (GET_MODE (op0) != DImode) 2434 { 2435 temp = gen_reg_rtx (DImode); 2436 convert_move (temp, op0, 0); 2437 } 2438 else 2439 temp = op0; 2440 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2441 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 2442 gen_rtx_fmt_ee (compare_code, DImode, 2443 temp, const0_rtx), 2444 const1_rtx, 2445 operands[0]))); 2446 return 1; 2447 } 2448 else 2449 { 2450 operands[1] = gen_compare_reg (compare_code, op0, op1); 2451 2452 switch (GET_MODE (operands[1])) 2453 { 2454 case CCmode : 2455 case CCXmode : 2456 case CCFPEmode : 2457 case CCFPmode : 2458 break; 2459 default : 2460 abort (); 2461 } 2462 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); 2463 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2464 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 2465 gen_rtx_fmt_ee (compare_code, 2466 GET_MODE (operands[1]), 2467 operands[1], const0_rtx), 2468 const1_rtx, operands[0]))); 2469 return 1; 2470 } 2471} 2472 2473/* Emit a conditional jump insn for the v9 architecture using comparison code 2474 CODE and jump target LABEL. 2475 This function exists to take advantage of the v9 brxx insns. */ 2476 2477void 2478emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label) 2479{ 2480 emit_jump_insn (gen_rtx_SET (VOIDmode, 2481 pc_rtx, 2482 gen_rtx_IF_THEN_ELSE (VOIDmode, 2483 gen_rtx_fmt_ee (code, GET_MODE (op0), 2484 op0, const0_rtx), 2485 gen_rtx_LABEL_REF (VOIDmode, label), 2486 pc_rtx))); 2487} 2488 2489/* Generate a DFmode part of a hard TFmode register. 2490 REG is the TFmode hard register, LOW is 1 for the 2491 low 64bit of the register and 0 otherwise. 2492 */ 2493rtx 2494gen_df_reg (rtx reg, int low) 2495{ 2496 int regno = REGNO (reg); 2497 2498 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) 2499 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; 2500 return gen_rtx_REG (DFmode, regno); 2501} 2502 2503/* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. 2504 Unlike normal calls, TFmode operands are passed by reference. It is 2505 assumed that no more than 3 operands are required. */ 2506 2507static void 2508emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands) 2509{ 2510 rtx ret_slot = NULL, arg[3], func_sym; 2511 int i; 2512 2513 /* We only expect to be called for conversions, unary, and binary ops. */ 2514 if (nargs < 2 || nargs > 3) 2515 abort (); 2516 2517 for (i = 0; i < nargs; ++i) 2518 { 2519 rtx this_arg = operands[i]; 2520 rtx this_slot; 2521 2522 /* TFmode arguments and return values are passed by reference. */ 2523 if (GET_MODE (this_arg) == TFmode) 2524 { 2525 int force_stack_temp; 2526 2527 force_stack_temp = 0; 2528 if (TARGET_BUGGY_QP_LIB && i == 0) 2529 force_stack_temp = 1; 2530 2531 if (GET_CODE (this_arg) == MEM 2532 && ! force_stack_temp) 2533 this_arg = XEXP (this_arg, 0); 2534 else if (CONSTANT_P (this_arg) 2535 && ! force_stack_temp) 2536 { 2537 this_slot = force_const_mem (TFmode, this_arg); 2538 this_arg = XEXP (this_slot, 0); 2539 } 2540 else 2541 { 2542 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0); 2543 2544 /* Operand 0 is the return value. We'll copy it out later. */ 2545 if (i > 0) 2546 emit_move_insn (this_slot, this_arg); 2547 else 2548 ret_slot = this_slot; 2549 2550 this_arg = XEXP (this_slot, 0); 2551 } 2552 } 2553 2554 arg[i] = this_arg; 2555 } 2556 2557 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); 2558 2559 if (GET_MODE (operands[0]) == TFmode) 2560 { 2561 if (nargs == 2) 2562 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2, 2563 arg[0], GET_MODE (arg[0]), 2564 arg[1], GET_MODE (arg[1])); 2565 else 2566 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3, 2567 arg[0], GET_MODE (arg[0]), 2568 arg[1], GET_MODE (arg[1]), 2569 arg[2], GET_MODE (arg[2])); 2570 2571 if (ret_slot) 2572 emit_move_insn (operands[0], ret_slot); 2573 } 2574 else 2575 { 2576 rtx ret; 2577 2578 if (nargs != 2) 2579 abort (); 2580 2581 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, 2582 GET_MODE (operands[0]), 1, 2583 arg[1], GET_MODE (arg[1])); 2584 2585 if (ret != operands[0]) 2586 emit_move_insn (operands[0], ret); 2587 } 2588} 2589 2590/* Expand soft-float TFmode calls to sparc abi routines. */ 2591 2592static void 2593emit_soft_tfmode_binop (enum rtx_code code, rtx *operands) 2594{ 2595 const char *func; 2596 2597 switch (code) 2598 { 2599 case PLUS: 2600 func = "_Qp_add"; 2601 break; 2602 case MINUS: 2603 func = "_Qp_sub"; 2604 break; 2605 case MULT: 2606 func = "_Qp_mul"; 2607 break; 2608 case DIV: 2609 func = "_Qp_div"; 2610 break; 2611 default: 2612 abort (); 2613 } 2614 2615 emit_soft_tfmode_libcall (func, 3, operands); 2616} 2617 2618static void 2619emit_soft_tfmode_unop (enum rtx_code code, rtx *operands) 2620{ 2621 const char *func; 2622 2623 switch (code) 2624 { 2625 case SQRT: 2626 func = "_Qp_sqrt"; 2627 break; 2628 default: 2629 abort (); 2630 } 2631 2632 emit_soft_tfmode_libcall (func, 2, operands); 2633} 2634 2635static void 2636emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) 2637{ 2638 const char *func; 2639 2640 switch (code) 2641 { 2642 case FLOAT_EXTEND: 2643 switch (GET_MODE (operands[1])) 2644 { 2645 case SFmode: 2646 func = "_Qp_stoq"; 2647 break; 2648 case DFmode: 2649 func = "_Qp_dtoq"; 2650 break; 2651 default: 2652 abort (); 2653 } 2654 break; 2655 2656 case FLOAT_TRUNCATE: 2657 switch (GET_MODE (operands[0])) 2658 { 2659 case SFmode: 2660 func = "_Qp_qtos"; 2661 break; 2662 case DFmode: 2663 func = "_Qp_qtod"; 2664 break; 2665 default: 2666 abort (); 2667 } 2668 break; 2669 2670 case FLOAT: 2671 switch (GET_MODE (operands[1])) 2672 { 2673 case SImode: 2674 func = "_Qp_itoq"; 2675 break; 2676 case DImode: 2677 func = "_Qp_xtoq"; 2678 break; 2679 default: 2680 abort (); 2681 } 2682 break; 2683 2684 case UNSIGNED_FLOAT: 2685 switch (GET_MODE (operands[1])) 2686 { 2687 case SImode: 2688 func = "_Qp_uitoq"; 2689 break; 2690 case DImode: 2691 func = "_Qp_uxtoq"; 2692 break; 2693 default: 2694 abort (); 2695 } 2696 break; 2697 2698 case FIX: 2699 switch (GET_MODE (operands[0])) 2700 { 2701 case SImode: 2702 func = "_Qp_qtoi"; 2703 break; 2704 case DImode: 2705 func = "_Qp_qtox"; 2706 break; 2707 default: 2708 abort (); 2709 } 2710 break; 2711 2712 case UNSIGNED_FIX: 2713 switch (GET_MODE (operands[0])) 2714 { 2715 case SImode: 2716 func = "_Qp_qtoui"; 2717 break; 2718 case DImode: 2719 func = "_Qp_qtoux"; 2720 break; 2721 default: 2722 abort (); 2723 } 2724 break; 2725 2726 default: 2727 abort (); 2728 } 2729 2730 emit_soft_tfmode_libcall (func, 2, operands); 2731} 2732 2733/* Expand a hard-float tfmode operation. All arguments must be in 2734 registers. */ 2735 2736static void 2737emit_hard_tfmode_operation (enum rtx_code code, rtx *operands) 2738{ 2739 rtx op, dest; 2740 2741 if (GET_RTX_CLASS (code) == '1') 2742 { 2743 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 2744 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); 2745 } 2746 else 2747 { 2748 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 2749 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); 2750 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), 2751 operands[1], operands[2]); 2752 } 2753 2754 if (register_operand (operands[0], VOIDmode)) 2755 dest = operands[0]; 2756 else 2757 dest = gen_reg_rtx (GET_MODE (operands[0])); 2758 2759 emit_insn (gen_rtx_SET (VOIDmode, dest, op)); 2760 2761 if (dest != operands[0]) 2762 emit_move_insn (operands[0], dest); 2763} 2764 2765void 2766emit_tfmode_binop (enum rtx_code code, rtx *operands) 2767{ 2768 if (TARGET_HARD_QUAD) 2769 emit_hard_tfmode_operation (code, operands); 2770 else 2771 emit_soft_tfmode_binop (code, operands); 2772} 2773 2774void 2775emit_tfmode_unop (enum rtx_code code, rtx *operands) 2776{ 2777 if (TARGET_HARD_QUAD) 2778 emit_hard_tfmode_operation (code, operands); 2779 else 2780 emit_soft_tfmode_unop (code, operands); 2781} 2782 2783void 2784emit_tfmode_cvt (enum rtx_code code, rtx *operands) 2785{ 2786 if (TARGET_HARD_QUAD) 2787 emit_hard_tfmode_operation (code, operands); 2788 else 2789 emit_soft_tfmode_cvt (code, operands); 2790} 2791 2792/* Return nonzero if a return peephole merging return with 2793 setting of output register is ok. */ 2794int 2795leaf_return_peephole_ok (void) 2796{ 2797 return (actual_fsize == 0); 2798} 2799 2800/* Return nonzero if a branch/jump/call instruction will be emitting 2801 nop into its delay slot. */ 2802 2803int 2804empty_delay_slot (rtx insn) 2805{ 2806 rtx seq; 2807 2808 /* If no previous instruction (should not happen), return true. */ 2809 if (PREV_INSN (insn) == NULL) 2810 return 1; 2811 2812 seq = NEXT_INSN (PREV_INSN (insn)); 2813 if (GET_CODE (PATTERN (seq)) == SEQUENCE) 2814 return 0; 2815 2816 return 1; 2817} 2818 2819/* Return nonzero if TRIAL can go into the function epilogue's 2820 delay slot. SLOT is the slot we are trying to fill. */ 2821 2822int 2823eligible_for_epilogue_delay (rtx trial, int slot) 2824{ 2825 rtx pat, src; 2826 2827 if (slot >= 1) 2828 return 0; 2829 2830 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) 2831 return 0; 2832 2833 if (get_attr_length (trial) != 1) 2834 return 0; 2835 2836 /* If there are any call-saved registers, we should scan TRIAL if it 2837 does not reference them. For now just make it easy. */ 2838 if (num_gfregs) 2839 return 0; 2840 2841 /* If the function uses __builtin_eh_return, the eh_return machinery 2842 occupies the delay slot. */ 2843 if (current_function_calls_eh_return) 2844 return 0; 2845 2846 /* In the case of a true leaf function, anything can go into the delay slot. 2847 A delay slot only exists however if the frame size is zero, otherwise 2848 we will put an insn to adjust the stack after the return. */ 2849 if (current_function_uses_only_leaf_regs) 2850 { 2851 if (leaf_return_peephole_ok ()) 2852 return ((get_attr_in_uncond_branch_delay (trial) 2853 == IN_BRANCH_DELAY_TRUE)); 2854 return 0; 2855 } 2856 2857 pat = PATTERN (trial); 2858 2859 /* Otherwise, only operations which can be done in tandem with 2860 a `restore' or `return' insn can go into the delay slot. */ 2861 if (GET_CODE (SET_DEST (pat)) != REG 2862 || REGNO (SET_DEST (pat)) < 24) 2863 return 0; 2864 2865 /* If this instruction sets up floating point register and we have a return 2866 instruction, it can probably go in. But restore will not work 2867 with FP_REGS. */ 2868 if (REGNO (SET_DEST (pat)) >= 32) 2869 { 2870 if (TARGET_V9 && ! epilogue_renumber (&pat, 1) 2871 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) 2872 return 1; 2873 return 0; 2874 } 2875 2876 /* The set of insns matched here must agree precisely with the set of 2877 patterns paired with a RETURN in sparc.md. */ 2878 2879 src = SET_SRC (pat); 2880 2881 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ 2882 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2883 && arith_operand (src, GET_MODE (src))) 2884 { 2885 if (TARGET_ARCH64) 2886 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2887 else 2888 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); 2889 } 2890 2891 /* This matches "*return_di". */ 2892 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2893 && arith_double_operand (src, GET_MODE (src))) 2894 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2895 2896 /* This matches "*return_sf_no_fpu". */ 2897 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) 2898 && register_operand (src, SFmode)) 2899 return 1; 2900 2901 /* If we have return instruction, anything that does not use 2902 local or output registers and can go into a delay slot wins. */ 2903 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1) 2904 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) 2905 return 1; 2906 2907 /* This matches "*return_addsi". */ 2908 else if (GET_CODE (src) == PLUS 2909 && arith_operand (XEXP (src, 0), SImode) 2910 && arith_operand (XEXP (src, 1), SImode) 2911 && (register_operand (XEXP (src, 0), SImode) 2912 || register_operand (XEXP (src, 1), SImode))) 2913 return 1; 2914 2915 /* This matches "*return_adddi". */ 2916 else if (GET_CODE (src) == PLUS 2917 && arith_double_operand (XEXP (src, 0), DImode) 2918 && arith_double_operand (XEXP (src, 1), DImode) 2919 && (register_operand (XEXP (src, 0), DImode) 2920 || register_operand (XEXP (src, 1), DImode))) 2921 return 1; 2922 2923 /* This can match "*return_losum_[sd]i". 2924 Catch only some cases, so that return_losum* don't have 2925 to be too big. */ 2926 else if (GET_CODE (src) == LO_SUM 2927 && ! TARGET_CM_MEDMID 2928 && ((register_operand (XEXP (src, 0), SImode) 2929 && immediate_operand (XEXP (src, 1), SImode)) 2930 || (TARGET_ARCH64 2931 && register_operand (XEXP (src, 0), DImode) 2932 && immediate_operand (XEXP (src, 1), DImode)))) 2933 return 1; 2934 2935 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */ 2936 else if (GET_CODE (src) == ASHIFT 2937 && (register_operand (XEXP (src, 0), SImode) 2938 || register_operand (XEXP (src, 0), DImode)) 2939 && XEXP (src, 1) == const1_rtx) 2940 return 1; 2941 2942 return 0; 2943} 2944 2945/* Return nonzero if TRIAL can go into the call delay slot. */ 2946int 2947tls_call_delay (rtx trial) 2948{ 2949 rtx pat, unspec; 2950 2951 /* Binutils allows 2952 call __tls_get_addr, %tgd_call (foo) 2953 add %l7, %o0, %o0, %tgd_add (foo) 2954 while Sun as/ld does not. */ 2955 if (TARGET_GNU_TLS || !TARGET_TLS) 2956 return 1; 2957 2958 pat = PATTERN (trial); 2959 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS) 2960 return 1; 2961 2962 unspec = XEXP (SET_DEST (pat), 1); 2963 if (GET_CODE (unspec) != UNSPEC 2964 || (XINT (unspec, 1) != UNSPEC_TLSGD 2965 && XINT (unspec, 1) != UNSPEC_TLSLDM)) 2966 return 1; 2967 2968 return 0; 2969} 2970 2971/* Return nonzero if TRIAL can go into the sibling call 2972 delay slot. */ 2973 2974int 2975eligible_for_sibcall_delay (rtx trial) 2976{ 2977 rtx pat, src; 2978 2979 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) 2980 return 0; 2981 2982 if (get_attr_length (trial) != 1) 2983 return 0; 2984 2985 pat = PATTERN (trial); 2986 2987 if (current_function_uses_only_leaf_regs) 2988 { 2989 /* If the tail call is done using the call instruction, 2990 we have to restore %o7 in the delay slot. */ 2991 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic) 2992 return 0; 2993 2994 /* %g1 is used to build the function address */ 2995 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) 2996 return 0; 2997 2998 return 1; 2999 } 3000 3001 /* Otherwise, only operations which can be done in tandem with 3002 a `restore' insn can go into the delay slot. */ 3003 if (GET_CODE (SET_DEST (pat)) != REG 3004 || REGNO (SET_DEST (pat)) < 24 3005 || REGNO (SET_DEST (pat)) >= 32) 3006 return 0; 3007 3008 /* If it mentions %o7, it can't go in, because sibcall will clobber it 3009 in most cases. */ 3010 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) 3011 return 0; 3012 3013 src = SET_SRC (pat); 3014 3015 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 3016 && arith_operand (src, GET_MODE (src))) 3017 { 3018 if (TARGET_ARCH64) 3019 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 3020 else 3021 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); 3022 } 3023 3024 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 3025 && arith_double_operand (src, GET_MODE (src))) 3026 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 3027 3028 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) 3029 && register_operand (src, SFmode)) 3030 return 1; 3031 3032 else if (GET_CODE (src) == PLUS 3033 && arith_operand (XEXP (src, 0), SImode) 3034 && arith_operand (XEXP (src, 1), SImode) 3035 && (register_operand (XEXP (src, 0), SImode) 3036 || register_operand (XEXP (src, 1), SImode))) 3037 return 1; 3038 3039 else if (GET_CODE (src) == PLUS 3040 && arith_double_operand (XEXP (src, 0), DImode) 3041 && arith_double_operand (XEXP (src, 1), DImode) 3042 && (register_operand (XEXP (src, 0), DImode) 3043 || register_operand (XEXP (src, 1), DImode))) 3044 return 1; 3045 3046 else if (GET_CODE (src) == LO_SUM 3047 && ! TARGET_CM_MEDMID 3048 && ((register_operand (XEXP (src, 0), SImode) 3049 && immediate_operand (XEXP (src, 1), SImode)) 3050 || (TARGET_ARCH64 3051 && register_operand (XEXP (src, 0), DImode) 3052 && immediate_operand (XEXP (src, 1), DImode)))) 3053 return 1; 3054 3055 else if (GET_CODE (src) == ASHIFT 3056 && (register_operand (XEXP (src, 0), SImode) 3057 || register_operand (XEXP (src, 0), DImode)) 3058 && XEXP (src, 1) == const1_rtx) 3059 return 1; 3060 3061 return 0; 3062} 3063 3064static int 3065check_return_regs (rtx x) 3066{ 3067 switch (GET_CODE (x)) 3068 { 3069 case REG: 3070 return IN_OR_GLOBAL_P (x); 3071 3072 case CONST_INT: 3073 case CONST_DOUBLE: 3074 case CONST: 3075 case SYMBOL_REF: 3076 case LABEL_REF: 3077 return 1; 3078 3079 case SET: 3080 case IOR: 3081 case AND: 3082 case XOR: 3083 case PLUS: 3084 case MINUS: 3085 if (check_return_regs (XEXP (x, 1)) == 0) 3086 return 0; 3087 case NOT: 3088 case NEG: 3089 case MEM: 3090 return check_return_regs (XEXP (x, 0)); 3091 3092 default: 3093 return 0; 3094 } 3095 3096} 3097 3098int 3099short_branch (int uid1, int uid2) 3100{ 3101 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2); 3102 3103 /* Leave a few words of "slop". */ 3104 if (delta >= -1023 && delta <= 1022) 3105 return 1; 3106 3107 return 0; 3108} 3109 3110/* Return nonzero if REG is not used after INSN. 3111 We assume REG is a reload reg, and therefore does 3112 not live past labels or calls or jumps. */ 3113int 3114reg_unused_after (rtx reg, rtx insn) 3115{ 3116 enum rtx_code code, prev_code = UNKNOWN; 3117 3118 while ((insn = NEXT_INSN (insn))) 3119 { 3120 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) 3121 return 1; 3122 3123 code = GET_CODE (insn); 3124 if (GET_CODE (insn) == CODE_LABEL) 3125 return 1; 3126 3127 if (GET_RTX_CLASS (code) == 'i') 3128 { 3129 rtx set = single_set (insn); 3130 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); 3131 if (set && in_src) 3132 return 0; 3133 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) 3134 return 1; 3135 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) 3136 return 0; 3137 } 3138 prev_code = code; 3139 } 3140 return 1; 3141} 3142 3143/* Determine if it's legal to put X into the constant pool. This 3144 is not possible if X contains the address of a symbol that is 3145 not constant (TLS) or not known at final link time (PIC). */ 3146 3147static bool 3148sparc_cannot_force_const_mem (rtx x) 3149{ 3150 switch (GET_CODE (x)) 3151 { 3152 case CONST_INT: 3153 case CONST_DOUBLE: 3154 /* Accept all non-symbolic constants. */ 3155 return false; 3156 3157 case LABEL_REF: 3158 /* Labels are OK iff we are non-PIC. */ 3159 return flag_pic != 0; 3160 3161 case SYMBOL_REF: 3162 /* 'Naked' TLS symbol references are never OK, 3163 non-TLS symbols are OK iff we are non-PIC. */ 3164 if (SYMBOL_REF_TLS_MODEL (x)) 3165 return true; 3166 else 3167 return flag_pic != 0; 3168 3169 case CONST: 3170 return sparc_cannot_force_const_mem (XEXP (x, 0)); 3171 case PLUS: 3172 case MINUS: 3173 return sparc_cannot_force_const_mem (XEXP (x, 0)) 3174 || sparc_cannot_force_const_mem (XEXP (x, 1)); 3175 case UNSPEC: 3176 return true; 3177 default: 3178 abort (); 3179 } 3180} 3181 3182/* The table we use to reference PIC data. */ 3183static GTY(()) rtx global_offset_table; 3184 3185/* The function we use to get at it. */ 3186static GTY(()) rtx get_pc_symbol; 3187static GTY(()) char get_pc_symbol_name[256]; 3188 3189/* Ensure that we are not using patterns that are not OK with PIC. */ 3190 3191int 3192check_pic (int i) 3193{ 3194 switch (flag_pic) 3195 { 3196 case 1: 3197 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF 3198 || (GET_CODE (recog_data.operand[i]) == CONST 3199 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS 3200 && (XEXP (XEXP (recog_data.operand[i], 0), 0) 3201 == global_offset_table) 3202 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) 3203 == CONST)))) 3204 abort (); 3205 case 2: 3206 default: 3207 return 1; 3208 } 3209} 3210 3211/* Return true if X is an address which needs a temporary register when 3212 reloaded while generating PIC code. */ 3213 3214int 3215pic_address_needs_scratch (rtx x) 3216{ 3217 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ 3218 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS 3219 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 3220 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3221 && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) 3222 return 1; 3223 3224 return 0; 3225} 3226 3227/* Determine if a given RTX is a valid constant. We already know this 3228 satisfies CONSTANT_P. */ 3229 3230bool 3231legitimate_constant_p (rtx x) 3232{ 3233 rtx inner; 3234 3235 switch (GET_CODE (x)) 3236 { 3237 case SYMBOL_REF: 3238 /* TLS symbols are not constant. */ 3239 if (SYMBOL_REF_TLS_MODEL (x)) 3240 return false; 3241 break; 3242 3243 case CONST: 3244 inner = XEXP (x, 0); 3245 3246 /* Offsets of TLS symbols are never valid. 3247 Discourage CSE from creating them. */ 3248 if (GET_CODE (inner) == PLUS 3249 && tls_symbolic_operand (XEXP (inner, 0))) 3250 return false; 3251 break; 3252 3253 case CONST_DOUBLE: 3254 if (GET_MODE (x) == VOIDmode) 3255 return true; 3256 3257 /* Floating point constants are generally not ok. 3258 The only exception is 0.0 in VIS. */ 3259 if (TARGET_VIS 3260 && (GET_MODE (x) == SFmode 3261 || GET_MODE (x) == DFmode 3262 || GET_MODE (x) == TFmode) 3263 && fp_zero_operand (x, GET_MODE (x))) 3264 return true; 3265 3266 return false; 3267 3268 default: 3269 break; 3270 } 3271 3272 return true; 3273} 3274 3275/* Determine if a given RTX is a valid constant address. */ 3276 3277bool 3278constant_address_p (rtx x) 3279{ 3280 switch (GET_CODE (x)) 3281 { 3282 case LABEL_REF: 3283 case CONST_INT: 3284 case HIGH: 3285 return true; 3286 3287 case CONST: 3288 if (flag_pic && pic_address_needs_scratch (x)) 3289 return false; 3290 return legitimate_constant_p (x); 3291 3292 case SYMBOL_REF: 3293 return !flag_pic && legitimate_constant_p (x); 3294 3295 default: 3296 return false; 3297 } 3298} 3299 3300/* Nonzero if the constant value X is a legitimate general operand 3301 when generating PIC code. It is given that flag_pic is on and 3302 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 3303 3304bool 3305legitimate_pic_operand_p (rtx x) 3306{ 3307 if (pic_address_needs_scratch (x)) 3308 return false; 3309 if (tls_symbolic_operand (x) 3310 || (GET_CODE (x) == CONST 3311 && GET_CODE (XEXP (x, 0)) == PLUS 3312 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0)))) 3313 return false; 3314 return true; 3315} 3316 3317/* Return nonzero if ADDR is a valid memory address. 3318 STRICT specifies whether strict register checking applies. */ 3319 3320int 3321legitimate_address_p (enum machine_mode mode, rtx addr, int strict) 3322{ 3323 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL; 3324 3325 if (REG_P (addr) || GET_CODE (addr) == SUBREG) 3326 rs1 = addr; 3327 else if (GET_CODE (addr) == PLUS) 3328 { 3329 rs1 = XEXP (addr, 0); 3330 rs2 = XEXP (addr, 1); 3331 3332 /* Canonicalize. REG comes first, if there are no regs, 3333 LO_SUM comes first. */ 3334 if (!REG_P (rs1) 3335 && GET_CODE (rs1) != SUBREG 3336 && (REG_P (rs2) 3337 || GET_CODE (rs2) == SUBREG 3338 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM))) 3339 { 3340 rs1 = XEXP (addr, 1); 3341 rs2 = XEXP (addr, 0); 3342 } 3343 3344 if ((flag_pic == 1 3345 && rs1 == pic_offset_table_rtx 3346 && !REG_P (rs2) 3347 && GET_CODE (rs2) != SUBREG 3348 && GET_CODE (rs2) != LO_SUM 3349 && GET_CODE (rs2) != MEM 3350 && !tls_symbolic_operand (rs2) 3351 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode) 3352 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2))) 3353 || ((REG_P (rs1) 3354 || GET_CODE (rs1) == SUBREG) 3355 && RTX_OK_FOR_OFFSET_P (rs2))) 3356 { 3357 imm1 = rs2; 3358 rs2 = NULL; 3359 } 3360 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG) 3361 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG)) 3362 { 3363 /* We prohibit REG + REG for TFmode when there are no quad move insns 3364 and we consequently need to split. We do this because REG+REG 3365 is not an offsettable address. If we get the situation in reload 3366 where source and destination of a movtf pattern are both MEMs with 3367 REG+REG address, then only one of them gets converted to an 3368 offsettable address. */ 3369 if (mode == TFmode 3370 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD)) 3371 return 0; 3372 3373 /* We prohibit REG + REG on ARCH32 if not optimizing for 3374 DFmode/DImode because then mem_min_alignment is likely to be zero 3375 after reload and the forced split would lack a matching splitter 3376 pattern. */ 3377 if (TARGET_ARCH32 && !optimize 3378 && (mode == DFmode || mode == DImode)) 3379 return 0; 3380 } 3381 else if (USE_AS_OFFSETABLE_LO10 3382 && GET_CODE (rs1) == LO_SUM 3383 && TARGET_ARCH64 3384 && ! TARGET_CM_MEDMID 3385 && RTX_OK_FOR_OLO10_P (rs2)) 3386 { 3387 rs2 = NULL; 3388 imm1 = XEXP (rs1, 1); 3389 rs1 = XEXP (rs1, 0); 3390 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1)) 3391 return 0; 3392 } 3393 } 3394 else if (GET_CODE (addr) == LO_SUM) 3395 { 3396 rs1 = XEXP (addr, 0); 3397 imm1 = XEXP (addr, 1); 3398 3399 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1)) 3400 return 0; 3401 3402 /* We can't allow TFmode in 32-bit mode, because an offset greater 3403 than the alignment (8) may cause the LO_SUM to overflow. */ 3404 if (mode == TFmode && TARGET_ARCH32) 3405 return 0; 3406 } 3407 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr)) 3408 return 1; 3409 else 3410 return 0; 3411 3412 if (GET_CODE (rs1) == SUBREG) 3413 rs1 = SUBREG_REG (rs1); 3414 if (!REG_P (rs1)) 3415 return 0; 3416 3417 if (rs2) 3418 { 3419 if (GET_CODE (rs2) == SUBREG) 3420 rs2 = SUBREG_REG (rs2); 3421 if (!REG_P (rs2)) 3422 return 0; 3423 } 3424 3425 if (strict) 3426 { 3427 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1)) 3428 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2)))) 3429 return 0; 3430 } 3431 else 3432 { 3433 if ((REGNO (rs1) >= 32 3434 && REGNO (rs1) != FRAME_POINTER_REGNUM 3435 && REGNO (rs1) < FIRST_PSEUDO_REGISTER) 3436 || (rs2 3437 && (REGNO (rs2) >= 32 3438 && REGNO (rs2) != FRAME_POINTER_REGNUM 3439 && REGNO (rs2) < FIRST_PSEUDO_REGISTER))) 3440 return 0; 3441 } 3442 return 1; 3443} 3444 3445/* Construct the SYMBOL_REF for the tls_get_offset function. */ 3446 3447static GTY(()) rtx sparc_tls_symbol; 3448static rtx 3449sparc_tls_get_addr (void) 3450{ 3451 if (!sparc_tls_symbol) 3452 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr"); 3453 3454 return sparc_tls_symbol; 3455} 3456 3457static rtx 3458sparc_tls_got (void) 3459{ 3460 rtx temp; 3461 if (flag_pic) 3462 { 3463 current_function_uses_pic_offset_table = 1; 3464 return pic_offset_table_rtx; 3465 } 3466 3467 if (!global_offset_table) 3468 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 3469 temp = gen_reg_rtx (Pmode); 3470 emit_move_insn (temp, global_offset_table); 3471 return temp; 3472} 3473 3474 3475/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute 3476 this (thread-local) address. */ 3477 3478rtx 3479legitimize_tls_address (rtx addr) 3480{ 3481 rtx temp1, temp2, temp3, ret, o0, got, insn; 3482 3483 if (no_new_pseudos) 3484 abort (); 3485 3486 if (GET_CODE (addr) == SYMBOL_REF) 3487 switch (SYMBOL_REF_TLS_MODEL (addr)) 3488 { 3489 case TLS_MODEL_GLOBAL_DYNAMIC: 3490 start_sequence (); 3491 temp1 = gen_reg_rtx (SImode); 3492 temp2 = gen_reg_rtx (SImode); 3493 ret = gen_reg_rtx (Pmode); 3494 o0 = gen_rtx_REG (Pmode, 8); 3495 got = sparc_tls_got (); 3496 emit_insn (gen_tgd_hi22 (temp1, addr)); 3497 emit_insn (gen_tgd_lo10 (temp2, temp1, addr)); 3498 if (TARGET_ARCH32) 3499 { 3500 emit_insn (gen_tgd_add32 (o0, got, temp2, addr)); 3501 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (), 3502 addr, const1_rtx)); 3503 } 3504 else 3505 { 3506 emit_insn (gen_tgd_add64 (o0, got, temp2, addr)); 3507 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (), 3508 addr, const1_rtx)); 3509 } 3510 CALL_INSN_FUNCTION_USAGE (insn) 3511 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0), 3512 CALL_INSN_FUNCTION_USAGE (insn)); 3513 insn = get_insns (); 3514 end_sequence (); 3515 emit_libcall_block (insn, ret, o0, addr); 3516 break; 3517 3518 case TLS_MODEL_LOCAL_DYNAMIC: 3519 start_sequence (); 3520 temp1 = gen_reg_rtx (SImode); 3521 temp2 = gen_reg_rtx (SImode); 3522 temp3 = gen_reg_rtx (Pmode); 3523 ret = gen_reg_rtx (Pmode); 3524 o0 = gen_rtx_REG (Pmode, 8); 3525 got = sparc_tls_got (); 3526 emit_insn (gen_tldm_hi22 (temp1)); 3527 emit_insn (gen_tldm_lo10 (temp2, temp1)); 3528 if (TARGET_ARCH32) 3529 { 3530 emit_insn (gen_tldm_add32 (o0, got, temp2)); 3531 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (), 3532 const1_rtx)); 3533 } 3534 else 3535 { 3536 emit_insn (gen_tldm_add64 (o0, got, temp2)); 3537 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (), 3538 const1_rtx)); 3539 } 3540 CALL_INSN_FUNCTION_USAGE (insn) 3541 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0), 3542 CALL_INSN_FUNCTION_USAGE (insn)); 3543 insn = get_insns (); 3544 end_sequence (); 3545 emit_libcall_block (insn, temp3, o0, 3546 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), 3547 UNSPEC_TLSLD_BASE)); 3548 temp1 = gen_reg_rtx (SImode); 3549 temp2 = gen_reg_rtx (SImode); 3550 emit_insn (gen_tldo_hix22 (temp1, addr)); 3551 emit_insn (gen_tldo_lox10 (temp2, temp1, addr)); 3552 if (TARGET_ARCH32) 3553 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr)); 3554 else 3555 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr)); 3556 break; 3557 3558 case TLS_MODEL_INITIAL_EXEC: 3559 temp1 = gen_reg_rtx (SImode); 3560 temp2 = gen_reg_rtx (SImode); 3561 temp3 = gen_reg_rtx (Pmode); 3562 got = sparc_tls_got (); 3563 emit_insn (gen_tie_hi22 (temp1, addr)); 3564 emit_insn (gen_tie_lo10 (temp2, temp1, addr)); 3565 if (TARGET_ARCH32) 3566 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr)); 3567 else 3568 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr)); 3569 if (TARGET_SUN_TLS) 3570 { 3571 ret = gen_reg_rtx (Pmode); 3572 if (TARGET_ARCH32) 3573 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7), 3574 temp3, addr)); 3575 else 3576 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7), 3577 temp3, addr)); 3578 } 3579 else 3580 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3); 3581 break; 3582 3583 case TLS_MODEL_LOCAL_EXEC: 3584 temp1 = gen_reg_rtx (Pmode); 3585 temp2 = gen_reg_rtx (Pmode); 3586 if (TARGET_ARCH32) 3587 { 3588 emit_insn (gen_tle_hix22_sp32 (temp1, addr)); 3589 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr)); 3590 } 3591 else 3592 { 3593 emit_insn (gen_tle_hix22_sp64 (temp1, addr)); 3594 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr)); 3595 } 3596 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2); 3597 break; 3598 3599 default: 3600 abort (); 3601 } 3602 3603 else 3604 abort (); /* for now ... */ 3605 3606 return ret; 3607} 3608 3609 3610/* Legitimize PIC addresses. If the address is already position-independent, 3611 we return ORIG. Newly generated position-independent addresses go into a 3612 reg. This is REG if nonzero, otherwise we allocate register(s) as 3613 necessary. */ 3614 3615rtx 3616legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, 3617 rtx reg) 3618{ 3619 if (GET_CODE (orig) == SYMBOL_REF) 3620 { 3621 rtx pic_ref, address; 3622 rtx insn; 3623 3624 if (reg == 0) 3625 { 3626 if (reload_in_progress || reload_completed) 3627 abort (); 3628 else 3629 reg = gen_reg_rtx (Pmode); 3630 } 3631 3632 if (flag_pic == 2) 3633 { 3634 /* If not during reload, allocate another temp reg here for loading 3635 in the address, so that these instructions can be optimized 3636 properly. */ 3637 rtx temp_reg = ((reload_in_progress || reload_completed) 3638 ? reg : gen_reg_rtx (Pmode)); 3639 3640 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse 3641 won't get confused into thinking that these two instructions 3642 are loading in the true address of the symbol. If in the 3643 future a PIC rtx exists, that should be used instead. */ 3644 if (Pmode == SImode) 3645 { 3646 emit_insn (gen_movsi_high_pic (temp_reg, orig)); 3647 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); 3648 } 3649 else 3650 { 3651 emit_insn (gen_movdi_high_pic (temp_reg, orig)); 3652 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); 3653 } 3654 address = temp_reg; 3655 } 3656 else 3657 address = orig; 3658 3659 pic_ref = gen_rtx_MEM (Pmode, 3660 gen_rtx_PLUS (Pmode, 3661 pic_offset_table_rtx, address)); 3662 current_function_uses_pic_offset_table = 1; 3663 RTX_UNCHANGING_P (pic_ref) = 1; 3664 insn = emit_move_insn (reg, pic_ref); 3665 /* Put a REG_EQUAL note on this insn, so that it can be optimized 3666 by loop. */ 3667 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, 3668 REG_NOTES (insn)); 3669 return reg; 3670 } 3671 else if (GET_CODE (orig) == CONST) 3672 { 3673 rtx base, offset; 3674 3675 if (GET_CODE (XEXP (orig, 0)) == PLUS 3676 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) 3677 return orig; 3678 3679 if (reg == 0) 3680 { 3681 if (reload_in_progress || reload_completed) 3682 abort (); 3683 else 3684 reg = gen_reg_rtx (Pmode); 3685 } 3686 3687 if (GET_CODE (XEXP (orig, 0)) == PLUS) 3688 { 3689 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); 3690 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, 3691 base == reg ? 0 : reg); 3692 } 3693 else 3694 abort (); 3695 3696 if (GET_CODE (offset) == CONST_INT) 3697 { 3698 if (SMALL_INT (offset)) 3699 return plus_constant (base, INTVAL (offset)); 3700 else if (! reload_in_progress && ! reload_completed) 3701 offset = force_reg (Pmode, offset); 3702 else 3703 /* If we reach here, then something is seriously wrong. */ 3704 abort (); 3705 } 3706 return gen_rtx_PLUS (Pmode, base, offset); 3707 } 3708 else if (GET_CODE (orig) == LABEL_REF) 3709 /* ??? Why do we do this? */ 3710 /* Now movsi_pic_label_ref uses it, but we ought to be checking that 3711 the register is live instead, in case it is eliminated. */ 3712 current_function_uses_pic_offset_table = 1; 3713 3714 return orig; 3715} 3716 3717/* Try machine-dependent ways of modifying an illegitimate address X 3718 to be legitimate. If we find one, return the new, valid address. 3719 3720 OLDX is the address as it was before break_out_memory_refs was called. 3721 In some cases it is useful to look at this to decide what needs to be done. 3722 3723 MODE is the mode of the operand pointed to by X. */ 3724 3725rtx 3726legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode) 3727{ 3728 rtx orig_x = x; 3729 3730 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT) 3731 x = gen_rtx_PLUS (Pmode, XEXP (x, 1), 3732 force_operand (XEXP (x, 0), NULL_RTX)); 3733 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT) 3734 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), 3735 force_operand (XEXP (x, 1), NULL_RTX)); 3736 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS) 3737 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX), 3738 XEXP (x, 1)); 3739 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS) 3740 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), 3741 force_operand (XEXP (x, 1), NULL_RTX)); 3742 3743 if (x != orig_x && legitimate_address_p (mode, x, FALSE)) 3744 return x; 3745 3746 if (tls_symbolic_operand (x)) 3747 x = legitimize_tls_address (x); 3748 else if (flag_pic) 3749 x = legitimize_pic_address (x, mode, 0); 3750 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1))) 3751 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), 3752 copy_to_mode_reg (Pmode, XEXP (x, 1))); 3753 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0))) 3754 x = gen_rtx_PLUS (Pmode, XEXP (x, 1), 3755 copy_to_mode_reg (Pmode, XEXP (x, 0))); 3756 else if (GET_CODE (x) == SYMBOL_REF 3757 || GET_CODE (x) == CONST 3758 || GET_CODE (x) == LABEL_REF) 3759 x = copy_to_suggested_reg (x, NULL_RTX, Pmode); 3760 return x; 3761} 3762 3763/* Emit special PIC prologues. */ 3764 3765void 3766load_pic_register (void) 3767{ 3768 /* Labels to get the PC in the prologue of this function. */ 3769 int orig_flag_pic = flag_pic; 3770 3771 if (! flag_pic) 3772 abort (); 3773 3774 /* If we haven't emitted the special get_pc helper function, do so now. */ 3775 if (get_pc_symbol_name[0] == 0) 3776 { 3777 int align; 3778 3779 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); 3780 text_section (); 3781 3782 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 3783 if (align > 0) 3784 ASM_OUTPUT_ALIGN (asm_out_file, align); 3785 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0); 3786 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file); 3787 } 3788 3789 /* Initialize every time through, since we can't easily 3790 know this to be permanent. */ 3791 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 3792 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); 3793 flag_pic = 0; 3794 3795 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, 3796 get_pc_symbol)); 3797 3798 flag_pic = orig_flag_pic; 3799 3800 /* Need to emit this whether or not we obey regdecls, 3801 since setjmp/longjmp can cause life info to screw up. 3802 ??? In the case where we don't obey regdecls, this is not sufficient 3803 since we may not fall out the bottom. */ 3804 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); 3805} 3806 3807/* Return 1 if RTX is a MEM which is known to be aligned to at 3808 least a DESIRED byte boundary. */ 3809 3810int 3811mem_min_alignment (rtx mem, int desired) 3812{ 3813 rtx addr, base, offset; 3814 3815 /* If it's not a MEM we can't accept it. */ 3816 if (GET_CODE (mem) != MEM) 3817 return 0; 3818 3819 addr = XEXP (mem, 0); 3820 base = offset = NULL_RTX; 3821 if (GET_CODE (addr) == PLUS) 3822 { 3823 if (GET_CODE (XEXP (addr, 0)) == REG) 3824 { 3825 base = XEXP (addr, 0); 3826 3827 /* What we are saying here is that if the base 3828 REG is aligned properly, the compiler will make 3829 sure any REG based index upon it will be so 3830 as well. */ 3831 if (GET_CODE (XEXP (addr, 1)) == CONST_INT) 3832 offset = XEXP (addr, 1); 3833 else 3834 offset = const0_rtx; 3835 } 3836 } 3837 else if (GET_CODE (addr) == REG) 3838 { 3839 base = addr; 3840 offset = const0_rtx; 3841 } 3842 3843 if (base != NULL_RTX) 3844 { 3845 int regno = REGNO (base); 3846 3847 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) 3848 { 3849 /* Check if the compiler has recorded some information 3850 about the alignment of the base REG. If reload has 3851 completed, we already matched with proper alignments. 3852 If not running global_alloc, reload might give us 3853 unaligned pointer to local stack though. */ 3854 if (((cfun != 0 3855 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) 3856 || (optimize && reload_completed)) 3857 && (INTVAL (offset) & (desired - 1)) == 0) 3858 return 1; 3859 } 3860 else 3861 { 3862 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) 3863 return 1; 3864 } 3865 } 3866 else if (! TARGET_UNALIGNED_DOUBLES 3867 || CONSTANT_P (addr) 3868 || GET_CODE (addr) == LO_SUM) 3869 { 3870 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES 3871 is true, in which case we can only assume that an access is aligned if 3872 it is to a constant address, or the address involves a LO_SUM. */ 3873 return 1; 3874 } 3875 3876 /* An obviously unaligned address. */ 3877 return 0; 3878} 3879 3880 3881/* Vectors to keep interesting information about registers where it can easily 3882 be got. We used to use the actual mode value as the bit number, but there 3883 are more than 32 modes now. Instead we use two tables: one indexed by 3884 hard register number, and one indexed by mode. */ 3885 3886/* The purpose of sparc_mode_class is to shrink the range of modes so that 3887 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is 3888 mapped into one sparc_mode_class mode. */ 3889 3890enum sparc_mode_class { 3891 S_MODE, D_MODE, T_MODE, O_MODE, 3892 SF_MODE, DF_MODE, TF_MODE, OF_MODE, 3893 CC_MODE, CCFP_MODE 3894}; 3895 3896/* Modes for single-word and smaller quantities. */ 3897#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) 3898 3899/* Modes for double-word and smaller quantities. */ 3900#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) 3901 3902/* Modes for quad-word and smaller quantities. */ 3903#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) 3904 3905/* Modes for 8-word and smaller quantities. */ 3906#define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) 3907 3908/* Modes for single-float quantities. We must allow any single word or 3909 smaller quantity. This is because the fix/float conversion instructions 3910 take integer inputs/outputs from the float registers. */ 3911#define SF_MODES (S_MODES) 3912 3913/* Modes for double-float and smaller quantities. */ 3914#define DF_MODES (S_MODES | D_MODES) 3915 3916/* Modes for double-float only quantities. */ 3917#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) 3918 3919/* Modes for quad-float only quantities. */ 3920#define TF_ONLY_MODES (1 << (int) TF_MODE) 3921 3922/* Modes for quad-float and smaller quantities. */ 3923#define TF_MODES (DF_MODES | TF_ONLY_MODES) 3924 3925/* Modes for quad-float and double-float quantities. */ 3926#define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) 3927 3928/* Modes for quad-float pair only quantities. */ 3929#define OF_ONLY_MODES (1 << (int) OF_MODE) 3930 3931/* Modes for quad-float pairs and smaller quantities. */ 3932#define OF_MODES (TF_MODES | OF_ONLY_MODES) 3933 3934#define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) 3935 3936/* Modes for condition codes. */ 3937#define CC_MODES (1 << (int) CC_MODE) 3938#define CCFP_MODES (1 << (int) CCFP_MODE) 3939 3940/* Value is 1 if register/mode pair is acceptable on sparc. 3941 The funny mixture of D and T modes is because integer operations 3942 do not specially operate on tetra quantities, so non-quad-aligned 3943 registers can hold quadword quantities (except %o4 and %i4 because 3944 they cross fixed registers). */ 3945 3946/* This points to either the 32 bit or the 64 bit version. */ 3947const int *hard_regno_mode_classes; 3948 3949static const int hard_32bit_mode_classes[] = { 3950 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 3951 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 3952 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 3953 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 3954 3955 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3956 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3957 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3958 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 3959 3960 /* FP regs f32 to f63. Only the even numbered registers actually exist, 3961 and none can hold SFmode/SImode values. */ 3962 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3963 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3964 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3965 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3966 3967 /* %fcc[0123] */ 3968 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 3969 3970 /* %icc */ 3971 CC_MODES 3972}; 3973 3974static const int hard_64bit_mode_classes[] = { 3975 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3976 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3977 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3978 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3979 3980 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3981 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3982 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3983 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 3984 3985 /* FP regs f32 to f63. Only the even numbered registers actually exist, 3986 and none can hold SFmode/SImode values. */ 3987 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3988 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3989 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3990 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3991 3992 /* %fcc[0123] */ 3993 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 3994 3995 /* %icc */ 3996 CC_MODES 3997}; 3998 3999int sparc_mode_class [NUM_MACHINE_MODES]; 4000 4001enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 4002 4003static void 4004sparc_init_modes (void) 4005{ 4006 int i; 4007 4008 for (i = 0; i < NUM_MACHINE_MODES; i++) 4009 { 4010 switch (GET_MODE_CLASS (i)) 4011 { 4012 case MODE_INT: 4013 case MODE_PARTIAL_INT: 4014 case MODE_COMPLEX_INT: 4015 if (GET_MODE_SIZE (i) <= 4) 4016 sparc_mode_class[i] = 1 << (int) S_MODE; 4017 else if (GET_MODE_SIZE (i) == 8) 4018 sparc_mode_class[i] = 1 << (int) D_MODE; 4019 else if (GET_MODE_SIZE (i) == 16) 4020 sparc_mode_class[i] = 1 << (int) T_MODE; 4021 else if (GET_MODE_SIZE (i) == 32) 4022 sparc_mode_class[i] = 1 << (int) O_MODE; 4023 else 4024 sparc_mode_class[i] = 0; 4025 break; 4026 case MODE_FLOAT: 4027 case MODE_COMPLEX_FLOAT: 4028 if (GET_MODE_SIZE (i) <= 4) 4029 sparc_mode_class[i] = 1 << (int) SF_MODE; 4030 else if (GET_MODE_SIZE (i) == 8) 4031 sparc_mode_class[i] = 1 << (int) DF_MODE; 4032 else if (GET_MODE_SIZE (i) == 16) 4033 sparc_mode_class[i] = 1 << (int) TF_MODE; 4034 else if (GET_MODE_SIZE (i) == 32) 4035 sparc_mode_class[i] = 1 << (int) OF_MODE; 4036 else 4037 sparc_mode_class[i] = 0; 4038 break; 4039 case MODE_CC: 4040 if (i == (int) CCFPmode || i == (int) CCFPEmode) 4041 sparc_mode_class[i] = 1 << (int) CCFP_MODE; 4042 else 4043 sparc_mode_class[i] = 1 << (int) CC_MODE; 4044 break; 4045 default: 4046 sparc_mode_class[i] = 0; 4047 break; 4048 } 4049 } 4050 4051 if (TARGET_ARCH64) 4052 hard_regno_mode_classes = hard_64bit_mode_classes; 4053 else 4054 hard_regno_mode_classes = hard_32bit_mode_classes; 4055 4056 /* Initialize the array used by REGNO_REG_CLASS. */ 4057 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4058 { 4059 if (i < 16 && TARGET_V8PLUS) 4060 sparc_regno_reg_class[i] = I64_REGS; 4061 else if (i < 32 || i == FRAME_POINTER_REGNUM) 4062 sparc_regno_reg_class[i] = GENERAL_REGS; 4063 else if (i < 64) 4064 sparc_regno_reg_class[i] = FP_REGS; 4065 else if (i < 96) 4066 sparc_regno_reg_class[i] = EXTRA_FP_REGS; 4067 else if (i < 100) 4068 sparc_regno_reg_class[i] = FPCC_REGS; 4069 else 4070 sparc_regno_reg_class[i] = NO_REGS; 4071 } 4072} 4073 4074/* Save non call used registers from LOW to HIGH at BASE+OFFSET. 4075 N_REGS is the number of 4-byte regs saved thus far. This applies even to 4076 v9 int regs as it simplifies the code. */ 4077 4078static int 4079save_regs (FILE *file, int low, int high, const char *base, 4080 int offset, int n_regs, HOST_WIDE_INT real_offset) 4081{ 4082 int i; 4083 4084 if (TARGET_ARCH64 && high <= 32) 4085 { 4086 for (i = low; i < high; i++) 4087 { 4088 if (regs_ever_live[i] && ! call_used_regs[i]) 4089 { 4090 fprintf (file, "\tstx\t%s, [%s+%d]\n", 4091 reg_names[i], base, offset + 4 * n_regs); 4092 if (dwarf2out_do_frame ()) 4093 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); 4094 n_regs += 2; 4095 } 4096 } 4097 } 4098 else 4099 { 4100 for (i = low; i < high; i += 2) 4101 { 4102 if (regs_ever_live[i] && ! call_used_regs[i]) 4103 { 4104 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 4105 { 4106 fprintf (file, "\tstd\t%s, [%s+%d]\n", 4107 reg_names[i], base, offset + 4 * n_regs); 4108 if (dwarf2out_do_frame ()) 4109 { 4110 char *l = dwarf2out_cfi_label (); 4111 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); 4112 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); 4113 } 4114 n_regs += 2; 4115 } 4116 else 4117 { 4118 fprintf (file, "\tst\t%s, [%s+%d]\n", 4119 reg_names[i], base, offset + 4 * n_regs); 4120 if (dwarf2out_do_frame ()) 4121 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); 4122 n_regs += 2; 4123 } 4124 } 4125 else 4126 { 4127 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 4128 { 4129 fprintf (file, "\tst\t%s, [%s+%d]\n", 4130 reg_names[i+1], base, offset + 4 * n_regs + 4); 4131 if (dwarf2out_do_frame ()) 4132 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); 4133 n_regs += 2; 4134 } 4135 } 4136 } 4137 } 4138 return n_regs; 4139} 4140 4141/* Restore non call used registers from LOW to HIGH at BASE+OFFSET. 4142 4143 N_REGS is the number of 4-byte regs saved thus far. This applies even to 4144 v9 int regs as it simplifies the code. */ 4145 4146static int 4147restore_regs (FILE *file, int low, int high, const char *base, 4148 int offset, int n_regs) 4149{ 4150 int i; 4151 4152 if (TARGET_ARCH64 && high <= 32) 4153 { 4154 for (i = low; i < high; i++) 4155 { 4156 if (regs_ever_live[i] && ! call_used_regs[i]) 4157 fprintf (file, "\tldx\t[%s+%d], %s\n", 4158 base, offset + 4 * n_regs, reg_names[i]), 4159 n_regs += 2; 4160 } 4161 } 4162 else 4163 { 4164 for (i = low; i < high; i += 2) 4165 { 4166 if (regs_ever_live[i] && ! call_used_regs[i]) 4167 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 4168 fprintf (file, "\tldd\t[%s+%d], %s\n", 4169 base, offset + 4 * n_regs, reg_names[i]), 4170 n_regs += 2; 4171 else 4172 fprintf (file, "\tld\t[%s+%d], %s\n", 4173 base, offset + 4 * n_regs, reg_names[i]), 4174 n_regs += 2; 4175 else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 4176 fprintf (file, "\tld\t[%s+%d], %s\n", 4177 base, offset + 4 * n_regs + 4, reg_names[i+1]), 4178 n_regs += 2; 4179 } 4180 } 4181 return n_regs; 4182} 4183 4184/* Compute the frame size required by the function. This function is called 4185 during the reload pass and also by output_function_prologue(). */ 4186 4187HOST_WIDE_INT 4188compute_frame_size (HOST_WIDE_INT size, int leaf_function) 4189{ 4190 int n_regs = 0, i; 4191 int outgoing_args_size = (current_function_outgoing_args_size 4192 + REG_PARM_STACK_SPACE (current_function_decl)); 4193 4194 /* N_REGS is the number of 4-byte regs saved thus far. This applies 4195 even to v9 int regs to be consistent with save_regs/restore_regs. */ 4196 4197 if (TARGET_ARCH64) 4198 { 4199 for (i = 0; i < 8; i++) 4200 if (regs_ever_live[i] && ! call_used_regs[i]) 4201 n_regs += 2; 4202 } 4203 else 4204 { 4205 for (i = 0; i < 8; i += 2) 4206 if ((regs_ever_live[i] && ! call_used_regs[i]) 4207 || (regs_ever_live[i+1] && ! call_used_regs[i+1])) 4208 n_regs += 2; 4209 } 4210 4211 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) 4212 if ((regs_ever_live[i] && ! call_used_regs[i]) 4213 || (regs_ever_live[i+1] && ! call_used_regs[i+1])) 4214 n_regs += 2; 4215 4216 /* Set up values for use in `function_epilogue'. */ 4217 num_gfregs = n_regs; 4218 4219 if (leaf_function && n_regs == 0 4220 && size == 0 && current_function_outgoing_args_size == 0) 4221 { 4222 actual_fsize = apparent_fsize = 0; 4223 } 4224 else 4225 { 4226 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ 4227 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8; 4228 apparent_fsize += n_regs * 4; 4229 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); 4230 } 4231 4232 /* Make sure nothing can clobber our register windows. 4233 If a SAVE must be done, or there is a stack-local variable, 4234 the register window area must be allocated. 4235 ??? For v8 we apparently need an additional 8 bytes of reserved space. */ 4236 if (leaf_function == 0 || size > 0) 4237 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); 4238 4239 return SPARC_STACK_ALIGN (actual_fsize); 4240} 4241 4242/* Build big number NUM in register REG and output the result to FILE. 4243 REG is guaranteed to be the only clobbered register. The function 4244 will very likely emit several instructions, so it must not be called 4245 from within a delay slot. */ 4246 4247static void 4248build_big_number (FILE *file, HOST_WIDE_INT num, const char *reg) 4249{ 4250#if HOST_BITS_PER_WIDE_INT == 64 4251 HOST_WIDE_INT high_bits = (num >> 32) & 0xffffffff; 4252 4253 if (high_bits == 0 4254#else 4255 if (num >= 0 4256#endif 4257 || ! TARGET_ARCH64) 4258 { 4259 /* We don't use the 'set' macro because it appears to be broken 4260 in the Solaris 7 assembler. */ 4261 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n", 4262 num, reg); 4263 if ((num & 0x3ff) != 0) 4264 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n", 4265 reg, num, reg); 4266 } 4267#if HOST_BITS_PER_WIDE_INT == 64 4268 else if (high_bits == 0xffffffff) /* && TARGET_ARCH64 */ 4269#else 4270 else /* num < 0 && TARGET_ARCH64 */ 4271#endif 4272 { 4273 /* Sethi does not sign extend, so we must use a little trickery 4274 to use it for negative numbers. Invert the constant before 4275 loading it in, then use xor immediate to invert the loaded bits 4276 (along with the upper 32 bits) to the desired constant. This 4277 works because the sethi and immediate fields overlap. */ 4278 HOST_WIDE_INT inv = ~num; 4279 HOST_WIDE_INT low = -0x400 + (num & 0x3ff); 4280 4281 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n", 4282 inv, reg); 4283 fprintf (file, "\txor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n", 4284 reg, low, reg); 4285 } 4286#if HOST_BITS_PER_WIDE_INT == 64 4287 else /* TARGET_ARCH64 */ 4288 { 4289 /* We don't use the 'setx' macro because if requires a scratch register. 4290 This is the translation of sparc_emit_set_const64_longway into asm. 4291 Hopefully we will soon have prologue/epilogue emitted as RTL. */ 4292 HOST_WIDE_INT low1 = (num >> (32 - 12)) & 0xfff; 4293 HOST_WIDE_INT low2 = (num >> (32 - 12 - 12)) & 0xfff; 4294 HOST_WIDE_INT low3 = (num >> (32 - 12 - 12 - 8)) & 0x0ff; 4295 int to_shift = 12; 4296 4297 /* We don't use the 'set' macro because it appears to be broken 4298 in the Solaris 7 assembler. */ 4299 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n", 4300 high_bits, reg); 4301 if ((high_bits & 0x3ff) != 0) 4302 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n", 4303 reg, high_bits, reg); 4304 4305 if (low1 != 0) 4306 { 4307 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg); 4308 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n", 4309 reg, low1, reg); 4310 to_shift = 12; 4311 } 4312 else 4313 { 4314 to_shift += 12; 4315 } 4316 if (low2 != 0) 4317 { 4318 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg); 4319 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n", 4320 reg, low2, reg); 4321 to_shift = 8; 4322 } 4323 else 4324 { 4325 to_shift += 8; 4326 } 4327 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg); 4328 if (low3 != 0) 4329 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n", 4330 reg, low3, reg); 4331 } 4332#endif 4333} 4334 4335/* Output any necessary .register pseudo-ops. */ 4336void 4337sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED) 4338{ 4339#ifdef HAVE_AS_REGISTER_PSEUDO_OP 4340 int i; 4341 4342 if (TARGET_ARCH32) 4343 return; 4344 4345 /* Check if %g[2367] were used without 4346 .register being printed for them already. */ 4347 for (i = 2; i < 8; i++) 4348 { 4349 if (regs_ever_live [i] 4350 && ! sparc_hard_reg_printed [i]) 4351 { 4352 sparc_hard_reg_printed [i] = 1; 4353 fprintf (file, "\t.register\t%%g%d, #scratch\n", i); 4354 } 4355 if (i == 3) i = 5; 4356 } 4357#endif 4358} 4359 4360/* This function generates the assembly code for function entry. 4361 FILE is a stdio stream to output the code to. 4362 SIZE is an int: how many units of temporary storage to allocate. 4363 Refer to the array `regs_ever_live' to determine which registers 4364 to save; `regs_ever_live[I]' is nonzero if register number I 4365 is ever used in the function. This macro is responsible for 4366 knowing which registers should not be saved even if used. */ 4367 4368/* On SPARC, move-double insns between fpu and cpu need an 8-byte block 4369 of memory. If any fpu reg is used in the function, we allocate 4370 such a block here, at the bottom of the frame, just in case it's needed. 4371 4372 If this function is a leaf procedure, then we may choose not 4373 to do a "save" insn. The decision about whether or not 4374 to do this is made in regclass.c. */ 4375 4376static void 4377sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size) 4378{ 4379 if (TARGET_FLAT) 4380 sparc_flat_function_prologue (file, size); 4381 else 4382 sparc_nonflat_function_prologue (file, size, 4383 current_function_uses_only_leaf_regs); 4384} 4385 4386/* Output code for the function prologue. */ 4387 4388static void 4389sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size, 4390 int leaf_function) 4391{ 4392 sparc_output_scratch_registers (file); 4393 4394 /* Need to use actual_fsize, since we are also allocating 4395 space for our callee (and our own register save area). */ 4396 actual_fsize = compute_frame_size (size, leaf_function); 4397 4398 if (leaf_function) 4399 { 4400 frame_base_name = "%sp"; 4401 frame_base_offset = actual_fsize + SPARC_STACK_BIAS; 4402 } 4403 else 4404 { 4405 frame_base_name = "%fp"; 4406 frame_base_offset = SPARC_STACK_BIAS; 4407 } 4408 4409 /* This is only for the human reader. */ 4410 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); 4411 4412 if (actual_fsize == 0) 4413 /* do nothing. */ ; 4414 else if (! leaf_function) 4415 { 4416 if (actual_fsize <= 4096) 4417 fprintf (file, "\tsave\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", 4418 actual_fsize); 4419 else if (actual_fsize <= 8192) 4420 { 4421 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); 4422 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", 4423 actual_fsize - 4096); 4424 } 4425 else 4426 { 4427 build_big_number (file, -actual_fsize, "%g1"); 4428 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); 4429 } 4430 } 4431 else /* leaf function */ 4432 { 4433 if (actual_fsize <= 4096) 4434 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", 4435 actual_fsize); 4436 else if (actual_fsize <= 8192) 4437 { 4438 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); 4439 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", 4440 actual_fsize - 4096); 4441 } 4442 else 4443 { 4444 build_big_number (file, -actual_fsize, "%g1"); 4445 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); 4446 } 4447 } 4448 4449 if (dwarf2out_do_frame () && actual_fsize) 4450 { 4451 char *label = dwarf2out_cfi_label (); 4452 4453 /* The canonical frame address refers to the top of the frame. */ 4454 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM 4455 : HARD_FRAME_POINTER_REGNUM), 4456 frame_base_offset); 4457 4458 if (! leaf_function) 4459 { 4460 /* Note the register window save. This tells the unwinder that 4461 it needs to restore the window registers from the previous 4462 frame's window save area at 0(cfa). */ 4463 dwarf2out_window_save (label); 4464 4465 /* The return address (-8) is now in %i7. */ 4466 dwarf2out_return_reg (label, 31); 4467 } 4468 } 4469 4470 /* If doing anything with PIC, do it now. */ 4471 if (! flag_pic) 4472 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); 4473 4474 /* Call saved registers are saved just above the outgoing argument area. */ 4475 if (num_gfregs) 4476 { 4477 HOST_WIDE_INT offset, real_offset; 4478 int n_regs; 4479 const char *base; 4480 4481 real_offset = -apparent_fsize; 4482 offset = -apparent_fsize + frame_base_offset; 4483 if (offset < -4096 || offset + num_gfregs * 4 > 4096) 4484 { 4485 /* ??? This might be optimized a little as %g1 might already have a 4486 value close enough that a single add insn will do. */ 4487 /* ??? Although, all of this is probably only a temporary fix 4488 because if %g1 can hold a function result, then 4489 output_function_epilogue will lose (the result will get 4490 clobbered). */ 4491 build_big_number (file, offset, "%g1"); 4492 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); 4493 base = "%g1"; 4494 offset = 0; 4495 } 4496 else 4497 { 4498 base = frame_base_name; 4499 } 4500 4501 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); 4502 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, 4503 real_offset); 4504 } 4505} 4506 4507/* Output code to restore any call saved registers. */ 4508 4509static void 4510output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED) 4511{ 4512 HOST_WIDE_INT offset; 4513 int n_regs; 4514 const char *base; 4515 4516 offset = -apparent_fsize + frame_base_offset; 4517 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) 4518 { 4519 build_big_number (file, offset, "%g1"); 4520 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); 4521 base = "%g1"; 4522 offset = 0; 4523 } 4524 else 4525 { 4526 base = frame_base_name; 4527 } 4528 4529 n_regs = restore_regs (file, 0, 8, base, offset, 0); 4530 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); 4531} 4532 4533/* This function generates the assembly code for function exit, 4534 on machines that need it. 4535 4536 The function epilogue should not depend on the current stack pointer! 4537 It should use the frame pointer only. This is mandatory because 4538 of alloca; we also take advantage of it to omit stack adjustments 4539 before returning. */ 4540 4541static void 4542sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size) 4543{ 4544 if (TARGET_FLAT) 4545 sparc_flat_function_epilogue (file, size); 4546 else 4547 sparc_nonflat_function_epilogue (file, size, 4548 current_function_uses_only_leaf_regs); 4549} 4550 4551/* Output code for the function epilogue. */ 4552 4553static void 4554sparc_nonflat_function_epilogue (FILE *file, 4555 HOST_WIDE_INT size ATTRIBUTE_UNUSED, 4556 int leaf_function) 4557{ 4558 const char *ret; 4559 4560 if (current_function_epilogue_delay_list == 0) 4561 { 4562 /* If code does not drop into the epilogue, we need 4563 do nothing except output pending case vectors. 4564 4565 We have to still output a dummy nop for the sake of 4566 sane backtraces. Otherwise, if the last two instructions 4567 of a function were call foo; dslot; this can make the return 4568 PC of foo (ie. address of call instruction plus 8) point to 4569 the first instruction in the next function. */ 4570 rtx insn, last_real_insn; 4571 4572 insn = get_last_insn (); 4573 4574 last_real_insn = prev_real_insn (insn); 4575 if (last_real_insn 4576 && GET_CODE (last_real_insn) == INSN 4577 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE) 4578 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0); 4579 4580 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN) 4581 fputs("\tnop\n", file); 4582 4583 if (GET_CODE (insn) == NOTE) 4584 insn = prev_nonnote_insn (insn); 4585 if (insn && GET_CODE (insn) == BARRIER) 4586 goto output_vectors; 4587 } 4588 4589 if (num_gfregs) 4590 output_restore_regs (file, leaf_function); 4591 4592 /* Work out how to skip the caller's unimp instruction if required. */ 4593 if (leaf_function) 4594 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); 4595 else 4596 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); 4597 4598 if (! leaf_function) 4599 { 4600 if (current_function_calls_eh_return) 4601 { 4602 if (current_function_epilogue_delay_list) 4603 abort (); 4604 if (SKIP_CALLERS_UNIMP_P) 4605 abort (); 4606 4607 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file); 4608 } 4609 /* If we wound up with things in our delay slot, flush them here. */ 4610 else if (current_function_epilogue_delay_list) 4611 { 4612 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0)); 4613 4614 if (TARGET_V9 && ! epilogue_renumber (&delay, 1)) 4615 { 4616 epilogue_renumber (&delay, 0); 4617 fputs (SKIP_CALLERS_UNIMP_P 4618 ? "\treturn\t%i7+12\n" 4619 : "\treturn\t%i7+8\n", file); 4620 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), 4621 file, 1, 0, 0, NULL); 4622 } 4623 else 4624 { 4625 rtx insn, src; 4626 4627 if (GET_CODE (delay) != SET) 4628 abort(); 4629 4630 src = SET_SRC (delay); 4631 if (GET_CODE (src) == ASHIFT) 4632 { 4633 if (XEXP (src, 1) != const1_rtx) 4634 abort(); 4635 SET_SRC (delay) 4636 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0), 4637 XEXP (src, 0)); 4638 } 4639 4640 insn = gen_rtx_PARALLEL (VOIDmode, 4641 gen_rtvec (2, delay, 4642 gen_rtx_RETURN (VOIDmode))); 4643 insn = emit_jump_insn (insn); 4644 4645 sparc_emitting_epilogue = true; 4646 final_scan_insn (insn, file, 1, 0, 1, NULL); 4647 sparc_emitting_epilogue = false; 4648 } 4649 } 4650 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) 4651 fputs ("\treturn\t%i7+8\n\tnop\n", file); 4652 else 4653 fprintf (file, "\t%s\n\trestore\n", ret); 4654 } 4655 /* All of the following cases are for leaf functions. */ 4656 else if (current_function_calls_eh_return) 4657 abort (); 4658 else if (current_function_epilogue_delay_list) 4659 { 4660 /* eligible_for_epilogue_delay_slot ensures that if this is a 4661 leaf function, then we will only have insn in the delay slot 4662 if the frame size is zero, thus no adjust for the stack is 4663 needed here. */ 4664 if (actual_fsize != 0) 4665 abort (); 4666 fprintf (file, "\t%s\n", ret); 4667 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), 4668 file, 1, 0, 1, NULL); 4669 } 4670 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to 4671 avoid generating confusing assembly language output. */ 4672 else if (actual_fsize == 0) 4673 fprintf (file, "\t%s\n\tnop\n", ret); 4674 else if (actual_fsize <= 4096) 4675 fprintf (file, "\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", 4676 ret, actual_fsize); 4677 else if (actual_fsize <= 8192) 4678 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", 4679 ret, actual_fsize - 4096); 4680 else 4681 { 4682 build_big_number (file, actual_fsize, "%g1"); 4683 fprintf (file, "\t%s\n\tadd\t%%sp, %%g1, %%sp\n", ret); 4684 } 4685 4686 output_vectors: 4687 sparc_output_deferred_case_vectors (); 4688} 4689 4690/* Output a sibling call. */ 4691 4692const char * 4693output_sibcall (rtx insn, rtx call_operand) 4694{ 4695 int leaf_regs = current_function_uses_only_leaf_regs; 4696 rtx operands[3]; 4697 int delay_slot = dbr_sequence_length () > 0; 4698 4699 if (num_gfregs) 4700 { 4701 /* Call to restore global regs might clobber 4702 the delay slot. Instead of checking for this 4703 output the delay slot now. */ 4704 if (delay_slot) 4705 { 4706 rtx delay = NEXT_INSN (insn); 4707 4708 if (! delay) 4709 abort (); 4710 4711 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL); 4712 PATTERN (delay) = gen_blockage (); 4713 INSN_CODE (delay) = -1; 4714 delay_slot = 0; 4715 } 4716 output_restore_regs (asm_out_file, leaf_regs); 4717 } 4718 4719 operands[0] = call_operand; 4720 4721 if (leaf_regs) 4722 { 4723#ifdef HAVE_AS_RELAX_OPTION 4724 /* If as and ld are relaxing tail call insns into branch always, 4725 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can 4726 be optimized. With sethi/jmpl as nor ld has no easy way how to 4727 find out if somebody does not branch between the sethi and jmpl. */ 4728 int spare_slot = 0; 4729#else 4730 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic); 4731#endif 4732 HOST_WIDE_INT size = 0; 4733 4734 if ((actual_fsize || ! spare_slot) && delay_slot) 4735 { 4736 rtx delay = NEXT_INSN (insn); 4737 4738 if (! delay) 4739 abort (); 4740 4741 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL); 4742 PATTERN (delay) = gen_blockage (); 4743 INSN_CODE (delay) = -1; 4744 delay_slot = 0; 4745 } 4746 if (actual_fsize) 4747 { 4748 if (actual_fsize <= 4096) 4749 size = actual_fsize; 4750 else if (actual_fsize <= 8192) 4751 { 4752 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file); 4753 size = actual_fsize - 4096; 4754 } 4755 else 4756 { 4757 build_big_number (asm_out_file, actual_fsize, "%g1"); 4758 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file); 4759 } 4760 } 4761 if (spare_slot) 4762 { 4763 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands); 4764 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands); 4765 if (size) 4766 fprintf (asm_out_file, "\t sub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size); 4767 else if (! delay_slot) 4768 fputs ("\t nop\n", asm_out_file); 4769 } 4770 else 4771 { 4772 if (size) 4773 fprintf (asm_out_file, "\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size); 4774 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize 4775 it into branch if possible. */ 4776 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands); 4777 output_asm_insn ("call\t%a0, 0", operands); 4778 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands); 4779 } 4780 return ""; 4781 } 4782 4783 output_asm_insn ("call\t%a0, 0", operands); 4784 if (delay_slot) 4785 { 4786 rtx delay = NEXT_INSN (insn), pat; 4787 4788 if (! delay) 4789 abort (); 4790 4791 pat = PATTERN (delay); 4792 if (GET_CODE (pat) != SET) 4793 abort (); 4794 4795 operands[0] = SET_DEST (pat); 4796 pat = SET_SRC (pat); 4797 switch (GET_CODE (pat)) 4798 { 4799 case PLUS: 4800 operands[1] = XEXP (pat, 0); 4801 operands[2] = XEXP (pat, 1); 4802 output_asm_insn (" restore %r1, %2, %Y0", operands); 4803 break; 4804 case LO_SUM: 4805 operands[1] = XEXP (pat, 0); 4806 operands[2] = XEXP (pat, 1); 4807 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); 4808 break; 4809 case ASHIFT: 4810 operands[1] = XEXP (pat, 0); 4811 output_asm_insn (" restore %r1, %r1, %Y0", operands); 4812 break; 4813 default: 4814 operands[1] = pat; 4815 output_asm_insn (" restore %%g0, %1, %Y0", operands); 4816 break; 4817 } 4818 PATTERN (delay) = gen_blockage (); 4819 INSN_CODE (delay) = -1; 4820 } 4821 else 4822 fputs ("\t restore\n", asm_out_file); 4823 return ""; 4824} 4825 4826/* Functions for handling argument passing. 4827 4828 For v8 the first six args are normally in registers and the rest are 4829 pushed. Any arg that starts within the first 6 words is at least 4830 partially passed in a register unless its data type forbids. 4831 4832 For v9, the argument registers are laid out as an array of 16 elements 4833 and arguments are added sequentially. The first 6 int args and up to the 4834 first 16 fp args (depending on size) are passed in regs. 4835 4836 Slot Stack Integral Float Float in structure Double Long Double 4837 ---- ----- -------- ----- ------------------ ------ ----------- 4838 15 [SP+248] %f31 %f30,%f31 %d30 4839 14 [SP+240] %f29 %f28,%f29 %d28 %q28 4840 13 [SP+232] %f27 %f26,%f27 %d26 4841 12 [SP+224] %f25 %f24,%f25 %d24 %q24 4842 11 [SP+216] %f23 %f22,%f23 %d22 4843 10 [SP+208] %f21 %f20,%f21 %d20 %q20 4844 9 [SP+200] %f19 %f18,%f19 %d18 4845 8 [SP+192] %f17 %f16,%f17 %d16 %q16 4846 7 [SP+184] %f15 %f14,%f15 %d14 4847 6 [SP+176] %f13 %f12,%f13 %d12 %q12 4848 5 [SP+168] %o5 %f11 %f10,%f11 %d10 4849 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 4850 3 [SP+152] %o3 %f7 %f6,%f7 %d6 4851 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 4852 1 [SP+136] %o1 %f3 %f2,%f3 %d2 4853 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 4854 4855 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. 4856 4857 Integral arguments are always passed as 64 bit quantities appropriately 4858 extended. 4859 4860 Passing of floating point values is handled as follows. 4861 If a prototype is in scope: 4862 If the value is in a named argument (i.e. not a stdarg function or a 4863 value not part of the `...') then the value is passed in the appropriate 4864 fp reg. 4865 If the value is part of the `...' and is passed in one of the first 6 4866 slots then the value is passed in the appropriate int reg. 4867 If the value is part of the `...' and is not passed in one of the first 6 4868 slots then the value is passed in memory. 4869 If a prototype is not in scope: 4870 If the value is one of the first 6 arguments the value is passed in the 4871 appropriate integer reg and the appropriate fp reg. 4872 If the value is not one of the first 6 arguments the value is passed in 4873 the appropriate fp reg and in memory. 4874 */ 4875 4876/* Maximum number of int regs for args. */ 4877#define SPARC_INT_ARG_MAX 6 4878/* Maximum number of fp regs for args. */ 4879#define SPARC_FP_ARG_MAX 16 4880 4881#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 4882 4883/* Handle the INIT_CUMULATIVE_ARGS macro. 4884 Initialize a variable CUM of type CUMULATIVE_ARGS 4885 for a call to a function whose data type is FNTYPE. 4886 For a library call, FNTYPE is 0. */ 4887 4888void 4889init_cumulative_args (struct sparc_args *cum, tree fntype, 4890 rtx libname ATTRIBUTE_UNUSED, 4891 tree fndecl ATTRIBUTE_UNUSED) 4892{ 4893 cum->words = 0; 4894 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); 4895 cum->libcall_p = fntype == 0; 4896} 4897 4898/* Scan the record type TYPE and return the following predicates: 4899 - INTREGS_P: the record contains at least one field or sub-field 4900 that is eligible for promotion in integer registers. 4901 - FP_REGS_P: the record contains at least one field or sub-field 4902 that is eligible for promotion in floating-point registers. 4903 - PACKED_P: the record contains at least one field that is packed. 4904 4905 Sub-fields are not taken into account for the PACKED_P predicate. */ 4906 4907static void 4908scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p) 4909{ 4910 tree field; 4911 4912 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4913 { 4914 if (TREE_CODE (field) == FIELD_DECL) 4915 { 4916 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 4917 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0); 4918 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU) 4919 *fpregs_p = 1; 4920 else 4921 *intregs_p = 1; 4922 4923 if (packed_p && DECL_PACKED (field)) 4924 *packed_p = 1; 4925 } 4926 } 4927} 4928 4929/* Compute the slot number to pass an argument in. 4930 Return the slot number or -1 if passing on the stack. 4931 4932 CUM is a variable of type CUMULATIVE_ARGS which gives info about 4933 the preceding args and about the function being called. 4934 MODE is the argument's machine mode. 4935 TYPE is the data type of the argument (as a tree). 4936 This is null for libcalls where that information may 4937 not be available. 4938 NAMED is nonzero if this argument is a named parameter 4939 (otherwise it is an extra parameter matching an ellipsis). 4940 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. 4941 *PREGNO records the register number to use if scalar type. 4942 *PPADDING records the amount of padding needed in words. */ 4943 4944static int 4945function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode, 4946 tree type, int named, int incoming_p, 4947 int *pregno, int *ppadding) 4948{ 4949 int regbase = (incoming_p 4950 ? SPARC_INCOMING_INT_ARG_FIRST 4951 : SPARC_OUTGOING_INT_ARG_FIRST); 4952 int slotno = cum->words; 4953 int regno; 4954 4955 *ppadding = 0; 4956 4957 if (type != 0 && TREE_ADDRESSABLE (type)) 4958 return -1; 4959 if (TARGET_ARCH32 4960 && type != 0 && mode == BLKmode 4961 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) 4962 return -1; 4963 4964 switch (mode) 4965 { 4966 case VOIDmode : 4967 /* MODE is VOIDmode when generating the actual call. 4968 See emit_call_1. */ 4969 return -1; 4970 4971 case TImode : case CTImode : 4972 if (TARGET_ARCH64 && (slotno & 1) != 0) 4973 slotno++, *ppadding = 1; 4974 /* fallthrough */ 4975 4976 case QImode : case CQImode : 4977 case HImode : case CHImode : 4978 case SImode : case CSImode : 4979 case DImode : case CDImode : 4980 if (slotno >= SPARC_INT_ARG_MAX) 4981 return -1; 4982 regno = regbase + slotno; 4983 break; 4984 4985 case TFmode : case TCmode : 4986 if (TARGET_ARCH64 && (slotno & 1) != 0) 4987 slotno++, *ppadding = 1; 4988 /* fallthrough */ 4989 4990 case SFmode : case SCmode : 4991 case DFmode : case DCmode : 4992 if (TARGET_ARCH32) 4993 { 4994 if (slotno >= SPARC_INT_ARG_MAX) 4995 return -1; 4996 regno = regbase + slotno; 4997 } 4998 else 4999 { 5000 if (TARGET_FPU && named) 5001 { 5002 if (slotno >= SPARC_FP_ARG_MAX) 5003 return -1; 5004 regno = SPARC_FP_ARG_FIRST + slotno * 2; 5005 if (mode == SFmode) 5006 regno++; 5007 } 5008 else 5009 { 5010 if (slotno >= SPARC_INT_ARG_MAX) 5011 return -1; 5012 regno = regbase + slotno; 5013 } 5014 } 5015 break; 5016 5017 case BLKmode : 5018 /* For sparc64, objects requiring 16 byte alignment get it. */ 5019 if (TARGET_ARCH64) 5020 { 5021 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) 5022 slotno++, *ppadding = 1; 5023 } 5024 5025 if (TARGET_ARCH32 5026 || (type && TREE_CODE (type) == UNION_TYPE)) 5027 { 5028 if (slotno >= SPARC_INT_ARG_MAX) 5029 return -1; 5030 regno = regbase + slotno; 5031 } 5032 else 5033 { 5034 int intregs_p = 0, fpregs_p = 0, packed_p = 0; 5035 5036 /* First see what kinds of registers we would need. */ 5037 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p); 5038 5039 /* The ABI obviously doesn't specify how packed structures 5040 are passed. These are defined to be passed in int regs 5041 if possible, otherwise memory. */ 5042 if (packed_p || !named) 5043 fpregs_p = 0, intregs_p = 1; 5044 5045 /* If all arg slots are filled, then must pass on stack. */ 5046 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) 5047 return -1; 5048 /* If there are only int args and all int arg slots are filled, 5049 then must pass on stack. */ 5050 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) 5051 return -1; 5052 /* Note that even if all int arg slots are filled, fp members may 5053 still be passed in regs if such regs are available. 5054 *PREGNO isn't set because there may be more than one, it's up 5055 to the caller to compute them. */ 5056 return slotno; 5057 } 5058 break; 5059 5060 default : 5061 abort (); 5062 } 5063 5064 *pregno = regno; 5065 return slotno; 5066} 5067 5068/* Handle recursive register counting for structure field layout. */ 5069 5070struct function_arg_record_value_parms 5071{ 5072 rtx ret; /* return expression being built. */ 5073 int slotno; /* slot number of the argument. */ 5074 int named; /* whether the argument is named. */ 5075 int regbase; /* regno of the base register. */ 5076 int stack; /* 1 if part of the argument is on the stack. */ 5077 int intoffset; /* offset of the first pending integer field. */ 5078 unsigned int nregs; /* number of words passed in registers. */ 5079}; 5080 5081static void function_arg_record_value_3 5082 (HOST_WIDE_INT, struct function_arg_record_value_parms *); 5083static void function_arg_record_value_2 5084 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool); 5085static void function_arg_record_value_1 5086 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool); 5087static rtx function_arg_record_value (tree, enum machine_mode, int, int, int); 5088static rtx function_arg_union_value (int, enum machine_mode, int, int); 5089 5090/* A subroutine of function_arg_record_value. Traverse the structure 5091 recursively and determine how many registers will be required. */ 5092 5093static void 5094function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos, 5095 struct function_arg_record_value_parms *parms, 5096 bool packed_p) 5097{ 5098 tree field; 5099 5100 /* We need to compute how many registers are needed so we can 5101 allocate the PARALLEL but before we can do that we need to know 5102 whether there are any packed fields. The ABI obviously doesn't 5103 specify how structures are passed in this case, so they are 5104 defined to be passed in int regs if possible, otherwise memory, 5105 regardless of whether there are fp values present. */ 5106 5107 if (! packed_p) 5108 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 5109 { 5110 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 5111 { 5112 packed_p = true; 5113 break; 5114 } 5115 } 5116 5117 /* Compute how many registers we need. */ 5118 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 5119 { 5120 if (TREE_CODE (field) == FIELD_DECL) 5121 { 5122 HOST_WIDE_INT bitpos = startbitpos; 5123 5124 if (DECL_SIZE (field) != 0 5125 && host_integerp (bit_position (field), 1)) 5126 bitpos += int_bit_position (field); 5127 5128 /* ??? FIXME: else assume zero offset. */ 5129 5130 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 5131 function_arg_record_value_1 (TREE_TYPE (field), 5132 bitpos, 5133 parms, 5134 packed_p); 5135 else if (FLOAT_TYPE_P (TREE_TYPE (field)) 5136 && TARGET_FPU 5137 && parms->named 5138 && ! packed_p) 5139 { 5140 if (parms->intoffset != -1) 5141 { 5142 unsigned int startbit, endbit; 5143 int intslots, this_slotno; 5144 5145 startbit = parms->intoffset & -BITS_PER_WORD; 5146 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; 5147 5148 intslots = (endbit - startbit) / BITS_PER_WORD; 5149 this_slotno = parms->slotno + parms->intoffset 5150 / BITS_PER_WORD; 5151 5152 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) 5153 { 5154 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); 5155 /* We need to pass this field on the stack. */ 5156 parms->stack = 1; 5157 } 5158 5159 parms->nregs += intslots; 5160 parms->intoffset = -1; 5161 } 5162 5163 /* There's no need to check this_slotno < SPARC_FP_ARG MAX. 5164 If it wasn't true we wouldn't be here. */ 5165 parms->nregs += 1; 5166 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 5167 parms->nregs += 1; 5168 } 5169 else 5170 { 5171 if (parms->intoffset == -1) 5172 parms->intoffset = bitpos; 5173 } 5174 } 5175 } 5176} 5177 5178/* A subroutine of function_arg_record_value. Assign the bits of the 5179 structure between parms->intoffset and bitpos to integer registers. */ 5180 5181static void 5182function_arg_record_value_3 (HOST_WIDE_INT bitpos, 5183 struct function_arg_record_value_parms *parms) 5184{ 5185 enum machine_mode mode; 5186 unsigned int regno; 5187 unsigned int startbit, endbit; 5188 int this_slotno, intslots, intoffset; 5189 rtx reg; 5190 5191 if (parms->intoffset == -1) 5192 return; 5193 5194 intoffset = parms->intoffset; 5195 parms->intoffset = -1; 5196 5197 startbit = intoffset & -BITS_PER_WORD; 5198 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; 5199 intslots = (endbit - startbit) / BITS_PER_WORD; 5200 this_slotno = parms->slotno + intoffset / BITS_PER_WORD; 5201 5202 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); 5203 if (intslots <= 0) 5204 return; 5205 5206 /* If this is the trailing part of a word, only load that much into 5207 the register. Otherwise load the whole register. Note that in 5208 the latter case we may pick up unwanted bits. It's not a problem 5209 at the moment but may wish to revisit. */ 5210 5211 if (intoffset % BITS_PER_WORD != 0) 5212 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, 5213 MODE_INT, 0); 5214 else 5215 mode = word_mode; 5216 5217 intoffset /= BITS_PER_UNIT; 5218 do 5219 { 5220 regno = parms->regbase + this_slotno; 5221 reg = gen_rtx_REG (mode, regno); 5222 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 5223 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); 5224 5225 this_slotno += 1; 5226 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; 5227 mode = word_mode; 5228 parms->nregs += 1; 5229 intslots -= 1; 5230 } 5231 while (intslots > 0); 5232} 5233 5234/* A subroutine of function_arg_record_value. Traverse the structure 5235 recursively and assign bits to floating point registers. Track which 5236 bits in between need integer registers; invoke function_arg_record_value_3 5237 to make that happen. */ 5238 5239static void 5240function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos, 5241 struct function_arg_record_value_parms *parms, 5242 bool packed_p) 5243{ 5244 tree field; 5245 5246 if (! packed_p) 5247 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 5248 { 5249 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 5250 { 5251 packed_p = true; 5252 break; 5253 } 5254 } 5255 5256 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 5257 { 5258 if (TREE_CODE (field) == FIELD_DECL) 5259 { 5260 HOST_WIDE_INT bitpos = startbitpos; 5261 5262 if (DECL_SIZE (field) != 0 5263 && host_integerp (bit_position (field), 1)) 5264 bitpos += int_bit_position (field); 5265 5266 /* ??? FIXME: else assume zero offset. */ 5267 5268 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 5269 function_arg_record_value_2 (TREE_TYPE (field), 5270 bitpos, 5271 parms, 5272 packed_p); 5273 else if (FLOAT_TYPE_P (TREE_TYPE (field)) 5274 && TARGET_FPU 5275 && parms->named 5276 && ! packed_p) 5277 { 5278 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; 5279 int regno; 5280 enum machine_mode mode = DECL_MODE (field); 5281 rtx reg; 5282 5283 function_arg_record_value_3 (bitpos, parms); 5284 regno = SPARC_FP_ARG_FIRST + this_slotno * 2 5285 + ((mode == SFmode || mode == SCmode) 5286 && (bitpos & 32) != 0); 5287 switch (mode) 5288 { 5289 case SCmode: mode = SFmode; break; 5290 case DCmode: mode = DFmode; break; 5291 case TCmode: mode = TFmode; break; 5292 default: break; 5293 } 5294 reg = gen_rtx_REG (mode, regno); 5295 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 5296 = gen_rtx_EXPR_LIST (VOIDmode, reg, 5297 GEN_INT (bitpos / BITS_PER_UNIT)); 5298 parms->nregs += 1; 5299 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 5300 { 5301 regno += GET_MODE_SIZE (mode) / 4; 5302 reg = gen_rtx_REG (mode, regno); 5303 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 5304 = gen_rtx_EXPR_LIST (VOIDmode, reg, 5305 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode)) 5306 / BITS_PER_UNIT)); 5307 parms->nregs += 1; 5308 } 5309 } 5310 else 5311 { 5312 if (parms->intoffset == -1) 5313 parms->intoffset = bitpos; 5314 } 5315 } 5316 } 5317} 5318 5319/* Used by function_arg and function_value to implement the complex 5320 conventions of the 64-bit ABI for passing and returning structures. 5321 Return an expression valid as a return value for the two macros 5322 FUNCTION_ARG and FUNCTION_VALUE. 5323 5324 TYPE is the data type of the argument (as a tree). 5325 This is null for libcalls where that information may 5326 not be available. 5327 MODE is the argument's machine mode. 5328 SLOTNO is the index number of the argument's slot in the parameter array. 5329 NAMED is nonzero if this argument is a named parameter 5330 (otherwise it is an extra parameter matching an ellipsis). 5331 REGBASE is the regno of the base register for the parameter array. */ 5332 5333static rtx 5334function_arg_record_value (tree type, enum machine_mode mode, 5335 int slotno, int named, int regbase) 5336{ 5337 HOST_WIDE_INT typesize = int_size_in_bytes (type); 5338 struct function_arg_record_value_parms parms; 5339 unsigned int nregs; 5340 5341 parms.ret = NULL_RTX; 5342 parms.slotno = slotno; 5343 parms.named = named; 5344 parms.regbase = regbase; 5345 parms.stack = 0; 5346 5347 /* Compute how many registers we need. */ 5348 parms.nregs = 0; 5349 parms.intoffset = 0; 5350 function_arg_record_value_1 (type, 0, &parms, false); 5351 5352 /* Take into account pending integer fields. */ 5353 if (parms.intoffset != -1) 5354 { 5355 unsigned int startbit, endbit; 5356 int intslots, this_slotno; 5357 5358 startbit = parms.intoffset & -BITS_PER_WORD; 5359 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; 5360 intslots = (endbit - startbit) / BITS_PER_WORD; 5361 this_slotno = slotno + parms.intoffset / BITS_PER_WORD; 5362 5363 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) 5364 { 5365 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); 5366 /* We need to pass this field on the stack. */ 5367 parms.stack = 1; 5368 } 5369 5370 parms.nregs += intslots; 5371 } 5372 nregs = parms.nregs; 5373 5374 /* Allocate the vector and handle some annoying special cases. */ 5375 if (nregs == 0) 5376 { 5377 /* ??? Empty structure has no value? Duh? */ 5378 if (typesize <= 0) 5379 { 5380 /* Though there's nothing really to store, return a word register 5381 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL 5382 leads to breakage due to the fact that there are zero bytes to 5383 load. */ 5384 return gen_rtx_REG (mode, regbase); 5385 } 5386 else 5387 { 5388 /* ??? C++ has structures with no fields, and yet a size. Give up 5389 for now and pass everything back in integer registers. */ 5390 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 5391 } 5392 if (nregs + slotno > SPARC_INT_ARG_MAX) 5393 nregs = SPARC_INT_ARG_MAX - slotno; 5394 } 5395 if (nregs == 0) 5396 abort (); 5397 5398 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs)); 5399 5400 /* If at least one field must be passed on the stack, generate 5401 (parallel [(expr_list (nil) ...) ...]) so that all fields will 5402 also be passed on the stack. We can't do much better because the 5403 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case 5404 of structures for which the fields passed exclusively in registers 5405 are not at the beginning of the structure. */ 5406 if (parms.stack) 5407 XVECEXP (parms.ret, 0, 0) 5408 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 5409 5410 /* Fill in the entries. */ 5411 parms.nregs = 0; 5412 parms.intoffset = 0; 5413 function_arg_record_value_2 (type, 0, &parms, false); 5414 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); 5415 5416 if (parms.nregs != nregs) 5417 abort (); 5418 5419 return parms.ret; 5420} 5421 5422/* Used by function_arg and function_value to implement the conventions 5423 of the 64-bit ABI for passing and returning unions. 5424 Return an expression valid as a return value for the two macros 5425 FUNCTION_ARG and FUNCTION_VALUE. 5426 5427 SIZE is the size in bytes of the union. 5428 MODE is the argument's machine mode. 5429 REGNO is the hard register the union will be passed in. */ 5430 5431static rtx 5432function_arg_union_value (int size, enum machine_mode mode, int slotno, 5433 int regno) 5434{ 5435 int nwords = ROUND_ADVANCE (size), i; 5436 rtx regs; 5437 5438 /* See comment in previous function for empty structures. */ 5439 if (nwords == 0) 5440 return gen_rtx_REG (mode, regno); 5441 5442 if (slotno == SPARC_INT_ARG_MAX - 1) 5443 nwords = 1; 5444 5445 /* Unions are passed left-justified. */ 5446 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords)); 5447 5448 for (i = 0; i < nwords; i++) 5449 XVECEXP (regs, 0, i) 5450 = gen_rtx_EXPR_LIST (VOIDmode, 5451 gen_rtx_REG (word_mode, regno + i), 5452 GEN_INT (UNITS_PER_WORD * i)); 5453 5454 return regs; 5455} 5456 5457/* Handle the FUNCTION_ARG macro. 5458 Determine where to put an argument to a function. 5459 Value is zero to push the argument on the stack, 5460 or a hard register in which to store the argument. 5461 5462 CUM is a variable of type CUMULATIVE_ARGS which gives info about 5463 the preceding args and about the function being called. 5464 MODE is the argument's machine mode. 5465 TYPE is the data type of the argument (as a tree). 5466 This is null for libcalls where that information may 5467 not be available. 5468 NAMED is nonzero if this argument is a named parameter 5469 (otherwise it is an extra parameter matching an ellipsis). 5470 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ 5471 5472rtx 5473function_arg (const struct sparc_args *cum, enum machine_mode mode, 5474 tree type, int named, int incoming_p) 5475{ 5476 int regbase = (incoming_p 5477 ? SPARC_INCOMING_INT_ARG_FIRST 5478 : SPARC_OUTGOING_INT_ARG_FIRST); 5479 int slotno, regno, padding; 5480 rtx reg; 5481 5482 slotno = function_arg_slotno (cum, mode, type, named, incoming_p, 5483 ®no, &padding); 5484 5485 if (slotno == -1) 5486 return 0; 5487 5488 if (TARGET_ARCH32) 5489 { 5490 reg = gen_rtx_REG (mode, regno); 5491 return reg; 5492 } 5493 5494 if (type && TREE_CODE (type) == RECORD_TYPE) 5495 { 5496 /* Structures up to 16 bytes in size are passed in arg slots on the 5497 stack and are promoted to registers where possible. */ 5498 5499 if (int_size_in_bytes (type) > 16) 5500 abort (); /* shouldn't get here */ 5501 5502 return function_arg_record_value (type, mode, slotno, named, regbase); 5503 } 5504 else if (type && TREE_CODE (type) == UNION_TYPE) 5505 { 5506 HOST_WIDE_INT size = int_size_in_bytes (type); 5507 5508 if (size > 16) 5509 abort (); /* shouldn't get here */ 5510 5511 return function_arg_union_value (size, mode, slotno, regno); 5512 } 5513 /* v9 fp args in reg slots beyond the int reg slots get passed in regs 5514 but also have the slot allocated for them. 5515 If no prototype is in scope fp values in register slots get passed 5516 in two places, either fp regs and int regs or fp regs and memory. */ 5517 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT 5518 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5519 && SPARC_FP_REG_P (regno)) 5520 { 5521 reg = gen_rtx_REG (mode, regno); 5522 if (cum->prototype_p || cum->libcall_p) 5523 { 5524 /* "* 2" because fp reg numbers are recorded in 4 byte 5525 quantities. */ 5526#if 0 5527 /* ??? This will cause the value to be passed in the fp reg and 5528 in the stack. When a prototype exists we want to pass the 5529 value in the reg but reserve space on the stack. That's an 5530 optimization, and is deferred [for a bit]. */ 5531 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) 5532 return gen_rtx_PARALLEL (mode, 5533 gen_rtvec (2, 5534 gen_rtx_EXPR_LIST (VOIDmode, 5535 NULL_RTX, const0_rtx), 5536 gen_rtx_EXPR_LIST (VOIDmode, 5537 reg, const0_rtx))); 5538 else 5539#else 5540 /* ??? It seems that passing back a register even when past 5541 the area declared by REG_PARM_STACK_SPACE will allocate 5542 space appropriately, and will not copy the data onto the 5543 stack, exactly as we desire. 5544 5545 This is due to locate_and_pad_parm being called in 5546 expand_call whenever reg_parm_stack_space > 0, which 5547 while beneficial to our example here, would seem to be 5548 in error from what had been intended. Ho hum... -- r~ */ 5549#endif 5550 return reg; 5551 } 5552 else 5553 { 5554 rtx v0, v1; 5555 5556 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) 5557 { 5558 int intreg; 5559 5560 /* On incoming, we don't need to know that the value 5561 is passed in %f0 and %i0, and it confuses other parts 5562 causing needless spillage even on the simplest cases. */ 5563 if (incoming_p) 5564 return reg; 5565 5566 intreg = (SPARC_OUTGOING_INT_ARG_FIRST 5567 + (regno - SPARC_FP_ARG_FIRST) / 2); 5568 5569 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 5570 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), 5571 const0_rtx); 5572 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 5573 } 5574 else 5575 { 5576 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 5577 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 5578 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 5579 } 5580 } 5581 } 5582 else 5583 { 5584 /* Scalar or complex int. */ 5585 reg = gen_rtx_REG (mode, regno); 5586 } 5587 5588 return reg; 5589} 5590 5591/* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. 5592 For an arg passed partly in registers and partly in memory, 5593 this is the number of registers used. 5594 For args passed entirely in registers or entirely in memory, zero. 5595 5596 Any arg that starts in the first 6 regs but won't entirely fit in them 5597 needs partial registers on v8. On v9, structures with integer 5598 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp 5599 values that begin in the last fp reg [where "last fp reg" varies with the 5600 mode] will be split between that reg and memory. */ 5601 5602int 5603function_arg_partial_nregs (const struct sparc_args *cum, 5604 enum machine_mode mode, tree type, int named) 5605{ 5606 int slotno, regno, padding; 5607 5608 /* We pass 0 for incoming_p here, it doesn't matter. */ 5609 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); 5610 5611 if (slotno == -1) 5612 return 0; 5613 5614 if (TARGET_ARCH32) 5615 { 5616 if ((slotno + (mode == BLKmode 5617 ? ROUND_ADVANCE (int_size_in_bytes (type)) 5618 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) 5619 > NPARM_REGS (SImode)) 5620 return NPARM_REGS (SImode) - slotno; 5621 return 0; 5622 } 5623 else 5624 { 5625 if (type && AGGREGATE_TYPE_P (type)) 5626 { 5627 int size = int_size_in_bytes (type); 5628 int align = TYPE_ALIGN (type); 5629 5630 if (align == 16) 5631 slotno += slotno & 1; 5632 if (size > 8 && size <= 16 5633 && slotno == SPARC_INT_ARG_MAX - 1) 5634 return 1; 5635 } 5636 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT 5637 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 5638 && ! (TARGET_FPU && named))) 5639 { 5640 /* The complex types are passed as packed types. */ 5641 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) 5642 return 0; 5643 5644 if (GET_MODE_ALIGNMENT (mode) == 128) 5645 { 5646 slotno += slotno & 1; 5647 5648 /* ??? The mode needs 3 slots? */ 5649 if (slotno == SPARC_INT_ARG_MAX - 2) 5650 return 1; 5651 } 5652 else 5653 { 5654 if (slotno == SPARC_INT_ARG_MAX - 1) 5655 return 1; 5656 } 5657 } 5658 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5659 { 5660 if (GET_MODE_ALIGNMENT (mode) == 128) 5661 slotno += slotno & 1; 5662 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) 5663 > SPARC_FP_ARG_MAX) 5664 return 1; 5665 } 5666 return 0; 5667 } 5668} 5669 5670/* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. 5671 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and 5672 quad-precision floats by invisible reference. 5673 v9: Aggregates greater than 16 bytes are passed by reference. 5674 For Pascal, also pass arrays by reference. */ 5675 5676int 5677function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED, 5678 enum machine_mode mode, tree type, 5679 int named ATTRIBUTE_UNUSED) 5680{ 5681 if (TARGET_ARCH32) 5682 { 5683 return ((type && AGGREGATE_TYPE_P (type)) 5684 || mode == SCmode 5685 || GET_MODE_SIZE (mode) > 8); 5686 } 5687 else 5688 { 5689 return ((type && TREE_CODE (type) == ARRAY_TYPE) 5690 /* Consider complex values as aggregates, so care 5691 for CTImode and TCmode. */ 5692 || GET_MODE_SIZE (mode) > 16 5693 || (type 5694 && AGGREGATE_TYPE_P (type) 5695 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)); 5696 } 5697} 5698 5699/* Handle the FUNCTION_ARG_ADVANCE macro. 5700 Update the data in CUM to advance over an argument 5701 of mode MODE and data type TYPE. 5702 TYPE is null for libcalls where that information may not be available. */ 5703 5704void 5705function_arg_advance (struct sparc_args *cum, enum machine_mode mode, 5706 tree type, int named) 5707{ 5708 int slotno, regno, padding; 5709 5710 /* We pass 0 for incoming_p here, it doesn't matter. */ 5711 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); 5712 5713 /* If register required leading padding, add it. */ 5714 if (slotno != -1) 5715 cum->words += padding; 5716 5717 if (TARGET_ARCH32) 5718 { 5719 cum->words += (mode != BLKmode 5720 ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) 5721 : ROUND_ADVANCE (int_size_in_bytes (type))); 5722 } 5723 else 5724 { 5725 if (type && AGGREGATE_TYPE_P (type)) 5726 { 5727 int size = int_size_in_bytes (type); 5728 5729 if (size <= 8) 5730 ++cum->words; 5731 else if (size <= 16) 5732 cum->words += 2; 5733 else /* passed by reference */ 5734 ++cum->words; 5735 } 5736 else 5737 { 5738 cum->words += (mode != BLKmode 5739 ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) 5740 : ROUND_ADVANCE (int_size_in_bytes (type))); 5741 } 5742 } 5743} 5744 5745/* Handle the FUNCTION_ARG_PADDING macro. 5746 For the 64 bit ABI structs are always stored left shifted in their 5747 argument slot. */ 5748 5749enum direction 5750function_arg_padding (enum machine_mode mode, tree type) 5751{ 5752 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) 5753 return upward; 5754 5755 /* Fall back to the default. */ 5756 return DEFAULT_FUNCTION_ARG_PADDING (mode, type); 5757} 5758 5759/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. 5760 For v9, function return values are subject to the same rules as arguments, 5761 except that up to 32-bytes may be returned in registers. */ 5762 5763rtx 5764function_value (tree type, enum machine_mode mode, int incoming_p) 5765{ 5766 int regno; 5767 5768 if (TARGET_ARCH64 && type) 5769 { 5770 int regbase = (incoming_p 5771 ? SPARC_OUTGOING_INT_ARG_FIRST 5772 : SPARC_INCOMING_INT_ARG_FIRST); 5773 5774 if (TREE_CODE (type) == RECORD_TYPE) 5775 { 5776 /* Structures up to 32 bytes in size are passed in registers, 5777 promoted to fp registers where possible. */ 5778 5779 if (int_size_in_bytes (type) > 32) 5780 abort (); /* shouldn't get here */ 5781 5782 return function_arg_record_value (type, mode, 0, 1, regbase); 5783 } 5784 else if (TREE_CODE (type) == UNION_TYPE) 5785 { 5786 HOST_WIDE_INT size = int_size_in_bytes (type); 5787 5788 if (size > 32) 5789 abort (); /* shouldn't get here */ 5790 5791 return function_arg_union_value (size, mode, 0, regbase); 5792 } 5793 else if (AGGREGATE_TYPE_P (type)) 5794 { 5795 /* All other aggregate types are passed in an integer register 5796 in a mode corresponding to the size of the type. */ 5797 HOST_WIDE_INT bytes = int_size_in_bytes (type); 5798 5799 if (bytes > 32) 5800 abort (); 5801 5802 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); 5803 5804 /* ??? We probably should have made the same ABI change in 5805 3.4.0 as the one we made for unions. The latter was 5806 required by the SCD though, while the former is not 5807 specified, so we favored compatibility and efficiency. 5808 5809 Now we're stuck for aggregates larger than 16 bytes, 5810 because OImode vanished in the meantime. Let's not 5811 try to be unduly clever, and simply follow the ABI 5812 for unions in that case. */ 5813 if (mode == BLKmode) 5814 return function_arg_union_value (bytes, mode, 0, regbase); 5815 } 5816 else if (GET_MODE_CLASS (mode) == MODE_INT 5817 && GET_MODE_SIZE (mode) < UNITS_PER_WORD) 5818 mode = word_mode; 5819 } 5820 5821 if (incoming_p) 5822 regno = BASE_RETURN_VALUE_REG (mode); 5823 else 5824 regno = BASE_OUTGOING_VALUE_REG (mode); 5825 5826 return gen_rtx_REG (mode, regno); 5827} 5828 5829/* Do what is necessary for `va_start'. We look at the current function 5830 to determine if stdarg or varargs is used and return the address of 5831 the first unnamed parameter. */ 5832 5833rtx 5834sparc_builtin_saveregs (void) 5835{ 5836 int first_reg = current_function_args_info.words; 5837 rtx address; 5838 int regno; 5839 5840 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) 5841 emit_move_insn (gen_rtx_MEM (word_mode, 5842 gen_rtx_PLUS (Pmode, 5843 frame_pointer_rtx, 5844 GEN_INT (FIRST_PARM_OFFSET (0) 5845 + (UNITS_PER_WORD 5846 * regno)))), 5847 gen_rtx_REG (word_mode, 5848 BASE_INCOMING_ARG_REG (word_mode) + regno)); 5849 5850 address = gen_rtx_PLUS (Pmode, 5851 frame_pointer_rtx, 5852 GEN_INT (FIRST_PARM_OFFSET (0) 5853 + UNITS_PER_WORD * first_reg)); 5854 5855 return address; 5856} 5857 5858/* Implement `va_start' for varargs and stdarg. */ 5859 5860void 5861sparc_va_start (tree valist, rtx nextarg) 5862{ 5863 nextarg = expand_builtin_saveregs (); 5864 std_expand_builtin_va_start (valist, nextarg); 5865} 5866 5867/* Implement `va_arg'. */ 5868 5869rtx 5870sparc_va_arg (tree valist, tree type) 5871{ 5872 HOST_WIDE_INT size, rsize, align; 5873 tree addr, incr; 5874 rtx addr_rtx; 5875 int indirect = 0; 5876 5877 /* Round up sizeof(type) to a word. */ 5878 size = int_size_in_bytes (type); 5879 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; 5880 align = 0; 5881 5882 if (TARGET_ARCH64) 5883 { 5884 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) 5885 align = 2 * UNITS_PER_WORD; 5886 5887 /* Consider complex values as aggregates, so care 5888 for CTImode and TCmode. */ 5889 if ((unsigned HOST_WIDE_INT) size > 16) 5890 { 5891 indirect = 1; 5892 size = rsize = UNITS_PER_WORD; 5893 align = 0; 5894 } 5895 else if (AGGREGATE_TYPE_P (type)) 5896 { 5897 /* SPARC-V9 ABI states that structures up to 16 bytes in size 5898 are given whole slots as needed. */ 5899 if (size == 0) 5900 size = rsize = UNITS_PER_WORD; 5901 else 5902 size = rsize; 5903 } 5904 } 5905 else 5906 { 5907 if (AGGREGATE_TYPE_P (type) 5908 || TYPE_MODE (type) == SCmode 5909 || GET_MODE_SIZE (TYPE_MODE (type)) > 8) 5910 { 5911 indirect = 1; 5912 size = rsize = UNITS_PER_WORD; 5913 } 5914 } 5915 5916 incr = valist; 5917 if (align) 5918 { 5919 incr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5920 build_int_2 (align - 1, 0))); 5921 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr, 5922 build_int_2 (-align, -1))); 5923 } 5924 5925 addr = incr = save_expr (incr); 5926 if (BYTES_BIG_ENDIAN && size < rsize) 5927 { 5928 addr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5929 build_int_2 (rsize - size, 0))); 5930 } 5931 incr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5932 build_int_2 (rsize, 0))); 5933 5934 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr); 5935 TREE_SIDE_EFFECTS (incr) = 1; 5936 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); 5937 5938 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); 5939 5940 /* If the address isn't aligned properly for the type, 5941 we may need to copy to a temporary. 5942 FIXME: This is inefficient. Usually we can do this 5943 in registers. */ 5944 if (align == 0 5945 && TYPE_ALIGN (type) > BITS_PER_WORD 5946 && !indirect) 5947 { 5948 /* FIXME: We really need to specify that the temporary is live 5949 for the whole function because expand_builtin_va_arg wants 5950 the alias set to be get_varargs_alias_set (), but in this 5951 case the alias set is that for TYPE and if the memory gets 5952 reused it will be reused with alias set TYPE. */ 5953 rtx tmp = assign_temp (type, 0, 1, 0); 5954 rtx dest_addr; 5955 5956 addr_rtx = force_reg (Pmode, addr_rtx); 5957 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx); 5958 set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); 5959 set_mem_align (addr_rtx, BITS_PER_WORD); 5960 tmp = shallow_copy_rtx (tmp); 5961 PUT_MODE (tmp, BLKmode); 5962 set_mem_alias_set (tmp, 0); 5963 5964 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize), 5965 BLOCK_OP_NORMAL); 5966 if (dest_addr != NULL_RTX) 5967 addr_rtx = dest_addr; 5968 else 5969 addr_rtx = XCEXP (tmp, 0, MEM); 5970 } 5971 5972 if (indirect) 5973 { 5974 addr_rtx = force_reg (Pmode, addr_rtx); 5975 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); 5976 set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); 5977 } 5978 5979 return addr_rtx; 5980} 5981 5982/* Return the string to output an unconditional branch to LABEL, which is 5983 the operand number of the label. 5984 5985 DEST is the destination insn (i.e. the label), INSN is the source. */ 5986 5987const char * 5988output_ubranch (rtx dest, int label, rtx insn) 5989{ 5990 static char string[64]; 5991 bool noop = false; 5992 char *p; 5993 5994 /* TurboSPARC is reported to have problems with 5995 with 5996 foo: b,a foo 5997 i.e. an empty loop with the annul bit set. The workaround is to use 5998 foo: b foo; nop 5999 instead. */ 6000 6001 if (! TARGET_V9 && flag_delayed_branch 6002 && (INSN_ADDRESSES (INSN_UID (dest)) 6003 == INSN_ADDRESSES (INSN_UID (insn)))) 6004 { 6005 strcpy (string, "b\t"); 6006 noop = true; 6007 } 6008 else 6009 { 6010 bool v9_form = false; 6011 6012 if (TARGET_V9 && INSN_ADDRESSES_SET_P ()) 6013 { 6014 int delta = (INSN_ADDRESSES (INSN_UID (dest)) 6015 - INSN_ADDRESSES (INSN_UID (insn))); 6016 /* Leave some instructions for "slop". */ 6017 if (delta >= -260000 && delta < 260000) 6018 v9_form = true; 6019 } 6020 6021 if (v9_form) 6022 strcpy (string, "ba%*,pt\t%%xcc, "); 6023 else 6024 strcpy (string, "b%*\t"); 6025 } 6026 6027 p = strchr (string, '\0'); 6028 *p++ = '%'; 6029 *p++ = 'l'; 6030 *p++ = '0' + label; 6031 *p++ = '%'; 6032 if (noop) 6033 *p++ = '#'; 6034 else 6035 *p++ = '('; 6036 *p = '\0'; 6037 6038 return string; 6039} 6040 6041/* Return the string to output a conditional branch to LABEL, which is 6042 the operand number of the label. OP is the conditional expression. 6043 XEXP (OP, 0) is assumed to be a condition code register (integer or 6044 floating point) and its mode specifies what kind of comparison we made. 6045 6046 DEST is the destination insn (i.e. the label), INSN is the source. 6047 6048 REVERSED is nonzero if we should reverse the sense of the comparison. 6049 6050 ANNUL is nonzero if we should generate an annulling branch. 6051 6052 NOOP is nonzero if we have to follow this branch by a noop. */ 6053 6054char * 6055output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, 6056 int noop, rtx insn) 6057{ 6058 static char string[50]; 6059 enum rtx_code code = GET_CODE (op); 6060 rtx cc_reg = XEXP (op, 0); 6061 enum machine_mode mode = GET_MODE (cc_reg); 6062 const char *labelno, *branch; 6063 int spaces = 8, far; 6064 char *p; 6065 6066 /* v9 branches are limited to +-1MB. If it is too far away, 6067 change 6068 6069 bne,pt %xcc, .LC30 6070 6071 to 6072 6073 be,pn %xcc, .+12 6074 nop 6075 ba .LC30 6076 6077 and 6078 6079 fbne,a,pn %fcc2, .LC29 6080 6081 to 6082 6083 fbe,pt %fcc2, .+16 6084 nop 6085 ba .LC29 */ 6086 6087 far = TARGET_V9 && (get_attr_length (insn) >= 3); 6088 if (reversed ^ far) 6089 { 6090 /* Reversal of FP compares takes care -- an ordered compare 6091 becomes an unordered compare and vice versa. */ 6092 if (mode == CCFPmode || mode == CCFPEmode) 6093 code = reverse_condition_maybe_unordered (code); 6094 else 6095 code = reverse_condition (code); 6096 } 6097 6098 /* Start by writing the branch condition. */ 6099 if (mode == CCFPmode || mode == CCFPEmode) 6100 { 6101 switch (code) 6102 { 6103 case NE: 6104 branch = "fbne"; 6105 break; 6106 case EQ: 6107 branch = "fbe"; 6108 break; 6109 case GE: 6110 branch = "fbge"; 6111 break; 6112 case GT: 6113 branch = "fbg"; 6114 break; 6115 case LE: 6116 branch = "fble"; 6117 break; 6118 case LT: 6119 branch = "fbl"; 6120 break; 6121 case UNORDERED: 6122 branch = "fbu"; 6123 break; 6124 case ORDERED: 6125 branch = "fbo"; 6126 break; 6127 case UNGT: 6128 branch = "fbug"; 6129 break; 6130 case UNLT: 6131 branch = "fbul"; 6132 break; 6133 case UNEQ: 6134 branch = "fbue"; 6135 break; 6136 case UNGE: 6137 branch = "fbuge"; 6138 break; 6139 case UNLE: 6140 branch = "fbule"; 6141 break; 6142 case LTGT: 6143 branch = "fblg"; 6144 break; 6145 6146 default: 6147 abort (); 6148 } 6149 6150 /* ??? !v9: FP branches cannot be preceded by another floating point 6151 insn. Because there is currently no concept of pre-delay slots, 6152 we can fix this only by always emitting a nop before a floating 6153 point branch. */ 6154 6155 string[0] = '\0'; 6156 if (! TARGET_V9) 6157 strcpy (string, "nop\n\t"); 6158 strcat (string, branch); 6159 } 6160 else 6161 { 6162 switch (code) 6163 { 6164 case NE: 6165 branch = "bne"; 6166 break; 6167 case EQ: 6168 branch = "be"; 6169 break; 6170 case GE: 6171 if (mode == CC_NOOVmode || mode == CCX_NOOVmode) 6172 branch = "bpos"; 6173 else 6174 branch = "bge"; 6175 break; 6176 case GT: 6177 branch = "bg"; 6178 break; 6179 case LE: 6180 branch = "ble"; 6181 break; 6182 case LT: 6183 if (mode == CC_NOOVmode || mode == CCX_NOOVmode) 6184 branch = "bneg"; 6185 else 6186 branch = "bl"; 6187 break; 6188 case GEU: 6189 branch = "bgeu"; 6190 break; 6191 case GTU: 6192 branch = "bgu"; 6193 break; 6194 case LEU: 6195 branch = "bleu"; 6196 break; 6197 case LTU: 6198 branch = "blu"; 6199 break; 6200 6201 default: 6202 abort (); 6203 } 6204 strcpy (string, branch); 6205 } 6206 spaces -= strlen (branch); 6207 p = strchr (string, '\0'); 6208 6209 /* Now add the annulling, the label, and a possible noop. */ 6210 if (annul && ! far) 6211 { 6212 strcpy (p, ",a"); 6213 p += 2; 6214 spaces -= 2; 6215 } 6216 6217 if (TARGET_V9) 6218 { 6219 rtx note; 6220 int v8 = 0; 6221 6222 if (! far && insn && INSN_ADDRESSES_SET_P ()) 6223 { 6224 int delta = (INSN_ADDRESSES (INSN_UID (dest)) 6225 - INSN_ADDRESSES (INSN_UID (insn))); 6226 /* Leave some instructions for "slop". */ 6227 if (delta < -260000 || delta >= 260000) 6228 v8 = 1; 6229 } 6230 6231 if (mode == CCFPmode || mode == CCFPEmode) 6232 { 6233 static char v9_fcc_labelno[] = "%%fccX, "; 6234 /* Set the char indicating the number of the fcc reg to use. */ 6235 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; 6236 labelno = v9_fcc_labelno; 6237 if (v8) 6238 { 6239 if (REGNO (cc_reg) == SPARC_FCC_REG) 6240 labelno = ""; 6241 else 6242 abort (); 6243 } 6244 } 6245 else if (mode == CCXmode || mode == CCX_NOOVmode) 6246 { 6247 labelno = "%%xcc, "; 6248 if (v8) 6249 abort (); 6250 } 6251 else 6252 { 6253 labelno = "%%icc, "; 6254 if (v8) 6255 labelno = ""; 6256 } 6257 6258 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 6259 { 6260 strcpy (p, 6261 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) 6262 ? ",pt" : ",pn"); 6263 p += 3; 6264 spaces -= 3; 6265 } 6266 } 6267 else 6268 labelno = ""; 6269 6270 if (spaces > 0) 6271 *p++ = '\t'; 6272 else 6273 *p++ = ' '; 6274 strcpy (p, labelno); 6275 p = strchr (p, '\0'); 6276 if (far) 6277 { 6278 strcpy (p, ".+12\n\tnop\n\tb\t"); 6279 if (annul || noop) 6280 p[3] = '6'; 6281 p += 13; 6282 } 6283 *p++ = '%'; 6284 *p++ = 'l'; 6285 /* Set the char indicating the number of the operand containing the 6286 label_ref. */ 6287 *p++ = label + '0'; 6288 *p = '\0'; 6289 if (noop) 6290 strcpy (p, "\n\tnop"); 6291 6292 return string; 6293} 6294 6295/* Emit a library call comparison between floating point X and Y. 6296 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). 6297 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode 6298 values as arguments instead of the TFmode registers themselves, 6299 that's why we cannot call emit_float_lib_cmp. */ 6300void 6301sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison) 6302{ 6303 const char *qpfunc; 6304 rtx slot0, slot1, result, tem, tem2; 6305 enum machine_mode mode; 6306 6307 switch (comparison) 6308 { 6309 case EQ: 6310 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; 6311 break; 6312 6313 case NE: 6314 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; 6315 break; 6316 6317 case GT: 6318 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; 6319 break; 6320 6321 case GE: 6322 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; 6323 break; 6324 6325 case LT: 6326 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; 6327 break; 6328 6329 case LE: 6330 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; 6331 break; 6332 6333 case ORDERED: 6334 case UNORDERED: 6335 case UNGT: 6336 case UNLT: 6337 case UNEQ: 6338 case UNGE: 6339 case UNLE: 6340 case LTGT: 6341 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; 6342 break; 6343 6344 default: 6345 abort(); 6346 break; 6347 } 6348 6349 if (TARGET_ARCH64) 6350 { 6351 if (GET_CODE (x) != MEM) 6352 { 6353 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); 6354 emit_insn (gen_rtx_SET (VOIDmode, slot0, x)); 6355 } 6356 else 6357 slot0 = x; 6358 6359 if (GET_CODE (y) != MEM) 6360 { 6361 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); 6362 emit_insn (gen_rtx_SET (VOIDmode, slot1, y)); 6363 } 6364 else 6365 slot1 = y; 6366 6367 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, 6368 DImode, 2, 6369 XEXP (slot0, 0), Pmode, 6370 XEXP (slot1, 0), Pmode); 6371 6372 mode = DImode; 6373 } 6374 else 6375 { 6376 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, 6377 SImode, 2, 6378 x, TFmode, y, TFmode); 6379 6380 mode = SImode; 6381 } 6382 6383 6384 /* Immediately move the result of the libcall into a pseudo 6385 register so reload doesn't clobber the value if it needs 6386 the return register for a spill reg. */ 6387 result = gen_reg_rtx (mode); 6388 emit_move_insn (result, hard_libcall_value (mode)); 6389 6390 switch (comparison) 6391 { 6392 default: 6393 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0); 6394 break; 6395 case ORDERED: 6396 case UNORDERED: 6397 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE, 6398 NULL_RTX, mode, 0); 6399 break; 6400 case UNGT: 6401 case UNGE: 6402 emit_cmp_insn (result, const1_rtx, 6403 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0); 6404 break; 6405 case UNLE: 6406 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0); 6407 break; 6408 case UNLT: 6409 tem = gen_reg_rtx (mode); 6410 if (TARGET_ARCH32) 6411 emit_insn (gen_andsi3 (tem, result, const1_rtx)); 6412 else 6413 emit_insn (gen_anddi3 (tem, result, const1_rtx)); 6414 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0); 6415 break; 6416 case UNEQ: 6417 case LTGT: 6418 tem = gen_reg_rtx (mode); 6419 if (TARGET_ARCH32) 6420 emit_insn (gen_addsi3 (tem, result, const1_rtx)); 6421 else 6422 emit_insn (gen_adddi3 (tem, result, const1_rtx)); 6423 tem2 = gen_reg_rtx (mode); 6424 if (TARGET_ARCH32) 6425 emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); 6426 else 6427 emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); 6428 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE, 6429 NULL_RTX, mode, 0); 6430 break; 6431 } 6432} 6433 6434/* Generate an unsigned DImode to FP conversion. This is the same code 6435 optabs would emit if we didn't have TFmode patterns. */ 6436 6437void 6438sparc_emit_floatunsdi (rtx *operands) 6439{ 6440 rtx neglab, donelab, i0, i1, f0, in, out; 6441 enum machine_mode mode; 6442 6443 out = operands[0]; 6444 in = force_reg (DImode, operands[1]); 6445 mode = GET_MODE (out); 6446 neglab = gen_label_rtx (); 6447 donelab = gen_label_rtx (); 6448 i0 = gen_reg_rtx (DImode); 6449 i1 = gen_reg_rtx (DImode); 6450 f0 = gen_reg_rtx (mode); 6451 6452 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); 6453 6454 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); 6455 emit_jump_insn (gen_jump (donelab)); 6456 emit_barrier (); 6457 6458 emit_label (neglab); 6459 6460 emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); 6461 emit_insn (gen_anddi3 (i1, in, const1_rtx)); 6462 emit_insn (gen_iordi3 (i0, i0, i1)); 6463 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); 6464 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); 6465 6466 emit_label (donelab); 6467} 6468 6469/* Return the string to output a conditional branch to LABEL, testing 6470 register REG. LABEL is the operand number of the label; REG is the 6471 operand number of the reg. OP is the conditional expression. The mode 6472 of REG says what kind of comparison we made. 6473 6474 DEST is the destination insn (i.e. the label), INSN is the source. 6475 6476 REVERSED is nonzero if we should reverse the sense of the comparison. 6477 6478 ANNUL is nonzero if we should generate an annulling branch. 6479 6480 NOOP is nonzero if we have to follow this branch by a noop. */ 6481 6482char * 6483output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, 6484 int annul, int noop, rtx insn) 6485{ 6486 static char string[50]; 6487 enum rtx_code code = GET_CODE (op); 6488 enum machine_mode mode = GET_MODE (XEXP (op, 0)); 6489 rtx note; 6490 int far; 6491 char *p; 6492 6493 /* branch on register are limited to +-128KB. If it is too far away, 6494 change 6495 6496 brnz,pt %g1, .LC30 6497 6498 to 6499 6500 brz,pn %g1, .+12 6501 nop 6502 ba,pt %xcc, .LC30 6503 6504 and 6505 6506 brgez,a,pn %o1, .LC29 6507 6508 to 6509 6510 brlz,pt %o1, .+16 6511 nop 6512 ba,pt %xcc, .LC29 */ 6513 6514 far = get_attr_length (insn) >= 3; 6515 6516 /* If not floating-point or if EQ or NE, we can just reverse the code. */ 6517 if (reversed ^ far) 6518 code = reverse_condition (code); 6519 6520 /* Only 64 bit versions of these instructions exist. */ 6521 if (mode != DImode) 6522 abort (); 6523 6524 /* Start by writing the branch condition. */ 6525 6526 switch (code) 6527 { 6528 case NE: 6529 strcpy (string, "brnz"); 6530 break; 6531 6532 case EQ: 6533 strcpy (string, "brz"); 6534 break; 6535 6536 case GE: 6537 strcpy (string, "brgez"); 6538 break; 6539 6540 case LT: 6541 strcpy (string, "brlz"); 6542 break; 6543 6544 case LE: 6545 strcpy (string, "brlez"); 6546 break; 6547 6548 case GT: 6549 strcpy (string, "brgz"); 6550 break; 6551 6552 default: 6553 abort (); 6554 } 6555 6556 p = strchr (string, '\0'); 6557 6558 /* Now add the annulling, reg, label, and nop. */ 6559 if (annul && ! far) 6560 { 6561 strcpy (p, ",a"); 6562 p += 2; 6563 } 6564 6565 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 6566 { 6567 strcpy (p, 6568 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) 6569 ? ",pt" : ",pn"); 6570 p += 3; 6571 } 6572 6573 *p = p < string + 8 ? '\t' : ' '; 6574 p++; 6575 *p++ = '%'; 6576 *p++ = '0' + reg; 6577 *p++ = ','; 6578 *p++ = ' '; 6579 if (far) 6580 { 6581 int veryfar = 1, delta; 6582 6583 if (INSN_ADDRESSES_SET_P ()) 6584 { 6585 delta = (INSN_ADDRESSES (INSN_UID (dest)) 6586 - INSN_ADDRESSES (INSN_UID (insn))); 6587 /* Leave some instructions for "slop". */ 6588 if (delta >= -260000 && delta < 260000) 6589 veryfar = 0; 6590 } 6591 6592 strcpy (p, ".+12\n\tnop\n\t"); 6593 if (annul || noop) 6594 p[3] = '6'; 6595 p += 11; 6596 if (veryfar) 6597 { 6598 strcpy (p, "b\t"); 6599 p += 2; 6600 } 6601 else 6602 { 6603 strcpy (p, "ba,pt\t%%xcc, "); 6604 p += 13; 6605 } 6606 } 6607 *p++ = '%'; 6608 *p++ = 'l'; 6609 *p++ = '0' + label; 6610 *p = '\0'; 6611 6612 if (noop) 6613 strcpy (p, "\n\tnop"); 6614 6615 return string; 6616} 6617 6618/* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. 6619 Such instructions cannot be used in the delay slot of return insn on v9. 6620 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. 6621 */ 6622 6623static int 6624epilogue_renumber (register rtx *where, int test) 6625{ 6626 register const char *fmt; 6627 register int i; 6628 register enum rtx_code code; 6629 6630 if (*where == 0) 6631 return 0; 6632 6633 code = GET_CODE (*where); 6634 6635 switch (code) 6636 { 6637 case REG: 6638 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ 6639 return 1; 6640 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) 6641 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); 6642 case SCRATCH: 6643 case CC0: 6644 case PC: 6645 case CONST_INT: 6646 case CONST_DOUBLE: 6647 return 0; 6648 6649 /* Do not replace the frame pointer with the stack pointer because 6650 it can cause the delayed instruction to load below the stack. 6651 This occurs when instructions like: 6652 6653 (set (reg/i:SI 24 %i0) 6654 (mem/f:SI (plus:SI (reg/f:SI 30 %fp) 6655 (const_int -20 [0xffffffec])) 0)) 6656 6657 are in the return delayed slot. */ 6658 case PLUS: 6659 if (GET_CODE (XEXP (*where, 0)) == REG 6660 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM 6661 && (GET_CODE (XEXP (*where, 1)) != CONST_INT 6662 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) 6663 return 1; 6664 break; 6665 6666 case MEM: 6667 if (SPARC_STACK_BIAS 6668 && GET_CODE (XEXP (*where, 0)) == REG 6669 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) 6670 return 1; 6671 break; 6672 6673 default: 6674 break; 6675 } 6676 6677 fmt = GET_RTX_FORMAT (code); 6678 6679 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 6680 { 6681 if (fmt[i] == 'E') 6682 { 6683 register int j; 6684 for (j = XVECLEN (*where, i) - 1; j >= 0; j--) 6685 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) 6686 return 1; 6687 } 6688 else if (fmt[i] == 'e' 6689 && epilogue_renumber (&(XEXP (*where, i)), test)) 6690 return 1; 6691 } 6692 return 0; 6693} 6694 6695/* Leaf functions and non-leaf functions have different needs. */ 6696 6697static const int 6698reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; 6699 6700static const int 6701reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; 6702 6703static const int *const reg_alloc_orders[] = { 6704 reg_leaf_alloc_order, 6705 reg_nonleaf_alloc_order}; 6706 6707void 6708order_regs_for_local_alloc (void) 6709{ 6710 static int last_order_nonleaf = 1; 6711 6712 if (regs_ever_live[15] != last_order_nonleaf) 6713 { 6714 last_order_nonleaf = !last_order_nonleaf; 6715 memcpy ((char *) reg_alloc_order, 6716 (const char *) reg_alloc_orders[last_order_nonleaf], 6717 FIRST_PSEUDO_REGISTER * sizeof (int)); 6718 } 6719} 6720 6721/* Return 1 if REG and MEM are legitimate enough to allow the various 6722 mem<-->reg splits to be run. */ 6723 6724int 6725sparc_splitdi_legitimate (rtx reg, rtx mem) 6726{ 6727 /* Punt if we are here by mistake. */ 6728 if (! reload_completed) 6729 abort (); 6730 6731 /* We must have an offsettable memory reference. */ 6732 if (! offsettable_memref_p (mem)) 6733 return 0; 6734 6735 /* If we have legitimate args for ldd/std, we do not want 6736 the split to happen. */ 6737 if ((REGNO (reg) % 2) == 0 6738 && mem_min_alignment (mem, 8)) 6739 return 0; 6740 6741 /* Success. */ 6742 return 1; 6743} 6744 6745/* Return 1 if x and y are some kind of REG and they refer to 6746 different hard registers. This test is guaranteed to be 6747 run after reload. */ 6748 6749int 6750sparc_absnegfloat_split_legitimate (rtx x, rtx y) 6751{ 6752 if (GET_CODE (x) != REG) 6753 return 0; 6754 if (GET_CODE (y) != REG) 6755 return 0; 6756 if (REGNO (x) == REGNO (y)) 6757 return 0; 6758 return 1; 6759} 6760 6761/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. 6762 This makes them candidates for using ldd and std insns. 6763 6764 Note reg1 and reg2 *must* be hard registers. */ 6765 6766int 6767registers_ok_for_ldd_peep (rtx reg1, rtx reg2) 6768{ 6769 /* We might have been passed a SUBREG. */ 6770 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 6771 return 0; 6772 6773 if (REGNO (reg1) % 2 != 0) 6774 return 0; 6775 6776 /* Integer ldd is deprecated in SPARC V9 */ 6777 if (TARGET_V9 && REGNO (reg1) < 32) 6778 return 0; 6779 6780 return (REGNO (reg1) == REGNO (reg2) - 1); 6781} 6782 6783/* Return 1 if the addresses in mem1 and mem2 are suitable for use in 6784 an ldd or std insn. 6785 6786 This can only happen when addr1 and addr2, the addresses in mem1 6787 and mem2, are consecutive memory locations (addr1 + 4 == addr2). 6788 addr1 must also be aligned on a 64-bit boundary. 6789 6790 Also iff dependent_reg_rtx is not null it should not be used to 6791 compute the address for mem1, i.e. we cannot optimize a sequence 6792 like: 6793 ld [%o0], %o0 6794 ld [%o0 + 4], %o1 6795 to 6796 ldd [%o0], %o0 6797 nor: 6798 ld [%g3 + 4], %g3 6799 ld [%g3], %g2 6800 to 6801 ldd [%g3], %g2 6802 6803 But, note that the transformation from: 6804 ld [%g2 + 4], %g3 6805 ld [%g2], %g2 6806 to 6807 ldd [%g2], %g2 6808 is perfectly fine. Thus, the peephole2 patterns always pass us 6809 the destination register of the first load, never the second one. 6810 6811 For stores we don't have a similar problem, so dependent_reg_rtx is 6812 NULL_RTX. */ 6813 6814int 6815mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx) 6816{ 6817 rtx addr1, addr2; 6818 unsigned int reg1; 6819 HOST_WIDE_INT offset1; 6820 6821 /* The mems cannot be volatile. */ 6822 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) 6823 return 0; 6824 6825 /* MEM1 should be aligned on a 64-bit boundary. */ 6826 if (MEM_ALIGN (mem1) < 64) 6827 return 0; 6828 6829 addr1 = XEXP (mem1, 0); 6830 addr2 = XEXP (mem2, 0); 6831 6832 /* Extract a register number and offset (if used) from the first addr. */ 6833 if (GET_CODE (addr1) == PLUS) 6834 { 6835 /* If not a REG, return zero. */ 6836 if (GET_CODE (XEXP (addr1, 0)) != REG) 6837 return 0; 6838 else 6839 { 6840 reg1 = REGNO (XEXP (addr1, 0)); 6841 /* The offset must be constant! */ 6842 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) 6843 return 0; 6844 offset1 = INTVAL (XEXP (addr1, 1)); 6845 } 6846 } 6847 else if (GET_CODE (addr1) != REG) 6848 return 0; 6849 else 6850 { 6851 reg1 = REGNO (addr1); 6852 /* This was a simple (mem (reg)) expression. Offset is 0. */ 6853 offset1 = 0; 6854 } 6855 6856 /* Make sure the second address is a (mem (plus (reg) (const_int). */ 6857 if (GET_CODE (addr2) != PLUS) 6858 return 0; 6859 6860 if (GET_CODE (XEXP (addr2, 0)) != REG 6861 || GET_CODE (XEXP (addr2, 1)) != CONST_INT) 6862 return 0; 6863 6864 if (reg1 != REGNO (XEXP (addr2, 0))) 6865 return 0; 6866 6867 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) 6868 return 0; 6869 6870 /* The first offset must be evenly divisible by 8 to ensure the 6871 address is 64 bit aligned. */ 6872 if (offset1 % 8 != 0) 6873 return 0; 6874 6875 /* The offset for the second addr must be 4 more than the first addr. */ 6876 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) 6877 return 0; 6878 6879 /* All the tests passed. addr1 and addr2 are valid for ldd and std 6880 instructions. */ 6881 return 1; 6882} 6883 6884/* Return 1 if reg is a pseudo, or is the first register in 6885 a hard register pair. This makes it a candidate for use in 6886 ldd and std insns. */ 6887 6888int 6889register_ok_for_ldd (rtx reg) 6890{ 6891 /* We might have been passed a SUBREG. */ 6892 if (GET_CODE (reg) != REG) 6893 return 0; 6894 6895 if (REGNO (reg) < FIRST_PSEUDO_REGISTER) 6896 return (REGNO (reg) % 2 == 0); 6897 else 6898 return 1; 6899} 6900 6901/* Print operand X (an rtx) in assembler syntax to file FILE. 6902 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 6903 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 6904 6905void 6906print_operand (FILE *file, rtx x, int code) 6907{ 6908 switch (code) 6909 { 6910 case '#': 6911 /* Output a 'nop' if there's nothing for the delay slot. */ 6912 if (dbr_sequence_length () == 0) 6913 fputs ("\n\t nop", file); 6914 return; 6915 case '*': 6916 /* Output an annul flag if there's nothing for the delay slot and we 6917 are optimizing. This is always used with '(' below. */ 6918 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; 6919 this is a dbx bug. So, we only do this when optimizing. */ 6920 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. 6921 Always emit a nop in case the next instruction is a branch. */ 6922 if (dbr_sequence_length () == 0 6923 && (optimize && (int)sparc_cpu < PROCESSOR_V9)) 6924 fputs (",a", file); 6925 return; 6926 case '(': 6927 /* Output a 'nop' if there's nothing for the delay slot and we are 6928 not optimizing. This is always used with '*' above. */ 6929 if (dbr_sequence_length () == 0 6930 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) 6931 fputs ("\n\t nop", file); 6932 return; 6933 case '_': 6934 /* Output the Embedded Medium/Anywhere code model base register. */ 6935 fputs (EMBMEDANY_BASE_REG, file); 6936 return; 6937 case '@': 6938 /* Print out what we are using as the frame pointer. This might 6939 be %fp, or might be %sp+offset. */ 6940 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ 6941 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC, frame_base_name, frame_base_offset); 6942 return; 6943 case '&': 6944 /* Print some local dynamic TLS name. */ 6945 assemble_name (file, get_some_local_dynamic_name ()); 6946 return; 6947 case 'Y': 6948 /* Adjust the operand to take into account a RESTORE operation. */ 6949 if (GET_CODE (x) == CONST_INT) 6950 break; 6951 else if (GET_CODE (x) != REG) 6952 output_operand_lossage ("invalid %%Y operand"); 6953 else if (REGNO (x) < 8) 6954 fputs (reg_names[REGNO (x)], file); 6955 else if (REGNO (x) >= 24 && REGNO (x) < 32) 6956 fputs (reg_names[REGNO (x)-16], file); 6957 else 6958 output_operand_lossage ("invalid %%Y operand"); 6959 return; 6960 case 'L': 6961 /* Print out the low order register name of a register pair. */ 6962 if (WORDS_BIG_ENDIAN) 6963 fputs (reg_names[REGNO (x)+1], file); 6964 else 6965 fputs (reg_names[REGNO (x)], file); 6966 return; 6967 case 'H': 6968 /* Print out the high order register name of a register pair. */ 6969 if (WORDS_BIG_ENDIAN) 6970 fputs (reg_names[REGNO (x)], file); 6971 else 6972 fputs (reg_names[REGNO (x)+1], file); 6973 return; 6974 case 'R': 6975 /* Print out the second register name of a register pair or quad. 6976 I.e., R (%o0) => %o1. */ 6977 fputs (reg_names[REGNO (x)+1], file); 6978 return; 6979 case 'S': 6980 /* Print out the third register name of a register quad. 6981 I.e., S (%o0) => %o2. */ 6982 fputs (reg_names[REGNO (x)+2], file); 6983 return; 6984 case 'T': 6985 /* Print out the fourth register name of a register quad. 6986 I.e., T (%o0) => %o3. */ 6987 fputs (reg_names[REGNO (x)+3], file); 6988 return; 6989 case 'x': 6990 /* Print a condition code register. */ 6991 if (REGNO (x) == SPARC_ICC_REG) 6992 { 6993 /* We don't handle CC[X]_NOOVmode because they're not supposed 6994 to occur here. */ 6995 if (GET_MODE (x) == CCmode) 6996 fputs ("%icc", file); 6997 else if (GET_MODE (x) == CCXmode) 6998 fputs ("%xcc", file); 6999 else 7000 abort (); 7001 } 7002 else 7003 /* %fccN register */ 7004 fputs (reg_names[REGNO (x)], file); 7005 return; 7006 case 'm': 7007 /* Print the operand's address only. */ 7008 output_address (XEXP (x, 0)); 7009 return; 7010 case 'r': 7011 /* In this case we need a register. Use %g0 if the 7012 operand is const0_rtx. */ 7013 if (x == const0_rtx 7014 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) 7015 { 7016 fputs ("%g0", file); 7017 return; 7018 } 7019 else 7020 break; 7021 7022 case 'A': 7023 switch (GET_CODE (x)) 7024 { 7025 case IOR: fputs ("or", file); break; 7026 case AND: fputs ("and", file); break; 7027 case XOR: fputs ("xor", file); break; 7028 default: output_operand_lossage ("invalid %%A operand"); 7029 } 7030 return; 7031 7032 case 'B': 7033 switch (GET_CODE (x)) 7034 { 7035 case IOR: fputs ("orn", file); break; 7036 case AND: fputs ("andn", file); break; 7037 case XOR: fputs ("xnor", file); break; 7038 default: output_operand_lossage ("invalid %%B operand"); 7039 } 7040 return; 7041 7042 /* These are used by the conditional move instructions. */ 7043 case 'c' : 7044 case 'C': 7045 { 7046 enum rtx_code rc = GET_CODE (x); 7047 7048 if (code == 'c') 7049 { 7050 enum machine_mode mode = GET_MODE (XEXP (x, 0)); 7051 if (mode == CCFPmode || mode == CCFPEmode) 7052 rc = reverse_condition_maybe_unordered (GET_CODE (x)); 7053 else 7054 rc = reverse_condition (GET_CODE (x)); 7055 } 7056 switch (rc) 7057 { 7058 case NE: fputs ("ne", file); break; 7059 case EQ: fputs ("e", file); break; 7060 case GE: fputs ("ge", file); break; 7061 case GT: fputs ("g", file); break; 7062 case LE: fputs ("le", file); break; 7063 case LT: fputs ("l", file); break; 7064 case GEU: fputs ("geu", file); break; 7065 case GTU: fputs ("gu", file); break; 7066 case LEU: fputs ("leu", file); break; 7067 case LTU: fputs ("lu", file); break; 7068 case LTGT: fputs ("lg", file); break; 7069 case UNORDERED: fputs ("u", file); break; 7070 case ORDERED: fputs ("o", file); break; 7071 case UNLT: fputs ("ul", file); break; 7072 case UNLE: fputs ("ule", file); break; 7073 case UNGT: fputs ("ug", file); break; 7074 case UNGE: fputs ("uge", file); break; 7075 case UNEQ: fputs ("ue", file); break; 7076 default: output_operand_lossage (code == 'c' 7077 ? "invalid %%c operand" 7078 : "invalid %%C operand"); 7079 } 7080 return; 7081 } 7082 7083 /* These are used by the movr instruction pattern. */ 7084 case 'd': 7085 case 'D': 7086 { 7087 enum rtx_code rc = (code == 'd' 7088 ? reverse_condition (GET_CODE (x)) 7089 : GET_CODE (x)); 7090 switch (rc) 7091 { 7092 case NE: fputs ("ne", file); break; 7093 case EQ: fputs ("e", file); break; 7094 case GE: fputs ("gez", file); break; 7095 case LT: fputs ("lz", file); break; 7096 case LE: fputs ("lez", file); break; 7097 case GT: fputs ("gz", file); break; 7098 default: output_operand_lossage (code == 'd' 7099 ? "invalid %%d operand" 7100 : "invalid %%D operand"); 7101 } 7102 return; 7103 } 7104 7105 case 'b': 7106 { 7107 /* Print a sign-extended character. */ 7108 int i = trunc_int_for_mode (INTVAL (x), QImode); 7109 fprintf (file, "%d", i); 7110 return; 7111 } 7112 7113 case 'f': 7114 /* Operand must be a MEM; write its address. */ 7115 if (GET_CODE (x) != MEM) 7116 output_operand_lossage ("invalid %%f operand"); 7117 output_address (XEXP (x, 0)); 7118 return; 7119 7120 case 's': 7121 { 7122 /* Print a sign-extended 32-bit value. */ 7123 HOST_WIDE_INT i; 7124 if (GET_CODE(x) == CONST_INT) 7125 i = INTVAL (x); 7126 else if (GET_CODE(x) == CONST_DOUBLE) 7127 i = CONST_DOUBLE_LOW (x); 7128 else 7129 { 7130 output_operand_lossage ("invalid %%s operand"); 7131 return; 7132 } 7133 i = trunc_int_for_mode (i, SImode); 7134 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); 7135 return; 7136 } 7137 7138 case 0: 7139 /* Do nothing special. */ 7140 break; 7141 7142 default: 7143 /* Undocumented flag. */ 7144 output_operand_lossage ("invalid operand output code"); 7145 } 7146 7147 if (GET_CODE (x) == REG) 7148 fputs (reg_names[REGNO (x)], file); 7149 else if (GET_CODE (x) == MEM) 7150 { 7151 fputc ('[', file); 7152 /* Poor Sun assembler doesn't understand absolute addressing. */ 7153 if (CONSTANT_P (XEXP (x, 0))) 7154 fputs ("%g0+", file); 7155 output_address (XEXP (x, 0)); 7156 fputc (']', file); 7157 } 7158 else if (GET_CODE (x) == HIGH) 7159 { 7160 fputs ("%hi(", file); 7161 output_addr_const (file, XEXP (x, 0)); 7162 fputc (')', file); 7163 } 7164 else if (GET_CODE (x) == LO_SUM) 7165 { 7166 print_operand (file, XEXP (x, 0), 0); 7167 if (TARGET_CM_MEDMID) 7168 fputs ("+%l44(", file); 7169 else 7170 fputs ("+%lo(", file); 7171 output_addr_const (file, XEXP (x, 1)); 7172 fputc (')', file); 7173 } 7174 else if (GET_CODE (x) == CONST_DOUBLE 7175 && (GET_MODE (x) == VOIDmode 7176 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) 7177 { 7178 if (CONST_DOUBLE_HIGH (x) == 0) 7179 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); 7180 else if (CONST_DOUBLE_HIGH (x) == -1 7181 && CONST_DOUBLE_LOW (x) < 0) 7182 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); 7183 else 7184 output_operand_lossage ("long long constant not a valid immediate operand"); 7185 } 7186 else if (GET_CODE (x) == CONST_DOUBLE) 7187 output_operand_lossage ("floating point constant not a valid immediate operand"); 7188 else { output_addr_const (file, x); } 7189} 7190 7191/* Target hook for assembling integer objects. The sparc version has 7192 special handling for aligned DI-mode objects. */ 7193 7194static bool 7195sparc_assemble_integer (rtx x, unsigned int size, int aligned_p) 7196{ 7197 /* ??? We only output .xword's for symbols and only then in environments 7198 where the assembler can handle them. */ 7199 if (aligned_p && size == 8 7200 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE)) 7201 { 7202 if (TARGET_V9) 7203 { 7204 assemble_integer_with_op ("\t.xword\t", x); 7205 return true; 7206 } 7207 else 7208 { 7209 assemble_aligned_integer (4, const0_rtx); 7210 assemble_aligned_integer (4, x); 7211 return true; 7212 } 7213 } 7214 return default_assemble_integer (x, size, aligned_p); 7215} 7216 7217/* Return the value of a code used in the .proc pseudo-op that says 7218 what kind of result this function returns. For non-C types, we pick 7219 the closest C type. */ 7220 7221#ifndef SHORT_TYPE_SIZE 7222#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) 7223#endif 7224 7225#ifndef INT_TYPE_SIZE 7226#define INT_TYPE_SIZE BITS_PER_WORD 7227#endif 7228 7229#ifndef LONG_TYPE_SIZE 7230#define LONG_TYPE_SIZE BITS_PER_WORD 7231#endif 7232 7233#ifndef LONG_LONG_TYPE_SIZE 7234#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) 7235#endif 7236 7237#ifndef FLOAT_TYPE_SIZE 7238#define FLOAT_TYPE_SIZE BITS_PER_WORD 7239#endif 7240 7241#ifndef DOUBLE_TYPE_SIZE 7242#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 7243#endif 7244 7245#ifndef LONG_DOUBLE_TYPE_SIZE 7246#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 7247#endif 7248 7249unsigned long 7250sparc_type_code (register tree type) 7251{ 7252 register unsigned long qualifiers = 0; 7253 register unsigned shift; 7254 7255 /* Only the first 30 bits of the qualifier are valid. We must refrain from 7256 setting more, since some assemblers will give an error for this. Also, 7257 we must be careful to avoid shifts of 32 bits or more to avoid getting 7258 unpredictable results. */ 7259 7260 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) 7261 { 7262 switch (TREE_CODE (type)) 7263 { 7264 case ERROR_MARK: 7265 return qualifiers; 7266 7267 case ARRAY_TYPE: 7268 qualifiers |= (3 << shift); 7269 break; 7270 7271 case FUNCTION_TYPE: 7272 case METHOD_TYPE: 7273 qualifiers |= (2 << shift); 7274 break; 7275 7276 case POINTER_TYPE: 7277 case REFERENCE_TYPE: 7278 case OFFSET_TYPE: 7279 qualifiers |= (1 << shift); 7280 break; 7281 7282 case RECORD_TYPE: 7283 return (qualifiers | 8); 7284 7285 case UNION_TYPE: 7286 case QUAL_UNION_TYPE: 7287 return (qualifiers | 9); 7288 7289 case ENUMERAL_TYPE: 7290 return (qualifiers | 10); 7291 7292 case VOID_TYPE: 7293 return (qualifiers | 16); 7294 7295 case INTEGER_TYPE: 7296 /* If this is a range type, consider it to be the underlying 7297 type. */ 7298 if (TREE_TYPE (type) != 0) 7299 break; 7300 7301 /* Carefully distinguish all the standard types of C, 7302 without messing up if the language is not C. We do this by 7303 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to 7304 look at both the names and the above fields, but that's redundant. 7305 Any type whose size is between two C types will be considered 7306 to be the wider of the two types. Also, we do not have a 7307 special code to use for "long long", so anything wider than 7308 long is treated the same. Note that we can't distinguish 7309 between "int" and "long" in this code if they are the same 7310 size, but that's fine, since neither can the assembler. */ 7311 7312 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) 7313 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); 7314 7315 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) 7316 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); 7317 7318 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) 7319 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); 7320 7321 else 7322 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); 7323 7324 case REAL_TYPE: 7325 /* If this is a range type, consider it to be the underlying 7326 type. */ 7327 if (TREE_TYPE (type) != 0) 7328 break; 7329 7330 /* Carefully distinguish all the standard types of C, 7331 without messing up if the language is not C. */ 7332 7333 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) 7334 return (qualifiers | 6); 7335 7336 else 7337 return (qualifiers | 7); 7338 7339 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ 7340 /* ??? We need to distinguish between double and float complex types, 7341 but I don't know how yet because I can't reach this code from 7342 existing front-ends. */ 7343 return (qualifiers | 7); /* Who knows? */ 7344 7345 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ 7346 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ 7347 case FILE_TYPE: /* GNU Pascal FILE type. */ 7348 case SET_TYPE: /* GNU Pascal SET type. */ 7349 case LANG_TYPE: /* ? */ 7350 return qualifiers; 7351 7352 default: 7353 abort (); /* Not a type! */ 7354 } 7355 } 7356 7357 return qualifiers; 7358} 7359 7360/* Nested function support. */ 7361 7362/* Emit RTL insns to initialize the variable parts of a trampoline. 7363 FNADDR is an RTX for the address of the function's pure code. 7364 CXT is an RTX for the static chain value for the function. 7365 7366 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi 7367 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes 7368 (to store insns). This is a bit excessive. Perhaps a different 7369 mechanism would be better here. 7370 7371 Emit enough FLUSH insns to synchronize the data and instruction caches. */ 7372 7373void 7374sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) 7375{ 7376 /* SPARC 32-bit trampoline: 7377 7378 sethi %hi(fn), %g1 7379 sethi %hi(static), %g2 7380 jmp %g1+%lo(fn) 7381 or %g2, %lo(static), %g2 7382 7383 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii 7384 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii 7385 */ 7386 7387 emit_move_insn 7388 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), 7389 expand_binop (SImode, ior_optab, 7390 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 7391 size_int (10), 0, 1), 7392 GEN_INT (trunc_int_for_mode (0x03000000, SImode)), 7393 NULL_RTX, 1, OPTAB_DIRECT)); 7394 7395 emit_move_insn 7396 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), 7397 expand_binop (SImode, ior_optab, 7398 expand_shift (RSHIFT_EXPR, SImode, cxt, 7399 size_int (10), 0, 1), 7400 GEN_INT (trunc_int_for_mode (0x05000000, SImode)), 7401 NULL_RTX, 1, OPTAB_DIRECT)); 7402 7403 emit_move_insn 7404 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), 7405 expand_binop (SImode, ior_optab, 7406 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), 7407 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), 7408 NULL_RTX, 1, OPTAB_DIRECT)); 7409 7410 emit_move_insn 7411 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), 7412 expand_binop (SImode, ior_optab, 7413 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), 7414 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), 7415 NULL_RTX, 1, OPTAB_DIRECT)); 7416 7417 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is 7418 aligned on a 16 byte boundary so one flush clears it all. */ 7419 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); 7420 if (sparc_cpu != PROCESSOR_ULTRASPARC 7421 && sparc_cpu != PROCESSOR_ULTRASPARC3) 7422 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, 7423 plus_constant (tramp, 8))))); 7424 7425 /* Call __enable_execute_stack after writing onto the stack to make sure 7426 the stack address is accessible. */ 7427#ifdef ENABLE_EXECUTE_STACK 7428 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), 7429 LCT_NORMAL, VOIDmode, 1, tramp, Pmode); 7430#endif 7431 7432} 7433 7434/* The 64-bit version is simpler because it makes more sense to load the 7435 values as "immediate" data out of the trampoline. It's also easier since 7436 we can read the PC without clobbering a register. */ 7437 7438void 7439sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) 7440{ 7441 /* SPARC 64-bit trampoline: 7442 7443 rd %pc, %g1 7444 ldx [%g1+24], %g5 7445 jmp %g5 7446 ldx [%g1+16], %g5 7447 +16 bytes data 7448 */ 7449 7450 emit_move_insn (gen_rtx_MEM (SImode, tramp), 7451 GEN_INT (trunc_int_for_mode (0x83414000, SImode))); 7452 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), 7453 GEN_INT (trunc_int_for_mode (0xca586018, SImode))); 7454 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), 7455 GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); 7456 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), 7457 GEN_INT (trunc_int_for_mode (0xca586010, SImode))); 7458 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); 7459 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); 7460 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); 7461 7462 if (sparc_cpu != PROCESSOR_ULTRASPARC 7463 && sparc_cpu != PROCESSOR_ULTRASPARC3) 7464 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); 7465 7466 /* Call __enable_execute_stack after writing onto the stack to make sure 7467 the stack address is accessible. */ 7468#ifdef ENABLE_EXECUTE_STACK 7469 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), 7470 LCT_NORMAL, VOIDmode, 1, tramp, Pmode); 7471#endif 7472} 7473 7474/* Subroutines to support a flat (single) register window calling 7475 convention. */ 7476 7477/* Single-register window sparc stack frames look like: 7478 7479 Before call After call 7480 +-----------------------+ +-----------------------+ 7481 high | | | | 7482 mem | caller's temps. | | caller's temps. | 7483 | | | | 7484 +-----------------------+ +-----------------------+ 7485 | | | | 7486 | arguments on stack. | | arguments on stack. | 7487 | | | | 7488 +-----------------------+FP+92->+-----------------------+ 7489 | 6 words to save | | 6 words to save | 7490 | arguments passed | | arguments passed | 7491 | in registers, even | | in registers, even | 7492 | if not passed. | | if not passed. | 7493 SP+68->+-----------------------+FP+68->+-----------------------+ 7494 | 1 word struct addr | | 1 word struct addr | 7495 +-----------------------+FP+64->+-----------------------+ 7496 | | | | 7497 | 16 word reg save area | | 16 word reg save area | 7498 | | | | 7499 SP->+-----------------------+ FP->+-----------------------+ 7500 | 4 word area for | 7501 | fp/alu reg moves | 7502 FP-16->+-----------------------+ 7503 | | 7504 | local variables | 7505 | | 7506 +-----------------------+ 7507 | | 7508 | fp register save | 7509 | | 7510 +-----------------------+ 7511 | | 7512 | gp register save | 7513 | | 7514 +-----------------------+ 7515 | | 7516 | alloca allocations | 7517 | | 7518 +-----------------------+ 7519 | | 7520 | arguments on stack | 7521 | | 7522 SP+92->+-----------------------+ 7523 | 6 words to save | 7524 | arguments passed | 7525 | in registers, even | 7526 low | if not passed. | 7527 memory SP+68->+-----------------------+ 7528 | 1 word struct addr | 7529 SP+64->+-----------------------+ 7530 | | 7531 I 16 word reg save area | 7532 | | 7533 SP->+-----------------------+ */ 7534 7535/* Structure to be filled in by sparc_flat_compute_frame_size with register 7536 save masks, and offsets for the current function. */ 7537 7538struct sparc_frame_info 7539{ 7540 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */ 7541 HOST_WIDE_INT var_size; /* # bytes that variables take up. */ 7542 int args_size; /* # bytes that outgoing arguments take up. */ 7543 int extra_size; /* # bytes of extra gunk. */ 7544 int gp_reg_size; /* # bytes needed to store gp regs. */ 7545 int fp_reg_size; /* # bytes needed to store fp regs. */ 7546 unsigned long gmask; /* Mask of saved gp registers. */ 7547 unsigned long fmask; /* Mask of saved fp registers. */ 7548 int reg_offset; /* Offset from new sp to store regs. */ 7549 int initialized; /* Nonzero if frame size already calculated. */ 7550}; 7551 7552/* Current frame information calculated by sparc_flat_compute_frame_size. */ 7553struct sparc_frame_info current_frame_info; 7554 7555/* Zero structure to initialize current_frame_info. */ 7556struct sparc_frame_info zero_frame_info; 7557 7558#define RETURN_ADDR_REGNUM 15 7559#define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM)) 7560#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) 7561 7562/* Tell prologue and epilogue if register REGNO should be saved / restored. */ 7563 7564static bool 7565sparc_flat_must_save_register_p (int regno) 7566{ 7567 /* General case: call-saved registers live at some point. */ 7568 if (!call_used_regs[regno] && regs_ever_live[regno]) 7569 return true; 7570 7571 /* Frame pointer register (%i7) if needed. */ 7572 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) 7573 return true; 7574 7575 /* PIC register (%l7) if needed. */ 7576 if (regno == (int) PIC_OFFSET_TABLE_REGNUM 7577 && flag_pic && current_function_uses_pic_offset_table) 7578 return true; 7579 7580 /* Return address register (%o7) if needed. */ 7581 if (regno == RETURN_ADDR_REGNUM 7582 && (regs_ever_live[RETURN_ADDR_REGNUM] 7583 /* When the PIC offset table is used, the PIC register 7584 is set by using a bare call that clobbers %o7. */ 7585 || (flag_pic && current_function_uses_pic_offset_table))) 7586 return true; 7587 7588 return false; 7589} 7590 7591/* Return the bytes needed to compute the frame pointer from the current 7592 stack pointer. */ 7593 7594HOST_WIDE_INT 7595sparc_flat_compute_frame_size (HOST_WIDE_INT size) 7596 /* # of var. bytes allocated. */ 7597{ 7598 int regno; 7599 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */ 7600 HOST_WIDE_INT var_size; /* # bytes that variables take up. */ 7601 int args_size; /* # bytes that outgoing arguments take up. */ 7602 int extra_size; /* # extra bytes. */ 7603 int gp_reg_size; /* # bytes needed to store gp regs. */ 7604 int fp_reg_size; /* # bytes needed to store fp regs. */ 7605 unsigned long gmask; /* Mask of saved gp registers. */ 7606 unsigned long fmask; /* Mask of saved fp registers. */ 7607 int reg_offset; /* Offset to register save area. */ 7608 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ 7609 7610 /* This is the size of the 16 word reg save area, 1 word struct addr 7611 area, and 4 word fp/alu register copy area. */ 7612 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); 7613 var_size = size; 7614 gp_reg_size = 0; 7615 fp_reg_size = 0; 7616 gmask = 0; 7617 fmask = 0; 7618 reg_offset = 0; 7619 need_aligned_p = 0; 7620 7621 args_size = 0; 7622 if (!leaf_function_p ()) 7623 { 7624 /* Also include the size needed for the 6 parameter registers. */ 7625 args_size = current_function_outgoing_args_size + 24; 7626 } 7627 total_size = var_size + args_size; 7628 7629 /* Calculate space needed for gp registers. */ 7630 for (regno = 1; regno <= 31; regno++) 7631 { 7632 if (sparc_flat_must_save_register_p (regno)) 7633 { 7634 /* If we need to save two regs in a row, ensure there's room to bump 7635 up the address to align it to a doubleword boundary. */ 7636 if ((regno & 0x1) == 0 && sparc_flat_must_save_register_p (regno+1)) 7637 { 7638 if (gp_reg_size % 8 != 0) 7639 gp_reg_size += 4; 7640 gp_reg_size += 2 * UNITS_PER_WORD; 7641 gmask |= 3 << regno; 7642 regno++; 7643 need_aligned_p = 1; 7644 } 7645 else 7646 { 7647 gp_reg_size += UNITS_PER_WORD; 7648 gmask |= 1 << regno; 7649 } 7650 } 7651 } 7652 7653 /* Calculate space needed for fp registers. */ 7654 for (regno = 32; regno <= 63; regno++) 7655 { 7656 if (regs_ever_live[regno] && !call_used_regs[regno]) 7657 { 7658 fp_reg_size += UNITS_PER_WORD; 7659 fmask |= 1 << (regno - 32); 7660 } 7661 } 7662 7663 if (gmask || fmask) 7664 { 7665 int n; 7666 reg_offset = FIRST_PARM_OFFSET(0) + args_size; 7667 /* Ensure save area is 8 byte aligned if we need it. */ 7668 n = reg_offset % 8; 7669 if (need_aligned_p && n != 0) 7670 { 7671 total_size += 8 - n; 7672 reg_offset += 8 - n; 7673 } 7674 total_size += gp_reg_size + fp_reg_size; 7675 } 7676 7677 /* If we must allocate a stack frame at all, we must also allocate 7678 room for register window spillage, so as to be binary compatible 7679 with libraries and operating systems that do not use -mflat. */ 7680 if (total_size > 0) 7681 total_size += extra_size; 7682 else 7683 extra_size = 0; 7684 7685 total_size = SPARC_STACK_ALIGN (total_size); 7686 7687 /* Save other computed information. */ 7688 current_frame_info.total_size = total_size; 7689 current_frame_info.var_size = var_size; 7690 current_frame_info.args_size = args_size; 7691 current_frame_info.extra_size = extra_size; 7692 current_frame_info.gp_reg_size = gp_reg_size; 7693 current_frame_info.fp_reg_size = fp_reg_size; 7694 current_frame_info.gmask = gmask; 7695 current_frame_info.fmask = fmask; 7696 current_frame_info.reg_offset = reg_offset; 7697 current_frame_info.initialized = reload_completed; 7698 7699 /* Ok, we're done. */ 7700 return total_size; 7701} 7702 7703/* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset 7704 OFFSET. 7705 7706 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for 7707 appropriate alignment and use DOUBLEWORD_OP when we can. We assume 7708 [BASE_REG+OFFSET] will always be a valid address. 7709 7710 WORD_OP is either "st" for save, "ld" for restore. 7711 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ 7712 7713static void 7714sparc_flat_save_restore (FILE *file, const char *base_reg, int offset, 7715 unsigned long gmask, unsigned long fmask, 7716 const char *word_op, const char *doubleword_op, 7717 HOST_WIDE_INT base_offset) 7718{ 7719 int regno; 7720 7721 if (gmask == 0 && fmask == 0) 7722 return; 7723 7724 /* Save registers starting from high to low. We've already saved the 7725 previous frame pointer and previous return address for the debugger's 7726 sake. The debugger allows us to not need a nop in the epilog if at least 7727 one register is reloaded in addition to return address. */ 7728 7729 if (gmask) 7730 { 7731 for (regno = 1; regno <= 31; regno++) 7732 { 7733 if ((gmask & (1L << regno)) != 0) 7734 { 7735 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) 7736 { 7737 /* We can save two registers in a row. If we're not at a 7738 double word boundary, move to one. 7739 sparc_flat_compute_frame_size ensures there's room to do 7740 this. */ 7741 if (offset % 8 != 0) 7742 offset += UNITS_PER_WORD; 7743 7744 if (word_op[0] == 's') 7745 { 7746 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7747 doubleword_op, reg_names[regno], 7748 base_reg, offset); 7749 if (dwarf2out_do_frame ()) 7750 { 7751 char *l = dwarf2out_cfi_label (); 7752 dwarf2out_reg_save (l, regno, offset + base_offset); 7753 dwarf2out_reg_save 7754 (l, regno+1, offset+base_offset + UNITS_PER_WORD); 7755 } 7756 } 7757 else 7758 fprintf (file, "\t%s\t[%s+%d], %s\n", 7759 doubleword_op, base_reg, offset, 7760 reg_names[regno]); 7761 7762 offset += 2 * UNITS_PER_WORD; 7763 regno++; 7764 } 7765 else 7766 { 7767 if (word_op[0] == 's') 7768 { 7769 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7770 word_op, reg_names[regno], 7771 base_reg, offset); 7772 if (dwarf2out_do_frame ()) 7773 dwarf2out_reg_save ("", regno, offset + base_offset); 7774 } 7775 else 7776 fprintf (file, "\t%s\t[%s+%d], %s\n", 7777 word_op, base_reg, offset, reg_names[regno]); 7778 7779 offset += UNITS_PER_WORD; 7780 } 7781 } 7782 } 7783 } 7784 7785 if (fmask) 7786 { 7787 for (regno = 32; regno <= 63; regno++) 7788 { 7789 if ((fmask & (1L << (regno - 32))) != 0) 7790 { 7791 if (word_op[0] == 's') 7792 { 7793 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7794 word_op, reg_names[regno], 7795 base_reg, offset); 7796 if (dwarf2out_do_frame ()) 7797 dwarf2out_reg_save ("", regno, offset + base_offset); 7798 } 7799 else 7800 fprintf (file, "\t%s\t[%s+%d], %s\n", 7801 word_op, base_reg, offset, reg_names[regno]); 7802 7803 offset += UNITS_PER_WORD; 7804 } 7805 } 7806 } 7807} 7808 7809/* Set up the stack and frame (if desired) for the function. */ 7810 7811static void 7812sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size) 7813{ 7814 const char *sp_str = reg_names[STACK_POINTER_REGNUM]; 7815 unsigned long gmask = current_frame_info.gmask; 7816 7817 sparc_output_scratch_registers (file); 7818 7819 /* This is only for the human reader. */ 7820 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); 7821 fprintf (file, "\t%s# vars= "HOST_WIDE_INT_PRINT_DEC", " 7822 "regs= %d/%d, args= %d, extra= %d\n", 7823 ASM_COMMENT_START, 7824 current_frame_info.var_size, 7825 current_frame_info.gp_reg_size / 4, 7826 current_frame_info.fp_reg_size / 4, 7827 current_function_outgoing_args_size, 7828 current_frame_info.extra_size); 7829 7830 size = SPARC_STACK_ALIGN (size); 7831 size = (! current_frame_info.initialized 7832 ? sparc_flat_compute_frame_size (size) 7833 : current_frame_info.total_size); 7834 7835 /* These cases shouldn't happen. Catch them now. */ 7836 if (size == 0 && (gmask || current_frame_info.fmask)) 7837 abort (); 7838 7839 /* Allocate our stack frame by decrementing %sp. 7840 At present, the only algorithm gdb can use to determine if this is a 7841 flat frame is if we always set %i7 if we set %sp. This can be optimized 7842 in the future by putting in some sort of debugging information that says 7843 this is a `flat' function. However, there is still the case of debugging 7844 code without such debugging information (including cases where most fns 7845 have such info, but there is one that doesn't). So, always do this now 7846 so we don't get a lot of code out there that gdb can't handle. 7847 If the frame pointer isn't needn't then that's ok - gdb won't be able to 7848 distinguish us from a non-flat function but there won't (and shouldn't) 7849 be any differences anyway. The return pc is saved (if necessary) right 7850 after %i7 so gdb won't have to look too far to find it. */ 7851 if (size > 0) 7852 { 7853 int reg_offset = current_frame_info.reg_offset; 7854 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; 7855 static const char *const t1_str = "%g1"; 7856 7857 /* Things get a little tricky if local variables take up more than ~4096 7858 bytes and outgoing arguments take up more than ~4096 bytes. When that 7859 happens, the register save area can't be accessed from either end of 7860 the frame. Handle this by decrementing %sp to the start of the gp 7861 register save area, save the regs, update %i7, and then set %sp to its 7862 final value. Given that we only have one scratch register to play 7863 with it is the cheapest solution, and it helps gdb out as it won't 7864 slow down recognition of flat functions. 7865 Don't change the order of insns emitted here without checking with 7866 the gdb folk first. */ 7867 7868 /* Is the entire register save area offsettable from %sp? */ 7869 if (reg_offset < 4096 - 64 * UNITS_PER_WORD) 7870 { 7871 if (size <= 4096) 7872 { 7873 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n", 7874 sp_str, size, sp_str); 7875 if (gmask & HARD_FRAME_POINTER_MASK) 7876 { 7877 fprintf (file, "\tst\t%s, [%s+%d]\n", 7878 fp_str, sp_str, reg_offset); 7879 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s" 7880 "\t%s# set up frame pointer\n", 7881 sp_str, size, fp_str, ASM_COMMENT_START); 7882 reg_offset += 4; 7883 } 7884 } 7885 else 7886 { 7887 build_big_number (file, size, t1_str); 7888 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str); 7889 if (gmask & HARD_FRAME_POINTER_MASK) 7890 { 7891 fprintf (file, "\tst\t%s, [%s+%d]\n", 7892 fp_str, sp_str, reg_offset); 7893 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", 7894 sp_str, t1_str, fp_str, ASM_COMMENT_START); 7895 reg_offset += 4; 7896 } 7897 } 7898 if (dwarf2out_do_frame ()) 7899 { 7900 char *l = dwarf2out_cfi_label (); 7901 if (gmask & HARD_FRAME_POINTER_MASK) 7902 { 7903 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, 7904 reg_offset - 4 - size); 7905 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); 7906 } 7907 else 7908 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); 7909 } 7910 if (gmask & RETURN_ADDR_MASK) 7911 { 7912 fprintf (file, "\tst\t%s, [%s+%d]\n", 7913 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); 7914 if (dwarf2out_do_frame ()) 7915 dwarf2out_return_save ("", reg_offset - size); 7916 reg_offset += 4; 7917 } 7918 sparc_flat_save_restore (file, sp_str, reg_offset, 7919 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7920 current_frame_info.fmask, 7921 "st", "std", -size); 7922 } 7923 else 7924 { 7925 /* Subtract %sp in two steps, but make sure there is always a 7926 64-byte register save area, and %sp is properly aligned. */ 7927 7928 /* Amount to decrement %sp by, the first time. */ 7929 HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16; 7930 7931 /* Amount to decrement %sp by, the second time. */ 7932 HOST_WIDE_INT size2 = size - size1; 7933 7934 /* Offset to register save area from %sp after first decrement. */ 7935 int offset = (int)(size1 - (size - reg_offset)); 7936 7937 if (size1 <= 4096) 7938 { 7939 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n", 7940 sp_str, size1, sp_str); 7941 if (gmask & HARD_FRAME_POINTER_MASK) 7942 { 7943 fprintf (file, "\tst\t%s, [%s+%d]\n" 7944 "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s" 7945 "\t%s# set up frame pointer\n", 7946 fp_str, sp_str, offset, sp_str, size1, 7947 fp_str, ASM_COMMENT_START); 7948 offset += 4; 7949 } 7950 } 7951 else 7952 { 7953 build_big_number (file, size1, t1_str); 7954 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str); 7955 if (gmask & HARD_FRAME_POINTER_MASK) 7956 { 7957 fprintf (file, "\tst\t%s, [%s+%d]\n" 7958 "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", 7959 fp_str, sp_str, offset, sp_str, t1_str, 7960 fp_str, ASM_COMMENT_START); 7961 offset += 4; 7962 } 7963 } 7964 if (dwarf2out_do_frame ()) 7965 { 7966 char *l = dwarf2out_cfi_label (); 7967 if (gmask & HARD_FRAME_POINTER_MASK) 7968 { 7969 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, 7970 offset - 4 - size1); 7971 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); 7972 } 7973 else 7974 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); 7975 } 7976 if (gmask & RETURN_ADDR_MASK) 7977 { 7978 fprintf (file, "\tst\t%s, [%s+%d]\n", 7979 reg_names[RETURN_ADDR_REGNUM], sp_str, offset); 7980 if (dwarf2out_do_frame ()) 7981 /* offset - size1 == reg_offset - size 7982 if reg_offset were updated above like offset. */ 7983 dwarf2out_return_save ("", offset - size1); 7984 offset += 4; 7985 } 7986 sparc_flat_save_restore (file, sp_str, offset, 7987 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7988 current_frame_info.fmask, 7989 "st", "std", -size1); 7990 if (size2 <= 4096) 7991 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n", 7992 sp_str, size2, sp_str); 7993 else 7994 { 7995 build_big_number (file, size2, t1_str); 7996 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str); 7997 } 7998 if (dwarf2out_do_frame ()) 7999 if (! (gmask & HARD_FRAME_POINTER_MASK)) 8000 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); 8001 } 8002 } 8003 8004 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); 8005} 8006 8007/* Do any necessary cleanup after a function to restore stack, frame, 8008 and regs. */ 8009 8010static void 8011sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size) 8012{ 8013 rtx epilogue_delay = current_function_epilogue_delay_list; 8014 int noepilogue = FALSE; 8015 8016 /* This is only for the human reader. */ 8017 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); 8018 8019 /* The epilogue does not depend on any registers, but the stack 8020 registers, so we assume that if we have 1 pending nop, it can be 8021 ignored, and 2 it must be filled (2 nops occur for integer 8022 multiply and divide). */ 8023 8024 size = SPARC_STACK_ALIGN (size); 8025 size = (!current_frame_info.initialized 8026 ? sparc_flat_compute_frame_size (size) 8027 : current_frame_info.total_size); 8028 8029 if (size == 0 && epilogue_delay == 0) 8030 { 8031 rtx insn = get_last_insn (); 8032 8033 /* If the last insn was a BARRIER, we don't have to write any code 8034 because a jump (aka return) was put there. */ 8035 if (GET_CODE (insn) == NOTE) 8036 insn = prev_nonnote_insn (insn); 8037 if (insn && GET_CODE (insn) == BARRIER) 8038 noepilogue = TRUE; 8039 } 8040 8041 if (!noepilogue) 8042 { 8043 int reg_offset = current_frame_info.reg_offset; 8044 int reg_offset1; 8045 const char *const sp_str = reg_names[STACK_POINTER_REGNUM]; 8046 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; 8047 static const char *const t1_str = "%g1"; 8048 8049 /* In the reload sequence, we don't need to fill the load delay 8050 slots for most of the loads, also see if we can fill the final 8051 delay slot if not otherwise filled by the reload sequence. */ 8052 8053 if (size > 4096) 8054 build_big_number (file, size, t1_str); 8055 8056 if (frame_pointer_needed) 8057 { 8058 if (size > 4096) 8059 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", 8060 fp_str, t1_str, sp_str, ASM_COMMENT_START); 8061 else 8062 fprintf (file,"\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s" 8063 "\t\t%s# sp not trusted here\n", 8064 fp_str, size, sp_str, ASM_COMMENT_START); 8065 } 8066 8067 /* Is the entire register save area offsettable from %sp? */ 8068 if (reg_offset < 4096 - 64 * UNITS_PER_WORD) 8069 { 8070 reg_offset1 = 0; 8071 } 8072 else 8073 { 8074 /* Restore %sp in two steps, but make sure there is always a 8075 64-byte register save area, and %sp is properly aligned. */ 8076 8077 /* Amount to increment %sp by, the first time. */ 8078 reg_offset1 = ((reg_offset - 64 - 16) + 15) & -16; 8079 8080 /* Offset to register save area from %sp. */ 8081 reg_offset = reg_offset1 - reg_offset; 8082 8083 if (reg_offset1 > 4096) 8084 { 8085 build_big_number (file, reg_offset1, t1_str); 8086 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); 8087 } 8088 else 8089 fprintf (file, "\tsub\t%s, -%d, %s\n", sp_str, reg_offset1, sp_str); 8090 } 8091 8092 /* We must restore the frame pointer and return address reg first 8093 because they are treated specially by the prologue output code. */ 8094 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK) 8095 { 8096 fprintf (file, "\tld\t[%s+%d], %s\n", 8097 sp_str, reg_offset, fp_str); 8098 reg_offset += 4; 8099 } 8100 if (current_frame_info.gmask & RETURN_ADDR_MASK) 8101 { 8102 fprintf (file, "\tld\t[%s+%d], %s\n", 8103 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]); 8104 reg_offset += 4; 8105 } 8106 8107 /* Restore any remaining saved registers. */ 8108 sparc_flat_save_restore (file, sp_str, reg_offset, 8109 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 8110 current_frame_info.fmask, 8111 "ld", "ldd", 0); 8112 8113 /* If we had to increment %sp in two steps, record it so the second 8114 restoration in the epilogue finishes up. */ 8115 if (reg_offset1 > 0) 8116 { 8117 size -= reg_offset1; 8118 if (size > 4096) 8119 build_big_number (file, size, t1_str); 8120 } 8121 8122 if (current_function_returns_struct) 8123 fprintf (file, "\tjmp\t%%o7+12\n"); 8124 else 8125 fprintf (file, "\tretl\n"); 8126 8127 /* If the only register saved is the return address, we need a 8128 nop, unless we have an instruction to put into it. Otherwise 8129 we don't since reloading multiple registers doesn't reference 8130 the register being loaded. */ 8131 8132 if (epilogue_delay) 8133 { 8134 if (size) 8135 abort (); 8136 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1, NULL); 8137 } 8138 8139 else if (size > 4096) 8140 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); 8141 8142 else if (size > 0) 8143 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n", 8144 sp_str, size, sp_str); 8145 8146 else 8147 fprintf (file, "\tnop\n"); 8148 } 8149 8150 /* Reset state info for each function. */ 8151 current_frame_info = zero_frame_info; 8152 8153 sparc_output_deferred_case_vectors (); 8154} 8155 8156/* Define the number of delay slots needed for the function epilogue. 8157 8158 On the sparc, we need a slot if either no stack has been allocated, 8159 or the only register saved is the return register. */ 8160 8161int 8162sparc_flat_epilogue_delay_slots (void) 8163{ 8164 if (!current_frame_info.initialized) 8165 (void) sparc_flat_compute_frame_size (get_frame_size ()); 8166 8167 if (current_frame_info.total_size == 0) 8168 return 1; 8169 8170 return 0; 8171} 8172 8173/* Return true if TRIAL is a valid insn for the epilogue delay slot. 8174 Any single length instruction which doesn't reference the stack or frame 8175 pointer is OK. */ 8176 8177int 8178sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED) 8179{ 8180 rtx pat = PATTERN (trial); 8181 8182 if (get_attr_length (trial) != 1) 8183 return 0; 8184 8185 if (! reg_mentioned_p (stack_pointer_rtx, pat) 8186 && ! reg_mentioned_p (frame_pointer_rtx, pat)) 8187 return 1; 8188 8189 return 0; 8190} 8191 8192/* Adjust the cost of a scheduling dependency. Return the new cost of 8193 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ 8194 8195static int 8196supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) 8197{ 8198 enum attr_type insn_type; 8199 8200 if (! recog_memoized (insn)) 8201 return 0; 8202 8203 insn_type = get_attr_type (insn); 8204 8205 if (REG_NOTE_KIND (link) == 0) 8206 { 8207 /* Data dependency; DEP_INSN writes a register that INSN reads some 8208 cycles later. */ 8209 8210 /* if a load, then the dependence must be on the memory address; 8211 add an extra "cycle". Note that the cost could be two cycles 8212 if the reg was written late in an instruction group; we ca not tell 8213 here. */ 8214 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) 8215 return cost + 3; 8216 8217 /* Get the delay only if the address of the store is the dependence. */ 8218 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) 8219 { 8220 rtx pat = PATTERN(insn); 8221 rtx dep_pat = PATTERN (dep_insn); 8222 8223 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 8224 return cost; /* This should not happen! */ 8225 8226 /* The dependency between the two instructions was on the data that 8227 is being stored. Assume that this implies that the address of the 8228 store is not dependent. */ 8229 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 8230 return cost; 8231 8232 return cost + 3; /* An approximation. */ 8233 } 8234 8235 /* A shift instruction cannot receive its data from an instruction 8236 in the same cycle; add a one cycle penalty. */ 8237 if (insn_type == TYPE_SHIFT) 8238 return cost + 3; /* Split before cascade into shift. */ 8239 } 8240 else 8241 { 8242 /* Anti- or output- dependency; DEP_INSN reads/writes a register that 8243 INSN writes some cycles later. */ 8244 8245 /* These are only significant for the fpu unit; writing a fp reg before 8246 the fpu has finished with it stalls the processor. */ 8247 8248 /* Reusing an integer register causes no problems. */ 8249 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 8250 return 0; 8251 } 8252 8253 return cost; 8254} 8255 8256static int 8257hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) 8258{ 8259 enum attr_type insn_type, dep_type; 8260 rtx pat = PATTERN(insn); 8261 rtx dep_pat = PATTERN (dep_insn); 8262 8263 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) 8264 return cost; 8265 8266 insn_type = get_attr_type (insn); 8267 dep_type = get_attr_type (dep_insn); 8268 8269 switch (REG_NOTE_KIND (link)) 8270 { 8271 case 0: 8272 /* Data dependency; DEP_INSN writes a register that INSN reads some 8273 cycles later. */ 8274 8275 switch (insn_type) 8276 { 8277 case TYPE_STORE: 8278 case TYPE_FPSTORE: 8279 /* Get the delay iff the address of the store is the dependence. */ 8280 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 8281 return cost; 8282 8283 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 8284 return cost; 8285 return cost + 3; 8286 8287 case TYPE_LOAD: 8288 case TYPE_SLOAD: 8289 case TYPE_FPLOAD: 8290 /* If a load, then the dependence must be on the memory address. If 8291 the addresses aren't equal, then it might be a false dependency */ 8292 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) 8293 { 8294 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET 8295 || GET_CODE (SET_DEST (dep_pat)) != MEM 8296 || GET_CODE (SET_SRC (pat)) != MEM 8297 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), 8298 XEXP (SET_SRC (pat), 0))) 8299 return cost + 2; 8300 8301 return cost + 8; 8302 } 8303 break; 8304 8305 case TYPE_BRANCH: 8306 /* Compare to branch latency is 0. There is no benefit from 8307 separating compare and branch. */ 8308 if (dep_type == TYPE_COMPARE) 8309 return 0; 8310 /* Floating point compare to branch latency is less than 8311 compare to conditional move. */ 8312 if (dep_type == TYPE_FPCMP) 8313 return cost - 1; 8314 break; 8315 default: 8316 break; 8317 } 8318 break; 8319 8320 case REG_DEP_ANTI: 8321 /* Anti-dependencies only penalize the fpu unit. */ 8322 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 8323 return 0; 8324 break; 8325 8326 default: 8327 break; 8328 } 8329 8330 return cost; 8331} 8332 8333static int 8334sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost) 8335{ 8336 switch (sparc_cpu) 8337 { 8338 case PROCESSOR_SUPERSPARC: 8339 cost = supersparc_adjust_cost (insn, link, dep, cost); 8340 break; 8341 case PROCESSOR_HYPERSPARC: 8342 case PROCESSOR_SPARCLITE86X: 8343 cost = hypersparc_adjust_cost (insn, link, dep, cost); 8344 break; 8345 default: 8346 break; 8347 } 8348 return cost; 8349} 8350 8351static void 8352sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED, 8353 int sched_verbose ATTRIBUTE_UNUSED, 8354 int max_ready ATTRIBUTE_UNUSED) 8355{ 8356} 8357 8358static int 8359sparc_use_dfa_pipeline_interface (void) 8360{ 8361 if ((1 << sparc_cpu) & 8362 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) | 8363 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | 8364 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) | 8365 (1 << PROCESSOR_ULTRASPARC3))) 8366 return 1; 8367 return 0; 8368} 8369 8370static int 8371sparc_use_sched_lookahead (void) 8372{ 8373 if (sparc_cpu == PROCESSOR_ULTRASPARC 8374 || sparc_cpu == PROCESSOR_ULTRASPARC3) 8375 return 4; 8376 if ((1 << sparc_cpu) & 8377 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | 8378 (1 << PROCESSOR_SPARCLITE86X))) 8379 return 3; 8380 return 0; 8381} 8382 8383static int 8384sparc_issue_rate (void) 8385{ 8386 switch (sparc_cpu) 8387 { 8388 default: 8389 return 1; 8390 case PROCESSOR_V9: 8391 /* Assume V9 processors are capable of at least dual-issue. */ 8392 return 2; 8393 case PROCESSOR_SUPERSPARC: 8394 return 3; 8395 case PROCESSOR_HYPERSPARC: 8396 case PROCESSOR_SPARCLITE86X: 8397 return 2; 8398 case PROCESSOR_ULTRASPARC: 8399 case PROCESSOR_ULTRASPARC3: 8400 return 4; 8401 } 8402} 8403 8404static int 8405set_extends (rtx insn) 8406{ 8407 register rtx pat = PATTERN (insn); 8408 8409 switch (GET_CODE (SET_SRC (pat))) 8410 { 8411 /* Load and some shift instructions zero extend. */ 8412 case MEM: 8413 case ZERO_EXTEND: 8414 /* sethi clears the high bits */ 8415 case HIGH: 8416 /* LO_SUM is used with sethi. sethi cleared the high 8417 bits and the values used with lo_sum are positive */ 8418 case LO_SUM: 8419 /* Store flag stores 0 or 1 */ 8420 case LT: case LTU: 8421 case GT: case GTU: 8422 case LE: case LEU: 8423 case GE: case GEU: 8424 case EQ: 8425 case NE: 8426 return 1; 8427 case AND: 8428 { 8429 rtx op0 = XEXP (SET_SRC (pat), 0); 8430 rtx op1 = XEXP (SET_SRC (pat), 1); 8431 if (GET_CODE (op1) == CONST_INT) 8432 return INTVAL (op1) >= 0; 8433 if (GET_CODE (op0) != REG) 8434 return 0; 8435 if (sparc_check_64 (op0, insn) == 1) 8436 return 1; 8437 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 8438 } 8439 case IOR: 8440 case XOR: 8441 { 8442 rtx op0 = XEXP (SET_SRC (pat), 0); 8443 rtx op1 = XEXP (SET_SRC (pat), 1); 8444 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) 8445 return 0; 8446 if (GET_CODE (op1) == CONST_INT) 8447 return INTVAL (op1) >= 0; 8448 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 8449 } 8450 case LSHIFTRT: 8451 return GET_MODE (SET_SRC (pat)) == SImode; 8452 /* Positive integers leave the high bits zero. */ 8453 case CONST_DOUBLE: 8454 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000); 8455 case CONST_INT: 8456 return ! (INTVAL (SET_SRC (pat)) & 0x80000000); 8457 case ASHIFTRT: 8458 case SIGN_EXTEND: 8459 return - (GET_MODE (SET_SRC (pat)) == SImode); 8460 case REG: 8461 return sparc_check_64 (SET_SRC (pat), insn); 8462 default: 8463 return 0; 8464 } 8465} 8466 8467/* We _ought_ to have only one kind per function, but... */ 8468static GTY(()) rtx sparc_addr_diff_list; 8469static GTY(()) rtx sparc_addr_list; 8470 8471void 8472sparc_defer_case_vector (rtx lab, rtx vec, int diff) 8473{ 8474 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); 8475 if (diff) 8476 sparc_addr_diff_list 8477 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); 8478 else 8479 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); 8480} 8481 8482static void 8483sparc_output_addr_vec (rtx vec) 8484{ 8485 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 8486 int idx, vlen = XVECLEN (body, 0); 8487 8488#ifdef ASM_OUTPUT_ADDR_VEC_START 8489 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 8490#endif 8491 8492#ifdef ASM_OUTPUT_CASE_LABEL 8493 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 8494 NEXT_INSN (lab)); 8495#else 8496 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 8497#endif 8498 8499 for (idx = 0; idx < vlen; idx++) 8500 { 8501 ASM_OUTPUT_ADDR_VEC_ELT 8502 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); 8503 } 8504 8505#ifdef ASM_OUTPUT_ADDR_VEC_END 8506 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 8507#endif 8508} 8509 8510static void 8511sparc_output_addr_diff_vec (rtx vec) 8512{ 8513 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 8514 rtx base = XEXP (XEXP (body, 0), 0); 8515 int idx, vlen = XVECLEN (body, 1); 8516 8517#ifdef ASM_OUTPUT_ADDR_VEC_START 8518 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 8519#endif 8520 8521#ifdef ASM_OUTPUT_CASE_LABEL 8522 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 8523 NEXT_INSN (lab)); 8524#else 8525 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 8526#endif 8527 8528 for (idx = 0; idx < vlen; idx++) 8529 { 8530 ASM_OUTPUT_ADDR_DIFF_ELT 8531 (asm_out_file, 8532 body, 8533 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), 8534 CODE_LABEL_NUMBER (base)); 8535 } 8536 8537#ifdef ASM_OUTPUT_ADDR_VEC_END 8538 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 8539#endif 8540} 8541 8542static void 8543sparc_output_deferred_case_vectors (void) 8544{ 8545 rtx t; 8546 int align; 8547 8548 if (sparc_addr_list == NULL_RTX 8549 && sparc_addr_diff_list == NULL_RTX) 8550 return; 8551 8552 /* Align to cache line in the function's code section. */ 8553 function_section (current_function_decl); 8554 8555 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 8556 if (align > 0) 8557 ASM_OUTPUT_ALIGN (asm_out_file, align); 8558 8559 for (t = sparc_addr_list; t ; t = XEXP (t, 1)) 8560 sparc_output_addr_vec (XEXP (t, 0)); 8561 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) 8562 sparc_output_addr_diff_vec (XEXP (t, 0)); 8563 8564 sparc_addr_list = sparc_addr_diff_list = NULL_RTX; 8565} 8566 8567/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are 8568 unknown. Return 1 if the high bits are zero, -1 if the register is 8569 sign extended. */ 8570int 8571sparc_check_64 (rtx x, rtx insn) 8572{ 8573 /* If a register is set only once it is safe to ignore insns this 8574 code does not know how to handle. The loop will either recognize 8575 the single set and return the correct value or fail to recognize 8576 it and return 0. */ 8577 int set_once = 0; 8578 rtx y = x; 8579 8580 if (GET_CODE (x) != REG) 8581 abort (); 8582 8583 if (GET_MODE (x) == DImode) 8584 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); 8585 8586 if (flag_expensive_optimizations 8587 && REG_N_SETS (REGNO (y)) == 1) 8588 set_once = 1; 8589 8590 if (insn == 0) 8591 { 8592 if (set_once) 8593 insn = get_last_insn_anywhere (); 8594 else 8595 return 0; 8596 } 8597 8598 while ((insn = PREV_INSN (insn))) 8599 { 8600 switch (GET_CODE (insn)) 8601 { 8602 case JUMP_INSN: 8603 case NOTE: 8604 break; 8605 case CODE_LABEL: 8606 case CALL_INSN: 8607 default: 8608 if (! set_once) 8609 return 0; 8610 break; 8611 case INSN: 8612 { 8613 rtx pat = PATTERN (insn); 8614 if (GET_CODE (pat) != SET) 8615 return 0; 8616 if (rtx_equal_p (x, SET_DEST (pat))) 8617 return set_extends (insn); 8618 if (y && rtx_equal_p (y, SET_DEST (pat))) 8619 return set_extends (insn); 8620 if (reg_overlap_mentioned_p (SET_DEST (pat), y)) 8621 return 0; 8622 } 8623 } 8624 } 8625 return 0; 8626} 8627 8628/* Returns assembly code to perform a DImode shift using 8629 a 64-bit global or out register on SPARC-V8+. */ 8630char * 8631sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode) 8632{ 8633 static char asm_code[60]; 8634 8635 /* The scratch register is only required when the destination 8636 register is not a 64-bit global or out register. */ 8637 if (which_alternative != 2) 8638 operands[3] = operands[0]; 8639 8640 /* We can only shift by constants <= 63. */ 8641 if (GET_CODE (operands[2]) == CONST_INT) 8642 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 8643 8644 if (GET_CODE (operands[1]) == CONST_INT) 8645 { 8646 output_asm_insn ("mov\t%1, %3", operands); 8647 } 8648 else 8649 { 8650 output_asm_insn ("sllx\t%H1, 32, %3", operands); 8651 if (sparc_check_64 (operands[1], insn) <= 0) 8652 output_asm_insn ("srl\t%L1, 0, %L1", operands); 8653 output_asm_insn ("or\t%L1, %3, %3", operands); 8654 } 8655 8656 strcpy(asm_code, opcode); 8657 8658 if (which_alternative != 2) 8659 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); 8660 else 8661 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); 8662} 8663 8664/* Output rtl to increment the profiler label LABELNO 8665 for profiling a function entry. */ 8666 8667void 8668sparc_profile_hook (int labelno) 8669{ 8670 char buf[32]; 8671 rtx lab, fun; 8672 8673 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); 8674 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 8675 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); 8676 8677 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); 8678} 8679 8680#ifdef OBJECT_FORMAT_ELF 8681static void 8682sparc_elf_asm_named_section (const char *name, unsigned int flags) 8683{ 8684 if (flags & SECTION_MERGE) 8685 { 8686 /* entsize cannot be expressed in this section attributes 8687 encoding style. */ 8688 default_elf_asm_named_section (name, flags); 8689 return; 8690 } 8691 8692 fprintf (asm_out_file, "\t.section\t\"%s\"", name); 8693 8694 if (!(flags & SECTION_DEBUG)) 8695 fputs (",#alloc", asm_out_file); 8696 if (flags & SECTION_WRITE) 8697 fputs (",#write", asm_out_file); 8698 if (flags & SECTION_TLS) 8699 fputs (",#tls", asm_out_file); 8700 if (flags & SECTION_CODE) 8701 fputs (",#execinstr", asm_out_file); 8702 8703 /* ??? Handle SECTION_BSS. */ 8704 8705 fputc ('\n', asm_out_file); 8706} 8707#endif /* OBJECT_FORMAT_ELF */ 8708 8709/* We do not allow sibling calls if -mflat, nor 8710 we do not allow indirect calls to be optimized into sibling calls. 8711 8712 Also, on sparc 32-bit we cannot emit a sibling call when the 8713 current function returns a structure. This is because the "unimp 8714 after call" convention would cause the callee to return to the 8715 wrong place. The generic code already disallows cases where the 8716 function being called returns a structure. 8717 8718 It may seem strange how this last case could occur. Usually there 8719 is code after the call which jumps to epilogue code which dumps the 8720 return value into the struct return area. That ought to invalidate 8721 the sibling call right? Well, in the c++ case we can end up passing 8722 the pointer to the struct return area to a constructor (which returns 8723 void) and then nothing else happens. Such a sibling call would look 8724 valid without the added check here. */ 8725static bool 8726sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) 8727{ 8728 return (decl 8729 && ! TARGET_FLAT 8730 && (TARGET_ARCH64 || ! current_function_returns_struct)); 8731} 8732 8733/* libfunc renaming. */ 8734#include "config/gofast.h" 8735 8736static void 8737sparc_init_libfuncs (void) 8738{ 8739 if (TARGET_ARCH32) 8740 { 8741 /* Use the subroutines that Sun's library provides for integer 8742 multiply and divide. The `*' prevents an underscore from 8743 being prepended by the compiler. .umul is a little faster 8744 than .mul. */ 8745 set_optab_libfunc (smul_optab, SImode, "*.umul"); 8746 set_optab_libfunc (sdiv_optab, SImode, "*.div"); 8747 set_optab_libfunc (udiv_optab, SImode, "*.udiv"); 8748 set_optab_libfunc (smod_optab, SImode, "*.rem"); 8749 set_optab_libfunc (umod_optab, SImode, "*.urem"); 8750 8751 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */ 8752 set_optab_libfunc (add_optab, TFmode, "_Q_add"); 8753 set_optab_libfunc (sub_optab, TFmode, "_Q_sub"); 8754 set_optab_libfunc (neg_optab, TFmode, "_Q_neg"); 8755 set_optab_libfunc (smul_optab, TFmode, "_Q_mul"); 8756 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div"); 8757 8758 /* We can define the TFmode sqrt optab only if TARGET_FPU. This 8759 is because with soft-float, the SFmode and DFmode sqrt 8760 instructions will be absent, and the compiler will notice and 8761 try to use the TFmode sqrt instruction for calls to the 8762 builtin function sqrt, but this fails. */ 8763 if (TARGET_FPU) 8764 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt"); 8765 8766 set_optab_libfunc (eq_optab, TFmode, "_Q_feq"); 8767 set_optab_libfunc (ne_optab, TFmode, "_Q_fne"); 8768 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt"); 8769 set_optab_libfunc (ge_optab, TFmode, "_Q_fge"); 8770 set_optab_libfunc (lt_optab, TFmode, "_Q_flt"); 8771 set_optab_libfunc (le_optab, TFmode, "_Q_fle"); 8772 8773 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq"); 8774 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq"); 8775 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos"); 8776 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod"); 8777 8778 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi"); 8779 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou"); 8780 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq"); 8781 8782 if (DITF_CONVERSION_LIBFUNCS) 8783 { 8784 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll"); 8785 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull"); 8786 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq"); 8787 } 8788 8789 if (SUN_CONVERSION_LIBFUNCS) 8790 { 8791 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); 8792 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); 8793 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); 8794 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); 8795 } 8796 } 8797 if (TARGET_ARCH64) 8798 { 8799 /* In the SPARC 64bit ABI, SImode multiply and divide functions 8800 do not exist in the library. Make sure the compiler does not 8801 emit calls to them by accident. (It should always use the 8802 hardware instructions.) */ 8803 set_optab_libfunc (smul_optab, SImode, 0); 8804 set_optab_libfunc (sdiv_optab, SImode, 0); 8805 set_optab_libfunc (udiv_optab, SImode, 0); 8806 set_optab_libfunc (smod_optab, SImode, 0); 8807 set_optab_libfunc (umod_optab, SImode, 0); 8808 8809 if (SUN_INTEGER_MULTIPLY_64) 8810 { 8811 set_optab_libfunc (smul_optab, DImode, "__mul64"); 8812 set_optab_libfunc (sdiv_optab, DImode, "__div64"); 8813 set_optab_libfunc (udiv_optab, DImode, "__udiv64"); 8814 set_optab_libfunc (smod_optab, DImode, "__rem64"); 8815 set_optab_libfunc (umod_optab, DImode, "__urem64"); 8816 } 8817 8818 if (SUN_CONVERSION_LIBFUNCS) 8819 { 8820 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol"); 8821 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul"); 8822 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol"); 8823 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul"); 8824 } 8825 } 8826 8827 gofast_maybe_init_libfuncs (); 8828} 8829 8830/* ??? Similar to the standard section selection, but force reloc-y-ness 8831 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to 8832 pretending PIC always on), but that's what the old code did. */ 8833 8834static void 8835sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align) 8836{ 8837 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align); 8838} 8839 8840/* Use text section for a constant unless we need more alignment than 8841 that offers. */ 8842 8843static void 8844sparc_aout_select_rtx_section (enum machine_mode mode, rtx x, 8845 unsigned HOST_WIDE_INT align) 8846{ 8847 if (align <= MAX_TEXT_ALIGN 8848 && ! (flag_pic && (symbolic_operand (x, mode) 8849 || SUNOS4_SHARED_LIBRARIES))) 8850 readonly_data_section (); 8851 else 8852 data_section (); 8853} 8854 8855int 8856sparc_extra_constraint_check (rtx op, int c, int strict) 8857{ 8858 int reload_ok_mem; 8859 8860 if (TARGET_ARCH64 8861 && (c == 'T' || c == 'U')) 8862 return 0; 8863 8864 switch (c) 8865 { 8866 case 'Q': 8867 return fp_sethi_p (op); 8868 8869 case 'R': 8870 return fp_mov_p (op); 8871 8872 case 'S': 8873 return fp_high_losum_p (op); 8874 8875 case 'U': 8876 if (! strict 8877 || (GET_CODE (op) == REG 8878 && (REGNO (op) < FIRST_PSEUDO_REGISTER 8879 || reg_renumber[REGNO (op)] >= 0))) 8880 return register_ok_for_ldd (op); 8881 8882 return 0; 8883 8884 case 'W': 8885 case 'T': 8886 break; 8887 8888 default: 8889 return 0; 8890 } 8891 8892 /* Our memory extra constraints have to emulate the 8893 behavior of 'm' and 'o' in order for reload to work 8894 correctly. */ 8895 if (GET_CODE (op) == MEM) 8896 { 8897 reload_ok_mem = 0; 8898 if ((TARGET_ARCH64 || mem_min_alignment (op, 8)) 8899 && (! strict 8900 || strict_memory_address_p (Pmode, XEXP (op, 0)))) 8901 reload_ok_mem = 1; 8902 } 8903 else 8904 { 8905 reload_ok_mem = (reload_in_progress 8906 && GET_CODE (op) == REG 8907 && REGNO (op) >= FIRST_PSEUDO_REGISTER 8908 && reg_renumber [REGNO (op)] < 0); 8909 } 8910 8911 return reload_ok_mem; 8912} 8913 8914/* ??? This duplicates information provided to the compiler by the 8915 ??? scheduler description. Some day, teach genautomata to output 8916 ??? the latencies and then CSE will just use that. */ 8917 8918static bool 8919sparc_rtx_costs (rtx x, int code, int outer_code, int *total) 8920{ 8921 switch (code) 8922 { 8923 case PLUS: case MINUS: case ABS: case NEG: 8924 case FLOAT: case UNSIGNED_FLOAT: 8925 case FIX: case UNSIGNED_FIX: 8926 case FLOAT_EXTEND: case FLOAT_TRUNCATE: 8927 if (FLOAT_MODE_P (GET_MODE (x))) 8928 { 8929 switch (sparc_cpu) 8930 { 8931 case PROCESSOR_ULTRASPARC: 8932 case PROCESSOR_ULTRASPARC3: 8933 *total = COSTS_N_INSNS (4); 8934 return true; 8935 8936 case PROCESSOR_SUPERSPARC: 8937 *total = COSTS_N_INSNS (3); 8938 return true; 8939 8940 case PROCESSOR_CYPRESS: 8941 *total = COSTS_N_INSNS (5); 8942 return true; 8943 8944 case PROCESSOR_HYPERSPARC: 8945 case PROCESSOR_SPARCLITE86X: 8946 default: 8947 *total = COSTS_N_INSNS (1); 8948 return true; 8949 } 8950 } 8951 8952 *total = COSTS_N_INSNS (1); 8953 return true; 8954 8955 case SQRT: 8956 switch (sparc_cpu) 8957 { 8958 case PROCESSOR_ULTRASPARC: 8959 if (GET_MODE (x) == SFmode) 8960 *total = COSTS_N_INSNS (13); 8961 else 8962 *total = COSTS_N_INSNS (23); 8963 return true; 8964 8965 case PROCESSOR_ULTRASPARC3: 8966 if (GET_MODE (x) == SFmode) 8967 *total = COSTS_N_INSNS (20); 8968 else 8969 *total = COSTS_N_INSNS (29); 8970 return true; 8971 8972 case PROCESSOR_SUPERSPARC: 8973 *total = COSTS_N_INSNS (12); 8974 return true; 8975 8976 case PROCESSOR_CYPRESS: 8977 *total = COSTS_N_INSNS (63); 8978 return true; 8979 8980 case PROCESSOR_HYPERSPARC: 8981 case PROCESSOR_SPARCLITE86X: 8982 *total = COSTS_N_INSNS (17); 8983 return true; 8984 8985 default: 8986 *total = COSTS_N_INSNS (30); 8987 return true; 8988 } 8989 8990 case COMPARE: 8991 if (FLOAT_MODE_P (GET_MODE (x))) 8992 { 8993 switch (sparc_cpu) 8994 { 8995 case PROCESSOR_ULTRASPARC: 8996 case PROCESSOR_ULTRASPARC3: 8997 *total = COSTS_N_INSNS (1); 8998 return true; 8999 9000 case PROCESSOR_SUPERSPARC: 9001 *total = COSTS_N_INSNS (3); 9002 return true; 9003 9004 case PROCESSOR_CYPRESS: 9005 *total = COSTS_N_INSNS (5); 9006 return true; 9007 9008 case PROCESSOR_HYPERSPARC: 9009 case PROCESSOR_SPARCLITE86X: 9010 default: 9011 *total = COSTS_N_INSNS (1); 9012 return true; 9013 } 9014 } 9015 9016 /* ??? Maybe mark integer compares as zero cost on 9017 ??? all UltraSPARC processors because the result 9018 ??? can be bypassed to a branch in the same group. */ 9019 9020 *total = COSTS_N_INSNS (1); 9021 return true; 9022 9023 case MULT: 9024 if (FLOAT_MODE_P (GET_MODE (x))) 9025 { 9026 switch (sparc_cpu) 9027 { 9028 case PROCESSOR_ULTRASPARC: 9029 case PROCESSOR_ULTRASPARC3: 9030 *total = COSTS_N_INSNS (4); 9031 return true; 9032 9033 case PROCESSOR_SUPERSPARC: 9034 *total = COSTS_N_INSNS (3); 9035 return true; 9036 9037 case PROCESSOR_CYPRESS: 9038 *total = COSTS_N_INSNS (7); 9039 return true; 9040 9041 case PROCESSOR_HYPERSPARC: 9042 case PROCESSOR_SPARCLITE86X: 9043 *total = COSTS_N_INSNS (1); 9044 return true; 9045 9046 default: 9047 *total = COSTS_N_INSNS (5); 9048 return true; 9049 } 9050 } 9051 9052 /* The latency is actually variable for Ultra-I/II 9053 And if one of the inputs have a known constant 9054 value, we could calculate this precisely. 9055 9056 However, for that to be useful we would need to 9057 add some machine description changes which would 9058 make sure small constants ended up in rs1 of the 9059 multiply instruction. This is because the multiply 9060 latency is determined by the number of clear (or 9061 set if the value is negative) bits starting from 9062 the most significant bit of the first input. 9063 9064 The algorithm for computing num_cycles of a multiply 9065 on Ultra-I/II is: 9066 9067 if (rs1 < 0) 9068 highest_bit = highest_clear_bit(rs1); 9069 else 9070 highest_bit = highest_set_bit(rs1); 9071 if (num_bits < 3) 9072 highest_bit = 3; 9073 num_cycles = 4 + ((highest_bit - 3) / 2); 9074 9075 If we did that we would have to also consider register 9076 allocation issues that would result from forcing such 9077 a value into a register. 9078 9079 There are other similar tricks we could play if we 9080 knew, for example, that one input was an array index. 9081 9082 Since we do not play any such tricks currently the 9083 safest thing to do is report the worst case latency. */ 9084 if (sparc_cpu == PROCESSOR_ULTRASPARC) 9085 { 9086 *total = (GET_MODE (x) == DImode 9087 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); 9088 return true; 9089 } 9090 9091 /* Multiply latency on Ultra-III, fortunately, is constant. */ 9092 if (sparc_cpu == PROCESSOR_ULTRASPARC3) 9093 { 9094 *total = COSTS_N_INSNS (6); 9095 return true; 9096 } 9097 9098 if (sparc_cpu == PROCESSOR_HYPERSPARC 9099 || sparc_cpu == PROCESSOR_SPARCLITE86X) 9100 { 9101 *total = COSTS_N_INSNS (17); 9102 return true; 9103 } 9104 9105 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25)); 9106 return true; 9107 9108 case DIV: 9109 case UDIV: 9110 case MOD: 9111 case UMOD: 9112 if (FLOAT_MODE_P (GET_MODE (x))) 9113 { 9114 switch (sparc_cpu) 9115 { 9116 case PROCESSOR_ULTRASPARC: 9117 if (GET_MODE (x) == SFmode) 9118 *total = COSTS_N_INSNS (13); 9119 else 9120 *total = COSTS_N_INSNS (23); 9121 return true; 9122 9123 case PROCESSOR_ULTRASPARC3: 9124 if (GET_MODE (x) == SFmode) 9125 *total = COSTS_N_INSNS (17); 9126 else 9127 *total = COSTS_N_INSNS (20); 9128 return true; 9129 9130 case PROCESSOR_SUPERSPARC: 9131 if (GET_MODE (x) == SFmode) 9132 *total = COSTS_N_INSNS (6); 9133 else 9134 *total = COSTS_N_INSNS (9); 9135 return true; 9136 9137 case PROCESSOR_HYPERSPARC: 9138 case PROCESSOR_SPARCLITE86X: 9139 if (GET_MODE (x) == SFmode) 9140 *total = COSTS_N_INSNS (8); 9141 else 9142 *total = COSTS_N_INSNS (12); 9143 return true; 9144 9145 default: 9146 *total = COSTS_N_INSNS (7); 9147 return true; 9148 } 9149 } 9150 9151 if (sparc_cpu == PROCESSOR_ULTRASPARC) 9152 *total = (GET_MODE (x) == DImode 9153 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); 9154 else if (sparc_cpu == PROCESSOR_ULTRASPARC3) 9155 *total = (GET_MODE (x) == DImode 9156 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40)); 9157 else 9158 *total = COSTS_N_INSNS (25); 9159 return true; 9160 9161 case IF_THEN_ELSE: 9162 /* Conditional moves. */ 9163 switch (sparc_cpu) 9164 { 9165 case PROCESSOR_ULTRASPARC: 9166 *total = COSTS_N_INSNS (2); 9167 return true; 9168 9169 case PROCESSOR_ULTRASPARC3: 9170 if (FLOAT_MODE_P (GET_MODE (x))) 9171 *total = COSTS_N_INSNS (3); 9172 else 9173 *total = COSTS_N_INSNS (2); 9174 return true; 9175 9176 default: 9177 *total = COSTS_N_INSNS (1); 9178 return true; 9179 } 9180 9181 case MEM: 9182 /* If outer-code is SIGN/ZERO extension we have to subtract 9183 out COSTS_N_INSNS (1) from whatever we return in determining 9184 the cost. */ 9185 switch (sparc_cpu) 9186 { 9187 case PROCESSOR_ULTRASPARC: 9188 if (outer_code == ZERO_EXTEND) 9189 *total = COSTS_N_INSNS (1); 9190 else 9191 *total = COSTS_N_INSNS (2); 9192 return true; 9193 9194 case PROCESSOR_ULTRASPARC3: 9195 if (outer_code == ZERO_EXTEND) 9196 { 9197 if (GET_MODE (x) == QImode 9198 || GET_MODE (x) == HImode 9199 || outer_code == SIGN_EXTEND) 9200 *total = COSTS_N_INSNS (2); 9201 else 9202 *total = COSTS_N_INSNS (1); 9203 } 9204 else 9205 { 9206 /* This handles sign extension (3 cycles) 9207 and everything else (2 cycles). */ 9208 *total = COSTS_N_INSNS (2); 9209 } 9210 return true; 9211 9212 case PROCESSOR_SUPERSPARC: 9213 if (FLOAT_MODE_P (GET_MODE (x)) 9214 || outer_code == ZERO_EXTEND 9215 || outer_code == SIGN_EXTEND) 9216 *total = COSTS_N_INSNS (0); 9217 else 9218 *total = COSTS_N_INSNS (1); 9219 return true; 9220 9221 case PROCESSOR_TSC701: 9222 if (outer_code == ZERO_EXTEND 9223 || outer_code == SIGN_EXTEND) 9224 *total = COSTS_N_INSNS (2); 9225 else 9226 *total = COSTS_N_INSNS (3); 9227 return true; 9228 9229 case PROCESSOR_CYPRESS: 9230 if (outer_code == ZERO_EXTEND 9231 || outer_code == SIGN_EXTEND) 9232 *total = COSTS_N_INSNS (1); 9233 else 9234 *total = COSTS_N_INSNS (2); 9235 return true; 9236 9237 case PROCESSOR_HYPERSPARC: 9238 case PROCESSOR_SPARCLITE86X: 9239 default: 9240 if (outer_code == ZERO_EXTEND 9241 || outer_code == SIGN_EXTEND) 9242 *total = COSTS_N_INSNS (0); 9243 else 9244 *total = COSTS_N_INSNS (1); 9245 return true; 9246 } 9247 9248 case CONST_INT: 9249 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000) 9250 { 9251 *total = 0; 9252 return true; 9253 } 9254 /* FALLTHRU */ 9255 9256 case HIGH: 9257 *total = 2; 9258 return true; 9259 9260 case CONST: 9261 case LABEL_REF: 9262 case SYMBOL_REF: 9263 *total = 4; 9264 return true; 9265 9266 case CONST_DOUBLE: 9267 if (GET_MODE (x) == DImode 9268 && ((XINT (x, 3) == 0 9269 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000) 9270 || (XINT (x, 3) == -1 9271 && XINT (x, 2) < 0 9272 && XINT (x, 2) >= -0x1000))) 9273 *total = 0; 9274 else 9275 *total = 8; 9276 return true; 9277 9278 default: 9279 return false; 9280 } 9281} 9282 9283/* Output the assembler code for a thunk function. THUNK_DECL is the 9284 declaration for the thunk function itself, FUNCTION is the decl for 9285 the target function. DELTA is an immediate constant offset to be 9286 added to THIS. If VCALL_OFFSET is nonzero, the word at address 9287 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */ 9288 9289static void 9290sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 9291 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 9292 tree function) 9293{ 9294 rtx this, insn, funexp; 9295 9296 reload_completed = 1; 9297 epilogue_completed = 1; 9298 no_new_pseudos = 1; 9299 current_function_uses_only_leaf_regs = 1; 9300 9301 emit_note (NOTE_INSN_PROLOGUE_END); 9302 9303 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function 9304 returns a structure, the structure return pointer is there instead. */ 9305 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 9306 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1); 9307 else 9308 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST); 9309 9310 /* Add DELTA. When possible use a plain add, otherwise load it into 9311 a register first. */ 9312 if (delta) 9313 { 9314 rtx delta_rtx = GEN_INT (delta); 9315 9316 if (! SPARC_SIMM13_P (delta)) 9317 { 9318 rtx scratch = gen_rtx_REG (Pmode, 1); 9319 emit_move_insn (scratch, delta_rtx); 9320 delta_rtx = scratch; 9321 } 9322 9323 /* THIS += DELTA. */ 9324 emit_insn (gen_add2_insn (this, delta_rtx)); 9325 } 9326 9327 /* Add the word at address (*THIS + VCALL_OFFSET). */ 9328 if (vcall_offset) 9329 { 9330 rtx vcall_offset_rtx = GEN_INT (vcall_offset); 9331 rtx scratch = gen_rtx_REG (Pmode, 1); 9332 9333 if (vcall_offset >= 0) 9334 abort (); 9335 9336 /* SCRATCH = *THIS. */ 9337 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this)); 9338 9339 /* Prepare for adding VCALL_OFFSET. The difficulty is that we 9340 may not have any available scratch register at this point. */ 9341 if (SPARC_SIMM13_P (vcall_offset)) 9342 ; 9343 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */ 9344 else if (! fixed_regs[5] 9345 /* The below sequence is made up of at least 2 insns, 9346 while the default method may need only one. */ 9347 && vcall_offset < -8192) 9348 { 9349 rtx scratch2 = gen_rtx_REG (Pmode, 5); 9350 emit_move_insn (scratch2, vcall_offset_rtx); 9351 vcall_offset_rtx = scratch2; 9352 } 9353 else 9354 { 9355 rtx increment = GEN_INT (-4096); 9356 9357 /* VCALL_OFFSET is a negative number whose typical range can be 9358 estimated as -32768..0 in 32-bit mode. In almost all cases 9359 it is therefore cheaper to emit multiple add insns than 9360 spilling and loading the constant into a register (at least 9361 6 insns). */ 9362 while (! SPARC_SIMM13_P (vcall_offset)) 9363 { 9364 emit_insn (gen_add2_insn (scratch, increment)); 9365 vcall_offset += 4096; 9366 } 9367 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */ 9368 } 9369 9370 /* SCRATCH = *(*THIS + VCALL_OFFSET). */ 9371 emit_move_insn (scratch, gen_rtx_MEM (Pmode, 9372 gen_rtx_PLUS (Pmode, 9373 scratch, 9374 vcall_offset_rtx))); 9375 9376 /* THIS += *(*THIS + VCALL_OFFSET). */ 9377 emit_insn (gen_add2_insn (this, scratch)); 9378 } 9379 9380 /* Generate a tail call to the target function. */ 9381 if (! TREE_USED (function)) 9382 { 9383 assemble_external (function); 9384 TREE_USED (function) = 1; 9385 } 9386 funexp = XEXP (DECL_RTL (function), 0); 9387 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); 9388 insn = emit_call_insn (gen_sibcall (funexp)); 9389 SIBLING_CALL_P (insn) = 1; 9390 emit_barrier (); 9391 9392 /* Run just enough of rest_of_compilation to get the insns emitted. 9393 There's not really enough bulk here to make other passes such as 9394 instruction scheduling worth while. Note that use_thunk calls 9395 assemble_start_function and assemble_end_function. */ 9396 insn = get_insns (); 9397 insn_locators_initialize (); 9398 shorten_branches (insn); 9399 final_start_function (insn, file, 1); 9400 final (insn, file, 1, 0); 9401 final_end_function (); 9402 9403 reload_completed = 0; 9404 epilogue_completed = 0; 9405 no_new_pseudos = 0; 9406} 9407 9408/* Return true if sparc_output_mi_thunk would be able to output the 9409 assembler code for the thunk function specified by the arguments 9410 it is passed, and false otherwise. */ 9411static bool 9412sparc_can_output_mi_thunk (tree thunk_fndecl ATTRIBUTE_UNUSED, 9413 HOST_WIDE_INT delta ATTRIBUTE_UNUSED, 9414 HOST_WIDE_INT vcall_offset, 9415 tree function ATTRIBUTE_UNUSED) 9416{ 9417 /* Bound the loop used in the default method above. */ 9418 return (vcall_offset >= -32768 || ! fixed_regs[5]); 9419} 9420 9421/* How to allocate a 'struct machine_function'. */ 9422 9423static struct machine_function * 9424sparc_init_machine_status (void) 9425{ 9426 return ggc_alloc_cleared (sizeof (struct machine_function)); 9427} 9428 9429/* Locate some local-dynamic symbol still in use by this function 9430 so that we can print its name in local-dynamic base patterns. */ 9431 9432static const char * 9433get_some_local_dynamic_name (void) 9434{ 9435 rtx insn; 9436 9437 if (cfun->machine->some_ld_name) 9438 return cfun->machine->some_ld_name; 9439 9440 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) 9441 if (INSN_P (insn) 9442 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0)) 9443 return cfun->machine->some_ld_name; 9444 9445 abort (); 9446} 9447 9448static int 9449get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) 9450{ 9451 rtx x = *px; 9452 9453 if (x 9454 && GET_CODE (x) == SYMBOL_REF 9455 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) 9456 { 9457 cfun->machine->some_ld_name = XSTR (x, 0); 9458 return 1; 9459 } 9460 9461 return 0; 9462} 9463 9464/* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL. 9465 We need to emit DTP-relative relocations. */ 9466 9467void 9468sparc_output_dwarf_dtprel (FILE *file, int size, rtx x) 9469{ 9470 switch (size) 9471 { 9472 case 4: 9473 fputs ("\t.word\t%r_tls_dtpoff32(", file); 9474 break; 9475 case 8: 9476 fputs ("\t.xword\t%r_tls_dtpoff64(", file); 9477 break; 9478 default: 9479 abort (); 9480 } 9481 output_addr_const (file, x); 9482 fputs (")", file); 9483} 9484 9485#include "gt-sparc.h" 9486