sparc.c revision 122180
128263Spst/* Subroutines for insn-output.c for Sun SPARC. 228263Spst Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 350472Speter 1999, 2000, 2001, 2002 Free Software Foundation, Inc. 428263Spst Contributed by Michael Tiemann (tiemann@cygnus.com) 528263Spst 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 628263Spst at Cygnus Support. 728263Spst 828263SpstThis file is part of GNU CC. 961981Sbrian 1061981SbrianGNU CC is free software; you can redistribute it and/or modify 1161981Sbrianit under the terms of the GNU General Public License as published by 1261981Sbrianthe Free Software Foundation; either version 2, or (at your option) 1361981Sbrianany later version. 1461981Sbrian 1528263SpstGNU CC is distributed in the hope that it will be useful, 1661981Sbrianbut WITHOUT ANY WARRANTY; without even the implied warranty of 1761981SbrianMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1861981SbrianGNU General Public License for more details. 1965843Sbrian 2061981SbrianYou should have received a copy of the GNU General Public License 2165843Sbrianalong with GNU CC; see the file COPYING. If not, write to 2265843Sbrianthe Free Software Foundation, 59 Temple Place - Suite 330, 2365843SbrianBoston, MA 02111-1307, USA. */ 2465843Sbrian 2561981Sbrian#include "config.h" 2661981Sbrian#include "system.h" 2761981Sbrian#include "tree.h" 2865843Sbrian#include "rtl.h" 2961981Sbrian#include "regs.h" 3065843Sbrian#include "hard-reg-set.h" 3165843Sbrian#include "real.h" 3261981Sbrian#include "insn-config.h" 3365843Sbrian#include "conditions.h" 3465843Sbrian#include "output.h" 35#include "insn-attr.h" 36#include "flags.h" 37#include "function.h" 38#include "expr.h" 39#include "optabs.h" 40#include "libfuncs.h" 41#include "recog.h" 42#include "toplev.h" 43#include "ggc.h" 44#include "tm_p.h" 45#include "debug.h" 46#include "target.h" 47#include "target-def.h" 48 49/* 1 if the caller has placed an "unimp" insn immediately after the call. 50 This is used in v8 code when calling a function that returns a structure. 51 v9 doesn't have this. Be careful to have this test be the same as that 52 used on the call. */ 53 54#define SKIP_CALLERS_UNIMP_P \ 55(!TARGET_ARCH64 && current_function_returns_struct \ 56 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ 57 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ 58 == INTEGER_CST)) 59 60/* Global variables for machine-dependent things. */ 61 62/* Size of frame. Need to know this to emit return insns from leaf procedures. 63 ACTUAL_FSIZE is set by compute_frame_size() which is called during the 64 reload pass. This is important as the value is later used in insn 65 scheduling (to see what can go in a delay slot). 66 APPARENT_FSIZE is the size of the stack less the register save area and less 67 the outgoing argument area. It is used when saving call preserved regs. */ 68static int apparent_fsize; 69static int actual_fsize; 70 71/* Number of live general or floating point registers needed to be 72 saved (as 4-byte quantities). */ 73static int num_gfregs; 74 75/* Save the operands last given to a compare for use when we 76 generate a scc or bcc insn. */ 77rtx sparc_compare_op0, sparc_compare_op1; 78 79/* Coordinate with the md file wrt special insns created by 80 sparc_nonflat_function_epilogue. */ 81bool sparc_emitting_epilogue; 82 83/* Vector to say how input registers are mapped to output registers. 84 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to 85 eliminate it. You must use -fomit-frame-pointer to get that. */ 86char leaf_reg_remap[] = 87{ 0, 1, 2, 3, 4, 5, 6, 7, 88 -1, -1, -1, -1, -1, -1, 14, -1, 89 -1, -1, -1, -1, -1, -1, -1, -1, 90 8, 9, 10, 11, 12, 13, -1, 15, 91 92 32, 33, 34, 35, 36, 37, 38, 39, 93 40, 41, 42, 43, 44, 45, 46, 47, 94 48, 49, 50, 51, 52, 53, 54, 55, 95 56, 57, 58, 59, 60, 61, 62, 63, 96 64, 65, 66, 67, 68, 69, 70, 71, 97 72, 73, 74, 75, 76, 77, 78, 79, 98 80, 81, 82, 83, 84, 85, 86, 87, 99 88, 89, 90, 91, 92, 93, 94, 95, 100 96, 97, 98, 99, 100}; 101 102/* Vector, indexed by hard register number, which contains 1 103 for a register that is allowable in a candidate for leaf 104 function treatment. */ 105char sparc_leaf_regs[] = 106{ 1, 1, 1, 1, 1, 1, 1, 1, 107 0, 0, 0, 0, 0, 0, 1, 0, 108 0, 0, 0, 0, 0, 0, 0, 0, 109 1, 1, 1, 1, 1, 1, 0, 1, 110 1, 1, 1, 1, 1, 1, 1, 1, 111 1, 1, 1, 1, 1, 1, 1, 1, 112 1, 1, 1, 1, 1, 1, 1, 1, 113 1, 1, 1, 1, 1, 1, 1, 1, 114 1, 1, 1, 1, 1, 1, 1, 1, 115 1, 1, 1, 1, 1, 1, 1, 1, 116 1, 1, 1, 1, 1, 1, 1, 1, 117 1, 1, 1, 1, 1, 1, 1, 1, 118 1, 1, 1, 1, 1}; 119 120/* Name of where we pretend to think the frame pointer points. 121 Normally, this is "%fp", but if we are in a leaf procedure, 122 this is "%sp+something". We record "something" separately as it may be 123 too big for reg+constant addressing. */ 124 125static const char *frame_base_name; 126static int frame_base_offset; 127 128static void sparc_init_modes PARAMS ((void)); 129static int save_regs PARAMS ((FILE *, int, int, const char *, 130 int, int, int)); 131static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int)); 132static void build_big_number PARAMS ((FILE *, int, const char *)); 133static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *, 134 enum machine_mode, tree, int, int, 135 int *, int *)); 136 137static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); 138static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); 139 140static void sparc_output_addr_vec PARAMS ((rtx)); 141static void sparc_output_addr_diff_vec PARAMS ((rtx)); 142static void sparc_output_deferred_case_vectors PARAMS ((void)); 143static int check_return_regs PARAMS ((rtx)); 144static int epilogue_renumber PARAMS ((rtx *, int)); 145static bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int)); 146static int set_extends PARAMS ((rtx)); 147static void output_restore_regs PARAMS ((FILE *, int)); 148static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); 149static void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); 150static void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); 151static void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); 152static void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT, 153 int)); 154static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT, 155 int)); 156#ifdef OBJECT_FORMAT_ELF 157static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int)); 158#endif 159static void sparc_aout_select_section PARAMS ((tree, int, 160 unsigned HOST_WIDE_INT)) 161 ATTRIBUTE_UNUSED; 162static void sparc_aout_select_rtx_section PARAMS ((enum machine_mode, rtx, 163 unsigned HOST_WIDE_INT)) 164 ATTRIBUTE_UNUSED; 165 166static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); 167static int sparc_issue_rate PARAMS ((void)); 168static void sparc_sched_init PARAMS ((FILE *, int, int)); 169static int sparc_use_dfa_pipeline_interface PARAMS ((void)); 170static int sparc_use_sched_lookahead PARAMS ((void)); 171 172static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *)); 173static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *)); 174static void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *)); 175static void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *)); 176static void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *)); 177 178static void sparc_encode_section_info PARAMS ((tree, int)); 179static void sparc_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, 180 HOST_WIDE_INT, tree)); 181 182/* Option handling. */ 183 184/* Code model option as passed by user. */ 185const char *sparc_cmodel_string; 186/* Parsed value. */ 187enum cmodel sparc_cmodel; 188 189char sparc_hard_reg_printed[8]; 190 191struct sparc_cpu_select sparc_select[] = 192{ 193 /* switch name, tune arch */ 194 { (char *)0, "default", 1, 1 }, 195 { (char *)0, "-mcpu=", 1, 1 }, 196 { (char *)0, "-mtune=", 1, 0 }, 197 { 0, 0, 0, 0 } 198}; 199 200/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ 201enum processor_type sparc_cpu; 202 203/* Initialize the GCC target structure. */ 204 205/* The sparc default is to use .half rather than .short for aligned 206 HI objects. Use .word instead of .long on non-ELF systems. */ 207#undef TARGET_ASM_ALIGNED_HI_OP 208#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 209#ifndef OBJECT_FORMAT_ELF 210#undef TARGET_ASM_ALIGNED_SI_OP 211#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 212#endif 213 214#undef TARGET_ASM_UNALIGNED_HI_OP 215#define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" 216#undef TARGET_ASM_UNALIGNED_SI_OP 217#define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" 218#undef TARGET_ASM_UNALIGNED_DI_OP 219#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" 220 221/* The target hook has to handle DI-mode values. */ 222#undef TARGET_ASM_INTEGER 223#define TARGET_ASM_INTEGER sparc_assemble_integer 224 225#undef TARGET_ASM_FUNCTION_PROLOGUE 226#define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue 227#undef TARGET_ASM_FUNCTION_EPILOGUE 228#define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue 229 230#undef TARGET_SCHED_ADJUST_COST 231#define TARGET_SCHED_ADJUST_COST sparc_adjust_cost 232#undef TARGET_SCHED_ISSUE_RATE 233#define TARGET_SCHED_ISSUE_RATE sparc_issue_rate 234#undef TARGET_SCHED_INIT 235#define TARGET_SCHED_INIT sparc_sched_init 236#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE 237#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface 238#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD 239#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead 240 241#undef TARGET_ENCODE_SECTION_INFO 242#define TARGET_ENCODE_SECTION_INFO sparc_encode_section_info 243 244#undef TARGET_ASM_OUTPUT_MI_THUNK 245#define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk 246#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 247#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall 248 249struct gcc_target targetm = TARGET_INITIALIZER; 250 251/* Validate and override various options, and do some machine dependent 252 initialization. */ 253 254void 255sparc_override_options () 256{ 257 static struct code_model { 258 const char *const name; 259 const int value; 260 } const cmodels[] = { 261 { "32", CM_32 }, 262 { "medlow", CM_MEDLOW }, 263 { "medmid", CM_MEDMID }, 264 { "medany", CM_MEDANY }, 265 { "embmedany", CM_EMBMEDANY }, 266 { 0, 0 } 267 }; 268 const struct code_model *cmodel; 269 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ 270 static struct cpu_default { 271 const int cpu; 272 const char *const name; 273 } const cpu_default[] = { 274 /* There must be one entry here for each TARGET_CPU value. */ 275 { TARGET_CPU_sparc, "cypress" }, 276 { TARGET_CPU_sparclet, "tsc701" }, 277 { TARGET_CPU_sparclite, "f930" }, 278 { TARGET_CPU_v8, "v8" }, 279 { TARGET_CPU_hypersparc, "hypersparc" }, 280 { TARGET_CPU_sparclite86x, "sparclite86x" }, 281 { TARGET_CPU_supersparc, "supersparc" }, 282 { TARGET_CPU_v9, "v9" }, 283 { TARGET_CPU_ultrasparc, "ultrasparc" }, 284 { TARGET_CPU_ultrasparc3, "ultrasparc3" }, 285 { 0, 0 } 286 }; 287 const struct cpu_default *def; 288 /* Table of values for -m{cpu,tune}=. */ 289 static struct cpu_table { 290 const char *const name; 291 const enum processor_type processor; 292 const int disable; 293 const int enable; 294 } const cpu_table[] = { 295 { "v7", PROCESSOR_V7, MASK_ISA, 0 }, 296 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, 297 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, 298 /* TI TMS390Z55 supersparc */ 299 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, 300 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, 301 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. 302 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ 303 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, 304 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, 305 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, 306 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, 307 MASK_SPARCLITE }, 308 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, 309 /* TEMIC sparclet */ 310 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, 311 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, 312 /* TI ultrasparc I, II, IIi */ 313 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 314 /* Although insns using %y are deprecated, it is a clear win on current 315 ultrasparcs. */ 316 |MASK_DEPRECATED_V8_INSNS}, 317 /* TI ultrasparc III */ 318 /* ??? Check if %y issue still holds true in ultra3. */ 319 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, 320 { 0, 0, 0, 0 } 321 }; 322 const struct cpu_table *cpu; 323 const struct sparc_cpu_select *sel; 324 int fpu; 325 326#ifndef SPARC_BI_ARCH 327 /* Check for unsupported architecture size. */ 328 if (! TARGET_64BIT != DEFAULT_ARCH32_P) 329 error ("%s is not supported by this configuration", 330 DEFAULT_ARCH32_P ? "-m64" : "-m32"); 331#endif 332 333 /* We force all 64bit archs to use 128 bit long double */ 334 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) 335 { 336 error ("-mlong-double-64 not allowed with -m64"); 337 target_flags |= MASK_LONG_DOUBLE_128; 338 } 339 340 /* Code model selection. */ 341 sparc_cmodel = SPARC_DEFAULT_CMODEL; 342 343#ifdef SPARC_BI_ARCH 344 if (TARGET_ARCH32) 345 sparc_cmodel = CM_32; 346#endif 347 348 if (sparc_cmodel_string != NULL) 349 { 350 if (TARGET_ARCH64) 351 { 352 for (cmodel = &cmodels[0]; cmodel->name; cmodel++) 353 if (strcmp (sparc_cmodel_string, cmodel->name) == 0) 354 break; 355 if (cmodel->name == NULL) 356 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); 357 else 358 sparc_cmodel = cmodel->value; 359 } 360 else 361 error ("-mcmodel= is not supported on 32 bit systems"); 362 } 363 364 fpu = TARGET_FPU; /* save current -mfpu status */ 365 366 /* Set the default CPU. */ 367 for (def = &cpu_default[0]; def->name; ++def) 368 if (def->cpu == TARGET_CPU_DEFAULT) 369 break; 370 if (! def->name) 371 abort (); 372 sparc_select[0].string = def->name; 373 374 for (sel = &sparc_select[0]; sel->name; ++sel) 375 { 376 if (sel->string) 377 { 378 for (cpu = &cpu_table[0]; cpu->name; ++cpu) 379 if (! strcmp (sel->string, cpu->name)) 380 { 381 if (sel->set_tune_p) 382 sparc_cpu = cpu->processor; 383 384 if (sel->set_arch_p) 385 { 386 target_flags &= ~cpu->disable; 387 target_flags |= cpu->enable; 388 } 389 break; 390 } 391 392 if (! cpu->name) 393 error ("bad value (%s) for %s switch", sel->string, sel->name); 394 } 395 } 396 397 /* If -mfpu or -mno-fpu was explicitly used, don't override with 398 the processor default. Clear MASK_FPU_SET to avoid confusing 399 the reverse mapping from switch values to names. */ 400 if (TARGET_FPU_SET) 401 { 402 target_flags = (target_flags & ~MASK_FPU) | fpu; 403 target_flags &= ~MASK_FPU_SET; 404 } 405 406 /* Don't allow -mvis if FPU is disabled. */ 407 if (! TARGET_FPU) 408 target_flags &= ~MASK_VIS; 409 410 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions 411 are available. 412 -m64 also implies v9. */ 413 if (TARGET_VIS || TARGET_ARCH64) 414 { 415 target_flags |= MASK_V9; 416 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); 417 } 418 419 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ 420 if (TARGET_V9 && TARGET_ARCH32) 421 target_flags |= MASK_DEPRECATED_V8_INSNS; 422 423 /* V8PLUS requires V9, makes no sense in 64 bit mode. */ 424 if (! TARGET_V9 || TARGET_ARCH64) 425 target_flags &= ~MASK_V8PLUS; 426 427 /* Don't use stack biasing in 32 bit mode. */ 428 if (TARGET_ARCH32) 429 target_flags &= ~MASK_STACK_BIAS; 430 431 /* Supply a default value for align_functions. */ 432 if (align_functions == 0 433 && (sparc_cpu == PROCESSOR_ULTRASPARC 434 || sparc_cpu == PROCESSOR_ULTRASPARC3)) 435 align_functions = 32; 436 437 /* Validate PCC_STRUCT_RETURN. */ 438 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) 439 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); 440 441 /* Only use .uaxword when compiling for a 64-bit target. */ 442 if (!TARGET_ARCH64) 443 targetm.asm_out.unaligned_op.di = NULL; 444 445 /* Do various machine dependent initializations. */ 446 sparc_init_modes (); 447} 448 449/* Miscellaneous utilities. */ 450 451/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move 452 or branch on register contents instructions. */ 453 454int 455v9_regcmp_p (code) 456 enum rtx_code code; 457{ 458 return (code == EQ || code == NE || code == GE || code == LT 459 || code == LE || code == GT); 460} 461 462 463/* Operand constraints. */ 464 465/* Return nonzero only if OP is a register of mode MODE, 466 or const0_rtx. */ 467 468int 469reg_or_0_operand (op, mode) 470 rtx op; 471 enum machine_mode mode; 472{ 473 if (register_operand (op, mode)) 474 return 1; 475 if (op == const0_rtx) 476 return 1; 477 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE 478 && CONST_DOUBLE_HIGH (op) == 0 479 && CONST_DOUBLE_LOW (op) == 0) 480 return 1; 481 if (fp_zero_operand (op, mode)) 482 return 1; 483 return 0; 484} 485 486/* Return nonzero only if OP is const1_rtx. */ 487 488int 489const1_operand (op, mode) 490 rtx op; 491 enum machine_mode mode ATTRIBUTE_UNUSED; 492{ 493 return op == const1_rtx; 494} 495 496/* Nonzero if OP is a floating point value with value 0.0. */ 497 498int 499fp_zero_operand (op, mode) 500 rtx op; 501 enum machine_mode mode; 502{ 503 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT) 504 return 0; 505 return op == CONST0_RTX (mode); 506} 507 508/* Nonzero if OP is a register operand in floating point register. */ 509 510int 511fp_register_operand (op, mode) 512 rtx op; 513 enum machine_mode mode; 514{ 515 if (! register_operand (op, mode)) 516 return 0; 517 if (GET_CODE (op) == SUBREG) 518 op = SUBREG_REG (op); 519 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op)); 520} 521 522/* Nonzero if OP is a floating point constant which can 523 be loaded into an integer register using a single 524 sethi instruction. */ 525 526int 527fp_sethi_p (op) 528 rtx op; 529{ 530 if (GET_CODE (op) == CONST_DOUBLE) 531 { 532 REAL_VALUE_TYPE r; 533 long i; 534 535 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 536 if (REAL_VALUES_EQUAL (r, dconst0) && 537 ! REAL_VALUE_MINUS_ZERO (r)) 538 return 0; 539 REAL_VALUE_TO_TARGET_SINGLE (r, i); 540 if (SPARC_SETHI_P (i)) 541 return 1; 542 } 543 544 return 0; 545} 546 547/* Nonzero if OP is a floating point constant which can 548 be loaded into an integer register using a single 549 mov instruction. */ 550 551int 552fp_mov_p (op) 553 rtx op; 554{ 555 if (GET_CODE (op) == CONST_DOUBLE) 556 { 557 REAL_VALUE_TYPE r; 558 long i; 559 560 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 561 if (REAL_VALUES_EQUAL (r, dconst0) && 562 ! REAL_VALUE_MINUS_ZERO (r)) 563 return 0; 564 REAL_VALUE_TO_TARGET_SINGLE (r, i); 565 if (SPARC_SIMM13_P (i)) 566 return 1; 567 } 568 569 return 0; 570} 571 572/* Nonzero if OP is a floating point constant which can 573 be loaded into an integer register using a high/losum 574 instruction sequence. */ 575 576int 577fp_high_losum_p (op) 578 rtx op; 579{ 580 /* The constraints calling this should only be in 581 SFmode move insns, so any constant which cannot 582 be moved using a single insn will do. */ 583 if (GET_CODE (op) == CONST_DOUBLE) 584 { 585 REAL_VALUE_TYPE r; 586 long i; 587 588 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 589 if (REAL_VALUES_EQUAL (r, dconst0) && 590 ! REAL_VALUE_MINUS_ZERO (r)) 591 return 0; 592 REAL_VALUE_TO_TARGET_SINGLE (r, i); 593 if (! SPARC_SETHI_P (i) 594 && ! SPARC_SIMM13_P (i)) 595 return 1; 596 } 597 598 return 0; 599} 600 601/* Nonzero if OP is an integer register. */ 602 603int 604intreg_operand (op, mode) 605 rtx op; 606 enum machine_mode mode ATTRIBUTE_UNUSED; 607{ 608 return (register_operand (op, SImode) 609 || (TARGET_ARCH64 && register_operand (op, DImode))); 610} 611 612/* Nonzero if OP is a floating point condition code register. */ 613 614int 615fcc_reg_operand (op, mode) 616 rtx op; 617 enum machine_mode mode; 618{ 619 /* This can happen when recog is called from combine. Op may be a MEM. 620 Fail instead of calling abort in this case. */ 621 if (GET_CODE (op) != REG) 622 return 0; 623 624 if (mode != VOIDmode && mode != GET_MODE (op)) 625 return 0; 626 if (mode == VOIDmode 627 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 628 return 0; 629 630#if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ 631 if (reg_renumber == 0) 632 return REGNO (op) >= FIRST_PSEUDO_REGISTER; 633 return REGNO_OK_FOR_CCFP_P (REGNO (op)); 634#else 635 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; 636#endif 637} 638 639/* Nonzero if OP is a floating point condition code fcc0 register. */ 640 641int 642fcc0_reg_operand (op, mode) 643 rtx op; 644 enum machine_mode mode; 645{ 646 /* This can happen when recog is called from combine. Op may be a MEM. 647 Fail instead of calling abort in this case. */ 648 if (GET_CODE (op) != REG) 649 return 0; 650 651 if (mode != VOIDmode && mode != GET_MODE (op)) 652 return 0; 653 if (mode == VOIDmode 654 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 655 return 0; 656 657 return REGNO (op) == SPARC_FCC_REG; 658} 659 660/* Nonzero if OP is an integer or floating point condition code register. */ 661 662int 663icc_or_fcc_reg_operand (op, mode) 664 rtx op; 665 enum machine_mode mode; 666{ 667 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) 668 { 669 if (mode != VOIDmode && mode != GET_MODE (op)) 670 return 0; 671 if (mode == VOIDmode 672 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) 673 return 0; 674 return 1; 675 } 676 677 return fcc_reg_operand (op, mode); 678} 679 680/* Nonzero if OP can appear as the dest of a RESTORE insn. */ 681int 682restore_operand (op, mode) 683 rtx op; 684 enum machine_mode mode; 685{ 686 return (GET_CODE (op) == REG && GET_MODE (op) == mode 687 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); 688} 689 690/* Call insn on SPARC can take a PC-relative constant address, or any regular 691 memory address. */ 692 693int 694call_operand (op, mode) 695 rtx op; 696 enum machine_mode mode; 697{ 698 if (GET_CODE (op) != MEM) 699 abort (); 700 op = XEXP (op, 0); 701 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); 702} 703 704int 705call_operand_address (op, mode) 706 rtx op; 707 enum machine_mode mode; 708{ 709 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); 710} 711 712/* Returns 1 if OP is either a symbol reference or a sum of a symbol 713 reference and a constant. */ 714 715int 716symbolic_operand (op, mode) 717 register rtx op; 718 enum machine_mode mode; 719{ 720 enum machine_mode omode = GET_MODE (op); 721 722 if (omode != mode && omode != VOIDmode && mode != VOIDmode) 723 return 0; 724 725 switch (GET_CODE (op)) 726 { 727 case SYMBOL_REF: 728 case LABEL_REF: 729 return 1; 730 731 case CONST: 732 op = XEXP (op, 0); 733 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF 734 || GET_CODE (XEXP (op, 0)) == LABEL_REF) 735 && GET_CODE (XEXP (op, 1)) == CONST_INT); 736 737 default: 738 return 0; 739 } 740} 741 742/* Return truth value of statement that OP is a symbolic memory 743 operand of mode MODE. */ 744 745int 746symbolic_memory_operand (op, mode) 747 rtx op; 748 enum machine_mode mode ATTRIBUTE_UNUSED; 749{ 750 if (GET_CODE (op) == SUBREG) 751 op = SUBREG_REG (op); 752 if (GET_CODE (op) != MEM) 753 return 0; 754 op = XEXP (op, 0); 755 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST 756 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); 757} 758 759/* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ 760 761int 762label_ref_operand (op, mode) 763 rtx op; 764 enum machine_mode mode; 765{ 766 if (GET_CODE (op) != LABEL_REF) 767 return 0; 768 if (GET_MODE (op) != mode) 769 return 0; 770 return 1; 771} 772 773/* Return 1 if the operand is an argument used in generating pic references 774 in either the medium/low or medium/anywhere code models of sparc64. */ 775 776int 777sp64_medium_pic_operand (op, mode) 778 rtx op; 779 enum machine_mode mode ATTRIBUTE_UNUSED; 780{ 781 /* Check for (const (minus (symbol_ref:GOT) 782 (const (minus (label) (pc))))). */ 783 if (GET_CODE (op) != CONST) 784 return 0; 785 op = XEXP (op, 0); 786 if (GET_CODE (op) != MINUS) 787 return 0; 788 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) 789 return 0; 790 /* ??? Ensure symbol is GOT. */ 791 if (GET_CODE (XEXP (op, 1)) != CONST) 792 return 0; 793 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) 794 return 0; 795 return 1; 796} 797 798/* Return 1 if the operand is a data segment reference. This includes 799 the readonly data segment, or in other words anything but the text segment. 800 This is needed in the medium/anywhere code model on v9. These values 801 are accessed with EMBMEDANY_BASE_REG. */ 802 803int 804data_segment_operand (op, mode) 805 rtx op; 806 enum machine_mode mode ATTRIBUTE_UNUSED; 807{ 808 switch (GET_CODE (op)) 809 { 810 case SYMBOL_REF : 811 return ! SYMBOL_REF_FLAG (op); 812 case PLUS : 813 /* Assume canonical format of symbol + constant. 814 Fall through. */ 815 case CONST : 816 return data_segment_operand (XEXP (op, 0), VOIDmode); 817 default : 818 return 0; 819 } 820} 821 822/* Return 1 if the operand is a text segment reference. 823 This is needed in the medium/anywhere code model on v9. */ 824 825int 826text_segment_operand (op, mode) 827 rtx op; 828 enum machine_mode mode ATTRIBUTE_UNUSED; 829{ 830 switch (GET_CODE (op)) 831 { 832 case LABEL_REF : 833 return 1; 834 case SYMBOL_REF : 835 return SYMBOL_REF_FLAG (op); 836 case PLUS : 837 /* Assume canonical format of symbol + constant. 838 Fall through. */ 839 case CONST : 840 return text_segment_operand (XEXP (op, 0), VOIDmode); 841 default : 842 return 0; 843 } 844} 845 846/* Return 1 if the operand is either a register or a memory operand that is 847 not symbolic. */ 848 849int 850reg_or_nonsymb_mem_operand (op, mode) 851 register rtx op; 852 enum machine_mode mode; 853{ 854 if (register_operand (op, mode)) 855 return 1; 856 857 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) 858 return 1; 859 860 return 0; 861} 862 863int 864splittable_symbolic_memory_operand (op, mode) 865 rtx op; 866 enum machine_mode mode ATTRIBUTE_UNUSED; 867{ 868 if (GET_CODE (op) != MEM) 869 return 0; 870 if (! symbolic_operand (XEXP (op, 0), Pmode)) 871 return 0; 872 return 1; 873} 874 875int 876splittable_immediate_memory_operand (op, mode) 877 rtx op; 878 enum machine_mode mode ATTRIBUTE_UNUSED; 879{ 880 if (GET_CODE (op) != MEM) 881 return 0; 882 if (! immediate_operand (XEXP (op, 0), Pmode)) 883 return 0; 884 return 1; 885} 886 887/* Return truth value of whether OP is EQ or NE. */ 888 889int 890eq_or_neq (op, mode) 891 rtx op; 892 enum machine_mode mode ATTRIBUTE_UNUSED; 893{ 894 return (GET_CODE (op) == EQ || GET_CODE (op) == NE); 895} 896 897/* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, 898 or LTU for non-floating-point. We handle those specially. */ 899 900int 901normal_comp_operator (op, mode) 902 rtx op; 903 enum machine_mode mode ATTRIBUTE_UNUSED; 904{ 905 enum rtx_code code = GET_CODE (op); 906 907 if (GET_RTX_CLASS (code) != '<') 908 return 0; 909 910 if (GET_MODE (XEXP (op, 0)) == CCFPmode 911 || GET_MODE (XEXP (op, 0)) == CCFPEmode) 912 return 1; 913 914 return (code != NE && code != EQ && code != GEU && code != LTU); 915} 916 917/* Return 1 if this is a comparison operator. This allows the use of 918 MATCH_OPERATOR to recognize all the branch insns. */ 919 920int 921noov_compare_op (op, mode) 922 register rtx op; 923 enum machine_mode mode ATTRIBUTE_UNUSED; 924{ 925 enum rtx_code code = GET_CODE (op); 926 927 if (GET_RTX_CLASS (code) != '<') 928 return 0; 929 930 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode 931 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 932 /* These are the only branches which work with CC_NOOVmode. */ 933 return (code == EQ || code == NE || code == GE || code == LT); 934 return 1; 935} 936 937/* Return 1 if this is a 64-bit comparison operator. This allows the use of 938 MATCH_OPERATOR to recognize all the branch insns. */ 939 940int 941noov_compare64_op (op, mode) 942 register rtx op; 943 enum machine_mode mode ATTRIBUTE_UNUSED; 944{ 945 enum rtx_code code = GET_CODE (op); 946 947 if (! TARGET_V9) 948 return 0; 949 950 if (GET_RTX_CLASS (code) != '<') 951 return 0; 952 953 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 954 /* These are the only branches which work with CCX_NOOVmode. */ 955 return (code == EQ || code == NE || code == GE || code == LT); 956 return (GET_MODE (XEXP (op, 0)) == CCXmode); 957} 958 959/* Nonzero if OP is a comparison operator suitable for use in v9 960 conditional move or branch on register contents instructions. */ 961 962int 963v9_regcmp_op (op, mode) 964 register rtx op; 965 enum machine_mode mode ATTRIBUTE_UNUSED; 966{ 967 enum rtx_code code = GET_CODE (op); 968 969 if (GET_RTX_CLASS (code) != '<') 970 return 0; 971 972 return v9_regcmp_p (code); 973} 974 975/* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ 976 977int 978extend_op (op, mode) 979 rtx op; 980 enum machine_mode mode ATTRIBUTE_UNUSED; 981{ 982 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; 983} 984 985/* Return nonzero if OP is an operator of mode MODE which can set 986 the condition codes explicitly. We do not include PLUS and MINUS 987 because these require CC_NOOVmode, which we handle explicitly. */ 988 989int 990cc_arithop (op, mode) 991 rtx op; 992 enum machine_mode mode ATTRIBUTE_UNUSED; 993{ 994 if (GET_CODE (op) == AND 995 || GET_CODE (op) == IOR 996 || GET_CODE (op) == XOR) 997 return 1; 998 999 return 0; 1000} 1001 1002/* Return nonzero if OP is an operator of mode MODE which can bitwise 1003 complement its second operand and set the condition codes explicitly. */ 1004 1005int 1006cc_arithopn (op, mode) 1007 rtx op; 1008 enum machine_mode mode ATTRIBUTE_UNUSED; 1009{ 1010 /* XOR is not here because combine canonicalizes (xor (not ...) ...) 1011 and (xor ... (not ...)) to (not (xor ...)). */ 1012 return (GET_CODE (op) == AND 1013 || GET_CODE (op) == IOR); 1014} 1015 1016/* Return true if OP is a register, or is a CONST_INT that can fit in a 1017 signed 13 bit immediate field. This is an acceptable SImode operand for 1018 most 3 address instructions. */ 1019 1020int 1021arith_operand (op, mode) 1022 rtx op; 1023 enum machine_mode mode; 1024{ 1025 if (register_operand (op, mode)) 1026 return 1; 1027 if (GET_CODE (op) != CONST_INT) 1028 return 0; 1029 return SMALL_INT32 (op); 1030} 1031 1032/* Return true if OP is a constant 4096 */ 1033 1034int 1035arith_4096_operand (op, mode) 1036 rtx op; 1037 enum machine_mode mode ATTRIBUTE_UNUSED; 1038{ 1039 if (GET_CODE (op) != CONST_INT) 1040 return 0; 1041 else 1042 return INTVAL (op) == 4096; 1043} 1044 1045/* Return true if OP is suitable as second operand for add/sub */ 1046 1047int 1048arith_add_operand (op, mode) 1049 rtx op; 1050 enum machine_mode mode; 1051{ 1052 return arith_operand (op, mode) || arith_4096_operand (op, mode); 1053} 1054 1055/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the 1056 immediate field of OR and XOR instructions. Used for 64-bit 1057 constant formation patterns. */ 1058int 1059const64_operand (op, mode) 1060 rtx op; 1061 enum machine_mode mode ATTRIBUTE_UNUSED; 1062{ 1063 return ((GET_CODE (op) == CONST_INT 1064 && SPARC_SIMM13_P (INTVAL (op))) 1065#if HOST_BITS_PER_WIDE_INT != 64 1066 || (GET_CODE (op) == CONST_DOUBLE 1067 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) 1068 && (CONST_DOUBLE_HIGH (op) == 1069 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? 1070 (HOST_WIDE_INT)-1 : 0))) 1071#endif 1072 ); 1073} 1074 1075/* The same, but only for sethi instructions. */ 1076int 1077const64_high_operand (op, mode) 1078 rtx op; 1079 enum machine_mode mode; 1080{ 1081 return ((GET_CODE (op) == CONST_INT 1082 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0 1083 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) 1084 ) 1085 || (GET_CODE (op) == CONST_DOUBLE 1086 && CONST_DOUBLE_HIGH (op) == 0 1087 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0 1088 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); 1089} 1090 1091/* Return true if OP is a register, or is a CONST_INT that can fit in a 1092 signed 11 bit immediate field. This is an acceptable SImode operand for 1093 the movcc instructions. */ 1094 1095int 1096arith11_operand (op, mode) 1097 rtx op; 1098 enum machine_mode mode; 1099{ 1100 return (register_operand (op, mode) 1101 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); 1102} 1103 1104/* Return true if OP is a register, or is a CONST_INT that can fit in a 1105 signed 10 bit immediate field. This is an acceptable SImode operand for 1106 the movrcc instructions. */ 1107 1108int 1109arith10_operand (op, mode) 1110 rtx op; 1111 enum machine_mode mode; 1112{ 1113 return (register_operand (op, mode) 1114 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); 1115} 1116 1117/* Return true if OP is a register, is a CONST_INT that fits in a 13 bit 1118 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit 1119 immediate field. 1120 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1121 can fit in a 13 bit immediate field. This is an acceptable DImode operand 1122 for most 3 address instructions. */ 1123 1124int 1125arith_double_operand (op, mode) 1126 rtx op; 1127 enum machine_mode mode; 1128{ 1129 return (register_operand (op, mode) 1130 || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) 1131 || (! TARGET_ARCH64 1132 && GET_CODE (op) == CONST_DOUBLE 1133 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 1134 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) 1135 || (TARGET_ARCH64 1136 && GET_CODE (op) == CONST_DOUBLE 1137 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 1138 && ((CONST_DOUBLE_HIGH (op) == -1 1139 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) 1140 || (CONST_DOUBLE_HIGH (op) == 0 1141 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); 1142} 1143 1144/* Return true if OP is a constant 4096 for DImode on ARCH64 */ 1145 1146int 1147arith_double_4096_operand (op, mode) 1148 rtx op; 1149 enum machine_mode mode ATTRIBUTE_UNUSED; 1150{ 1151 return (TARGET_ARCH64 && 1152 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || 1153 (GET_CODE (op) == CONST_DOUBLE && 1154 CONST_DOUBLE_LOW (op) == 4096 && 1155 CONST_DOUBLE_HIGH (op) == 0))); 1156} 1157 1158/* Return true if OP is suitable as second operand for add/sub in DImode */ 1159 1160int 1161arith_double_add_operand (op, mode) 1162 rtx op; 1163 enum machine_mode mode; 1164{ 1165 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); 1166} 1167 1168/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1169 can fit in an 11 bit immediate field. This is an acceptable DImode 1170 operand for the movcc instructions. */ 1171/* ??? Replace with arith11_operand? */ 1172 1173int 1174arith11_double_operand (op, mode) 1175 rtx op; 1176 enum machine_mode mode; 1177{ 1178 return (register_operand (op, mode) 1179 || (GET_CODE (op) == CONST_DOUBLE 1180 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1181 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 1182 && ((CONST_DOUBLE_HIGH (op) == -1 1183 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) 1184 || (CONST_DOUBLE_HIGH (op) == 0 1185 && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) 1186 || (GET_CODE (op) == CONST_INT 1187 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1188 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); 1189} 1190 1191/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1192 can fit in an 10 bit immediate field. This is an acceptable DImode 1193 operand for the movrcc instructions. */ 1194/* ??? Replace with arith10_operand? */ 1195 1196int 1197arith10_double_operand (op, mode) 1198 rtx op; 1199 enum machine_mode mode; 1200{ 1201 return (register_operand (op, mode) 1202 || (GET_CODE (op) == CONST_DOUBLE 1203 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1204 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 1205 && ((CONST_DOUBLE_HIGH (op) == -1 1206 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) 1207 || (CONST_DOUBLE_HIGH (op) == 0 1208 && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) 1209 || (GET_CODE (op) == CONST_INT 1210 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1211 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); 1212} 1213 1214/* Return truth value of whether OP is an integer which fits the 1215 range constraining immediate operands in most three-address insns, 1216 which have a 13 bit immediate field. */ 1217 1218int 1219small_int (op, mode) 1220 rtx op; 1221 enum machine_mode mode ATTRIBUTE_UNUSED; 1222{ 1223 return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); 1224} 1225 1226int 1227small_int_or_double (op, mode) 1228 rtx op; 1229 enum machine_mode mode ATTRIBUTE_UNUSED; 1230{ 1231 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) 1232 || (GET_CODE (op) == CONST_DOUBLE 1233 && CONST_DOUBLE_HIGH (op) == 0 1234 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); 1235} 1236 1237/* Recognize operand values for the umul instruction. That instruction sign 1238 extends immediate values just like all other sparc instructions, but 1239 interprets the extended result as an unsigned number. */ 1240 1241int 1242uns_small_int (op, mode) 1243 rtx op; 1244 enum machine_mode mode ATTRIBUTE_UNUSED; 1245{ 1246#if HOST_BITS_PER_WIDE_INT > 32 1247 /* All allowed constants will fit a CONST_INT. */ 1248 return (GET_CODE (op) == CONST_INT 1249 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) 1250 || (INTVAL (op) >= 0xFFFFF000 1251 && INTVAL (op) <= 0xFFFFFFFF))); 1252#else 1253 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) 1254 || (GET_CODE (op) == CONST_DOUBLE 1255 && CONST_DOUBLE_HIGH (op) == 0 1256 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); 1257#endif 1258} 1259 1260int 1261uns_arith_operand (op, mode) 1262 rtx op; 1263 enum machine_mode mode; 1264{ 1265 return register_operand (op, mode) || uns_small_int (op, mode); 1266} 1267 1268/* Return truth value of statement that OP is a call-clobbered register. */ 1269int 1270clobbered_register (op, mode) 1271 rtx op; 1272 enum machine_mode mode ATTRIBUTE_UNUSED; 1273{ 1274 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); 1275} 1276 1277/* Return 1 if OP is a valid operand for the source of a move insn. */ 1278 1279int 1280input_operand (op, mode) 1281 rtx op; 1282 enum machine_mode mode; 1283{ 1284 /* If both modes are non-void they must be the same. */ 1285 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) 1286 return 0; 1287 1288 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ 1289 if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX) 1290 return 1; 1291 1292 /* Allow any one instruction integer constant, and all CONST_INT 1293 variants when we are working in DImode and !arch64. */ 1294 if (GET_MODE_CLASS (mode) == MODE_INT 1295 && ((GET_CODE (op) == CONST_INT 1296 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) 1297 || SPARC_SIMM13_P (INTVAL (op)) 1298 || (mode == DImode 1299 && ! TARGET_ARCH64))) 1300 || (TARGET_ARCH64 1301 && GET_CODE (op) == CONST_DOUBLE 1302 && ((CONST_DOUBLE_HIGH (op) == 0 1303 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) 1304 || 1305#if HOST_BITS_PER_WIDE_INT == 64 1306 (CONST_DOUBLE_HIGH (op) == 0 1307 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) 1308#else 1309 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) 1310 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 1311 && CONST_DOUBLE_HIGH (op) == 0) 1312 || (CONST_DOUBLE_HIGH (op) == -1 1313 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0)) 1314#endif 1315 )))) 1316 return 1; 1317 1318 /* If !arch64 and this is a DImode const, allow it so that 1319 the splits can be generated. */ 1320 if (! TARGET_ARCH64 1321 && mode == DImode 1322 && GET_CODE (op) == CONST_DOUBLE) 1323 return 1; 1324 1325 if (register_operand (op, mode)) 1326 return 1; 1327 1328 if (GET_MODE_CLASS (mode) == MODE_FLOAT 1329 && GET_CODE (op) == CONST_DOUBLE) 1330 return 1; 1331 1332 /* If this is a SUBREG, look inside so that we handle 1333 paradoxical ones. */ 1334 if (GET_CODE (op) == SUBREG) 1335 op = SUBREG_REG (op); 1336 1337 /* Check for valid MEM forms. */ 1338 if (GET_CODE (op) == MEM) 1339 { 1340 rtx inside = XEXP (op, 0); 1341 1342 if (GET_CODE (inside) == LO_SUM) 1343 { 1344 /* We can't allow these because all of the splits 1345 (eventually as they trickle down into DFmode 1346 splits) require offsettable memory references. */ 1347 if (! TARGET_V9 1348 && GET_MODE (op) == TFmode) 1349 return 0; 1350 1351 return (register_operand (XEXP (inside, 0), Pmode) 1352 && CONSTANT_P (XEXP (inside, 1))); 1353 } 1354 return memory_address_p (mode, inside); 1355 } 1356 1357 return 0; 1358} 1359 1360 1361/* We know it can't be done in one insn when we get here, 1362 the movsi expander guarentees this. */ 1363void 1364sparc_emit_set_const32 (op0, op1) 1365 rtx op0; 1366 rtx op1; 1367{ 1368 enum machine_mode mode = GET_MODE (op0); 1369 rtx temp; 1370 1371 if (GET_CODE (op1) == CONST_INT) 1372 { 1373 HOST_WIDE_INT value = INTVAL (op1); 1374 1375 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode)) 1376 || SPARC_SIMM13_P (value)) 1377 abort (); 1378 } 1379 1380 /* Full 2-insn decomposition is needed. */ 1381 if (reload_in_progress || reload_completed) 1382 temp = op0; 1383 else 1384 temp = gen_reg_rtx (mode); 1385 1386 if (GET_CODE (op1) == CONST_INT) 1387 { 1388 /* Emit them as real moves instead of a HIGH/LO_SUM, 1389 this way CSE can see everything and reuse intermediate 1390 values if it wants. */ 1391 if (TARGET_ARCH64 1392 && HOST_BITS_PER_WIDE_INT != 64 1393 && (INTVAL (op1) & 0x80000000) != 0) 1394 emit_insn (gen_rtx_SET 1395 (VOIDmode, temp, 1396 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff, 1397 0, DImode))); 1398 else 1399 emit_insn (gen_rtx_SET (VOIDmode, temp, 1400 GEN_INT (INTVAL (op1) 1401 & ~(HOST_WIDE_INT)0x3ff))); 1402 1403 emit_insn (gen_rtx_SET (VOIDmode, 1404 op0, 1405 gen_rtx_IOR (mode, temp, 1406 GEN_INT (INTVAL (op1) & 0x3ff)))); 1407 } 1408 else 1409 { 1410 /* A symbol, emit in the traditional way. */ 1411 emit_insn (gen_rtx_SET (VOIDmode, temp, 1412 gen_rtx_HIGH (mode, op1))); 1413 emit_insn (gen_rtx_SET (VOIDmode, 1414 op0, gen_rtx_LO_SUM (mode, temp, op1))); 1415 1416 } 1417} 1418 1419 1420/* SPARC-v9 code-model support. */ 1421void 1422sparc_emit_set_symbolic_const64 (op0, op1, temp1) 1423 rtx op0; 1424 rtx op1; 1425 rtx temp1; 1426{ 1427 rtx ti_temp1 = 0; 1428 1429 if (temp1 && GET_MODE (temp1) == TImode) 1430 { 1431 ti_temp1 = temp1; 1432 temp1 = gen_rtx_REG (DImode, REGNO (temp1)); 1433 } 1434 1435 switch (sparc_cmodel) 1436 { 1437 case CM_MEDLOW: 1438 /* The range spanned by all instructions in the object is less 1439 than 2^31 bytes (2GB) and the distance from any instruction 1440 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1441 than 2^31 bytes (2GB). 1442 1443 The executable must be in the low 4TB of the virtual address 1444 space. 1445 1446 sethi %hi(symbol), %temp 1447 or %temp, %lo(symbol), %reg */ 1448 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); 1449 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); 1450 break; 1451 1452 case CM_MEDMID: 1453 /* The range spanned by all instructions in the object is less 1454 than 2^31 bytes (2GB) and the distance from any instruction 1455 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1456 than 2^31 bytes (2GB). 1457 1458 The executable must be in the low 16TB of the virtual address 1459 space. 1460 1461 sethi %h44(symbol), %temp1 1462 or %temp1, %m44(symbol), %temp2 1463 sllx %temp2, 12, %temp3 1464 or %temp3, %l44(symbol), %reg */ 1465 emit_insn (gen_seth44 (op0, op1)); 1466 emit_insn (gen_setm44 (op0, op0, op1)); 1467 emit_insn (gen_rtx_SET (VOIDmode, temp1, 1468 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12)))); 1469 emit_insn (gen_setl44 (op0, temp1, op1)); 1470 break; 1471 1472 case CM_MEDANY: 1473 /* The range spanned by all instructions in the object is less 1474 than 2^31 bytes (2GB) and the distance from any instruction 1475 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1476 than 2^31 bytes (2GB). 1477 1478 The executable can be placed anywhere in the virtual address 1479 space. 1480 1481 sethi %hh(symbol), %temp1 1482 sethi %lm(symbol), %temp2 1483 or %temp1, %hm(symbol), %temp3 1484 or %temp2, %lo(symbol), %temp4 1485 sllx %temp3, 32, %temp5 1486 or %temp4, %temp5, %reg */ 1487 1488 /* It is possible that one of the registers we got for operands[2] 1489 might coincide with that of operands[0] (which is why we made 1490 it TImode). Pick the other one to use as our scratch. */ 1491 if (rtx_equal_p (temp1, op0)) 1492 { 1493 if (ti_temp1) 1494 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); 1495 else 1496 abort(); 1497 } 1498 1499 emit_insn (gen_sethh (op0, op1)); 1500 emit_insn (gen_setlm (temp1, op1)); 1501 emit_insn (gen_sethm (op0, op0, op1)); 1502 emit_insn (gen_rtx_SET (VOIDmode, op0, 1503 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); 1504 emit_insn (gen_rtx_SET (VOIDmode, op0, 1505 gen_rtx_PLUS (DImode, op0, temp1))); 1506 emit_insn (gen_setlo (op0, op0, op1)); 1507 break; 1508 1509 case CM_EMBMEDANY: 1510 /* Old old old backwards compatibility kruft here. 1511 Essentially it is MEDLOW with a fixed 64-bit 1512 virtual base added to all data segment addresses. 1513 Text-segment stuff is computed like MEDANY, we can't 1514 reuse the code above because the relocation knobs 1515 look different. 1516 1517 Data segment: sethi %hi(symbol), %temp1 1518 or %temp1, %lo(symbol), %temp2 1519 add %temp2, EMBMEDANY_BASE_REG, %reg 1520 1521 Text segment: sethi %uhi(symbol), %temp1 1522 sethi %hi(symbol), %temp2 1523 or %temp1, %ulo(symbol), %temp3 1524 or %temp2, %lo(symbol), %temp4 1525 sllx %temp3, 32, %temp5 1526 or %temp4, %temp5, %reg */ 1527 if (data_segment_operand (op1, GET_MODE (op1))) 1528 { 1529 emit_insn (gen_embmedany_sethi (temp1, op1)); 1530 emit_insn (gen_embmedany_brsum (op0, temp1)); 1531 emit_insn (gen_embmedany_losum (op0, op0, op1)); 1532 } 1533 else 1534 { 1535 /* It is possible that one of the registers we got for operands[2] 1536 might coincide with that of operands[0] (which is why we made 1537 it TImode). Pick the other one to use as our scratch. */ 1538 if (rtx_equal_p (temp1, op0)) 1539 { 1540 if (ti_temp1) 1541 temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); 1542 else 1543 abort(); 1544 } 1545 1546 emit_insn (gen_embmedany_textuhi (op0, op1)); 1547 emit_insn (gen_embmedany_texthi (temp1, op1)); 1548 emit_insn (gen_embmedany_textulo (op0, op0, op1)); 1549 emit_insn (gen_rtx_SET (VOIDmode, op0, 1550 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); 1551 emit_insn (gen_rtx_SET (VOIDmode, op0, 1552 gen_rtx_PLUS (DImode, op0, temp1))); 1553 emit_insn (gen_embmedany_textlo (op0, op0, op1)); 1554 } 1555 break; 1556 1557 default: 1558 abort(); 1559 } 1560} 1561 1562/* These avoid problems when cross compiling. If we do not 1563 go through all this hair then the optimizer will see 1564 invalid REG_EQUAL notes or in some cases none at all. */ 1565static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT)); 1566static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT)); 1567static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT)); 1568static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT)); 1569 1570#if HOST_BITS_PER_WIDE_INT == 64 1571#define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff) 1572#define GEN_INT64(__x) GEN_INT (__x) 1573#else 1574#define GEN_HIGHINT64(__x) \ 1575 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode) 1576#define GEN_INT64(__x) \ 1577 immed_double_const ((__x) & 0xffffffff, \ 1578 ((__x) & 0x80000000 ? -1 : 0), DImode) 1579#endif 1580 1581/* The optimizer is not to assume anything about exactly 1582 which bits are set for a HIGH, they are unspecified. 1583 Unfortunately this leads to many missed optimizations 1584 during CSE. We mask out the non-HIGH bits, and matches 1585 a plain movdi, to alleviate this problem. */ 1586static void 1587sparc_emit_set_safe_HIGH64 (dest, val) 1588 rtx dest; 1589 HOST_WIDE_INT val; 1590{ 1591 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); 1592} 1593 1594static rtx 1595gen_safe_SET64 (dest, val) 1596 rtx dest; 1597 HOST_WIDE_INT val; 1598{ 1599 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); 1600} 1601 1602static rtx 1603gen_safe_OR64 (src, val) 1604 rtx src; 1605 HOST_WIDE_INT val; 1606{ 1607 return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); 1608} 1609 1610static rtx 1611gen_safe_XOR64 (src, val) 1612 rtx src; 1613 HOST_WIDE_INT val; 1614{ 1615 return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); 1616} 1617 1618/* Worker routines for 64-bit constant formation on arch64. 1619 One of the key things to be doing in these emissions is 1620 to create as many temp REGs as possible. This makes it 1621 possible for half-built constants to be used later when 1622 such values are similar to something required later on. 1623 Without doing this, the optimizer cannot see such 1624 opportunities. */ 1625 1626static void sparc_emit_set_const64_quick1 1627 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int)); 1628 1629static void 1630sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg) 1631 rtx op0; 1632 rtx temp; 1633 unsigned HOST_WIDE_INT low_bits; 1634 int is_neg; 1635{ 1636 unsigned HOST_WIDE_INT high_bits; 1637 1638 if (is_neg) 1639 high_bits = (~low_bits) & 0xffffffff; 1640 else 1641 high_bits = low_bits; 1642 1643 sparc_emit_set_safe_HIGH64 (temp, high_bits); 1644 if (!is_neg) 1645 { 1646 emit_insn (gen_rtx_SET (VOIDmode, op0, 1647 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1648 } 1649 else 1650 { 1651 /* If we are XOR'ing with -1, then we should emit a one's complement 1652 instead. This way the combiner will notice logical operations 1653 such as ANDN later on and substitute. */ 1654 if ((low_bits & 0x3ff) == 0x3ff) 1655 { 1656 emit_insn (gen_rtx_SET (VOIDmode, op0, 1657 gen_rtx_NOT (DImode, temp))); 1658 } 1659 else 1660 { 1661 emit_insn (gen_rtx_SET (VOIDmode, op0, 1662 gen_safe_XOR64 (temp, 1663 (-(HOST_WIDE_INT)0x400 1664 | (low_bits & 0x3ff))))); 1665 } 1666 } 1667} 1668 1669static void sparc_emit_set_const64_quick2 1670 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, 1671 unsigned HOST_WIDE_INT, int)); 1672 1673static void 1674sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count) 1675 rtx op0; 1676 rtx temp; 1677 unsigned HOST_WIDE_INT high_bits; 1678 unsigned HOST_WIDE_INT low_immediate; 1679 int shift_count; 1680{ 1681 rtx temp2 = op0; 1682 1683 if ((high_bits & 0xfffffc00) != 0) 1684 { 1685 sparc_emit_set_safe_HIGH64 (temp, high_bits); 1686 if ((high_bits & ~0xfffffc00) != 0) 1687 emit_insn (gen_rtx_SET (VOIDmode, op0, 1688 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1689 else 1690 temp2 = temp; 1691 } 1692 else 1693 { 1694 emit_insn (gen_safe_SET64 (temp, high_bits)); 1695 temp2 = temp; 1696 } 1697 1698 /* Now shift it up into place. */ 1699 emit_insn (gen_rtx_SET (VOIDmode, op0, 1700 gen_rtx_ASHIFT (DImode, temp2, 1701 GEN_INT (shift_count)))); 1702 1703 /* If there is a low immediate part piece, finish up by 1704 putting that in as well. */ 1705 if (low_immediate != 0) 1706 emit_insn (gen_rtx_SET (VOIDmode, op0, 1707 gen_safe_OR64 (op0, low_immediate))); 1708} 1709 1710static void sparc_emit_set_const64_longway 1711 PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); 1712 1713/* Full 64-bit constant decomposition. Even though this is the 1714 'worst' case, we still optimize a few things away. */ 1715static void 1716sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits) 1717 rtx op0; 1718 rtx temp; 1719 unsigned HOST_WIDE_INT high_bits; 1720 unsigned HOST_WIDE_INT low_bits; 1721{ 1722 rtx sub_temp; 1723 1724 if (reload_in_progress || reload_completed) 1725 sub_temp = op0; 1726 else 1727 sub_temp = gen_reg_rtx (DImode); 1728 1729 if ((high_bits & 0xfffffc00) != 0) 1730 { 1731 sparc_emit_set_safe_HIGH64 (temp, high_bits); 1732 if ((high_bits & ~0xfffffc00) != 0) 1733 emit_insn (gen_rtx_SET (VOIDmode, 1734 sub_temp, 1735 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1736 else 1737 sub_temp = temp; 1738 } 1739 else 1740 { 1741 emit_insn (gen_safe_SET64 (temp, high_bits)); 1742 sub_temp = temp; 1743 } 1744 1745 if (!reload_in_progress && !reload_completed) 1746 { 1747 rtx temp2 = gen_reg_rtx (DImode); 1748 rtx temp3 = gen_reg_rtx (DImode); 1749 rtx temp4 = gen_reg_rtx (DImode); 1750 1751 emit_insn (gen_rtx_SET (VOIDmode, temp4, 1752 gen_rtx_ASHIFT (DImode, sub_temp, 1753 GEN_INT (32)))); 1754 1755 sparc_emit_set_safe_HIGH64 (temp2, low_bits); 1756 if ((low_bits & ~0xfffffc00) != 0) 1757 { 1758 emit_insn (gen_rtx_SET (VOIDmode, temp3, 1759 gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); 1760 emit_insn (gen_rtx_SET (VOIDmode, op0, 1761 gen_rtx_PLUS (DImode, temp4, temp3))); 1762 } 1763 else 1764 { 1765 emit_insn (gen_rtx_SET (VOIDmode, op0, 1766 gen_rtx_PLUS (DImode, temp4, temp2))); 1767 } 1768 } 1769 else 1770 { 1771 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); 1772 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); 1773 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); 1774 int to_shift = 12; 1775 1776 /* We are in the middle of reload, so this is really 1777 painful. However we do still make an attempt to 1778 avoid emitting truly stupid code. */ 1779 if (low1 != const0_rtx) 1780 { 1781 emit_insn (gen_rtx_SET (VOIDmode, op0, 1782 gen_rtx_ASHIFT (DImode, sub_temp, 1783 GEN_INT (to_shift)))); 1784 emit_insn (gen_rtx_SET (VOIDmode, op0, 1785 gen_rtx_IOR (DImode, op0, low1))); 1786 sub_temp = op0; 1787 to_shift = 12; 1788 } 1789 else 1790 { 1791 to_shift += 12; 1792 } 1793 if (low2 != const0_rtx) 1794 { 1795 emit_insn (gen_rtx_SET (VOIDmode, op0, 1796 gen_rtx_ASHIFT (DImode, sub_temp, 1797 GEN_INT (to_shift)))); 1798 emit_insn (gen_rtx_SET (VOIDmode, op0, 1799 gen_rtx_IOR (DImode, op0, low2))); 1800 sub_temp = op0; 1801 to_shift = 8; 1802 } 1803 else 1804 { 1805 to_shift += 8; 1806 } 1807 emit_insn (gen_rtx_SET (VOIDmode, op0, 1808 gen_rtx_ASHIFT (DImode, sub_temp, 1809 GEN_INT (to_shift)))); 1810 if (low3 != const0_rtx) 1811 emit_insn (gen_rtx_SET (VOIDmode, op0, 1812 gen_rtx_IOR (DImode, op0, low3))); 1813 /* phew... */ 1814 } 1815} 1816 1817/* Analyze a 64-bit constant for certain properties. */ 1818static void analyze_64bit_constant 1819 PARAMS ((unsigned HOST_WIDE_INT, 1820 unsigned HOST_WIDE_INT, 1821 int *, int *, int *)); 1822 1823static void 1824analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp) 1825 unsigned HOST_WIDE_INT high_bits, low_bits; 1826 int *hbsp, *lbsp, *abbasp; 1827{ 1828 int lowest_bit_set, highest_bit_set, all_bits_between_are_set; 1829 int i; 1830 1831 lowest_bit_set = highest_bit_set = -1; 1832 i = 0; 1833 do 1834 { 1835 if ((lowest_bit_set == -1) 1836 && ((low_bits >> i) & 1)) 1837 lowest_bit_set = i; 1838 if ((highest_bit_set == -1) 1839 && ((high_bits >> (32 - i - 1)) & 1)) 1840 highest_bit_set = (64 - i - 1); 1841 } 1842 while (++i < 32 1843 && ((highest_bit_set == -1) 1844 || (lowest_bit_set == -1))); 1845 if (i == 32) 1846 { 1847 i = 0; 1848 do 1849 { 1850 if ((lowest_bit_set == -1) 1851 && ((high_bits >> i) & 1)) 1852 lowest_bit_set = i + 32; 1853 if ((highest_bit_set == -1) 1854 && ((low_bits >> (32 - i - 1)) & 1)) 1855 highest_bit_set = 32 - i - 1; 1856 } 1857 while (++i < 32 1858 && ((highest_bit_set == -1) 1859 || (lowest_bit_set == -1))); 1860 } 1861 /* If there are no bits set this should have gone out 1862 as one instruction! */ 1863 if (lowest_bit_set == -1 1864 || highest_bit_set == -1) 1865 abort (); 1866 all_bits_between_are_set = 1; 1867 for (i = lowest_bit_set; i <= highest_bit_set; i++) 1868 { 1869 if (i < 32) 1870 { 1871 if ((low_bits & (1 << i)) != 0) 1872 continue; 1873 } 1874 else 1875 { 1876 if ((high_bits & (1 << (i - 32))) != 0) 1877 continue; 1878 } 1879 all_bits_between_are_set = 0; 1880 break; 1881 } 1882 *hbsp = highest_bit_set; 1883 *lbsp = lowest_bit_set; 1884 *abbasp = all_bits_between_are_set; 1885} 1886 1887static int const64_is_2insns 1888 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); 1889 1890static int 1891const64_is_2insns (high_bits, low_bits) 1892 unsigned HOST_WIDE_INT high_bits, low_bits; 1893{ 1894 int highest_bit_set, lowest_bit_set, all_bits_between_are_set; 1895 1896 if (high_bits == 0 1897 || high_bits == 0xffffffff) 1898 return 1; 1899 1900 analyze_64bit_constant (high_bits, low_bits, 1901 &highest_bit_set, &lowest_bit_set, 1902 &all_bits_between_are_set); 1903 1904 if ((highest_bit_set == 63 1905 || lowest_bit_set == 0) 1906 && all_bits_between_are_set != 0) 1907 return 1; 1908 1909 if ((highest_bit_set - lowest_bit_set) < 21) 1910 return 1; 1911 1912 return 0; 1913} 1914 1915static unsigned HOST_WIDE_INT create_simple_focus_bits 1916 PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, 1917 int, int)); 1918 1919static unsigned HOST_WIDE_INT 1920create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift) 1921 unsigned HOST_WIDE_INT high_bits, low_bits; 1922 int lowest_bit_set, shift; 1923{ 1924 HOST_WIDE_INT hi, lo; 1925 1926 if (lowest_bit_set < 32) 1927 { 1928 lo = (low_bits >> lowest_bit_set) << shift; 1929 hi = ((high_bits << (32 - lowest_bit_set)) << shift); 1930 } 1931 else 1932 { 1933 lo = 0; 1934 hi = ((high_bits >> (lowest_bit_set - 32)) << shift); 1935 } 1936 if (hi & lo) 1937 abort (); 1938 return (hi | lo); 1939} 1940 1941/* Here we are sure to be arch64 and this is an integer constant 1942 being loaded into a register. Emit the most efficient 1943 insn sequence possible. Detection of all the 1-insn cases 1944 has been done already. */ 1945void 1946sparc_emit_set_const64 (op0, op1) 1947 rtx op0; 1948 rtx op1; 1949{ 1950 unsigned HOST_WIDE_INT high_bits, low_bits; 1951 int lowest_bit_set, highest_bit_set; 1952 int all_bits_between_are_set; 1953 rtx temp; 1954 1955 /* Sanity check that we know what we are working with. */ 1956 if (! TARGET_ARCH64) 1957 abort (); 1958 1959 if (GET_CODE (op0) != SUBREG) 1960 { 1961 if (GET_CODE (op0) != REG 1962 || (REGNO (op0) >= SPARC_FIRST_FP_REG 1963 && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) 1964 abort (); 1965 } 1966 1967 if (reload_in_progress || reload_completed) 1968 temp = op0; 1969 else 1970 temp = gen_reg_rtx (DImode); 1971 1972 if (GET_CODE (op1) != CONST_DOUBLE 1973 && GET_CODE (op1) != CONST_INT) 1974 { 1975 sparc_emit_set_symbolic_const64 (op0, op1, temp); 1976 return; 1977 } 1978 1979 if (GET_CODE (op1) == CONST_DOUBLE) 1980 { 1981#if HOST_BITS_PER_WIDE_INT == 64 1982 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; 1983 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; 1984#else 1985 high_bits = CONST_DOUBLE_HIGH (op1); 1986 low_bits = CONST_DOUBLE_LOW (op1); 1987#endif 1988 } 1989 else 1990 { 1991#if HOST_BITS_PER_WIDE_INT == 64 1992 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); 1993 low_bits = (INTVAL (op1) & 0xffffffff); 1994#else 1995 high_bits = ((INTVAL (op1) < 0) ? 1996 0xffffffff : 1997 0x00000000); 1998 low_bits = INTVAL (op1); 1999#endif 2000 } 2001 2002 /* low_bits bits 0 --> 31 2003 high_bits bits 32 --> 63 */ 2004 2005 analyze_64bit_constant (high_bits, low_bits, 2006 &highest_bit_set, &lowest_bit_set, 2007 &all_bits_between_are_set); 2008 2009 /* First try for a 2-insn sequence. */ 2010 2011 /* These situations are preferred because the optimizer can 2012 * do more things with them: 2013 * 1) mov -1, %reg 2014 * sllx %reg, shift, %reg 2015 * 2) mov -1, %reg 2016 * srlx %reg, shift, %reg 2017 * 3) mov some_small_const, %reg 2018 * sllx %reg, shift, %reg 2019 */ 2020 if (((highest_bit_set == 63 2021 || lowest_bit_set == 0) 2022 && all_bits_between_are_set != 0) 2023 || ((highest_bit_set - lowest_bit_set) < 12)) 2024 { 2025 HOST_WIDE_INT the_const = -1; 2026 int shift = lowest_bit_set; 2027 2028 if ((highest_bit_set != 63 2029 && lowest_bit_set != 0) 2030 || all_bits_between_are_set == 0) 2031 { 2032 the_const = 2033 create_simple_focus_bits (high_bits, low_bits, 2034 lowest_bit_set, 0); 2035 } 2036 else if (lowest_bit_set == 0) 2037 shift = -(63 - highest_bit_set); 2038 2039 if (! SPARC_SIMM13_P (the_const)) 2040 abort (); 2041 2042 emit_insn (gen_safe_SET64 (temp, the_const)); 2043 if (shift > 0) 2044 emit_insn (gen_rtx_SET (VOIDmode, 2045 op0, 2046 gen_rtx_ASHIFT (DImode, 2047 temp, 2048 GEN_INT (shift)))); 2049 else if (shift < 0) 2050 emit_insn (gen_rtx_SET (VOIDmode, 2051 op0, 2052 gen_rtx_LSHIFTRT (DImode, 2053 temp, 2054 GEN_INT (-shift)))); 2055 else 2056 abort (); 2057 return; 2058 } 2059 2060 /* Now a range of 22 or less bits set somewhere. 2061 * 1) sethi %hi(focus_bits), %reg 2062 * sllx %reg, shift, %reg 2063 * 2) sethi %hi(focus_bits), %reg 2064 * srlx %reg, shift, %reg 2065 */ 2066 if ((highest_bit_set - lowest_bit_set) < 21) 2067 { 2068 unsigned HOST_WIDE_INT focus_bits = 2069 create_simple_focus_bits (high_bits, low_bits, 2070 lowest_bit_set, 10); 2071 2072 if (! SPARC_SETHI_P (focus_bits)) 2073 abort (); 2074 2075 sparc_emit_set_safe_HIGH64 (temp, focus_bits); 2076 2077 /* If lowest_bit_set == 10 then a sethi alone could have done it. */ 2078 if (lowest_bit_set < 10) 2079 emit_insn (gen_rtx_SET (VOIDmode, 2080 op0, 2081 gen_rtx_LSHIFTRT (DImode, temp, 2082 GEN_INT (10 - lowest_bit_set)))); 2083 else if (lowest_bit_set > 10) 2084 emit_insn (gen_rtx_SET (VOIDmode, 2085 op0, 2086 gen_rtx_ASHIFT (DImode, temp, 2087 GEN_INT (lowest_bit_set - 10)))); 2088 else 2089 abort (); 2090 return; 2091 } 2092 2093 /* 1) sethi %hi(low_bits), %reg 2094 * or %reg, %lo(low_bits), %reg 2095 * 2) sethi %hi(~low_bits), %reg 2096 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg 2097 */ 2098 if (high_bits == 0 2099 || high_bits == 0xffffffff) 2100 { 2101 sparc_emit_set_const64_quick1 (op0, temp, low_bits, 2102 (high_bits == 0xffffffff)); 2103 return; 2104 } 2105 2106 /* Now, try 3-insn sequences. */ 2107 2108 /* 1) sethi %hi(high_bits), %reg 2109 * or %reg, %lo(high_bits), %reg 2110 * sllx %reg, 32, %reg 2111 */ 2112 if (low_bits == 0) 2113 { 2114 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); 2115 return; 2116 } 2117 2118 /* We may be able to do something quick 2119 when the constant is negated, so try that. */ 2120 if (const64_is_2insns ((~high_bits) & 0xffffffff, 2121 (~low_bits) & 0xfffffc00)) 2122 { 2123 /* NOTE: The trailing bits get XOR'd so we need the 2124 non-negated bits, not the negated ones. */ 2125 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; 2126 2127 if ((((~high_bits) & 0xffffffff) == 0 2128 && ((~low_bits) & 0x80000000) == 0) 2129 || (((~high_bits) & 0xffffffff) == 0xffffffff 2130 && ((~low_bits) & 0x80000000) != 0)) 2131 { 2132 int fast_int = (~low_bits & 0xffffffff); 2133 2134 if ((SPARC_SETHI_P (fast_int) 2135 && (~high_bits & 0xffffffff) == 0) 2136 || SPARC_SIMM13_P (fast_int)) 2137 emit_insn (gen_safe_SET64 (temp, fast_int)); 2138 else 2139 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); 2140 } 2141 else 2142 { 2143 rtx negated_const; 2144#if HOST_BITS_PER_WIDE_INT == 64 2145 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | 2146 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); 2147#else 2148 negated_const = immed_double_const ((~low_bits) & 0xfffffc00, 2149 (~high_bits) & 0xffffffff, 2150 DImode); 2151#endif 2152 sparc_emit_set_const64 (temp, negated_const); 2153 } 2154 2155 /* If we are XOR'ing with -1, then we should emit a one's complement 2156 instead. This way the combiner will notice logical operations 2157 such as ANDN later on and substitute. */ 2158 if (trailing_bits == 0x3ff) 2159 { 2160 emit_insn (gen_rtx_SET (VOIDmode, op0, 2161 gen_rtx_NOT (DImode, temp))); 2162 } 2163 else 2164 { 2165 emit_insn (gen_rtx_SET (VOIDmode, 2166 op0, 2167 gen_safe_XOR64 (temp, 2168 (-0x400 | trailing_bits)))); 2169 } 2170 return; 2171 } 2172 2173 /* 1) sethi %hi(xxx), %reg 2174 * or %reg, %lo(xxx), %reg 2175 * sllx %reg, yyy, %reg 2176 * 2177 * ??? This is just a generalized version of the low_bits==0 2178 * thing above, FIXME... 2179 */ 2180 if ((highest_bit_set - lowest_bit_set) < 32) 2181 { 2182 unsigned HOST_WIDE_INT focus_bits = 2183 create_simple_focus_bits (high_bits, low_bits, 2184 lowest_bit_set, 0); 2185 2186 /* We can't get here in this state. */ 2187 if (highest_bit_set < 32 2188 || lowest_bit_set >= 32) 2189 abort (); 2190 2191 /* So what we know is that the set bits straddle the 2192 middle of the 64-bit word. */ 2193 sparc_emit_set_const64_quick2 (op0, temp, 2194 focus_bits, 0, 2195 lowest_bit_set); 2196 return; 2197 } 2198 2199 /* 1) sethi %hi(high_bits), %reg 2200 * or %reg, %lo(high_bits), %reg 2201 * sllx %reg, 32, %reg 2202 * or %reg, low_bits, %reg 2203 */ 2204 if (SPARC_SIMM13_P(low_bits) 2205 && ((int)low_bits > 0)) 2206 { 2207 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); 2208 return; 2209 } 2210 2211 /* The easiest way when all else fails, is full decomposition. */ 2212#if 0 2213 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", 2214 high_bits, low_bits, ~high_bits, ~low_bits); 2215#endif 2216 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); 2217} 2218 2219/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2220 return the mode to be used for the comparison. For floating-point, 2221 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 2222 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 2223 processing is needed. */ 2224 2225enum machine_mode 2226select_cc_mode (op, x, y) 2227 enum rtx_code op; 2228 rtx x; 2229 rtx y ATTRIBUTE_UNUSED; 2230{ 2231 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2232 { 2233 switch (op) 2234 { 2235 case EQ: 2236 case NE: 2237 case UNORDERED: 2238 case ORDERED: 2239 case UNLT: 2240 case UNLE: 2241 case UNGT: 2242 case UNGE: 2243 case UNEQ: 2244 case LTGT: 2245 return CCFPmode; 2246 2247 case LT: 2248 case LE: 2249 case GT: 2250 case GE: 2251 return CCFPEmode; 2252 2253 default: 2254 abort (); 2255 } 2256 } 2257 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS 2258 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) 2259 { 2260 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 2261 return CCX_NOOVmode; 2262 else 2263 return CC_NOOVmode; 2264 } 2265 else 2266 { 2267 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 2268 return CCXmode; 2269 else 2270 return CCmode; 2271 } 2272} 2273 2274/* X and Y are two things to compare using CODE. Emit the compare insn and 2275 return the rtx for the cc reg in the proper mode. */ 2276 2277rtx 2278gen_compare_reg (code, x, y) 2279 enum rtx_code code; 2280 rtx x, y; 2281{ 2282 enum machine_mode mode = SELECT_CC_MODE (code, x, y); 2283 rtx cc_reg; 2284 2285 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the 2286 fcc regs (cse can't tell they're really call clobbered regs and will 2287 remove a duplicate comparison even if there is an intervening function 2288 call - it will then try to reload the cc reg via an int reg which is why 2289 we need the movcc patterns). It is possible to provide the movcc 2290 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two 2291 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be 2292 to tell cse that CCFPE mode registers (even pseudos) are call 2293 clobbered. */ 2294 2295 /* ??? This is an experiment. Rather than making changes to cse which may 2296 or may not be easy/clean, we do our own cse. This is possible because 2297 we will generate hard registers. Cse knows they're call clobbered (it 2298 doesn't know the same thing about pseudos). If we guess wrong, no big 2299 deal, but if we win, great! */ 2300 2301 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2302#if 1 /* experiment */ 2303 { 2304 int reg; 2305 /* We cycle through the registers to ensure they're all exercised. */ 2306 static int next_fcc_reg = 0; 2307 /* Previous x,y for each fcc reg. */ 2308 static rtx prev_args[4][2]; 2309 2310 /* Scan prev_args for x,y. */ 2311 for (reg = 0; reg < 4; reg++) 2312 if (prev_args[reg][0] == x && prev_args[reg][1] == y) 2313 break; 2314 if (reg == 4) 2315 { 2316 reg = next_fcc_reg; 2317 prev_args[reg][0] = x; 2318 prev_args[reg][1] = y; 2319 next_fcc_reg = (next_fcc_reg + 1) & 3; 2320 } 2321 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); 2322 } 2323#else 2324 cc_reg = gen_reg_rtx (mode); 2325#endif /* ! experiment */ 2326 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2327 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); 2328 else 2329 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); 2330 2331 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, 2332 gen_rtx_COMPARE (mode, x, y))); 2333 2334 return cc_reg; 2335} 2336 2337/* This function is used for v9 only. 2338 CODE is the code for an Scc's comparison. 2339 OPERANDS[0] is the target of the Scc insn. 2340 OPERANDS[1] is the value we compare against const0_rtx (which hasn't 2341 been generated yet). 2342 2343 This function is needed to turn 2344 2345 (set (reg:SI 110) 2346 (gt (reg:CCX 100 %icc) 2347 (const_int 0))) 2348 into 2349 (set (reg:SI 110) 2350 (gt:DI (reg:CCX 100 %icc) 2351 (const_int 0))) 2352 2353 IE: The instruction recognizer needs to see the mode of the comparison to 2354 find the right instruction. We could use "gt:DI" right in the 2355 define_expand, but leaving it out allows us to handle DI, SI, etc. 2356 2357 We refer to the global sparc compare operands sparc_compare_op0 and 2358 sparc_compare_op1. */ 2359 2360int 2361gen_v9_scc (compare_code, operands) 2362 enum rtx_code compare_code; 2363 register rtx *operands; 2364{ 2365 rtx temp, op0, op1; 2366 2367 if (! TARGET_ARCH64 2368 && (GET_MODE (sparc_compare_op0) == DImode 2369 || GET_MODE (operands[0]) == DImode)) 2370 return 0; 2371 2372 op0 = sparc_compare_op0; 2373 op1 = sparc_compare_op1; 2374 2375 /* Try to use the movrCC insns. */ 2376 if (TARGET_ARCH64 2377 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 2378 && op1 == const0_rtx 2379 && v9_regcmp_p (compare_code)) 2380 { 2381 /* Special case for op0 != 0. This can be done with one instruction if 2382 operands[0] == sparc_compare_op0. */ 2383 2384 if (compare_code == NE 2385 && GET_MODE (operands[0]) == DImode 2386 && rtx_equal_p (op0, operands[0])) 2387 { 2388 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2389 gen_rtx_IF_THEN_ELSE (DImode, 2390 gen_rtx_fmt_ee (compare_code, DImode, 2391 op0, const0_rtx), 2392 const1_rtx, 2393 operands[0]))); 2394 return 1; 2395 } 2396 2397 if (reg_overlap_mentioned_p (operands[0], op0)) 2398 { 2399 /* Handle the case where operands[0] == sparc_compare_op0. 2400 We "early clobber" the result. */ 2401 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); 2402 emit_move_insn (op0, sparc_compare_op0); 2403 } 2404 2405 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); 2406 if (GET_MODE (op0) != DImode) 2407 { 2408 temp = gen_reg_rtx (DImode); 2409 convert_move (temp, op0, 0); 2410 } 2411 else 2412 temp = op0; 2413 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2414 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 2415 gen_rtx_fmt_ee (compare_code, DImode, 2416 temp, const0_rtx), 2417 const1_rtx, 2418 operands[0]))); 2419 return 1; 2420 } 2421 else 2422 { 2423 operands[1] = gen_compare_reg (compare_code, op0, op1); 2424 2425 switch (GET_MODE (operands[1])) 2426 { 2427 case CCmode : 2428 case CCXmode : 2429 case CCFPEmode : 2430 case CCFPmode : 2431 break; 2432 default : 2433 abort (); 2434 } 2435 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); 2436 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2437 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 2438 gen_rtx_fmt_ee (compare_code, 2439 GET_MODE (operands[1]), 2440 operands[1], const0_rtx), 2441 const1_rtx, operands[0]))); 2442 return 1; 2443 } 2444} 2445 2446/* Emit a conditional jump insn for the v9 architecture using comparison code 2447 CODE and jump target LABEL. 2448 This function exists to take advantage of the v9 brxx insns. */ 2449 2450void 2451emit_v9_brxx_insn (code, op0, label) 2452 enum rtx_code code; 2453 rtx op0, label; 2454{ 2455 emit_jump_insn (gen_rtx_SET (VOIDmode, 2456 pc_rtx, 2457 gen_rtx_IF_THEN_ELSE (VOIDmode, 2458 gen_rtx_fmt_ee (code, GET_MODE (op0), 2459 op0, const0_rtx), 2460 gen_rtx_LABEL_REF (VOIDmode, label), 2461 pc_rtx))); 2462} 2463 2464/* Generate a DFmode part of a hard TFmode register. 2465 REG is the TFmode hard register, LOW is 1 for the 2466 low 64bit of the register and 0 otherwise. 2467 */ 2468rtx 2469gen_df_reg (reg, low) 2470 rtx reg; 2471 int low; 2472{ 2473 int regno = REGNO (reg); 2474 2475 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) 2476 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; 2477 return gen_rtx_REG (DFmode, regno); 2478} 2479 2480/* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. 2481 Unlike normal calls, TFmode operands are passed by reference. It is 2482 assumed that no more than 3 operands are required. */ 2483 2484static void 2485emit_soft_tfmode_libcall (func_name, nargs, operands) 2486 const char *func_name; 2487 int nargs; 2488 rtx *operands; 2489{ 2490 rtx ret_slot = NULL, arg[3], func_sym; 2491 int i; 2492 2493 /* We only expect to be called for conversions, unary, and binary ops. */ 2494 if (nargs < 2 || nargs > 3) 2495 abort (); 2496 2497 for (i = 0; i < nargs; ++i) 2498 { 2499 rtx this_arg = operands[i]; 2500 rtx this_slot; 2501 2502 /* TFmode arguments and return values are passed by reference. */ 2503 if (GET_MODE (this_arg) == TFmode) 2504 { 2505 int force_stack_temp; 2506 2507 force_stack_temp = 0; 2508 if (TARGET_BUGGY_QP_LIB && i == 0) 2509 force_stack_temp = 1; 2510 2511 if (GET_CODE (this_arg) == MEM 2512 && ! force_stack_temp) 2513 this_arg = XEXP (this_arg, 0); 2514 else if (CONSTANT_P (this_arg) 2515 && ! force_stack_temp) 2516 { 2517 this_slot = force_const_mem (TFmode, this_arg); 2518 this_arg = XEXP (this_slot, 0); 2519 } 2520 else 2521 { 2522 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0); 2523 2524 /* Operand 0 is the return value. We'll copy it out later. */ 2525 if (i > 0) 2526 emit_move_insn (this_slot, this_arg); 2527 else 2528 ret_slot = this_slot; 2529 2530 this_arg = XEXP (this_slot, 0); 2531 } 2532 } 2533 2534 arg[i] = this_arg; 2535 } 2536 2537 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); 2538 2539 if (GET_MODE (operands[0]) == TFmode) 2540 { 2541 if (nargs == 2) 2542 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2, 2543 arg[0], GET_MODE (arg[0]), 2544 arg[1], GET_MODE (arg[1])); 2545 else 2546 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3, 2547 arg[0], GET_MODE (arg[0]), 2548 arg[1], GET_MODE (arg[1]), 2549 arg[2], GET_MODE (arg[2])); 2550 2551 if (ret_slot) 2552 emit_move_insn (operands[0], ret_slot); 2553 } 2554 else 2555 { 2556 rtx ret; 2557 2558 if (nargs != 2) 2559 abort (); 2560 2561 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, 2562 GET_MODE (operands[0]), 1, 2563 arg[1], GET_MODE (arg[1])); 2564 2565 if (ret != operands[0]) 2566 emit_move_insn (operands[0], ret); 2567 } 2568} 2569 2570/* Expand soft-float TFmode calls to sparc abi routines. */ 2571 2572static void 2573emit_soft_tfmode_binop (code, operands) 2574 enum rtx_code code; 2575 rtx *operands; 2576{ 2577 const char *func; 2578 2579 switch (code) 2580 { 2581 case PLUS: 2582 func = "_Qp_add"; 2583 break; 2584 case MINUS: 2585 func = "_Qp_sub"; 2586 break; 2587 case MULT: 2588 func = "_Qp_mul"; 2589 break; 2590 case DIV: 2591 func = "_Qp_div"; 2592 break; 2593 default: 2594 abort (); 2595 } 2596 2597 emit_soft_tfmode_libcall (func, 3, operands); 2598} 2599 2600static void 2601emit_soft_tfmode_unop (code, operands) 2602 enum rtx_code code; 2603 rtx *operands; 2604{ 2605 const char *func; 2606 2607 switch (code) 2608 { 2609 case SQRT: 2610 func = "_Qp_sqrt"; 2611 break; 2612 default: 2613 abort (); 2614 } 2615 2616 emit_soft_tfmode_libcall (func, 2, operands); 2617} 2618 2619static void 2620emit_soft_tfmode_cvt (code, operands) 2621 enum rtx_code code; 2622 rtx *operands; 2623{ 2624 const char *func; 2625 2626 switch (code) 2627 { 2628 case FLOAT_EXTEND: 2629 switch (GET_MODE (operands[1])) 2630 { 2631 case SFmode: 2632 func = "_Qp_stoq"; 2633 break; 2634 case DFmode: 2635 func = "_Qp_dtoq"; 2636 break; 2637 default: 2638 abort (); 2639 } 2640 break; 2641 2642 case FLOAT_TRUNCATE: 2643 switch (GET_MODE (operands[0])) 2644 { 2645 case SFmode: 2646 func = "_Qp_qtos"; 2647 break; 2648 case DFmode: 2649 func = "_Qp_qtod"; 2650 break; 2651 default: 2652 abort (); 2653 } 2654 break; 2655 2656 case FLOAT: 2657 switch (GET_MODE (operands[1])) 2658 { 2659 case SImode: 2660 func = "_Qp_itoq"; 2661 break; 2662 case DImode: 2663 func = "_Qp_xtoq"; 2664 break; 2665 default: 2666 abort (); 2667 } 2668 break; 2669 2670 case UNSIGNED_FLOAT: 2671 switch (GET_MODE (operands[1])) 2672 { 2673 case SImode: 2674 func = "_Qp_uitoq"; 2675 break; 2676 case DImode: 2677 func = "_Qp_uxtoq"; 2678 break; 2679 default: 2680 abort (); 2681 } 2682 break; 2683 2684 case FIX: 2685 switch (GET_MODE (operands[0])) 2686 { 2687 case SImode: 2688 func = "_Qp_qtoi"; 2689 break; 2690 case DImode: 2691 func = "_Qp_qtox"; 2692 break; 2693 default: 2694 abort (); 2695 } 2696 break; 2697 2698 case UNSIGNED_FIX: 2699 switch (GET_MODE (operands[0])) 2700 { 2701 case SImode: 2702 func = "_Qp_qtoui"; 2703 break; 2704 case DImode: 2705 func = "_Qp_qtoux"; 2706 break; 2707 default: 2708 abort (); 2709 } 2710 break; 2711 2712 default: 2713 abort (); 2714 } 2715 2716 emit_soft_tfmode_libcall (func, 2, operands); 2717} 2718 2719/* Expand a hard-float tfmode operation. All arguments must be in 2720 registers. */ 2721 2722static void 2723emit_hard_tfmode_operation (code, operands) 2724 enum rtx_code code; 2725 rtx *operands; 2726{ 2727 rtx op, dest; 2728 2729 if (GET_RTX_CLASS (code) == '1') 2730 { 2731 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 2732 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); 2733 } 2734 else 2735 { 2736 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 2737 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); 2738 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), 2739 operands[1], operands[2]); 2740 } 2741 2742 if (register_operand (operands[0], VOIDmode)) 2743 dest = operands[0]; 2744 else 2745 dest = gen_reg_rtx (GET_MODE (operands[0])); 2746 2747 emit_insn (gen_rtx_SET (VOIDmode, dest, op)); 2748 2749 if (dest != operands[0]) 2750 emit_move_insn (operands[0], dest); 2751} 2752 2753void 2754emit_tfmode_binop (code, operands) 2755 enum rtx_code code; 2756 rtx *operands; 2757{ 2758 if (TARGET_HARD_QUAD) 2759 emit_hard_tfmode_operation (code, operands); 2760 else 2761 emit_soft_tfmode_binop (code, operands); 2762} 2763 2764void 2765emit_tfmode_unop (code, operands) 2766 enum rtx_code code; 2767 rtx *operands; 2768{ 2769 if (TARGET_HARD_QUAD) 2770 emit_hard_tfmode_operation (code, operands); 2771 else 2772 emit_soft_tfmode_unop (code, operands); 2773} 2774 2775void 2776emit_tfmode_cvt (code, operands) 2777 enum rtx_code code; 2778 rtx *operands; 2779{ 2780 if (TARGET_HARD_QUAD) 2781 emit_hard_tfmode_operation (code, operands); 2782 else 2783 emit_soft_tfmode_cvt (code, operands); 2784} 2785 2786/* Return nonzero if a return peephole merging return with 2787 setting of output register is ok. */ 2788int 2789leaf_return_peephole_ok () 2790{ 2791 return (actual_fsize == 0); 2792} 2793 2794/* Return nonzero if a branch/jump/call instruction will be emitting 2795 nop into its delay slot. */ 2796 2797int 2798empty_delay_slot (insn) 2799 rtx insn; 2800{ 2801 rtx seq; 2802 2803 /* If no previous instruction (should not happen), return true. */ 2804 if (PREV_INSN (insn) == NULL) 2805 return 1; 2806 2807 seq = NEXT_INSN (PREV_INSN (insn)); 2808 if (GET_CODE (PATTERN (seq)) == SEQUENCE) 2809 return 0; 2810 2811 return 1; 2812} 2813 2814/* Return nonzero if TRIAL can go into the function epilogue's 2815 delay slot. SLOT is the slot we are trying to fill. */ 2816 2817int 2818eligible_for_epilogue_delay (trial, slot) 2819 rtx trial; 2820 int slot; 2821{ 2822 rtx pat, src; 2823 2824 if (slot >= 1) 2825 return 0; 2826 2827 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) 2828 return 0; 2829 2830 if (get_attr_length (trial) != 1) 2831 return 0; 2832 2833 /* If there are any call-saved registers, we should scan TRIAL if it 2834 does not reference them. For now just make it easy. */ 2835 if (num_gfregs) 2836 return 0; 2837 2838 /* If the function uses __builtin_eh_return, the eh_return machinery 2839 occupies the delay slot. */ 2840 if (current_function_calls_eh_return) 2841 return 0; 2842 2843 /* In the case of a true leaf function, anything can go into the delay slot. 2844 A delay slot only exists however if the frame size is zero, otherwise 2845 we will put an insn to adjust the stack after the return. */ 2846 if (current_function_uses_only_leaf_regs) 2847 { 2848 if (leaf_return_peephole_ok ()) 2849 return ((get_attr_in_uncond_branch_delay (trial) 2850 == IN_BRANCH_DELAY_TRUE)); 2851 return 0; 2852 } 2853 2854 pat = PATTERN (trial); 2855 2856 /* Otherwise, only operations which can be done in tandem with 2857 a `restore' or `return' insn can go into the delay slot. */ 2858 if (GET_CODE (SET_DEST (pat)) != REG 2859 || REGNO (SET_DEST (pat)) < 24) 2860 return 0; 2861 2862 /* If this instruction sets up floating point register and we have a return 2863 instruction, it can probably go in. But restore will not work 2864 with FP_REGS. */ 2865 if (REGNO (SET_DEST (pat)) >= 32) 2866 { 2867 if (TARGET_V9 && ! epilogue_renumber (&pat, 1) 2868 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) 2869 return 1; 2870 return 0; 2871 } 2872 2873 /* The set of insns matched here must agree precisely with the set of 2874 patterns paired with a RETURN in sparc.md. */ 2875 2876 src = SET_SRC (pat); 2877 2878 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ 2879 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2880 && arith_operand (src, GET_MODE (src))) 2881 { 2882 if (TARGET_ARCH64) 2883 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2884 else 2885 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); 2886 } 2887 2888 /* This matches "*return_di". */ 2889 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2890 && arith_double_operand (src, GET_MODE (src))) 2891 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2892 2893 /* This matches "*return_sf_no_fpu". */ 2894 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) 2895 && register_operand (src, SFmode)) 2896 return 1; 2897 2898 /* If we have return instruction, anything that does not use 2899 local or output registers and can go into a delay slot wins. */ 2900 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1) 2901 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) 2902 return 1; 2903 2904 /* This matches "*return_addsi". */ 2905 else if (GET_CODE (src) == PLUS 2906 && arith_operand (XEXP (src, 0), SImode) 2907 && arith_operand (XEXP (src, 1), SImode) 2908 && (register_operand (XEXP (src, 0), SImode) 2909 || register_operand (XEXP (src, 1), SImode))) 2910 return 1; 2911 2912 /* This matches "*return_adddi". */ 2913 else if (GET_CODE (src) == PLUS 2914 && arith_double_operand (XEXP (src, 0), DImode) 2915 && arith_double_operand (XEXP (src, 1), DImode) 2916 && (register_operand (XEXP (src, 0), DImode) 2917 || register_operand (XEXP (src, 1), DImode))) 2918 return 1; 2919 2920 /* This can match "*return_losum_[sd]i". 2921 Catch only some cases, so that return_losum* don't have 2922 to be too big. */ 2923 else if (GET_CODE (src) == LO_SUM 2924 && ! TARGET_CM_MEDMID 2925 && ((register_operand (XEXP (src, 0), SImode) 2926 && immediate_operand (XEXP (src, 1), SImode)) 2927 || (TARGET_ARCH64 2928 && register_operand (XEXP (src, 0), DImode) 2929 && immediate_operand (XEXP (src, 1), DImode)))) 2930 return 1; 2931 2932 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */ 2933 else if (GET_CODE (src) == ASHIFT 2934 && (register_operand (XEXP (src, 0), SImode) 2935 || register_operand (XEXP (src, 0), DImode)) 2936 && XEXP (src, 1) == const1_rtx) 2937 return 1; 2938 2939 return 0; 2940} 2941 2942/* Return nonzero if TRIAL can go into the sibling call 2943 delay slot. */ 2944 2945int 2946eligible_for_sibcall_delay (trial) 2947 rtx trial; 2948{ 2949 rtx pat, src; 2950 2951 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) 2952 return 0; 2953 2954 if (get_attr_length (trial) != 1) 2955 return 0; 2956 2957 pat = PATTERN (trial); 2958 2959 if (current_function_uses_only_leaf_regs) 2960 { 2961 /* If the tail call is done using the call instruction, 2962 we have to restore %o7 in the delay slot. */ 2963 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic) 2964 return 0; 2965 2966 /* %g1 is used to build the function address */ 2967 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) 2968 return 0; 2969 2970 return 1; 2971 } 2972 2973 /* Otherwise, only operations which can be done in tandem with 2974 a `restore' insn can go into the delay slot. */ 2975 if (GET_CODE (SET_DEST (pat)) != REG 2976 || REGNO (SET_DEST (pat)) < 24 2977 || REGNO (SET_DEST (pat)) >= 32) 2978 return 0; 2979 2980 /* If it mentions %o7, it can't go in, because sibcall will clobber it 2981 in most cases. */ 2982 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) 2983 return 0; 2984 2985 src = SET_SRC (pat); 2986 2987 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2988 && arith_operand (src, GET_MODE (src))) 2989 { 2990 if (TARGET_ARCH64) 2991 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2992 else 2993 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); 2994 } 2995 2996 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2997 && arith_double_operand (src, GET_MODE (src))) 2998 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2999 3000 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) 3001 && register_operand (src, SFmode)) 3002 return 1; 3003 3004 else if (GET_CODE (src) == PLUS 3005 && arith_operand (XEXP (src, 0), SImode) 3006 && arith_operand (XEXP (src, 1), SImode) 3007 && (register_operand (XEXP (src, 0), SImode) 3008 || register_operand (XEXP (src, 1), SImode))) 3009 return 1; 3010 3011 else if (GET_CODE (src) == PLUS 3012 && arith_double_operand (XEXP (src, 0), DImode) 3013 && arith_double_operand (XEXP (src, 1), DImode) 3014 && (register_operand (XEXP (src, 0), DImode) 3015 || register_operand (XEXP (src, 1), DImode))) 3016 return 1; 3017 3018 else if (GET_CODE (src) == LO_SUM 3019 && ! TARGET_CM_MEDMID 3020 && ((register_operand (XEXP (src, 0), SImode) 3021 && immediate_operand (XEXP (src, 1), SImode)) 3022 || (TARGET_ARCH64 3023 && register_operand (XEXP (src, 0), DImode) 3024 && immediate_operand (XEXP (src, 1), DImode)))) 3025 return 1; 3026 3027 else if (GET_CODE (src) == ASHIFT 3028 && (register_operand (XEXP (src, 0), SImode) 3029 || register_operand (XEXP (src, 0), DImode)) 3030 && XEXP (src, 1) == const1_rtx) 3031 return 1; 3032 3033 return 0; 3034} 3035 3036static int 3037check_return_regs (x) 3038 rtx x; 3039{ 3040 switch (GET_CODE (x)) 3041 { 3042 case REG: 3043 return IN_OR_GLOBAL_P (x); 3044 3045 case CONST_INT: 3046 case CONST_DOUBLE: 3047 case CONST: 3048 case SYMBOL_REF: 3049 case LABEL_REF: 3050 return 1; 3051 3052 case SET: 3053 case IOR: 3054 case AND: 3055 case XOR: 3056 case PLUS: 3057 case MINUS: 3058 if (check_return_regs (XEXP (x, 1)) == 0) 3059 return 0; 3060 case NOT: 3061 case NEG: 3062 case MEM: 3063 return check_return_regs (XEXP (x, 0)); 3064 3065 default: 3066 return 0; 3067 } 3068 3069} 3070 3071int 3072short_branch (uid1, uid2) 3073 int uid1, uid2; 3074{ 3075 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2); 3076 3077 /* Leave a few words of "slop". */ 3078 if (delta >= -1023 && delta <= 1022) 3079 return 1; 3080 3081 return 0; 3082} 3083 3084/* Return nonzero if REG is not used after INSN. 3085 We assume REG is a reload reg, and therefore does 3086 not live past labels or calls or jumps. */ 3087int 3088reg_unused_after (reg, insn) 3089 rtx reg; 3090 rtx insn; 3091{ 3092 enum rtx_code code, prev_code = UNKNOWN; 3093 3094 while ((insn = NEXT_INSN (insn))) 3095 { 3096 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) 3097 return 1; 3098 3099 code = GET_CODE (insn); 3100 if (GET_CODE (insn) == CODE_LABEL) 3101 return 1; 3102 3103 if (GET_RTX_CLASS (code) == 'i') 3104 { 3105 rtx set = single_set (insn); 3106 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); 3107 if (set && in_src) 3108 return 0; 3109 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) 3110 return 1; 3111 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) 3112 return 0; 3113 } 3114 prev_code = code; 3115 } 3116 return 1; 3117} 3118 3119/* The table we use to reference PIC data. */ 3120static GTY(()) rtx global_offset_table; 3121 3122/* The function we use to get at it. */ 3123static GTY(()) rtx get_pc_symbol; 3124static char get_pc_symbol_name[256]; 3125 3126/* Ensure that we are not using patterns that are not OK with PIC. */ 3127 3128int 3129check_pic (i) 3130 int i; 3131{ 3132 switch (flag_pic) 3133 { 3134 case 1: 3135 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF 3136 || (GET_CODE (recog_data.operand[i]) == CONST 3137 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS 3138 && (XEXP (XEXP (recog_data.operand[i], 0), 0) 3139 == global_offset_table) 3140 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) 3141 == CONST)))) 3142 abort (); 3143 case 2: 3144 default: 3145 return 1; 3146 } 3147} 3148 3149/* Return true if X is an address which needs a temporary register when 3150 reloaded while generating PIC code. */ 3151 3152int 3153pic_address_needs_scratch (x) 3154 rtx x; 3155{ 3156 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ 3157 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS 3158 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 3159 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3160 && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) 3161 return 1; 3162 3163 return 0; 3164} 3165 3166/* Legitimize PIC addresses. If the address is already position-independent, 3167 we return ORIG. Newly generated position-independent addresses go into a 3168 reg. This is REG if nonzero, otherwise we allocate register(s) as 3169 necessary. */ 3170 3171rtx 3172legitimize_pic_address (orig, mode, reg) 3173 rtx orig; 3174 enum machine_mode mode ATTRIBUTE_UNUSED; 3175 rtx reg; 3176{ 3177 if (GET_CODE (orig) == SYMBOL_REF) 3178 { 3179 rtx pic_ref, address; 3180 rtx insn; 3181 3182 if (reg == 0) 3183 { 3184 if (reload_in_progress || reload_completed) 3185 abort (); 3186 else 3187 reg = gen_reg_rtx (Pmode); 3188 } 3189 3190 if (flag_pic == 2) 3191 { 3192 /* If not during reload, allocate another temp reg here for loading 3193 in the address, so that these instructions can be optimized 3194 properly. */ 3195 rtx temp_reg = ((reload_in_progress || reload_completed) 3196 ? reg : gen_reg_rtx (Pmode)); 3197 3198 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse 3199 won't get confused into thinking that these two instructions 3200 are loading in the true address of the symbol. If in the 3201 future a PIC rtx exists, that should be used instead. */ 3202 if (Pmode == SImode) 3203 { 3204 emit_insn (gen_movsi_high_pic (temp_reg, orig)); 3205 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); 3206 } 3207 else 3208 { 3209 emit_insn (gen_movdi_high_pic (temp_reg, orig)); 3210 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); 3211 } 3212 address = temp_reg; 3213 } 3214 else 3215 address = orig; 3216 3217 pic_ref = gen_rtx_MEM (Pmode, 3218 gen_rtx_PLUS (Pmode, 3219 pic_offset_table_rtx, address)); 3220 current_function_uses_pic_offset_table = 1; 3221 RTX_UNCHANGING_P (pic_ref) = 1; 3222 insn = emit_move_insn (reg, pic_ref); 3223 /* Put a REG_EQUAL note on this insn, so that it can be optimized 3224 by loop. */ 3225 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, 3226 REG_NOTES (insn)); 3227 return reg; 3228 } 3229 else if (GET_CODE (orig) == CONST) 3230 { 3231 rtx base, offset; 3232 3233 if (GET_CODE (XEXP (orig, 0)) == PLUS 3234 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) 3235 return orig; 3236 3237 if (reg == 0) 3238 { 3239 if (reload_in_progress || reload_completed) 3240 abort (); 3241 else 3242 reg = gen_reg_rtx (Pmode); 3243 } 3244 3245 if (GET_CODE (XEXP (orig, 0)) == PLUS) 3246 { 3247 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); 3248 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, 3249 base == reg ? 0 : reg); 3250 } 3251 else 3252 abort (); 3253 3254 if (GET_CODE (offset) == CONST_INT) 3255 { 3256 if (SMALL_INT (offset)) 3257 return plus_constant (base, INTVAL (offset)); 3258 else if (! reload_in_progress && ! reload_completed) 3259 offset = force_reg (Pmode, offset); 3260 else 3261 /* If we reach here, then something is seriously wrong. */ 3262 abort (); 3263 } 3264 return gen_rtx_PLUS (Pmode, base, offset); 3265 } 3266 else if (GET_CODE (orig) == LABEL_REF) 3267 /* ??? Why do we do this? */ 3268 /* Now movsi_pic_label_ref uses it, but we ought to be checking that 3269 the register is live instead, in case it is eliminated. */ 3270 current_function_uses_pic_offset_table = 1; 3271 3272 return orig; 3273} 3274 3275/* Emit special PIC prologues. */ 3276 3277void 3278load_pic_register () 3279{ 3280 /* Labels to get the PC in the prologue of this function. */ 3281 int orig_flag_pic = flag_pic; 3282 3283 if (! flag_pic) 3284 abort (); 3285 3286 /* If we haven't emitted the special get_pc helper function, do so now. */ 3287 if (get_pc_symbol_name[0] == 0) 3288 { 3289 int align; 3290 3291 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); 3292 text_section (); 3293 3294 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 3295 if (align > 0) 3296 ASM_OUTPUT_ALIGN (asm_out_file, align); 3297 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0); 3298 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file); 3299 } 3300 3301 /* Initialize every time through, since we can't easily 3302 know this to be permanent. */ 3303 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 3304 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); 3305 flag_pic = 0; 3306 3307 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, 3308 get_pc_symbol)); 3309 3310 flag_pic = orig_flag_pic; 3311 3312 /* Need to emit this whether or not we obey regdecls, 3313 since setjmp/longjmp can cause life info to screw up. 3314 ??? In the case where we don't obey regdecls, this is not sufficient 3315 since we may not fall out the bottom. */ 3316 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); 3317} 3318 3319/* Return 1 if RTX is a MEM which is known to be aligned to at 3320 least a DESIRED byte boundary. */ 3321 3322int 3323mem_min_alignment (mem, desired) 3324 rtx mem; 3325 int desired; 3326{ 3327 rtx addr, base, offset; 3328 3329 /* If it's not a MEM we can't accept it. */ 3330 if (GET_CODE (mem) != MEM) 3331 return 0; 3332 3333 addr = XEXP (mem, 0); 3334 base = offset = NULL_RTX; 3335 if (GET_CODE (addr) == PLUS) 3336 { 3337 if (GET_CODE (XEXP (addr, 0)) == REG) 3338 { 3339 base = XEXP (addr, 0); 3340 3341 /* What we are saying here is that if the base 3342 REG is aligned properly, the compiler will make 3343 sure any REG based index upon it will be so 3344 as well. */ 3345 if (GET_CODE (XEXP (addr, 1)) == CONST_INT) 3346 offset = XEXP (addr, 1); 3347 else 3348 offset = const0_rtx; 3349 } 3350 } 3351 else if (GET_CODE (addr) == REG) 3352 { 3353 base = addr; 3354 offset = const0_rtx; 3355 } 3356 3357 if (base != NULL_RTX) 3358 { 3359 int regno = REGNO (base); 3360 3361 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) 3362 { 3363 /* Check if the compiler has recorded some information 3364 about the alignment of the base REG. If reload has 3365 completed, we already matched with proper alignments. 3366 If not running global_alloc, reload might give us 3367 unaligned pointer to local stack though. */ 3368 if (((cfun != 0 3369 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) 3370 || (optimize && reload_completed)) 3371 && (INTVAL (offset) & (desired - 1)) == 0) 3372 return 1; 3373 } 3374 else 3375 { 3376 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) 3377 return 1; 3378 } 3379 } 3380 else if (! TARGET_UNALIGNED_DOUBLES 3381 || CONSTANT_P (addr) 3382 || GET_CODE (addr) == LO_SUM) 3383 { 3384 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES 3385 is true, in which case we can only assume that an access is aligned if 3386 it is to a constant address, or the address involves a LO_SUM. */ 3387 return 1; 3388 } 3389 3390 /* An obviously unaligned address. */ 3391 return 0; 3392} 3393 3394 3395/* Vectors to keep interesting information about registers where it can easily 3396 be got. We used to use the actual mode value as the bit number, but there 3397 are more than 32 modes now. Instead we use two tables: one indexed by 3398 hard register number, and one indexed by mode. */ 3399 3400/* The purpose of sparc_mode_class is to shrink the range of modes so that 3401 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is 3402 mapped into one sparc_mode_class mode. */ 3403 3404enum sparc_mode_class { 3405 S_MODE, D_MODE, T_MODE, O_MODE, 3406 SF_MODE, DF_MODE, TF_MODE, OF_MODE, 3407 CC_MODE, CCFP_MODE 3408}; 3409 3410/* Modes for single-word and smaller quantities. */ 3411#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) 3412 3413/* Modes for double-word and smaller quantities. */ 3414#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) 3415 3416/* Modes for quad-word and smaller quantities. */ 3417#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) 3418 3419/* Modes for 8-word and smaller quantities. */ 3420#define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) 3421 3422/* Modes for single-float quantities. We must allow any single word or 3423 smaller quantity. This is because the fix/float conversion instructions 3424 take integer inputs/outputs from the float registers. */ 3425#define SF_MODES (S_MODES) 3426 3427/* Modes for double-float and smaller quantities. */ 3428#define DF_MODES (S_MODES | D_MODES) 3429 3430/* Modes for double-float only quantities. */ 3431#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) 3432 3433/* Modes for quad-float only quantities. */ 3434#define TF_ONLY_MODES (1 << (int) TF_MODE) 3435 3436/* Modes for quad-float and smaller quantities. */ 3437#define TF_MODES (DF_MODES | TF_ONLY_MODES) 3438 3439/* Modes for quad-float and double-float quantities. */ 3440#define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) 3441 3442/* Modes for quad-float pair only quantities. */ 3443#define OF_ONLY_MODES (1 << (int) OF_MODE) 3444 3445/* Modes for quad-float pairs and smaller quantities. */ 3446#define OF_MODES (TF_MODES | OF_ONLY_MODES) 3447 3448#define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) 3449 3450/* Modes for condition codes. */ 3451#define CC_MODES (1 << (int) CC_MODE) 3452#define CCFP_MODES (1 << (int) CCFP_MODE) 3453 3454/* Value is 1 if register/mode pair is acceptable on sparc. 3455 The funny mixture of D and T modes is because integer operations 3456 do not specially operate on tetra quantities, so non-quad-aligned 3457 registers can hold quadword quantities (except %o4 and %i4 because 3458 they cross fixed registers). */ 3459 3460/* This points to either the 32 bit or the 64 bit version. */ 3461const int *hard_regno_mode_classes; 3462 3463static const int hard_32bit_mode_classes[] = { 3464 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 3465 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 3466 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 3467 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 3468 3469 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3470 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3471 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3472 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 3473 3474 /* FP regs f32 to f63. Only the even numbered registers actually exist, 3475 and none can hold SFmode/SImode values. */ 3476 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3477 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3478 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3479 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3480 3481 /* %fcc[0123] */ 3482 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 3483 3484 /* %icc */ 3485 CC_MODES 3486}; 3487 3488static const int hard_64bit_mode_classes[] = { 3489 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3490 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3491 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3492 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3493 3494 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3495 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3496 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3497 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 3498 3499 /* FP regs f32 to f63. Only the even numbered registers actually exist, 3500 and none can hold SFmode/SImode values. */ 3501 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3502 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3503 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3504 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3505 3506 /* %fcc[0123] */ 3507 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 3508 3509 /* %icc */ 3510 CC_MODES 3511}; 3512 3513int sparc_mode_class [NUM_MACHINE_MODES]; 3514 3515enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 3516 3517static void 3518sparc_init_modes () 3519{ 3520 int i; 3521 3522 for (i = 0; i < NUM_MACHINE_MODES; i++) 3523 { 3524 switch (GET_MODE_CLASS (i)) 3525 { 3526 case MODE_INT: 3527 case MODE_PARTIAL_INT: 3528 case MODE_COMPLEX_INT: 3529 if (GET_MODE_SIZE (i) <= 4) 3530 sparc_mode_class[i] = 1 << (int) S_MODE; 3531 else if (GET_MODE_SIZE (i) == 8) 3532 sparc_mode_class[i] = 1 << (int) D_MODE; 3533 else if (GET_MODE_SIZE (i) == 16) 3534 sparc_mode_class[i] = 1 << (int) T_MODE; 3535 else if (GET_MODE_SIZE (i) == 32) 3536 sparc_mode_class[i] = 1 << (int) O_MODE; 3537 else 3538 sparc_mode_class[i] = 0; 3539 break; 3540 case MODE_FLOAT: 3541 case MODE_COMPLEX_FLOAT: 3542 if (GET_MODE_SIZE (i) <= 4) 3543 sparc_mode_class[i] = 1 << (int) SF_MODE; 3544 else if (GET_MODE_SIZE (i) == 8) 3545 sparc_mode_class[i] = 1 << (int) DF_MODE; 3546 else if (GET_MODE_SIZE (i) == 16) 3547 sparc_mode_class[i] = 1 << (int) TF_MODE; 3548 else if (GET_MODE_SIZE (i) == 32) 3549 sparc_mode_class[i] = 1 << (int) OF_MODE; 3550 else 3551 sparc_mode_class[i] = 0; 3552 break; 3553 case MODE_CC: 3554 default: 3555 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so 3556 we must explicitly check for them here. */ 3557 if (i == (int) CCFPmode || i == (int) CCFPEmode) 3558 sparc_mode_class[i] = 1 << (int) CCFP_MODE; 3559 else if (i == (int) CCmode || i == (int) CC_NOOVmode 3560 || i == (int) CCXmode || i == (int) CCX_NOOVmode) 3561 sparc_mode_class[i] = 1 << (int) CC_MODE; 3562 else 3563 sparc_mode_class[i] = 0; 3564 break; 3565 } 3566 } 3567 3568 if (TARGET_ARCH64) 3569 hard_regno_mode_classes = hard_64bit_mode_classes; 3570 else 3571 hard_regno_mode_classes = hard_32bit_mode_classes; 3572 3573 /* Initialize the array used by REGNO_REG_CLASS. */ 3574 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3575 { 3576 if (i < 16 && TARGET_V8PLUS) 3577 sparc_regno_reg_class[i] = I64_REGS; 3578 else if (i < 32 || i == FRAME_POINTER_REGNUM) 3579 sparc_regno_reg_class[i] = GENERAL_REGS; 3580 else if (i < 64) 3581 sparc_regno_reg_class[i] = FP_REGS; 3582 else if (i < 96) 3583 sparc_regno_reg_class[i] = EXTRA_FP_REGS; 3584 else if (i < 100) 3585 sparc_regno_reg_class[i] = FPCC_REGS; 3586 else 3587 sparc_regno_reg_class[i] = NO_REGS; 3588 } 3589} 3590 3591/* Save non call used registers from LOW to HIGH at BASE+OFFSET. 3592 N_REGS is the number of 4-byte regs saved thus far. This applies even to 3593 v9 int regs as it simplifies the code. */ 3594 3595static int 3596save_regs (file, low, high, base, offset, n_regs, real_offset) 3597 FILE *file; 3598 int low, high; 3599 const char *base; 3600 int offset; 3601 int n_regs; 3602 int real_offset; 3603{ 3604 int i; 3605 3606 if (TARGET_ARCH64 && high <= 32) 3607 { 3608 for (i = low; i < high; i++) 3609 { 3610 if (regs_ever_live[i] && ! call_used_regs[i]) 3611 { 3612 fprintf (file, "\tstx\t%s, [%s+%d]\n", 3613 reg_names[i], base, offset + 4 * n_regs); 3614 if (dwarf2out_do_frame ()) 3615 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); 3616 n_regs += 2; 3617 } 3618 } 3619 } 3620 else 3621 { 3622 for (i = low; i < high; i += 2) 3623 { 3624 if (regs_ever_live[i] && ! call_used_regs[i]) 3625 { 3626 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 3627 { 3628 fprintf (file, "\tstd\t%s, [%s+%d]\n", 3629 reg_names[i], base, offset + 4 * n_regs); 3630 if (dwarf2out_do_frame ()) 3631 { 3632 char *l = dwarf2out_cfi_label (); 3633 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); 3634 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); 3635 } 3636 n_regs += 2; 3637 } 3638 else 3639 { 3640 fprintf (file, "\tst\t%s, [%s+%d]\n", 3641 reg_names[i], base, offset + 4 * n_regs); 3642 if (dwarf2out_do_frame ()) 3643 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); 3644 n_regs += 2; 3645 } 3646 } 3647 else 3648 { 3649 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 3650 { 3651 fprintf (file, "\tst\t%s, [%s+%d]\n", 3652 reg_names[i+1], base, offset + 4 * n_regs + 4); 3653 if (dwarf2out_do_frame ()) 3654 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); 3655 n_regs += 2; 3656 } 3657 } 3658 } 3659 } 3660 return n_regs; 3661} 3662 3663/* Restore non call used registers from LOW to HIGH at BASE+OFFSET. 3664 3665 N_REGS is the number of 4-byte regs saved thus far. This applies even to 3666 v9 int regs as it simplifies the code. */ 3667 3668static int 3669restore_regs (file, low, high, base, offset, n_regs) 3670 FILE *file; 3671 int low, high; 3672 const char *base; 3673 int offset; 3674 int n_regs; 3675{ 3676 int i; 3677 3678 if (TARGET_ARCH64 && high <= 32) 3679 { 3680 for (i = low; i < high; i++) 3681 { 3682 if (regs_ever_live[i] && ! call_used_regs[i]) 3683 fprintf (file, "\tldx\t[%s+%d], %s\n", 3684 base, offset + 4 * n_regs, reg_names[i]), 3685 n_regs += 2; 3686 } 3687 } 3688 else 3689 { 3690 for (i = low; i < high; i += 2) 3691 { 3692 if (regs_ever_live[i] && ! call_used_regs[i]) 3693 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 3694 fprintf (file, "\tldd\t[%s+%d], %s\n", 3695 base, offset + 4 * n_regs, reg_names[i]), 3696 n_regs += 2; 3697 else 3698 fprintf (file, "\tld\t[%s+%d], %s\n", 3699 base, offset + 4 * n_regs, reg_names[i]), 3700 n_regs += 2; 3701 else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 3702 fprintf (file, "\tld\t[%s+%d], %s\n", 3703 base, offset + 4 * n_regs + 4, reg_names[i+1]), 3704 n_regs += 2; 3705 } 3706 } 3707 return n_regs; 3708} 3709 3710/* Compute the frame size required by the function. This function is called 3711 during the reload pass and also by output_function_prologue(). */ 3712 3713int 3714compute_frame_size (size, leaf_function) 3715 int size; 3716 int leaf_function; 3717{ 3718 int n_regs = 0, i; 3719 int outgoing_args_size = (current_function_outgoing_args_size 3720 + REG_PARM_STACK_SPACE (current_function_decl)); 3721 3722 /* N_REGS is the number of 4-byte regs saved thus far. This applies 3723 even to v9 int regs to be consistent with save_regs/restore_regs. */ 3724 3725 if (TARGET_ARCH64) 3726 { 3727 for (i = 0; i < 8; i++) 3728 if (regs_ever_live[i] && ! call_used_regs[i]) 3729 n_regs += 2; 3730 } 3731 else 3732 { 3733 for (i = 0; i < 8; i += 2) 3734 if ((regs_ever_live[i] && ! call_used_regs[i]) 3735 || (regs_ever_live[i+1] && ! call_used_regs[i+1])) 3736 n_regs += 2; 3737 } 3738 3739 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) 3740 if ((regs_ever_live[i] && ! call_used_regs[i]) 3741 || (regs_ever_live[i+1] && ! call_used_regs[i+1])) 3742 n_regs += 2; 3743 3744 /* Set up values for use in `function_epilogue'. */ 3745 num_gfregs = n_regs; 3746 3747 if (leaf_function && n_regs == 0 3748 && size == 0 && current_function_outgoing_args_size == 0) 3749 { 3750 actual_fsize = apparent_fsize = 0; 3751 } 3752 else 3753 { 3754 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ 3755 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8; 3756 apparent_fsize += n_regs * 4; 3757 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); 3758 } 3759 3760 /* Make sure nothing can clobber our register windows. 3761 If a SAVE must be done, or there is a stack-local variable, 3762 the register window area must be allocated. 3763 ??? For v8 we apparently need an additional 8 bytes of reserved space. */ 3764 if (leaf_function == 0 || size > 0) 3765 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); 3766 3767 return SPARC_STACK_ALIGN (actual_fsize); 3768} 3769 3770/* Build a (32 bit) big number in a register. */ 3771/* ??? We may be able to use the set macro here too. */ 3772 3773static void 3774build_big_number (file, num, reg) 3775 FILE *file; 3776 int num; 3777 const char *reg; 3778{ 3779 if (num >= 0 || ! TARGET_ARCH64) 3780 { 3781 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg); 3782 if ((num & 0x3ff) != 0) 3783 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg); 3784 } 3785 else /* num < 0 && TARGET_ARCH64 */ 3786 { 3787 /* Sethi does not sign extend, so we must use a little trickery 3788 to use it for negative numbers. Invert the constant before 3789 loading it in, then use xor immediate to invert the loaded bits 3790 (along with the upper 32 bits) to the desired constant. This 3791 works because the sethi and immediate fields overlap. */ 3792 int asize = num; 3793 int inv = ~asize; 3794 int low = -0x400 + (asize & 0x3FF); 3795 3796 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n", 3797 inv, reg, reg, low, reg); 3798 } 3799} 3800 3801/* Output any necessary .register pseudo-ops. */ 3802void 3803sparc_output_scratch_registers (file) 3804 FILE *file ATTRIBUTE_UNUSED; 3805{ 3806#ifdef HAVE_AS_REGISTER_PSEUDO_OP 3807 int i; 3808 3809 if (TARGET_ARCH32) 3810 return; 3811 3812 /* Check if %g[2367] were used without 3813 .register being printed for them already. */ 3814 for (i = 2; i < 8; i++) 3815 { 3816 if (regs_ever_live [i] 3817 && ! sparc_hard_reg_printed [i]) 3818 { 3819 sparc_hard_reg_printed [i] = 1; 3820 fprintf (file, "\t.register\t%%g%d, #scratch\n", i); 3821 } 3822 if (i == 3) i = 5; 3823 } 3824#endif 3825} 3826 3827/* This function generates the assembly code for function entry. 3828 FILE is a stdio stream to output the code to. 3829 SIZE is an int: how many units of temporary storage to allocate. 3830 Refer to the array `regs_ever_live' to determine which registers 3831 to save; `regs_ever_live[I]' is nonzero if register number I 3832 is ever used in the function. This macro is responsible for 3833 knowing which registers should not be saved even if used. */ 3834 3835/* On SPARC, move-double insns between fpu and cpu need an 8-byte block 3836 of memory. If any fpu reg is used in the function, we allocate 3837 such a block here, at the bottom of the frame, just in case it's needed. 3838 3839 If this function is a leaf procedure, then we may choose not 3840 to do a "save" insn. The decision about whether or not 3841 to do this is made in regclass.c. */ 3842 3843static void 3844sparc_output_function_prologue (file, size) 3845 FILE *file; 3846 HOST_WIDE_INT size; 3847{ 3848 if (TARGET_FLAT) 3849 sparc_flat_function_prologue (file, size); 3850 else 3851 sparc_nonflat_function_prologue (file, size, 3852 current_function_uses_only_leaf_regs); 3853} 3854 3855/* Output code for the function prologue. */ 3856 3857static void 3858sparc_nonflat_function_prologue (file, size, leaf_function) 3859 FILE *file; 3860 HOST_WIDE_INT size; 3861 int leaf_function; 3862{ 3863 sparc_output_scratch_registers (file); 3864 3865 /* Need to use actual_fsize, since we are also allocating 3866 space for our callee (and our own register save area). */ 3867 actual_fsize = compute_frame_size (size, leaf_function); 3868 3869 if (leaf_function) 3870 { 3871 frame_base_name = "%sp"; 3872 frame_base_offset = actual_fsize + SPARC_STACK_BIAS; 3873 } 3874 else 3875 { 3876 frame_base_name = "%fp"; 3877 frame_base_offset = SPARC_STACK_BIAS; 3878 } 3879 3880 /* This is only for the human reader. */ 3881 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); 3882 3883 if (actual_fsize == 0) 3884 /* do nothing. */ ; 3885 else if (! leaf_function) 3886 { 3887 if (actual_fsize <= 4096) 3888 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize); 3889 else if (actual_fsize <= 8192) 3890 { 3891 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); 3892 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); 3893 } 3894 else 3895 { 3896 build_big_number (file, -actual_fsize, "%g1"); 3897 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); 3898 } 3899 } 3900 else /* leaf function */ 3901 { 3902 if (actual_fsize <= 4096) 3903 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize); 3904 else if (actual_fsize <= 8192) 3905 { 3906 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); 3907 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); 3908 } 3909 else 3910 { 3911 build_big_number (file, -actual_fsize, "%g1"); 3912 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); 3913 } 3914 } 3915 3916 if (dwarf2out_do_frame () && actual_fsize) 3917 { 3918 char *label = dwarf2out_cfi_label (); 3919 3920 /* The canonical frame address refers to the top of the frame. */ 3921 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM 3922 : HARD_FRAME_POINTER_REGNUM), 3923 frame_base_offset); 3924 3925 if (! leaf_function) 3926 { 3927 /* Note the register window save. This tells the unwinder that 3928 it needs to restore the window registers from the previous 3929 frame's window save area at 0(cfa). */ 3930 dwarf2out_window_save (label); 3931 3932 /* The return address (-8) is now in %i7. */ 3933 dwarf2out_return_reg (label, 31); 3934 } 3935 } 3936 3937 /* If doing anything with PIC, do it now. */ 3938 if (! flag_pic) 3939 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); 3940 3941 /* Call saved registers are saved just above the outgoing argument area. */ 3942 if (num_gfregs) 3943 { 3944 int offset, real_offset, n_regs; 3945 const char *base; 3946 3947 real_offset = -apparent_fsize; 3948 offset = -apparent_fsize + frame_base_offset; 3949 if (offset < -4096 || offset + num_gfregs * 4 > 4096) 3950 { 3951 /* ??? This might be optimized a little as %g1 might already have a 3952 value close enough that a single add insn will do. */ 3953 /* ??? Although, all of this is probably only a temporary fix 3954 because if %g1 can hold a function result, then 3955 output_function_epilogue will lose (the result will get 3956 clobbered). */ 3957 build_big_number (file, offset, "%g1"); 3958 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); 3959 base = "%g1"; 3960 offset = 0; 3961 } 3962 else 3963 { 3964 base = frame_base_name; 3965 } 3966 3967 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); 3968 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, 3969 real_offset); 3970 } 3971} 3972 3973/* Output code to restore any call saved registers. */ 3974 3975static void 3976output_restore_regs (file, leaf_function) 3977 FILE *file; 3978 int leaf_function ATTRIBUTE_UNUSED; 3979{ 3980 int offset, n_regs; 3981 const char *base; 3982 3983 offset = -apparent_fsize + frame_base_offset; 3984 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) 3985 { 3986 build_big_number (file, offset, "%g1"); 3987 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); 3988 base = "%g1"; 3989 offset = 0; 3990 } 3991 else 3992 { 3993 base = frame_base_name; 3994 } 3995 3996 n_regs = restore_regs (file, 0, 8, base, offset, 0); 3997 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); 3998} 3999 4000/* This function generates the assembly code for function exit, 4001 on machines that need it. 4002 4003 The function epilogue should not depend on the current stack pointer! 4004 It should use the frame pointer only. This is mandatory because 4005 of alloca; we also take advantage of it to omit stack adjustments 4006 before returning. */ 4007 4008static void 4009sparc_output_function_epilogue (file, size) 4010 FILE *file; 4011 HOST_WIDE_INT size; 4012{ 4013 if (TARGET_FLAT) 4014 sparc_flat_function_epilogue (file, size); 4015 else 4016 sparc_nonflat_function_epilogue (file, size, 4017 current_function_uses_only_leaf_regs); 4018} 4019 4020/* Output code for the function epilogue. */ 4021 4022static void 4023sparc_nonflat_function_epilogue (file, size, leaf_function) 4024 FILE *file; 4025 HOST_WIDE_INT size ATTRIBUTE_UNUSED; 4026 int leaf_function; 4027{ 4028 const char *ret; 4029 4030 if (current_function_epilogue_delay_list == 0) 4031 { 4032 /* If code does not drop into the epilogue, we need 4033 do nothing except output pending case vectors. 4034 4035 We have to still output a dummy nop for the sake of 4036 sane backtraces. Otherwise, if the last two instructions 4037 of a function were call foo; dslot; this can make the return 4038 PC of foo (ie. address of call instruction plus 8) point to 4039 the first instruction in the next function. */ 4040 rtx insn, last_real_insn; 4041 4042 insn = get_last_insn (); 4043 4044 last_real_insn = prev_real_insn (insn); 4045 if (last_real_insn 4046 && GET_CODE (last_real_insn) == INSN 4047 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE) 4048 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0); 4049 4050 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN) 4051 fputs("\tnop\n", file); 4052 4053 if (GET_CODE (insn) == NOTE) 4054 insn = prev_nonnote_insn (insn); 4055 if (insn && GET_CODE (insn) == BARRIER) 4056 goto output_vectors; 4057 } 4058 4059 if (num_gfregs) 4060 output_restore_regs (file, leaf_function); 4061 4062 /* Work out how to skip the caller's unimp instruction if required. */ 4063 if (leaf_function) 4064 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); 4065 else 4066 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); 4067 4068 if (! leaf_function) 4069 { 4070 if (current_function_calls_eh_return) 4071 { 4072 if (current_function_epilogue_delay_list) 4073 abort (); 4074 if (SKIP_CALLERS_UNIMP_P) 4075 abort (); 4076 4077 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file); 4078 } 4079 /* If we wound up with things in our delay slot, flush them here. */ 4080 else if (current_function_epilogue_delay_list) 4081 { 4082 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0)); 4083 4084 if (TARGET_V9 && ! epilogue_renumber (&delay, 1)) 4085 { 4086 epilogue_renumber (&delay, 0); 4087 fputs (SKIP_CALLERS_UNIMP_P 4088 ? "\treturn\t%i7+12\n" 4089 : "\treturn\t%i7+8\n", file); 4090 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), 4091 file, 1, 0, 0); 4092 } 4093 else 4094 { 4095 rtx insn, src; 4096 4097 if (GET_CODE (delay) != SET) 4098 abort(); 4099 4100 src = SET_SRC (delay); 4101 if (GET_CODE (src) == ASHIFT) 4102 { 4103 if (XEXP (src, 1) != const1_rtx) 4104 abort(); 4105 SET_SRC (delay) 4106 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0), 4107 XEXP (src, 0)); 4108 } 4109 4110 insn = gen_rtx_PARALLEL (VOIDmode, 4111 gen_rtvec (2, delay, 4112 gen_rtx_RETURN (VOIDmode))); 4113 insn = emit_jump_insn (insn); 4114 4115 sparc_emitting_epilogue = true; 4116 final_scan_insn (insn, file, 1, 0, 1); 4117 sparc_emitting_epilogue = false; 4118 } 4119 } 4120 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) 4121 fputs ("\treturn\t%i7+8\n\tnop\n", file); 4122 else 4123 fprintf (file, "\t%s\n\trestore\n", ret); 4124 } 4125 /* All of the following cases are for leaf functions. */ 4126 else if (current_function_calls_eh_return) 4127 abort (); 4128 else if (current_function_epilogue_delay_list) 4129 { 4130 /* eligible_for_epilogue_delay_slot ensures that if this is a 4131 leaf function, then we will only have insn in the delay slot 4132 if the frame size is zero, thus no adjust for the stack is 4133 needed here. */ 4134 if (actual_fsize != 0) 4135 abort (); 4136 fprintf (file, "\t%s\n", ret); 4137 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), 4138 file, 1, 0, 1); 4139 } 4140 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to 4141 avoid generating confusing assembly language output. */ 4142 else if (actual_fsize == 0) 4143 fprintf (file, "\t%s\n\tnop\n", ret); 4144 else if (actual_fsize <= 4096) 4145 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize); 4146 else if (actual_fsize <= 8192) 4147 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n", 4148 ret, actual_fsize - 4096); 4149 else if ((actual_fsize & 0x3ff) == 0) 4150 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", 4151 actual_fsize, ret); 4152 else 4153 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", 4154 actual_fsize, actual_fsize, ret); 4155 4156 output_vectors: 4157 sparc_output_deferred_case_vectors (); 4158} 4159 4160/* Output a sibling call. */ 4161 4162const char * 4163output_sibcall (insn, call_operand) 4164 rtx insn, call_operand; 4165{ 4166 int leaf_regs = current_function_uses_only_leaf_regs; 4167 rtx operands[3]; 4168 int delay_slot = dbr_sequence_length () > 0; 4169 4170 if (num_gfregs) 4171 { 4172 /* Call to restore global regs might clobber 4173 the delay slot. Instead of checking for this 4174 output the delay slot now. */ 4175 if (delay_slot) 4176 { 4177 rtx delay = NEXT_INSN (insn); 4178 4179 if (! delay) 4180 abort (); 4181 4182 final_scan_insn (delay, asm_out_file, 1, 0, 1); 4183 PATTERN (delay) = gen_blockage (); 4184 INSN_CODE (delay) = -1; 4185 delay_slot = 0; 4186 } 4187 output_restore_regs (asm_out_file, leaf_regs); 4188 } 4189 4190 operands[0] = call_operand; 4191 4192 if (leaf_regs) 4193 { 4194#ifdef HAVE_AS_RELAX_OPTION 4195 /* If as and ld are relaxing tail call insns into branch always, 4196 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can 4197 be optimized. With sethi/jmpl as nor ld has no easy way how to 4198 find out if somebody does not branch between the sethi and jmpl. */ 4199 int spare_slot = 0; 4200#else 4201 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic); 4202#endif 4203 int size = 0; 4204 4205 if ((actual_fsize || ! spare_slot) && delay_slot) 4206 { 4207 rtx delay = NEXT_INSN (insn); 4208 4209 if (! delay) 4210 abort (); 4211 4212 final_scan_insn (delay, asm_out_file, 1, 0, 1); 4213 PATTERN (delay) = gen_blockage (); 4214 INSN_CODE (delay) = -1; 4215 delay_slot = 0; 4216 } 4217 if (actual_fsize) 4218 { 4219 if (actual_fsize <= 4096) 4220 size = actual_fsize; 4221 else if (actual_fsize <= 8192) 4222 { 4223 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file); 4224 size = actual_fsize - 4096; 4225 } 4226 else if ((actual_fsize & 0x3ff) == 0) 4227 fprintf (asm_out_file, 4228 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n", 4229 actual_fsize); 4230 else 4231 { 4232 fprintf (asm_out_file, 4233 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n", 4234 actual_fsize, actual_fsize); 4235 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file); 4236 } 4237 } 4238 if (spare_slot) 4239 { 4240 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands); 4241 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands); 4242 if (size) 4243 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size); 4244 else if (! delay_slot) 4245 fputs ("\t nop\n", asm_out_file); 4246 } 4247 else 4248 { 4249 if (size) 4250 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size); 4251 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize 4252 it into branch if possible. */ 4253 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands); 4254 output_asm_insn ("call\t%a0, 0", operands); 4255 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands); 4256 } 4257 return ""; 4258 } 4259 4260 output_asm_insn ("call\t%a0, 0", operands); 4261 if (delay_slot) 4262 { 4263 rtx delay = NEXT_INSN (insn), pat; 4264 4265 if (! delay) 4266 abort (); 4267 4268 pat = PATTERN (delay); 4269 if (GET_CODE (pat) != SET) 4270 abort (); 4271 4272 operands[0] = SET_DEST (pat); 4273 pat = SET_SRC (pat); 4274 switch (GET_CODE (pat)) 4275 { 4276 case PLUS: 4277 operands[1] = XEXP (pat, 0); 4278 operands[2] = XEXP (pat, 1); 4279 output_asm_insn (" restore %r1, %2, %Y0", operands); 4280 break; 4281 case LO_SUM: 4282 operands[1] = XEXP (pat, 0); 4283 operands[2] = XEXP (pat, 1); 4284 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); 4285 break; 4286 case ASHIFT: 4287 operands[1] = XEXP (pat, 0); 4288 output_asm_insn (" restore %r1, %r1, %Y0", operands); 4289 break; 4290 default: 4291 operands[1] = pat; 4292 output_asm_insn (" restore %%g0, %1, %Y0", operands); 4293 break; 4294 } 4295 PATTERN (delay) = gen_blockage (); 4296 INSN_CODE (delay) = -1; 4297 } 4298 else 4299 fputs ("\t restore\n", asm_out_file); 4300 return ""; 4301} 4302 4303/* Functions for handling argument passing. 4304 4305 For v8 the first six args are normally in registers and the rest are 4306 pushed. Any arg that starts within the first 6 words is at least 4307 partially passed in a register unless its data type forbids. 4308 4309 For v9, the argument registers are laid out as an array of 16 elements 4310 and arguments are added sequentially. The first 6 int args and up to the 4311 first 16 fp args (depending on size) are passed in regs. 4312 4313 Slot Stack Integral Float Float in structure Double Long Double 4314 ---- ----- -------- ----- ------------------ ------ ----------- 4315 15 [SP+248] %f31 %f30,%f31 %d30 4316 14 [SP+240] %f29 %f28,%f29 %d28 %q28 4317 13 [SP+232] %f27 %f26,%f27 %d26 4318 12 [SP+224] %f25 %f24,%f25 %d24 %q24 4319 11 [SP+216] %f23 %f22,%f23 %d22 4320 10 [SP+208] %f21 %f20,%f21 %d20 %q20 4321 9 [SP+200] %f19 %f18,%f19 %d18 4322 8 [SP+192] %f17 %f16,%f17 %d16 %q16 4323 7 [SP+184] %f15 %f14,%f15 %d14 4324 6 [SP+176] %f13 %f12,%f13 %d12 %q12 4325 5 [SP+168] %o5 %f11 %f10,%f11 %d10 4326 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 4327 3 [SP+152] %o3 %f7 %f6,%f7 %d6 4328 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 4329 1 [SP+136] %o1 %f3 %f2,%f3 %d2 4330 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 4331 4332 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. 4333 4334 Integral arguments are always passed as 64 bit quantities appropriately 4335 extended. 4336 4337 Passing of floating point values is handled as follows. 4338 If a prototype is in scope: 4339 If the value is in a named argument (i.e. not a stdarg function or a 4340 value not part of the `...') then the value is passed in the appropriate 4341 fp reg. 4342 If the value is part of the `...' and is passed in one of the first 6 4343 slots then the value is passed in the appropriate int reg. 4344 If the value is part of the `...' and is not passed in one of the first 6 4345 slots then the value is passed in memory. 4346 If a prototype is not in scope: 4347 If the value is one of the first 6 arguments the value is passed in the 4348 appropriate integer reg and the appropriate fp reg. 4349 If the value is not one of the first 6 arguments the value is passed in 4350 the appropriate fp reg and in memory. 4351 */ 4352 4353/* Maximum number of int regs for args. */ 4354#define SPARC_INT_ARG_MAX 6 4355/* Maximum number of fp regs for args. */ 4356#define SPARC_FP_ARG_MAX 16 4357 4358#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 4359 4360/* Handle the INIT_CUMULATIVE_ARGS macro. 4361 Initialize a variable CUM of type CUMULATIVE_ARGS 4362 for a call to a function whose data type is FNTYPE. 4363 For a library call, FNTYPE is 0. */ 4364 4365void 4366init_cumulative_args (cum, fntype, libname, indirect) 4367 CUMULATIVE_ARGS *cum; 4368 tree fntype; 4369 rtx libname ATTRIBUTE_UNUSED; 4370 int indirect ATTRIBUTE_UNUSED; 4371{ 4372 cum->words = 0; 4373 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); 4374 cum->libcall_p = fntype == 0; 4375} 4376 4377/* Compute the slot number to pass an argument in. 4378 Returns the slot number or -1 if passing on the stack. 4379 4380 CUM is a variable of type CUMULATIVE_ARGS which gives info about 4381 the preceding args and about the function being called. 4382 MODE is the argument's machine mode. 4383 TYPE is the data type of the argument (as a tree). 4384 This is null for libcalls where that information may 4385 not be available. 4386 NAMED is nonzero if this argument is a named parameter 4387 (otherwise it is an extra parameter matching an ellipsis). 4388 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. 4389 *PREGNO records the register number to use if scalar type. 4390 *PPADDING records the amount of padding needed in words. */ 4391 4392static int 4393function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding) 4394 const CUMULATIVE_ARGS *cum; 4395 enum machine_mode mode; 4396 tree type; 4397 int named; 4398 int incoming_p; 4399 int *pregno; 4400 int *ppadding; 4401{ 4402 int regbase = (incoming_p 4403 ? SPARC_INCOMING_INT_ARG_FIRST 4404 : SPARC_OUTGOING_INT_ARG_FIRST); 4405 int slotno = cum->words; 4406 int regno; 4407 4408 *ppadding = 0; 4409 4410 if (type != 0 && TREE_ADDRESSABLE (type)) 4411 return -1; 4412 if (TARGET_ARCH32 4413 && type != 0 && mode == BLKmode 4414 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) 4415 return -1; 4416 4417 switch (mode) 4418 { 4419 case VOIDmode : 4420 /* MODE is VOIDmode when generating the actual call. 4421 See emit_call_1. */ 4422 return -1; 4423 4424 case QImode : case CQImode : 4425 case HImode : case CHImode : 4426 case SImode : case CSImode : 4427 case DImode : case CDImode : 4428 case TImode : case CTImode : 4429 if (slotno >= SPARC_INT_ARG_MAX) 4430 return -1; 4431 regno = regbase + slotno; 4432 break; 4433 4434 case SFmode : case SCmode : 4435 case DFmode : case DCmode : 4436 case TFmode : case TCmode : 4437 if (TARGET_ARCH32) 4438 { 4439 if (slotno >= SPARC_INT_ARG_MAX) 4440 return -1; 4441 regno = regbase + slotno; 4442 } 4443 else 4444 { 4445 if ((mode == TFmode || mode == TCmode) 4446 && (slotno & 1) != 0) 4447 slotno++, *ppadding = 1; 4448 if (TARGET_FPU && named) 4449 { 4450 if (slotno >= SPARC_FP_ARG_MAX) 4451 return -1; 4452 regno = SPARC_FP_ARG_FIRST + slotno * 2; 4453 if (mode == SFmode) 4454 regno++; 4455 } 4456 else 4457 { 4458 if (slotno >= SPARC_INT_ARG_MAX) 4459 return -1; 4460 regno = regbase + slotno; 4461 } 4462 } 4463 break; 4464 4465 case BLKmode : 4466 /* For sparc64, objects requiring 16 byte alignment get it. */ 4467 if (TARGET_ARCH64) 4468 { 4469 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) 4470 slotno++, *ppadding = 1; 4471 } 4472 4473 if (TARGET_ARCH32 4474 || (type && TREE_CODE (type) == UNION_TYPE)) 4475 { 4476 if (slotno >= SPARC_INT_ARG_MAX) 4477 return -1; 4478 regno = regbase + slotno; 4479 } 4480 else 4481 { 4482 tree field; 4483 int intregs_p = 0, fpregs_p = 0; 4484 /* The ABI obviously doesn't specify how packed 4485 structures are passed. These are defined to be passed 4486 in int regs if possible, otherwise memory. */ 4487 int packed_p = 0; 4488 4489 /* First see what kinds of registers we need. */ 4490 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4491 { 4492 if (TREE_CODE (field) == FIELD_DECL) 4493 { 4494 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE 4495 && TARGET_FPU) 4496 fpregs_p = 1; 4497 else 4498 intregs_p = 1; 4499 if (DECL_PACKED (field)) 4500 packed_p = 1; 4501 } 4502 } 4503 if (packed_p || !named) 4504 fpregs_p = 0, intregs_p = 1; 4505 4506 /* If all arg slots are filled, then must pass on stack. */ 4507 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) 4508 return -1; 4509 /* If there are only int args and all int arg slots are filled, 4510 then must pass on stack. */ 4511 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) 4512 return -1; 4513 /* Note that even if all int arg slots are filled, fp members may 4514 still be passed in regs if such regs are available. 4515 *PREGNO isn't set because there may be more than one, it's up 4516 to the caller to compute them. */ 4517 return slotno; 4518 } 4519 break; 4520 4521 default : 4522 abort (); 4523 } 4524 4525 *pregno = regno; 4526 return slotno; 4527} 4528 4529/* Handle recursive register counting for structure field layout. */ 4530 4531struct function_arg_record_value_parms 4532{ 4533 rtx ret; /* return expression being built. */ 4534 int slotno; /* slot number of the argument. */ 4535 int named; /* whether the argument is named. */ 4536 int regbase; /* regno of the base register. */ 4537 int stack; /* 1 if part of the argument is on the stack. */ 4538 int intoffset; /* offset of the pending integer field. */ 4539 unsigned int nregs; /* number of words passed in registers. */ 4540}; 4541 4542static void function_arg_record_value_3 4543 PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *)); 4544static void function_arg_record_value_2 4545 PARAMS ((tree, HOST_WIDE_INT, 4546 struct function_arg_record_value_parms *)); 4547static void function_arg_record_value_1 4548 PARAMS ((tree, HOST_WIDE_INT, 4549 struct function_arg_record_value_parms *)); 4550static rtx function_arg_record_value 4551 PARAMS ((tree, enum machine_mode, int, int, int)); 4552 4553/* A subroutine of function_arg_record_value. Traverse the structure 4554 recusively and determine how many registers will be required. */ 4555 4556static void 4557function_arg_record_value_1 (type, startbitpos, parms) 4558 tree type; 4559 HOST_WIDE_INT startbitpos; 4560 struct function_arg_record_value_parms *parms; 4561{ 4562 tree field; 4563 4564 /* The ABI obviously doesn't specify how packed structures are 4565 passed. These are defined to be passed in int regs if possible, 4566 otherwise memory. */ 4567 int packed_p = 0; 4568 4569 /* We need to compute how many registers are needed so we can 4570 allocate the PARALLEL but before we can do that we need to know 4571 whether there are any packed fields. If there are, int regs are 4572 used regardless of whether there are fp values present. */ 4573 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4574 { 4575 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 4576 { 4577 packed_p = 1; 4578 break; 4579 } 4580 } 4581 4582 /* Compute how many registers we need. */ 4583 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4584 { 4585 if (TREE_CODE (field) == FIELD_DECL) 4586 { 4587 HOST_WIDE_INT bitpos = startbitpos; 4588 4589 if (DECL_SIZE (field) != 0 4590 && host_integerp (bit_position (field), 1)) 4591 bitpos += int_bit_position (field); 4592 4593 /* ??? FIXME: else assume zero offset. */ 4594 4595 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 4596 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms); 4597 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE 4598 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE 4599 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) 4600 == REAL_TYPE))) 4601 && TARGET_FPU 4602 && ! packed_p 4603 && parms->named) 4604 { 4605 if (parms->intoffset != -1) 4606 { 4607 int intslots, this_slotno; 4608 4609 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1) 4610 / BITS_PER_WORD; 4611 this_slotno = parms->slotno + parms->intoffset 4612 / BITS_PER_WORD; 4613 4614 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) 4615 { 4616 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); 4617 /* We need to pass this field on the stack. */ 4618 parms->stack = 1; 4619 } 4620 4621 parms->nregs += intslots; 4622 parms->intoffset = -1; 4623 } 4624 4625 /* There's no need to check this_slotno < SPARC_FP_ARG MAX. 4626 If it wasn't true we wouldn't be here. */ 4627 parms->nregs += 1; 4628 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 4629 parms->nregs += 1; 4630 } 4631 else 4632 { 4633 if (parms->intoffset == -1) 4634 parms->intoffset = bitpos; 4635 } 4636 } 4637 } 4638} 4639 4640/* A subroutine of function_arg_record_value. Assign the bits of the 4641 structure between parms->intoffset and bitpos to integer registers. */ 4642 4643static void 4644function_arg_record_value_3 (bitpos, parms) 4645 HOST_WIDE_INT bitpos; 4646 struct function_arg_record_value_parms *parms; 4647{ 4648 enum machine_mode mode; 4649 unsigned int regno; 4650 unsigned int startbit, endbit; 4651 int this_slotno, intslots, intoffset; 4652 rtx reg; 4653 4654 if (parms->intoffset == -1) 4655 return; 4656 4657 intoffset = parms->intoffset; 4658 parms->intoffset = -1; 4659 4660 startbit = intoffset & -BITS_PER_WORD; 4661 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; 4662 intslots = (endbit - startbit) / BITS_PER_WORD; 4663 this_slotno = parms->slotno + intoffset / BITS_PER_WORD; 4664 4665 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); 4666 if (intslots <= 0) 4667 return; 4668 4669 /* If this is the trailing part of a word, only load that much into 4670 the register. Otherwise load the whole register. Note that in 4671 the latter case we may pick up unwanted bits. It's not a problem 4672 at the moment but may wish to revisit. */ 4673 4674 if (intoffset % BITS_PER_WORD != 0) 4675 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, 4676 MODE_INT, 0); 4677 else 4678 mode = word_mode; 4679 4680 intoffset /= BITS_PER_UNIT; 4681 do 4682 { 4683 regno = parms->regbase + this_slotno; 4684 reg = gen_rtx_REG (mode, regno); 4685 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 4686 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); 4687 4688 this_slotno += 1; 4689 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; 4690 parms->nregs += 1; 4691 intslots -= 1; 4692 } 4693 while (intslots > 0); 4694} 4695 4696/* A subroutine of function_arg_record_value. Traverse the structure 4697 recursively and assign bits to floating point registers. Track which 4698 bits in between need integer registers; invoke function_arg_record_value_3 4699 to make that happen. */ 4700 4701static void 4702function_arg_record_value_2 (type, startbitpos, parms) 4703 tree type; 4704 HOST_WIDE_INT startbitpos; 4705 struct function_arg_record_value_parms *parms; 4706{ 4707 tree field; 4708 int packed_p = 0; 4709 4710 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4711 { 4712 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 4713 { 4714 packed_p = 1; 4715 break; 4716 } 4717 } 4718 4719 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4720 { 4721 if (TREE_CODE (field) == FIELD_DECL) 4722 { 4723 HOST_WIDE_INT bitpos = startbitpos; 4724 4725 if (DECL_SIZE (field) != 0 4726 && host_integerp (bit_position (field), 1)) 4727 bitpos += int_bit_position (field); 4728 4729 /* ??? FIXME: else assume zero offset. */ 4730 4731 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 4732 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms); 4733 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE 4734 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE 4735 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) 4736 == REAL_TYPE))) 4737 && TARGET_FPU 4738 && ! packed_p 4739 && parms->named) 4740 { 4741 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; 4742 int regno; 4743 enum machine_mode mode = DECL_MODE (field); 4744 rtx reg; 4745 4746 function_arg_record_value_3 (bitpos, parms); 4747 regno = SPARC_FP_ARG_FIRST + this_slotno * 2 4748 + ((mode == SFmode || mode == SCmode) 4749 && (bitpos & 32) != 0); 4750 switch (mode) 4751 { 4752 case SCmode: mode = SFmode; break; 4753 case DCmode: mode = DFmode; break; 4754 case TCmode: mode = TFmode; break; 4755 default: break; 4756 } 4757 reg = gen_rtx_REG (mode, regno); 4758 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 4759 = gen_rtx_EXPR_LIST (VOIDmode, reg, 4760 GEN_INT (bitpos / BITS_PER_UNIT)); 4761 parms->nregs += 1; 4762 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 4763 { 4764 regno += GET_MODE_SIZE (mode) / 4; 4765 reg = gen_rtx_REG (mode, regno); 4766 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 4767 = gen_rtx_EXPR_LIST (VOIDmode, reg, 4768 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode)) 4769 / BITS_PER_UNIT)); 4770 parms->nregs += 1; 4771 } 4772 } 4773 else 4774 { 4775 if (parms->intoffset == -1) 4776 parms->intoffset = bitpos; 4777 } 4778 } 4779 } 4780} 4781 4782/* Used by function_arg and function_value to implement the complex 4783 conventions of the 64-bit ABI for passing and returning structures. 4784 Return an expression valid as a return value for the two macros 4785 FUNCTION_ARG and FUNCTION_VALUE. 4786 4787 TYPE is the data type of the argument (as a tree). 4788 This is null for libcalls where that information may 4789 not be available. 4790 MODE is the argument's machine mode. 4791 SLOTNO is the index number of the argument's slot in the parameter array. 4792 NAMED is nonzero if this argument is a named parameter 4793 (otherwise it is an extra parameter matching an ellipsis). 4794 REGBASE is the regno of the base register for the parameter array. */ 4795 4796static rtx 4797function_arg_record_value (type, mode, slotno, named, regbase) 4798 tree type; 4799 enum machine_mode mode; 4800 int slotno, named, regbase; 4801{ 4802 HOST_WIDE_INT typesize = int_size_in_bytes (type); 4803 struct function_arg_record_value_parms parms; 4804 unsigned int nregs; 4805 4806 parms.ret = NULL_RTX; 4807 parms.slotno = slotno; 4808 parms.named = named; 4809 parms.regbase = regbase; 4810 parms.stack = 0; 4811 4812 /* Compute how many registers we need. */ 4813 parms.nregs = 0; 4814 parms.intoffset = 0; 4815 function_arg_record_value_1 (type, 0, &parms); 4816 4817 if (parms.intoffset != -1) 4818 { 4819 unsigned int startbit, endbit; 4820 int intslots, this_slotno; 4821 4822 startbit = parms.intoffset & -BITS_PER_WORD; 4823 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; 4824 intslots = (endbit - startbit) / BITS_PER_WORD; 4825 this_slotno = slotno + parms.intoffset / BITS_PER_WORD; 4826 4827 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) 4828 { 4829 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); 4830 /* We need to pass this field on the stack. */ 4831 parms.stack = 1; 4832 } 4833 4834 parms.nregs += intslots; 4835 } 4836 nregs = parms.nregs; 4837 4838 /* Allocate the vector and handle some annoying special cases. */ 4839 if (nregs == 0) 4840 { 4841 /* ??? Empty structure has no value? Duh? */ 4842 if (typesize <= 0) 4843 { 4844 /* Though there's nothing really to store, return a word register 4845 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL 4846 leads to breakage due to the fact that there are zero bytes to 4847 load. */ 4848 return gen_rtx_REG (mode, regbase); 4849 } 4850 else 4851 { 4852 /* ??? C++ has structures with no fields, and yet a size. Give up 4853 for now and pass everything back in integer registers. */ 4854 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 4855 } 4856 if (nregs + slotno > SPARC_INT_ARG_MAX) 4857 nregs = SPARC_INT_ARG_MAX - slotno; 4858 } 4859 if (nregs == 0) 4860 abort (); 4861 4862 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs)); 4863 4864 /* If at least one field must be passed on the stack, generate 4865 (parallel [(expr_list (nil) ...) ...]) so that all fields will 4866 also be passed on the stack. We can't do much better because the 4867 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case 4868 of structures for which the fields passed exclusively in registers 4869 are not at the beginning of the structure. */ 4870 if (parms.stack) 4871 XVECEXP (parms.ret, 0, 0) 4872 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 4873 4874 /* Fill in the entries. */ 4875 parms.nregs = 0; 4876 parms.intoffset = 0; 4877 function_arg_record_value_2 (type, 0, &parms); 4878 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); 4879 4880 if (parms.nregs != nregs) 4881 abort (); 4882 4883 return parms.ret; 4884} 4885 4886/* Handle the FUNCTION_ARG macro. 4887 Determine where to put an argument to a function. 4888 Value is zero to push the argument on the stack, 4889 or a hard register in which to store the argument. 4890 4891 CUM is a variable of type CUMULATIVE_ARGS which gives info about 4892 the preceding args and about the function being called. 4893 MODE is the argument's machine mode. 4894 TYPE is the data type of the argument (as a tree). 4895 This is null for libcalls where that information may 4896 not be available. 4897 NAMED is nonzero if this argument is a named parameter 4898 (otherwise it is an extra parameter matching an ellipsis). 4899 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ 4900 4901rtx 4902function_arg (cum, mode, type, named, incoming_p) 4903 const CUMULATIVE_ARGS *cum; 4904 enum machine_mode mode; 4905 tree type; 4906 int named; 4907 int incoming_p; 4908{ 4909 int regbase = (incoming_p 4910 ? SPARC_INCOMING_INT_ARG_FIRST 4911 : SPARC_OUTGOING_INT_ARG_FIRST); 4912 int slotno, regno, padding; 4913 rtx reg; 4914 4915 slotno = function_arg_slotno (cum, mode, type, named, incoming_p, 4916 ®no, &padding); 4917 4918 if (slotno == -1) 4919 return 0; 4920 4921 if (TARGET_ARCH32) 4922 { 4923 reg = gen_rtx_REG (mode, regno); 4924 return reg; 4925 } 4926 4927 /* v9 fp args in reg slots beyond the int reg slots get passed in regs 4928 but also have the slot allocated for them. 4929 If no prototype is in scope fp values in register slots get passed 4930 in two places, either fp regs and int regs or fp regs and memory. */ 4931 if ((GET_MODE_CLASS (mode) == MODE_FLOAT 4932 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 4933 && SPARC_FP_REG_P (regno)) 4934 { 4935 reg = gen_rtx_REG (mode, regno); 4936 if (cum->prototype_p || cum->libcall_p) 4937 { 4938 /* "* 2" because fp reg numbers are recorded in 4 byte 4939 quantities. */ 4940#if 0 4941 /* ??? This will cause the value to be passed in the fp reg and 4942 in the stack. When a prototype exists we want to pass the 4943 value in the reg but reserve space on the stack. That's an 4944 optimization, and is deferred [for a bit]. */ 4945 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) 4946 return gen_rtx_PARALLEL (mode, 4947 gen_rtvec (2, 4948 gen_rtx_EXPR_LIST (VOIDmode, 4949 NULL_RTX, const0_rtx), 4950 gen_rtx_EXPR_LIST (VOIDmode, 4951 reg, const0_rtx))); 4952 else 4953#else 4954 /* ??? It seems that passing back a register even when past 4955 the area declared by REG_PARM_STACK_SPACE will allocate 4956 space appropriately, and will not copy the data onto the 4957 stack, exactly as we desire. 4958 4959 This is due to locate_and_pad_parm being called in 4960 expand_call whenever reg_parm_stack_space > 0, which 4961 while benefical to our example here, would seem to be 4962 in error from what had been intended. Ho hum... -- r~ */ 4963#endif 4964 return reg; 4965 } 4966 else 4967 { 4968 rtx v0, v1; 4969 4970 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) 4971 { 4972 int intreg; 4973 4974 /* On incoming, we don't need to know that the value 4975 is passed in %f0 and %i0, and it confuses other parts 4976 causing needless spillage even on the simplest cases. */ 4977 if (incoming_p) 4978 return reg; 4979 4980 intreg = (SPARC_OUTGOING_INT_ARG_FIRST 4981 + (regno - SPARC_FP_ARG_FIRST) / 2); 4982 4983 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 4984 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), 4985 const0_rtx); 4986 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 4987 } 4988 else 4989 { 4990 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 4991 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 4992 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 4993 } 4994 } 4995 } 4996 else if (type && TREE_CODE (type) == RECORD_TYPE) 4997 { 4998 /* Structures up to 16 bytes in size are passed in arg slots on the 4999 stack and are promoted to registers where possible. */ 5000 5001 if (int_size_in_bytes (type) > 16) 5002 abort (); /* shouldn't get here */ 5003 5004 return function_arg_record_value (type, mode, slotno, named, regbase); 5005 } 5006 else if (type && TREE_CODE (type) == UNION_TYPE) 5007 { 5008 enum machine_mode mode; 5009 int bytes = int_size_in_bytes (type); 5010 5011 if (bytes > 16) 5012 abort (); 5013 5014 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); 5015 reg = gen_rtx_REG (mode, regno); 5016 } 5017 else 5018 { 5019 /* Scalar or complex int. */ 5020 reg = gen_rtx_REG (mode, regno); 5021 } 5022 5023 return reg; 5024} 5025 5026/* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. 5027 For an arg passed partly in registers and partly in memory, 5028 this is the number of registers used. 5029 For args passed entirely in registers or entirely in memory, zero. 5030 5031 Any arg that starts in the first 6 regs but won't entirely fit in them 5032 needs partial registers on v8. On v9, structures with integer 5033 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp 5034 values that begin in the last fp reg [where "last fp reg" varies with the 5035 mode] will be split between that reg and memory. */ 5036 5037int 5038function_arg_partial_nregs (cum, mode, type, named) 5039 const CUMULATIVE_ARGS *cum; 5040 enum machine_mode mode; 5041 tree type; 5042 int named; 5043{ 5044 int slotno, regno, padding; 5045 5046 /* We pass 0 for incoming_p here, it doesn't matter. */ 5047 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); 5048 5049 if (slotno == -1) 5050 return 0; 5051 5052 if (TARGET_ARCH32) 5053 { 5054 if ((slotno + (mode == BLKmode 5055 ? ROUND_ADVANCE (int_size_in_bytes (type)) 5056 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) 5057 > NPARM_REGS (SImode)) 5058 return NPARM_REGS (SImode) - slotno; 5059 return 0; 5060 } 5061 else 5062 { 5063 if (type && AGGREGATE_TYPE_P (type)) 5064 { 5065 int size = int_size_in_bytes (type); 5066 int align = TYPE_ALIGN (type); 5067 5068 if (align == 16) 5069 slotno += slotno & 1; 5070 if (size > 8 && size <= 16 5071 && slotno == SPARC_INT_ARG_MAX - 1) 5072 return 1; 5073 } 5074 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT 5075 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 5076 && ! TARGET_FPU)) 5077 { 5078 if (GET_MODE_ALIGNMENT (mode) == 128) 5079 { 5080 slotno += slotno & 1; 5081 if (slotno == SPARC_INT_ARG_MAX - 2) 5082 return 1; 5083 } 5084 else 5085 { 5086 if (slotno == SPARC_INT_ARG_MAX - 1) 5087 return 1; 5088 } 5089 } 5090 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5091 { 5092 if (GET_MODE_ALIGNMENT (mode) == 128) 5093 slotno += slotno & 1; 5094 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) 5095 > SPARC_FP_ARG_MAX) 5096 return 1; 5097 } 5098 return 0; 5099 } 5100} 5101 5102/* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. 5103 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and 5104 quad-precision floats by invisible reference. 5105 v9: Aggregates greater than 16 bytes are passed by reference. 5106 For Pascal, also pass arrays by reference. */ 5107 5108int 5109function_arg_pass_by_reference (cum, mode, type, named) 5110 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; 5111 enum machine_mode mode; 5112 tree type; 5113 int named ATTRIBUTE_UNUSED; 5114{ 5115 if (TARGET_ARCH32) 5116 { 5117 return ((type && AGGREGATE_TYPE_P (type)) 5118 || mode == TFmode || mode == TCmode); 5119 } 5120 else 5121 { 5122 return ((type && TREE_CODE (type) == ARRAY_TYPE) 5123 /* Consider complex values as aggregates, so care for TCmode. */ 5124 || GET_MODE_SIZE (mode) > 16 5125 || (type 5126 && AGGREGATE_TYPE_P (type) 5127 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)); 5128 } 5129} 5130 5131/* Handle the FUNCTION_ARG_ADVANCE macro. 5132 Update the data in CUM to advance over an argument 5133 of mode MODE and data type TYPE. 5134 TYPE is null for libcalls where that information may not be available. */ 5135 5136void 5137function_arg_advance (cum, mode, type, named) 5138 CUMULATIVE_ARGS *cum; 5139 enum machine_mode mode; 5140 tree type; 5141 int named; 5142{ 5143 int slotno, regno, padding; 5144 5145 /* We pass 0 for incoming_p here, it doesn't matter. */ 5146 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); 5147 5148 /* If register required leading padding, add it. */ 5149 if (slotno != -1) 5150 cum->words += padding; 5151 5152 if (TARGET_ARCH32) 5153 { 5154 cum->words += (mode != BLKmode 5155 ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) 5156 : ROUND_ADVANCE (int_size_in_bytes (type))); 5157 } 5158 else 5159 { 5160 if (type && AGGREGATE_TYPE_P (type)) 5161 { 5162 int size = int_size_in_bytes (type); 5163 5164 if (size <= 8) 5165 ++cum->words; 5166 else if (size <= 16) 5167 cum->words += 2; 5168 else /* passed by reference */ 5169 ++cum->words; 5170 } 5171 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) 5172 { 5173 cum->words += 2; 5174 } 5175 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5176 { 5177 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD; 5178 } 5179 else 5180 { 5181 cum->words += (mode != BLKmode 5182 ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) 5183 : ROUND_ADVANCE (int_size_in_bytes (type))); 5184 } 5185 } 5186} 5187 5188/* Handle the FUNCTION_ARG_PADDING macro. 5189 For the 64 bit ABI structs are always stored left shifted in their 5190 argument slot. */ 5191 5192enum direction 5193function_arg_padding (mode, type) 5194 enum machine_mode mode; 5195 tree type; 5196{ 5197 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) 5198 return upward; 5199 5200 /* This is the default definition. */ 5201 return (! BYTES_BIG_ENDIAN 5202 ? upward 5203 : ((mode == BLKmode 5204 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST 5205 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) 5206 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) 5207 ? downward : upward)); 5208} 5209 5210/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. 5211 For v9, function return values are subject to the same rules as arguments, 5212 except that up to 32-bytes may be returned in registers. */ 5213 5214rtx 5215function_value (type, mode, incoming_p) 5216 tree type; 5217 enum machine_mode mode; 5218 int incoming_p; 5219{ 5220 int regno; 5221 int regbase = (incoming_p 5222 ? SPARC_OUTGOING_INT_ARG_FIRST 5223 : SPARC_INCOMING_INT_ARG_FIRST); 5224 5225 if (TARGET_ARCH64 && type) 5226 { 5227 if (TREE_CODE (type) == RECORD_TYPE) 5228 { 5229 /* Structures up to 32 bytes in size are passed in registers, 5230 promoted to fp registers where possible. */ 5231 5232 if (int_size_in_bytes (type) > 32) 5233 abort (); /* shouldn't get here */ 5234 5235 return function_arg_record_value (type, mode, 0, 1, regbase); 5236 } 5237 else if (AGGREGATE_TYPE_P (type)) 5238 { 5239 /* All other aggregate types are passed in an integer register 5240 in a mode corresponding to the size of the type. */ 5241 HOST_WIDE_INT bytes = int_size_in_bytes (type); 5242 5243 if (bytes > 32) 5244 abort (); 5245 5246 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); 5247 } 5248 } 5249 5250 if (TARGET_ARCH64 5251 && GET_MODE_CLASS (mode) == MODE_INT 5252 && GET_MODE_SIZE (mode) < UNITS_PER_WORD 5253 && type && ! AGGREGATE_TYPE_P (type)) 5254 mode = DImode; 5255 5256 if (incoming_p) 5257 regno = BASE_RETURN_VALUE_REG (mode); 5258 else 5259 regno = BASE_OUTGOING_VALUE_REG (mode); 5260 5261 return gen_rtx_REG (mode, regno); 5262} 5263 5264/* Do what is necessary for `va_start'. We look at the current function 5265 to determine if stdarg or varargs is used and return the address of 5266 the first unnamed parameter. */ 5267 5268rtx 5269sparc_builtin_saveregs () 5270{ 5271 int first_reg = current_function_args_info.words; 5272 rtx address; 5273 int regno; 5274 5275 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) 5276 emit_move_insn (gen_rtx_MEM (word_mode, 5277 gen_rtx_PLUS (Pmode, 5278 frame_pointer_rtx, 5279 GEN_INT (FIRST_PARM_OFFSET (0) 5280 + (UNITS_PER_WORD 5281 * regno)))), 5282 gen_rtx_REG (word_mode, 5283 BASE_INCOMING_ARG_REG (word_mode) + regno)); 5284 5285 address = gen_rtx_PLUS (Pmode, 5286 frame_pointer_rtx, 5287 GEN_INT (FIRST_PARM_OFFSET (0) 5288 + UNITS_PER_WORD * first_reg)); 5289 5290 return address; 5291} 5292 5293/* Implement `va_start' for varargs and stdarg. */ 5294 5295void 5296sparc_va_start (valist, nextarg) 5297 tree valist; 5298 rtx nextarg; 5299{ 5300 nextarg = expand_builtin_saveregs (); 5301 std_expand_builtin_va_start (valist, nextarg); 5302} 5303 5304/* Implement `va_arg'. */ 5305 5306rtx 5307sparc_va_arg (valist, type) 5308 tree valist, type; 5309{ 5310 HOST_WIDE_INT size, rsize, align; 5311 tree addr, incr; 5312 rtx addr_rtx; 5313 int indirect = 0; 5314 5315 /* Round up sizeof(type) to a word. */ 5316 size = int_size_in_bytes (type); 5317 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; 5318 align = 0; 5319 5320 if (TARGET_ARCH64) 5321 { 5322 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) 5323 align = 2 * UNITS_PER_WORD; 5324 5325 if (AGGREGATE_TYPE_P (type)) 5326 { 5327 if ((unsigned HOST_WIDE_INT) size > 16) 5328 { 5329 indirect = 1; 5330 size = rsize = UNITS_PER_WORD; 5331 } 5332 /* SPARC v9 ABI states that structures up to 8 bytes in size are 5333 given one 8 byte slot. */ 5334 else if (size == 0) 5335 size = rsize = UNITS_PER_WORD; 5336 else 5337 size = rsize; 5338 } 5339 } 5340 else 5341 { 5342 if (AGGREGATE_TYPE_P (type) 5343 || TYPE_MODE (type) == TFmode 5344 || TYPE_MODE (type) == TCmode) 5345 { 5346 indirect = 1; 5347 size = rsize = UNITS_PER_WORD; 5348 } 5349 } 5350 5351 incr = valist; 5352 if (align) 5353 { 5354 incr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5355 build_int_2 (align - 1, 0))); 5356 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr, 5357 build_int_2 (-align, -1))); 5358 } 5359 5360 addr = incr = save_expr (incr); 5361 if (BYTES_BIG_ENDIAN && size < rsize) 5362 { 5363 addr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5364 build_int_2 (rsize - size, 0))); 5365 } 5366 incr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5367 build_int_2 (rsize, 0))); 5368 5369 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr); 5370 TREE_SIDE_EFFECTS (incr) = 1; 5371 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); 5372 5373 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); 5374 5375 /* If the address isn't aligned properly for the type, 5376 we may need to copy to a temporary. 5377 FIXME: This is inefficient. Usually we can do this 5378 in registers. */ 5379 if (align == 0 5380 && TYPE_ALIGN (type) > BITS_PER_WORD 5381 && !indirect) 5382 { 5383 /* FIXME: We really need to specify that the temporary is live 5384 for the whole function because expand_builtin_va_arg wants 5385 the alias set to be get_varargs_alias_set (), but in this 5386 case the alias set is that for TYPE and if the memory gets 5387 reused it will be reused with alias set TYPE. */ 5388 rtx tmp = assign_temp (type, 0, 1, 0); 5389 rtx dest_addr; 5390 5391 addr_rtx = force_reg (Pmode, addr_rtx); 5392 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx); 5393 set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); 5394 set_mem_align (addr_rtx, BITS_PER_WORD); 5395 tmp = shallow_copy_rtx (tmp); 5396 PUT_MODE (tmp, BLKmode); 5397 set_mem_alias_set (tmp, 0); 5398 5399 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize), 5400 BLOCK_OP_NORMAL); 5401 if (dest_addr != NULL_RTX) 5402 addr_rtx = dest_addr; 5403 else 5404 addr_rtx = XCEXP (tmp, 0, MEM); 5405 } 5406 5407 if (indirect) 5408 { 5409 addr_rtx = force_reg (Pmode, addr_rtx); 5410 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); 5411 set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); 5412 } 5413 5414 return addr_rtx; 5415} 5416 5417/* Return the string to output a conditional branch to LABEL, which is 5418 the operand number of the label. OP is the conditional expression. 5419 XEXP (OP, 0) is assumed to be a condition code register (integer or 5420 floating point) and its mode specifies what kind of comparison we made. 5421 5422 REVERSED is nonzero if we should reverse the sense of the comparison. 5423 5424 ANNUL is nonzero if we should generate an annulling branch. 5425 5426 NOOP is nonzero if we have to follow this branch by a noop. 5427 5428 INSN, if set, is the insn. */ 5429 5430char * 5431output_cbranch (op, dest, label, reversed, annul, noop, insn) 5432 rtx op, dest; 5433 int label; 5434 int reversed, annul, noop; 5435 rtx insn; 5436{ 5437 static char string[50]; 5438 enum rtx_code code = GET_CODE (op); 5439 rtx cc_reg = XEXP (op, 0); 5440 enum machine_mode mode = GET_MODE (cc_reg); 5441 const char *labelno, *branch; 5442 int spaces = 8, far; 5443 char *p; 5444 5445 /* v9 branches are limited to +-1MB. If it is too far away, 5446 change 5447 5448 bne,pt %xcc, .LC30 5449 5450 to 5451 5452 be,pn %xcc, .+12 5453 nop 5454 ba .LC30 5455 5456 and 5457 5458 fbne,a,pn %fcc2, .LC29 5459 5460 to 5461 5462 fbe,pt %fcc2, .+16 5463 nop 5464 ba .LC29 */ 5465 5466 far = get_attr_length (insn) >= 3; 5467 if (reversed ^ far) 5468 { 5469 /* Reversal of FP compares takes care -- an ordered compare 5470 becomes an unordered compare and vice versa. */ 5471 if (mode == CCFPmode || mode == CCFPEmode) 5472 code = reverse_condition_maybe_unordered (code); 5473 else 5474 code = reverse_condition (code); 5475 } 5476 5477 /* Start by writing the branch condition. */ 5478 if (mode == CCFPmode || mode == CCFPEmode) 5479 { 5480 switch (code) 5481 { 5482 case NE: 5483 branch = "fbne"; 5484 break; 5485 case EQ: 5486 branch = "fbe"; 5487 break; 5488 case GE: 5489 branch = "fbge"; 5490 break; 5491 case GT: 5492 branch = "fbg"; 5493 break; 5494 case LE: 5495 branch = "fble"; 5496 break; 5497 case LT: 5498 branch = "fbl"; 5499 break; 5500 case UNORDERED: 5501 branch = "fbu"; 5502 break; 5503 case ORDERED: 5504 branch = "fbo"; 5505 break; 5506 case UNGT: 5507 branch = "fbug"; 5508 break; 5509 case UNLT: 5510 branch = "fbul"; 5511 break; 5512 case UNEQ: 5513 branch = "fbue"; 5514 break; 5515 case UNGE: 5516 branch = "fbuge"; 5517 break; 5518 case UNLE: 5519 branch = "fbule"; 5520 break; 5521 case LTGT: 5522 branch = "fblg"; 5523 break; 5524 5525 default: 5526 abort (); 5527 } 5528 5529 /* ??? !v9: FP branches cannot be preceded by another floating point 5530 insn. Because there is currently no concept of pre-delay slots, 5531 we can fix this only by always emitting a nop before a floating 5532 point branch. */ 5533 5534 string[0] = '\0'; 5535 if (! TARGET_V9) 5536 strcpy (string, "nop\n\t"); 5537 strcat (string, branch); 5538 } 5539 else 5540 { 5541 switch (code) 5542 { 5543 case NE: 5544 branch = "bne"; 5545 break; 5546 case EQ: 5547 branch = "be"; 5548 break; 5549 case GE: 5550 if (mode == CC_NOOVmode || mode == CCX_NOOVmode) 5551 branch = "bpos"; 5552 else 5553 branch = "bge"; 5554 break; 5555 case GT: 5556 branch = "bg"; 5557 break; 5558 case LE: 5559 branch = "ble"; 5560 break; 5561 case LT: 5562 if (mode == CC_NOOVmode || mode == CCX_NOOVmode) 5563 branch = "bneg"; 5564 else 5565 branch = "bl"; 5566 break; 5567 case GEU: 5568 branch = "bgeu"; 5569 break; 5570 case GTU: 5571 branch = "bgu"; 5572 break; 5573 case LEU: 5574 branch = "bleu"; 5575 break; 5576 case LTU: 5577 branch = "blu"; 5578 break; 5579 5580 default: 5581 abort (); 5582 } 5583 strcpy (string, branch); 5584 } 5585 spaces -= strlen (branch); 5586 p = strchr (string, '\0'); 5587 5588 /* Now add the annulling, the label, and a possible noop. */ 5589 if (annul && ! far) 5590 { 5591 strcpy (p, ",a"); 5592 p += 2; 5593 spaces -= 2; 5594 } 5595 5596 if (! TARGET_V9) 5597 labelno = ""; 5598 else 5599 { 5600 rtx note; 5601 int v8 = 0; 5602 5603 if (! far && insn && INSN_ADDRESSES_SET_P ()) 5604 { 5605 int delta = (INSN_ADDRESSES (INSN_UID (dest)) 5606 - INSN_ADDRESSES (INSN_UID (insn))); 5607 /* Leave some instructions for "slop". */ 5608 if (delta < -260000 || delta >= 260000) 5609 v8 = 1; 5610 } 5611 5612 if (mode == CCFPmode || mode == CCFPEmode) 5613 { 5614 static char v9_fcc_labelno[] = "%%fccX, "; 5615 /* Set the char indicating the number of the fcc reg to use. */ 5616 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; 5617 labelno = v9_fcc_labelno; 5618 if (v8) 5619 { 5620 if (REGNO (cc_reg) == SPARC_FCC_REG) 5621 labelno = ""; 5622 else 5623 abort (); 5624 } 5625 } 5626 else if (mode == CCXmode || mode == CCX_NOOVmode) 5627 { 5628 labelno = "%%xcc, "; 5629 if (v8) 5630 abort (); 5631 } 5632 else 5633 { 5634 labelno = "%%icc, "; 5635 if (v8) 5636 labelno = ""; 5637 } 5638 5639 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 5640 { 5641 strcpy (p, 5642 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) 5643 ? ",pt" : ",pn"); 5644 p += 3; 5645 spaces -= 3; 5646 } 5647 } 5648 if (spaces > 0) 5649 *p++ = '\t'; 5650 else 5651 *p++ = ' '; 5652 strcpy (p, labelno); 5653 p = strchr (p, '\0'); 5654 if (far) 5655 { 5656 strcpy (p, ".+12\n\tnop\n\tb\t"); 5657 if (annul || noop) 5658 p[3] = '6'; 5659 p += 13; 5660 } 5661 *p++ = '%'; 5662 *p++ = 'l'; 5663 /* Set the char indicating the number of the operand containing the 5664 label_ref. */ 5665 *p++ = label + '0'; 5666 *p = '\0'; 5667 if (noop) 5668 strcpy (p, "\n\tnop"); 5669 5670 return string; 5671} 5672 5673/* Emit a library call comparison between floating point X and Y. 5674 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). 5675 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode 5676 values as arguments instead of the TFmode registers themselves, 5677 that's why we cannot call emit_float_lib_cmp. */ 5678void 5679sparc_emit_float_lib_cmp (x, y, comparison) 5680 rtx x, y; 5681 enum rtx_code comparison; 5682{ 5683 const char *qpfunc; 5684 rtx slot0, slot1, result, tem, tem2; 5685 enum machine_mode mode; 5686 5687 switch (comparison) 5688 { 5689 case EQ: 5690 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; 5691 break; 5692 5693 case NE: 5694 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; 5695 break; 5696 5697 case GT: 5698 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; 5699 break; 5700 5701 case GE: 5702 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; 5703 break; 5704 5705 case LT: 5706 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; 5707 break; 5708 5709 case LE: 5710 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; 5711 break; 5712 5713 case ORDERED: 5714 case UNORDERED: 5715 case UNGT: 5716 case UNLT: 5717 case UNEQ: 5718 case UNGE: 5719 case UNLE: 5720 case LTGT: 5721 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; 5722 break; 5723 5724 default: 5725 abort(); 5726 break; 5727 } 5728 5729 if (TARGET_ARCH64) 5730 { 5731 if (GET_CODE (x) != MEM) 5732 { 5733 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); 5734 emit_insn (gen_rtx_SET (VOIDmode, slot0, x)); 5735 } 5736 else 5737 slot0 = x; 5738 5739 if (GET_CODE (y) != MEM) 5740 { 5741 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); 5742 emit_insn (gen_rtx_SET (VOIDmode, slot1, y)); 5743 } 5744 else 5745 slot1 = y; 5746 5747 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, 5748 DImode, 2, 5749 XEXP (slot0, 0), Pmode, 5750 XEXP (slot1, 0), Pmode); 5751 5752 mode = DImode; 5753 } 5754 else 5755 { 5756 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, 5757 SImode, 2, 5758 x, TFmode, y, TFmode); 5759 5760 mode = SImode; 5761 } 5762 5763 5764 /* Immediately move the result of the libcall into a pseudo 5765 register so reload doesn't clobber the value if it needs 5766 the return register for a spill reg. */ 5767 result = gen_reg_rtx (mode); 5768 emit_move_insn (result, hard_libcall_value (mode)); 5769 5770 switch (comparison) 5771 { 5772 default: 5773 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0); 5774 break; 5775 case ORDERED: 5776 case UNORDERED: 5777 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE, 5778 NULL_RTX, mode, 0); 5779 break; 5780 case UNGT: 5781 case UNGE: 5782 emit_cmp_insn (result, const1_rtx, 5783 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0); 5784 break; 5785 case UNLE: 5786 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0); 5787 break; 5788 case UNLT: 5789 tem = gen_reg_rtx (mode); 5790 if (TARGET_ARCH32) 5791 emit_insn (gen_andsi3 (tem, result, const1_rtx)); 5792 else 5793 emit_insn (gen_anddi3 (tem, result, const1_rtx)); 5794 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0); 5795 break; 5796 case UNEQ: 5797 case LTGT: 5798 tem = gen_reg_rtx (mode); 5799 if (TARGET_ARCH32) 5800 emit_insn (gen_addsi3 (tem, result, const1_rtx)); 5801 else 5802 emit_insn (gen_adddi3 (tem, result, const1_rtx)); 5803 tem2 = gen_reg_rtx (mode); 5804 if (TARGET_ARCH32) 5805 emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); 5806 else 5807 emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); 5808 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE, 5809 NULL_RTX, mode, 0); 5810 break; 5811 } 5812} 5813 5814/* Generate an unsigned DImode to FP conversion. This is the same code 5815 optabs would emit if we didn't have TFmode patterns. */ 5816 5817void 5818sparc_emit_floatunsdi (operands) 5819 rtx operands[2]; 5820{ 5821 rtx neglab, donelab, i0, i1, f0, in, out; 5822 enum machine_mode mode; 5823 5824 out = operands[0]; 5825 in = force_reg (DImode, operands[1]); 5826 mode = GET_MODE (out); 5827 neglab = gen_label_rtx (); 5828 donelab = gen_label_rtx (); 5829 i0 = gen_reg_rtx (DImode); 5830 i1 = gen_reg_rtx (DImode); 5831 f0 = gen_reg_rtx (mode); 5832 5833 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); 5834 5835 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); 5836 emit_jump_insn (gen_jump (donelab)); 5837 emit_barrier (); 5838 5839 emit_label (neglab); 5840 5841 emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); 5842 emit_insn (gen_anddi3 (i1, in, const1_rtx)); 5843 emit_insn (gen_iordi3 (i0, i0, i1)); 5844 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); 5845 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); 5846 5847 emit_label (donelab); 5848} 5849 5850/* Return the string to output a conditional branch to LABEL, testing 5851 register REG. LABEL is the operand number of the label; REG is the 5852 operand number of the reg. OP is the conditional expression. The mode 5853 of REG says what kind of comparison we made. 5854 5855 REVERSED is nonzero if we should reverse the sense of the comparison. 5856 5857 ANNUL is nonzero if we should generate an annulling branch. 5858 5859 NOOP is nonzero if we have to follow this branch by a noop. */ 5860 5861char * 5862output_v9branch (op, dest, reg, label, reversed, annul, noop, insn) 5863 rtx op, dest; 5864 int reg, label; 5865 int reversed, annul, noop; 5866 rtx insn; 5867{ 5868 static char string[50]; 5869 enum rtx_code code = GET_CODE (op); 5870 enum machine_mode mode = GET_MODE (XEXP (op, 0)); 5871 rtx note; 5872 int far; 5873 char *p; 5874 5875 /* branch on register are limited to +-128KB. If it is too far away, 5876 change 5877 5878 brnz,pt %g1, .LC30 5879 5880 to 5881 5882 brz,pn %g1, .+12 5883 nop 5884 ba,pt %xcc, .LC30 5885 5886 and 5887 5888 brgez,a,pn %o1, .LC29 5889 5890 to 5891 5892 brlz,pt %o1, .+16 5893 nop 5894 ba,pt %xcc, .LC29 */ 5895 5896 far = get_attr_length (insn) >= 3; 5897 5898 /* If not floating-point or if EQ or NE, we can just reverse the code. */ 5899 if (reversed ^ far) 5900 code = reverse_condition (code); 5901 5902 /* Only 64 bit versions of these instructions exist. */ 5903 if (mode != DImode) 5904 abort (); 5905 5906 /* Start by writing the branch condition. */ 5907 5908 switch (code) 5909 { 5910 case NE: 5911 strcpy (string, "brnz"); 5912 break; 5913 5914 case EQ: 5915 strcpy (string, "brz"); 5916 break; 5917 5918 case GE: 5919 strcpy (string, "brgez"); 5920 break; 5921 5922 case LT: 5923 strcpy (string, "brlz"); 5924 break; 5925 5926 case LE: 5927 strcpy (string, "brlez"); 5928 break; 5929 5930 case GT: 5931 strcpy (string, "brgz"); 5932 break; 5933 5934 default: 5935 abort (); 5936 } 5937 5938 p = strchr (string, '\0'); 5939 5940 /* Now add the annulling, reg, label, and nop. */ 5941 if (annul && ! far) 5942 { 5943 strcpy (p, ",a"); 5944 p += 2; 5945 } 5946 5947 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 5948 { 5949 strcpy (p, 5950 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) 5951 ? ",pt" : ",pn"); 5952 p += 3; 5953 } 5954 5955 *p = p < string + 8 ? '\t' : ' '; 5956 p++; 5957 *p++ = '%'; 5958 *p++ = '0' + reg; 5959 *p++ = ','; 5960 *p++ = ' '; 5961 if (far) 5962 { 5963 int veryfar = 1, delta; 5964 5965 if (INSN_ADDRESSES_SET_P ()) 5966 { 5967 delta = (INSN_ADDRESSES (INSN_UID (dest)) 5968 - INSN_ADDRESSES (INSN_UID (insn))); 5969 /* Leave some instructions for "slop". */ 5970 if (delta >= -260000 && delta < 260000) 5971 veryfar = 0; 5972 } 5973 5974 strcpy (p, ".+12\n\tnop\n\t"); 5975 if (annul || noop) 5976 p[3] = '6'; 5977 p += 11; 5978 if (veryfar) 5979 { 5980 strcpy (p, "b\t"); 5981 p += 2; 5982 } 5983 else 5984 { 5985 strcpy (p, "ba,pt\t%%xcc, "); 5986 p += 13; 5987 } 5988 } 5989 *p++ = '%'; 5990 *p++ = 'l'; 5991 *p++ = '0' + label; 5992 *p = '\0'; 5993 5994 if (noop) 5995 strcpy (p, "\n\tnop"); 5996 5997 return string; 5998} 5999 6000/* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. 6001 Such instructions cannot be used in the delay slot of return insn on v9. 6002 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. 6003 */ 6004 6005static int 6006epilogue_renumber (where, test) 6007 register rtx *where; 6008 int test; 6009{ 6010 register const char *fmt; 6011 register int i; 6012 register enum rtx_code code; 6013 6014 if (*where == 0) 6015 return 0; 6016 6017 code = GET_CODE (*where); 6018 6019 switch (code) 6020 { 6021 case REG: 6022 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ 6023 return 1; 6024 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) 6025 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); 6026 case SCRATCH: 6027 case CC0: 6028 case PC: 6029 case CONST_INT: 6030 case CONST_DOUBLE: 6031 return 0; 6032 6033 /* Do not replace the frame pointer with the stack pointer because 6034 it can cause the delayed instruction to load below the stack. 6035 This occurs when instructions like: 6036 6037 (set (reg/i:SI 24 %i0) 6038 (mem/f:SI (plus:SI (reg/f:SI 30 %fp) 6039 (const_int -20 [0xffffffec])) 0)) 6040 6041 are in the return delayed slot. */ 6042 case PLUS: 6043 if (GET_CODE (XEXP (*where, 0)) == REG 6044 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM 6045 && (GET_CODE (XEXP (*where, 1)) != CONST_INT 6046 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) 6047 return 1; 6048 break; 6049 6050 case MEM: 6051 if (SPARC_STACK_BIAS 6052 && GET_CODE (XEXP (*where, 0)) == REG 6053 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) 6054 return 1; 6055 break; 6056 6057 default: 6058 break; 6059 } 6060 6061 fmt = GET_RTX_FORMAT (code); 6062 6063 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 6064 { 6065 if (fmt[i] == 'E') 6066 { 6067 register int j; 6068 for (j = XVECLEN (*where, i) - 1; j >= 0; j--) 6069 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) 6070 return 1; 6071 } 6072 else if (fmt[i] == 'e' 6073 && epilogue_renumber (&(XEXP (*where, i)), test)) 6074 return 1; 6075 } 6076 return 0; 6077} 6078 6079/* Leaf functions and non-leaf functions have different needs. */ 6080 6081static const int 6082reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; 6083 6084static const int 6085reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; 6086 6087static const int *const reg_alloc_orders[] = { 6088 reg_leaf_alloc_order, 6089 reg_nonleaf_alloc_order}; 6090 6091void 6092order_regs_for_local_alloc () 6093{ 6094 static int last_order_nonleaf = 1; 6095 6096 if (regs_ever_live[15] != last_order_nonleaf) 6097 { 6098 last_order_nonleaf = !last_order_nonleaf; 6099 memcpy ((char *) reg_alloc_order, 6100 (const char *) reg_alloc_orders[last_order_nonleaf], 6101 FIRST_PSEUDO_REGISTER * sizeof (int)); 6102 } 6103} 6104 6105/* Return 1 if REG and MEM are legitimate enough to allow the various 6106 mem<-->reg splits to be run. */ 6107 6108int 6109sparc_splitdi_legitimate (reg, mem) 6110 rtx reg; 6111 rtx mem; 6112{ 6113 /* Punt if we are here by mistake. */ 6114 if (! reload_completed) 6115 abort (); 6116 6117 /* We must have an offsettable memory reference. */ 6118 if (! offsettable_memref_p (mem)) 6119 return 0; 6120 6121 /* If we have legitimate args for ldd/std, we do not want 6122 the split to happen. */ 6123 if ((REGNO (reg) % 2) == 0 6124 && mem_min_alignment (mem, 8)) 6125 return 0; 6126 6127 /* Success. */ 6128 return 1; 6129} 6130 6131/* Return 1 if x and y are some kind of REG and they refer to 6132 different hard registers. This test is guarenteed to be 6133 run after reload. */ 6134 6135int 6136sparc_absnegfloat_split_legitimate (x, y) 6137 rtx x, y; 6138{ 6139 if (GET_CODE (x) != REG) 6140 return 0; 6141 if (GET_CODE (y) != REG) 6142 return 0; 6143 if (REGNO (x) == REGNO (y)) 6144 return 0; 6145 return 1; 6146} 6147 6148/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. 6149 This makes them candidates for using ldd and std insns. 6150 6151 Note reg1 and reg2 *must* be hard registers. */ 6152 6153int 6154registers_ok_for_ldd_peep (reg1, reg2) 6155 rtx reg1, reg2; 6156{ 6157 /* We might have been passed a SUBREG. */ 6158 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 6159 return 0; 6160 6161 if (REGNO (reg1) % 2 != 0) 6162 return 0; 6163 6164 /* Integer ldd is deprecated in SPARC V9 */ 6165 if (TARGET_V9 && REGNO (reg1) < 32) 6166 return 0; 6167 6168 return (REGNO (reg1) == REGNO (reg2) - 1); 6169} 6170 6171/* Return 1 if the addresses in mem1 and mem2 are suitable for use in 6172 an ldd or std insn. 6173 6174 This can only happen when addr1 and addr2, the addresses in mem1 6175 and mem2, are consecutive memory locations (addr1 + 4 == addr2). 6176 addr1 must also be aligned on a 64-bit boundary. 6177 6178 Also iff dependent_reg_rtx is not null it should not be used to 6179 compute the address for mem1, i.e. we cannot optimize a sequence 6180 like: 6181 ld [%o0], %o0 6182 ld [%o0 + 4], %o1 6183 to 6184 ldd [%o0], %o0 6185 nor: 6186 ld [%g3 + 4], %g3 6187 ld [%g3], %g2 6188 to 6189 ldd [%g3], %g2 6190 6191 But, note that the transformation from: 6192 ld [%g2 + 4], %g3 6193 ld [%g2], %g2 6194 to 6195 ldd [%g2], %g2 6196 is perfectly fine. Thus, the peephole2 patterns always pass us 6197 the destination register of the first load, never the second one. 6198 6199 For stores we don't have a similar problem, so dependent_reg_rtx is 6200 NULL_RTX. */ 6201 6202int 6203mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx) 6204 rtx mem1, mem2, dependent_reg_rtx; 6205{ 6206 rtx addr1, addr2; 6207 unsigned int reg1; 6208 int offset1; 6209 6210 /* The mems cannot be volatile. */ 6211 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) 6212 return 0; 6213 6214 /* MEM1 should be aligned on a 64-bit boundary. */ 6215 if (MEM_ALIGN (mem1) < 64) 6216 return 0; 6217 6218 addr1 = XEXP (mem1, 0); 6219 addr2 = XEXP (mem2, 0); 6220 6221 /* Extract a register number and offset (if used) from the first addr. */ 6222 if (GET_CODE (addr1) == PLUS) 6223 { 6224 /* If not a REG, return zero. */ 6225 if (GET_CODE (XEXP (addr1, 0)) != REG) 6226 return 0; 6227 else 6228 { 6229 reg1 = REGNO (XEXP (addr1, 0)); 6230 /* The offset must be constant! */ 6231 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) 6232 return 0; 6233 offset1 = INTVAL (XEXP (addr1, 1)); 6234 } 6235 } 6236 else if (GET_CODE (addr1) != REG) 6237 return 0; 6238 else 6239 { 6240 reg1 = REGNO (addr1); 6241 /* This was a simple (mem (reg)) expression. Offset is 0. */ 6242 offset1 = 0; 6243 } 6244 6245 /* Make sure the second address is a (mem (plus (reg) (const_int). */ 6246 if (GET_CODE (addr2) != PLUS) 6247 return 0; 6248 6249 if (GET_CODE (XEXP (addr2, 0)) != REG 6250 || GET_CODE (XEXP (addr2, 1)) != CONST_INT) 6251 return 0; 6252 6253 if (reg1 != REGNO (XEXP (addr2, 0))) 6254 return 0; 6255 6256 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) 6257 return 0; 6258 6259 /* The first offset must be evenly divisible by 8 to ensure the 6260 address is 64 bit aligned. */ 6261 if (offset1 % 8 != 0) 6262 return 0; 6263 6264 /* The offset for the second addr must be 4 more than the first addr. */ 6265 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) 6266 return 0; 6267 6268 /* All the tests passed. addr1 and addr2 are valid for ldd and std 6269 instructions. */ 6270 return 1; 6271} 6272 6273/* Return 1 if reg is a pseudo, or is the first register in 6274 a hard register pair. This makes it a candidate for use in 6275 ldd and std insns. */ 6276 6277int 6278register_ok_for_ldd (reg) 6279 rtx reg; 6280{ 6281 /* We might have been passed a SUBREG. */ 6282 if (GET_CODE (reg) != REG) 6283 return 0; 6284 6285 if (REGNO (reg) < FIRST_PSEUDO_REGISTER) 6286 return (REGNO (reg) % 2 == 0); 6287 else 6288 return 1; 6289} 6290 6291/* Print operand X (an rtx) in assembler syntax to file FILE. 6292 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 6293 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 6294 6295void 6296print_operand (file, x, code) 6297 FILE *file; 6298 rtx x; 6299 int code; 6300{ 6301 switch (code) 6302 { 6303 case '#': 6304 /* Output a 'nop' if there's nothing for the delay slot. */ 6305 if (dbr_sequence_length () == 0) 6306 fputs ("\n\t nop", file); 6307 return; 6308 case '*': 6309 /* Output an annul flag if there's nothing for the delay slot and we 6310 are optimizing. This is always used with '(' below. */ 6311 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; 6312 this is a dbx bug. So, we only do this when optimizing. */ 6313 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. 6314 Always emit a nop in case the next instruction is a branch. */ 6315 if (dbr_sequence_length () == 0 6316 && (optimize && (int)sparc_cpu < PROCESSOR_V9)) 6317 fputs (",a", file); 6318 return; 6319 case '(': 6320 /* Output a 'nop' if there's nothing for the delay slot and we are 6321 not optimizing. This is always used with '*' above. */ 6322 if (dbr_sequence_length () == 0 6323 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) 6324 fputs ("\n\t nop", file); 6325 return; 6326 case '_': 6327 /* Output the Embedded Medium/Anywhere code model base register. */ 6328 fputs (EMBMEDANY_BASE_REG, file); 6329 return; 6330 case '@': 6331 /* Print out what we are using as the frame pointer. This might 6332 be %fp, or might be %sp+offset. */ 6333 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ 6334 fprintf (file, "%s+%d", frame_base_name, frame_base_offset); 6335 return; 6336 case 'Y': 6337 /* Adjust the operand to take into account a RESTORE operation. */ 6338 if (GET_CODE (x) == CONST_INT) 6339 break; 6340 else if (GET_CODE (x) != REG) 6341 output_operand_lossage ("invalid %%Y operand"); 6342 else if (REGNO (x) < 8) 6343 fputs (reg_names[REGNO (x)], file); 6344 else if (REGNO (x) >= 24 && REGNO (x) < 32) 6345 fputs (reg_names[REGNO (x)-16], file); 6346 else 6347 output_operand_lossage ("invalid %%Y operand"); 6348 return; 6349 case 'L': 6350 /* Print out the low order register name of a register pair. */ 6351 if (WORDS_BIG_ENDIAN) 6352 fputs (reg_names[REGNO (x)+1], file); 6353 else 6354 fputs (reg_names[REGNO (x)], file); 6355 return; 6356 case 'H': 6357 /* Print out the high order register name of a register pair. */ 6358 if (WORDS_BIG_ENDIAN) 6359 fputs (reg_names[REGNO (x)], file); 6360 else 6361 fputs (reg_names[REGNO (x)+1], file); 6362 return; 6363 case 'R': 6364 /* Print out the second register name of a register pair or quad. 6365 I.e., R (%o0) => %o1. */ 6366 fputs (reg_names[REGNO (x)+1], file); 6367 return; 6368 case 'S': 6369 /* Print out the third register name of a register quad. 6370 I.e., S (%o0) => %o2. */ 6371 fputs (reg_names[REGNO (x)+2], file); 6372 return; 6373 case 'T': 6374 /* Print out the fourth register name of a register quad. 6375 I.e., T (%o0) => %o3. */ 6376 fputs (reg_names[REGNO (x)+3], file); 6377 return; 6378 case 'x': 6379 /* Print a condition code register. */ 6380 if (REGNO (x) == SPARC_ICC_REG) 6381 { 6382 /* We don't handle CC[X]_NOOVmode because they're not supposed 6383 to occur here. */ 6384 if (GET_MODE (x) == CCmode) 6385 fputs ("%icc", file); 6386 else if (GET_MODE (x) == CCXmode) 6387 fputs ("%xcc", file); 6388 else 6389 abort (); 6390 } 6391 else 6392 /* %fccN register */ 6393 fputs (reg_names[REGNO (x)], file); 6394 return; 6395 case 'm': 6396 /* Print the operand's address only. */ 6397 output_address (XEXP (x, 0)); 6398 return; 6399 case 'r': 6400 /* In this case we need a register. Use %g0 if the 6401 operand is const0_rtx. */ 6402 if (x == const0_rtx 6403 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) 6404 { 6405 fputs ("%g0", file); 6406 return; 6407 } 6408 else 6409 break; 6410 6411 case 'A': 6412 switch (GET_CODE (x)) 6413 { 6414 case IOR: fputs ("or", file); break; 6415 case AND: fputs ("and", file); break; 6416 case XOR: fputs ("xor", file); break; 6417 default: output_operand_lossage ("invalid %%A operand"); 6418 } 6419 return; 6420 6421 case 'B': 6422 switch (GET_CODE (x)) 6423 { 6424 case IOR: fputs ("orn", file); break; 6425 case AND: fputs ("andn", file); break; 6426 case XOR: fputs ("xnor", file); break; 6427 default: output_operand_lossage ("invalid %%B operand"); 6428 } 6429 return; 6430 6431 /* These are used by the conditional move instructions. */ 6432 case 'c' : 6433 case 'C': 6434 { 6435 enum rtx_code rc = GET_CODE (x); 6436 6437 if (code == 'c') 6438 { 6439 enum machine_mode mode = GET_MODE (XEXP (x, 0)); 6440 if (mode == CCFPmode || mode == CCFPEmode) 6441 rc = reverse_condition_maybe_unordered (GET_CODE (x)); 6442 else 6443 rc = reverse_condition (GET_CODE (x)); 6444 } 6445 switch (rc) 6446 { 6447 case NE: fputs ("ne", file); break; 6448 case EQ: fputs ("e", file); break; 6449 case GE: fputs ("ge", file); break; 6450 case GT: fputs ("g", file); break; 6451 case LE: fputs ("le", file); break; 6452 case LT: fputs ("l", file); break; 6453 case GEU: fputs ("geu", file); break; 6454 case GTU: fputs ("gu", file); break; 6455 case LEU: fputs ("leu", file); break; 6456 case LTU: fputs ("lu", file); break; 6457 case LTGT: fputs ("lg", file); break; 6458 case UNORDERED: fputs ("u", file); break; 6459 case ORDERED: fputs ("o", file); break; 6460 case UNLT: fputs ("ul", file); break; 6461 case UNLE: fputs ("ule", file); break; 6462 case UNGT: fputs ("ug", file); break; 6463 case UNGE: fputs ("uge", file); break; 6464 case UNEQ: fputs ("ue", file); break; 6465 default: output_operand_lossage (code == 'c' 6466 ? "invalid %%c operand" 6467 : "invalid %%C operand"); 6468 } 6469 return; 6470 } 6471 6472 /* These are used by the movr instruction pattern. */ 6473 case 'd': 6474 case 'D': 6475 { 6476 enum rtx_code rc = (code == 'd' 6477 ? reverse_condition (GET_CODE (x)) 6478 : GET_CODE (x)); 6479 switch (rc) 6480 { 6481 case NE: fputs ("ne", file); break; 6482 case EQ: fputs ("e", file); break; 6483 case GE: fputs ("gez", file); break; 6484 case LT: fputs ("lz", file); break; 6485 case LE: fputs ("lez", file); break; 6486 case GT: fputs ("gz", file); break; 6487 default: output_operand_lossage (code == 'd' 6488 ? "invalid %%d operand" 6489 : "invalid %%D operand"); 6490 } 6491 return; 6492 } 6493 6494 case 'b': 6495 { 6496 /* Print a sign-extended character. */ 6497 int i = trunc_int_for_mode (INTVAL (x), QImode); 6498 fprintf (file, "%d", i); 6499 return; 6500 } 6501 6502 case 'f': 6503 /* Operand must be a MEM; write its address. */ 6504 if (GET_CODE (x) != MEM) 6505 output_operand_lossage ("invalid %%f operand"); 6506 output_address (XEXP (x, 0)); 6507 return; 6508 6509 case 's': 6510 { 6511 /* Print a sign-extended 32-bit value. */ 6512 HOST_WIDE_INT i; 6513 if (GET_CODE(x) == CONST_INT) 6514 i = INTVAL (x); 6515 else if (GET_CODE(x) == CONST_DOUBLE) 6516 i = CONST_DOUBLE_LOW (x); 6517 else 6518 { 6519 output_operand_lossage ("invalid %%s operand"); 6520 return; 6521 } 6522 i = trunc_int_for_mode (i, SImode); 6523 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); 6524 return; 6525 } 6526 6527 case 0: 6528 /* Do nothing special. */ 6529 break; 6530 6531 default: 6532 /* Undocumented flag. */ 6533 output_operand_lossage ("invalid operand output code"); 6534 } 6535 6536 if (GET_CODE (x) == REG) 6537 fputs (reg_names[REGNO (x)], file); 6538 else if (GET_CODE (x) == MEM) 6539 { 6540 fputc ('[', file); 6541 /* Poor Sun assembler doesn't understand absolute addressing. */ 6542 if (CONSTANT_P (XEXP (x, 0))) 6543 fputs ("%g0+", file); 6544 output_address (XEXP (x, 0)); 6545 fputc (']', file); 6546 } 6547 else if (GET_CODE (x) == HIGH) 6548 { 6549 fputs ("%hi(", file); 6550 output_addr_const (file, XEXP (x, 0)); 6551 fputc (')', file); 6552 } 6553 else if (GET_CODE (x) == LO_SUM) 6554 { 6555 print_operand (file, XEXP (x, 0), 0); 6556 if (TARGET_CM_MEDMID) 6557 fputs ("+%l44(", file); 6558 else 6559 fputs ("+%lo(", file); 6560 output_addr_const (file, XEXP (x, 1)); 6561 fputc (')', file); 6562 } 6563 else if (GET_CODE (x) == CONST_DOUBLE 6564 && (GET_MODE (x) == VOIDmode 6565 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) 6566 { 6567 if (CONST_DOUBLE_HIGH (x) == 0) 6568 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); 6569 else if (CONST_DOUBLE_HIGH (x) == -1 6570 && CONST_DOUBLE_LOW (x) < 0) 6571 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); 6572 else 6573 output_operand_lossage ("long long constant not a valid immediate operand"); 6574 } 6575 else if (GET_CODE (x) == CONST_DOUBLE) 6576 output_operand_lossage ("floating point constant not a valid immediate operand"); 6577 else { output_addr_const (file, x); } 6578} 6579 6580/* Target hook for assembling integer objects. The sparc version has 6581 special handling for aligned DI-mode objects. */ 6582 6583static bool 6584sparc_assemble_integer (x, size, aligned_p) 6585 rtx x; 6586 unsigned int size; 6587 int aligned_p; 6588{ 6589 /* ??? We only output .xword's for symbols and only then in environments 6590 where the assembler can handle them. */ 6591 if (aligned_p && size == 8 6592 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE)) 6593 { 6594 if (TARGET_V9) 6595 { 6596 assemble_integer_with_op ("\t.xword\t", x); 6597 return true; 6598 } 6599 else 6600 { 6601 assemble_aligned_integer (4, const0_rtx); 6602 assemble_aligned_integer (4, x); 6603 return true; 6604 } 6605 } 6606 return default_assemble_integer (x, size, aligned_p); 6607} 6608 6609/* Return the value of a code used in the .proc pseudo-op that says 6610 what kind of result this function returns. For non-C types, we pick 6611 the closest C type. */ 6612 6613#ifndef SHORT_TYPE_SIZE 6614#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) 6615#endif 6616 6617#ifndef INT_TYPE_SIZE 6618#define INT_TYPE_SIZE BITS_PER_WORD 6619#endif 6620 6621#ifndef LONG_TYPE_SIZE 6622#define LONG_TYPE_SIZE BITS_PER_WORD 6623#endif 6624 6625#ifndef LONG_LONG_TYPE_SIZE 6626#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) 6627#endif 6628 6629#ifndef FLOAT_TYPE_SIZE 6630#define FLOAT_TYPE_SIZE BITS_PER_WORD 6631#endif 6632 6633#ifndef DOUBLE_TYPE_SIZE 6634#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 6635#endif 6636 6637#ifndef LONG_DOUBLE_TYPE_SIZE 6638#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 6639#endif 6640 6641unsigned long 6642sparc_type_code (type) 6643 register tree type; 6644{ 6645 register unsigned long qualifiers = 0; 6646 register unsigned shift; 6647 6648 /* Only the first 30 bits of the qualifier are valid. We must refrain from 6649 setting more, since some assemblers will give an error for this. Also, 6650 we must be careful to avoid shifts of 32 bits or more to avoid getting 6651 unpredictable results. */ 6652 6653 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) 6654 { 6655 switch (TREE_CODE (type)) 6656 { 6657 case ERROR_MARK: 6658 return qualifiers; 6659 6660 case ARRAY_TYPE: 6661 qualifiers |= (3 << shift); 6662 break; 6663 6664 case FUNCTION_TYPE: 6665 case METHOD_TYPE: 6666 qualifiers |= (2 << shift); 6667 break; 6668 6669 case POINTER_TYPE: 6670 case REFERENCE_TYPE: 6671 case OFFSET_TYPE: 6672 qualifiers |= (1 << shift); 6673 break; 6674 6675 case RECORD_TYPE: 6676 return (qualifiers | 8); 6677 6678 case UNION_TYPE: 6679 case QUAL_UNION_TYPE: 6680 return (qualifiers | 9); 6681 6682 case ENUMERAL_TYPE: 6683 return (qualifiers | 10); 6684 6685 case VOID_TYPE: 6686 return (qualifiers | 16); 6687 6688 case INTEGER_TYPE: 6689 /* If this is a range type, consider it to be the underlying 6690 type. */ 6691 if (TREE_TYPE (type) != 0) 6692 break; 6693 6694 /* Carefully distinguish all the standard types of C, 6695 without messing up if the language is not C. We do this by 6696 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to 6697 look at both the names and the above fields, but that's redundant. 6698 Any type whose size is between two C types will be considered 6699 to be the wider of the two types. Also, we do not have a 6700 special code to use for "long long", so anything wider than 6701 long is treated the same. Note that we can't distinguish 6702 between "int" and "long" in this code if they are the same 6703 size, but that's fine, since neither can the assembler. */ 6704 6705 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) 6706 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); 6707 6708 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) 6709 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); 6710 6711 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) 6712 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); 6713 6714 else 6715 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); 6716 6717 case REAL_TYPE: 6718 /* If this is a range type, consider it to be the underlying 6719 type. */ 6720 if (TREE_TYPE (type) != 0) 6721 break; 6722 6723 /* Carefully distinguish all the standard types of C, 6724 without messing up if the language is not C. */ 6725 6726 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) 6727 return (qualifiers | 6); 6728 6729 else 6730 return (qualifiers | 7); 6731 6732 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ 6733 /* ??? We need to distinguish between double and float complex types, 6734 but I don't know how yet because I can't reach this code from 6735 existing front-ends. */ 6736 return (qualifiers | 7); /* Who knows? */ 6737 6738 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ 6739 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ 6740 case FILE_TYPE: /* GNU Pascal FILE type. */ 6741 case SET_TYPE: /* GNU Pascal SET type. */ 6742 case LANG_TYPE: /* ? */ 6743 return qualifiers; 6744 6745 default: 6746 abort (); /* Not a type! */ 6747 } 6748 } 6749 6750 return qualifiers; 6751} 6752 6753/* Nested function support. */ 6754 6755/* Emit RTL insns to initialize the variable parts of a trampoline. 6756 FNADDR is an RTX for the address of the function's pure code. 6757 CXT is an RTX for the static chain value for the function. 6758 6759 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi 6760 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes 6761 (to store insns). This is a bit excessive. Perhaps a different 6762 mechanism would be better here. 6763 6764 Emit enough FLUSH insns to synchronize the data and instruction caches. */ 6765 6766void 6767sparc_initialize_trampoline (tramp, fnaddr, cxt) 6768 rtx tramp, fnaddr, cxt; 6769{ 6770 /* SPARC 32 bit trampoline: 6771 6772 sethi %hi(fn), %g1 6773 sethi %hi(static), %g2 6774 jmp %g1+%lo(fn) 6775 or %g2, %lo(static), %g2 6776 6777 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii 6778 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii 6779 */ 6780#ifdef TRANSFER_FROM_TRAMPOLINE 6781 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), 6782 LCT_NORMAL, VOIDmode, 1, tramp, Pmode); 6783#endif 6784 6785 emit_move_insn 6786 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), 6787 expand_binop (SImode, ior_optab, 6788 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 6789 size_int (10), 0, 1), 6790 GEN_INT (trunc_int_for_mode (0x03000000, SImode)), 6791 NULL_RTX, 1, OPTAB_DIRECT)); 6792 6793 emit_move_insn 6794 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), 6795 expand_binop (SImode, ior_optab, 6796 expand_shift (RSHIFT_EXPR, SImode, cxt, 6797 size_int (10), 0, 1), 6798 GEN_INT (trunc_int_for_mode (0x05000000, SImode)), 6799 NULL_RTX, 1, OPTAB_DIRECT)); 6800 6801 emit_move_insn 6802 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), 6803 expand_binop (SImode, ior_optab, 6804 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), 6805 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), 6806 NULL_RTX, 1, OPTAB_DIRECT)); 6807 6808 emit_move_insn 6809 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), 6810 expand_binop (SImode, ior_optab, 6811 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), 6812 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), 6813 NULL_RTX, 1, OPTAB_DIRECT)); 6814 6815 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is 6816 aligned on a 16 byte boundary so one flush clears it all. */ 6817 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); 6818 if (sparc_cpu != PROCESSOR_ULTRASPARC 6819 && sparc_cpu != PROCESSOR_ULTRASPARC3) 6820 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, 6821 plus_constant (tramp, 8))))); 6822} 6823 6824/* The 64 bit version is simpler because it makes more sense to load the 6825 values as "immediate" data out of the trampoline. It's also easier since 6826 we can read the PC without clobbering a register. */ 6827 6828void 6829sparc64_initialize_trampoline (tramp, fnaddr, cxt) 6830 rtx tramp, fnaddr, cxt; 6831{ 6832#ifdef TRANSFER_FROM_TRAMPOLINE 6833 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), 6834 LCT_NORMAL, VOIDmode, 1, tramp, Pmode); 6835#endif 6836 6837 /* 6838 rd %pc, %g1 6839 ldx [%g1+24], %g5 6840 jmp %g5 6841 ldx [%g1+16], %g5 6842 +16 bytes data 6843 */ 6844 6845 emit_move_insn (gen_rtx_MEM (SImode, tramp), 6846 GEN_INT (trunc_int_for_mode (0x83414000, SImode))); 6847 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), 6848 GEN_INT (trunc_int_for_mode (0xca586018, SImode))); 6849 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), 6850 GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); 6851 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), 6852 GEN_INT (trunc_int_for_mode (0xca586010, SImode))); 6853 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); 6854 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); 6855 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); 6856 6857 if (sparc_cpu != PROCESSOR_ULTRASPARC 6858 && sparc_cpu != PROCESSOR_ULTRASPARC3) 6859 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); 6860} 6861 6862/* Subroutines to support a flat (single) register window calling 6863 convention. */ 6864 6865/* Single-register window sparc stack frames look like: 6866 6867 Before call After call 6868 +-----------------------+ +-----------------------+ 6869 high | | | | 6870 mem | caller's temps. | | caller's temps. | 6871 | | | | 6872 +-----------------------+ +-----------------------+ 6873 | | | | 6874 | arguments on stack. | | arguments on stack. | 6875 | | | | 6876 +-----------------------+FP+92->+-----------------------+ 6877 | 6 words to save | | 6 words to save | 6878 | arguments passed | | arguments passed | 6879 | in registers, even | | in registers, even | 6880 | if not passed. | | if not passed. | 6881 SP+68->+-----------------------+FP+68->+-----------------------+ 6882 | 1 word struct addr | | 1 word struct addr | 6883 +-----------------------+FP+64->+-----------------------+ 6884 | | | | 6885 | 16 word reg save area | | 16 word reg save area | 6886 | | | | 6887 SP->+-----------------------+ FP->+-----------------------+ 6888 | 4 word area for | 6889 | fp/alu reg moves | 6890 FP-16->+-----------------------+ 6891 | | 6892 | local variables | 6893 | | 6894 +-----------------------+ 6895 | | 6896 | fp register save | 6897 | | 6898 +-----------------------+ 6899 | | 6900 | gp register save | 6901 | | 6902 +-----------------------+ 6903 | | 6904 | alloca allocations | 6905 | | 6906 +-----------------------+ 6907 | | 6908 | arguments on stack | 6909 | | 6910 SP+92->+-----------------------+ 6911 | 6 words to save | 6912 | arguments passed | 6913 | in registers, even | 6914 low | if not passed. | 6915 memory SP+68->+-----------------------+ 6916 | 1 word struct addr | 6917 SP+64->+-----------------------+ 6918 | | 6919 I 16 word reg save area | 6920 | | 6921 SP->+-----------------------+ */ 6922 6923/* Structure to be filled in by sparc_flat_compute_frame_size with register 6924 save masks, and offsets for the current function. */ 6925 6926struct sparc_frame_info 6927{ 6928 unsigned long total_size; /* # bytes that the entire frame takes up. */ 6929 unsigned long var_size; /* # bytes that variables take up. */ 6930 unsigned long args_size; /* # bytes that outgoing arguments take up. */ 6931 unsigned long extra_size; /* # bytes of extra gunk. */ 6932 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ 6933 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ 6934 unsigned long gmask; /* Mask of saved gp registers. */ 6935 unsigned long fmask; /* Mask of saved fp registers. */ 6936 unsigned long reg_offset; /* Offset from new sp to store regs. */ 6937 int initialized; /* Nonzero if frame size already calculated. */ 6938}; 6939 6940/* Current frame information calculated by sparc_flat_compute_frame_size. */ 6941struct sparc_frame_info current_frame_info; 6942 6943/* Zero structure to initialize current_frame_info. */ 6944struct sparc_frame_info zero_frame_info; 6945 6946/* Tell prologue and epilogue if register REGNO should be saved / restored. */ 6947 6948#define RETURN_ADDR_REGNUM 15 6949#define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM)) 6950#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) 6951 6952#define MUST_SAVE_REGISTER(regno) \ 6953 ((regs_ever_live[regno] && !call_used_regs[regno]) \ 6954 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \ 6955 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) 6956 6957/* Return the bytes needed to compute the frame pointer from the current 6958 stack pointer. */ 6959 6960unsigned long 6961sparc_flat_compute_frame_size (size) 6962 int size; /* # of var. bytes allocated. */ 6963{ 6964 int regno; 6965 unsigned long total_size; /* # bytes that the entire frame takes up. */ 6966 unsigned long var_size; /* # bytes that variables take up. */ 6967 unsigned long args_size; /* # bytes that outgoing arguments take up. */ 6968 unsigned long extra_size; /* # extra bytes. */ 6969 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ 6970 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ 6971 unsigned long gmask; /* Mask of saved gp registers. */ 6972 unsigned long fmask; /* Mask of saved fp registers. */ 6973 unsigned long reg_offset; /* Offset to register save area. */ 6974 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ 6975 6976 /* This is the size of the 16 word reg save area, 1 word struct addr 6977 area, and 4 word fp/alu register copy area. */ 6978 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); 6979 var_size = size; 6980 gp_reg_size = 0; 6981 fp_reg_size = 0; 6982 gmask = 0; 6983 fmask = 0; 6984 reg_offset = 0; 6985 need_aligned_p = 0; 6986 6987 args_size = 0; 6988 if (!leaf_function_p ()) 6989 { 6990 /* Also include the size needed for the 6 parameter registers. */ 6991 args_size = current_function_outgoing_args_size + 24; 6992 } 6993 total_size = var_size + args_size; 6994 6995 /* Calculate space needed for gp registers. */ 6996 for (regno = 1; regno <= 31; regno++) 6997 { 6998 if (MUST_SAVE_REGISTER (regno)) 6999 { 7000 /* If we need to save two regs in a row, ensure there's room to bump 7001 up the address to align it to a doubleword boundary. */ 7002 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) 7003 { 7004 if (gp_reg_size % 8 != 0) 7005 gp_reg_size += 4; 7006 gp_reg_size += 2 * UNITS_PER_WORD; 7007 gmask |= 3 << regno; 7008 regno++; 7009 need_aligned_p = 1; 7010 } 7011 else 7012 { 7013 gp_reg_size += UNITS_PER_WORD; 7014 gmask |= 1 << regno; 7015 } 7016 } 7017 } 7018 7019 /* Calculate space needed for fp registers. */ 7020 for (regno = 32; regno <= 63; regno++) 7021 { 7022 if (regs_ever_live[regno] && !call_used_regs[regno]) 7023 { 7024 fp_reg_size += UNITS_PER_WORD; 7025 fmask |= 1 << (regno - 32); 7026 } 7027 } 7028 7029 if (gmask || fmask) 7030 { 7031 int n; 7032 reg_offset = FIRST_PARM_OFFSET(0) + args_size; 7033 /* Ensure save area is 8 byte aligned if we need it. */ 7034 n = reg_offset % 8; 7035 if (need_aligned_p && n != 0) 7036 { 7037 total_size += 8 - n; 7038 reg_offset += 8 - n; 7039 } 7040 total_size += gp_reg_size + fp_reg_size; 7041 } 7042 7043 /* If we must allocate a stack frame at all, we must also allocate 7044 room for register window spillage, so as to be binary compatible 7045 with libraries and operating systems that do not use -mflat. */ 7046 if (total_size > 0) 7047 total_size += extra_size; 7048 else 7049 extra_size = 0; 7050 7051 total_size = SPARC_STACK_ALIGN (total_size); 7052 7053 /* Save other computed information. */ 7054 current_frame_info.total_size = total_size; 7055 current_frame_info.var_size = var_size; 7056 current_frame_info.args_size = args_size; 7057 current_frame_info.extra_size = extra_size; 7058 current_frame_info.gp_reg_size = gp_reg_size; 7059 current_frame_info.fp_reg_size = fp_reg_size; 7060 current_frame_info.gmask = gmask; 7061 current_frame_info.fmask = fmask; 7062 current_frame_info.reg_offset = reg_offset; 7063 current_frame_info.initialized = reload_completed; 7064 7065 /* Ok, we're done. */ 7066 return total_size; 7067} 7068 7069/* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset 7070 OFFSET. 7071 7072 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for 7073 appropriate alignment and use DOUBLEWORD_OP when we can. We assume 7074 [BASE_REG+OFFSET] will always be a valid address. 7075 7076 WORD_OP is either "st" for save, "ld" for restore. 7077 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ 7078 7079void 7080sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, 7081 doubleword_op, base_offset) 7082 FILE *file; 7083 const char *base_reg; 7084 unsigned int offset; 7085 unsigned long gmask; 7086 unsigned long fmask; 7087 const char *word_op; 7088 const char *doubleword_op; 7089 unsigned long base_offset; 7090{ 7091 int regno; 7092 7093 if (gmask == 0 && fmask == 0) 7094 return; 7095 7096 /* Save registers starting from high to low. We've already saved the 7097 previous frame pointer and previous return address for the debugger's 7098 sake. The debugger allows us to not need a nop in the epilog if at least 7099 one register is reloaded in addition to return address. */ 7100 7101 if (gmask) 7102 { 7103 for (regno = 1; regno <= 31; regno++) 7104 { 7105 if ((gmask & (1L << regno)) != 0) 7106 { 7107 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) 7108 { 7109 /* We can save two registers in a row. If we're not at a 7110 double word boundary, move to one. 7111 sparc_flat_compute_frame_size ensures there's room to do 7112 this. */ 7113 if (offset % 8 != 0) 7114 offset += UNITS_PER_WORD; 7115 7116 if (word_op[0] == 's') 7117 { 7118 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7119 doubleword_op, reg_names[regno], 7120 base_reg, offset); 7121 if (dwarf2out_do_frame ()) 7122 { 7123 char *l = dwarf2out_cfi_label (); 7124 dwarf2out_reg_save (l, regno, offset + base_offset); 7125 dwarf2out_reg_save 7126 (l, regno+1, offset+base_offset + UNITS_PER_WORD); 7127 } 7128 } 7129 else 7130 fprintf (file, "\t%s\t[%s+%d], %s\n", 7131 doubleword_op, base_reg, offset, 7132 reg_names[regno]); 7133 7134 offset += 2 * UNITS_PER_WORD; 7135 regno++; 7136 } 7137 else 7138 { 7139 if (word_op[0] == 's') 7140 { 7141 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7142 word_op, reg_names[regno], 7143 base_reg, offset); 7144 if (dwarf2out_do_frame ()) 7145 dwarf2out_reg_save ("", regno, offset + base_offset); 7146 } 7147 else 7148 fprintf (file, "\t%s\t[%s+%d], %s\n", 7149 word_op, base_reg, offset, reg_names[regno]); 7150 7151 offset += UNITS_PER_WORD; 7152 } 7153 } 7154 } 7155 } 7156 7157 if (fmask) 7158 { 7159 for (regno = 32; regno <= 63; regno++) 7160 { 7161 if ((fmask & (1L << (regno - 32))) != 0) 7162 { 7163 if (word_op[0] == 's') 7164 { 7165 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7166 word_op, reg_names[regno], 7167 base_reg, offset); 7168 if (dwarf2out_do_frame ()) 7169 dwarf2out_reg_save ("", regno, offset + base_offset); 7170 } 7171 else 7172 fprintf (file, "\t%s\t[%s+%d], %s\n", 7173 word_op, base_reg, offset, reg_names[regno]); 7174 7175 offset += UNITS_PER_WORD; 7176 } 7177 } 7178 } 7179} 7180 7181/* Set up the stack and frame (if desired) for the function. */ 7182 7183static void 7184sparc_flat_function_prologue (file, size) 7185 FILE *file; 7186 HOST_WIDE_INT size; 7187{ 7188 const char *sp_str = reg_names[STACK_POINTER_REGNUM]; 7189 unsigned long gmask = current_frame_info.gmask; 7190 7191 sparc_output_scratch_registers (file); 7192 7193 /* This is only for the human reader. */ 7194 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); 7195 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", 7196 ASM_COMMENT_START, 7197 current_frame_info.var_size, 7198 current_frame_info.gp_reg_size / 4, 7199 current_frame_info.fp_reg_size / 4, 7200 current_function_outgoing_args_size, 7201 current_frame_info.extra_size); 7202 7203 size = SPARC_STACK_ALIGN (size); 7204 size = (! current_frame_info.initialized 7205 ? sparc_flat_compute_frame_size (size) 7206 : current_frame_info.total_size); 7207 7208 /* These cases shouldn't happen. Catch them now. */ 7209 if (size == 0 && (gmask || current_frame_info.fmask)) 7210 abort (); 7211 7212 /* Allocate our stack frame by decrementing %sp. 7213 At present, the only algorithm gdb can use to determine if this is a 7214 flat frame is if we always set %i7 if we set %sp. This can be optimized 7215 in the future by putting in some sort of debugging information that says 7216 this is a `flat' function. However, there is still the case of debugging 7217 code without such debugging information (including cases where most fns 7218 have such info, but there is one that doesn't). So, always do this now 7219 so we don't get a lot of code out there that gdb can't handle. 7220 If the frame pointer isn't needn't then that's ok - gdb won't be able to 7221 distinguish us from a non-flat function but there won't (and shouldn't) 7222 be any differences anyway. The return pc is saved (if necessary) right 7223 after %i7 so gdb won't have to look too far to find it. */ 7224 if (size > 0) 7225 { 7226 unsigned int reg_offset = current_frame_info.reg_offset; 7227 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; 7228 static const char *const t1_str = "%g1"; 7229 7230 /* Things get a little tricky if local variables take up more than ~4096 7231 bytes and outgoing arguments take up more than ~4096 bytes. When that 7232 happens, the register save area can't be accessed from either end of 7233 the frame. Handle this by decrementing %sp to the start of the gp 7234 register save area, save the regs, update %i7, and then set %sp to its 7235 final value. Given that we only have one scratch register to play 7236 with it is the cheapest solution, and it helps gdb out as it won't 7237 slow down recognition of flat functions. 7238 Don't change the order of insns emitted here without checking with 7239 the gdb folk first. */ 7240 7241 /* Is the entire register save area offsettable from %sp? */ 7242 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) 7243 { 7244 if (size <= 4096) 7245 { 7246 fprintf (file, "\tadd\t%s, %d, %s\n", 7247 sp_str, (int) -size, sp_str); 7248 if (gmask & HARD_FRAME_POINTER_MASK) 7249 { 7250 fprintf (file, "\tst\t%s, [%s+%d]\n", 7251 fp_str, sp_str, reg_offset); 7252 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n", 7253 sp_str, (int) -size, fp_str, ASM_COMMENT_START); 7254 reg_offset += 4; 7255 } 7256 } 7257 else 7258 { 7259 fprintf (file, "\tset\t"); 7260 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); 7261 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", 7262 t1_str, sp_str, t1_str, sp_str); 7263 if (gmask & HARD_FRAME_POINTER_MASK) 7264 { 7265 fprintf (file, "\tst\t%s, [%s+%d]\n", 7266 fp_str, sp_str, reg_offset); 7267 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", 7268 sp_str, t1_str, fp_str, ASM_COMMENT_START); 7269 reg_offset += 4; 7270 } 7271 } 7272 if (dwarf2out_do_frame ()) 7273 { 7274 char *l = dwarf2out_cfi_label (); 7275 if (gmask & HARD_FRAME_POINTER_MASK) 7276 { 7277 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, 7278 reg_offset - 4 - size); 7279 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); 7280 } 7281 else 7282 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); 7283 } 7284 if (gmask & RETURN_ADDR_MASK) 7285 { 7286 fprintf (file, "\tst\t%s, [%s+%d]\n", 7287 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); 7288 if (dwarf2out_do_frame ()) 7289 dwarf2out_return_save ("", reg_offset - size); 7290 reg_offset += 4; 7291 } 7292 sparc_flat_save_restore (file, sp_str, reg_offset, 7293 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7294 current_frame_info.fmask, 7295 "st", "std", -size); 7296 } 7297 else 7298 { 7299 /* Subtract %sp in two steps, but make sure there is always a 7300 64 byte register save area, and %sp is properly aligned. */ 7301 /* Amount to decrement %sp by, the first time. */ 7302 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16; 7303 /* Offset to register save area from %sp. */ 7304 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset); 7305 7306 if (size1 <= 4096) 7307 { 7308 fprintf (file, "\tadd\t%s, %d, %s\n", 7309 sp_str, (int) -size1, sp_str); 7310 if (gmask & HARD_FRAME_POINTER_MASK) 7311 { 7312 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n", 7313 fp_str, sp_str, (int) offset, sp_str, (int) -size1, 7314 fp_str, ASM_COMMENT_START); 7315 offset += 4; 7316 } 7317 } 7318 else 7319 { 7320 fprintf (file, "\tset\t"); 7321 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1); 7322 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", 7323 t1_str, sp_str, t1_str, sp_str); 7324 if (gmask & HARD_FRAME_POINTER_MASK) 7325 { 7326 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n", 7327 fp_str, sp_str, (int) offset, sp_str, t1_str, 7328 fp_str, ASM_COMMENT_START); 7329 offset += 4; 7330 } 7331 } 7332 if (dwarf2out_do_frame ()) 7333 { 7334 char *l = dwarf2out_cfi_label (); 7335 if (gmask & HARD_FRAME_POINTER_MASK) 7336 { 7337 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, 7338 offset - 4 - size1); 7339 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); 7340 } 7341 else 7342 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); 7343 } 7344 if (gmask & RETURN_ADDR_MASK) 7345 { 7346 fprintf (file, "\tst\t%s, [%s+%d]\n", 7347 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset); 7348 if (dwarf2out_do_frame ()) 7349 /* offset - size1 == reg_offset - size 7350 if reg_offset were updated above like offset. */ 7351 dwarf2out_return_save ("", offset - size1); 7352 offset += 4; 7353 } 7354 sparc_flat_save_restore (file, sp_str, offset, 7355 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7356 current_frame_info.fmask, 7357 "st", "std", -size1); 7358 fprintf (file, "\tset\t"); 7359 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size - size1); 7360 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", 7361 t1_str, sp_str, t1_str, sp_str); 7362 if (dwarf2out_do_frame ()) 7363 if (! (gmask & HARD_FRAME_POINTER_MASK)) 7364 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); 7365 } 7366 } 7367 7368 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); 7369} 7370 7371/* Do any necessary cleanup after a function to restore stack, frame, 7372 and regs. */ 7373 7374static void 7375sparc_flat_function_epilogue (file, size) 7376 FILE *file; 7377 HOST_WIDE_INT size; 7378{ 7379 rtx epilogue_delay = current_function_epilogue_delay_list; 7380 int noepilogue = FALSE; 7381 7382 /* This is only for the human reader. */ 7383 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); 7384 7385 /* The epilogue does not depend on any registers, but the stack 7386 registers, so we assume that if we have 1 pending nop, it can be 7387 ignored, and 2 it must be filled (2 nops occur for integer 7388 multiply and divide). */ 7389 7390 size = SPARC_STACK_ALIGN (size); 7391 size = (!current_frame_info.initialized 7392 ? sparc_flat_compute_frame_size (size) 7393 : current_frame_info.total_size); 7394 7395 if (size == 0 && epilogue_delay == 0) 7396 { 7397 rtx insn = get_last_insn (); 7398 7399 /* If the last insn was a BARRIER, we don't have to write any code 7400 because a jump (aka return) was put there. */ 7401 if (GET_CODE (insn) == NOTE) 7402 insn = prev_nonnote_insn (insn); 7403 if (insn && GET_CODE (insn) == BARRIER) 7404 noepilogue = TRUE; 7405 } 7406 7407 if (!noepilogue) 7408 { 7409 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset; 7410 unsigned HOST_WIDE_INT size1; 7411 const char *const sp_str = reg_names[STACK_POINTER_REGNUM]; 7412 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; 7413 static const char *const t1_str = "%g1"; 7414 7415 /* In the reload sequence, we don't need to fill the load delay 7416 slots for most of the loads, also see if we can fill the final 7417 delay slot if not otherwise filled by the reload sequence. */ 7418 7419 if (size > 4095) 7420 { 7421 fprintf (file, "\tset\t"); 7422 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); 7423 fprintf (file, ", %s\n", t1_str); 7424 } 7425 7426 if (frame_pointer_needed) 7427 { 7428 if (size > 4095) 7429 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", 7430 fp_str, t1_str, sp_str, ASM_COMMENT_START); 7431 else 7432 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n", 7433 fp_str, (int) size, sp_str, ASM_COMMENT_START); 7434 } 7435 7436 /* Is the entire register save area offsettable from %sp? */ 7437 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) 7438 { 7439 size1 = 0; 7440 } 7441 else 7442 { 7443 /* Restore %sp in two steps, but make sure there is always a 7444 64 byte register save area, and %sp is properly aligned. */ 7445 /* Amount to increment %sp by, the first time. */ 7446 size1 = ((reg_offset - 64 - 16) + 15) & -16; 7447 /* Offset to register save area from %sp. */ 7448 reg_offset = size1 - reg_offset; 7449 7450 fprintf (file, "\tset\t"); 7451 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1); 7452 fprintf (file, ", %s\n\tadd\t%s, %s, %s\n", 7453 t1_str, sp_str, t1_str, sp_str); 7454 } 7455 7456 /* We must restore the frame pointer and return address reg first 7457 because they are treated specially by the prologue output code. */ 7458 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK) 7459 { 7460 fprintf (file, "\tld\t[%s+%d], %s\n", 7461 sp_str, (int) reg_offset, fp_str); 7462 reg_offset += 4; 7463 } 7464 if (current_frame_info.gmask & RETURN_ADDR_MASK) 7465 { 7466 fprintf (file, "\tld\t[%s+%d], %s\n", 7467 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]); 7468 reg_offset += 4; 7469 } 7470 7471 /* Restore any remaining saved registers. */ 7472 sparc_flat_save_restore (file, sp_str, reg_offset, 7473 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7474 current_frame_info.fmask, 7475 "ld", "ldd", 0); 7476 7477 /* If we had to increment %sp in two steps, record it so the second 7478 restoration in the epilogue finishes up. */ 7479 if (size1 > 0) 7480 { 7481 size -= size1; 7482 if (size > 4095) 7483 { 7484 fprintf (file, "\tset\t"); 7485 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); 7486 fprintf (file, ", %s\n", t1_str); 7487 } 7488 } 7489 7490 if (current_function_returns_struct) 7491 fprintf (file, "\tjmp\t%%o7+12\n"); 7492 else 7493 fprintf (file, "\tretl\n"); 7494 7495 /* If the only register saved is the return address, we need a 7496 nop, unless we have an instruction to put into it. Otherwise 7497 we don't since reloading multiple registers doesn't reference 7498 the register being loaded. */ 7499 7500 if (epilogue_delay) 7501 { 7502 if (size) 7503 abort (); 7504 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); 7505 } 7506 7507 else if (size > 4095) 7508 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); 7509 7510 else if (size > 0) 7511 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str); 7512 7513 else 7514 fprintf (file, "\tnop\n"); 7515 } 7516 7517 /* Reset state info for each function. */ 7518 current_frame_info = zero_frame_info; 7519 7520 sparc_output_deferred_case_vectors (); 7521} 7522 7523/* Define the number of delay slots needed for the function epilogue. 7524 7525 On the sparc, we need a slot if either no stack has been allocated, 7526 or the only register saved is the return register. */ 7527 7528int 7529sparc_flat_epilogue_delay_slots () 7530{ 7531 if (!current_frame_info.initialized) 7532 (void) sparc_flat_compute_frame_size (get_frame_size ()); 7533 7534 if (current_frame_info.total_size == 0) 7535 return 1; 7536 7537 return 0; 7538} 7539 7540/* Return true if TRIAL is a valid insn for the epilogue delay slot. 7541 Any single length instruction which doesn't reference the stack or frame 7542 pointer is OK. */ 7543 7544int 7545sparc_flat_eligible_for_epilogue_delay (trial, slot) 7546 rtx trial; 7547 int slot ATTRIBUTE_UNUSED; 7548{ 7549 rtx pat = PATTERN (trial); 7550 7551 if (get_attr_length (trial) != 1) 7552 return 0; 7553 7554 if (! reg_mentioned_p (stack_pointer_rtx, pat) 7555 && ! reg_mentioned_p (frame_pointer_rtx, pat)) 7556 return 1; 7557 7558 return 0; 7559} 7560 7561/* Adjust the cost of a scheduling dependency. Return the new cost of 7562 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ 7563 7564static int 7565supersparc_adjust_cost (insn, link, dep_insn, cost) 7566 rtx insn; 7567 rtx link; 7568 rtx dep_insn; 7569 int cost; 7570{ 7571 enum attr_type insn_type; 7572 7573 if (! recog_memoized (insn)) 7574 return 0; 7575 7576 insn_type = get_attr_type (insn); 7577 7578 if (REG_NOTE_KIND (link) == 0) 7579 { 7580 /* Data dependency; DEP_INSN writes a register that INSN reads some 7581 cycles later. */ 7582 7583 /* if a load, then the dependence must be on the memory address; 7584 add an extra "cycle". Note that the cost could be two cycles 7585 if the reg was written late in an instruction group; we ca not tell 7586 here. */ 7587 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) 7588 return cost + 3; 7589 7590 /* Get the delay only if the address of the store is the dependence. */ 7591 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) 7592 { 7593 rtx pat = PATTERN(insn); 7594 rtx dep_pat = PATTERN (dep_insn); 7595 7596 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 7597 return cost; /* This should not happen! */ 7598 7599 /* The dependency between the two instructions was on the data that 7600 is being stored. Assume that this implies that the address of the 7601 store is not dependent. */ 7602 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 7603 return cost; 7604 7605 return cost + 3; /* An approximation. */ 7606 } 7607 7608 /* A shift instruction cannot receive its data from an instruction 7609 in the same cycle; add a one cycle penalty. */ 7610 if (insn_type == TYPE_SHIFT) 7611 return cost + 3; /* Split before cascade into shift. */ 7612 } 7613 else 7614 { 7615 /* Anti- or output- dependency; DEP_INSN reads/writes a register that 7616 INSN writes some cycles later. */ 7617 7618 /* These are only significant for the fpu unit; writing a fp reg before 7619 the fpu has finished with it stalls the processor. */ 7620 7621 /* Reusing an integer register causes no problems. */ 7622 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 7623 return 0; 7624 } 7625 7626 return cost; 7627} 7628 7629static int 7630hypersparc_adjust_cost (insn, link, dep_insn, cost) 7631 rtx insn; 7632 rtx link; 7633 rtx dep_insn; 7634 int cost; 7635{ 7636 enum attr_type insn_type, dep_type; 7637 rtx pat = PATTERN(insn); 7638 rtx dep_pat = PATTERN (dep_insn); 7639 7640 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) 7641 return cost; 7642 7643 insn_type = get_attr_type (insn); 7644 dep_type = get_attr_type (dep_insn); 7645 7646 switch (REG_NOTE_KIND (link)) 7647 { 7648 case 0: 7649 /* Data dependency; DEP_INSN writes a register that INSN reads some 7650 cycles later. */ 7651 7652 switch (insn_type) 7653 { 7654 case TYPE_STORE: 7655 case TYPE_FPSTORE: 7656 /* Get the delay iff the address of the store is the dependence. */ 7657 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 7658 return cost; 7659 7660 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 7661 return cost; 7662 return cost + 3; 7663 7664 case TYPE_LOAD: 7665 case TYPE_SLOAD: 7666 case TYPE_FPLOAD: 7667 /* If a load, then the dependence must be on the memory address. If 7668 the addresses aren't equal, then it might be a false dependency */ 7669 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) 7670 { 7671 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET 7672 || GET_CODE (SET_DEST (dep_pat)) != MEM 7673 || GET_CODE (SET_SRC (pat)) != MEM 7674 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), 7675 XEXP (SET_SRC (pat), 0))) 7676 return cost + 2; 7677 7678 return cost + 8; 7679 } 7680 break; 7681 7682 case TYPE_BRANCH: 7683 /* Compare to branch latency is 0. There is no benefit from 7684 separating compare and branch. */ 7685 if (dep_type == TYPE_COMPARE) 7686 return 0; 7687 /* Floating point compare to branch latency is less than 7688 compare to conditional move. */ 7689 if (dep_type == TYPE_FPCMP) 7690 return cost - 1; 7691 break; 7692 default: 7693 break; 7694 } 7695 break; 7696 7697 case REG_DEP_ANTI: 7698 /* Anti-dependencies only penalize the fpu unit. */ 7699 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 7700 return 0; 7701 break; 7702 7703 default: 7704 break; 7705 } 7706 7707 return cost; 7708} 7709 7710static int 7711sparc_adjust_cost(insn, link, dep, cost) 7712 rtx insn; 7713 rtx link; 7714 rtx dep; 7715 int cost; 7716{ 7717 switch (sparc_cpu) 7718 { 7719 case PROCESSOR_SUPERSPARC: 7720 cost = supersparc_adjust_cost (insn, link, dep, cost); 7721 break; 7722 case PROCESSOR_HYPERSPARC: 7723 case PROCESSOR_SPARCLITE86X: 7724 cost = hypersparc_adjust_cost (insn, link, dep, cost); 7725 break; 7726 default: 7727 break; 7728 } 7729 return cost; 7730} 7731 7732static void 7733sparc_sched_init (dump, sched_verbose, max_ready) 7734 FILE *dump ATTRIBUTE_UNUSED; 7735 int sched_verbose ATTRIBUTE_UNUSED; 7736 int max_ready ATTRIBUTE_UNUSED; 7737{ 7738} 7739 7740static int 7741sparc_use_dfa_pipeline_interface () 7742{ 7743 if ((1 << sparc_cpu) & 7744 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) | 7745 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | 7746 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) | 7747 (1 << PROCESSOR_ULTRASPARC3))) 7748 return 1; 7749 return 0; 7750} 7751 7752static int 7753sparc_use_sched_lookahead () 7754{ 7755 if (sparc_cpu == PROCESSOR_ULTRASPARC 7756 || sparc_cpu == PROCESSOR_ULTRASPARC3) 7757 return 4; 7758 if ((1 << sparc_cpu) & 7759 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | 7760 (1 << PROCESSOR_SPARCLITE86X))) 7761 return 3; 7762 return 0; 7763} 7764 7765static int 7766sparc_issue_rate () 7767{ 7768 switch (sparc_cpu) 7769 { 7770 default: 7771 return 1; 7772 case PROCESSOR_V9: 7773 /* Assume V9 processors are capable of at least dual-issue. */ 7774 return 2; 7775 case PROCESSOR_SUPERSPARC: 7776 return 3; 7777 case PROCESSOR_HYPERSPARC: 7778 case PROCESSOR_SPARCLITE86X: 7779 return 2; 7780 case PROCESSOR_ULTRASPARC: 7781 case PROCESSOR_ULTRASPARC3: 7782 return 4; 7783 } 7784} 7785 7786static int 7787set_extends (insn) 7788 rtx insn; 7789{ 7790 register rtx pat = PATTERN (insn); 7791 7792 switch (GET_CODE (SET_SRC (pat))) 7793 { 7794 /* Load and some shift instructions zero extend. */ 7795 case MEM: 7796 case ZERO_EXTEND: 7797 /* sethi clears the high bits */ 7798 case HIGH: 7799 /* LO_SUM is used with sethi. sethi cleared the high 7800 bits and the values used with lo_sum are positive */ 7801 case LO_SUM: 7802 /* Store flag stores 0 or 1 */ 7803 case LT: case LTU: 7804 case GT: case GTU: 7805 case LE: case LEU: 7806 case GE: case GEU: 7807 case EQ: 7808 case NE: 7809 return 1; 7810 case AND: 7811 { 7812 rtx op0 = XEXP (SET_SRC (pat), 0); 7813 rtx op1 = XEXP (SET_SRC (pat), 1); 7814 if (GET_CODE (op1) == CONST_INT) 7815 return INTVAL (op1) >= 0; 7816 if (GET_CODE (op0) != REG) 7817 return 0; 7818 if (sparc_check_64 (op0, insn) == 1) 7819 return 1; 7820 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 7821 } 7822 case IOR: 7823 case XOR: 7824 { 7825 rtx op0 = XEXP (SET_SRC (pat), 0); 7826 rtx op1 = XEXP (SET_SRC (pat), 1); 7827 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) 7828 return 0; 7829 if (GET_CODE (op1) == CONST_INT) 7830 return INTVAL (op1) >= 0; 7831 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 7832 } 7833 case LSHIFTRT: 7834 return GET_MODE (SET_SRC (pat)) == SImode; 7835 /* Positive integers leave the high bits zero. */ 7836 case CONST_DOUBLE: 7837 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000); 7838 case CONST_INT: 7839 return ! (INTVAL (SET_SRC (pat)) & 0x80000000); 7840 case ASHIFTRT: 7841 case SIGN_EXTEND: 7842 return - (GET_MODE (SET_SRC (pat)) == SImode); 7843 case REG: 7844 return sparc_check_64 (SET_SRC (pat), insn); 7845 default: 7846 return 0; 7847 } 7848} 7849 7850/* We _ought_ to have only one kind per function, but... */ 7851static GTY(()) rtx sparc_addr_diff_list; 7852static GTY(()) rtx sparc_addr_list; 7853 7854void 7855sparc_defer_case_vector (lab, vec, diff) 7856 rtx lab, vec; 7857 int diff; 7858{ 7859 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); 7860 if (diff) 7861 sparc_addr_diff_list 7862 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); 7863 else 7864 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); 7865} 7866 7867static void 7868sparc_output_addr_vec (vec) 7869 rtx vec; 7870{ 7871 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 7872 int idx, vlen = XVECLEN (body, 0); 7873 7874#ifdef ASM_OUTPUT_ADDR_VEC_START 7875 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 7876#endif 7877 7878#ifdef ASM_OUTPUT_CASE_LABEL 7879 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 7880 NEXT_INSN (lab)); 7881#else 7882 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 7883#endif 7884 7885 for (idx = 0; idx < vlen; idx++) 7886 { 7887 ASM_OUTPUT_ADDR_VEC_ELT 7888 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); 7889 } 7890 7891#ifdef ASM_OUTPUT_ADDR_VEC_END 7892 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 7893#endif 7894} 7895 7896static void 7897sparc_output_addr_diff_vec (vec) 7898 rtx vec; 7899{ 7900 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 7901 rtx base = XEXP (XEXP (body, 0), 0); 7902 int idx, vlen = XVECLEN (body, 1); 7903 7904#ifdef ASM_OUTPUT_ADDR_VEC_START 7905 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 7906#endif 7907 7908#ifdef ASM_OUTPUT_CASE_LABEL 7909 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 7910 NEXT_INSN (lab)); 7911#else 7912 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 7913#endif 7914 7915 for (idx = 0; idx < vlen; idx++) 7916 { 7917 ASM_OUTPUT_ADDR_DIFF_ELT 7918 (asm_out_file, 7919 body, 7920 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), 7921 CODE_LABEL_NUMBER (base)); 7922 } 7923 7924#ifdef ASM_OUTPUT_ADDR_VEC_END 7925 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 7926#endif 7927} 7928 7929static void 7930sparc_output_deferred_case_vectors () 7931{ 7932 rtx t; 7933 int align; 7934 7935 if (sparc_addr_list == NULL_RTX 7936 && sparc_addr_diff_list == NULL_RTX) 7937 return; 7938 7939 /* Align to cache line in the function's code section. */ 7940 function_section (current_function_decl); 7941 7942 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 7943 if (align > 0) 7944 ASM_OUTPUT_ALIGN (asm_out_file, align); 7945 7946 for (t = sparc_addr_list; t ; t = XEXP (t, 1)) 7947 sparc_output_addr_vec (XEXP (t, 0)); 7948 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) 7949 sparc_output_addr_diff_vec (XEXP (t, 0)); 7950 7951 sparc_addr_list = sparc_addr_diff_list = NULL_RTX; 7952} 7953 7954/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are 7955 unknown. Return 1 if the high bits are zero, -1 if the register is 7956 sign extended. */ 7957int 7958sparc_check_64 (x, insn) 7959 rtx x, insn; 7960{ 7961 /* If a register is set only once it is safe to ignore insns this 7962 code does not know how to handle. The loop will either recognize 7963 the single set and return the correct value or fail to recognize 7964 it and return 0. */ 7965 int set_once = 0; 7966 rtx y = x; 7967 7968 if (GET_CODE (x) != REG) 7969 abort (); 7970 7971 if (GET_MODE (x) == DImode) 7972 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); 7973 7974 if (flag_expensive_optimizations 7975 && REG_N_SETS (REGNO (y)) == 1) 7976 set_once = 1; 7977 7978 if (insn == 0) 7979 { 7980 if (set_once) 7981 insn = get_last_insn_anywhere (); 7982 else 7983 return 0; 7984 } 7985 7986 while ((insn = PREV_INSN (insn))) 7987 { 7988 switch (GET_CODE (insn)) 7989 { 7990 case JUMP_INSN: 7991 case NOTE: 7992 break; 7993 case CODE_LABEL: 7994 case CALL_INSN: 7995 default: 7996 if (! set_once) 7997 return 0; 7998 break; 7999 case INSN: 8000 { 8001 rtx pat = PATTERN (insn); 8002 if (GET_CODE (pat) != SET) 8003 return 0; 8004 if (rtx_equal_p (x, SET_DEST (pat))) 8005 return set_extends (insn); 8006 if (y && rtx_equal_p (y, SET_DEST (pat))) 8007 return set_extends (insn); 8008 if (reg_overlap_mentioned_p (SET_DEST (pat), y)) 8009 return 0; 8010 } 8011 } 8012 } 8013 return 0; 8014} 8015 8016/* Returns assembly code to perform a DImode shift using 8017 a 64-bit global or out register on SPARC-V8+. */ 8018char * 8019sparc_v8plus_shift (operands, insn, opcode) 8020 rtx *operands; 8021 rtx insn; 8022 const char *opcode; 8023{ 8024 static char asm_code[60]; 8025 8026 /* The scratch register is only required when the destination 8027 register is not a 64-bit global or out register. */ 8028 if (which_alternative != 2) 8029 operands[3] = operands[0]; 8030 8031 /* We can only shift by constants <= 63. */ 8032 if (GET_CODE (operands[2]) == CONST_INT) 8033 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 8034 8035 if (GET_CODE (operands[1]) == CONST_INT) 8036 { 8037 output_asm_insn ("mov\t%1, %3", operands); 8038 } 8039 else 8040 { 8041 output_asm_insn ("sllx\t%H1, 32, %3", operands); 8042 if (sparc_check_64 (operands[1], insn) <= 0) 8043 output_asm_insn ("srl\t%L1, 0, %L1", operands); 8044 output_asm_insn ("or\t%L1, %3, %3", operands); 8045 } 8046 8047 strcpy(asm_code, opcode); 8048 8049 if (which_alternative != 2) 8050 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); 8051 else 8052 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); 8053} 8054 8055/* Output rtl to increment the profiler label LABELNO 8056 for profiling a function entry. */ 8057 8058void 8059sparc_profile_hook (labelno) 8060 int labelno; 8061{ 8062 char buf[32]; 8063 rtx lab, fun; 8064 8065 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); 8066 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 8067 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); 8068 8069 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); 8070} 8071 8072#ifdef OBJECT_FORMAT_ELF 8073static void 8074sparc_elf_asm_named_section (name, flags) 8075 const char *name; 8076 unsigned int flags; 8077{ 8078 if (flags & SECTION_MERGE) 8079 { 8080 /* entsize cannot be expressed in this section attributes 8081 encoding style. */ 8082 default_elf_asm_named_section (name, flags); 8083 return; 8084 } 8085 8086 fprintf (asm_out_file, "\t.section\t\"%s\"", name); 8087 8088 if (!(flags & SECTION_DEBUG)) 8089 fputs (",#alloc", asm_out_file); 8090 if (flags & SECTION_WRITE) 8091 fputs (",#write", asm_out_file); 8092 if (flags & SECTION_CODE) 8093 fputs (",#execinstr", asm_out_file); 8094 8095 /* ??? Handle SECTION_BSS. */ 8096 8097 fputc ('\n', asm_out_file); 8098} 8099#endif /* OBJECT_FORMAT_ELF */ 8100 8101/* ??? Similar to the standard section selection, but force reloc-y-ness 8102 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to 8103 pretending PIC always on), but that's what the old code did. */ 8104 8105static void 8106sparc_aout_select_section (t, reloc, align) 8107 tree t; 8108 int reloc; 8109 unsigned HOST_WIDE_INT align; 8110{ 8111 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align); 8112} 8113 8114/* Use text section for a constant unless we need more alignment than 8115 that offers. */ 8116 8117static void 8118sparc_aout_select_rtx_section (mode, x, align) 8119 enum machine_mode mode; 8120 rtx x; 8121 unsigned HOST_WIDE_INT align; 8122{ 8123 if (align <= MAX_TEXT_ALIGN 8124 && ! (flag_pic && (symbolic_operand (x, mode) 8125 || SUNOS4_SHARED_LIBRARIES))) 8126 readonly_data_section (); 8127 else 8128 data_section (); 8129} 8130 8131int 8132sparc_extra_constraint_check (op, c, strict) 8133 rtx op; 8134 int c; 8135 int strict; 8136{ 8137 int reload_ok_mem; 8138 8139 if (TARGET_ARCH64 8140 && (c == 'T' || c == 'U')) 8141 return 0; 8142 8143 switch (c) 8144 { 8145 case 'Q': 8146 return fp_sethi_p (op); 8147 8148 case 'R': 8149 return fp_mov_p (op); 8150 8151 case 'S': 8152 return fp_high_losum_p (op); 8153 8154 case 'U': 8155 if (! strict 8156 || (GET_CODE (op) == REG 8157 && (REGNO (op) < FIRST_PSEUDO_REGISTER 8158 || reg_renumber[REGNO (op)] >= 0))) 8159 return register_ok_for_ldd (op); 8160 8161 return 0; 8162 8163 case 'W': 8164 case 'T': 8165 break; 8166 8167 default: 8168 return 0; 8169 } 8170 8171 /* Our memory extra constraints have to emulate the 8172 behavior of 'm' and 'o' in order for reload to work 8173 correctly. */ 8174 if (GET_CODE (op) == MEM) 8175 { 8176 reload_ok_mem = 0; 8177 if ((TARGET_ARCH64 || mem_min_alignment (op, 8)) 8178 && (! strict 8179 || strict_memory_address_p (Pmode, XEXP (op, 0)))) 8180 reload_ok_mem = 1; 8181 } 8182 else 8183 { 8184 reload_ok_mem = (reload_in_progress 8185 && GET_CODE (op) == REG 8186 && REGNO (op) >= FIRST_PSEUDO_REGISTER 8187 && reg_renumber [REGNO (op)] < 0); 8188 } 8189 8190 return reload_ok_mem; 8191} 8192 8193/* ??? This duplicates information provided to the compiler by the 8194 ??? scheduler description. Some day, teach genautomata to output 8195 ??? the latencies and then CSE will just use that. */ 8196 8197int 8198sparc_rtx_costs (x, code, outer_code) 8199 rtx x; 8200 enum rtx_code code, outer_code; 8201{ 8202 switch (code) 8203 { 8204 case PLUS: case MINUS: case ABS: case NEG: 8205 case FLOAT: case UNSIGNED_FLOAT: 8206 case FIX: case UNSIGNED_FIX: 8207 case FLOAT_EXTEND: case FLOAT_TRUNCATE: 8208 if (FLOAT_MODE_P (GET_MODE (x))) 8209 { 8210 switch (sparc_cpu) 8211 { 8212 case PROCESSOR_ULTRASPARC: 8213 case PROCESSOR_ULTRASPARC3: 8214 return COSTS_N_INSNS (4); 8215 8216 case PROCESSOR_SUPERSPARC: 8217 return COSTS_N_INSNS (3); 8218 8219 case PROCESSOR_CYPRESS: 8220 return COSTS_N_INSNS (5); 8221 8222 case PROCESSOR_HYPERSPARC: 8223 case PROCESSOR_SPARCLITE86X: 8224 default: 8225 return COSTS_N_INSNS (1); 8226 } 8227 } 8228 8229 return COSTS_N_INSNS (1); 8230 8231 case SQRT: 8232 switch (sparc_cpu) 8233 { 8234 case PROCESSOR_ULTRASPARC: 8235 if (GET_MODE (x) == SFmode) 8236 return COSTS_N_INSNS (13); 8237 else 8238 return COSTS_N_INSNS (23); 8239 8240 case PROCESSOR_ULTRASPARC3: 8241 if (GET_MODE (x) == SFmode) 8242 return COSTS_N_INSNS (20); 8243 else 8244 return COSTS_N_INSNS (29); 8245 8246 case PROCESSOR_SUPERSPARC: 8247 return COSTS_N_INSNS (12); 8248 8249 case PROCESSOR_CYPRESS: 8250 return COSTS_N_INSNS (63); 8251 8252 case PROCESSOR_HYPERSPARC: 8253 case PROCESSOR_SPARCLITE86X: 8254 return COSTS_N_INSNS (17); 8255 8256 default: 8257 return COSTS_N_INSNS (30); 8258 } 8259 8260 case COMPARE: 8261 if (FLOAT_MODE_P (GET_MODE (x))) 8262 { 8263 switch (sparc_cpu) 8264 { 8265 case PROCESSOR_ULTRASPARC: 8266 case PROCESSOR_ULTRASPARC3: 8267 return COSTS_N_INSNS (1); 8268 8269 case PROCESSOR_SUPERSPARC: 8270 return COSTS_N_INSNS (3); 8271 8272 case PROCESSOR_CYPRESS: 8273 return COSTS_N_INSNS (5); 8274 8275 case PROCESSOR_HYPERSPARC: 8276 case PROCESSOR_SPARCLITE86X: 8277 default: 8278 return COSTS_N_INSNS (1); 8279 } 8280 } 8281 8282 /* ??? Maybe mark integer compares as zero cost on 8283 ??? all UltraSPARC processors because the result 8284 ??? can be bypassed to a branch in the same group. */ 8285 8286 return COSTS_N_INSNS (1); 8287 8288 case MULT: 8289 if (FLOAT_MODE_P (GET_MODE (x))) 8290 { 8291 switch (sparc_cpu) 8292 { 8293 case PROCESSOR_ULTRASPARC: 8294 case PROCESSOR_ULTRASPARC3: 8295 return COSTS_N_INSNS (4); 8296 8297 case PROCESSOR_SUPERSPARC: 8298 return COSTS_N_INSNS (3); 8299 8300 case PROCESSOR_CYPRESS: 8301 return COSTS_N_INSNS (7); 8302 8303 case PROCESSOR_HYPERSPARC: 8304 case PROCESSOR_SPARCLITE86X: 8305 return COSTS_N_INSNS (1); 8306 8307 default: 8308 return COSTS_N_INSNS (5); 8309 } 8310 } 8311 8312 /* The latency is actually variable for Ultra-I/II 8313 And if one of the inputs have a known constant 8314 value, we could calculate this precisely. 8315 8316 However, for that to be useful we would need to 8317 add some machine description changes which would 8318 make sure small constants ended up in rs1 of the 8319 multiply instruction. This is because the multiply 8320 latency is determined by the number of clear (or 8321 set if the value is negative) bits starting from 8322 the most significant bit of the first input. 8323 8324 The algorithm for computing num_cycles of a multiply 8325 on Ultra-I/II is: 8326 8327 if (rs1 < 0) 8328 highest_bit = highest_clear_bit(rs1); 8329 else 8330 highest_bit = highest_set_bit(rs1); 8331 if (num_bits < 3) 8332 highest_bit = 3; 8333 num_cycles = 4 + ((highest_bit - 3) / 2); 8334 8335 If we did that we would have to also consider register 8336 allocation issues that would result from forcing such 8337 a value into a register. 8338 8339 There are other similar tricks we could play if we 8340 knew, for example, that one input was an array index. 8341 8342 Since we do not play any such tricks currently the 8343 safest thing to do is report the worst case latency. */ 8344 if (sparc_cpu == PROCESSOR_ULTRASPARC) 8345 return (GET_MODE (x) == DImode ? 8346 COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); 8347 8348 /* Multiply latency on Ultra-III, fortunately, is constant. */ 8349 if (sparc_cpu == PROCESSOR_ULTRASPARC3) 8350 return COSTS_N_INSNS (6); 8351 8352 if (sparc_cpu == PROCESSOR_HYPERSPARC 8353 || sparc_cpu == PROCESSOR_SPARCLITE86X) 8354 return COSTS_N_INSNS (17); 8355 8356 return (TARGET_HARD_MUL 8357 ? COSTS_N_INSNS (5) 8358 : COSTS_N_INSNS (25)); 8359 8360 case DIV: 8361 case UDIV: 8362 case MOD: 8363 case UMOD: 8364 if (FLOAT_MODE_P (GET_MODE (x))) 8365 { 8366 switch (sparc_cpu) 8367 { 8368 case PROCESSOR_ULTRASPARC: 8369 if (GET_MODE (x) == SFmode) 8370 return COSTS_N_INSNS (13); 8371 else 8372 return COSTS_N_INSNS (23); 8373 8374 case PROCESSOR_ULTRASPARC3: 8375 if (GET_MODE (x) == SFmode) 8376 return COSTS_N_INSNS (17); 8377 else 8378 return COSTS_N_INSNS (20); 8379 8380 case PROCESSOR_SUPERSPARC: 8381 if (GET_MODE (x) == SFmode) 8382 return COSTS_N_INSNS (6); 8383 else 8384 return COSTS_N_INSNS (9); 8385 8386 case PROCESSOR_HYPERSPARC: 8387 case PROCESSOR_SPARCLITE86X: 8388 if (GET_MODE (x) == SFmode) 8389 return COSTS_N_INSNS (8); 8390 else 8391 return COSTS_N_INSNS (12); 8392 8393 default: 8394 return COSTS_N_INSNS (7); 8395 } 8396 } 8397 8398 if (sparc_cpu == PROCESSOR_ULTRASPARC) 8399 return (GET_MODE (x) == DImode ? 8400 COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); 8401 if (sparc_cpu == PROCESSOR_ULTRASPARC3) 8402 return (GET_MODE (x) == DImode ? 8403 COSTS_N_INSNS (71) : COSTS_N_INSNS (40)); 8404 return COSTS_N_INSNS (25); 8405 8406 case IF_THEN_ELSE: 8407 /* Conditional moves. */ 8408 switch (sparc_cpu) 8409 { 8410 case PROCESSOR_ULTRASPARC: 8411 return COSTS_N_INSNS (2); 8412 8413 case PROCESSOR_ULTRASPARC3: 8414 if (FLOAT_MODE_P (GET_MODE (x))) 8415 return COSTS_N_INSNS (3); 8416 else 8417 return COSTS_N_INSNS (2); 8418 8419 default: 8420 return COSTS_N_INSNS (1); 8421 } 8422 8423 case MEM: 8424 /* If outer-code is SIGN/ZERO extension we have to subtract 8425 out COSTS_N_INSNS (1) from whatever we return in determining 8426 the cost. */ 8427 switch (sparc_cpu) 8428 { 8429 case PROCESSOR_ULTRASPARC: 8430 if (outer_code == ZERO_EXTEND) 8431 return COSTS_N_INSNS (1); 8432 else 8433 return COSTS_N_INSNS (2); 8434 8435 case PROCESSOR_ULTRASPARC3: 8436 if (outer_code == ZERO_EXTEND) 8437 { 8438 if (GET_MODE (x) == QImode 8439 || GET_MODE (x) == HImode 8440 || outer_code == SIGN_EXTEND) 8441 return COSTS_N_INSNS (2); 8442 else 8443 return COSTS_N_INSNS (1); 8444 } 8445 else 8446 { 8447 /* This handles sign extension (3 cycles) 8448 and everything else (2 cycles). */ 8449 return COSTS_N_INSNS (2); 8450 } 8451 8452 case PROCESSOR_SUPERSPARC: 8453 if (FLOAT_MODE_P (GET_MODE (x)) 8454 || outer_code == ZERO_EXTEND 8455 || outer_code == SIGN_EXTEND) 8456 return COSTS_N_INSNS (0); 8457 else 8458 return COSTS_N_INSNS (1); 8459 8460 case PROCESSOR_TSC701: 8461 if (outer_code == ZERO_EXTEND 8462 || outer_code == SIGN_EXTEND) 8463 return COSTS_N_INSNS (2); 8464 else 8465 return COSTS_N_INSNS (3); 8466 8467 case PROCESSOR_CYPRESS: 8468 if (outer_code == ZERO_EXTEND 8469 || outer_code == SIGN_EXTEND) 8470 return COSTS_N_INSNS (1); 8471 else 8472 return COSTS_N_INSNS (2); 8473 8474 case PROCESSOR_HYPERSPARC: 8475 case PROCESSOR_SPARCLITE86X: 8476 default: 8477 if (outer_code == ZERO_EXTEND 8478 || outer_code == SIGN_EXTEND) 8479 return COSTS_N_INSNS (0); 8480 else 8481 return COSTS_N_INSNS (1); 8482 } 8483 8484 case CONST_INT: 8485 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000) 8486 return 0; 8487 8488 /* fallthru */ 8489 case HIGH: 8490 return 2; 8491 8492 case CONST: 8493 case LABEL_REF: 8494 case SYMBOL_REF: 8495 return 4; 8496 8497 case CONST_DOUBLE: 8498 if (GET_MODE (x) == DImode) 8499 if ((XINT (x, 3) == 0 8500 && (unsigned) XINT (x, 2) < 0x1000) 8501 || (XINT (x, 3) == -1 8502 && XINT (x, 2) < 0 8503 && XINT (x, 2) >= -0x1000)) 8504 return 0; 8505 return 8; 8506 8507 default: 8508 abort(); 8509 }; 8510} 8511 8512/* If we are referencing a function make the SYMBOL_REF special. In 8513 the Embedded Medium/Anywhere code model, %g4 points to the data 8514 segment so we must not add it to function addresses. */ 8515 8516static void 8517sparc_encode_section_info (decl, first) 8518 tree decl; 8519 int first ATTRIBUTE_UNUSED; 8520{ 8521 if (TARGET_CM_EMBMEDANY && TREE_CODE (decl) == FUNCTION_DECL) 8522 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1; 8523} 8524 8525/* Output code to add DELTA to the first argument, and then jump to FUNCTION. 8526 Used for C++ multiple inheritance. */ 8527 8528static void 8529sparc_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) 8530 FILE *file; 8531 tree thunk_fndecl ATTRIBUTE_UNUSED; 8532 HOST_WIDE_INT delta; 8533 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED; 8534 tree function; 8535{ 8536 rtx this, insn, funexp, delta_rtx, tmp; 8537 8538 reload_completed = 1; 8539 no_new_pseudos = 1; 8540 current_function_uses_only_leaf_regs = 1; 8541 8542 emit_note (NULL, NOTE_INSN_PROLOGUE_END); 8543 8544 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function 8545 returns a structure, the structure return pointer is there instead. */ 8546 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)))) 8547 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1); 8548 else 8549 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST); 8550 8551 /* Add DELTA. When possible use a plain add, otherwise load it into 8552 a register first. */ 8553 delta_rtx = GEN_INT (delta); 8554 if (!SPARC_SIMM13_P (delta)) 8555 { 8556 rtx scratch = gen_rtx_REG (Pmode, 1); 8557 if (TARGET_ARCH64) 8558 sparc_emit_set_const64 (scratch, delta_rtx); 8559 else 8560 sparc_emit_set_const32 (scratch, delta_rtx); 8561 delta_rtx = scratch; 8562 } 8563 8564 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx); 8565 emit_insn (gen_rtx_SET (VOIDmode, this, tmp)); 8566 8567 /* Generate a tail call to the target function. */ 8568 if (! TREE_USED (function)) 8569 { 8570 assemble_external (function); 8571 TREE_USED (function) = 1; 8572 } 8573 funexp = XEXP (DECL_RTL (function), 0); 8574 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); 8575 insn = emit_call_insn (gen_sibcall (funexp)); 8576 SIBLING_CALL_P (insn) = 1; 8577 emit_barrier (); 8578 8579 /* Run just enough of rest_of_compilation to get the insns emitted. 8580 There's not really enough bulk here to make other passes such as 8581 instruction scheduling worth while. Note that use_thunk calls 8582 assemble_start_function and assemble_end_function. */ 8583 insn = get_insns (); 8584 shorten_branches (insn); 8585 final_start_function (insn, file, 1); 8586 final (insn, file, 1, 0); 8587 final_end_function (); 8588 8589 reload_completed = 0; 8590 no_new_pseudos = 0; 8591} 8592 8593#include "gt-sparc.h" 8594