1;; GCC machine description for IA-64 synchronization instructions. 2;; Copyright (C) 2005 3;; Free Software Foundation, Inc. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 2, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING. If not, write to 19;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20;; Boston, MA 02110-1301, USA. 21 22(define_mode_macro IMODE [QI HI SI DI]) 23(define_mode_macro I124MODE [QI HI SI]) 24(define_mode_macro I48MODE [SI DI]) 25(define_mode_attr modesuffix [(QI "1") (HI "2") (SI "4") (DI "8")]) 26 27(define_code_macro FETCHOP [plus minus ior xor and]) 28(define_code_attr fetchop_name 29 [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")]) 30 31(define_insn "memory_barrier" 32 [(set (mem:BLK (match_scratch:DI 0 "X")) 33 (unspec:BLK [(mem:BLK (match_scratch:DI 1 "X"))] UNSPEC_MF))] 34 "" 35 "mf" 36 [(set_attr "itanium_class" "syst_m")]) 37 38(define_insn "fetchadd_acq_<mode>" 39 [(set (match_operand:I48MODE 0 "gr_register_operand" "=r") 40 (match_operand:I48MODE 1 "not_postinc_memory_operand" "+S")) 41 (set (match_dup 1) 42 (unspec:I48MODE [(match_dup 1) 43 (match_operand:I48MODE 2 "fetchadd_operand" "n")] 44 UNSPEC_FETCHADD_ACQ))] 45 "" 46 "fetchadd<modesuffix>.acq %0 = %1, %2" 47 [(set_attr "itanium_class" "sem")]) 48 49(define_expand "sync_<fetchop_name><mode>" 50 [(set (match_operand:IMODE 0 "memory_operand" "") 51 (FETCHOP:IMODE (match_dup 0) 52 (match_operand:IMODE 1 "general_operand" "")))] 53 "" 54{ 55 ia64_expand_atomic_op (<CODE>, operands[0], operands[1], NULL, NULL); 56 DONE; 57}) 58 59(define_expand "sync_nand<mode>" 60 [(set (match_operand:IMODE 0 "memory_operand" "") 61 (and:IMODE (not:IMODE (match_dup 0)) 62 (match_operand:IMODE 1 "general_operand" "")))] 63 "" 64{ 65 ia64_expand_atomic_op (NOT, operands[0], operands[1], NULL, NULL); 66 DONE; 67}) 68 69(define_expand "sync_old_<fetchop_name><mode>" 70 [(set (match_operand:IMODE 0 "gr_register_operand" "") 71 (FETCHOP:IMODE 72 (match_operand:IMODE 1 "memory_operand" "") 73 (match_operand:IMODE 2 "general_operand" "")))] 74 "" 75{ 76 ia64_expand_atomic_op (<CODE>, operands[1], operands[2], operands[0], NULL); 77 DONE; 78}) 79 80(define_expand "sync_old_nand<mode>" 81 [(set (match_operand:IMODE 0 "gr_register_operand" "") 82 (and:IMODE 83 (not:IMODE (match_operand:IMODE 1 "memory_operand" "")) 84 (match_operand:IMODE 2 "general_operand" "")))] 85 "" 86{ 87 ia64_expand_atomic_op (NOT, operands[1], operands[2], operands[0], NULL); 88 DONE; 89}) 90 91(define_expand "sync_new_<fetchop_name><mode>" 92 [(set (match_operand:IMODE 0 "gr_register_operand" "") 93 (FETCHOP:IMODE 94 (match_operand:IMODE 1 "memory_operand" "") 95 (match_operand:IMODE 2 "general_operand" "")))] 96 "" 97{ 98 ia64_expand_atomic_op (<CODE>, operands[1], operands[2], NULL, operands[0]); 99 DONE; 100}) 101 102(define_expand "sync_new_nand<mode>" 103 [(set (match_operand:IMODE 0 "gr_register_operand" "") 104 (and:IMODE 105 (not:IMODE (match_operand:IMODE 1 "memory_operand" "")) 106 (match_operand:IMODE 2 "general_operand" "")))] 107 "" 108{ 109 ia64_expand_atomic_op (NOT, operands[1], operands[2], NULL, operands[0]); 110 DONE; 111}) 112 113(define_expand "sync_compare_and_swap<mode>" 114 [(match_operand:IMODE 0 "gr_register_operand" "") 115 (match_operand:IMODE 1 "memory_operand" "") 116 (match_operand:IMODE 2 "gr_register_operand" "") 117 (match_operand:IMODE 3 "gr_register_operand" "")] 118 "" 119{ 120 rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM); 121 rtx dst; 122 123 convert_move (ccv, operands[2], 1); 124 125 dst = operands[0]; 126 if (GET_MODE (dst) != DImode) 127 dst = gen_reg_rtx (DImode); 128 129 emit_insn (gen_memory_barrier ()); 130 emit_insn (gen_cmpxchg_rel_<mode> (dst, operands[1], ccv, operands[3])); 131 132 if (dst != operands[0]) 133 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, dst)); 134 DONE; 135}) 136 137(define_insn "cmpxchg_rel_<mode>" 138 [(set (match_operand:DI 0 "gr_register_operand" "=r") 139 (zero_extend:DI 140 (match_operand:I124MODE 1 "not_postinc_memory_operand" "+S"))) 141 (set (match_dup 1) 142 (unspec:I124MODE 143 [(match_dup 1) 144 (match_operand:DI 2 "ar_ccv_reg_operand" "") 145 (match_operand:I124MODE 3 "gr_register_operand" "r")] 146 UNSPEC_CMPXCHG_ACQ))] 147 "" 148 "cmpxchg<modesuffix>.rel %0 = %1, %3, %2" 149 [(set_attr "itanium_class" "sem")]) 150 151(define_insn "cmpxchg_rel_di" 152 [(set (match_operand:DI 0 "gr_register_operand" "=r") 153 (match_operand:DI 1 "not_postinc_memory_operand" "+S")) 154 (set (match_dup 1) 155 (unspec:DI [(match_dup 1) 156 (match_operand:DI 2 "ar_ccv_reg_operand" "") 157 (match_operand:DI 3 "gr_register_operand" "r")] 158 UNSPEC_CMPXCHG_ACQ))] 159 "" 160 "cmpxchg8.rel %0 = %1, %3, %2" 161 [(set_attr "itanium_class" "sem")]) 162 163(define_insn "sync_lock_test_and_set<mode>" 164 [(set (match_operand:IMODE 0 "gr_register_operand" "=r") 165 (match_operand:IMODE 1 "not_postinc_memory_operand" "+S")) 166 (set (match_dup 1) 167 (match_operand:IMODE 2 "gr_register_operand" "r"))] 168 "" 169 "xchg<modesuffix> %0 = %1, %2" 170 [(set_attr "itanium_class" "sem")]) 171 172(define_expand "sync_lock_release<mode>" 173 [(set (match_operand:IMODE 0 "memory_operand" "") 174 (match_operand:IMODE 1 "gr_reg_or_0_operand" ""))] 175 "" 176{ 177 gcc_assert (MEM_VOLATILE_P (operands[0])); 178}) 179