combine.c revision 96263
1193323Sed/* Optimize by combining instructions for GNU compiler. 2193323Sed Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3193323Sed 1999, 2000, 2001, 2002 Free Software Foundation, Inc. 4193323Sed 5193323SedThis file is part of GCC. 6193323Sed 7193323SedGCC is free software; you can redistribute it and/or modify it under 8193323Sedthe terms of the GNU General Public License as published by the Free 9193323SedSoftware Foundation; either version 2, or (at your option) any later 10193323Sedversion. 11193323Sed 12193323SedGCC is distributed in the hope that it will be useful, but WITHOUT ANY 13193323SedWARRANTY; without even the implied warranty of MERCHANTABILITY or 14193323SedFITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15212904Sdimfor more details. 16249423Sdim 17249423SdimYou should have received a copy of the GNU General Public License 18249423Sdimalong with GCC; see the file COPYING. If not, write to the Free 19249423SdimSoftware Foundation, 59 Temple Place - Suite 330, Boston, MA 20249423Sdim02111-1307, USA. */ 21193323Sed 22193323Sed/* This module is essentially the "combiner" phase of the U. of Arizona 23193323Sed Portable Optimizer, but redone to work on our list-structured 24263508Sdim representation for RTL instead of their string representation. 25263508Sdim 26263508Sdim The LOG_LINKS of each insn identify the most recent assignment 27263508Sdim to each REG used in the insn. It is a list of previous insns, 28263508Sdim each of which contains a SET for a REG that is used in this insn 29263508Sdim and not used or set in between. LOG_LINKs never cross basic blocks. 30263508Sdim They were set up by the preceding pass (lifetime analysis). 31263508Sdim 32263508Sdim We try to combine each pair of insns joined by a logical link. 33263508Sdim We also try to combine triples of insns A, B and C when 34263508Sdim C has a link back to B and B has a link back to A. 35263508Sdim 36263508Sdim LOG_LINKS does not have links for use of the CC0. They don't 37263508Sdim need to, because the insn that sets the CC0 is always immediately 38263508Sdim before the insn that tests it. So we always regard a branch 39263508Sdim insn as having a logical link to the preceding insn. The same is true 40263508Sdim for an insn explicitly using CC0. 41263508Sdim 42263508Sdim We check (with use_crosses_set_p) to avoid combining in such a way 43263508Sdim as to move a computation to a place where its value would be different. 44263508Sdim 45263508Sdim Combination is done by mathematically substituting the previous 46263508Sdim insn(s) values for the regs they set into the expressions in 47263508Sdim the later insns that refer to these regs. If the result is a valid insn 48263508Sdim for our target machine, according to the machine description, 49263508Sdim we install it, delete the earlier insns, and update the data flow 50263508Sdim information (LOG_LINKS and REG_NOTES) for what we did. 51263508Sdim 52263508Sdim There are a few exceptions where the dataflow information created by 53263508Sdim flow.c aren't completely updated: 54263508Sdim 55263508Sdim - reg_live_length is not updated 56193323Sed - reg_n_refs is not adjusted in the rare case when a register is 57193323Sed no longer required in a computation 58198892Srdivacky - there are extremely rare cases (see distribute_regnotes) when a 59212904Sdim REG_DEAD note is lost 60193323Sed - a LOG_LINKS entry that refers to an insn with multiple SETs may be 61193323Sed removed because there is no way to know which register it was 62193323Sed linking 63193323Sed 64193323Sed To simplify substitution, we combine only when the earlier insn(s) 65193323Sed consist of only a single assignment. To simplify updating afterward, 66193323Sed we never combine when a subroutine call appears in the middle. 67193323Sed 68212904Sdim Since we do not represent assignments to CC0 explicitly except when that 69212904Sdim is all an insn does, there is no LOG_LINKS entry in an insn that uses 70193323Sed the condition code for the insn that set the condition code. 71193323Sed Fortunately, these two insns must be consecutive. 72212904Sdim Therefore, every JUMP_INSN is taken to have an implicit logical link 73212904Sdim to the preceding insn. This is not quite right, since non-jumps can 74212904Sdim also use the condition code; but in practice such insns would not 75193323Sed combine anyway. */ 76212904Sdim 77212904Sdim#include "config.h" 78212904Sdim#include "system.h" 79212904Sdim#include "rtl.h" 80212904Sdim#include "tm_p.h" 81212904Sdim#include "flags.h" 82193323Sed#include "regs.h" 83212904Sdim#include "hard-reg-set.h" 84212904Sdim#include "basic-block.h" 85218893Sdim#include "insn-config.h" 86243830Sdim#include "function.h" 87243830Sdim/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ 88243830Sdim#include "expr.h" 89239462Sdim#include "insn-attr.h" 90239462Sdim#include "recog.h" 91239462Sdim#include "real.h" 92239462Sdim#include "toplev.h" 93239462Sdim 94223017Sdim/* It is not safe to use ordinary gen_lowpart in combine. 95263508Sdim Use gen_lowpart_for_combine instead. See comments there. */ 96243830Sdim#define gen_lowpart dont_use_gen_lowpart_you_dummy 97243830Sdim 98243830Sdim/* Number of attempts to combine instructions in this function. */ 99218893Sdim 100212904Sdimstatic int combine_attempts; 101212904Sdim 102218893Sdim/* Number of attempts that got as far as substitution in this function. */ 103243830Sdim 104243830Sdimstatic int combine_merges; 105243830Sdim 106239462Sdim/* Number of instructions combined with added SETs in this function. */ 107239462Sdim 108239462Sdimstatic int combine_extras; 109223017Sdim 110263508Sdim/* Number of instructions combined in this function. */ 111243830Sdim 112243830Sdimstatic int combine_successes; 113243830Sdim 114218893Sdim/* Totals over entire compilation. */ 115193323Sed 116243830Sdimstatic int total_attempts, total_merges, total_extras, total_successes; 117243830Sdim 118243830Sdim 119243830Sdim/* Vector mapping INSN_UIDs to cuids. 120243830Sdim The cuids are like uids but increase monotonically always. 121243830Sdim Combine always uses cuids so that it can compare them. 122263508Sdim But actually renumbering the uids, which we used to do, 123263508Sdim proves to be a bad idea because it makes it hard to compare 124243830Sdim the dumps produced by earlier passes with those from later passes. */ 125263508Sdim 126243830Sdimstatic int *uid_cuid; 127243830Sdimstatic int max_uid_cuid; 128243830Sdim 129243830Sdim/* Get the cuid of an insn. */ 130243830Sdim 131243830Sdim#define INSN_CUID(INSN) \ 132243830Sdim(INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)]) 133243830Sdim 134243830Sdim/* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by 135243830Sdim BITS_PER_WORD would invoke undefined behavior. Work around it. */ 136243830Sdim 137243830Sdim#define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \ 138243830Sdim (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1) 139243830Sdim 140243830Sdim/* Maximum register number, which is the size of the tables below. */ 141243830Sdim 142243830Sdimstatic unsigned int combine_max_regno; 143243830Sdim 144243830Sdim/* Record last point of death of (hard or pseudo) register n. */ 145193323Sed 146193323Sedstatic rtx *reg_last_death; 147193323Sed 148193323Sed/* Record last point of modification of (hard or pseudo) register n. */ 149193323Sed 150193323Sedstatic rtx *reg_last_set; 151193323Sed 152193323Sed/* Record the cuid of the last insn that invalidated memory 153212904Sdim (anything that writes memory, and subroutine calls, but not pushes). */ 154212904Sdim 155193323Sedstatic int mem_last_set; 156 157/* Record the cuid of the last CALL_INSN 158 so we can tell whether a potential combination crosses any calls. */ 159 160static int last_call_cuid; 161 162/* When `subst' is called, this is the insn that is being modified 163 (by combining in a previous insn). The PATTERN of this insn 164 is still the old pattern partially modified and it should not be 165 looked at, but this may be used to examine the successors of the insn 166 to judge whether a simplification is valid. */ 167 168static rtx subst_insn; 169 170/* This is an insn that belongs before subst_insn, but is not currently 171 on the insn chain. */ 172 173static rtx subst_prev_insn; 174 175/* This is the lowest CUID that `subst' is currently dealing with. 176 get_last_value will not return a value if the register was set at or 177 after this CUID. If not for this mechanism, we could get confused if 178 I2 or I1 in try_combine were an insn that used the old value of a register 179 to obtain a new value. In that case, we might erroneously get the 180 new value of the register when we wanted the old one. */ 181 182static int subst_low_cuid; 183 184/* This contains any hard registers that are used in newpat; reg_dead_at_p 185 must consider all these registers to be always live. */ 186 187static HARD_REG_SET newpat_used_regs; 188 189/* This is an insn to which a LOG_LINKS entry has been added. If this 190 insn is the earlier than I2 or I3, combine should rescan starting at 191 that location. */ 192 193static rtx added_links_insn; 194 195/* Basic block number of the block in which we are performing combines. */ 196static int this_basic_block; 197 198/* A bitmap indicating which blocks had registers go dead at entry. 199 After combine, we'll need to re-do global life analysis with 200 those blocks as starting points. */ 201static sbitmap refresh_blocks; 202static int need_refresh; 203 204/* The next group of arrays allows the recording of the last value assigned 205 to (hard or pseudo) register n. We use this information to see if a 206 operation being processed is redundant given a prior operation performed 207 on the register. For example, an `and' with a constant is redundant if 208 all the zero bits are already known to be turned off. 209 210 We use an approach similar to that used by cse, but change it in the 211 following ways: 212 213 (1) We do not want to reinitialize at each label. 214 (2) It is useful, but not critical, to know the actual value assigned 215 to a register. Often just its form is helpful. 216 217 Therefore, we maintain the following arrays: 218 219 reg_last_set_value the last value assigned 220 reg_last_set_label records the value of label_tick when the 221 register was assigned 222 reg_last_set_table_tick records the value of label_tick when a 223 value using the register is assigned 224 reg_last_set_invalid set to non-zero when it is not valid 225 to use the value of this register in some 226 register's value 227 228 To understand the usage of these tables, it is important to understand 229 the distinction between the value in reg_last_set_value being valid 230 and the register being validly contained in some other expression in the 231 table. 232 233 Entry I in reg_last_set_value is valid if it is non-zero, and either 234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick. 235 236 Register I may validly appear in any expression returned for the value 237 of another register if reg_n_sets[i] is 1. It may also appear in the 238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or 239 reg_last_set_invalid[j] is zero. 240 241 If an expression is found in the table containing a register which may 242 not validly appear in an expression, the register is replaced by 243 something that won't match, (clobber (const_int 0)). 244 245 reg_last_set_invalid[i] is set non-zero when register I is being assigned 246 to and reg_last_set_table_tick[i] == label_tick. */ 247 248/* Record last value assigned to (hard or pseudo) register n. */ 249 250static rtx *reg_last_set_value; 251 252/* Record the value of label_tick when the value for register n is placed in 253 reg_last_set_value[n]. */ 254 255static int *reg_last_set_label; 256 257/* Record the value of label_tick when an expression involving register n 258 is placed in reg_last_set_value. */ 259 260static int *reg_last_set_table_tick; 261 262/* Set non-zero if references to register n in expressions should not be 263 used. */ 264 265static char *reg_last_set_invalid; 266 267/* Incremented for each label. */ 268 269static int label_tick; 270 271/* Some registers that are set more than once and used in more than one 272 basic block are nevertheless always set in similar ways. For example, 273 a QImode register may be loaded from memory in two places on a machine 274 where byte loads zero extend. 275 276 We record in the following array what we know about the nonzero 277 bits of a register, specifically which bits are known to be zero. 278 279 If an entry is zero, it means that we don't know anything special. */ 280 281static unsigned HOST_WIDE_INT *reg_nonzero_bits; 282 283/* Mode used to compute significance in reg_nonzero_bits. It is the largest 284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ 285 286static enum machine_mode nonzero_bits_mode; 287 288/* Nonzero if we know that a register has some leading bits that are always 289 equal to the sign bit. */ 290 291static unsigned char *reg_sign_bit_copies; 292 293/* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used. 294 It is zero while computing them and after combine has completed. This 295 former test prevents propagating values based on previously set values, 296 which can be incorrect if a variable is modified in a loop. */ 297 298static int nonzero_sign_valid; 299 300/* These arrays are maintained in parallel with reg_last_set_value 301 and are used to store the mode in which the register was last set, 302 the bits that were known to be zero when it was last set, and the 303 number of sign bits copies it was known to have when it was last set. */ 304 305static enum machine_mode *reg_last_set_mode; 306static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits; 307static char *reg_last_set_sign_bit_copies; 308 309/* Record one modification to rtl structure 310 to be undone by storing old_contents into *where. 311 is_int is 1 if the contents are an int. */ 312 313struct undo 314{ 315 struct undo *next; 316 int is_int; 317 union {rtx r; unsigned int i;} old_contents; 318 union {rtx *r; unsigned int *i;} where; 319}; 320 321/* Record a bunch of changes to be undone, up to MAX_UNDO of them. 322 num_undo says how many are currently recorded. 323 324 other_insn is nonzero if we have modified some other insn in the process 325 of working on subst_insn. It must be verified too. */ 326 327struct undobuf 328{ 329 struct undo *undos; 330 struct undo *frees; 331 rtx other_insn; 332}; 333 334static struct undobuf undobuf; 335 336/* Number of times the pseudo being substituted for 337 was found and replaced. */ 338 339static int n_occurrences; 340 341static void do_SUBST PARAMS ((rtx *, rtx)); 342static void do_SUBST_INT PARAMS ((unsigned int *, 343 unsigned int)); 344static void init_reg_last_arrays PARAMS ((void)); 345static void setup_incoming_promotions PARAMS ((void)); 346static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *)); 347static int cant_combine_insn_p PARAMS ((rtx)); 348static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *)); 349static int sets_function_arg_p PARAMS ((rtx)); 350static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *)); 351static int contains_muldiv PARAMS ((rtx)); 352static rtx try_combine PARAMS ((rtx, rtx, rtx, int *)); 353static void undo_all PARAMS ((void)); 354static void undo_commit PARAMS ((void)); 355static rtx *find_split_point PARAMS ((rtx *, rtx)); 356static rtx subst PARAMS ((rtx, rtx, rtx, int, int)); 357static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int)); 358static rtx simplify_if_then_else PARAMS ((rtx)); 359static rtx simplify_set PARAMS ((rtx)); 360static rtx simplify_logical PARAMS ((rtx, int)); 361static rtx expand_compound_operation PARAMS ((rtx)); 362static rtx expand_field_assignment PARAMS ((rtx)); 363static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT, 364 rtx, unsigned HOST_WIDE_INT, int, 365 int, int)); 366static rtx extract_left_shift PARAMS ((rtx, int)); 367static rtx make_compound_operation PARAMS ((rtx, enum rtx_code)); 368static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT, 369 unsigned HOST_WIDE_INT *)); 370static rtx force_to_mode PARAMS ((rtx, enum machine_mode, 371 unsigned HOST_WIDE_INT, rtx, int)); 372static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *)); 373static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx)); 374static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx)); 375static rtx make_field_assignment PARAMS ((rtx)); 376static rtx apply_distributive_law PARAMS ((rtx)); 377static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx, 378 unsigned HOST_WIDE_INT)); 379static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode)); 380static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode)); 381static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *, 382 enum rtx_code, HOST_WIDE_INT, 383 enum machine_mode, int *)); 384static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode, 385 rtx, int)); 386static int recog_for_combine PARAMS ((rtx *, rtx, rtx *)); 387static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx)); 388static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode, 389 rtx, rtx)); 390static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *)); 391static void update_table_tick PARAMS ((rtx)); 392static void record_value_for_reg PARAMS ((rtx, rtx, rtx)); 393static void check_promoted_subreg PARAMS ((rtx, rtx)); 394static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *)); 395static void record_dead_and_set_regs PARAMS ((rtx)); 396static int get_last_value_validate PARAMS ((rtx *, rtx, int, int)); 397static rtx get_last_value PARAMS ((rtx)); 398static int use_crosses_set_p PARAMS ((rtx, int)); 399static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *)); 400static int reg_dead_at_p PARAMS ((rtx, rtx)); 401static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *)); 402static int reg_bitfield_target_p PARAMS ((rtx, rtx)); 403static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx)); 404static void distribute_links PARAMS ((rtx)); 405static void mark_used_regs_combine PARAMS ((rtx)); 406static int insn_cuid PARAMS ((rtx)); 407static void record_promoted_value PARAMS ((rtx, rtx)); 408static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx)); 409static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx)); 410 411/* Substitute NEWVAL, an rtx expression, into INTO, a place in some 412 insn. The substitution can be undone by undo_all. If INTO is already 413 set to NEWVAL, do not record this change. Because computing NEWVAL might 414 also call SUBST, we have to compute it before we put anything into 415 the undo table. */ 416 417static void 418do_SUBST (into, newval) 419 rtx *into, newval; 420{ 421 struct undo *buf; 422 rtx oldval = *into; 423 424 if (oldval == newval) 425 return; 426 427 /* We'd like to catch as many invalid transformations here as 428 possible. Unfortunately, there are way too many mode changes 429 that are perfectly valid, so we'd waste too much effort for 430 little gain doing the checks here. Focus on catching invalid 431 transformations involving integer constants. */ 432 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT 433 && GET_CODE (newval) == CONST_INT) 434 { 435 /* Sanity check that we're replacing oldval with a CONST_INT 436 that is a valid sign-extension for the original mode. */ 437 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval), 438 GET_MODE (oldval))) 439 abort (); 440 441 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a 442 CONST_INT is not valid, because after the replacement, the 443 original mode would be gone. Unfortunately, we can't tell 444 when do_SUBST is called to replace the operand thereof, so we 445 perform this test on oldval instead, checking whether an 446 invalid replacement took place before we got here. */ 447 if ((GET_CODE (oldval) == SUBREG 448 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT) 449 || (GET_CODE (oldval) == ZERO_EXTEND 450 && GET_CODE (XEXP (oldval, 0)) == CONST_INT)) 451 abort (); 452 } 453 454 if (undobuf.frees) 455 buf = undobuf.frees, undobuf.frees = buf->next; 456 else 457 buf = (struct undo *) xmalloc (sizeof (struct undo)); 458 459 buf->is_int = 0; 460 buf->where.r = into; 461 buf->old_contents.r = oldval; 462 *into = newval; 463 464 buf->next = undobuf.undos, undobuf.undos = buf; 465} 466 467#define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL)) 468 469/* Similar to SUBST, but NEWVAL is an int expression. Note that substitution 470 for the value of a HOST_WIDE_INT value (including CONST_INT) is 471 not safe. */ 472 473static void 474do_SUBST_INT (into, newval) 475 unsigned int *into, newval; 476{ 477 struct undo *buf; 478 unsigned int oldval = *into; 479 480 if (oldval == newval) 481 return; 482 483 if (undobuf.frees) 484 buf = undobuf.frees, undobuf.frees = buf->next; 485 else 486 buf = (struct undo *) xmalloc (sizeof (struct undo)); 487 488 buf->is_int = 1; 489 buf->where.i = into; 490 buf->old_contents.i = oldval; 491 *into = newval; 492 493 buf->next = undobuf.undos, undobuf.undos = buf; 494} 495 496#define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL)) 497 498/* Main entry point for combiner. F is the first insn of the function. 499 NREGS is the first unused pseudo-reg number. 500 501 Return non-zero if the combiner has turned an indirect jump 502 instruction into a direct jump. */ 503int 504combine_instructions (f, nregs) 505 rtx f; 506 unsigned int nregs; 507{ 508 rtx insn, next; 509#ifdef HAVE_cc0 510 rtx prev; 511#endif 512 int i; 513 rtx links, nextlinks; 514 515 int new_direct_jump_p = 0; 516 517 combine_attempts = 0; 518 combine_merges = 0; 519 combine_extras = 0; 520 combine_successes = 0; 521 522 combine_max_regno = nregs; 523 524 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *) 525 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT))); 526 reg_sign_bit_copies 527 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char)); 528 529 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx)); 530 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx)); 531 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx)); 532 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int)); 533 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int)); 534 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char)); 535 reg_last_set_mode 536 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode)); 537 reg_last_set_nonzero_bits 538 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT)); 539 reg_last_set_sign_bit_copies 540 = (char *) xmalloc (nregs * sizeof (char)); 541 542 init_reg_last_arrays (); 543 544 init_recog_no_volatile (); 545 546 /* Compute maximum uid value so uid_cuid can be allocated. */ 547 548 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) 549 if (INSN_UID (insn) > i) 550 i = INSN_UID (insn); 551 552 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int)); 553 max_uid_cuid = i; 554 555 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); 556 557 /* Don't use reg_nonzero_bits when computing it. This can cause problems 558 when, for example, we have j <<= 1 in a loop. */ 559 560 nonzero_sign_valid = 0; 561 562 /* Compute the mapping from uids to cuids. 563 Cuids are numbers assigned to insns, like uids, 564 except that cuids increase monotonically through the code. 565 566 Scan all SETs and see if we can deduce anything about what 567 bits are known to be zero for some registers and how many copies 568 of the sign bit are known to exist for those registers. 569 570 Also set any known values so that we can use it while searching 571 for what bits are known to be set. */ 572 573 label_tick = 1; 574 575 /* We need to initialize it here, because record_dead_and_set_regs may call 576 get_last_value. */ 577 subst_prev_insn = NULL_RTX; 578 579 setup_incoming_promotions (); 580 581 refresh_blocks = sbitmap_alloc (n_basic_blocks); 582 sbitmap_zero (refresh_blocks); 583 need_refresh = 0; 584 585 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) 586 { 587 uid_cuid[INSN_UID (insn)] = ++i; 588 subst_low_cuid = i; 589 subst_insn = insn; 590 591 if (INSN_P (insn)) 592 { 593 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies, 594 NULL); 595 record_dead_and_set_regs (insn); 596 597#ifdef AUTO_INC_DEC 598 for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) 599 if (REG_NOTE_KIND (links) == REG_INC) 600 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX, 601 NULL); 602#endif 603 } 604 605 if (GET_CODE (insn) == CODE_LABEL) 606 label_tick++; 607 } 608 609 nonzero_sign_valid = 1; 610 611 /* Now scan all the insns in forward order. */ 612 613 this_basic_block = -1; 614 label_tick = 1; 615 last_call_cuid = 0; 616 mem_last_set = 0; 617 init_reg_last_arrays (); 618 setup_incoming_promotions (); 619 620 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn)) 621 { 622 next = 0; 623 624 /* If INSN starts a new basic block, update our basic block number. */ 625 if (this_basic_block + 1 < n_basic_blocks 626 && BLOCK_HEAD (this_basic_block + 1) == insn) 627 this_basic_block++; 628 629 if (GET_CODE (insn) == CODE_LABEL) 630 label_tick++; 631 632 else if (INSN_P (insn)) 633 { 634 /* See if we know about function return values before this 635 insn based upon SUBREG flags. */ 636 check_promoted_subreg (insn, PATTERN (insn)); 637 638 /* Try this insn with each insn it links back to. */ 639 640 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 641 if ((next = try_combine (insn, XEXP (links, 0), 642 NULL_RTX, &new_direct_jump_p)) != 0) 643 goto retry; 644 645 /* Try each sequence of three linked insns ending with this one. */ 646 647 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 648 { 649 rtx link = XEXP (links, 0); 650 651 /* If the linked insn has been replaced by a note, then there 652 is no point in pursuing this chain any further. */ 653 if (GET_CODE (link) == NOTE) 654 continue; 655 656 for (nextlinks = LOG_LINKS (link); 657 nextlinks; 658 nextlinks = XEXP (nextlinks, 1)) 659 if ((next = try_combine (insn, link, 660 XEXP (nextlinks, 0), 661 &new_direct_jump_p)) != 0) 662 goto retry; 663 } 664 665#ifdef HAVE_cc0 666 /* Try to combine a jump insn that uses CC0 667 with a preceding insn that sets CC0, and maybe with its 668 logical predecessor as well. 669 This is how we make decrement-and-branch insns. 670 We need this special code because data flow connections 671 via CC0 do not get entered in LOG_LINKS. */ 672 673 if (GET_CODE (insn) == JUMP_INSN 674 && (prev = prev_nonnote_insn (insn)) != 0 675 && GET_CODE (prev) == INSN 676 && sets_cc0_p (PATTERN (prev))) 677 { 678 if ((next = try_combine (insn, prev, 679 NULL_RTX, &new_direct_jump_p)) != 0) 680 goto retry; 681 682 for (nextlinks = LOG_LINKS (prev); nextlinks; 683 nextlinks = XEXP (nextlinks, 1)) 684 if ((next = try_combine (insn, prev, 685 XEXP (nextlinks, 0), 686 &new_direct_jump_p)) != 0) 687 goto retry; 688 } 689 690 /* Do the same for an insn that explicitly references CC0. */ 691 if (GET_CODE (insn) == INSN 692 && (prev = prev_nonnote_insn (insn)) != 0 693 && GET_CODE (prev) == INSN 694 && sets_cc0_p (PATTERN (prev)) 695 && GET_CODE (PATTERN (insn)) == SET 696 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) 697 { 698 if ((next = try_combine (insn, prev, 699 NULL_RTX, &new_direct_jump_p)) != 0) 700 goto retry; 701 702 for (nextlinks = LOG_LINKS (prev); nextlinks; 703 nextlinks = XEXP (nextlinks, 1)) 704 if ((next = try_combine (insn, prev, 705 XEXP (nextlinks, 0), 706 &new_direct_jump_p)) != 0) 707 goto retry; 708 } 709 710 /* Finally, see if any of the insns that this insn links to 711 explicitly references CC0. If so, try this insn, that insn, 712 and its predecessor if it sets CC0. */ 713 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 714 if (GET_CODE (XEXP (links, 0)) == INSN 715 && GET_CODE (PATTERN (XEXP (links, 0))) == SET 716 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0)))) 717 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0 718 && GET_CODE (prev) == INSN 719 && sets_cc0_p (PATTERN (prev)) 720 && (next = try_combine (insn, XEXP (links, 0), 721 prev, &new_direct_jump_p)) != 0) 722 goto retry; 723#endif 724 725 /* Try combining an insn with two different insns whose results it 726 uses. */ 727 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 728 for (nextlinks = XEXP (links, 1); nextlinks; 729 nextlinks = XEXP (nextlinks, 1)) 730 if ((next = try_combine (insn, XEXP (links, 0), 731 XEXP (nextlinks, 0), 732 &new_direct_jump_p)) != 0) 733 goto retry; 734 735 if (GET_CODE (insn) != NOTE) 736 record_dead_and_set_regs (insn); 737 738 retry: 739 ; 740 } 741 } 742 743 delete_noop_moves (f); 744 745 if (need_refresh) 746 { 747 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES, 748 PROP_DEATH_NOTES); 749 } 750 751 /* Clean up. */ 752 sbitmap_free (refresh_blocks); 753 free (reg_nonzero_bits); 754 free (reg_sign_bit_copies); 755 free (reg_last_death); 756 free (reg_last_set); 757 free (reg_last_set_value); 758 free (reg_last_set_table_tick); 759 free (reg_last_set_label); 760 free (reg_last_set_invalid); 761 free (reg_last_set_mode); 762 free (reg_last_set_nonzero_bits); 763 free (reg_last_set_sign_bit_copies); 764 free (uid_cuid); 765 766 { 767 struct undo *undo, *next; 768 for (undo = undobuf.frees; undo; undo = next) 769 { 770 next = undo->next; 771 free (undo); 772 } 773 undobuf.frees = 0; 774 } 775 776 total_attempts += combine_attempts; 777 total_merges += combine_merges; 778 total_extras += combine_extras; 779 total_successes += combine_successes; 780 781 nonzero_sign_valid = 0; 782 783 /* Make recognizer allow volatile MEMs again. */ 784 init_recog (); 785 786 return new_direct_jump_p; 787} 788 789/* Wipe the reg_last_xxx arrays in preparation for another pass. */ 790 791static void 792init_reg_last_arrays () 793{ 794 unsigned int nregs = combine_max_regno; 795 796 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx)); 797 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx)); 798 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx)); 799 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int)); 800 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int)); 801 memset (reg_last_set_invalid, 0, nregs * sizeof (char)); 802 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode)); 803 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT)); 804 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char)); 805} 806 807/* Set up any promoted values for incoming argument registers. */ 808 809static void 810setup_incoming_promotions () 811{ 812#ifdef PROMOTE_FUNCTION_ARGS 813 unsigned int regno; 814 rtx reg; 815 enum machine_mode mode; 816 int unsignedp; 817 rtx first = get_insns (); 818 819#ifndef OUTGOING_REGNO 820#define OUTGOING_REGNO(N) N 821#endif 822 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 823 /* Check whether this register can hold an incoming pointer 824 argument. FUNCTION_ARG_REGNO_P tests outgoing register 825 numbers, so translate if necessary due to register windows. */ 826 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno)) 827 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0) 828 { 829 record_value_for_reg 830 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND 831 : SIGN_EXTEND), 832 GET_MODE (reg), 833 gen_rtx_CLOBBER (mode, const0_rtx))); 834 } 835#endif 836} 837 838/* Called via note_stores. If X is a pseudo that is narrower than 839 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. 840 841 If we are setting only a portion of X and we can't figure out what 842 portion, assume all bits will be used since we don't know what will 843 be happening. 844 845 Similarly, set how many bits of X are known to be copies of the sign bit 846 at all locations in the function. This is the smallest number implied 847 by any set of X. */ 848 849static void 850set_nonzero_bits_and_sign_copies (x, set, data) 851 rtx x; 852 rtx set; 853 void *data ATTRIBUTE_UNUSED; 854{ 855 unsigned int num; 856 857 if (GET_CODE (x) == REG 858 && REGNO (x) >= FIRST_PSEUDO_REGISTER 859 /* If this register is undefined at the start of the file, we can't 860 say what its contents were. */ 861 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x)) 862 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) 863 { 864 if (set == 0 || GET_CODE (set) == CLOBBER) 865 { 866 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); 867 reg_sign_bit_copies[REGNO (x)] = 1; 868 return; 869 } 870 871 /* If this is a complex assignment, see if we can convert it into a 872 simple assignment. */ 873 set = expand_field_assignment (set); 874 875 /* If this is a simple assignment, or we have a paradoxical SUBREG, 876 set what we know about X. */ 877 878 if (SET_DEST (set) == x 879 || (GET_CODE (SET_DEST (set)) == SUBREG 880 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set))) 881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set))))) 882 && SUBREG_REG (SET_DEST (set)) == x)) 883 { 884 rtx src = SET_SRC (set); 885 886#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 887 /* If X is narrower than a word and SRC is a non-negative 888 constant that would appear negative in the mode of X, 889 sign-extend it for use in reg_nonzero_bits because some 890 machines (maybe most) will actually do the sign-extension 891 and this is the conservative approach. 892 893 ??? For 2.5, try to tighten up the MD files in this regard 894 instead of this kludge. */ 895 896 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD 897 && GET_CODE (src) == CONST_INT 898 && INTVAL (src) > 0 899 && 0 != (INTVAL (src) 900 & ((HOST_WIDE_INT) 1 901 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 902 src = GEN_INT (INTVAL (src) 903 | ((HOST_WIDE_INT) (-1) 904 << GET_MODE_BITSIZE (GET_MODE (x)))); 905#endif 906 907 /* Don't call nonzero_bits if it cannot change anything. */ 908 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0) 909 reg_nonzero_bits[REGNO (x)] 910 |= nonzero_bits (src, nonzero_bits_mode); 911 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); 912 if (reg_sign_bit_copies[REGNO (x)] == 0 913 || reg_sign_bit_copies[REGNO (x)] > num) 914 reg_sign_bit_copies[REGNO (x)] = num; 915 } 916 else 917 { 918 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); 919 reg_sign_bit_copies[REGNO (x)] = 1; 920 } 921 } 922} 923 924/* See if INSN can be combined into I3. PRED and SUCC are optionally 925 insns that were previously combined into I3 or that will be combined 926 into the merger of INSN and I3. 927 928 Return 0 if the combination is not allowed for any reason. 929 930 If the combination is allowed, *PDEST will be set to the single 931 destination of INSN and *PSRC to the single source, and this function 932 will return 1. */ 933 934static int 935can_combine_p (insn, i3, pred, succ, pdest, psrc) 936 rtx insn; 937 rtx i3; 938 rtx pred ATTRIBUTE_UNUSED; 939 rtx succ; 940 rtx *pdest, *psrc; 941{ 942 int i; 943 rtx set = 0, src, dest; 944 rtx p; 945#ifdef AUTO_INC_DEC 946 rtx link; 947#endif 948 int all_adjacent = (succ ? (next_active_insn (insn) == succ 949 && next_active_insn (succ) == i3) 950 : next_active_insn (insn) == i3); 951 952 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. 953 or a PARALLEL consisting of such a SET and CLOBBERs. 954 955 If INSN has CLOBBER parallel parts, ignore them for our processing. 956 By definition, these happen during the execution of the insn. When it 957 is merged with another insn, all bets are off. If they are, in fact, 958 needed and aren't also supplied in I3, they may be added by 959 recog_for_combine. Otherwise, it won't match. 960 961 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED 962 note. 963 964 Get the source and destination of INSN. If more than one, can't 965 combine. */ 966 967 if (GET_CODE (PATTERN (insn)) == SET) 968 set = PATTERN (insn); 969 else if (GET_CODE (PATTERN (insn)) == PARALLEL 970 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) 971 { 972 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) 973 { 974 rtx elt = XVECEXP (PATTERN (insn), 0, i); 975 976 switch (GET_CODE (elt)) 977 { 978 /* This is important to combine floating point insns 979 for the SH4 port. */ 980 case USE: 981 /* Combining an isolated USE doesn't make sense. 982 We depend here on combinable_i3pat to reject them. */ 983 /* The code below this loop only verifies that the inputs of 984 the SET in INSN do not change. We call reg_set_between_p 985 to verify that the REG in the USE does not change between 986 I3 and INSN. 987 If the USE in INSN was for a pseudo register, the matching 988 insn pattern will likely match any register; combining this 989 with any other USE would only be safe if we knew that the 990 used registers have identical values, or if there was 991 something to tell them apart, e.g. different modes. For 992 now, we forgo such complicated tests and simply disallow 993 combining of USES of pseudo registers with any other USE. */ 994 if (GET_CODE (XEXP (elt, 0)) == REG 995 && GET_CODE (PATTERN (i3)) == PARALLEL) 996 { 997 rtx i3pat = PATTERN (i3); 998 int i = XVECLEN (i3pat, 0) - 1; 999 unsigned int regno = REGNO (XEXP (elt, 0)); 1000 1001 do 1002 { 1003 rtx i3elt = XVECEXP (i3pat, 0, i); 1004 1005 if (GET_CODE (i3elt) == USE 1006 && GET_CODE (XEXP (i3elt, 0)) == REG 1007 && (REGNO (XEXP (i3elt, 0)) == regno 1008 ? reg_set_between_p (XEXP (elt, 0), 1009 PREV_INSN (insn), i3) 1010 : regno >= FIRST_PSEUDO_REGISTER)) 1011 return 0; 1012 } 1013 while (--i >= 0); 1014 } 1015 break; 1016 1017 /* We can ignore CLOBBERs. */ 1018 case CLOBBER: 1019 break; 1020 1021 case SET: 1022 /* Ignore SETs whose result isn't used but not those that 1023 have side-effects. */ 1024 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) 1025 && ! side_effects_p (elt)) 1026 break; 1027 1028 /* If we have already found a SET, this is a second one and 1029 so we cannot combine with this insn. */ 1030 if (set) 1031 return 0; 1032 1033 set = elt; 1034 break; 1035 1036 default: 1037 /* Anything else means we can't combine. */ 1038 return 0; 1039 } 1040 } 1041 1042 if (set == 0 1043 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, 1044 so don't do anything with it. */ 1045 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) 1046 return 0; 1047 } 1048 else 1049 return 0; 1050 1051 if (set == 0) 1052 return 0; 1053 1054 set = expand_field_assignment (set); 1055 src = SET_SRC (set), dest = SET_DEST (set); 1056 1057 /* Don't eliminate a store in the stack pointer. */ 1058 if (dest == stack_pointer_rtx 1059 /* If we couldn't eliminate a field assignment, we can't combine. */ 1060 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART 1061 /* Don't combine with an insn that sets a register to itself if it has 1062 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */ 1063 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) 1064 /* Can't merge an ASM_OPERANDS. */ 1065 || GET_CODE (src) == ASM_OPERANDS 1066 /* Can't merge a function call. */ 1067 || GET_CODE (src) == CALL 1068 /* Don't eliminate a function call argument. */ 1069 || (GET_CODE (i3) == CALL_INSN 1070 && (find_reg_fusage (i3, USE, dest) 1071 || (GET_CODE (dest) == REG 1072 && REGNO (dest) < FIRST_PSEUDO_REGISTER 1073 && global_regs[REGNO (dest)]))) 1074 /* Don't substitute into an incremented register. */ 1075 || FIND_REG_INC_NOTE (i3, dest) 1076 || (succ && FIND_REG_INC_NOTE (succ, dest)) 1077#if 0 1078 /* Don't combine the end of a libcall into anything. */ 1079 /* ??? This gives worse code, and appears to be unnecessary, since no 1080 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does 1081 use REG_RETVAL notes for noconflict blocks, but other code here 1082 makes sure that those insns don't disappear. */ 1083 || find_reg_note (insn, REG_RETVAL, NULL_RTX) 1084#endif 1085 /* Make sure that DEST is not used after SUCC but before I3. */ 1086 || (succ && ! all_adjacent 1087 && reg_used_between_p (dest, succ, i3)) 1088 /* Make sure that the value that is to be substituted for the register 1089 does not use any registers whose values alter in between. However, 1090 If the insns are adjacent, a use can't cross a set even though we 1091 think it might (this can happen for a sequence of insns each setting 1092 the same destination; reg_last_set of that register might point to 1093 a NOTE). If INSN has a REG_EQUIV note, the register is always 1094 equivalent to the memory so the substitution is valid even if there 1095 are intervening stores. Also, don't move a volatile asm or 1096 UNSPEC_VOLATILE across any other insns. */ 1097 || (! all_adjacent 1098 && (((GET_CODE (src) != MEM 1099 || ! find_reg_note (insn, REG_EQUIV, src)) 1100 && use_crosses_set_p (src, INSN_CUID (insn))) 1101 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) 1102 || GET_CODE (src) == UNSPEC_VOLATILE)) 1103 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get 1104 better register allocation by not doing the combine. */ 1105 || find_reg_note (i3, REG_NO_CONFLICT, dest) 1106 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest)) 1107 /* Don't combine across a CALL_INSN, because that would possibly 1108 change whether the life span of some REGs crosses calls or not, 1109 and it is a pain to update that information. 1110 Exception: if source is a constant, moving it later can't hurt. 1111 Accept that special case, because it helps -fforce-addr a lot. */ 1112 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src))) 1113 return 0; 1114 1115 /* DEST must either be a REG or CC0. */ 1116 if (GET_CODE (dest) == REG) 1117 { 1118 /* If register alignment is being enforced for multi-word items in all 1119 cases except for parameters, it is possible to have a register copy 1120 insn referencing a hard register that is not allowed to contain the 1121 mode being copied and which would not be valid as an operand of most 1122 insns. Eliminate this problem by not combining with such an insn. 1123 1124 Also, on some machines we don't want to extend the life of a hard 1125 register. */ 1126 1127 if (GET_CODE (src) == REG 1128 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER 1129 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) 1130 /* Don't extend the life of a hard register unless it is 1131 user variable (if we have few registers) or it can't 1132 fit into the desired register (meaning something special 1133 is going on). 1134 Also avoid substituting a return register into I3, because 1135 reload can't handle a conflict with constraints of other 1136 inputs. */ 1137 || (REGNO (src) < FIRST_PSEUDO_REGISTER 1138 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))))) 1139 return 0; 1140 } 1141 else if (GET_CODE (dest) != CC0) 1142 return 0; 1143 1144 /* Don't substitute for a register intended as a clobberable operand. 1145 Similarly, don't substitute an expression containing a register that 1146 will be clobbered in I3. */ 1147 if (GET_CODE (PATTERN (i3)) == PARALLEL) 1148 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) 1149 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER 1150 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), 1151 src) 1152 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest))) 1153 return 0; 1154 1155 /* If INSN contains anything volatile, or is an `asm' (whether volatile 1156 or not), reject, unless nothing volatile comes between it and I3 */ 1157 1158 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) 1159 { 1160 /* Make sure succ doesn't contain a volatile reference. */ 1161 if (succ != 0 && volatile_refs_p (PATTERN (succ))) 1162 return 0; 1163 1164 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 1165 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p))) 1166 return 0; 1167 } 1168 1169 /* If INSN is an asm, and DEST is a hard register, reject, since it has 1170 to be an explicit register variable, and was chosen for a reason. */ 1171 1172 if (GET_CODE (src) == ASM_OPERANDS 1173 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER) 1174 return 0; 1175 1176 /* If there are any volatile insns between INSN and I3, reject, because 1177 they might affect machine state. */ 1178 1179 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 1180 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p))) 1181 return 0; 1182 1183 /* If INSN or I2 contains an autoincrement or autodecrement, 1184 make sure that register is not used between there and I3, 1185 and not already used in I3 either. 1186 Also insist that I3 not be a jump; if it were one 1187 and the incremented register were spilled, we would lose. */ 1188 1189#ifdef AUTO_INC_DEC 1190 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1191 if (REG_NOTE_KIND (link) == REG_INC 1192 && (GET_CODE (i3) == JUMP_INSN 1193 || reg_used_between_p (XEXP (link, 0), insn, i3) 1194 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) 1195 return 0; 1196#endif 1197 1198#ifdef HAVE_cc0 1199 /* Don't combine an insn that follows a CC0-setting insn. 1200 An insn that uses CC0 must not be separated from the one that sets it. 1201 We do, however, allow I2 to follow a CC0-setting insn if that insn 1202 is passed as I1; in that case it will be deleted also. 1203 We also allow combining in this case if all the insns are adjacent 1204 because that would leave the two CC0 insns adjacent as well. 1205 It would be more logical to test whether CC0 occurs inside I1 or I2, 1206 but that would be much slower, and this ought to be equivalent. */ 1207 1208 p = prev_nonnote_insn (insn); 1209 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p)) 1210 && ! all_adjacent) 1211 return 0; 1212#endif 1213 1214 /* If we get here, we have passed all the tests and the combination is 1215 to be allowed. */ 1216 1217 *pdest = dest; 1218 *psrc = src; 1219 1220 return 1; 1221} 1222 1223/* Check if PAT is an insn - or a part of it - used to set up an 1224 argument for a function in a hard register. */ 1225 1226static int 1227sets_function_arg_p (pat) 1228 rtx pat; 1229{ 1230 int i; 1231 rtx inner_dest; 1232 1233 switch (GET_CODE (pat)) 1234 { 1235 case INSN: 1236 return sets_function_arg_p (PATTERN (pat)); 1237 1238 case PARALLEL: 1239 for (i = XVECLEN (pat, 0); --i >= 0;) 1240 if (sets_function_arg_p (XVECEXP (pat, 0, i))) 1241 return 1; 1242 1243 break; 1244 1245 case SET: 1246 inner_dest = SET_DEST (pat); 1247 while (GET_CODE (inner_dest) == STRICT_LOW_PART 1248 || GET_CODE (inner_dest) == SUBREG 1249 || GET_CODE (inner_dest) == ZERO_EXTRACT) 1250 inner_dest = XEXP (inner_dest, 0); 1251 1252 return (GET_CODE (inner_dest) == REG 1253 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 1254 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest))); 1255 1256 default: 1257 break; 1258 } 1259 1260 return 0; 1261} 1262 1263/* LOC is the location within I3 that contains its pattern or the component 1264 of a PARALLEL of the pattern. We validate that it is valid for combining. 1265 1266 One problem is if I3 modifies its output, as opposed to replacing it 1267 entirely, we can't allow the output to contain I2DEST or I1DEST as doing 1268 so would produce an insn that is not equivalent to the original insns. 1269 1270 Consider: 1271 1272 (set (reg:DI 101) (reg:DI 100)) 1273 (set (subreg:SI (reg:DI 101) 0) <foo>) 1274 1275 This is NOT equivalent to: 1276 1277 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) 1278 (set (reg:DI 101) (reg:DI 100))]) 1279 1280 Not only does this modify 100 (in which case it might still be valid 1281 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. 1282 1283 We can also run into a problem if I2 sets a register that I1 1284 uses and I1 gets directly substituted into I3 (not via I2). In that 1285 case, we would be getting the wrong value of I2DEST into I3, so we 1286 must reject the combination. This case occurs when I2 and I1 both 1287 feed into I3, rather than when I1 feeds into I2, which feeds into I3. 1288 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source 1289 of a SET must prevent combination from occurring. 1290 1291 Before doing the above check, we first try to expand a field assignment 1292 into a set of logical operations. 1293 1294 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which 1295 we place a register that is both set and used within I3. If more than one 1296 such register is detected, we fail. 1297 1298 Return 1 if the combination is valid, zero otherwise. */ 1299 1300static int 1301combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed) 1302 rtx i3; 1303 rtx *loc; 1304 rtx i2dest; 1305 rtx i1dest; 1306 int i1_not_in_src; 1307 rtx *pi3dest_killed; 1308{ 1309 rtx x = *loc; 1310 1311 if (GET_CODE (x) == SET) 1312 { 1313 rtx set = expand_field_assignment (x); 1314 rtx dest = SET_DEST (set); 1315 rtx src = SET_SRC (set); 1316 rtx inner_dest = dest; 1317 1318#if 0 1319 rtx inner_src = src; 1320#endif 1321 1322 SUBST (*loc, set); 1323 1324 while (GET_CODE (inner_dest) == STRICT_LOW_PART 1325 || GET_CODE (inner_dest) == SUBREG 1326 || GET_CODE (inner_dest) == ZERO_EXTRACT) 1327 inner_dest = XEXP (inner_dest, 0); 1328 1329 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS 1330 was added. */ 1331#if 0 1332 while (GET_CODE (inner_src) == STRICT_LOW_PART 1333 || GET_CODE (inner_src) == SUBREG 1334 || GET_CODE (inner_src) == ZERO_EXTRACT) 1335 inner_src = XEXP (inner_src, 0); 1336 1337 /* If it is better that two different modes keep two different pseudos, 1338 avoid combining them. This avoids producing the following pattern 1339 on a 386: 1340 (set (subreg:SI (reg/v:QI 21) 0) 1341 (lshiftrt:SI (reg/v:SI 20) 1342 (const_int 24))) 1343 If that were made, reload could not handle the pair of 1344 reg 20/21, since it would try to get any GENERAL_REGS 1345 but some of them don't handle QImode. */ 1346 1347 if (rtx_equal_p (inner_src, i2dest) 1348 && GET_CODE (inner_dest) == REG 1349 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest))) 1350 return 0; 1351#endif 1352 1353 /* Check for the case where I3 modifies its output, as 1354 discussed above. */ 1355 if ((inner_dest != dest 1356 && (reg_overlap_mentioned_p (i2dest, inner_dest) 1357 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) 1358 1359 /* This is the same test done in can_combine_p except we can't test 1360 all_adjacent; we don't have to, since this instruction will stay 1361 in place, thus we are not considering increasing the lifetime of 1362 INNER_DEST. 1363 1364 Also, if this insn sets a function argument, combining it with 1365 something that might need a spill could clobber a previous 1366 function argument; the all_adjacent test in can_combine_p also 1367 checks this; here, we do a more specific test for this case. */ 1368 1369 || (GET_CODE (inner_dest) == REG 1370 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 1371 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), 1372 GET_MODE (inner_dest)))) 1373 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) 1374 return 0; 1375 1376 /* If DEST is used in I3, it is being killed in this insn, 1377 so record that for later. 1378 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the 1379 STACK_POINTER_REGNUM, since these are always considered to be 1380 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ 1381 if (pi3dest_killed && GET_CODE (dest) == REG 1382 && reg_referenced_p (dest, PATTERN (i3)) 1383 && REGNO (dest) != FRAME_POINTER_REGNUM 1384#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 1385 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM 1386#endif 1387#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM 1388 && (REGNO (dest) != ARG_POINTER_REGNUM 1389 || ! fixed_regs [REGNO (dest)]) 1390#endif 1391 && REGNO (dest) != STACK_POINTER_REGNUM) 1392 { 1393 if (*pi3dest_killed) 1394 return 0; 1395 1396 *pi3dest_killed = dest; 1397 } 1398 } 1399 1400 else if (GET_CODE (x) == PARALLEL) 1401 { 1402 int i; 1403 1404 for (i = 0; i < XVECLEN (x, 0); i++) 1405 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, 1406 i1_not_in_src, pi3dest_killed)) 1407 return 0; 1408 } 1409 1410 return 1; 1411} 1412 1413/* Return 1 if X is an arithmetic expression that contains a multiplication 1414 and division. We don't count multiplications by powers of two here. */ 1415 1416static int 1417contains_muldiv (x) 1418 rtx x; 1419{ 1420 switch (GET_CODE (x)) 1421 { 1422 case MOD: case DIV: case UMOD: case UDIV: 1423 return 1; 1424 1425 case MULT: 1426 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT 1427 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0); 1428 default: 1429 switch (GET_RTX_CLASS (GET_CODE (x))) 1430 { 1431 case 'c': case '<': case '2': 1432 return contains_muldiv (XEXP (x, 0)) 1433 || contains_muldiv (XEXP (x, 1)); 1434 1435 case '1': 1436 return contains_muldiv (XEXP (x, 0)); 1437 1438 default: 1439 return 0; 1440 } 1441 } 1442} 1443 1444/* Determine whether INSN can be used in a combination. Return nonzero if 1445 not. This is used in try_combine to detect early some cases where we 1446 can't perform combinations. */ 1447 1448static int 1449cant_combine_insn_p (insn) 1450 rtx insn; 1451{ 1452 rtx set; 1453 rtx src, dest; 1454 1455 /* If this isn't really an insn, we can't do anything. 1456 This can occur when flow deletes an insn that it has merged into an 1457 auto-increment address. */ 1458 if (! INSN_P (insn)) 1459 return 1; 1460 1461 /* Never combine loads and stores involving hard regs. The register 1462 allocator can usually handle such reg-reg moves by tying. If we allow 1463 the combiner to make substitutions of hard regs, we risk aborting in 1464 reload on machines that have SMALL_REGISTER_CLASSES. 1465 As an exception, we allow combinations involving fixed regs; these are 1466 not available to the register allocator so there's no risk involved. */ 1467 1468 set = single_set (insn); 1469 if (! set) 1470 return 0; 1471 src = SET_SRC (set); 1472 dest = SET_DEST (set); 1473 if (GET_CODE (src) == SUBREG) 1474 src = SUBREG_REG (src); 1475 if (GET_CODE (dest) == SUBREG) 1476 dest = SUBREG_REG (dest); 1477 if (REG_P (src) && REG_P (dest) 1478 && ((REGNO (src) < FIRST_PSEUDO_REGISTER 1479 && ! fixed_regs[REGNO (src)]) 1480 || (REGNO (dest) < FIRST_PSEUDO_REGISTER 1481 && ! fixed_regs[REGNO (dest)]))) 1482 return 1; 1483 1484 return 0; 1485} 1486 1487/* Try to combine the insns I1 and I2 into I3. 1488 Here I1 and I2 appear earlier than I3. 1489 I1 can be zero; then we combine just I2 into I3. 1490 1491 If we are combining three insns and the resulting insn is not recognized, 1492 try splitting it into two insns. If that happens, I2 and I3 are retained 1493 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2 1494 are pseudo-deleted. 1495 1496 Return 0 if the combination does not work. Then nothing is changed. 1497 If we did the combination, return the insn at which combine should 1498 resume scanning. 1499 1500 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a 1501 new direct jump instruction. */ 1502 1503static rtx 1504try_combine (i3, i2, i1, new_direct_jump_p) 1505 rtx i3, i2, i1; 1506 int *new_direct_jump_p; 1507{ 1508 /* New patterns for I3 and I2, respectively. */ 1509 rtx newpat, newi2pat = 0; 1510 int substed_i2 = 0, substed_i1 = 0; 1511 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */ 1512 int added_sets_1, added_sets_2; 1513 /* Total number of SETs to put into I3. */ 1514 int total_sets; 1515 /* Nonzero is I2's body now appears in I3. */ 1516 int i2_is_used; 1517 /* INSN_CODEs for new I3, new I2, and user of condition code. */ 1518 int insn_code_number, i2_code_number = 0, other_code_number = 0; 1519 /* Contains I3 if the destination of I3 is used in its source, which means 1520 that the old life of I3 is being killed. If that usage is placed into 1521 I2 and not in I3, a REG_DEAD note must be made. */ 1522 rtx i3dest_killed = 0; 1523 /* SET_DEST and SET_SRC of I2 and I1. */ 1524 rtx i2dest, i2src, i1dest = 0, i1src = 0; 1525 /* PATTERN (I2), or a copy of it in certain cases. */ 1526 rtx i2pat; 1527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ 1528 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; 1529 int i1_feeds_i3 = 0; 1530 /* Notes that must be added to REG_NOTES in I3 and I2. */ 1531 rtx new_i3_notes, new_i2_notes; 1532 /* Notes that we substituted I3 into I2 instead of the normal case. */ 1533 int i3_subst_into_i2 = 0; 1534 /* Notes that I1, I2 or I3 is a MULT operation. */ 1535 int have_mult = 0; 1536 1537 int maxreg; 1538 rtx temp; 1539 rtx link; 1540 int i; 1541 1542 /* Exit early if one of the insns involved can't be used for 1543 combinations. */ 1544 if (cant_combine_insn_p (i3) 1545 || cant_combine_insn_p (i2) 1546 || (i1 && cant_combine_insn_p (i1)) 1547 /* We also can't do anything if I3 has a 1548 REG_LIBCALL note since we don't want to disrupt the contiguity of a 1549 libcall. */ 1550#if 0 1551 /* ??? This gives worse code, and appears to be unnecessary, since no 1552 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */ 1553 || find_reg_note (i3, REG_LIBCALL, NULL_RTX) 1554#endif 1555 ) 1556 return 0; 1557 1558 combine_attempts++; 1559 undobuf.other_insn = 0; 1560 1561 /* Reset the hard register usage information. */ 1562 CLEAR_HARD_REG_SET (newpat_used_regs); 1563 1564 /* If I1 and I2 both feed I3, they can be in any order. To simplify the 1565 code below, set I1 to be the earlier of the two insns. */ 1566 if (i1 && INSN_CUID (i1) > INSN_CUID (i2)) 1567 temp = i1, i1 = i2, i2 = temp; 1568 1569 added_links_insn = 0; 1570 1571 /* First check for one important special-case that the code below will 1572 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL 1573 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, 1574 we may be able to replace that destination with the destination of I3. 1575 This occurs in the common code where we compute both a quotient and 1576 remainder into a structure, in which case we want to do the computation 1577 directly into the structure to avoid register-register copies. 1578 1579 Note that this case handles both multiple sets in I2 and also 1580 cases where I2 has a number of CLOBBER or PARALLELs. 1581 1582 We make very conservative checks below and only try to handle the 1583 most common cases of this. For example, we only handle the case 1584 where I2 and I3 are adjacent to avoid making difficult register 1585 usage tests. */ 1586 1587 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET 1588 && GET_CODE (SET_SRC (PATTERN (i3))) == REG 1589 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER 1590 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) 1591 && GET_CODE (PATTERN (i2)) == PARALLEL 1592 && ! side_effects_p (SET_DEST (PATTERN (i3))) 1593 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code 1594 below would need to check what is inside (and reg_overlap_mentioned_p 1595 doesn't support those codes anyway). Don't allow those destinations; 1596 the resulting insn isn't likely to be recognized anyway. */ 1597 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT 1598 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART 1599 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), 1600 SET_DEST (PATTERN (i3))) 1601 && next_real_insn (i2) == i3) 1602 { 1603 rtx p2 = PATTERN (i2); 1604 1605 /* Make sure that the destination of I3, 1606 which we are going to substitute into one output of I2, 1607 is not used within another output of I2. We must avoid making this: 1608 (parallel [(set (mem (reg 69)) ...) 1609 (set (reg 69) ...)]) 1610 which is not well-defined as to order of actions. 1611 (Besides, reload can't handle output reloads for this.) 1612 1613 The problem can also happen if the dest of I3 is a memory ref, 1614 if another dest in I2 is an indirect memory ref. */ 1615 for (i = 0; i < XVECLEN (p2, 0); i++) 1616 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET 1617 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) 1618 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), 1619 SET_DEST (XVECEXP (p2, 0, i)))) 1620 break; 1621 1622 if (i == XVECLEN (p2, 0)) 1623 for (i = 0; i < XVECLEN (p2, 0); i++) 1624 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET 1625 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) 1626 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) 1627 { 1628 combine_merges++; 1629 1630 subst_insn = i3; 1631 subst_low_cuid = INSN_CUID (i2); 1632 1633 added_sets_2 = added_sets_1 = 0; 1634 i2dest = SET_SRC (PATTERN (i3)); 1635 1636 /* Replace the dest in I2 with our dest and make the resulting 1637 insn the new pattern for I3. Then skip to where we 1638 validate the pattern. Everything was set up above. */ 1639 SUBST (SET_DEST (XVECEXP (p2, 0, i)), 1640 SET_DEST (PATTERN (i3))); 1641 1642 newpat = p2; 1643 i3_subst_into_i2 = 1; 1644 goto validate_replacement; 1645 } 1646 } 1647 1648 /* If I2 is setting a double-word pseudo to a constant and I3 is setting 1649 one of those words to another constant, merge them by making a new 1650 constant. */ 1651 if (i1 == 0 1652 && (temp = single_set (i2)) != 0 1653 && (GET_CODE (SET_SRC (temp)) == CONST_INT 1654 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE) 1655 && GET_CODE (SET_DEST (temp)) == REG 1656 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT 1657 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD 1658 && GET_CODE (PATTERN (i3)) == SET 1659 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG 1660 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp) 1661 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT 1662 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD 1663 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT) 1664 { 1665 HOST_WIDE_INT lo, hi; 1666 1667 if (GET_CODE (SET_SRC (temp)) == CONST_INT) 1668 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0; 1669 else 1670 { 1671 lo = CONST_DOUBLE_LOW (SET_SRC (temp)); 1672 hi = CONST_DOUBLE_HIGH (SET_SRC (temp)); 1673 } 1674 1675 if (subreg_lowpart_p (SET_DEST (PATTERN (i3)))) 1676 { 1677 /* We don't handle the case of the target word being wider 1678 than a host wide int. */ 1679 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD) 1680 abort (); 1681 1682 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1); 1683 lo |= (INTVAL (SET_SRC (PATTERN (i3))) 1684 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1)); 1685 } 1686 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) 1687 hi = INTVAL (SET_SRC (PATTERN (i3))); 1688 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD) 1689 { 1690 int sign = -(int) ((unsigned HOST_WIDE_INT) lo 1691 >> (HOST_BITS_PER_WIDE_INT - 1)); 1692 1693 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD 1694 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1)); 1695 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD 1696 (INTVAL (SET_SRC (PATTERN (i3))))); 1697 if (hi == sign) 1698 hi = lo < 0 ? -1 : 0; 1699 } 1700 else 1701 /* We don't handle the case of the higher word not fitting 1702 entirely in either hi or lo. */ 1703 abort (); 1704 1705 combine_merges++; 1706 subst_insn = i3; 1707 subst_low_cuid = INSN_CUID (i2); 1708 added_sets_2 = added_sets_1 = 0; 1709 i2dest = SET_DEST (temp); 1710 1711 SUBST (SET_SRC (temp), 1712 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp)))); 1713 1714 newpat = PATTERN (i2); 1715 goto validate_replacement; 1716 } 1717 1718#ifndef HAVE_cc0 1719 /* If we have no I1 and I2 looks like: 1720 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) 1721 (set Y OP)]) 1722 make up a dummy I1 that is 1723 (set Y OP) 1724 and change I2 to be 1725 (set (reg:CC X) (compare:CC Y (const_int 0))) 1726 1727 (We can ignore any trailing CLOBBERs.) 1728 1729 This undoes a previous combination and allows us to match a branch-and- 1730 decrement insn. */ 1731 1732 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL 1733 && XVECLEN (PATTERN (i2), 0) >= 2 1734 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET 1735 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) 1736 == MODE_CC) 1737 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE 1738 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx 1739 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET 1740 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG 1741 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), 1742 SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) 1743 { 1744 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) 1745 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) 1746 break; 1747 1748 if (i == 1) 1749 { 1750 /* We make I1 with the same INSN_UID as I2. This gives it 1751 the same INSN_CUID for value tracking. Our fake I1 will 1752 never appear in the insn stream so giving it the same INSN_UID 1753 as I2 will not cause a problem. */ 1754 1755 subst_prev_insn = i1 1756 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2, 1757 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, 1758 NULL_RTX); 1759 1760 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); 1761 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), 1762 SET_DEST (PATTERN (i1))); 1763 } 1764 } 1765#endif 1766 1767 /* Verify that I2 and I1 are valid for combining. */ 1768 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src) 1769 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src))) 1770 { 1771 undo_all (); 1772 return 0; 1773 } 1774 1775 /* Record whether I2DEST is used in I2SRC and similarly for the other 1776 cases. Knowing this will help in register status updating below. */ 1777 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); 1778 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); 1779 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); 1780 1781 /* See if I1 directly feeds into I3. It does if I1DEST is not used 1782 in I2SRC. */ 1783 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); 1784 1785 /* Ensure that I3's pattern can be the destination of combines. */ 1786 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, 1787 i1 && i2dest_in_i1src && i1_feeds_i3, 1788 &i3dest_killed)) 1789 { 1790 undo_all (); 1791 return 0; 1792 } 1793 1794 /* See if any of the insns is a MULT operation. Unless one is, we will 1795 reject a combination that is, since it must be slower. Be conservative 1796 here. */ 1797 if (GET_CODE (i2src) == MULT 1798 || (i1 != 0 && GET_CODE (i1src) == MULT) 1799 || (GET_CODE (PATTERN (i3)) == SET 1800 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) 1801 have_mult = 1; 1802 1803 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. 1804 We used to do this EXCEPT in one case: I3 has a post-inc in an 1805 output operand. However, that exception can give rise to insns like 1806 mov r3,(r3)+ 1807 which is a famous insn on the PDP-11 where the value of r3 used as the 1808 source was model-dependent. Avoid this sort of thing. */ 1809 1810#if 0 1811 if (!(GET_CODE (PATTERN (i3)) == SET 1812 && GET_CODE (SET_SRC (PATTERN (i3))) == REG 1813 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM 1814 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC 1815 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) 1816 /* It's not the exception. */ 1817#endif 1818#ifdef AUTO_INC_DEC 1819 for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) 1820 if (REG_NOTE_KIND (link) == REG_INC 1821 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) 1822 || (i1 != 0 1823 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) 1824 { 1825 undo_all (); 1826 return 0; 1827 } 1828#endif 1829 1830 /* See if the SETs in I1 or I2 need to be kept around in the merged 1831 instruction: whenever the value set there is still needed past I3. 1832 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3. 1833 1834 For the SET in I1, we have two cases: If I1 and I2 independently 1835 feed into I3, the set in I1 needs to be kept around if I1DEST dies 1836 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set 1837 in I1 needs to be kept around unless I1DEST dies or is set in either 1838 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions 1839 I1DEST. If so, we know I1 feeds into I2. */ 1840 1841 added_sets_2 = ! dead_or_set_p (i3, i2dest); 1842 1843 added_sets_1 1844 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) 1845 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); 1846 1847 /* If the set in I2 needs to be kept around, we must make a copy of 1848 PATTERN (I2), so that when we substitute I1SRC for I1DEST in 1849 PATTERN (I2), we are only substituting for the original I1DEST, not into 1850 an already-substituted copy. This also prevents making self-referential 1851 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to 1852 I2DEST. */ 1853 1854 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL 1855 ? gen_rtx_SET (VOIDmode, i2dest, i2src) 1856 : PATTERN (i2)); 1857 1858 if (added_sets_2) 1859 i2pat = copy_rtx (i2pat); 1860 1861 combine_merges++; 1862 1863 /* Substitute in the latest insn for the regs set by the earlier ones. */ 1864 1865 maxreg = max_reg_num (); 1866 1867 subst_insn = i3; 1868 1869 /* It is possible that the source of I2 or I1 may be performing an 1870 unneeded operation, such as a ZERO_EXTEND of something that is known 1871 to have the high part zero. Handle that case by letting subst look at 1872 the innermost one of them. 1873 1874 Another way to do this would be to have a function that tries to 1875 simplify a single insn instead of merging two or more insns. We don't 1876 do this because of the potential of infinite loops and because 1877 of the potential extra memory required. However, doing it the way 1878 we are is a bit of a kludge and doesn't catch all cases. 1879 1880 But only do this if -fexpensive-optimizations since it slows things down 1881 and doesn't usually win. */ 1882 1883 if (flag_expensive_optimizations) 1884 { 1885 /* Pass pc_rtx so no substitutions are done, just simplifications. 1886 The cases that we are interested in here do not involve the few 1887 cases were is_replaced is checked. */ 1888 if (i1) 1889 { 1890 subst_low_cuid = INSN_CUID (i1); 1891 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); 1892 } 1893 else 1894 { 1895 subst_low_cuid = INSN_CUID (i2); 1896 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); 1897 } 1898 } 1899 1900#ifndef HAVE_cc0 1901 /* Many machines that don't use CC0 have insns that can both perform an 1902 arithmetic operation and set the condition code. These operations will 1903 be represented as a PARALLEL with the first element of the vector 1904 being a COMPARE of an arithmetic operation with the constant zero. 1905 The second element of the vector will set some pseudo to the result 1906 of the same arithmetic operation. If we simplify the COMPARE, we won't 1907 match such a pattern and so will generate an extra insn. Here we test 1908 for this case, where both the comparison and the operation result are 1909 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with 1910 I2SRC. Later we will make the PARALLEL that contains I2. */ 1911 1912 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET 1913 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE 1914 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx 1915 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) 1916 { 1917#ifdef EXTRA_CC_MODES 1918 rtx *cc_use; 1919 enum machine_mode compare_mode; 1920#endif 1921 1922 newpat = PATTERN (i3); 1923 SUBST (XEXP (SET_SRC (newpat), 0), i2src); 1924 1925 i2_is_used = 1; 1926 1927#ifdef EXTRA_CC_MODES 1928 /* See if a COMPARE with the operand we substituted in should be done 1929 with the mode that is currently being used. If not, do the same 1930 processing we do in `subst' for a SET; namely, if the destination 1931 is used only once, try to replace it with a register of the proper 1932 mode and also replace the COMPARE. */ 1933 if (undobuf.other_insn == 0 1934 && (cc_use = find_single_use (SET_DEST (newpat), i3, 1935 &undobuf.other_insn)) 1936 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), 1937 i2src, const0_rtx)) 1938 != GET_MODE (SET_DEST (newpat)))) 1939 { 1940 unsigned int regno = REGNO (SET_DEST (newpat)); 1941 rtx new_dest = gen_rtx_REG (compare_mode, regno); 1942 1943 if (regno < FIRST_PSEUDO_REGISTER 1944 || (REG_N_SETS (regno) == 1 && ! added_sets_2 1945 && ! REG_USERVAR_P (SET_DEST (newpat)))) 1946 { 1947 if (regno >= FIRST_PSEUDO_REGISTER) 1948 SUBST (regno_reg_rtx[regno], new_dest); 1949 1950 SUBST (SET_DEST (newpat), new_dest); 1951 SUBST (XEXP (*cc_use, 0), new_dest); 1952 SUBST (SET_SRC (newpat), 1953 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx)); 1954 } 1955 else 1956 undobuf.other_insn = 0; 1957 } 1958#endif 1959 } 1960 else 1961#endif 1962 { 1963 n_occurrences = 0; /* `subst' counts here */ 1964 1965 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we 1966 need to make a unique copy of I2SRC each time we substitute it 1967 to avoid self-referential rtl. */ 1968 1969 subst_low_cuid = INSN_CUID (i2); 1970 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 1971 ! i1_feeds_i3 && i1dest_in_i1src); 1972 substed_i2 = 1; 1973 1974 /* Record whether i2's body now appears within i3's body. */ 1975 i2_is_used = n_occurrences; 1976 } 1977 1978 /* If we already got a failure, don't try to do more. Otherwise, 1979 try to substitute in I1 if we have it. */ 1980 1981 if (i1 && GET_CODE (newpat) != CLOBBER) 1982 { 1983 /* Before we can do this substitution, we must redo the test done 1984 above (see detailed comments there) that ensures that I1DEST 1985 isn't mentioned in any SETs in NEWPAT that are field assignments. */ 1986 1987 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 1988 0, (rtx*) 0)) 1989 { 1990 undo_all (); 1991 return 0; 1992 } 1993 1994 n_occurrences = 0; 1995 subst_low_cuid = INSN_CUID (i1); 1996 newpat = subst (newpat, i1dest, i1src, 0, 0); 1997 substed_i1 = 1; 1998 } 1999 2000 /* Fail if an autoincrement side-effect has been duplicated. Be careful 2001 to count all the ways that I2SRC and I1SRC can be used. */ 2002 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 2003 && i2_is_used + added_sets_2 > 1) 2004 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 2005 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) 2006 > 1)) 2007 /* Fail if we tried to make a new register (we used to abort, but there's 2008 really no reason to). */ 2009 || max_reg_num () != maxreg 2010 /* Fail if we couldn't do something and have a CLOBBER. */ 2011 || GET_CODE (newpat) == CLOBBER 2012 /* Fail if this new pattern is a MULT and we didn't have one before 2013 at the outer level. */ 2014 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT 2015 && ! have_mult)) 2016 { 2017 undo_all (); 2018 return 0; 2019 } 2020 2021 /* If the actions of the earlier insns must be kept 2022 in addition to substituting them into the latest one, 2023 we must make a new PARALLEL for the latest insn 2024 to hold additional the SETs. */ 2025 2026 if (added_sets_1 || added_sets_2) 2027 { 2028 combine_extras++; 2029 2030 if (GET_CODE (newpat) == PARALLEL) 2031 { 2032 rtvec old = XVEC (newpat, 0); 2033 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2; 2034 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 2035 memcpy (XVEC (newpat, 0)->elem, &old->elem[0], 2036 sizeof (old->elem[0]) * old->num_elem); 2037 } 2038 else 2039 { 2040 rtx old = newpat; 2041 total_sets = 1 + added_sets_1 + added_sets_2; 2042 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 2043 XVECEXP (newpat, 0, 0) = old; 2044 } 2045 2046 if (added_sets_1) 2047 XVECEXP (newpat, 0, --total_sets) 2048 = (GET_CODE (PATTERN (i1)) == PARALLEL 2049 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1)); 2050 2051 if (added_sets_2) 2052 { 2053 /* If there is no I1, use I2's body as is. We used to also not do 2054 the subst call below if I2 was substituted into I3, 2055 but that could lose a simplification. */ 2056 if (i1 == 0) 2057 XVECEXP (newpat, 0, --total_sets) = i2pat; 2058 else 2059 /* See comment where i2pat is assigned. */ 2060 XVECEXP (newpat, 0, --total_sets) 2061 = subst (i2pat, i1dest, i1src, 0, 0); 2062 } 2063 } 2064 2065 /* We come here when we are replacing a destination in I2 with the 2066 destination of I3. */ 2067 validate_replacement: 2068 2069 /* Note which hard regs this insn has as inputs. */ 2070 mark_used_regs_combine (newpat); 2071 2072 /* Is the result of combination a valid instruction? */ 2073 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2074 2075 /* If the result isn't valid, see if it is a PARALLEL of two SETs where 2076 the second SET's destination is a register that is unused. In that case, 2077 we just need the first SET. This can occur when simplifying a divmod 2078 insn. We *must* test for this case here because the code below that 2079 splits two independent SETs doesn't handle this case correctly when it 2080 updates the register status. Also check the case where the first 2081 SET's destination is unused. That would not cause incorrect code, but 2082 does cause an unneeded insn to remain. */ 2083 2084 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL 2085 && XVECLEN (newpat, 0) == 2 2086 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2087 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2088 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG 2089 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1))) 2090 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1))) 2091 && asm_noperands (newpat) < 0) 2092 { 2093 newpat = XVECEXP (newpat, 0, 0); 2094 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2095 } 2096 2097 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL 2098 && XVECLEN (newpat, 0) == 2 2099 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2100 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2101 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG 2102 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0))) 2103 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0))) 2104 && asm_noperands (newpat) < 0) 2105 { 2106 newpat = XVECEXP (newpat, 0, 1); 2107 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2108 } 2109 2110 /* If we were combining three insns and the result is a simple SET 2111 with no ASM_OPERANDS that wasn't recognized, try to split it into two 2112 insns. There are two ways to do this. It can be split using a 2113 machine-specific method (like when you have an addition of a large 2114 constant) or by combine in the function find_split_point. */ 2115 2116 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET 2117 && asm_noperands (newpat) < 0) 2118 { 2119 rtx m_split, *split; 2120 rtx ni2dest = i2dest; 2121 2122 /* See if the MD file can split NEWPAT. If it can't, see if letting it 2123 use I2DEST as a scratch register will help. In the latter case, 2124 convert I2DEST to the mode of the source of NEWPAT if we can. */ 2125 2126 m_split = split_insns (newpat, i3); 2127 2128 /* We can only use I2DEST as a scratch reg if it doesn't overlap any 2129 inputs of NEWPAT. */ 2130 2131 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be 2132 possible to try that as a scratch reg. This would require adding 2133 more code to make it work though. */ 2134 2135 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat)) 2136 { 2137 /* If I2DEST is a hard register or the only use of a pseudo, 2138 we can change its mode. */ 2139 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest) 2140 && GET_MODE (SET_DEST (newpat)) != VOIDmode 2141 && GET_CODE (i2dest) == REG 2142 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER 2143 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2 2144 && ! REG_USERVAR_P (i2dest)))) 2145 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)), 2146 REGNO (i2dest)); 2147 2148 m_split = split_insns (gen_rtx_PARALLEL 2149 (VOIDmode, 2150 gen_rtvec (2, newpat, 2151 gen_rtx_CLOBBER (VOIDmode, 2152 ni2dest))), 2153 i3); 2154 /* If the split with the mode-changed register didn't work, try 2155 the original register. */ 2156 if (! m_split && ni2dest != i2dest) 2157 { 2158 ni2dest = i2dest; 2159 m_split = split_insns (gen_rtx_PARALLEL 2160 (VOIDmode, 2161 gen_rtvec (2, newpat, 2162 gen_rtx_CLOBBER (VOIDmode, 2163 i2dest))), 2164 i3); 2165 } 2166 } 2167 2168 /* If we've split a jump pattern, we'll wind up with a sequence even 2169 with one instruction. We can handle that below, so extract it. */ 2170 if (m_split && GET_CODE (m_split) == SEQUENCE 2171 && XVECLEN (m_split, 0) == 1) 2172 m_split = PATTERN (XVECEXP (m_split, 0, 0)); 2173 2174 if (m_split && GET_CODE (m_split) != SEQUENCE) 2175 { 2176 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes); 2177 if (insn_code_number >= 0) 2178 newpat = m_split; 2179 } 2180 else if (m_split && GET_CODE (m_split) == SEQUENCE 2181 && XVECLEN (m_split, 0) == 2 2182 && (next_real_insn (i2) == i3 2183 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)), 2184 INSN_CUID (i2)))) 2185 { 2186 rtx i2set, i3set; 2187 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1)); 2188 newi2pat = PATTERN (XVECEXP (m_split, 0, 0)); 2189 2190 i3set = single_set (XVECEXP (m_split, 0, 1)); 2191 i2set = single_set (XVECEXP (m_split, 0, 0)); 2192 2193 /* In case we changed the mode of I2DEST, replace it in the 2194 pseudo-register table here. We can't do it above in case this 2195 code doesn't get executed and we do a split the other way. */ 2196 2197 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 2198 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest); 2199 2200 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2201 2202 /* If I2 or I3 has multiple SETs, we won't know how to track 2203 register status, so don't use these insns. If I2's destination 2204 is used between I2 and I3, we also can't use these insns. */ 2205 2206 if (i2_code_number >= 0 && i2set && i3set 2207 && (next_real_insn (i2) == i3 2208 || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) 2209 insn_code_number = recog_for_combine (&newi3pat, i3, 2210 &new_i3_notes); 2211 if (insn_code_number >= 0) 2212 newpat = newi3pat; 2213 2214 /* It is possible that both insns now set the destination of I3. 2215 If so, we must show an extra use of it. */ 2216 2217 if (insn_code_number >= 0) 2218 { 2219 rtx new_i3_dest = SET_DEST (i3set); 2220 rtx new_i2_dest = SET_DEST (i2set); 2221 2222 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT 2223 || GET_CODE (new_i3_dest) == STRICT_LOW_PART 2224 || GET_CODE (new_i3_dest) == SUBREG) 2225 new_i3_dest = XEXP (new_i3_dest, 0); 2226 2227 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT 2228 || GET_CODE (new_i2_dest) == STRICT_LOW_PART 2229 || GET_CODE (new_i2_dest) == SUBREG) 2230 new_i2_dest = XEXP (new_i2_dest, 0); 2231 2232 if (GET_CODE (new_i3_dest) == REG 2233 && GET_CODE (new_i2_dest) == REG 2234 && REGNO (new_i3_dest) == REGNO (new_i2_dest)) 2235 REG_N_SETS (REGNO (new_i2_dest))++; 2236 } 2237 } 2238 2239 /* If we can split it and use I2DEST, go ahead and see if that 2240 helps things be recognized. Verify that none of the registers 2241 are set between I2 and I3. */ 2242 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0 2243#ifdef HAVE_cc0 2244 && GET_CODE (i2dest) == REG 2245#endif 2246 /* We need I2DEST in the proper mode. If it is a hard register 2247 or the only use of a pseudo, we can change its mode. */ 2248 && (GET_MODE (*split) == GET_MODE (i2dest) 2249 || GET_MODE (*split) == VOIDmode 2250 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER 2251 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2 2252 && ! REG_USERVAR_P (i2dest))) 2253 && (next_real_insn (i2) == i3 2254 || ! use_crosses_set_p (*split, INSN_CUID (i2))) 2255 /* We can't overwrite I2DEST if its value is still used by 2256 NEWPAT. */ 2257 && ! reg_referenced_p (i2dest, newpat)) 2258 { 2259 rtx newdest = i2dest; 2260 enum rtx_code split_code = GET_CODE (*split); 2261 enum machine_mode split_mode = GET_MODE (*split); 2262 2263 /* Get NEWDEST as a register in the proper mode. We have already 2264 validated that we can do this. */ 2265 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) 2266 { 2267 newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); 2268 2269 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 2270 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest); 2271 } 2272 2273 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to 2274 an ASHIFT. This can occur if it was inside a PLUS and hence 2275 appeared to be a memory address. This is a kludge. */ 2276 if (split_code == MULT 2277 && GET_CODE (XEXP (*split, 1)) == CONST_INT 2278 && INTVAL (XEXP (*split, 1)) > 0 2279 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0) 2280 { 2281 SUBST (*split, gen_rtx_ASHIFT (split_mode, 2282 XEXP (*split, 0), GEN_INT (i))); 2283 /* Update split_code because we may not have a multiply 2284 anymore. */ 2285 split_code = GET_CODE (*split); 2286 } 2287 2288#ifdef INSN_SCHEDULING 2289 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should 2290 be written as a ZERO_EXTEND. */ 2291 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM) 2292 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode, 2293 SUBREG_REG (*split))); 2294#endif 2295 2296 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split); 2297 SUBST (*split, newdest); 2298 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2299 2300 /* If the split point was a MULT and we didn't have one before, 2301 don't use one now. */ 2302 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) 2303 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2304 } 2305 } 2306 2307 /* Check for a case where we loaded from memory in a narrow mode and 2308 then sign extended it, but we need both registers. In that case, 2309 we have a PARALLEL with both loads from the same memory location. 2310 We can split this into a load from memory followed by a register-register 2311 copy. This saves at least one insn, more if register allocation can 2312 eliminate the copy. 2313 2314 We cannot do this if the destination of the second assignment is 2315 a register that we have already assumed is zero-extended. Similarly 2316 for a SUBREG of such a register. */ 2317 2318 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 2319 && GET_CODE (newpat) == PARALLEL 2320 && XVECLEN (newpat, 0) == 2 2321 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2322 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND 2323 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2324 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2325 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) 2326 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2327 INSN_CUID (i2)) 2328 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 2329 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 2330 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)), 2331 (GET_CODE (temp) == REG 2332 && reg_nonzero_bits[REGNO (temp)] != 0 2333 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD 2334 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT 2335 && (reg_nonzero_bits[REGNO (temp)] 2336 != GET_MODE_MASK (word_mode)))) 2337 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG 2338 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), 2339 (GET_CODE (temp) == REG 2340 && reg_nonzero_bits[REGNO (temp)] != 0 2341 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD 2342 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT 2343 && (reg_nonzero_bits[REGNO (temp)] 2344 != GET_MODE_MASK (word_mode))))) 2345 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), 2346 SET_SRC (XVECEXP (newpat, 0, 1))) 2347 && ! find_reg_note (i3, REG_UNUSED, 2348 SET_DEST (XVECEXP (newpat, 0, 0)))) 2349 { 2350 rtx ni2dest; 2351 2352 newi2pat = XVECEXP (newpat, 0, 0); 2353 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); 2354 newpat = XVECEXP (newpat, 0, 1); 2355 SUBST (SET_SRC (newpat), 2356 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest)); 2357 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2358 2359 if (i2_code_number >= 0) 2360 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2361 2362 if (insn_code_number >= 0) 2363 { 2364 rtx insn; 2365 rtx link; 2366 2367 /* If we will be able to accept this, we have made a change to the 2368 destination of I3. This can invalidate a LOG_LINKS pointing 2369 to I3. No other part of combine.c makes such a transformation. 2370 2371 The new I3 will have a destination that was previously the 2372 destination of I1 or I2 and which was used in i2 or I3. Call 2373 distribute_links to make a LOG_LINK from the next use of 2374 that destination. */ 2375 2376 PATTERN (i3) = newpat; 2377 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX)); 2378 2379 /* I3 now uses what used to be its destination and which is 2380 now I2's destination. That means we need a LOG_LINK from 2381 I3 to I2. But we used to have one, so we still will. 2382 2383 However, some later insn might be using I2's dest and have 2384 a LOG_LINK pointing at I3. We must remove this link. 2385 The simplest way to remove the link is to point it at I1, 2386 which we know will be a NOTE. */ 2387 2388 for (insn = NEXT_INSN (i3); 2389 insn && (this_basic_block == n_basic_blocks - 1 2390 || insn != BLOCK_HEAD (this_basic_block + 1)); 2391 insn = NEXT_INSN (insn)) 2392 { 2393 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn))) 2394 { 2395 for (link = LOG_LINKS (insn); link; 2396 link = XEXP (link, 1)) 2397 if (XEXP (link, 0) == i3) 2398 XEXP (link, 0) = i1; 2399 2400 break; 2401 } 2402 } 2403 } 2404 } 2405 2406 /* Similarly, check for a case where we have a PARALLEL of two independent 2407 SETs but we started with three insns. In this case, we can do the sets 2408 as two separate insns. This case occurs when some SET allows two 2409 other insns to combine, but the destination of that SET is still live. */ 2410 2411 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 2412 && GET_CODE (newpat) == PARALLEL 2413 && XVECLEN (newpat, 0) == 2 2414 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2415 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT 2416 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART 2417 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2418 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 2419 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 2420 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2421 INSN_CUID (i2)) 2422 /* Don't pass sets with (USE (MEM ...)) dests to the following. */ 2423 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE 2424 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE 2425 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), 2426 XVECEXP (newpat, 0, 0)) 2427 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), 2428 XVECEXP (newpat, 0, 1)) 2429 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))) 2430 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))) 2431 { 2432 /* Normally, it doesn't matter which of the two is done first, 2433 but it does if one references cc0. In that case, it has to 2434 be first. */ 2435#ifdef HAVE_cc0 2436 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))) 2437 { 2438 newi2pat = XVECEXP (newpat, 0, 0); 2439 newpat = XVECEXP (newpat, 0, 1); 2440 } 2441 else 2442#endif 2443 { 2444 newi2pat = XVECEXP (newpat, 0, 1); 2445 newpat = XVECEXP (newpat, 0, 0); 2446 } 2447 2448 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2449 2450 if (i2_code_number >= 0) 2451 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2452 } 2453 2454 /* If it still isn't recognized, fail and change things back the way they 2455 were. */ 2456 if ((insn_code_number < 0 2457 /* Is the result a reasonable ASM_OPERANDS? */ 2458 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) 2459 { 2460 undo_all (); 2461 return 0; 2462 } 2463 2464 /* If we had to change another insn, make sure it is valid also. */ 2465 if (undobuf.other_insn) 2466 { 2467 rtx other_pat = PATTERN (undobuf.other_insn); 2468 rtx new_other_notes; 2469 rtx note, next; 2470 2471 CLEAR_HARD_REG_SET (newpat_used_regs); 2472 2473 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, 2474 &new_other_notes); 2475 2476 if (other_code_number < 0 && ! check_asm_operands (other_pat)) 2477 { 2478 undo_all (); 2479 return 0; 2480 } 2481 2482 PATTERN (undobuf.other_insn) = other_pat; 2483 2484 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they 2485 are still valid. Then add any non-duplicate notes added by 2486 recog_for_combine. */ 2487 for (note = REG_NOTES (undobuf.other_insn); note; note = next) 2488 { 2489 next = XEXP (note, 1); 2490 2491 if (REG_NOTE_KIND (note) == REG_UNUSED 2492 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) 2493 { 2494 if (GET_CODE (XEXP (note, 0)) == REG) 2495 REG_N_DEATHS (REGNO (XEXP (note, 0)))--; 2496 2497 remove_note (undobuf.other_insn, note); 2498 } 2499 } 2500 2501 for (note = new_other_notes; note; note = XEXP (note, 1)) 2502 if (GET_CODE (XEXP (note, 0)) == REG) 2503 REG_N_DEATHS (REGNO (XEXP (note, 0)))++; 2504 2505 distribute_notes (new_other_notes, undobuf.other_insn, 2506 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX); 2507 } 2508#ifdef HAVE_cc0 2509 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether 2510 they are adjacent to each other or not. */ 2511 { 2512 rtx p = prev_nonnote_insn (i3); 2513 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat 2514 && sets_cc0_p (newi2pat)) 2515 { 2516 undo_all (); 2517 return 0; 2518 } 2519 } 2520#endif 2521 2522 /* We now know that we can do this combination. Merge the insns and 2523 update the status of registers and LOG_LINKS. */ 2524 2525 { 2526 rtx i3notes, i2notes, i1notes = 0; 2527 rtx i3links, i2links, i1links = 0; 2528 rtx midnotes = 0; 2529 unsigned int regno; 2530 /* Compute which registers we expect to eliminate. newi2pat may be setting 2531 either i3dest or i2dest, so we must check it. Also, i1dest may be the 2532 same as i3dest, in which case newi2pat may be setting i1dest. */ 2533 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat)) 2534 || i2dest_in_i2src || i2dest_in_i1src 2535 ? 0 : i2dest); 2536 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src 2537 || (newi2pat && reg_set_p (i1dest, newi2pat)) 2538 ? 0 : i1dest); 2539 2540 /* Get the old REG_NOTES and LOG_LINKS from all our insns and 2541 clear them. */ 2542 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); 2543 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); 2544 if (i1) 2545 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); 2546 2547 /* Ensure that we do not have something that should not be shared but 2548 occurs multiple times in the new insns. Check this by first 2549 resetting all the `used' flags and then copying anything is shared. */ 2550 2551 reset_used_flags (i3notes); 2552 reset_used_flags (i2notes); 2553 reset_used_flags (i1notes); 2554 reset_used_flags (newpat); 2555 reset_used_flags (newi2pat); 2556 if (undobuf.other_insn) 2557 reset_used_flags (PATTERN (undobuf.other_insn)); 2558 2559 i3notes = copy_rtx_if_shared (i3notes); 2560 i2notes = copy_rtx_if_shared (i2notes); 2561 i1notes = copy_rtx_if_shared (i1notes); 2562 newpat = copy_rtx_if_shared (newpat); 2563 newi2pat = copy_rtx_if_shared (newi2pat); 2564 if (undobuf.other_insn) 2565 reset_used_flags (PATTERN (undobuf.other_insn)); 2566 2567 INSN_CODE (i3) = insn_code_number; 2568 PATTERN (i3) = newpat; 2569 2570 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3)) 2571 { 2572 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3); 2573 2574 reset_used_flags (call_usage); 2575 call_usage = copy_rtx (call_usage); 2576 2577 if (substed_i2) 2578 replace_rtx (call_usage, i2dest, i2src); 2579 2580 if (substed_i1) 2581 replace_rtx (call_usage, i1dest, i1src); 2582 2583 CALL_INSN_FUNCTION_USAGE (i3) = call_usage; 2584 } 2585 2586 if (undobuf.other_insn) 2587 INSN_CODE (undobuf.other_insn) = other_code_number; 2588 2589 /* We had one special case above where I2 had more than one set and 2590 we replaced a destination of one of those sets with the destination 2591 of I3. In that case, we have to update LOG_LINKS of insns later 2592 in this basic block. Note that this (expensive) case is rare. 2593 2594 Also, in this case, we must pretend that all REG_NOTEs for I2 2595 actually came from I3, so that REG_UNUSED notes from I2 will be 2596 properly handled. */ 2597 2598 if (i3_subst_into_i2) 2599 { 2600 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) 2601 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE 2602 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG 2603 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest 2604 && ! find_reg_note (i2, REG_UNUSED, 2605 SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) 2606 for (temp = NEXT_INSN (i2); 2607 temp && (this_basic_block == n_basic_blocks - 1 2608 || BLOCK_HEAD (this_basic_block) != temp); 2609 temp = NEXT_INSN (temp)) 2610 if (temp != i3 && INSN_P (temp)) 2611 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1)) 2612 if (XEXP (link, 0) == i2) 2613 XEXP (link, 0) = i3; 2614 2615 if (i3notes) 2616 { 2617 rtx link = i3notes; 2618 while (XEXP (link, 1)) 2619 link = XEXP (link, 1); 2620 XEXP (link, 1) = i2notes; 2621 } 2622 else 2623 i3notes = i2notes; 2624 i2notes = 0; 2625 } 2626 2627 LOG_LINKS (i3) = 0; 2628 REG_NOTES (i3) = 0; 2629 LOG_LINKS (i2) = 0; 2630 REG_NOTES (i2) = 0; 2631 2632 if (newi2pat) 2633 { 2634 INSN_CODE (i2) = i2_code_number; 2635 PATTERN (i2) = newi2pat; 2636 } 2637 else 2638 { 2639 PUT_CODE (i2, NOTE); 2640 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; 2641 NOTE_SOURCE_FILE (i2) = 0; 2642 } 2643 2644 if (i1) 2645 { 2646 LOG_LINKS (i1) = 0; 2647 REG_NOTES (i1) = 0; 2648 PUT_CODE (i1, NOTE); 2649 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED; 2650 NOTE_SOURCE_FILE (i1) = 0; 2651 } 2652 2653 /* Get death notes for everything that is now used in either I3 or 2654 I2 and used to die in a previous insn. If we built two new 2655 patterns, move from I1 to I2 then I2 to I3 so that we get the 2656 proper movement on registers that I2 modifies. */ 2657 2658 if (newi2pat) 2659 { 2660 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes); 2661 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes); 2662 } 2663 else 2664 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2), 2665 i3, &midnotes); 2666 2667 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ 2668 if (i3notes) 2669 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX, 2670 elim_i2, elim_i1); 2671 if (i2notes) 2672 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX, 2673 elim_i2, elim_i1); 2674 if (i1notes) 2675 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX, 2676 elim_i2, elim_i1); 2677 if (midnotes) 2678 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2679 elim_i2, elim_i1); 2680 2681 /* Distribute any notes added to I2 or I3 by recog_for_combine. We 2682 know these are REG_UNUSED and want them to go to the desired insn, 2683 so we always pass it as i3. We have not counted the notes in 2684 reg_n_deaths yet, so we need to do so now. */ 2685 2686 if (newi2pat && new_i2_notes) 2687 { 2688 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1)) 2689 if (GET_CODE (XEXP (temp, 0)) == REG) 2690 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; 2691 2692 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2693 } 2694 2695 if (new_i3_notes) 2696 { 2697 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1)) 2698 if (GET_CODE (XEXP (temp, 0)) == REG) 2699 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; 2700 2701 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX); 2702 } 2703 2704 /* If I3DEST was used in I3SRC, it really died in I3. We may need to 2705 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets 2706 I3DEST, the death must be somewhere before I2, not I3. If we passed I3 2707 in that case, it might delete I2. Similarly for I2 and I1. 2708 Show an additional death due to the REG_DEAD note we make here. If 2709 we discard it in distribute_notes, we will decrement it again. */ 2710 2711 if (i3dest_killed) 2712 { 2713 if (GET_CODE (i3dest_killed) == REG) 2714 REG_N_DEATHS (REGNO (i3dest_killed))++; 2715 2716 if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) 2717 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, 2718 NULL_RTX), 2719 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1); 2720 else 2721 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, 2722 NULL_RTX), 2723 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2724 elim_i2, elim_i1); 2725 } 2726 2727 if (i2dest_in_i2src) 2728 { 2729 if (GET_CODE (i2dest) == REG) 2730 REG_N_DEATHS (REGNO (i2dest))++; 2731 2732 if (newi2pat && reg_set_p (i2dest, newi2pat)) 2733 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), 2734 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2735 else 2736 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), 2737 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2738 NULL_RTX, NULL_RTX); 2739 } 2740 2741 if (i1dest_in_i1src) 2742 { 2743 if (GET_CODE (i1dest) == REG) 2744 REG_N_DEATHS (REGNO (i1dest))++; 2745 2746 if (newi2pat && reg_set_p (i1dest, newi2pat)) 2747 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), 2748 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2749 else 2750 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), 2751 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2752 NULL_RTX, NULL_RTX); 2753 } 2754 2755 distribute_links (i3links); 2756 distribute_links (i2links); 2757 distribute_links (i1links); 2758 2759 if (GET_CODE (i2dest) == REG) 2760 { 2761 rtx link; 2762 rtx i2_insn = 0, i2_val = 0, set; 2763 2764 /* The insn that used to set this register doesn't exist, and 2765 this life of the register may not exist either. See if one of 2766 I3's links points to an insn that sets I2DEST. If it does, 2767 that is now the last known value for I2DEST. If we don't update 2768 this and I2 set the register to a value that depended on its old 2769 contents, we will get confused. If this insn is used, thing 2770 will be set correctly in combine_instructions. */ 2771 2772 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) 2773 if ((set = single_set (XEXP (link, 0))) != 0 2774 && rtx_equal_p (i2dest, SET_DEST (set))) 2775 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set); 2776 2777 record_value_for_reg (i2dest, i2_insn, i2_val); 2778 2779 /* If the reg formerly set in I2 died only once and that was in I3, 2780 zero its use count so it won't make `reload' do any work. */ 2781 if (! added_sets_2 2782 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) 2783 && ! i2dest_in_i2src) 2784 { 2785 regno = REGNO (i2dest); 2786 REG_N_SETS (regno)--; 2787 } 2788 } 2789 2790 if (i1 && GET_CODE (i1dest) == REG) 2791 { 2792 rtx link; 2793 rtx i1_insn = 0, i1_val = 0, set; 2794 2795 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) 2796 if ((set = single_set (XEXP (link, 0))) != 0 2797 && rtx_equal_p (i1dest, SET_DEST (set))) 2798 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set); 2799 2800 record_value_for_reg (i1dest, i1_insn, i1_val); 2801 2802 regno = REGNO (i1dest); 2803 if (! added_sets_1 && ! i1dest_in_i1src) 2804 REG_N_SETS (regno)--; 2805 } 2806 2807 /* Update reg_nonzero_bits et al for any changes that may have been made 2808 to this insn. The order of set_nonzero_bits_and_sign_copies() is 2809 important. Because newi2pat can affect nonzero_bits of newpat */ 2810 if (newi2pat) 2811 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL); 2812 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL); 2813 2814 /* Set new_direct_jump_p if a new return or simple jump instruction 2815 has been created. 2816 2817 If I3 is now an unconditional jump, ensure that it has a 2818 BARRIER following it since it may have initially been a 2819 conditional jump. It may also be the last nonnote insn. */ 2820 2821 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3)) 2822 { 2823 *new_direct_jump_p = 1; 2824 2825 if ((temp = next_nonnote_insn (i3)) == NULL_RTX 2826 || GET_CODE (temp) != BARRIER) 2827 emit_barrier_after (i3); 2828 } 2829 /* An NOOP jump does not need barrier, but it does need cleaning up 2830 of CFG. */ 2831 if (GET_CODE (newpat) == SET 2832 && SET_SRC (newpat) == pc_rtx 2833 && SET_DEST (newpat) == pc_rtx) 2834 *new_direct_jump_p = 1; 2835 } 2836 2837 combine_successes++; 2838 undo_commit (); 2839 2840 /* Clear this here, so that subsequent get_last_value calls are not 2841 affected. */ 2842 subst_prev_insn = NULL_RTX; 2843 2844 if (added_links_insn 2845 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2)) 2846 && INSN_CUID (added_links_insn) < INSN_CUID (i3)) 2847 return added_links_insn; 2848 else 2849 return newi2pat ? i2 : i3; 2850} 2851 2852/* Undo all the modifications recorded in undobuf. */ 2853 2854static void 2855undo_all () 2856{ 2857 struct undo *undo, *next; 2858 2859 for (undo = undobuf.undos; undo; undo = next) 2860 { 2861 next = undo->next; 2862 if (undo->is_int) 2863 *undo->where.i = undo->old_contents.i; 2864 else 2865 *undo->where.r = undo->old_contents.r; 2866 2867 undo->next = undobuf.frees; 2868 undobuf.frees = undo; 2869 } 2870 2871 undobuf.undos = 0; 2872 2873 /* Clear this here, so that subsequent get_last_value calls are not 2874 affected. */ 2875 subst_prev_insn = NULL_RTX; 2876} 2877 2878/* We've committed to accepting the changes we made. Move all 2879 of the undos to the free list. */ 2880 2881static void 2882undo_commit () 2883{ 2884 struct undo *undo, *next; 2885 2886 for (undo = undobuf.undos; undo; undo = next) 2887 { 2888 next = undo->next; 2889 undo->next = undobuf.frees; 2890 undobuf.frees = undo; 2891 } 2892 undobuf.undos = 0; 2893} 2894 2895 2896/* Find the innermost point within the rtx at LOC, possibly LOC itself, 2897 where we have an arithmetic expression and return that point. LOC will 2898 be inside INSN. 2899 2900 try_combine will call this function to see if an insn can be split into 2901 two insns. */ 2902 2903static rtx * 2904find_split_point (loc, insn) 2905 rtx *loc; 2906 rtx insn; 2907{ 2908 rtx x = *loc; 2909 enum rtx_code code = GET_CODE (x); 2910 rtx *split; 2911 unsigned HOST_WIDE_INT len = 0; 2912 HOST_WIDE_INT pos = 0; 2913 int unsignedp = 0; 2914 rtx inner = NULL_RTX; 2915 2916 /* First special-case some codes. */ 2917 switch (code) 2918 { 2919 case SUBREG: 2920#ifdef INSN_SCHEDULING 2921 /* If we are making a paradoxical SUBREG invalid, it becomes a split 2922 point. */ 2923 if (GET_CODE (SUBREG_REG (x)) == MEM) 2924 return loc; 2925#endif 2926 return find_split_point (&SUBREG_REG (x), insn); 2927 2928 case MEM: 2929#ifdef HAVE_lo_sum 2930 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it 2931 using LO_SUM and HIGH. */ 2932 if (GET_CODE (XEXP (x, 0)) == CONST 2933 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) 2934 { 2935 SUBST (XEXP (x, 0), 2936 gen_rtx_LO_SUM (Pmode, 2937 gen_rtx_HIGH (Pmode, XEXP (x, 0)), 2938 XEXP (x, 0))); 2939 return &XEXP (XEXP (x, 0), 0); 2940 } 2941#endif 2942 2943 /* If we have a PLUS whose second operand is a constant and the 2944 address is not valid, perhaps will can split it up using 2945 the machine-specific way to split large constants. We use 2946 the first pseudo-reg (one of the virtual regs) as a placeholder; 2947 it will not remain in the result. */ 2948 if (GET_CODE (XEXP (x, 0)) == PLUS 2949 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 2950 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) 2951 { 2952 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; 2953 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)), 2954 subst_insn); 2955 2956 /* This should have produced two insns, each of which sets our 2957 placeholder. If the source of the second is a valid address, 2958 we can make put both sources together and make a split point 2959 in the middle. */ 2960 2961 if (seq && XVECLEN (seq, 0) == 2 2962 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN 2963 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET 2964 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg 2965 && ! reg_mentioned_p (reg, 2966 SET_SRC (PATTERN (XVECEXP (seq, 0, 0)))) 2967 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN 2968 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET 2969 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg 2970 && memory_address_p (GET_MODE (x), 2971 SET_SRC (PATTERN (XVECEXP (seq, 0, 1))))) 2972 { 2973 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0))); 2974 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1))); 2975 2976 /* Replace the placeholder in SRC2 with SRC1. If we can 2977 find where in SRC2 it was placed, that can become our 2978 split point and we can replace this address with SRC2. 2979 Just try two obvious places. */ 2980 2981 src2 = replace_rtx (src2, reg, src1); 2982 split = 0; 2983 if (XEXP (src2, 0) == src1) 2984 split = &XEXP (src2, 0); 2985 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' 2986 && XEXP (XEXP (src2, 0), 0) == src1) 2987 split = &XEXP (XEXP (src2, 0), 0); 2988 2989 if (split) 2990 { 2991 SUBST (XEXP (x, 0), src2); 2992 return split; 2993 } 2994 } 2995 2996 /* If that didn't work, perhaps the first operand is complex and 2997 needs to be computed separately, so make a split point there. 2998 This will occur on machines that just support REG + CONST 2999 and have a constant moved through some previous computation. */ 3000 3001 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o' 3002 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG 3003 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0)))) 3004 == 'o'))) 3005 return &XEXP (XEXP (x, 0), 0); 3006 } 3007 break; 3008 3009 case SET: 3010#ifdef HAVE_cc0 3011 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a 3012 ZERO_EXTRACT, the most likely reason why this doesn't match is that 3013 we need to put the operand into a register. So split at that 3014 point. */ 3015 3016 if (SET_DEST (x) == cc0_rtx 3017 && GET_CODE (SET_SRC (x)) != COMPARE 3018 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT 3019 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o' 3020 && ! (GET_CODE (SET_SRC (x)) == SUBREG 3021 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o')) 3022 return &SET_SRC (x); 3023#endif 3024 3025 /* See if we can split SET_SRC as it stands. */ 3026 split = find_split_point (&SET_SRC (x), insn); 3027 if (split && split != &SET_SRC (x)) 3028 return split; 3029 3030 /* See if we can split SET_DEST as it stands. */ 3031 split = find_split_point (&SET_DEST (x), insn); 3032 if (split && split != &SET_DEST (x)) 3033 return split; 3034 3035 /* See if this is a bitfield assignment with everything constant. If 3036 so, this is an IOR of an AND, so split it into that. */ 3037 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 3038 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))) 3039 <= HOST_BITS_PER_WIDE_INT) 3040 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT 3041 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT 3042 && GET_CODE (SET_SRC (x)) == CONST_INT 3043 && ((INTVAL (XEXP (SET_DEST (x), 1)) 3044 + INTVAL (XEXP (SET_DEST (x), 2))) 3045 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))) 3046 && ! side_effects_p (XEXP (SET_DEST (x), 0))) 3047 { 3048 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2)); 3049 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1)); 3050 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)); 3051 rtx dest = XEXP (SET_DEST (x), 0); 3052 enum machine_mode mode = GET_MODE (dest); 3053 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1; 3054 3055 if (BITS_BIG_ENDIAN) 3056 pos = GET_MODE_BITSIZE (mode) - len - pos; 3057 3058 if (src == mask) 3059 SUBST (SET_SRC (x), 3060 gen_binary (IOR, mode, dest, GEN_INT (src << pos))); 3061 else 3062 SUBST (SET_SRC (x), 3063 gen_binary (IOR, mode, 3064 gen_binary (AND, mode, dest, 3065 GEN_INT 3066 ( 3067 trunc_int_for_mode 3068 (~(mask << pos) 3069 & GET_MODE_MASK (mode), mode))), 3070 GEN_INT (src << pos))); 3071 3072 SUBST (SET_DEST (x), dest); 3073 3074 split = find_split_point (&SET_SRC (x), insn); 3075 if (split && split != &SET_SRC (x)) 3076 return split; 3077 } 3078 3079 /* Otherwise, see if this is an operation that we can split into two. 3080 If so, try to split that. */ 3081 code = GET_CODE (SET_SRC (x)); 3082 3083 switch (code) 3084 { 3085 case AND: 3086 /* If we are AND'ing with a large constant that is only a single 3087 bit and the result is only being used in a context where we 3088 need to know if it is zero or non-zero, replace it with a bit 3089 extraction. This will avoid the large constant, which might 3090 have taken more than one insn to make. If the constant were 3091 not a valid argument to the AND but took only one insn to make, 3092 this is no worse, but if it took more than one insn, it will 3093 be better. */ 3094 3095 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 3096 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 3097 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7 3098 && GET_CODE (SET_DEST (x)) == REG 3099 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0 3100 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) 3101 && XEXP (*split, 0) == SET_DEST (x) 3102 && XEXP (*split, 1) == const0_rtx) 3103 { 3104 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), 3105 XEXP (SET_SRC (x), 0), 3106 pos, NULL_RTX, 1, 1, 0, 0); 3107 if (extraction != 0) 3108 { 3109 SUBST (SET_SRC (x), extraction); 3110 return find_split_point (loc, insn); 3111 } 3112 } 3113 break; 3114 3115 case NE: 3116 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X 3117 is known to be on, this can be converted into a NEG of a shift. */ 3118 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx 3119 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) 3120 && 1 <= (pos = exact_log2 3121 (nonzero_bits (XEXP (SET_SRC (x), 0), 3122 GET_MODE (XEXP (SET_SRC (x), 0)))))) 3123 { 3124 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); 3125 3126 SUBST (SET_SRC (x), 3127 gen_rtx_NEG (mode, 3128 gen_rtx_LSHIFTRT (mode, 3129 XEXP (SET_SRC (x), 0), 3130 GEN_INT (pos)))); 3131 3132 split = find_split_point (&SET_SRC (x), insn); 3133 if (split && split != &SET_SRC (x)) 3134 return split; 3135 } 3136 break; 3137 3138 case SIGN_EXTEND: 3139 inner = XEXP (SET_SRC (x), 0); 3140 3141 /* We can't optimize if either mode is a partial integer 3142 mode as we don't know how many bits are significant 3143 in those modes. */ 3144 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT 3145 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) 3146 break; 3147 3148 pos = 0; 3149 len = GET_MODE_BITSIZE (GET_MODE (inner)); 3150 unsignedp = 0; 3151 break; 3152 3153 case SIGN_EXTRACT: 3154 case ZERO_EXTRACT: 3155 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 3156 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT) 3157 { 3158 inner = XEXP (SET_SRC (x), 0); 3159 len = INTVAL (XEXP (SET_SRC (x), 1)); 3160 pos = INTVAL (XEXP (SET_SRC (x), 2)); 3161 3162 if (BITS_BIG_ENDIAN) 3163 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos; 3164 unsignedp = (code == ZERO_EXTRACT); 3165 } 3166 break; 3167 3168 default: 3169 break; 3170 } 3171 3172 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner))) 3173 { 3174 enum machine_mode mode = GET_MODE (SET_SRC (x)); 3175 3176 /* For unsigned, we have a choice of a shift followed by an 3177 AND or two shifts. Use two shifts for field sizes where the 3178 constant might be too large. We assume here that we can 3179 always at least get 8-bit constants in an AND insn, which is 3180 true for every current RISC. */ 3181 3182 if (unsignedp && len <= 8) 3183 { 3184 SUBST (SET_SRC (x), 3185 gen_rtx_AND (mode, 3186 gen_rtx_LSHIFTRT 3187 (mode, gen_lowpart_for_combine (mode, inner), 3188 GEN_INT (pos)), 3189 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1))); 3190 3191 split = find_split_point (&SET_SRC (x), insn); 3192 if (split && split != &SET_SRC (x)) 3193 return split; 3194 } 3195 else 3196 { 3197 SUBST (SET_SRC (x), 3198 gen_rtx_fmt_ee 3199 (unsignedp ? LSHIFTRT : ASHIFTRT, mode, 3200 gen_rtx_ASHIFT (mode, 3201 gen_lowpart_for_combine (mode, inner), 3202 GEN_INT (GET_MODE_BITSIZE (mode) 3203 - len - pos)), 3204 GEN_INT (GET_MODE_BITSIZE (mode) - len))); 3205 3206 split = find_split_point (&SET_SRC (x), insn); 3207 if (split && split != &SET_SRC (x)) 3208 return split; 3209 } 3210 } 3211 3212 /* See if this is a simple operation with a constant as the second 3213 operand. It might be that this constant is out of range and hence 3214 could be used as a split point. */ 3215 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' 3216 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' 3217 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<') 3218 && CONSTANT_P (XEXP (SET_SRC (x), 1)) 3219 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o' 3220 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG 3221 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0)))) 3222 == 'o')))) 3223 return &XEXP (SET_SRC (x), 1); 3224 3225 /* Finally, see if this is a simple operation with its first operand 3226 not in a register. The operation might require this operand in a 3227 register, so return it as a split point. We can always do this 3228 because if the first operand were another operation, we would have 3229 already found it as a split point. */ 3230 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' 3231 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' 3232 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<' 3233 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1') 3234 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) 3235 return &XEXP (SET_SRC (x), 0); 3236 3237 return 0; 3238 3239 case AND: 3240 case IOR: 3241 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, 3242 it is better to write this as (not (ior A B)) so we can split it. 3243 Similarly for IOR. */ 3244 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) 3245 { 3246 SUBST (*loc, 3247 gen_rtx_NOT (GET_MODE (x), 3248 gen_rtx_fmt_ee (code == IOR ? AND : IOR, 3249 GET_MODE (x), 3250 XEXP (XEXP (x, 0), 0), 3251 XEXP (XEXP (x, 1), 0)))); 3252 return find_split_point (loc, insn); 3253 } 3254 3255 /* Many RISC machines have a large set of logical insns. If the 3256 second operand is a NOT, put it first so we will try to split the 3257 other operand first. */ 3258 if (GET_CODE (XEXP (x, 1)) == NOT) 3259 { 3260 rtx tem = XEXP (x, 0); 3261 SUBST (XEXP (x, 0), XEXP (x, 1)); 3262 SUBST (XEXP (x, 1), tem); 3263 } 3264 break; 3265 3266 default: 3267 break; 3268 } 3269 3270 /* Otherwise, select our actions depending on our rtx class. */ 3271 switch (GET_RTX_CLASS (code)) 3272 { 3273 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ 3274 case '3': 3275 split = find_split_point (&XEXP (x, 2), insn); 3276 if (split) 3277 return split; 3278 /* ... fall through ... */ 3279 case '2': 3280 case 'c': 3281 case '<': 3282 split = find_split_point (&XEXP (x, 1), insn); 3283 if (split) 3284 return split; 3285 /* ... fall through ... */ 3286 case '1': 3287 /* Some machines have (and (shift ...) ...) insns. If X is not 3288 an AND, but XEXP (X, 0) is, use it as our split point. */ 3289 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) 3290 return &XEXP (x, 0); 3291 3292 split = find_split_point (&XEXP (x, 0), insn); 3293 if (split) 3294 return split; 3295 return loc; 3296 } 3297 3298 /* Otherwise, we don't have a split point. */ 3299 return 0; 3300} 3301 3302/* Throughout X, replace FROM with TO, and return the result. 3303 The result is TO if X is FROM; 3304 otherwise the result is X, but its contents may have been modified. 3305 If they were modified, a record was made in undobuf so that 3306 undo_all will (among other things) return X to its original state. 3307 3308 If the number of changes necessary is too much to record to undo, 3309 the excess changes are not made, so the result is invalid. 3310 The changes already made can still be undone. 3311 undobuf.num_undo is incremented for such changes, so by testing that 3312 the caller can tell whether the result is valid. 3313 3314 `n_occurrences' is incremented each time FROM is replaced. 3315 3316 IN_DEST is non-zero if we are processing the SET_DEST of a SET. 3317 3318 UNIQUE_COPY is non-zero if each substitution must be unique. We do this 3319 by copying if `n_occurrences' is non-zero. */ 3320 3321static rtx 3322subst (x, from, to, in_dest, unique_copy) 3323 rtx x, from, to; 3324 int in_dest; 3325 int unique_copy; 3326{ 3327 enum rtx_code code = GET_CODE (x); 3328 enum machine_mode op0_mode = VOIDmode; 3329 const char *fmt; 3330 int len, i; 3331 rtx new; 3332 3333/* Two expressions are equal if they are identical copies of a shared 3334 RTX or if they are both registers with the same register number 3335 and mode. */ 3336 3337#define COMBINE_RTX_EQUAL_P(X,Y) \ 3338 ((X) == (Y) \ 3339 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \ 3340 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) 3341 3342 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) 3343 { 3344 n_occurrences++; 3345 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); 3346 } 3347 3348 /* If X and FROM are the same register but different modes, they will 3349 not have been seen as equal above. However, flow.c will make a 3350 LOG_LINKS entry for that case. If we do nothing, we will try to 3351 rerecognize our original insn and, when it succeeds, we will 3352 delete the feeding insn, which is incorrect. 3353 3354 So force this insn not to match in this (rare) case. */ 3355 if (! in_dest && code == REG && GET_CODE (from) == REG 3356 && REGNO (x) == REGNO (from)) 3357 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 3358 3359 /* If this is an object, we are done unless it is a MEM or LO_SUM, both 3360 of which may contain things that can be combined. */ 3361 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o') 3362 return x; 3363 3364 /* It is possible to have a subexpression appear twice in the insn. 3365 Suppose that FROM is a register that appears within TO. 3366 Then, after that subexpression has been scanned once by `subst', 3367 the second time it is scanned, TO may be found. If we were 3368 to scan TO here, we would find FROM within it and create a 3369 self-referent rtl structure which is completely wrong. */ 3370 if (COMBINE_RTX_EQUAL_P (x, to)) 3371 return to; 3372 3373 /* Parallel asm_operands need special attention because all of the 3374 inputs are shared across the arms. Furthermore, unsharing the 3375 rtl results in recognition failures. Failure to handle this case 3376 specially can result in circular rtl. 3377 3378 Solve this by doing a normal pass across the first entry of the 3379 parallel, and only processing the SET_DESTs of the subsequent 3380 entries. Ug. */ 3381 3382 if (code == PARALLEL 3383 && GET_CODE (XVECEXP (x, 0, 0)) == SET 3384 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) 3385 { 3386 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy); 3387 3388 /* If this substitution failed, this whole thing fails. */ 3389 if (GET_CODE (new) == CLOBBER 3390 && XEXP (new, 0) == const0_rtx) 3391 return new; 3392 3393 SUBST (XVECEXP (x, 0, 0), new); 3394 3395 for (i = XVECLEN (x, 0) - 1; i >= 1; i--) 3396 { 3397 rtx dest = SET_DEST (XVECEXP (x, 0, i)); 3398 3399 if (GET_CODE (dest) != REG 3400 && GET_CODE (dest) != CC0 3401 && GET_CODE (dest) != PC) 3402 { 3403 new = subst (dest, from, to, 0, unique_copy); 3404 3405 /* If this substitution failed, this whole thing fails. */ 3406 if (GET_CODE (new) == CLOBBER 3407 && XEXP (new, 0) == const0_rtx) 3408 return new; 3409 3410 SUBST (SET_DEST (XVECEXP (x, 0, i)), new); 3411 } 3412 } 3413 } 3414 else 3415 { 3416 len = GET_RTX_LENGTH (code); 3417 fmt = GET_RTX_FORMAT (code); 3418 3419 /* We don't need to process a SET_DEST that is a register, CC0, 3420 or PC, so set up to skip this common case. All other cases 3421 where we want to suppress replacing something inside a 3422 SET_SRC are handled via the IN_DEST operand. */ 3423 if (code == SET 3424 && (GET_CODE (SET_DEST (x)) == REG 3425 || GET_CODE (SET_DEST (x)) == CC0 3426 || GET_CODE (SET_DEST (x)) == PC)) 3427 fmt = "ie"; 3428 3429 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a 3430 constant. */ 3431 if (fmt[0] == 'e') 3432 op0_mode = GET_MODE (XEXP (x, 0)); 3433 3434 for (i = 0; i < len; i++) 3435 { 3436 if (fmt[i] == 'E') 3437 { 3438 int j; 3439 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3440 { 3441 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) 3442 { 3443 new = (unique_copy && n_occurrences 3444 ? copy_rtx (to) : to); 3445 n_occurrences++; 3446 } 3447 else 3448 { 3449 new = subst (XVECEXP (x, i, j), from, to, 0, 3450 unique_copy); 3451 3452 /* If this substitution failed, this whole thing 3453 fails. */ 3454 if (GET_CODE (new) == CLOBBER 3455 && XEXP (new, 0) == const0_rtx) 3456 return new; 3457 } 3458 3459 SUBST (XVECEXP (x, i, j), new); 3460 } 3461 } 3462 else if (fmt[i] == 'e') 3463 { 3464 /* If this is a register being set, ignore it. */ 3465 new = XEXP (x, i); 3466 if (in_dest 3467 && (code == SUBREG || code == STRICT_LOW_PART 3468 || code == ZERO_EXTRACT) 3469 && i == 0 3470 && GET_CODE (new) == REG) 3471 ; 3472 3473 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) 3474 { 3475 /* In general, don't install a subreg involving two 3476 modes not tieable. It can worsen register 3477 allocation, and can even make invalid reload 3478 insns, since the reg inside may need to be copied 3479 from in the outside mode, and that may be invalid 3480 if it is an fp reg copied in integer mode. 3481 3482 We allow two exceptions to this: It is valid if 3483 it is inside another SUBREG and the mode of that 3484 SUBREG and the mode of the inside of TO is 3485 tieable and it is valid if X is a SET that copies 3486 FROM to CC0. */ 3487 3488 if (GET_CODE (to) == SUBREG 3489 && ! MODES_TIEABLE_P (GET_MODE (to), 3490 GET_MODE (SUBREG_REG (to))) 3491 && ! (code == SUBREG 3492 && MODES_TIEABLE_P (GET_MODE (x), 3493 GET_MODE (SUBREG_REG (to)))) 3494#ifdef HAVE_cc0 3495 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx) 3496#endif 3497 ) 3498 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 3499 3500#ifdef CLASS_CANNOT_CHANGE_MODE 3501 if (code == SUBREG 3502 && GET_CODE (to) == REG 3503 && REGNO (to) < FIRST_PSEUDO_REGISTER 3504 && (TEST_HARD_REG_BIT 3505 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], 3506 REGNO (to))) 3507 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to), 3508 GET_MODE (x))) 3509 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 3510#endif 3511 3512 new = (unique_copy && n_occurrences ? copy_rtx (to) : to); 3513 n_occurrences++; 3514 } 3515 else 3516 /* If we are in a SET_DEST, suppress most cases unless we 3517 have gone inside a MEM, in which case we want to 3518 simplify the address. We assume here that things that 3519 are actually part of the destination have their inner 3520 parts in the first expression. This is true for SUBREG, 3521 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only 3522 things aside from REG and MEM that should appear in a 3523 SET_DEST. */ 3524 new = subst (XEXP (x, i), from, to, 3525 (((in_dest 3526 && (code == SUBREG || code == STRICT_LOW_PART 3527 || code == ZERO_EXTRACT)) 3528 || code == SET) 3529 && i == 0), unique_copy); 3530 3531 /* If we found that we will have to reject this combination, 3532 indicate that by returning the CLOBBER ourselves, rather than 3533 an expression containing it. This will speed things up as 3534 well as prevent accidents where two CLOBBERs are considered 3535 to be equal, thus producing an incorrect simplification. */ 3536 3537 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) 3538 return new; 3539 3540 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG) 3541 { 3542 x = simplify_subreg (GET_MODE (x), new, 3543 GET_MODE (SUBREG_REG (x)), 3544 SUBREG_BYTE (x)); 3545 if (! x) 3546 abort (); 3547 } 3548 else if (GET_CODE (new) == CONST_INT 3549 && GET_CODE (x) == ZERO_EXTEND) 3550 { 3551 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), 3552 new, GET_MODE (XEXP (x, 0))); 3553 if (! x) 3554 abort (); 3555 } 3556 else 3557 SUBST (XEXP (x, i), new); 3558 } 3559 } 3560 } 3561 3562 /* Try to simplify X. If the simplification changed the code, it is likely 3563 that further simplification will help, so loop, but limit the number 3564 of repetitions that will be performed. */ 3565 3566 for (i = 0; i < 4; i++) 3567 { 3568 /* If X is sufficiently simple, don't bother trying to do anything 3569 with it. */ 3570 if (code != CONST_INT && code != REG && code != CLOBBER) 3571 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest); 3572 3573 if (GET_CODE (x) == code) 3574 break; 3575 3576 code = GET_CODE (x); 3577 3578 /* We no longer know the original mode of operand 0 since we 3579 have changed the form of X) */ 3580 op0_mode = VOIDmode; 3581 } 3582 3583 return x; 3584} 3585 3586/* Simplify X, a piece of RTL. We just operate on the expression at the 3587 outer level; call `subst' to simplify recursively. Return the new 3588 expression. 3589 3590 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this 3591 will be the iteration even if an expression with a code different from 3592 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */ 3593 3594static rtx 3595combine_simplify_rtx (x, op0_mode, last, in_dest) 3596 rtx x; 3597 enum machine_mode op0_mode; 3598 int last; 3599 int in_dest; 3600{ 3601 enum rtx_code code = GET_CODE (x); 3602 enum machine_mode mode = GET_MODE (x); 3603 rtx temp; 3604 rtx reversed; 3605 int i; 3606 3607 /* If this is a commutative operation, put a constant last and a complex 3608 expression first. We don't need to do this for comparisons here. */ 3609 if (GET_RTX_CLASS (code) == 'c' 3610 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 3611 { 3612 temp = XEXP (x, 0); 3613 SUBST (XEXP (x, 0), XEXP (x, 1)); 3614 SUBST (XEXP (x, 1), temp); 3615 } 3616 3617 /* If this is a PLUS, MINUS, or MULT, and the first operand is the 3618 sign extension of a PLUS with a constant, reverse the order of the sign 3619 extension and the addition. Note that this not the same as the original 3620 code, but overflow is undefined for signed values. Also note that the 3621 PLUS will have been partially moved "inside" the sign-extension, so that 3622 the first operand of X will really look like: 3623 (ashiftrt (plus (ashift A C4) C5) C4). 3624 We convert this to 3625 (plus (ashiftrt (ashift A C4) C2) C4) 3626 and replace the first operand of X with that expression. Later parts 3627 of this function may simplify the expression further. 3628 3629 For example, if we start with (mult (sign_extend (plus A C1)) C2), 3630 we swap the SIGN_EXTEND and PLUS. Later code will apply the 3631 distributive law to produce (plus (mult (sign_extend X) C1) C3). 3632 3633 We do this to simplify address expressions. */ 3634 3635 if ((code == PLUS || code == MINUS || code == MULT) 3636 && GET_CODE (XEXP (x, 0)) == ASHIFTRT 3637 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS 3638 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT 3639 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT 3640 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3641 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1) 3642 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT 3643 && (temp = simplify_binary_operation (ASHIFTRT, mode, 3644 XEXP (XEXP (XEXP (x, 0), 0), 1), 3645 XEXP (XEXP (x, 0), 1))) != 0) 3646 { 3647 rtx new 3648 = simplify_shift_const (NULL_RTX, ASHIFT, mode, 3649 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0), 3650 INTVAL (XEXP (XEXP (x, 0), 1))); 3651 3652 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new, 3653 INTVAL (XEXP (XEXP (x, 0), 1))); 3654 3655 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp)); 3656 } 3657 3658 /* If this is a simple operation applied to an IF_THEN_ELSE, try 3659 applying it to the arms of the IF_THEN_ELSE. This often simplifies 3660 things. Check for cases where both arms are testing the same 3661 condition. 3662 3663 Don't do anything if all operands are very simple. */ 3664 3665 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c' 3666 || GET_RTX_CLASS (code) == '<') 3667 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' 3668 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 3669 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) 3670 == 'o'))) 3671 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o' 3672 && ! (GET_CODE (XEXP (x, 1)) == SUBREG 3673 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1)))) 3674 == 'o'))))) 3675 || (GET_RTX_CLASS (code) == '1' 3676 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' 3677 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 3678 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) 3679 == 'o')))))) 3680 { 3681 rtx cond, true_rtx, false_rtx; 3682 3683 cond = if_then_else_cond (x, &true_rtx, &false_rtx); 3684 if (cond != 0 3685 /* If everything is a comparison, what we have is highly unlikely 3686 to be simpler, so don't use it. */ 3687 && ! (GET_RTX_CLASS (code) == '<' 3688 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<' 3689 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<'))) 3690 { 3691 rtx cop1 = const0_rtx; 3692 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); 3693 3694 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<') 3695 return x; 3696 3697 /* Simplify the alternative arms; this may collapse the true and 3698 false arms to store-flag values. */ 3699 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0); 3700 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0); 3701 3702 /* If true_rtx and false_rtx are not general_operands, an if_then_else 3703 is unlikely to be simpler. */ 3704 if (general_operand (true_rtx, VOIDmode) 3705 && general_operand (false_rtx, VOIDmode)) 3706 { 3707 /* Restarting if we generate a store-flag expression will cause 3708 us to loop. Just drop through in this case. */ 3709 3710 /* If the result values are STORE_FLAG_VALUE and zero, we can 3711 just make the comparison operation. */ 3712 if (true_rtx == const_true_rtx && false_rtx == const0_rtx) 3713 x = gen_binary (cond_code, mode, cond, cop1); 3714 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx 3715 && reverse_condition (cond_code) != UNKNOWN) 3716 x = gen_binary (reverse_condition (cond_code), 3717 mode, cond, cop1); 3718 3719 /* Likewise, we can make the negate of a comparison operation 3720 if the result values are - STORE_FLAG_VALUE and zero. */ 3721 else if (GET_CODE (true_rtx) == CONST_INT 3722 && INTVAL (true_rtx) == - STORE_FLAG_VALUE 3723 && false_rtx == const0_rtx) 3724 x = simplify_gen_unary (NEG, mode, 3725 gen_binary (cond_code, mode, cond, 3726 cop1), 3727 mode); 3728 else if (GET_CODE (false_rtx) == CONST_INT 3729 && INTVAL (false_rtx) == - STORE_FLAG_VALUE 3730 && true_rtx == const0_rtx) 3731 x = simplify_gen_unary (NEG, mode, 3732 gen_binary (reverse_condition 3733 (cond_code), 3734 mode, cond, cop1), 3735 mode); 3736 else 3737 return gen_rtx_IF_THEN_ELSE (mode, 3738 gen_binary (cond_code, VOIDmode, 3739 cond, cop1), 3740 true_rtx, false_rtx); 3741 3742 code = GET_CODE (x); 3743 op0_mode = VOIDmode; 3744 } 3745 } 3746 } 3747 3748 /* Try to fold this expression in case we have constants that weren't 3749 present before. */ 3750 temp = 0; 3751 switch (GET_RTX_CLASS (code)) 3752 { 3753 case '1': 3754 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); 3755 break; 3756 case '<': 3757 { 3758 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0)); 3759 if (cmp_mode == VOIDmode) 3760 { 3761 cmp_mode = GET_MODE (XEXP (x, 1)); 3762 if (cmp_mode == VOIDmode) 3763 cmp_mode = op0_mode; 3764 } 3765 temp = simplify_relational_operation (code, cmp_mode, 3766 XEXP (x, 0), XEXP (x, 1)); 3767 } 3768#ifdef FLOAT_STORE_FLAG_VALUE 3769 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT) 3770 { 3771 if (temp == const0_rtx) 3772 temp = CONST0_RTX (mode); 3773 else 3774 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode); 3775 } 3776#endif 3777 break; 3778 case 'c': 3779 case '2': 3780 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); 3781 break; 3782 case 'b': 3783 case '3': 3784 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), 3785 XEXP (x, 1), XEXP (x, 2)); 3786 break; 3787 } 3788 3789 if (temp) 3790 { 3791 x = temp; 3792 code = GET_CODE (temp); 3793 op0_mode = VOIDmode; 3794 mode = GET_MODE (temp); 3795 } 3796 3797 /* First see if we can apply the inverse distributive law. */ 3798 if (code == PLUS || code == MINUS 3799 || code == AND || code == IOR || code == XOR) 3800 { 3801 x = apply_distributive_law (x); 3802 code = GET_CODE (x); 3803 op0_mode = VOIDmode; 3804 } 3805 3806 /* If CODE is an associative operation not otherwise handled, see if we 3807 can associate some operands. This can win if they are constants or 3808 if they are logically related (i.e. (a & b) & a). */ 3809 if ((code == PLUS || code == MINUS || code == MULT || code == DIV 3810 || code == AND || code == IOR || code == XOR 3811 || code == SMAX || code == SMIN || code == UMAX || code == UMIN) 3812 && ((INTEGRAL_MODE_P (mode) && code != DIV) 3813 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode)))) 3814 { 3815 if (GET_CODE (XEXP (x, 0)) == code) 3816 { 3817 rtx other = XEXP (XEXP (x, 0), 0); 3818 rtx inner_op0 = XEXP (XEXP (x, 0), 1); 3819 rtx inner_op1 = XEXP (x, 1); 3820 rtx inner; 3821 3822 /* Make sure we pass the constant operand if any as the second 3823 one if this is a commutative operation. */ 3824 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c') 3825 { 3826 rtx tem = inner_op0; 3827 inner_op0 = inner_op1; 3828 inner_op1 = tem; 3829 } 3830 inner = simplify_binary_operation (code == MINUS ? PLUS 3831 : code == DIV ? MULT 3832 : code, 3833 mode, inner_op0, inner_op1); 3834 3835 /* For commutative operations, try the other pair if that one 3836 didn't simplify. */ 3837 if (inner == 0 && GET_RTX_CLASS (code) == 'c') 3838 { 3839 other = XEXP (XEXP (x, 0), 1); 3840 inner = simplify_binary_operation (code, mode, 3841 XEXP (XEXP (x, 0), 0), 3842 XEXP (x, 1)); 3843 } 3844 3845 if (inner) 3846 return gen_binary (code, mode, other, inner); 3847 } 3848 } 3849 3850 /* A little bit of algebraic simplification here. */ 3851 switch (code) 3852 { 3853 case MEM: 3854 /* Ensure that our address has any ASHIFTs converted to MULT in case 3855 address-recognizing predicates are called later. */ 3856 temp = make_compound_operation (XEXP (x, 0), MEM); 3857 SUBST (XEXP (x, 0), temp); 3858 break; 3859 3860 case SUBREG: 3861 if (op0_mode == VOIDmode) 3862 op0_mode = GET_MODE (SUBREG_REG (x)); 3863 3864 /* simplify_subreg can't use gen_lowpart_for_combine. */ 3865 if (CONSTANT_P (SUBREG_REG (x)) 3866 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)) 3867 return gen_lowpart_for_combine (mode, SUBREG_REG (x)); 3868 3869 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC) 3870 break; 3871 { 3872 rtx temp; 3873 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode, 3874 SUBREG_BYTE (x)); 3875 if (temp) 3876 return temp; 3877 } 3878 3879 /* Don't change the mode of the MEM if that would change the meaning 3880 of the address. */ 3881 if (GET_CODE (SUBREG_REG (x)) == MEM 3882 && (MEM_VOLATILE_P (SUBREG_REG (x)) 3883 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0)))) 3884 return gen_rtx_CLOBBER (mode, const0_rtx); 3885 3886 /* Note that we cannot do any narrowing for non-constants since 3887 we might have been counting on using the fact that some bits were 3888 zero. We now do this in the SET. */ 3889 3890 break; 3891 3892 case NOT: 3893 /* (not (plus X -1)) can become (neg X). */ 3894 if (GET_CODE (XEXP (x, 0)) == PLUS 3895 && XEXP (XEXP (x, 0), 1) == constm1_rtx) 3896 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0)); 3897 3898 /* Similarly, (not (neg X)) is (plus X -1). */ 3899 if (GET_CODE (XEXP (x, 0)) == NEG) 3900 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx); 3901 3902 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */ 3903 if (GET_CODE (XEXP (x, 0)) == XOR 3904 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3905 && (temp = simplify_unary_operation (NOT, mode, 3906 XEXP (XEXP (x, 0), 1), 3907 mode)) != 0) 3908 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp); 3909 3910 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands 3911 other than 1, but that is not valid. We could do a similar 3912 simplification for (not (lshiftrt C X)) where C is just the sign bit, 3913 but this doesn't seem common enough to bother with. */ 3914 if (GET_CODE (XEXP (x, 0)) == ASHIFT 3915 && XEXP (XEXP (x, 0), 0) == const1_rtx) 3916 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode, 3917 const1_rtx, mode), 3918 XEXP (XEXP (x, 0), 1)); 3919 3920 if (GET_CODE (XEXP (x, 0)) == SUBREG 3921 && subreg_lowpart_p (XEXP (x, 0)) 3922 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) 3923 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0))))) 3924 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT 3925 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx) 3926 { 3927 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0))); 3928 3929 x = gen_rtx_ROTATE (inner_mode, 3930 simplify_gen_unary (NOT, inner_mode, const1_rtx, 3931 inner_mode), 3932 XEXP (SUBREG_REG (XEXP (x, 0)), 1)); 3933 return gen_lowpart_for_combine (mode, x); 3934 } 3935 3936 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by 3937 reversing the comparison code if valid. */ 3938 if (STORE_FLAG_VALUE == -1 3939 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 3940 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0), 3941 XEXP (XEXP (x, 0), 1)))) 3942 return reversed; 3943 3944 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1 3945 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can 3946 perform the above simplification. */ 3947 3948 if (STORE_FLAG_VALUE == -1 3949 && GET_CODE (XEXP (x, 0)) == ASHIFTRT 3950 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3951 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1) 3952 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx); 3953 3954 /* Apply De Morgan's laws to reduce number of patterns for machines 3955 with negating logical insns (and-not, nand, etc.). If result has 3956 only one NOT, put it first, since that is how the patterns are 3957 coded. */ 3958 3959 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND) 3960 { 3961 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1); 3962 enum machine_mode op_mode; 3963 3964 op_mode = GET_MODE (in1); 3965 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode); 3966 3967 op_mode = GET_MODE (in2); 3968 if (op_mode == VOIDmode) 3969 op_mode = mode; 3970 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode); 3971 3972 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT) 3973 { 3974 rtx tem = in2; 3975 in2 = in1; in1 = tem; 3976 } 3977 3978 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR, 3979 mode, in1, in2); 3980 } 3981 break; 3982 3983 case NEG: 3984 /* (neg (plus X 1)) can become (not X). */ 3985 if (GET_CODE (XEXP (x, 0)) == PLUS 3986 && XEXP (XEXP (x, 0), 1) == const1_rtx) 3987 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0)); 3988 3989 /* Similarly, (neg (not X)) is (plus X 1). */ 3990 if (GET_CODE (XEXP (x, 0)) == NOT) 3991 return plus_constant (XEXP (XEXP (x, 0), 0), 1); 3992 3993 /* (neg (minus X Y)) can become (minus Y X). */ 3994 if (GET_CODE (XEXP (x, 0)) == MINUS 3995 && (! FLOAT_MODE_P (mode) 3996 /* x-y != -(y-x) with IEEE floating point. */ 3997 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT 3998 || flag_unsafe_math_optimizations)) 3999 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1), 4000 XEXP (XEXP (x, 0), 0)); 4001 4002 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */ 4003 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx 4004 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1) 4005 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx); 4006 4007 /* NEG commutes with ASHIFT since it is multiplication. Only do this 4008 if we can then eliminate the NEG (e.g., 4009 if the operand is a constant). */ 4010 4011 if (GET_CODE (XEXP (x, 0)) == ASHIFT) 4012 { 4013 temp = simplify_unary_operation (NEG, mode, 4014 XEXP (XEXP (x, 0), 0), mode); 4015 if (temp) 4016 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1)); 4017 } 4018 4019 temp = expand_compound_operation (XEXP (x, 0)); 4020 4021 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be 4022 replaced by (lshiftrt X C). This will convert 4023 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ 4024 4025 if (GET_CODE (temp) == ASHIFTRT 4026 && GET_CODE (XEXP (temp, 1)) == CONST_INT 4027 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1) 4028 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0), 4029 INTVAL (XEXP (temp, 1))); 4030 4031 /* If X has only a single bit that might be nonzero, say, bit I, convert 4032 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of 4033 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to 4034 (sign_extract X 1 Y). But only do this if TEMP isn't a register 4035 or a SUBREG of one since we'd be making the expression more 4036 complex if it was just a register. */ 4037 4038 if (GET_CODE (temp) != REG 4039 && ! (GET_CODE (temp) == SUBREG 4040 && GET_CODE (SUBREG_REG (temp)) == REG) 4041 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) 4042 { 4043 rtx temp1 = simplify_shift_const 4044 (NULL_RTX, ASHIFTRT, mode, 4045 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, 4046 GET_MODE_BITSIZE (mode) - 1 - i), 4047 GET_MODE_BITSIZE (mode) - 1 - i); 4048 4049 /* If all we did was surround TEMP with the two shifts, we 4050 haven't improved anything, so don't use it. Otherwise, 4051 we are better off with TEMP1. */ 4052 if (GET_CODE (temp1) != ASHIFTRT 4053 || GET_CODE (XEXP (temp1, 0)) != ASHIFT 4054 || XEXP (XEXP (temp1, 0), 0) != temp) 4055 return temp1; 4056 } 4057 break; 4058 4059 case TRUNCATE: 4060 /* We can't handle truncation to a partial integer mode here 4061 because we don't know the real bitsize of the partial 4062 integer mode. */ 4063 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) 4064 break; 4065 4066 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4067 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 4068 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))) 4069 SUBST (XEXP (x, 0), 4070 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), 4071 GET_MODE_MASK (mode), NULL_RTX, 0)); 4072 4073 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */ 4074 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND 4075 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) 4076 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) 4077 return XEXP (XEXP (x, 0), 0); 4078 4079 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is 4080 (OP:SI foo:SI) if OP is NEG or ABS. */ 4081 if ((GET_CODE (XEXP (x, 0)) == ABS 4082 || GET_CODE (XEXP (x, 0)) == NEG) 4083 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND 4084 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND) 4085 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) 4086 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode, 4087 XEXP (XEXP (XEXP (x, 0), 0), 0), mode); 4088 4089 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is 4090 (truncate:SI x). */ 4091 if (GET_CODE (XEXP (x, 0)) == SUBREG 4092 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE 4093 && subreg_lowpart_p (XEXP (x, 0))) 4094 return SUBREG_REG (XEXP (x, 0)); 4095 4096 /* If we know that the value is already truncated, we can 4097 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION 4098 is nonzero for the corresponding modes. But don't do this 4099 for an (LSHIFTRT (MULT ...)) since this will cause problems 4100 with the umulXi3_highpart patterns. */ 4101 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 4102 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) 4103 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 4104 >= GET_MODE_BITSIZE (mode) + 1 4105 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT 4106 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)) 4107 return gen_lowpart_for_combine (mode, XEXP (x, 0)); 4108 4109 /* A truncate of a comparison can be replaced with a subreg if 4110 STORE_FLAG_VALUE permits. This is like the previous test, 4111 but it works even if the comparison is done in a mode larger 4112 than HOST_BITS_PER_WIDE_INT. */ 4113 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4114 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 4115 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0) 4116 return gen_lowpart_for_combine (mode, XEXP (x, 0)); 4117 4118 /* Similarly, a truncate of a register whose value is a 4119 comparison can be replaced with a subreg if STORE_FLAG_VALUE 4120 permits. */ 4121 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4122 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0 4123 && (temp = get_last_value (XEXP (x, 0))) 4124 && GET_RTX_CLASS (GET_CODE (temp)) == '<') 4125 return gen_lowpart_for_combine (mode, XEXP (x, 0)); 4126 4127 break; 4128 4129 case FLOAT_TRUNCATE: 4130 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */ 4131 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND 4132 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) 4133 return XEXP (XEXP (x, 0), 0); 4134 4135 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is 4136 (OP:SF foo:SF) if OP is NEG or ABS. */ 4137 if ((GET_CODE (XEXP (x, 0)) == ABS 4138 || GET_CODE (XEXP (x, 0)) == NEG) 4139 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND 4140 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) 4141 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode, 4142 XEXP (XEXP (XEXP (x, 0), 0), 0), mode); 4143 4144 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0)) 4145 is (float_truncate:SF x). */ 4146 if (GET_CODE (XEXP (x, 0)) == SUBREG 4147 && subreg_lowpart_p (XEXP (x, 0)) 4148 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE) 4149 return SUBREG_REG (XEXP (x, 0)); 4150 break; 4151 4152#ifdef HAVE_cc0 4153 case COMPARE: 4154 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't 4155 using cc0, in which case we want to leave it as a COMPARE 4156 so we can distinguish it from a register-register-copy. */ 4157 if (XEXP (x, 1) == const0_rtx) 4158 return XEXP (x, 0); 4159 4160 /* In IEEE floating point, x-0 is not the same as x. */ 4161 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT 4162 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))) 4163 || flag_unsafe_math_optimizations) 4164 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0)))) 4165 return XEXP (x, 0); 4166 break; 4167#endif 4168 4169 case CONST: 4170 /* (const (const X)) can become (const X). Do it this way rather than 4171 returning the inner CONST since CONST can be shared with a 4172 REG_EQUAL note. */ 4173 if (GET_CODE (XEXP (x, 0)) == CONST) 4174 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4175 break; 4176 4177#ifdef HAVE_lo_sum 4178 case LO_SUM: 4179 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we 4180 can add in an offset. find_split_point will split this address up 4181 again if it doesn't match. */ 4182 if (GET_CODE (XEXP (x, 0)) == HIGH 4183 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) 4184 return XEXP (x, 1); 4185 break; 4186#endif 4187 4188 case PLUS: 4189 /* If we have (plus (plus (A const) B)), associate it so that CONST is 4190 outermost. That's because that's the way indexed addresses are 4191 supposed to appear. This code used to check many more cases, but 4192 they are now checked elsewhere. */ 4193 if (GET_CODE (XEXP (x, 0)) == PLUS 4194 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1))) 4195 return gen_binary (PLUS, mode, 4196 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), 4197 XEXP (x, 1)), 4198 XEXP (XEXP (x, 0), 1)); 4199 4200 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) 4201 when c is (const_int (pow2 + 1) / 2) is a sign extension of a 4202 bit-field and can be replaced by either a sign_extend or a 4203 sign_extract. The `and' may be a zero_extend and the two 4204 <c>, -<c> constants may be reversed. */ 4205 if (GET_CODE (XEXP (x, 0)) == XOR 4206 && GET_CODE (XEXP (x, 1)) == CONST_INT 4207 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 4208 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1)) 4209 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 4210 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) 4211 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4212 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND 4213 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT 4214 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) 4215 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1)) 4216 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND 4217 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) 4218 == (unsigned int) i + 1)))) 4219 return simplify_shift_const 4220 (NULL_RTX, ASHIFTRT, mode, 4221 simplify_shift_const (NULL_RTX, ASHIFT, mode, 4222 XEXP (XEXP (XEXP (x, 0), 0), 0), 4223 GET_MODE_BITSIZE (mode) - (i + 1)), 4224 GET_MODE_BITSIZE (mode) - (i + 1)); 4225 4226 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if 4227 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE 4228 is 1. This produces better code than the alternative immediately 4229 below. */ 4230 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 4231 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx) 4232 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)) 4233 && (reversed = reversed_comparison (XEXP (x, 0), mode, 4234 XEXP (XEXP (x, 0), 0), 4235 XEXP (XEXP (x, 0), 1)))) 4236 return 4237 simplify_gen_unary (NEG, mode, reversed, mode); 4238 4239 /* If only the low-order bit of X is possibly nonzero, (plus x -1) 4240 can become (ashiftrt (ashift (xor x 1) C) C) where C is 4241 the bitsize of the mode - 1. This allows simplification of 4242 "a = (b & 8) == 0;" */ 4243 if (XEXP (x, 1) == constm1_rtx 4244 && GET_CODE (XEXP (x, 0)) != REG 4245 && ! (GET_CODE (XEXP (x,0)) == SUBREG 4246 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG) 4247 && nonzero_bits (XEXP (x, 0), mode) == 1) 4248 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, 4249 simplify_shift_const (NULL_RTX, ASHIFT, mode, 4250 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx), 4251 GET_MODE_BITSIZE (mode) - 1), 4252 GET_MODE_BITSIZE (mode) - 1); 4253 4254 /* If we are adding two things that have no bits in common, convert 4255 the addition into an IOR. This will often be further simplified, 4256 for example in cases like ((a & 1) + (a & 2)), which can 4257 become a & 3. */ 4258 4259 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4260 && (nonzero_bits (XEXP (x, 0), mode) 4261 & nonzero_bits (XEXP (x, 1), mode)) == 0) 4262 { 4263 /* Try to simplify the expression further. */ 4264 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); 4265 temp = combine_simplify_rtx (tor, mode, last, in_dest); 4266 4267 /* If we could, great. If not, do not go ahead with the IOR 4268 replacement, since PLUS appears in many special purpose 4269 address arithmetic instructions. */ 4270 if (GET_CODE (temp) != CLOBBER && temp != tor) 4271 return temp; 4272 } 4273 break; 4274 4275 case MINUS: 4276 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done 4277 by reversing the comparison code if valid. */ 4278 if (STORE_FLAG_VALUE == 1 4279 && XEXP (x, 0) == const1_rtx 4280 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<' 4281 && (reversed = reversed_comparison (XEXP (x, 1), mode, 4282 XEXP (XEXP (x, 1), 0), 4283 XEXP (XEXP (x, 1), 1)))) 4284 return reversed; 4285 4286 /* (minus <foo> (and <foo> (const_int -pow2))) becomes 4287 (and <foo> (const_int pow2-1)) */ 4288 if (GET_CODE (XEXP (x, 1)) == AND 4289 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 4290 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0 4291 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) 4292 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), 4293 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1); 4294 4295 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for 4296 integers. */ 4297 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode)) 4298 return gen_binary (MINUS, mode, 4299 gen_binary (MINUS, mode, XEXP (x, 0), 4300 XEXP (XEXP (x, 1), 0)), 4301 XEXP (XEXP (x, 1), 1)); 4302 break; 4303 4304 case MULT: 4305 /* If we have (mult (plus A B) C), apply the distributive law and then 4306 the inverse distributive law to see if things simplify. This 4307 occurs mostly in addresses, often when unrolling loops. */ 4308 4309 if (GET_CODE (XEXP (x, 0)) == PLUS) 4310 { 4311 x = apply_distributive_law 4312 (gen_binary (PLUS, mode, 4313 gen_binary (MULT, mode, 4314 XEXP (XEXP (x, 0), 0), XEXP (x, 1)), 4315 gen_binary (MULT, mode, 4316 XEXP (XEXP (x, 0), 1), 4317 copy_rtx (XEXP (x, 1))))); 4318 4319 if (GET_CODE (x) != MULT) 4320 return x; 4321 } 4322 /* Try simplify a*(b/c) as (a*b)/c. */ 4323 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations 4324 && GET_CODE (XEXP (x, 0)) == DIV) 4325 { 4326 rtx tem = simplify_binary_operation (MULT, mode, 4327 XEXP (XEXP (x, 0), 0), 4328 XEXP (x, 1)); 4329 if (tem) 4330 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1)); 4331 } 4332 break; 4333 4334 case UDIV: 4335 /* If this is a divide by a power of two, treat it as a shift if 4336 its first operand is a shift. */ 4337 if (GET_CODE (XEXP (x, 1)) == CONST_INT 4338 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 4339 && (GET_CODE (XEXP (x, 0)) == ASHIFT 4340 || GET_CODE (XEXP (x, 0)) == LSHIFTRT 4341 || GET_CODE (XEXP (x, 0)) == ASHIFTRT 4342 || GET_CODE (XEXP (x, 0)) == ROTATE 4343 || GET_CODE (XEXP (x, 0)) == ROTATERT)) 4344 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); 4345 break; 4346 4347 case EQ: case NE: 4348 case GT: case GTU: case GE: case GEU: 4349 case LT: case LTU: case LE: case LEU: 4350 case UNEQ: case LTGT: 4351 case UNGT: case UNGE: 4352 case UNLT: case UNLE: 4353 case UNORDERED: case ORDERED: 4354 /* If the first operand is a condition code, we can't do anything 4355 with it. */ 4356 if (GET_CODE (XEXP (x, 0)) == COMPARE 4357 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC 4358#ifdef HAVE_cc0 4359 && XEXP (x, 0) != cc0_rtx 4360#endif 4361 )) 4362 { 4363 rtx op0 = XEXP (x, 0); 4364 rtx op1 = XEXP (x, 1); 4365 enum rtx_code new_code; 4366 4367 if (GET_CODE (op0) == COMPARE) 4368 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); 4369 4370 /* Simplify our comparison, if possible. */ 4371 new_code = simplify_comparison (code, &op0, &op1); 4372 4373 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X 4374 if only the low-order bit is possibly nonzero in X (such as when 4375 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to 4376 (xor X 1) or (minus 1 X); we use the former. Finally, if X is 4377 known to be either 0 or -1, NE becomes a NEG and EQ becomes 4378 (plus X 1). 4379 4380 Remove any ZERO_EXTRACT we made when thinking this was a 4381 comparison. It may now be simpler to use, e.g., an AND. If a 4382 ZERO_EXTRACT is indeed appropriate, it will be placed back by 4383 the call to make_compound_operation in the SET case. */ 4384 4385 if (STORE_FLAG_VALUE == 1 4386 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4387 && op1 == const0_rtx 4388 && mode == GET_MODE (op0) 4389 && nonzero_bits (op0, mode) == 1) 4390 return gen_lowpart_for_combine (mode, 4391 expand_compound_operation (op0)); 4392 4393 else if (STORE_FLAG_VALUE == 1 4394 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4395 && op1 == const0_rtx 4396 && mode == GET_MODE (op0) 4397 && (num_sign_bit_copies (op0, mode) 4398 == GET_MODE_BITSIZE (mode))) 4399 { 4400 op0 = expand_compound_operation (op0); 4401 return simplify_gen_unary (NEG, mode, 4402 gen_lowpart_for_combine (mode, op0), 4403 mode); 4404 } 4405 4406 else if (STORE_FLAG_VALUE == 1 4407 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4408 && op1 == const0_rtx 4409 && mode == GET_MODE (op0) 4410 && nonzero_bits (op0, mode) == 1) 4411 { 4412 op0 = expand_compound_operation (op0); 4413 return gen_binary (XOR, mode, 4414 gen_lowpart_for_combine (mode, op0), 4415 const1_rtx); 4416 } 4417 4418 else if (STORE_FLAG_VALUE == 1 4419 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4420 && op1 == const0_rtx 4421 && mode == GET_MODE (op0) 4422 && (num_sign_bit_copies (op0, mode) 4423 == GET_MODE_BITSIZE (mode))) 4424 { 4425 op0 = expand_compound_operation (op0); 4426 return plus_constant (gen_lowpart_for_combine (mode, op0), 1); 4427 } 4428 4429 /* If STORE_FLAG_VALUE is -1, we have cases similar to 4430 those above. */ 4431 if (STORE_FLAG_VALUE == -1 4432 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4433 && op1 == const0_rtx 4434 && (num_sign_bit_copies (op0, mode) 4435 == GET_MODE_BITSIZE (mode))) 4436 return gen_lowpart_for_combine (mode, 4437 expand_compound_operation (op0)); 4438 4439 else if (STORE_FLAG_VALUE == -1 4440 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4441 && op1 == const0_rtx 4442 && mode == GET_MODE (op0) 4443 && nonzero_bits (op0, mode) == 1) 4444 { 4445 op0 = expand_compound_operation (op0); 4446 return simplify_gen_unary (NEG, mode, 4447 gen_lowpart_for_combine (mode, op0), 4448 mode); 4449 } 4450 4451 else if (STORE_FLAG_VALUE == -1 4452 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4453 && op1 == const0_rtx 4454 && mode == GET_MODE (op0) 4455 && (num_sign_bit_copies (op0, mode) 4456 == GET_MODE_BITSIZE (mode))) 4457 { 4458 op0 = expand_compound_operation (op0); 4459 return simplify_gen_unary (NOT, mode, 4460 gen_lowpart_for_combine (mode, op0), 4461 mode); 4462 } 4463 4464 /* If X is 0/1, (eq X 0) is X-1. */ 4465 else if (STORE_FLAG_VALUE == -1 4466 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4467 && op1 == const0_rtx 4468 && mode == GET_MODE (op0) 4469 && nonzero_bits (op0, mode) == 1) 4470 { 4471 op0 = expand_compound_operation (op0); 4472 return plus_constant (gen_lowpart_for_combine (mode, op0), -1); 4473 } 4474 4475 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just 4476 one bit that might be nonzero, we can convert (ne x 0) to 4477 (ashift x c) where C puts the bit in the sign bit. Remove any 4478 AND with STORE_FLAG_VALUE when we are done, since we are only 4479 going to test the sign bit. */ 4480 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4481 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4482 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) 4483 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1)) 4484 && op1 == const0_rtx 4485 && mode == GET_MODE (op0) 4486 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) 4487 { 4488 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, 4489 expand_compound_operation (op0), 4490 GET_MODE_BITSIZE (mode) - 1 - i); 4491 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) 4492 return XEXP (x, 0); 4493 else 4494 return x; 4495 } 4496 4497 /* If the code changed, return a whole new comparison. */ 4498 if (new_code != code) 4499 return gen_rtx_fmt_ee (new_code, mode, op0, op1); 4500 4501 /* Otherwise, keep this operation, but maybe change its operands. 4502 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ 4503 SUBST (XEXP (x, 0), op0); 4504 SUBST (XEXP (x, 1), op1); 4505 } 4506 break; 4507 4508 case IF_THEN_ELSE: 4509 return simplify_if_then_else (x); 4510 4511 case ZERO_EXTRACT: 4512 case SIGN_EXTRACT: 4513 case ZERO_EXTEND: 4514 case SIGN_EXTEND: 4515 /* If we are processing SET_DEST, we are done. */ 4516 if (in_dest) 4517 return x; 4518 4519 return expand_compound_operation (x); 4520 4521 case SET: 4522 return simplify_set (x); 4523 4524 case AND: 4525 case IOR: 4526 case XOR: 4527 return simplify_logical (x, last); 4528 4529 case ABS: 4530 /* (abs (neg <foo>)) -> (abs <foo>) */ 4531 if (GET_CODE (XEXP (x, 0)) == NEG) 4532 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4533 4534 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS), 4535 do nothing. */ 4536 if (GET_MODE (XEXP (x, 0)) == VOIDmode) 4537 break; 4538 4539 /* If operand is something known to be positive, ignore the ABS. */ 4540 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS 4541 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 4542 <= HOST_BITS_PER_WIDE_INT) 4543 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 4544 & ((HOST_WIDE_INT) 1 4545 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))) 4546 == 0))) 4547 return XEXP (x, 0); 4548 4549 /* If operand is known to be only -1 or 0, convert ABS to NEG. */ 4550 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode)) 4551 return gen_rtx_NEG (mode, XEXP (x, 0)); 4552 4553 break; 4554 4555 case FFS: 4556 /* (ffs (*_extend <X>)) = (ffs <X>) */ 4557 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND 4558 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) 4559 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4560 break; 4561 4562 case FLOAT: 4563 /* (float (sign_extend <X>)) = (float <X>). */ 4564 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) 4565 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4566 break; 4567 4568 case ASHIFT: 4569 case LSHIFTRT: 4570 case ASHIFTRT: 4571 case ROTATE: 4572 case ROTATERT: 4573 /* If this is a shift by a constant amount, simplify it. */ 4574 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 4575 return simplify_shift_const (x, code, mode, XEXP (x, 0), 4576 INTVAL (XEXP (x, 1))); 4577 4578#ifdef SHIFT_COUNT_TRUNCATED 4579 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG) 4580 SUBST (XEXP (x, 1), 4581 force_to_mode (XEXP (x, 1), GET_MODE (x), 4582 ((HOST_WIDE_INT) 1 4583 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) 4584 - 1, 4585 NULL_RTX, 0)); 4586#endif 4587 4588 break; 4589 4590 case VEC_SELECT: 4591 { 4592 rtx op0 = XEXP (x, 0); 4593 rtx op1 = XEXP (x, 1); 4594 int len; 4595 4596 if (GET_CODE (op1) != PARALLEL) 4597 abort (); 4598 len = XVECLEN (op1, 0); 4599 if (len == 1 4600 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT 4601 && GET_CODE (op0) == VEC_CONCAT) 4602 { 4603 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x)); 4604 4605 /* Try to find the element in the VEC_CONCAT. */ 4606 for (;;) 4607 { 4608 if (GET_MODE (op0) == GET_MODE (x)) 4609 return op0; 4610 if (GET_CODE (op0) == VEC_CONCAT) 4611 { 4612 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))); 4613 if (op0_size < offset) 4614 op0 = XEXP (op0, 0); 4615 else 4616 { 4617 offset -= op0_size; 4618 op0 = XEXP (op0, 1); 4619 } 4620 } 4621 else 4622 break; 4623 } 4624 } 4625 } 4626 4627 break; 4628 4629 default: 4630 break; 4631 } 4632 4633 return x; 4634} 4635 4636/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ 4637 4638static rtx 4639simplify_if_then_else (x) 4640 rtx x; 4641{ 4642 enum machine_mode mode = GET_MODE (x); 4643 rtx cond = XEXP (x, 0); 4644 rtx true_rtx = XEXP (x, 1); 4645 rtx false_rtx = XEXP (x, 2); 4646 enum rtx_code true_code = GET_CODE (cond); 4647 int comparison_p = GET_RTX_CLASS (true_code) == '<'; 4648 rtx temp; 4649 int i; 4650 enum rtx_code false_code; 4651 rtx reversed; 4652 4653 /* Simplify storing of the truth value. */ 4654 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx) 4655 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1)); 4656 4657 /* Also when the truth value has to be reversed. */ 4658 if (comparison_p 4659 && true_rtx == const0_rtx && false_rtx == const_true_rtx 4660 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0), 4661 XEXP (cond, 1)))) 4662 return reversed; 4663 4664 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used 4665 in it is being compared against certain values. Get the true and false 4666 comparisons and see if that says anything about the value of each arm. */ 4667 4668 if (comparison_p 4669 && ((false_code = combine_reversed_comparison_code (cond)) 4670 != UNKNOWN) 4671 && GET_CODE (XEXP (cond, 0)) == REG) 4672 { 4673 HOST_WIDE_INT nzb; 4674 rtx from = XEXP (cond, 0); 4675 rtx true_val = XEXP (cond, 1); 4676 rtx false_val = true_val; 4677 int swapped = 0; 4678 4679 /* If FALSE_CODE is EQ, swap the codes and arms. */ 4680 4681 if (false_code == EQ) 4682 { 4683 swapped = 1, true_code = EQ, false_code = NE; 4684 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; 4685 } 4686 4687 /* If we are comparing against zero and the expression being tested has 4688 only a single bit that might be nonzero, that is its value when it is 4689 not equal to zero. Similarly if it is known to be -1 or 0. */ 4690 4691 if (true_code == EQ && true_val == const0_rtx 4692 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) 4693 false_code = EQ, false_val = GEN_INT (nzb); 4694 else if (true_code == EQ && true_val == const0_rtx 4695 && (num_sign_bit_copies (from, GET_MODE (from)) 4696 == GET_MODE_BITSIZE (GET_MODE (from)))) 4697 false_code = EQ, false_val = constm1_rtx; 4698 4699 /* Now simplify an arm if we know the value of the register in the 4700 branch and it is used in the arm. Be careful due to the potential 4701 of locally-shared RTL. */ 4702 4703 if (reg_mentioned_p (from, true_rtx)) 4704 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, 4705 from, true_val), 4706 pc_rtx, pc_rtx, 0, 0); 4707 if (reg_mentioned_p (from, false_rtx)) 4708 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, 4709 from, false_val), 4710 pc_rtx, pc_rtx, 0, 0); 4711 4712 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); 4713 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); 4714 4715 true_rtx = XEXP (x, 1); 4716 false_rtx = XEXP (x, 2); 4717 true_code = GET_CODE (cond); 4718 } 4719 4720 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be 4721 reversed, do so to avoid needing two sets of patterns for 4722 subtract-and-branch insns. Similarly if we have a constant in the true 4723 arm, the false arm is the same as the first operand of the comparison, or 4724 the false arm is more complicated than the true arm. */ 4725 4726 if (comparison_p 4727 && combine_reversed_comparison_code (cond) != UNKNOWN 4728 && (true_rtx == pc_rtx 4729 || (CONSTANT_P (true_rtx) 4730 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx) 4731 || true_rtx == const0_rtx 4732 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o' 4733 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o') 4734 || (GET_CODE (true_rtx) == SUBREG 4735 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o' 4736 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o') 4737 || reg_mentioned_p (true_rtx, false_rtx) 4738 || rtx_equal_p (false_rtx, XEXP (cond, 0)))) 4739 { 4740 true_code = reversed_comparison_code (cond, NULL); 4741 SUBST (XEXP (x, 0), 4742 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0), 4743 XEXP (cond, 1))); 4744 4745 SUBST (XEXP (x, 1), false_rtx); 4746 SUBST (XEXP (x, 2), true_rtx); 4747 4748 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; 4749 cond = XEXP (x, 0); 4750 4751 /* It is possible that the conditional has been simplified out. */ 4752 true_code = GET_CODE (cond); 4753 comparison_p = GET_RTX_CLASS (true_code) == '<'; 4754 } 4755 4756 /* If the two arms are identical, we don't need the comparison. */ 4757 4758 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond)) 4759 return true_rtx; 4760 4761 /* Convert a == b ? b : a to "a". */ 4762 if (true_code == EQ && ! side_effects_p (cond) 4763 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) 4764 && rtx_equal_p (XEXP (cond, 0), false_rtx) 4765 && rtx_equal_p (XEXP (cond, 1), true_rtx)) 4766 return false_rtx; 4767 else if (true_code == NE && ! side_effects_p (cond) 4768 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) 4769 && rtx_equal_p (XEXP (cond, 0), true_rtx) 4770 && rtx_equal_p (XEXP (cond, 1), false_rtx)) 4771 return true_rtx; 4772 4773 /* Look for cases where we have (abs x) or (neg (abs X)). */ 4774 4775 if (GET_MODE_CLASS (mode) == MODE_INT 4776 && GET_CODE (false_rtx) == NEG 4777 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0)) 4778 && comparison_p 4779 && rtx_equal_p (true_rtx, XEXP (cond, 0)) 4780 && ! side_effects_p (true_rtx)) 4781 switch (true_code) 4782 { 4783 case GT: 4784 case GE: 4785 return simplify_gen_unary (ABS, mode, true_rtx, mode); 4786 case LT: 4787 case LE: 4788 return 4789 simplify_gen_unary (NEG, mode, 4790 simplify_gen_unary (ABS, mode, true_rtx, mode), 4791 mode); 4792 default: 4793 break; 4794 } 4795 4796 /* Look for MIN or MAX. */ 4797 4798 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) 4799 && comparison_p 4800 && rtx_equal_p (XEXP (cond, 0), true_rtx) 4801 && rtx_equal_p (XEXP (cond, 1), false_rtx) 4802 && ! side_effects_p (cond)) 4803 switch (true_code) 4804 { 4805 case GE: 4806 case GT: 4807 return gen_binary (SMAX, mode, true_rtx, false_rtx); 4808 case LE: 4809 case LT: 4810 return gen_binary (SMIN, mode, true_rtx, false_rtx); 4811 case GEU: 4812 case GTU: 4813 return gen_binary (UMAX, mode, true_rtx, false_rtx); 4814 case LEU: 4815 case LTU: 4816 return gen_binary (UMIN, mode, true_rtx, false_rtx); 4817 default: 4818 break; 4819 } 4820 4821 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its 4822 second operand is zero, this can be done as (OP Z (mult COND C2)) where 4823 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or 4824 SIGN_EXTEND as long as Z is already extended (so we don't destroy it). 4825 We can do this kind of thing in some cases when STORE_FLAG_VALUE is 4826 neither 1 or -1, but it isn't worth checking for. */ 4827 4828 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 4829 && comparison_p && mode != VOIDmode && ! side_effects_p (x)) 4830 { 4831 rtx t = make_compound_operation (true_rtx, SET); 4832 rtx f = make_compound_operation (false_rtx, SET); 4833 rtx cond_op0 = XEXP (cond, 0); 4834 rtx cond_op1 = XEXP (cond, 1); 4835 enum rtx_code op = NIL, extend_op = NIL; 4836 enum machine_mode m = mode; 4837 rtx z = 0, c1 = NULL_RTX; 4838 4839 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS 4840 || GET_CODE (t) == IOR || GET_CODE (t) == XOR 4841 || GET_CODE (t) == ASHIFT 4842 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) 4843 && rtx_equal_p (XEXP (t, 0), f)) 4844 c1 = XEXP (t, 1), op = GET_CODE (t), z = f; 4845 4846 /* If an identity-zero op is commutative, check whether there 4847 would be a match if we swapped the operands. */ 4848 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR 4849 || GET_CODE (t) == XOR) 4850 && rtx_equal_p (XEXP (t, 1), f)) 4851 c1 = XEXP (t, 0), op = GET_CODE (t), z = f; 4852 else if (GET_CODE (t) == SIGN_EXTEND 4853 && (GET_CODE (XEXP (t, 0)) == PLUS 4854 || GET_CODE (XEXP (t, 0)) == MINUS 4855 || GET_CODE (XEXP (t, 0)) == IOR 4856 || GET_CODE (XEXP (t, 0)) == XOR 4857 || GET_CODE (XEXP (t, 0)) == ASHIFT 4858 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 4859 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 4860 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 4861 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 4862 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 4863 && (num_sign_bit_copies (f, GET_MODE (f)) 4864 > (GET_MODE_BITSIZE (mode) 4865 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0)))))) 4866 { 4867 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 4868 extend_op = SIGN_EXTEND; 4869 m = GET_MODE (XEXP (t, 0)); 4870 } 4871 else if (GET_CODE (t) == SIGN_EXTEND 4872 && (GET_CODE (XEXP (t, 0)) == PLUS 4873 || GET_CODE (XEXP (t, 0)) == IOR 4874 || GET_CODE (XEXP (t, 0)) == XOR) 4875 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 4876 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 4877 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 4878 && (num_sign_bit_copies (f, GET_MODE (f)) 4879 > (GET_MODE_BITSIZE (mode) 4880 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1)))))) 4881 { 4882 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 4883 extend_op = SIGN_EXTEND; 4884 m = GET_MODE (XEXP (t, 0)); 4885 } 4886 else if (GET_CODE (t) == ZERO_EXTEND 4887 && (GET_CODE (XEXP (t, 0)) == PLUS 4888 || GET_CODE (XEXP (t, 0)) == MINUS 4889 || GET_CODE (XEXP (t, 0)) == IOR 4890 || GET_CODE (XEXP (t, 0)) == XOR 4891 || GET_CODE (XEXP (t, 0)) == ASHIFT 4892 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 4893 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 4894 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 4895 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4896 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 4897 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 4898 && ((nonzero_bits (f, GET_MODE (f)) 4899 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) 4900 == 0)) 4901 { 4902 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 4903 extend_op = ZERO_EXTEND; 4904 m = GET_MODE (XEXP (t, 0)); 4905 } 4906 else if (GET_CODE (t) == ZERO_EXTEND 4907 && (GET_CODE (XEXP (t, 0)) == PLUS 4908 || GET_CODE (XEXP (t, 0)) == IOR 4909 || GET_CODE (XEXP (t, 0)) == XOR) 4910 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 4911 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4912 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 4913 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 4914 && ((nonzero_bits (f, GET_MODE (f)) 4915 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) 4916 == 0)) 4917 { 4918 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 4919 extend_op = ZERO_EXTEND; 4920 m = GET_MODE (XEXP (t, 0)); 4921 } 4922 4923 if (z) 4924 { 4925 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1), 4926 pc_rtx, pc_rtx, 0, 0); 4927 temp = gen_binary (MULT, m, temp, 4928 gen_binary (MULT, m, c1, const_true_rtx)); 4929 temp = subst (temp, pc_rtx, pc_rtx, 0, 0); 4930 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp); 4931 4932 if (extend_op != NIL) 4933 temp = simplify_gen_unary (extend_op, mode, temp, m); 4934 4935 return temp; 4936 } 4937 } 4938 4939 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or 4940 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the 4941 negation of a single bit, we can convert this operation to a shift. We 4942 can actually do this more generally, but it doesn't seem worth it. */ 4943 4944 if (true_code == NE && XEXP (cond, 1) == const0_rtx 4945 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT 4946 && ((1 == nonzero_bits (XEXP (cond, 0), mode) 4947 && (i = exact_log2 (INTVAL (true_rtx))) >= 0) 4948 || ((num_sign_bit_copies (XEXP (cond, 0), mode) 4949 == GET_MODE_BITSIZE (mode)) 4950 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0))) 4951 return 4952 simplify_shift_const (NULL_RTX, ASHIFT, mode, 4953 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i); 4954 4955 return x; 4956} 4957 4958/* Simplify X, a SET expression. Return the new expression. */ 4959 4960static rtx 4961simplify_set (x) 4962 rtx x; 4963{ 4964 rtx src = SET_SRC (x); 4965 rtx dest = SET_DEST (x); 4966 enum machine_mode mode 4967 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); 4968 rtx other_insn; 4969 rtx *cc_use; 4970 4971 /* (set (pc) (return)) gets written as (return). */ 4972 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN) 4973 return src; 4974 4975 /* Now that we know for sure which bits of SRC we are using, see if we can 4976 simplify the expression for the object knowing that we only need the 4977 low-order bits. */ 4978 4979 if (GET_MODE_CLASS (mode) == MODE_INT) 4980 { 4981 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0); 4982 SUBST (SET_SRC (x), src); 4983 } 4984 4985 /* If we are setting CC0 or if the source is a COMPARE, look for the use of 4986 the comparison result and try to simplify it unless we already have used 4987 undobuf.other_insn. */ 4988 if ((GET_CODE (src) == COMPARE 4989#ifdef HAVE_cc0 4990 || dest == cc0_rtx 4991#endif 4992 ) 4993 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 4994 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) 4995 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<' 4996 && rtx_equal_p (XEXP (*cc_use, 0), dest)) 4997 { 4998 enum rtx_code old_code = GET_CODE (*cc_use); 4999 enum rtx_code new_code; 5000 rtx op0, op1; 5001 int other_changed = 0; 5002 enum machine_mode compare_mode = GET_MODE (dest); 5003 5004 if (GET_CODE (src) == COMPARE) 5005 op0 = XEXP (src, 0), op1 = XEXP (src, 1); 5006 else 5007 op0 = src, op1 = const0_rtx; 5008 5009 /* Simplify our comparison, if possible. */ 5010 new_code = simplify_comparison (old_code, &op0, &op1); 5011 5012#ifdef EXTRA_CC_MODES 5013 /* If this machine has CC modes other than CCmode, check to see if we 5014 need to use a different CC mode here. */ 5015 compare_mode = SELECT_CC_MODE (new_code, op0, op1); 5016#endif /* EXTRA_CC_MODES */ 5017 5018#if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES) 5019 /* If the mode changed, we have to change SET_DEST, the mode in the 5020 compare, and the mode in the place SET_DEST is used. If SET_DEST is 5021 a hard register, just build new versions with the proper mode. If it 5022 is a pseudo, we lose unless it is only time we set the pseudo, in 5023 which case we can safely change its mode. */ 5024 if (compare_mode != GET_MODE (dest)) 5025 { 5026 unsigned int regno = REGNO (dest); 5027 rtx new_dest = gen_rtx_REG (compare_mode, regno); 5028 5029 if (regno < FIRST_PSEUDO_REGISTER 5030 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest))) 5031 { 5032 if (regno >= FIRST_PSEUDO_REGISTER) 5033 SUBST (regno_reg_rtx[regno], new_dest); 5034 5035 SUBST (SET_DEST (x), new_dest); 5036 SUBST (XEXP (*cc_use, 0), new_dest); 5037 other_changed = 1; 5038 5039 dest = new_dest; 5040 } 5041 } 5042#endif 5043 5044 /* If the code changed, we have to build a new comparison in 5045 undobuf.other_insn. */ 5046 if (new_code != old_code) 5047 { 5048 unsigned HOST_WIDE_INT mask; 5049 5050 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use), 5051 dest, const0_rtx)); 5052 5053 /* If the only change we made was to change an EQ into an NE or 5054 vice versa, OP0 has only one bit that might be nonzero, and OP1 5055 is zero, check if changing the user of the condition code will 5056 produce a valid insn. If it won't, we can keep the original code 5057 in that insn by surrounding our operation with an XOR. */ 5058 5059 if (((old_code == NE && new_code == EQ) 5060 || (old_code == EQ && new_code == NE)) 5061 && ! other_changed && op1 == const0_rtx 5062 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 5063 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0) 5064 { 5065 rtx pat = PATTERN (other_insn), note = 0; 5066 5067 if ((recog_for_combine (&pat, other_insn, ¬e) < 0 5068 && ! check_asm_operands (pat))) 5069 { 5070 PUT_CODE (*cc_use, old_code); 5071 other_insn = 0; 5072 5073 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask)); 5074 } 5075 } 5076 5077 other_changed = 1; 5078 } 5079 5080 if (other_changed) 5081 undobuf.other_insn = other_insn; 5082 5083#ifdef HAVE_cc0 5084 /* If we are now comparing against zero, change our source if 5085 needed. If we do not use cc0, we always have a COMPARE. */ 5086 if (op1 == const0_rtx && dest == cc0_rtx) 5087 { 5088 SUBST (SET_SRC (x), op0); 5089 src = op0; 5090 } 5091 else 5092#endif 5093 5094 /* Otherwise, if we didn't previously have a COMPARE in the 5095 correct mode, we need one. */ 5096 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode) 5097 { 5098 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); 5099 src = SET_SRC (x); 5100 } 5101 else 5102 { 5103 /* Otherwise, update the COMPARE if needed. */ 5104 SUBST (XEXP (src, 0), op0); 5105 SUBST (XEXP (src, 1), op1); 5106 } 5107 } 5108 else 5109 { 5110 /* Get SET_SRC in a form where we have placed back any 5111 compound expressions. Then do the checks below. */ 5112 src = make_compound_operation (src, SET); 5113 SUBST (SET_SRC (x), src); 5114 } 5115 5116 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, 5117 and X being a REG or (subreg (reg)), we may be able to convert this to 5118 (set (subreg:m2 x) (op)). 5119 5120 We can always do this if M1 is narrower than M2 because that means that 5121 we only care about the low bits of the result. 5122 5123 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot 5124 perform a narrower operation than requested since the high-order bits will 5125 be undefined. On machine where it is defined, this transformation is safe 5126 as long as M1 and M2 have the same number of words. */ 5127 5128 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 5129 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o' 5130 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) 5131 / UNITS_PER_WORD) 5132 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) 5133 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) 5134#ifndef WORD_REGISTER_OPERATIONS 5135 && (GET_MODE_SIZE (GET_MODE (src)) 5136 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) 5137#endif 5138#ifdef CLASS_CANNOT_CHANGE_MODE 5139 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER 5140 && (TEST_HARD_REG_BIT 5141 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], 5142 REGNO (dest))) 5143 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src), 5144 GET_MODE (SUBREG_REG (src)))) 5145#endif 5146 && (GET_CODE (dest) == REG 5147 || (GET_CODE (dest) == SUBREG 5148 && GET_CODE (SUBREG_REG (dest)) == REG))) 5149 { 5150 SUBST (SET_DEST (x), 5151 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)), 5152 dest)); 5153 SUBST (SET_SRC (x), SUBREG_REG (src)); 5154 5155 src = SET_SRC (x), dest = SET_DEST (x); 5156 } 5157 5158#ifdef LOAD_EXTEND_OP 5159 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this 5160 would require a paradoxical subreg. Replace the subreg with a 5161 zero_extend to avoid the reload that would otherwise be required. */ 5162 5163 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 5164 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL 5165 && SUBREG_BYTE (src) == 0 5166 && (GET_MODE_SIZE (GET_MODE (src)) 5167 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) 5168 && GET_CODE (SUBREG_REG (src)) == MEM) 5169 { 5170 SUBST (SET_SRC (x), 5171 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))), 5172 GET_MODE (src), SUBREG_REG (src))); 5173 5174 src = SET_SRC (x); 5175 } 5176#endif 5177 5178 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we 5179 are comparing an item known to be 0 or -1 against 0, use a logical 5180 operation instead. Check for one of the arms being an IOR of the other 5181 arm with some value. We compute three terms to be IOR'ed together. In 5182 practice, at most two will be nonzero. Then we do the IOR's. */ 5183 5184 if (GET_CODE (dest) != PC 5185 && GET_CODE (src) == IF_THEN_ELSE 5186 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT 5187 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) 5188 && XEXP (XEXP (src, 0), 1) == const0_rtx 5189 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) 5190#ifdef HAVE_conditional_move 5191 && ! can_conditionally_move_p (GET_MODE (src)) 5192#endif 5193 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), 5194 GET_MODE (XEXP (XEXP (src, 0), 0))) 5195 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0)))) 5196 && ! side_effects_p (src)) 5197 { 5198 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE 5199 ? XEXP (src, 1) : XEXP (src, 2)); 5200 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE 5201 ? XEXP (src, 2) : XEXP (src, 1)); 5202 rtx term1 = const0_rtx, term2, term3; 5203 5204 if (GET_CODE (true_rtx) == IOR 5205 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx)) 5206 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx; 5207 else if (GET_CODE (true_rtx) == IOR 5208 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx)) 5209 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx; 5210 else if (GET_CODE (false_rtx) == IOR 5211 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx)) 5212 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx; 5213 else if (GET_CODE (false_rtx) == IOR 5214 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx)) 5215 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx; 5216 5217 term2 = gen_binary (AND, GET_MODE (src), 5218 XEXP (XEXP (src, 0), 0), true_rtx); 5219 term3 = gen_binary (AND, GET_MODE (src), 5220 simplify_gen_unary (NOT, GET_MODE (src), 5221 XEXP (XEXP (src, 0), 0), 5222 GET_MODE (src)), 5223 false_rtx); 5224 5225 SUBST (SET_SRC (x), 5226 gen_binary (IOR, GET_MODE (src), 5227 gen_binary (IOR, GET_MODE (src), term1, term2), 5228 term3)); 5229 5230 src = SET_SRC (x); 5231 } 5232 5233 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this 5234 whole thing fail. */ 5235 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) 5236 return src; 5237 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) 5238 return dest; 5239 else 5240 /* Convert this into a field assignment operation, if possible. */ 5241 return make_field_assignment (x); 5242} 5243 5244/* Simplify, X, and AND, IOR, or XOR operation, and return the simplified 5245 result. LAST is nonzero if this is the last retry. */ 5246 5247static rtx 5248simplify_logical (x, last) 5249 rtx x; 5250 int last; 5251{ 5252 enum machine_mode mode = GET_MODE (x); 5253 rtx op0 = XEXP (x, 0); 5254 rtx op1 = XEXP (x, 1); 5255 rtx reversed; 5256 5257 switch (GET_CODE (x)) 5258 { 5259 case AND: 5260 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single 5261 insn (and may simplify more). */ 5262 if (GET_CODE (op0) == XOR 5263 && rtx_equal_p (XEXP (op0, 0), op1) 5264 && ! side_effects_p (op1)) 5265 x = gen_binary (AND, mode, 5266 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode), 5267 op1); 5268 5269 if (GET_CODE (op0) == XOR 5270 && rtx_equal_p (XEXP (op0, 1), op1) 5271 && ! side_effects_p (op1)) 5272 x = gen_binary (AND, mode, 5273 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode), 5274 op1); 5275 5276 /* Similarly for (~(A ^ B)) & A. */ 5277 if (GET_CODE (op0) == NOT 5278 && GET_CODE (XEXP (op0, 0)) == XOR 5279 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1) 5280 && ! side_effects_p (op1)) 5281 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1); 5282 5283 if (GET_CODE (op0) == NOT 5284 && GET_CODE (XEXP (op0, 0)) == XOR 5285 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1) 5286 && ! side_effects_p (op1)) 5287 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1); 5288 5289 /* We can call simplify_and_const_int only if we don't lose 5290 any (sign) bits when converting INTVAL (op1) to 5291 "unsigned HOST_WIDE_INT". */ 5292 if (GET_CODE (op1) == CONST_INT 5293 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5294 || INTVAL (op1) > 0)) 5295 { 5296 x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); 5297 5298 /* If we have (ior (and (X C1) C2)) and the next restart would be 5299 the last, simplify this by making C1 as small as possible 5300 and then exit. */ 5301 if (last 5302 && GET_CODE (x) == IOR && GET_CODE (op0) == AND 5303 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5304 && GET_CODE (op1) == CONST_INT) 5305 return gen_binary (IOR, mode, 5306 gen_binary (AND, mode, XEXP (op0, 0), 5307 GEN_INT (INTVAL (XEXP (op0, 1)) 5308 & ~INTVAL (op1))), op1); 5309 5310 if (GET_CODE (x) != AND) 5311 return x; 5312 5313 if (GET_RTX_CLASS (GET_CODE (x)) == 'c' 5314 || GET_RTX_CLASS (GET_CODE (x)) == '2') 5315 op0 = XEXP (x, 0), op1 = XEXP (x, 1); 5316 } 5317 5318 /* Convert (A | B) & A to A. */ 5319 if (GET_CODE (op0) == IOR 5320 && (rtx_equal_p (XEXP (op0, 0), op1) 5321 || rtx_equal_p (XEXP (op0, 1), op1)) 5322 && ! side_effects_p (XEXP (op0, 0)) 5323 && ! side_effects_p (XEXP (op0, 1))) 5324 return op1; 5325 5326 /* In the following group of tests (and those in case IOR below), 5327 we start with some combination of logical operations and apply 5328 the distributive law followed by the inverse distributive law. 5329 Most of the time, this results in no change. However, if some of 5330 the operands are the same or inverses of each other, simplifications 5331 will result. 5332 5333 For example, (and (ior A B) (not B)) can occur as the result of 5334 expanding a bit field assignment. When we apply the distributive 5335 law to this, we get (ior (and (A (not B))) (and (B (not B)))), 5336 which then simplifies to (and (A (not B))). 5337 5338 If we have (and (ior A B) C), apply the distributive law and then 5339 the inverse distributive law to see if things simplify. */ 5340 5341 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) 5342 { 5343 x = apply_distributive_law 5344 (gen_binary (GET_CODE (op0), mode, 5345 gen_binary (AND, mode, XEXP (op0, 0), op1), 5346 gen_binary (AND, mode, XEXP (op0, 1), 5347 copy_rtx (op1)))); 5348 if (GET_CODE (x) != AND) 5349 return x; 5350 } 5351 5352 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) 5353 return apply_distributive_law 5354 (gen_binary (GET_CODE (op1), mode, 5355 gen_binary (AND, mode, XEXP (op1, 0), op0), 5356 gen_binary (AND, mode, XEXP (op1, 1), 5357 copy_rtx (op0)))); 5358 5359 /* Similarly, taking advantage of the fact that 5360 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */ 5361 5362 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR) 5363 return apply_distributive_law 5364 (gen_binary (XOR, mode, 5365 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)), 5366 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)), 5367 XEXP (op1, 1)))); 5368 5369 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR) 5370 return apply_distributive_law 5371 (gen_binary (XOR, mode, 5372 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)), 5373 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1)))); 5374 break; 5375 5376 case IOR: 5377 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ 5378 if (GET_CODE (op1) == CONST_INT 5379 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5380 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0) 5381 return op1; 5382 5383 /* Convert (A & B) | A to A. */ 5384 if (GET_CODE (op0) == AND 5385 && (rtx_equal_p (XEXP (op0, 0), op1) 5386 || rtx_equal_p (XEXP (op0, 1), op1)) 5387 && ! side_effects_p (XEXP (op0, 0)) 5388 && ! side_effects_p (XEXP (op0, 1))) 5389 return op1; 5390 5391 /* If we have (ior (and A B) C), apply the distributive law and then 5392 the inverse distributive law to see if things simplify. */ 5393 5394 if (GET_CODE (op0) == AND) 5395 { 5396 x = apply_distributive_law 5397 (gen_binary (AND, mode, 5398 gen_binary (IOR, mode, XEXP (op0, 0), op1), 5399 gen_binary (IOR, mode, XEXP (op0, 1), 5400 copy_rtx (op1)))); 5401 5402 if (GET_CODE (x) != IOR) 5403 return x; 5404 } 5405 5406 if (GET_CODE (op1) == AND) 5407 { 5408 x = apply_distributive_law 5409 (gen_binary (AND, mode, 5410 gen_binary (IOR, mode, XEXP (op1, 0), op0), 5411 gen_binary (IOR, mode, XEXP (op1, 1), 5412 copy_rtx (op0)))); 5413 5414 if (GET_CODE (x) != IOR) 5415 return x; 5416 } 5417 5418 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the 5419 mode size to (rotate A CX). */ 5420 5421 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT) 5422 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT)) 5423 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0)) 5424 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5425 && GET_CODE (XEXP (op1, 1)) == CONST_INT 5426 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1)) 5427 == GET_MODE_BITSIZE (mode))) 5428 return gen_rtx_ROTATE (mode, XEXP (op0, 0), 5429 (GET_CODE (op0) == ASHIFT 5430 ? XEXP (op0, 1) : XEXP (op1, 1))); 5431 5432 /* If OP0 is (ashiftrt (plus ...) C), it might actually be 5433 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS 5434 does not affect any of the bits in OP1, it can really be done 5435 as a PLUS and we can associate. We do this by seeing if OP1 5436 can be safely shifted left C bits. */ 5437 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT 5438 && GET_CODE (XEXP (op0, 0)) == PLUS 5439 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 5440 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5441 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT) 5442 { 5443 int count = INTVAL (XEXP (op0, 1)); 5444 HOST_WIDE_INT mask = INTVAL (op1) << count; 5445 5446 if (mask >> count == INTVAL (op1) 5447 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0) 5448 { 5449 SUBST (XEXP (XEXP (op0, 0), 1), 5450 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask)); 5451 return op0; 5452 } 5453 } 5454 break; 5455 5456 case XOR: 5457 /* If we are XORing two things that have no bits in common, 5458 convert them into an IOR. This helps to detect rotation encoded 5459 using those methods and possibly other simplifications. */ 5460 5461 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5462 && (nonzero_bits (op0, mode) 5463 & nonzero_bits (op1, mode)) == 0) 5464 return (gen_binary (IOR, mode, op0, op1)); 5465 5466 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y). 5467 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for 5468 (NOT y). */ 5469 { 5470 int num_negated = 0; 5471 5472 if (GET_CODE (op0) == NOT) 5473 num_negated++, op0 = XEXP (op0, 0); 5474 if (GET_CODE (op1) == NOT) 5475 num_negated++, op1 = XEXP (op1, 0); 5476 5477 if (num_negated == 2) 5478 { 5479 SUBST (XEXP (x, 0), op0); 5480 SUBST (XEXP (x, 1), op1); 5481 } 5482 else if (num_negated == 1) 5483 return 5484 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1), 5485 mode); 5486 } 5487 5488 /* Convert (xor (and A B) B) to (and (not A) B). The latter may 5489 correspond to a machine insn or result in further simplifications 5490 if B is a constant. */ 5491 5492 if (GET_CODE (op0) == AND 5493 && rtx_equal_p (XEXP (op0, 1), op1) 5494 && ! side_effects_p (op1)) 5495 return gen_binary (AND, mode, 5496 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode), 5497 op1); 5498 5499 else if (GET_CODE (op0) == AND 5500 && rtx_equal_p (XEXP (op0, 0), op1) 5501 && ! side_effects_p (op1)) 5502 return gen_binary (AND, mode, 5503 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode), 5504 op1); 5505 5506 /* (xor (comparison foo bar) (const_int 1)) can become the reversed 5507 comparison if STORE_FLAG_VALUE is 1. */ 5508 if (STORE_FLAG_VALUE == 1 5509 && op1 == const1_rtx 5510 && GET_RTX_CLASS (GET_CODE (op0)) == '<' 5511 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0), 5512 XEXP (op0, 1)))) 5513 return reversed; 5514 5515 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1 5516 is (lt foo (const_int 0)), so we can perform the above 5517 simplification if STORE_FLAG_VALUE is 1. */ 5518 5519 if (STORE_FLAG_VALUE == 1 5520 && op1 == const1_rtx 5521 && GET_CODE (op0) == LSHIFTRT 5522 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5523 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1) 5524 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx); 5525 5526 /* (xor (comparison foo bar) (const_int sign-bit)) 5527 when STORE_FLAG_VALUE is the sign bit. */ 5528 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5529 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) 5530 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) 5531 && op1 == const_true_rtx 5532 && GET_RTX_CLASS (GET_CODE (op0)) == '<' 5533 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0), 5534 XEXP (op0, 1)))) 5535 return reversed; 5536 5537 break; 5538 5539 default: 5540 abort (); 5541 } 5542 5543 return x; 5544} 5545 5546/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound 5547 operations" because they can be replaced with two more basic operations. 5548 ZERO_EXTEND is also considered "compound" because it can be replaced with 5549 an AND operation, which is simpler, though only one operation. 5550 5551 The function expand_compound_operation is called with an rtx expression 5552 and will convert it to the appropriate shifts and AND operations, 5553 simplifying at each stage. 5554 5555 The function make_compound_operation is called to convert an expression 5556 consisting of shifts and ANDs into the equivalent compound expression. 5557 It is the inverse of this function, loosely speaking. */ 5558 5559static rtx 5560expand_compound_operation (x) 5561 rtx x; 5562{ 5563 unsigned HOST_WIDE_INT pos = 0, len; 5564 int unsignedp = 0; 5565 unsigned int modewidth; 5566 rtx tem; 5567 5568 switch (GET_CODE (x)) 5569 { 5570 case ZERO_EXTEND: 5571 unsignedp = 1; 5572 case SIGN_EXTEND: 5573 /* We can't necessarily use a const_int for a multiword mode; 5574 it depends on implicitly extending the value. 5575 Since we don't know the right way to extend it, 5576 we can't tell whether the implicit way is right. 5577 5578 Even for a mode that is no wider than a const_int, 5579 we can't win, because we need to sign extend one of its bits through 5580 the rest of it, and we don't know which bit. */ 5581 if (GET_CODE (XEXP (x, 0)) == CONST_INT) 5582 return x; 5583 5584 /* Return if (subreg:MODE FROM 0) is not a safe replacement for 5585 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM 5586 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be 5587 reloaded. If not for that, MEM's would very rarely be safe. 5588 5589 Reject MODEs bigger than a word, because we might not be able 5590 to reference a two-register group starting with an arbitrary register 5591 (and currently gen_lowpart might crash for a SUBREG). */ 5592 5593 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) 5594 return x; 5595 5596 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))); 5597 /* If the inner object has VOIDmode (the only way this can happen 5598 is if it is a ASM_OPERANDS), we can't do anything since we don't 5599 know how much masking to do. */ 5600 if (len == 0) 5601 return x; 5602 5603 break; 5604 5605 case ZERO_EXTRACT: 5606 unsignedp = 1; 5607 case SIGN_EXTRACT: 5608 /* If the operand is a CLOBBER, just return it. */ 5609 if (GET_CODE (XEXP (x, 0)) == CLOBBER) 5610 return XEXP (x, 0); 5611 5612 if (GET_CODE (XEXP (x, 1)) != CONST_INT 5613 || GET_CODE (XEXP (x, 2)) != CONST_INT 5614 || GET_MODE (XEXP (x, 0)) == VOIDmode) 5615 return x; 5616 5617 len = INTVAL (XEXP (x, 1)); 5618 pos = INTVAL (XEXP (x, 2)); 5619 5620 /* If this goes outside the object being extracted, replace the object 5621 with a (use (mem ...)) construct that only combine understands 5622 and is used only for this purpose. */ 5623 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) 5624 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0))); 5625 5626 if (BITS_BIG_ENDIAN) 5627 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos; 5628 5629 break; 5630 5631 default: 5632 return x; 5633 } 5634 /* Convert sign extension to zero extension, if we know that the high 5635 bit is not set, as this is easier to optimize. It will be converted 5636 back to cheaper alternative in make_extraction. */ 5637 if (GET_CODE (x) == SIGN_EXTEND 5638 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5639 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 5640 & ~(((unsigned HOST_WIDE_INT) 5641 GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) 5642 >> 1)) 5643 == 0))) 5644 { 5645 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0)); 5646 return expand_compound_operation (temp); 5647 } 5648 5649 /* We can optimize some special cases of ZERO_EXTEND. */ 5650 if (GET_CODE (x) == ZERO_EXTEND) 5651 { 5652 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we 5653 know that the last value didn't have any inappropriate bits 5654 set. */ 5655 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 5656 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 5657 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5658 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x)) 5659 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5660 return XEXP (XEXP (x, 0), 0); 5661 5662 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 5663 if (GET_CODE (XEXP (x, 0)) == SUBREG 5664 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 5665 && subreg_lowpart_p (XEXP (x, 0)) 5666 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5667 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x)) 5668 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5669 return SUBREG_REG (XEXP (x, 0)); 5670 5671 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo 5672 is a comparison and STORE_FLAG_VALUE permits. This is like 5673 the first case, but it works even when GET_MODE (x) is larger 5674 than HOST_WIDE_INT. */ 5675 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 5676 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 5677 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<' 5678 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 5679 <= HOST_BITS_PER_WIDE_INT) 5680 && ((HOST_WIDE_INT) STORE_FLAG_VALUE 5681 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5682 return XEXP (XEXP (x, 0), 0); 5683 5684 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 5685 if (GET_CODE (XEXP (x, 0)) == SUBREG 5686 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 5687 && subreg_lowpart_p (XEXP (x, 0)) 5688 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<' 5689 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 5690 <= HOST_BITS_PER_WIDE_INT) 5691 && ((HOST_WIDE_INT) STORE_FLAG_VALUE 5692 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5693 return SUBREG_REG (XEXP (x, 0)); 5694 5695 } 5696 5697 /* If we reach here, we want to return a pair of shifts. The inner 5698 shift is a left shift of BITSIZE - POS - LEN bits. The outer 5699 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or 5700 logical depending on the value of UNSIGNEDP. 5701 5702 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be 5703 converted into an AND of a shift. 5704 5705 We must check for the case where the left shift would have a negative 5706 count. This can happen in a case like (x >> 31) & 255 on machines 5707 that can't shift by a constant. On those machines, we would first 5708 combine the shift with the AND to produce a variable-position 5709 extraction. Then the constant of 31 would be substituted in to produce 5710 a such a position. */ 5711 5712 modewidth = GET_MODE_BITSIZE (GET_MODE (x)); 5713 if (modewidth + len >= pos) 5714 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, 5715 GET_MODE (x), 5716 simplify_shift_const (NULL_RTX, ASHIFT, 5717 GET_MODE (x), 5718 XEXP (x, 0), 5719 modewidth - pos - len), 5720 modewidth - len); 5721 5722 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) 5723 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), 5724 simplify_shift_const (NULL_RTX, LSHIFTRT, 5725 GET_MODE (x), 5726 XEXP (x, 0), pos), 5727 ((HOST_WIDE_INT) 1 << len) - 1); 5728 else 5729 /* Any other cases we can't handle. */ 5730 return x; 5731 5732 /* If we couldn't do this for some reason, return the original 5733 expression. */ 5734 if (GET_CODE (tem) == CLOBBER) 5735 return x; 5736 5737 return tem; 5738} 5739 5740/* X is a SET which contains an assignment of one object into 5741 a part of another (such as a bit-field assignment, STRICT_LOW_PART, 5742 or certain SUBREGS). If possible, convert it into a series of 5743 logical operations. 5744 5745 We half-heartedly support variable positions, but do not at all 5746 support variable lengths. */ 5747 5748static rtx 5749expand_field_assignment (x) 5750 rtx x; 5751{ 5752 rtx inner; 5753 rtx pos; /* Always counts from low bit. */ 5754 int len; 5755 rtx mask; 5756 enum machine_mode compute_mode; 5757 5758 /* Loop until we find something we can't simplify. */ 5759 while (1) 5760 { 5761 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART 5762 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) 5763 { 5764 inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); 5765 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))); 5766 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0))); 5767 } 5768 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 5769 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT) 5770 { 5771 inner = XEXP (SET_DEST (x), 0); 5772 len = INTVAL (XEXP (SET_DEST (x), 1)); 5773 pos = XEXP (SET_DEST (x), 2); 5774 5775 /* If the position is constant and spans the width of INNER, 5776 surround INNER with a USE to indicate this. */ 5777 if (GET_CODE (pos) == CONST_INT 5778 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner))) 5779 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner); 5780 5781 if (BITS_BIG_ENDIAN) 5782 { 5783 if (GET_CODE (pos) == CONST_INT) 5784 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len 5785 - INTVAL (pos)); 5786 else if (GET_CODE (pos) == MINUS 5787 && GET_CODE (XEXP (pos, 1)) == CONST_INT 5788 && (INTVAL (XEXP (pos, 1)) 5789 == GET_MODE_BITSIZE (GET_MODE (inner)) - len)) 5790 /* If position is ADJUST - X, new position is X. */ 5791 pos = XEXP (pos, 0); 5792 else 5793 pos = gen_binary (MINUS, GET_MODE (pos), 5794 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) 5795 - len), 5796 pos); 5797 } 5798 } 5799 5800 /* A SUBREG between two modes that occupy the same numbers of words 5801 can be done by moving the SUBREG to the source. */ 5802 else if (GET_CODE (SET_DEST (x)) == SUBREG 5803 /* We need SUBREGs to compute nonzero_bits properly. */ 5804 && nonzero_sign_valid 5805 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) 5806 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 5807 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) 5808 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) 5809 { 5810 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)), 5811 gen_lowpart_for_combine 5812 (GET_MODE (SUBREG_REG (SET_DEST (x))), 5813 SET_SRC (x))); 5814 continue; 5815 } 5816 else 5817 break; 5818 5819 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 5820 inner = SUBREG_REG (inner); 5821 5822 compute_mode = GET_MODE (inner); 5823 5824 /* Don't attempt bitwise arithmetic on non-integral modes. */ 5825 if (! INTEGRAL_MODE_P (compute_mode)) 5826 { 5827 enum machine_mode imode; 5828 5829 /* Something is probably seriously wrong if this matches. */ 5830 if (! FLOAT_MODE_P (compute_mode)) 5831 break; 5832 5833 /* Try to find an integral mode to pun with. */ 5834 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0); 5835 if (imode == BLKmode) 5836 break; 5837 5838 compute_mode = imode; 5839 inner = gen_lowpart_for_combine (imode, inner); 5840 } 5841 5842 /* Compute a mask of LEN bits, if we can do this on the host machine. */ 5843 if (len < HOST_BITS_PER_WIDE_INT) 5844 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1); 5845 else 5846 break; 5847 5848 /* Now compute the equivalent expression. Make a copy of INNER 5849 for the SET_DEST in case it is a MEM into which we will substitute; 5850 we don't want shared RTL in that case. */ 5851 x = gen_rtx_SET 5852 (VOIDmode, copy_rtx (inner), 5853 gen_binary (IOR, compute_mode, 5854 gen_binary (AND, compute_mode, 5855 simplify_gen_unary (NOT, compute_mode, 5856 gen_binary (ASHIFT, 5857 compute_mode, 5858 mask, pos), 5859 compute_mode), 5860 inner), 5861 gen_binary (ASHIFT, compute_mode, 5862 gen_binary (AND, compute_mode, 5863 gen_lowpart_for_combine 5864 (compute_mode, SET_SRC (x)), 5865 mask), 5866 pos))); 5867 } 5868 5869 return x; 5870} 5871 5872/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, 5873 it is an RTX that represents a variable starting position; otherwise, 5874 POS is the (constant) starting bit position (counted from the LSB). 5875 5876 INNER may be a USE. This will occur when we started with a bitfield 5877 that went outside the boundary of the object in memory, which is 5878 allowed on most machines. To isolate this case, we produce a USE 5879 whose mode is wide enough and surround the MEM with it. The only 5880 code that understands the USE is this routine. If it is not removed, 5881 it will cause the resulting insn not to match. 5882 5883 UNSIGNEDP is non-zero for an unsigned reference and zero for a 5884 signed reference. 5885 5886 IN_DEST is non-zero if this is a reference in the destination of a 5887 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero, 5888 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will 5889 be used. 5890 5891 IN_COMPARE is non-zero if we are in a COMPARE. This means that a 5892 ZERO_EXTRACT should be built even for bits starting at bit 0. 5893 5894 MODE is the desired mode of the result (if IN_DEST == 0). 5895 5896 The result is an RTX for the extraction or NULL_RTX if the target 5897 can't handle it. */ 5898 5899static rtx 5900make_extraction (mode, inner, pos, pos_rtx, len, 5901 unsignedp, in_dest, in_compare) 5902 enum machine_mode mode; 5903 rtx inner; 5904 HOST_WIDE_INT pos; 5905 rtx pos_rtx; 5906 unsigned HOST_WIDE_INT len; 5907 int unsignedp; 5908 int in_dest, in_compare; 5909{ 5910 /* This mode describes the size of the storage area 5911 to fetch the overall value from. Within that, we 5912 ignore the POS lowest bits, etc. */ 5913 enum machine_mode is_mode = GET_MODE (inner); 5914 enum machine_mode inner_mode; 5915 enum machine_mode wanted_inner_mode = byte_mode; 5916 enum machine_mode wanted_inner_reg_mode = word_mode; 5917 enum machine_mode pos_mode = word_mode; 5918 enum machine_mode extraction_mode = word_mode; 5919 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); 5920 int spans_byte = 0; 5921 rtx new = 0; 5922 rtx orig_pos_rtx = pos_rtx; 5923 HOST_WIDE_INT orig_pos; 5924 5925 /* Get some information about INNER and get the innermost object. */ 5926 if (GET_CODE (inner) == USE) 5927 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */ 5928 /* We don't need to adjust the position because we set up the USE 5929 to pretend that it was a full-word object. */ 5930 spans_byte = 1, inner = XEXP (inner, 0); 5931 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 5932 { 5933 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), 5934 consider just the QI as the memory to extract from. 5935 The subreg adds or removes high bits; its mode is 5936 irrelevant to the meaning of this extraction, 5937 since POS and LEN count from the lsb. */ 5938 if (GET_CODE (SUBREG_REG (inner)) == MEM) 5939 is_mode = GET_MODE (SUBREG_REG (inner)); 5940 inner = SUBREG_REG (inner); 5941 } 5942 5943 inner_mode = GET_MODE (inner); 5944 5945 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT) 5946 pos = INTVAL (pos_rtx), pos_rtx = 0; 5947 5948 /* See if this can be done without an extraction. We never can if the 5949 width of the field is not the same as that of some integer mode. For 5950 registers, we can only avoid the extraction if the position is at the 5951 low-order bit and this is either not in the destination or we have the 5952 appropriate STRICT_LOW_PART operation available. 5953 5954 For MEM, we can avoid an extract if the field starts on an appropriate 5955 boundary and we can change the mode of the memory reference. However, 5956 we cannot directly access the MEM if we have a USE and the underlying 5957 MEM is not TMODE. This combination means that MEM was being used in a 5958 context where bits outside its mode were being referenced; that is only 5959 valid in bit-field insns. */ 5960 5961 if (tmode != BLKmode 5962 && ! (spans_byte && inner_mode != tmode) 5963 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 5964 && GET_CODE (inner) != MEM 5965 && (! in_dest 5966 || (GET_CODE (inner) == REG 5967 && have_insn_for (STRICT_LOW_PART, tmode)))) 5968 || (GET_CODE (inner) == MEM && pos_rtx == 0 5969 && (pos 5970 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) 5971 : BITS_PER_UNIT)) == 0 5972 /* We can't do this if we are widening INNER_MODE (it 5973 may not be aligned, for one thing). */ 5974 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode) 5975 && (inner_mode == tmode 5976 || (! mode_dependent_address_p (XEXP (inner, 0)) 5977 && ! MEM_VOLATILE_P (inner)))))) 5978 { 5979 /* If INNER is a MEM, make a new MEM that encompasses just the desired 5980 field. If the original and current mode are the same, we need not 5981 adjust the offset. Otherwise, we do if bytes big endian. 5982 5983 If INNER is not a MEM, get a piece consisting of just the field 5984 of interest (in this case POS % BITS_PER_WORD must be 0). */ 5985 5986 if (GET_CODE (inner) == MEM) 5987 { 5988 HOST_WIDE_INT offset; 5989 5990 /* POS counts from lsb, but make OFFSET count in memory order. */ 5991 if (BYTES_BIG_ENDIAN) 5992 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT; 5993 else 5994 offset = pos / BITS_PER_UNIT; 5995 5996 new = adjust_address_nv (inner, tmode, offset); 5997 } 5998 else if (GET_CODE (inner) == REG) 5999 { 6000 /* We can't call gen_lowpart_for_combine here since we always want 6001 a SUBREG and it would sometimes return a new hard register. */ 6002 if (tmode != inner_mode) 6003 { 6004 HOST_WIDE_INT final_word = pos / BITS_PER_WORD; 6005 6006 if (WORDS_BIG_ENDIAN 6007 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD) 6008 final_word = ((GET_MODE_SIZE (inner_mode) 6009 - GET_MODE_SIZE (tmode)) 6010 / UNITS_PER_WORD) - final_word; 6011 6012 final_word *= UNITS_PER_WORD; 6013 if (BYTES_BIG_ENDIAN && 6014 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode)) 6015 final_word += (GET_MODE_SIZE (inner_mode) 6016 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD; 6017 6018 new = gen_rtx_SUBREG (tmode, inner, final_word); 6019 } 6020 else 6021 new = inner; 6022 } 6023 else 6024 new = force_to_mode (inner, tmode, 6025 len >= HOST_BITS_PER_WIDE_INT 6026 ? ~(unsigned HOST_WIDE_INT) 0 6027 : ((unsigned HOST_WIDE_INT) 1 << len) - 1, 6028 NULL_RTX, 0); 6029 6030 /* If this extraction is going into the destination of a SET, 6031 make a STRICT_LOW_PART unless we made a MEM. */ 6032 6033 if (in_dest) 6034 return (GET_CODE (new) == MEM ? new 6035 : (GET_CODE (new) != SUBREG 6036 ? gen_rtx_CLOBBER (tmode, const0_rtx) 6037 : gen_rtx_STRICT_LOW_PART (VOIDmode, new))); 6038 6039 if (mode == tmode) 6040 return new; 6041 6042 if (GET_CODE (new) == CONST_INT) 6043 return GEN_INT (trunc_int_for_mode (INTVAL (new), mode)); 6044 6045 /* If we know that no extraneous bits are set, and that the high 6046 bit is not set, convert the extraction to the cheaper of 6047 sign and zero extension, that are equivalent in these cases. */ 6048 if (flag_expensive_optimizations 6049 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT 6050 && ((nonzero_bits (new, tmode) 6051 & ~(((unsigned HOST_WIDE_INT) 6052 GET_MODE_MASK (tmode)) 6053 >> 1)) 6054 == 0))) 6055 { 6056 rtx temp = gen_rtx_ZERO_EXTEND (mode, new); 6057 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new); 6058 6059 /* Prefer ZERO_EXTENSION, since it gives more information to 6060 backends. */ 6061 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET)) 6062 return temp; 6063 return temp1; 6064 } 6065 6066 /* Otherwise, sign- or zero-extend unless we already are in the 6067 proper mode. */ 6068 6069 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 6070 mode, new)); 6071 } 6072 6073 /* Unless this is a COMPARE or we have a funny memory reference, 6074 don't do anything with zero-extending field extracts starting at 6075 the low-order bit since they are simple AND operations. */ 6076 if (pos_rtx == 0 && pos == 0 && ! in_dest 6077 && ! in_compare && ! spans_byte && unsignedp) 6078 return 0; 6079 6080 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if 6081 we would be spanning bytes or if the position is not a constant and the 6082 length is not 1. In all other cases, we would only be going outside 6083 our object in cases when an original shift would have been 6084 undefined. */ 6085 if (! spans_byte && GET_CODE (inner) == MEM 6086 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode)) 6087 || (pos_rtx != 0 && len != 1))) 6088 return 0; 6089 6090 /* Get the mode to use should INNER not be a MEM, the mode for the position, 6091 and the mode for the result. */ 6092 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE) 6093 { 6094 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0); 6095 pos_mode = mode_for_extraction (EP_insv, 2); 6096 extraction_mode = mode_for_extraction (EP_insv, 3); 6097 } 6098 6099 if (! in_dest && unsignedp 6100 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE) 6101 { 6102 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1); 6103 pos_mode = mode_for_extraction (EP_extzv, 3); 6104 extraction_mode = mode_for_extraction (EP_extzv, 0); 6105 } 6106 6107 if (! in_dest && ! unsignedp 6108 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE) 6109 { 6110 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1); 6111 pos_mode = mode_for_extraction (EP_extv, 3); 6112 extraction_mode = mode_for_extraction (EP_extv, 0); 6113 } 6114 6115 /* Never narrow an object, since that might not be safe. */ 6116 6117 if (mode != VOIDmode 6118 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) 6119 extraction_mode = mode; 6120 6121 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode 6122 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) 6123 pos_mode = GET_MODE (pos_rtx); 6124 6125 /* If this is not from memory, the desired mode is wanted_inner_reg_mode; 6126 if we have to change the mode of memory and cannot, the desired mode is 6127 EXTRACTION_MODE. */ 6128 if (GET_CODE (inner) != MEM) 6129 wanted_inner_mode = wanted_inner_reg_mode; 6130 else if (inner_mode != wanted_inner_mode 6131 && (mode_dependent_address_p (XEXP (inner, 0)) 6132 || MEM_VOLATILE_P (inner))) 6133 wanted_inner_mode = extraction_mode; 6134 6135 orig_pos = pos; 6136 6137 if (BITS_BIG_ENDIAN) 6138 { 6139 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to 6140 BITS_BIG_ENDIAN style. If position is constant, compute new 6141 position. Otherwise, build subtraction. 6142 Note that POS is relative to the mode of the original argument. 6143 If it's a MEM we need to recompute POS relative to that. 6144 However, if we're extracting from (or inserting into) a register, 6145 we want to recompute POS relative to wanted_inner_mode. */ 6146 int width = (GET_CODE (inner) == MEM 6147 ? GET_MODE_BITSIZE (is_mode) 6148 : GET_MODE_BITSIZE (wanted_inner_mode)); 6149 6150 if (pos_rtx == 0) 6151 pos = width - len - pos; 6152 else 6153 pos_rtx 6154 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx); 6155 /* POS may be less than 0 now, but we check for that below. 6156 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */ 6157 } 6158 6159 /* If INNER has a wider mode, make it smaller. If this is a constant 6160 extract, try to adjust the byte to point to the byte containing 6161 the value. */ 6162 if (wanted_inner_mode != VOIDmode 6163 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode) 6164 && ((GET_CODE (inner) == MEM 6165 && (inner_mode == wanted_inner_mode 6166 || (! mode_dependent_address_p (XEXP (inner, 0)) 6167 && ! MEM_VOLATILE_P (inner)))))) 6168 { 6169 int offset = 0; 6170 6171 /* The computations below will be correct if the machine is big 6172 endian in both bits and bytes or little endian in bits and bytes. 6173 If it is mixed, we must adjust. */ 6174 6175 /* If bytes are big endian and we had a paradoxical SUBREG, we must 6176 adjust OFFSET to compensate. */ 6177 if (BYTES_BIG_ENDIAN 6178 && ! spans_byte 6179 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) 6180 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); 6181 6182 /* If this is a constant position, we can move to the desired byte. */ 6183 if (pos_rtx == 0) 6184 { 6185 offset += pos / BITS_PER_UNIT; 6186 pos %= GET_MODE_BITSIZE (wanted_inner_mode); 6187 } 6188 6189 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN 6190 && ! spans_byte 6191 && is_mode != wanted_inner_mode) 6192 offset = (GET_MODE_SIZE (is_mode) 6193 - GET_MODE_SIZE (wanted_inner_mode) - offset); 6194 6195 if (offset != 0 || inner_mode != wanted_inner_mode) 6196 inner = adjust_address_nv (inner, wanted_inner_mode, offset); 6197 } 6198 6199 /* If INNER is not memory, we can always get it into the proper mode. If we 6200 are changing its mode, POS must be a constant and smaller than the size 6201 of the new mode. */ 6202 else if (GET_CODE (inner) != MEM) 6203 { 6204 if (GET_MODE (inner) != wanted_inner_mode 6205 && (pos_rtx != 0 6206 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) 6207 return 0; 6208 6209 inner = force_to_mode (inner, wanted_inner_mode, 6210 pos_rtx 6211 || len + orig_pos >= HOST_BITS_PER_WIDE_INT 6212 ? ~(unsigned HOST_WIDE_INT) 0 6213 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1) 6214 << orig_pos), 6215 NULL_RTX, 0); 6216 } 6217 6218 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we 6219 have to zero extend. Otherwise, we can just use a SUBREG. */ 6220 if (pos_rtx != 0 6221 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) 6222 { 6223 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx); 6224 6225 /* If we know that no extraneous bits are set, and that the high 6226 bit is not set, convert extraction to cheaper one - either 6227 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these 6228 cases. */ 6229 if (flag_expensive_optimizations 6230 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT 6231 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx)) 6232 & ~(((unsigned HOST_WIDE_INT) 6233 GET_MODE_MASK (GET_MODE (pos_rtx))) 6234 >> 1)) 6235 == 0))) 6236 { 6237 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx); 6238 6239 /* Prefer ZERO_EXTENSION, since it gives more information to 6240 backends. */ 6241 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET)) 6242 temp = temp1; 6243 } 6244 pos_rtx = temp; 6245 } 6246 else if (pos_rtx != 0 6247 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) 6248 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx); 6249 6250 /* Make POS_RTX unless we already have it and it is correct. If we don't 6251 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must 6252 be a CONST_INT. */ 6253 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) 6254 pos_rtx = orig_pos_rtx; 6255 6256 else if (pos_rtx == 0) 6257 pos_rtx = GEN_INT (pos); 6258 6259 /* Make the required operation. See if we can use existing rtx. */ 6260 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, 6261 extraction_mode, inner, GEN_INT (len), pos_rtx); 6262 if (! in_dest) 6263 new = gen_lowpart_for_combine (mode, new); 6264 6265 return new; 6266} 6267 6268/* See if X contains an ASHIFT of COUNT or more bits that can be commuted 6269 with any other operations in X. Return X without that shift if so. */ 6270 6271static rtx 6272extract_left_shift (x, count) 6273 rtx x; 6274 int count; 6275{ 6276 enum rtx_code code = GET_CODE (x); 6277 enum machine_mode mode = GET_MODE (x); 6278 rtx tem; 6279 6280 switch (code) 6281 { 6282 case ASHIFT: 6283 /* This is the shift itself. If it is wide enough, we will return 6284 either the value being shifted if the shift count is equal to 6285 COUNT or a shift for the difference. */ 6286 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6287 && INTVAL (XEXP (x, 1)) >= count) 6288 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), 6289 INTVAL (XEXP (x, 1)) - count); 6290 break; 6291 6292 case NEG: case NOT: 6293 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) 6294 return simplify_gen_unary (code, mode, tem, mode); 6295 6296 break; 6297 6298 case PLUS: case IOR: case XOR: case AND: 6299 /* If we can safely shift this constant and we find the inner shift, 6300 make a new operation. */ 6301 if (GET_CODE (XEXP (x,1)) == CONST_INT 6302 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0 6303 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) 6304 return gen_binary (code, mode, tem, 6305 GEN_INT (INTVAL (XEXP (x, 1)) >> count)); 6306 6307 break; 6308 6309 default: 6310 break; 6311 } 6312 6313 return 0; 6314} 6315 6316/* Look at the expression rooted at X. Look for expressions 6317 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. 6318 Form these expressions. 6319 6320 Return the new rtx, usually just X. 6321 6322 Also, for machines like the VAX that don't have logical shift insns, 6323 try to convert logical to arithmetic shift operations in cases where 6324 they are equivalent. This undoes the canonicalizations to logical 6325 shifts done elsewhere. 6326 6327 We try, as much as possible, to re-use rtl expressions to save memory. 6328 6329 IN_CODE says what kind of expression we are processing. Normally, it is 6330 SET. In a memory address (inside a MEM, PLUS or minus, the latter two 6331 being kludges), it is MEM. When processing the arguments of a comparison 6332 or a COMPARE against zero, it is COMPARE. */ 6333 6334static rtx 6335make_compound_operation (x, in_code) 6336 rtx x; 6337 enum rtx_code in_code; 6338{ 6339 enum rtx_code code = GET_CODE (x); 6340 enum machine_mode mode = GET_MODE (x); 6341 int mode_width = GET_MODE_BITSIZE (mode); 6342 rtx rhs, lhs; 6343 enum rtx_code next_code; 6344 int i; 6345 rtx new = 0; 6346 rtx tem; 6347 const char *fmt; 6348 6349 /* Select the code to be used in recursive calls. Once we are inside an 6350 address, we stay there. If we have a comparison, set to COMPARE, 6351 but once inside, go back to our default of SET. */ 6352 6353 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM 6354 : ((code == COMPARE || GET_RTX_CLASS (code) == '<') 6355 && XEXP (x, 1) == const0_rtx) ? COMPARE 6356 : in_code == COMPARE ? SET : in_code); 6357 6358 /* Process depending on the code of this operation. If NEW is set 6359 non-zero, it will be returned. */ 6360 6361 switch (code) 6362 { 6363 case ASHIFT: 6364 /* Convert shifts by constants into multiplications if inside 6365 an address. */ 6366 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT 6367 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 6368 && INTVAL (XEXP (x, 1)) >= 0) 6369 { 6370 new = make_compound_operation (XEXP (x, 0), next_code); 6371 new = gen_rtx_MULT (mode, new, 6372 GEN_INT ((HOST_WIDE_INT) 1 6373 << INTVAL (XEXP (x, 1)))); 6374 } 6375 break; 6376 6377 case AND: 6378 /* If the second operand is not a constant, we can't do anything 6379 with it. */ 6380 if (GET_CODE (XEXP (x, 1)) != CONST_INT) 6381 break; 6382 6383 /* If the constant is a power of two minus one and the first operand 6384 is a logical right shift, make an extraction. */ 6385 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6386 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6387 { 6388 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 6389 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1, 6390 0, in_code == COMPARE); 6391 } 6392 6393 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ 6394 else if (GET_CODE (XEXP (x, 0)) == SUBREG 6395 && subreg_lowpart_p (XEXP (x, 0)) 6396 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT 6397 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6398 { 6399 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), 6400 next_code); 6401 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0, 6402 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, 6403 0, in_code == COMPARE); 6404 } 6405 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ 6406 else if ((GET_CODE (XEXP (x, 0)) == XOR 6407 || GET_CODE (XEXP (x, 0)) == IOR) 6408 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT 6409 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT 6410 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6411 { 6412 /* Apply the distributive law, and then try to make extractions. */ 6413 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode, 6414 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), 6415 XEXP (x, 1)), 6416 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), 6417 XEXP (x, 1))); 6418 new = make_compound_operation (new, in_code); 6419 } 6420 6421 /* If we are have (and (rotate X C) M) and C is larger than the number 6422 of bits in M, this is an extraction. */ 6423 6424 else if (GET_CODE (XEXP (x, 0)) == ROTATE 6425 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6426 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 6427 && i <= INTVAL (XEXP (XEXP (x, 0), 1))) 6428 { 6429 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 6430 new = make_extraction (mode, new, 6431 (GET_MODE_BITSIZE (mode) 6432 - INTVAL (XEXP (XEXP (x, 0), 1))), 6433 NULL_RTX, i, 1, 0, in_code == COMPARE); 6434 } 6435 6436 /* On machines without logical shifts, if the operand of the AND is 6437 a logical shift and our mask turns off all the propagated sign 6438 bits, we can replace the logical shift with an arithmetic shift. */ 6439 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6440 && !have_insn_for (LSHIFTRT, mode) 6441 && have_insn_for (ASHIFTRT, mode) 6442 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6443 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 6444 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 6445 && mode_width <= HOST_BITS_PER_WIDE_INT) 6446 { 6447 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 6448 6449 mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); 6450 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) 6451 SUBST (XEXP (x, 0), 6452 gen_rtx_ASHIFTRT (mode, 6453 make_compound_operation 6454 (XEXP (XEXP (x, 0), 0), next_code), 6455 XEXP (XEXP (x, 0), 1))); 6456 } 6457 6458 /* If the constant is one less than a power of two, this might be 6459 representable by an extraction even if no shift is present. 6460 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless 6461 we are in a COMPARE. */ 6462 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6463 new = make_extraction (mode, 6464 make_compound_operation (XEXP (x, 0), 6465 next_code), 6466 0, NULL_RTX, i, 1, 0, in_code == COMPARE); 6467 6468 /* If we are in a comparison and this is an AND with a power of two, 6469 convert this into the appropriate bit extract. */ 6470 else if (in_code == COMPARE 6471 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) 6472 new = make_extraction (mode, 6473 make_compound_operation (XEXP (x, 0), 6474 next_code), 6475 i, NULL_RTX, 1, 1, 0, 1); 6476 6477 break; 6478 6479 case LSHIFTRT: 6480 /* If the sign bit is known to be zero, replace this with an 6481 arithmetic shift. */ 6482 if (have_insn_for (ASHIFTRT, mode) 6483 && ! have_insn_for (LSHIFTRT, mode) 6484 && mode_width <= HOST_BITS_PER_WIDE_INT 6485 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) 6486 { 6487 new = gen_rtx_ASHIFTRT (mode, 6488 make_compound_operation (XEXP (x, 0), 6489 next_code), 6490 XEXP (x, 1)); 6491 break; 6492 } 6493 6494 /* ... fall through ... */ 6495 6496 case ASHIFTRT: 6497 lhs = XEXP (x, 0); 6498 rhs = XEXP (x, 1); 6499 6500 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, 6501 this is a SIGN_EXTRACT. */ 6502 if (GET_CODE (rhs) == CONST_INT 6503 && GET_CODE (lhs) == ASHIFT 6504 && GET_CODE (XEXP (lhs, 1)) == CONST_INT 6505 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))) 6506 { 6507 new = make_compound_operation (XEXP (lhs, 0), next_code); 6508 new = make_extraction (mode, new, 6509 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), 6510 NULL_RTX, mode_width - INTVAL (rhs), 6511 code == LSHIFTRT, 0, in_code == COMPARE); 6512 break; 6513 } 6514 6515 /* See if we have operations between an ASHIFTRT and an ASHIFT. 6516 If so, try to merge the shifts into a SIGN_EXTEND. We could 6517 also do this for some cases of SIGN_EXTRACT, but it doesn't 6518 seem worth the effort; the case checked for occurs on Alpha. */ 6519 6520 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o' 6521 && ! (GET_CODE (lhs) == SUBREG 6522 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o')) 6523 && GET_CODE (rhs) == CONST_INT 6524 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT 6525 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0) 6526 new = make_extraction (mode, make_compound_operation (new, next_code), 6527 0, NULL_RTX, mode_width - INTVAL (rhs), 6528 code == LSHIFTRT, 0, in_code == COMPARE); 6529 6530 break; 6531 6532 case SUBREG: 6533 /* Call ourselves recursively on the inner expression. If we are 6534 narrowing the object and it has a different RTL code from 6535 what it originally did, do this SUBREG as a force_to_mode. */ 6536 6537 tem = make_compound_operation (SUBREG_REG (x), in_code); 6538 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x)) 6539 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem)) 6540 && subreg_lowpart_p (x)) 6541 { 6542 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0, 6543 NULL_RTX, 0); 6544 6545 /* If we have something other than a SUBREG, we might have 6546 done an expansion, so rerun ourselves. */ 6547 if (GET_CODE (newer) != SUBREG) 6548 newer = make_compound_operation (newer, in_code); 6549 6550 return newer; 6551 } 6552 6553 /* If this is a paradoxical subreg, and the new code is a sign or 6554 zero extension, omit the subreg and widen the extension. If it 6555 is a regular subreg, we can still get rid of the subreg by not 6556 widening so much, or in fact removing the extension entirely. */ 6557 if ((GET_CODE (tem) == SIGN_EXTEND 6558 || GET_CODE (tem) == ZERO_EXTEND) 6559 && subreg_lowpart_p (x)) 6560 { 6561 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem)) 6562 || (GET_MODE_SIZE (mode) > 6563 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0))))) 6564 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0)); 6565 else 6566 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0)); 6567 return tem; 6568 } 6569 break; 6570 6571 default: 6572 break; 6573 } 6574 6575 if (new) 6576 { 6577 x = gen_lowpart_for_combine (mode, new); 6578 code = GET_CODE (x); 6579 } 6580 6581 /* Now recursively process each operand of this operation. */ 6582 fmt = GET_RTX_FORMAT (code); 6583 for (i = 0; i < GET_RTX_LENGTH (code); i++) 6584 if (fmt[i] == 'e') 6585 { 6586 new = make_compound_operation (XEXP (x, i), next_code); 6587 SUBST (XEXP (x, i), new); 6588 } 6589 6590 return x; 6591} 6592 6593/* Given M see if it is a value that would select a field of bits 6594 within an item, but not the entire word. Return -1 if not. 6595 Otherwise, return the starting position of the field, where 0 is the 6596 low-order bit. 6597 6598 *PLEN is set to the length of the field. */ 6599 6600static int 6601get_pos_from_mask (m, plen) 6602 unsigned HOST_WIDE_INT m; 6603 unsigned HOST_WIDE_INT *plen; 6604{ 6605 /* Get the bit number of the first 1 bit from the right, -1 if none. */ 6606 int pos = exact_log2 (m & -m); 6607 int len; 6608 6609 if (pos < 0) 6610 return -1; 6611 6612 /* Now shift off the low-order zero bits and see if we have a power of 6613 two minus 1. */ 6614 len = exact_log2 ((m >> pos) + 1); 6615 6616 if (len <= 0) 6617 return -1; 6618 6619 *plen = len; 6620 return pos; 6621} 6622 6623/* See if X can be simplified knowing that we will only refer to it in 6624 MODE and will only refer to those bits that are nonzero in MASK. 6625 If other bits are being computed or if masking operations are done 6626 that select a superset of the bits in MASK, they can sometimes be 6627 ignored. 6628 6629 Return a possibly simplified expression, but always convert X to 6630 MODE. If X is a CONST_INT, AND the CONST_INT with MASK. 6631 6632 Also, if REG is non-zero and X is a register equal in value to REG, 6633 replace X with REG. 6634 6635 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK 6636 are all off in X. This is used when X will be complemented, by either 6637 NOT, NEG, or XOR. */ 6638 6639static rtx 6640force_to_mode (x, mode, mask, reg, just_select) 6641 rtx x; 6642 enum machine_mode mode; 6643 unsigned HOST_WIDE_INT mask; 6644 rtx reg; 6645 int just_select; 6646{ 6647 enum rtx_code code = GET_CODE (x); 6648 int next_select = just_select || code == XOR || code == NOT || code == NEG; 6649 enum machine_mode op_mode; 6650 unsigned HOST_WIDE_INT fuller_mask, nonzero; 6651 rtx op0, op1, temp; 6652 6653 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the 6654 code below will do the wrong thing since the mode of such an 6655 expression is VOIDmode. 6656 6657 Also do nothing if X is a CLOBBER; this can happen if X was 6658 the return value from a call to gen_lowpart_for_combine. */ 6659 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) 6660 return x; 6661 6662 /* We want to perform the operation is its present mode unless we know 6663 that the operation is valid in MODE, in which case we do the operation 6664 in MODE. */ 6665 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) 6666 && have_insn_for (code, mode)) 6667 ? mode : GET_MODE (x)); 6668 6669 /* It is not valid to do a right-shift in a narrower mode 6670 than the one it came in with. */ 6671 if ((code == LSHIFTRT || code == ASHIFTRT) 6672 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x))) 6673 op_mode = GET_MODE (x); 6674 6675 /* Truncate MASK to fit OP_MODE. */ 6676 if (op_mode) 6677 mask &= GET_MODE_MASK (op_mode); 6678 6679 /* When we have an arithmetic operation, or a shift whose count we 6680 do not know, we need to assume that all bit the up to the highest-order 6681 bit in MASK will be needed. This is how we form such a mask. */ 6682 if (op_mode) 6683 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT 6684 ? GET_MODE_MASK (op_mode) 6685 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) 6686 - 1)); 6687 else 6688 fuller_mask = ~(HOST_WIDE_INT) 0; 6689 6690 /* Determine what bits of X are guaranteed to be (non)zero. */ 6691 nonzero = nonzero_bits (x, mode); 6692 6693 /* If none of the bits in X are needed, return a zero. */ 6694 if (! just_select && (nonzero & mask) == 0) 6695 return const0_rtx; 6696 6697 /* If X is a CONST_INT, return a new one. Do this here since the 6698 test below will fail. */ 6699 if (GET_CODE (x) == CONST_INT) 6700 { 6701 HOST_WIDE_INT cval = INTVAL (x) & mask; 6702 int width = GET_MODE_BITSIZE (mode); 6703 6704 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative 6705 number, sign extend it. */ 6706 if (width > 0 && width < HOST_BITS_PER_WIDE_INT 6707 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6708 cval |= (HOST_WIDE_INT) -1 << width; 6709 6710 return GEN_INT (cval); 6711 } 6712 6713 /* If X is narrower than MODE and we want all the bits in X's mode, just 6714 get X in the proper mode. */ 6715 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) 6716 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0) 6717 return gen_lowpart_for_combine (mode, x); 6718 6719 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in 6720 MASK are already known to be zero in X, we need not do anything. */ 6721 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0) 6722 return x; 6723 6724 switch (code) 6725 { 6726 case CLOBBER: 6727 /* If X is a (clobber (const_int)), return it since we know we are 6728 generating something that won't match. */ 6729 return x; 6730 6731 case USE: 6732 /* X is a (use (mem ..)) that was made from a bit-field extraction that 6733 spanned the boundary of the MEM. If we are now masking so it is 6734 within that boundary, we don't need the USE any more. */ 6735 if (! BITS_BIG_ENDIAN 6736 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 6737 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 6738 break; 6739 6740 case SIGN_EXTEND: 6741 case ZERO_EXTEND: 6742 case ZERO_EXTRACT: 6743 case SIGN_EXTRACT: 6744 x = expand_compound_operation (x); 6745 if (GET_CODE (x) != code) 6746 return force_to_mode (x, mode, mask, reg, next_select); 6747 break; 6748 6749 case REG: 6750 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x) 6751 || rtx_equal_p (reg, get_last_value (x)))) 6752 x = reg; 6753 break; 6754 6755 case SUBREG: 6756 if (subreg_lowpart_p (x) 6757 /* We can ignore the effect of this SUBREG if it narrows the mode or 6758 if the constant masks to zero all the bits the mode doesn't 6759 have. */ 6760 && ((GET_MODE_SIZE (GET_MODE (x)) 6761 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 6762 || (0 == (mask 6763 & GET_MODE_MASK (GET_MODE (x)) 6764 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) 6765 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select); 6766 break; 6767 6768 case AND: 6769 /* If this is an AND with a constant, convert it into an AND 6770 whose constant is the AND of that constant with MASK. If it 6771 remains an AND of MASK, delete it since it is redundant. */ 6772 6773 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 6774 { 6775 x = simplify_and_const_int (x, op_mode, XEXP (x, 0), 6776 mask & INTVAL (XEXP (x, 1))); 6777 6778 /* If X is still an AND, see if it is an AND with a mask that 6779 is just some low-order bits. If so, and it is MASK, we don't 6780 need it. */ 6781 6782 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT 6783 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x))) 6784 == (HOST_WIDE_INT) mask)) 6785 x = XEXP (x, 0); 6786 6787 /* If it remains an AND, try making another AND with the bits 6788 in the mode mask that aren't in MASK turned on. If the 6789 constant in the AND is wide enough, this might make a 6790 cheaper constant. */ 6791 6792 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT 6793 && GET_MODE_MASK (GET_MODE (x)) != mask 6794 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) 6795 { 6796 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1)) 6797 | (GET_MODE_MASK (GET_MODE (x)) & ~mask)); 6798 int width = GET_MODE_BITSIZE (GET_MODE (x)); 6799 rtx y; 6800 6801 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative 6802 number, sign extend it. */ 6803 if (width > 0 && width < HOST_BITS_PER_WIDE_INT 6804 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6805 cval |= (HOST_WIDE_INT) -1 << width; 6806 6807 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval)); 6808 if (rtx_cost (y, SET) < rtx_cost (x, SET)) 6809 x = y; 6810 } 6811 6812 break; 6813 } 6814 6815 goto binop; 6816 6817 case PLUS: 6818 /* In (and (plus FOO C1) M), if M is a mask that just turns off 6819 low-order bits (as in an alignment operation) and FOO is already 6820 aligned to that boundary, mask C1 to that boundary as well. 6821 This may eliminate that PLUS and, later, the AND. */ 6822 6823 { 6824 unsigned int width = GET_MODE_BITSIZE (mode); 6825 unsigned HOST_WIDE_INT smask = mask; 6826 6827 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative 6828 number, sign extend it. */ 6829 6830 if (width < HOST_BITS_PER_WIDE_INT 6831 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6832 smask |= (HOST_WIDE_INT) -1 << width; 6833 6834 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6835 && exact_log2 (- smask) >= 0 6836 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0 6837 && (INTVAL (XEXP (x, 1)) & ~smask) != 0) 6838 return force_to_mode (plus_constant (XEXP (x, 0), 6839 (INTVAL (XEXP (x, 1)) & smask)), 6840 mode, smask, reg, next_select); 6841 } 6842 6843 /* ... fall through ... */ 6844 6845 case MULT: 6846 /* For PLUS, MINUS and MULT, we need any bits less significant than the 6847 most significant bit in MASK since carries from those bits will 6848 affect the bits we are interested in. */ 6849 mask = fuller_mask; 6850 goto binop; 6851 6852 case MINUS: 6853 /* If X is (minus C Y) where C's least set bit is larger than any bit 6854 in the mask, then we may replace with (neg Y). */ 6855 if (GET_CODE (XEXP (x, 0)) == CONST_INT 6856 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0)) 6857 & -INTVAL (XEXP (x, 0)))) 6858 > mask)) 6859 { 6860 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1), 6861 GET_MODE (x)); 6862 return force_to_mode (x, mode, mask, reg, next_select); 6863 } 6864 6865 /* Similarly, if C contains every bit in the mask, then we may 6866 replace with (not Y). */ 6867 if (GET_CODE (XEXP (x, 0)) == CONST_INT 6868 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask) 6869 == INTVAL (XEXP (x, 0)))) 6870 { 6871 x = simplify_gen_unary (NOT, GET_MODE (x), 6872 XEXP (x, 1), GET_MODE (x)); 6873 return force_to_mode (x, mode, mask, reg, next_select); 6874 } 6875 6876 mask = fuller_mask; 6877 goto binop; 6878 6879 case IOR: 6880 case XOR: 6881 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and 6882 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) 6883 operation which may be a bitfield extraction. Ensure that the 6884 constant we form is not wider than the mode of X. */ 6885 6886 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6887 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6888 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 6889 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 6890 && GET_CODE (XEXP (x, 1)) == CONST_INT 6891 && ((INTVAL (XEXP (XEXP (x, 0), 1)) 6892 + floor_log2 (INTVAL (XEXP (x, 1)))) 6893 < GET_MODE_BITSIZE (GET_MODE (x))) 6894 && (INTVAL (XEXP (x, 1)) 6895 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0) 6896 { 6897 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask) 6898 << INTVAL (XEXP (XEXP (x, 0), 1))); 6899 temp = gen_binary (GET_CODE (x), GET_MODE (x), 6900 XEXP (XEXP (x, 0), 0), temp); 6901 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, 6902 XEXP (XEXP (x, 0), 1)); 6903 return force_to_mode (x, mode, mask, reg, next_select); 6904 } 6905 6906 binop: 6907 /* For most binary operations, just propagate into the operation and 6908 change the mode if we have an operation of that mode. */ 6909 6910 op0 = gen_lowpart_for_combine (op_mode, 6911 force_to_mode (XEXP (x, 0), mode, mask, 6912 reg, next_select)); 6913 op1 = gen_lowpart_for_combine (op_mode, 6914 force_to_mode (XEXP (x, 1), mode, mask, 6915 reg, next_select)); 6916 6917 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside 6918 MASK since OP1 might have been sign-extended but we never want 6919 to turn on extra bits, since combine might have previously relied 6920 on them being off. */ 6921 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR) 6922 && (INTVAL (op1) & mask) != 0) 6923 op1 = GEN_INT (INTVAL (op1) & mask); 6924 6925 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 6926 x = gen_binary (code, op_mode, op0, op1); 6927 break; 6928 6929 case ASHIFT: 6930 /* For left shifts, do the same, but just for the first operand. 6931 However, we cannot do anything with shifts where we cannot 6932 guarantee that the counts are smaller than the size of the mode 6933 because such a count will have a different meaning in a 6934 wider mode. */ 6935 6936 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT 6937 && INTVAL (XEXP (x, 1)) >= 0 6938 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode)) 6939 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode 6940 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) 6941 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))) 6942 break; 6943 6944 /* If the shift count is a constant and we can do arithmetic in 6945 the mode of the shift, refine which bits we need. Otherwise, use the 6946 conservative form of the mask. */ 6947 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6948 && INTVAL (XEXP (x, 1)) >= 0 6949 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode) 6950 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) 6951 mask >>= INTVAL (XEXP (x, 1)); 6952 else 6953 mask = fuller_mask; 6954 6955 op0 = gen_lowpart_for_combine (op_mode, 6956 force_to_mode (XEXP (x, 0), op_mode, 6957 mask, reg, next_select)); 6958 6959 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 6960 x = gen_binary (code, op_mode, op0, XEXP (x, 1)); 6961 break; 6962 6963 case LSHIFTRT: 6964 /* Here we can only do something if the shift count is a constant, 6965 this shift constant is valid for the host, and we can do arithmetic 6966 in OP_MODE. */ 6967 6968 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6969 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 6970 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) 6971 { 6972 rtx inner = XEXP (x, 0); 6973 unsigned HOST_WIDE_INT inner_mask; 6974 6975 /* Select the mask of the bits we need for the shift operand. */ 6976 inner_mask = mask << INTVAL (XEXP (x, 1)); 6977 6978 /* We can only change the mode of the shift if we can do arithmetic 6979 in the mode of the shift and INNER_MASK is no wider than the 6980 width of OP_MODE. */ 6981 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT 6982 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0) 6983 op_mode = GET_MODE (x); 6984 6985 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select); 6986 6987 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) 6988 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); 6989 } 6990 6991 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the 6992 shift and AND produces only copies of the sign bit (C2 is one less 6993 than a power of two), we can do this with just a shift. */ 6994 6995 if (GET_CODE (x) == LSHIFTRT 6996 && GET_CODE (XEXP (x, 1)) == CONST_INT 6997 /* The shift puts one of the sign bit copies in the least significant 6998 bit. */ 6999 && ((INTVAL (XEXP (x, 1)) 7000 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) 7001 >= GET_MODE_BITSIZE (GET_MODE (x))) 7002 && exact_log2 (mask + 1) >= 0 7003 /* Number of bits left after the shift must be more than the mask 7004 needs. */ 7005 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1)) 7006 <= GET_MODE_BITSIZE (GET_MODE (x))) 7007 /* Must be more sign bit copies than the mask needs. */ 7008 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 7009 >= exact_log2 (mask + 1))) 7010 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), 7011 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x)) 7012 - exact_log2 (mask + 1))); 7013 7014 goto shiftrt; 7015 7016 case ASHIFTRT: 7017 /* If we are just looking for the sign bit, we don't need this shift at 7018 all, even if it has a variable count. */ 7019 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 7020 && (mask == ((unsigned HOST_WIDE_INT) 1 7021 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 7022 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 7023 7024 /* If this is a shift by a constant, get a mask that contains those bits 7025 that are not copies of the sign bit. We then have two cases: If 7026 MASK only includes those bits, this can be a logical shift, which may 7027 allow simplifications. If MASK is a single-bit field not within 7028 those bits, we are requesting a copy of the sign bit and hence can 7029 shift the sign bit to the appropriate location. */ 7030 7031 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0 7032 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 7033 { 7034 int i = -1; 7035 7036 /* If the considered data is wider than HOST_WIDE_INT, we can't 7037 represent a mask for all its bits in a single scalar. 7038 But we only care about the lower bits, so calculate these. */ 7039 7040 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT) 7041 { 7042 nonzero = ~(HOST_WIDE_INT) 0; 7043 7044 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 7045 is the number of bits a full-width mask would have set. 7046 We need only shift if these are fewer than nonzero can 7047 hold. If not, we must keep all bits set in nonzero. */ 7048 7049 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 7050 < HOST_BITS_PER_WIDE_INT) 7051 nonzero >>= INTVAL (XEXP (x, 1)) 7052 + HOST_BITS_PER_WIDE_INT 7053 - GET_MODE_BITSIZE (GET_MODE (x)) ; 7054 } 7055 else 7056 { 7057 nonzero = GET_MODE_MASK (GET_MODE (x)); 7058 nonzero >>= INTVAL (XEXP (x, 1)); 7059 } 7060 7061 if ((mask & ~nonzero) == 0 7062 || (i = exact_log2 (mask)) >= 0) 7063 { 7064 x = simplify_shift_const 7065 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0), 7066 i < 0 ? INTVAL (XEXP (x, 1)) 7067 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i); 7068 7069 if (GET_CODE (x) != ASHIFTRT) 7070 return force_to_mode (x, mode, mask, reg, next_select); 7071 } 7072 } 7073 7074 /* If MASK is 1, convert this to a LSHIFTRT. This can be done 7075 even if the shift count isn't a constant. */ 7076 if (mask == 1) 7077 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)); 7078 7079 shiftrt: 7080 7081 /* If this is a zero- or sign-extension operation that just affects bits 7082 we don't care about, remove it. Be sure the call above returned 7083 something that is still a shift. */ 7084 7085 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) 7086 && GET_CODE (XEXP (x, 1)) == CONST_INT 7087 && INTVAL (XEXP (x, 1)) >= 0 7088 && (INTVAL (XEXP (x, 1)) 7089 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1)) 7090 && GET_CODE (XEXP (x, 0)) == ASHIFT 7091 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 7092 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1))) 7093 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, 7094 reg, next_select); 7095 7096 break; 7097 7098 case ROTATE: 7099 case ROTATERT: 7100 /* If the shift count is constant and we can do computations 7101 in the mode of X, compute where the bits we care about are. 7102 Otherwise, we can't do anything. Don't change the mode of 7103 the shift or propagate MODE into the shift, though. */ 7104 if (GET_CODE (XEXP (x, 1)) == CONST_INT 7105 && INTVAL (XEXP (x, 1)) >= 0) 7106 { 7107 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, 7108 GET_MODE (x), GEN_INT (mask), 7109 XEXP (x, 1)); 7110 if (temp && GET_CODE(temp) == CONST_INT) 7111 SUBST (XEXP (x, 0), 7112 force_to_mode (XEXP (x, 0), GET_MODE (x), 7113 INTVAL (temp), reg, next_select)); 7114 } 7115 break; 7116 7117 case NEG: 7118 /* If we just want the low-order bit, the NEG isn't needed since it 7119 won't change the low-order bit. */ 7120 if (mask == 1) 7121 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select); 7122 7123 /* We need any bits less significant than the most significant bit in 7124 MASK since carries from those bits will affect the bits we are 7125 interested in. */ 7126 mask = fuller_mask; 7127 goto unop; 7128 7129 case NOT: 7130 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the 7131 same as the XOR case above. Ensure that the constant we form is not 7132 wider than the mode of X. */ 7133 7134 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 7135 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 7136 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 7137 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) 7138 < GET_MODE_BITSIZE (GET_MODE (x))) 7139 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) 7140 { 7141 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1))); 7142 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp); 7143 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1)); 7144 7145 return force_to_mode (x, mode, mask, reg, next_select); 7146 } 7147 7148 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must 7149 use the full mask inside the NOT. */ 7150 mask = fuller_mask; 7151 7152 unop: 7153 op0 = gen_lowpart_for_combine (op_mode, 7154 force_to_mode (XEXP (x, 0), mode, mask, 7155 reg, next_select)); 7156 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 7157 x = simplify_gen_unary (code, op_mode, op0, op_mode); 7158 break; 7159 7160 case NE: 7161 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included 7162 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, 7163 which is equal to STORE_FLAG_VALUE. */ 7164 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx 7165 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0 7166 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE) 7167 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 7168 7169 break; 7170 7171 case IF_THEN_ELSE: 7172 /* We have no way of knowing if the IF_THEN_ELSE can itself be 7173 written in a narrower mode. We play it safe and do not do so. */ 7174 7175 SUBST (XEXP (x, 1), 7176 gen_lowpart_for_combine (GET_MODE (x), 7177 force_to_mode (XEXP (x, 1), mode, 7178 mask, reg, next_select))); 7179 SUBST (XEXP (x, 2), 7180 gen_lowpart_for_combine (GET_MODE (x), 7181 force_to_mode (XEXP (x, 2), mode, 7182 mask, reg,next_select))); 7183 break; 7184 7185 default: 7186 break; 7187 } 7188 7189 /* Ensure we return a value of the proper mode. */ 7190 return gen_lowpart_for_combine (mode, x); 7191} 7192 7193/* Return nonzero if X is an expression that has one of two values depending on 7194 whether some other value is zero or nonzero. In that case, we return the 7195 value that is being tested, *PTRUE is set to the value if the rtx being 7196 returned has a nonzero value, and *PFALSE is set to the other alternative. 7197 7198 If we return zero, we set *PTRUE and *PFALSE to X. */ 7199 7200static rtx 7201if_then_else_cond (x, ptrue, pfalse) 7202 rtx x; 7203 rtx *ptrue, *pfalse; 7204{ 7205 enum machine_mode mode = GET_MODE (x); 7206 enum rtx_code code = GET_CODE (x); 7207 rtx cond0, cond1, true0, true1, false0, false1; 7208 unsigned HOST_WIDE_INT nz; 7209 7210 /* If we are comparing a value against zero, we are done. */ 7211 if ((code == NE || code == EQ) 7212 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0) 7213 { 7214 *ptrue = (code == NE) ? const_true_rtx : const0_rtx; 7215 *pfalse = (code == NE) ? const0_rtx : const_true_rtx; 7216 return XEXP (x, 0); 7217 } 7218 7219 /* If this is a unary operation whose operand has one of two values, apply 7220 our opcode to compute those values. */ 7221 else if (GET_RTX_CLASS (code) == '1' 7222 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) 7223 { 7224 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0))); 7225 *pfalse = simplify_gen_unary (code, mode, false0, 7226 GET_MODE (XEXP (x, 0))); 7227 return cond0; 7228 } 7229 7230 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would 7231 make can't possibly match and would suppress other optimizations. */ 7232 else if (code == COMPARE) 7233 ; 7234 7235 /* If this is a binary operation, see if either side has only one of two 7236 values. If either one does or if both do and they are conditional on 7237 the same value, compute the new true and false values. */ 7238 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2' 7239 || GET_RTX_CLASS (code) == '<') 7240 { 7241 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0); 7242 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1); 7243 7244 if ((cond0 != 0 || cond1 != 0) 7245 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1))) 7246 { 7247 /* If if_then_else_cond returned zero, then true/false are the 7248 same rtl. We must copy one of them to prevent invalid rtl 7249 sharing. */ 7250 if (cond0 == 0) 7251 true0 = copy_rtx (true0); 7252 else if (cond1 == 0) 7253 true1 = copy_rtx (true1); 7254 7255 *ptrue = gen_binary (code, mode, true0, true1); 7256 *pfalse = gen_binary (code, mode, false0, false1); 7257 return cond0 ? cond0 : cond1; 7258 } 7259 7260 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the 7261 operands is zero when the other is non-zero, and vice-versa, 7262 and STORE_FLAG_VALUE is 1 or -1. */ 7263 7264 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 7265 && (code == PLUS || code == IOR || code == XOR || code == MINUS 7266 || code == UMAX) 7267 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 7268 { 7269 rtx op0 = XEXP (XEXP (x, 0), 1); 7270 rtx op1 = XEXP (XEXP (x, 1), 1); 7271 7272 cond0 = XEXP (XEXP (x, 0), 0); 7273 cond1 = XEXP (XEXP (x, 1), 0); 7274 7275 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<' 7276 && GET_RTX_CLASS (GET_CODE (cond1)) == '<' 7277 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1) 7278 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 7279 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 7280 || ((swap_condition (GET_CODE (cond0)) 7281 == combine_reversed_comparison_code (cond1)) 7282 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 7283 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 7284 && ! side_effects_p (x)) 7285 { 7286 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx); 7287 *pfalse = gen_binary (MULT, mode, 7288 (code == MINUS 7289 ? simplify_gen_unary (NEG, mode, op1, 7290 mode) 7291 : op1), 7292 const_true_rtx); 7293 return cond0; 7294 } 7295 } 7296 7297 /* Similarly for MULT, AND and UMIN, except that for these the result 7298 is always zero. */ 7299 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 7300 && (code == MULT || code == AND || code == UMIN) 7301 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 7302 { 7303 cond0 = XEXP (XEXP (x, 0), 0); 7304 cond1 = XEXP (XEXP (x, 1), 0); 7305 7306 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<' 7307 && GET_RTX_CLASS (GET_CODE (cond1)) == '<' 7308 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1) 7309 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 7310 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 7311 || ((swap_condition (GET_CODE (cond0)) 7312 == combine_reversed_comparison_code (cond1)) 7313 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 7314 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 7315 && ! side_effects_p (x)) 7316 { 7317 *ptrue = *pfalse = const0_rtx; 7318 return cond0; 7319 } 7320 } 7321 } 7322 7323 else if (code == IF_THEN_ELSE) 7324 { 7325 /* If we have IF_THEN_ELSE already, extract the condition and 7326 canonicalize it if it is NE or EQ. */ 7327 cond0 = XEXP (x, 0); 7328 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); 7329 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) 7330 return XEXP (cond0, 0); 7331 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) 7332 { 7333 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); 7334 return XEXP (cond0, 0); 7335 } 7336 else 7337 return cond0; 7338 } 7339 7340 /* If X is a SUBREG, we can narrow both the true and false values 7341 if the inner expression, if there is a condition. */ 7342 else if (code == SUBREG 7343 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), 7344 &true0, &false0))) 7345 { 7346 *ptrue = simplify_gen_subreg (mode, true0, 7347 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 7348 *pfalse = simplify_gen_subreg (mode, false0, 7349 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 7350 7351 return cond0; 7352 } 7353 7354 /* If X is a constant, this isn't special and will cause confusions 7355 if we treat it as such. Likewise if it is equivalent to a constant. */ 7356 else if (CONSTANT_P (x) 7357 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) 7358 ; 7359 7360 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that 7361 will be least confusing to the rest of the compiler. */ 7362 else if (mode == BImode) 7363 { 7364 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx; 7365 return x; 7366 } 7367 7368 /* If X is known to be either 0 or -1, those are the true and 7369 false values when testing X. */ 7370 else if (x == constm1_rtx || x == const0_rtx 7371 || (mode != VOIDmode 7372 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode))) 7373 { 7374 *ptrue = constm1_rtx, *pfalse = const0_rtx; 7375 return x; 7376 } 7377 7378 /* Likewise for 0 or a single bit. */ 7379 else if (mode != VOIDmode 7380 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 7381 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0) 7382 { 7383 *ptrue = GEN_INT (trunc_int_for_mode (nz, mode)), *pfalse = const0_rtx; 7384 return x; 7385 } 7386 7387 /* Otherwise fail; show no condition with true and false values the same. */ 7388 *ptrue = *pfalse = x; 7389 return 0; 7390} 7391 7392/* Return the value of expression X given the fact that condition COND 7393 is known to be true when applied to REG as its first operand and VAL 7394 as its second. X is known to not be shared and so can be modified in 7395 place. 7396 7397 We only handle the simplest cases, and specifically those cases that 7398 arise with IF_THEN_ELSE expressions. */ 7399 7400static rtx 7401known_cond (x, cond, reg, val) 7402 rtx x; 7403 enum rtx_code cond; 7404 rtx reg, val; 7405{ 7406 enum rtx_code code = GET_CODE (x); 7407 rtx temp; 7408 const char *fmt; 7409 int i, j; 7410 7411 if (side_effects_p (x)) 7412 return x; 7413 7414 /* If either operand of the condition is a floating point value, 7415 then we have to avoid collapsing an EQ comparison. */ 7416 if (cond == EQ 7417 && rtx_equal_p (x, reg) 7418 && ! FLOAT_MODE_P (GET_MODE (x)) 7419 && ! FLOAT_MODE_P (GET_MODE (val))) 7420 return val; 7421 7422 if (cond == UNEQ && rtx_equal_p (x, reg)) 7423 return val; 7424 7425 /* If X is (abs REG) and we know something about REG's relationship 7426 with zero, we may be able to simplify this. */ 7427 7428 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) 7429 switch (cond) 7430 { 7431 case GE: case GT: case EQ: 7432 return XEXP (x, 0); 7433 case LT: case LE: 7434 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)), 7435 XEXP (x, 0), 7436 GET_MODE (XEXP (x, 0))); 7437 default: 7438 break; 7439 } 7440 7441 /* The only other cases we handle are MIN, MAX, and comparisons if the 7442 operands are the same as REG and VAL. */ 7443 7444 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') 7445 { 7446 if (rtx_equal_p (XEXP (x, 0), val)) 7447 cond = swap_condition (cond), temp = val, val = reg, reg = temp; 7448 7449 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) 7450 { 7451 if (GET_RTX_CLASS (code) == '<') 7452 { 7453 if (comparison_dominates_p (cond, code)) 7454 return const_true_rtx; 7455 7456 code = combine_reversed_comparison_code (x); 7457 if (code != UNKNOWN 7458 && comparison_dominates_p (cond, code)) 7459 return const0_rtx; 7460 else 7461 return x; 7462 } 7463 else if (code == SMAX || code == SMIN 7464 || code == UMIN || code == UMAX) 7465 { 7466 int unsignedp = (code == UMIN || code == UMAX); 7467 7468 /* Do not reverse the condition when it is NE or EQ. 7469 This is because we cannot conclude anything about 7470 the value of 'SMAX (x, y)' when x is not equal to y, 7471 but we can when x equals y. */ 7472 if ((code == SMAX || code == UMAX) 7473 && ! (cond == EQ || cond == NE)) 7474 cond = reverse_condition (cond); 7475 7476 switch (cond) 7477 { 7478 case GE: case GT: 7479 return unsignedp ? x : XEXP (x, 1); 7480 case LE: case LT: 7481 return unsignedp ? x : XEXP (x, 0); 7482 case GEU: case GTU: 7483 return unsignedp ? XEXP (x, 1) : x; 7484 case LEU: case LTU: 7485 return unsignedp ? XEXP (x, 0) : x; 7486 default: 7487 break; 7488 } 7489 } 7490 } 7491 } 7492 else if (code == SUBREG) 7493 { 7494 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x)); 7495 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val); 7496 7497 if (SUBREG_REG (x) != r) 7498 { 7499 /* We must simplify subreg here, before we lose track of the 7500 original inner_mode. */ 7501 new = simplify_subreg (GET_MODE (x), r, 7502 inner_mode, SUBREG_BYTE (x)); 7503 if (new) 7504 return new; 7505 else 7506 SUBST (SUBREG_REG (x), r); 7507 } 7508 7509 return x; 7510 } 7511 /* We don't have to handle SIGN_EXTEND here, because even in the 7512 case of replacing something with a modeless CONST_INT, a 7513 CONST_INT is already (supposed to be) a valid sign extension for 7514 its narrower mode, which implies it's already properly 7515 sign-extended for the wider mode. Now, for ZERO_EXTEND, the 7516 story is different. */ 7517 else if (code == ZERO_EXTEND) 7518 { 7519 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0)); 7520 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val); 7521 7522 if (XEXP (x, 0) != r) 7523 { 7524 /* We must simplify the zero_extend here, before we lose 7525 track of the original inner_mode. */ 7526 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), 7527 r, inner_mode); 7528 if (new) 7529 return new; 7530 else 7531 SUBST (XEXP (x, 0), r); 7532 } 7533 7534 return x; 7535 } 7536 7537 fmt = GET_RTX_FORMAT (code); 7538 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 7539 { 7540 if (fmt[i] == 'e') 7541 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); 7542 else if (fmt[i] == 'E') 7543 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 7544 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), 7545 cond, reg, val)); 7546 } 7547 7548 return x; 7549} 7550 7551/* See if X and Y are equal for the purposes of seeing if we can rewrite an 7552 assignment as a field assignment. */ 7553 7554static int 7555rtx_equal_for_field_assignment_p (x, y) 7556 rtx x; 7557 rtx y; 7558{ 7559 if (x == y || rtx_equal_p (x, y)) 7560 return 1; 7561 7562 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) 7563 return 0; 7564 7565 /* Check for a paradoxical SUBREG of a MEM compared with the MEM. 7566 Note that all SUBREGs of MEM are paradoxical; otherwise they 7567 would have been rewritten. */ 7568 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG 7569 && GET_CODE (SUBREG_REG (y)) == MEM 7570 && rtx_equal_p (SUBREG_REG (y), 7571 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x))) 7572 return 1; 7573 7574 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG 7575 && GET_CODE (SUBREG_REG (x)) == MEM 7576 && rtx_equal_p (SUBREG_REG (x), 7577 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y))) 7578 return 1; 7579 7580 /* We used to see if get_last_value of X and Y were the same but that's 7581 not correct. In one direction, we'll cause the assignment to have 7582 the wrong destination and in the case, we'll import a register into this 7583 insn that might have already have been dead. So fail if none of the 7584 above cases are true. */ 7585 return 0; 7586} 7587 7588/* See if X, a SET operation, can be rewritten as a bit-field assignment. 7589 Return that assignment if so. 7590 7591 We only handle the most common cases. */ 7592 7593static rtx 7594make_field_assignment (x) 7595 rtx x; 7596{ 7597 rtx dest = SET_DEST (x); 7598 rtx src = SET_SRC (x); 7599 rtx assign; 7600 rtx rhs, lhs; 7601 HOST_WIDE_INT c1; 7602 HOST_WIDE_INT pos; 7603 unsigned HOST_WIDE_INT len; 7604 rtx other; 7605 enum machine_mode mode; 7606 7607 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is 7608 a clear of a one-bit field. We will have changed it to 7609 (and (rotate (const_int -2) POS) DEST), so check for that. Also check 7610 for a SUBREG. */ 7611 7612 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE 7613 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT 7614 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 7615 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7616 { 7617 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 7618 1, 1, 1, 0); 7619 if (assign != 0) 7620 return gen_rtx_SET (VOIDmode, assign, const0_rtx); 7621 return x; 7622 } 7623 7624 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG 7625 && subreg_lowpart_p (XEXP (src, 0)) 7626 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) 7627 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) 7628 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE 7629 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 7630 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7631 { 7632 assign = make_extraction (VOIDmode, dest, 0, 7633 XEXP (SUBREG_REG (XEXP (src, 0)), 1), 7634 1, 1, 1, 0); 7635 if (assign != 0) 7636 return gen_rtx_SET (VOIDmode, assign, const0_rtx); 7637 return x; 7638 } 7639 7640 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a 7641 one-bit field. */ 7642 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT 7643 && XEXP (XEXP (src, 0), 0) == const1_rtx 7644 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7645 { 7646 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 7647 1, 1, 1, 0); 7648 if (assign != 0) 7649 return gen_rtx_SET (VOIDmode, assign, const1_rtx); 7650 return x; 7651 } 7652 7653 /* The other case we handle is assignments into a constant-position 7654 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents 7655 a mask that has all one bits except for a group of zero bits and 7656 OTHER is known to have zeros where C1 has ones, this is such an 7657 assignment. Compute the position and length from C1. Shift OTHER 7658 to the appropriate position, force it to the required mode, and 7659 make the extraction. Check for the AND in both operands. */ 7660 7661 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) 7662 return x; 7663 7664 rhs = expand_compound_operation (XEXP (src, 0)); 7665 lhs = expand_compound_operation (XEXP (src, 1)); 7666 7667 if (GET_CODE (rhs) == AND 7668 && GET_CODE (XEXP (rhs, 1)) == CONST_INT 7669 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) 7670 c1 = INTVAL (XEXP (rhs, 1)), other = lhs; 7671 else if (GET_CODE (lhs) == AND 7672 && GET_CODE (XEXP (lhs, 1)) == CONST_INT 7673 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) 7674 c1 = INTVAL (XEXP (lhs, 1)), other = rhs; 7675 else 7676 return x; 7677 7678 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len); 7679 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest)) 7680 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT 7681 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0) 7682 return x; 7683 7684 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); 7685 if (assign == 0) 7686 return x; 7687 7688 /* The mode to use for the source is the mode of the assignment, or of 7689 what is inside a possible STRICT_LOW_PART. */ 7690 mode = (GET_CODE (assign) == STRICT_LOW_PART 7691 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); 7692 7693 /* Shift OTHER right POS places and make it the source, restricting it 7694 to the proper length and mode. */ 7695 7696 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT, 7697 GET_MODE (src), other, pos), 7698 mode, 7699 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT 7700 ? ~(unsigned HOST_WIDE_INT) 0 7701 : ((unsigned HOST_WIDE_INT) 1 << len) - 1, 7702 dest, 0); 7703 7704 return gen_rtx_SET (VOIDmode, assign, src); 7705} 7706 7707/* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) 7708 if so. */ 7709 7710static rtx 7711apply_distributive_law (x) 7712 rtx x; 7713{ 7714 enum rtx_code code = GET_CODE (x); 7715 rtx lhs, rhs, other; 7716 rtx tem; 7717 enum rtx_code inner_code; 7718 7719 /* Distributivity is not true for floating point. 7720 It can change the value. So don't do it. 7721 -- rms and moshier@world.std.com. */ 7722 if (FLOAT_MODE_P (GET_MODE (x))) 7723 return x; 7724 7725 /* The outer operation can only be one of the following: */ 7726 if (code != IOR && code != AND && code != XOR 7727 && code != PLUS && code != MINUS) 7728 return x; 7729 7730 lhs = XEXP (x, 0), rhs = XEXP (x, 1); 7731 7732 /* If either operand is a primitive we can't do anything, so get out 7733 fast. */ 7734 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o' 7735 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o') 7736 return x; 7737 7738 lhs = expand_compound_operation (lhs); 7739 rhs = expand_compound_operation (rhs); 7740 inner_code = GET_CODE (lhs); 7741 if (inner_code != GET_CODE (rhs)) 7742 return x; 7743 7744 /* See if the inner and outer operations distribute. */ 7745 switch (inner_code) 7746 { 7747 case LSHIFTRT: 7748 case ASHIFTRT: 7749 case AND: 7750 case IOR: 7751 /* These all distribute except over PLUS. */ 7752 if (code == PLUS || code == MINUS) 7753 return x; 7754 break; 7755 7756 case MULT: 7757 if (code != PLUS && code != MINUS) 7758 return x; 7759 break; 7760 7761 case ASHIFT: 7762 /* This is also a multiply, so it distributes over everything. */ 7763 break; 7764 7765 case SUBREG: 7766 /* Non-paradoxical SUBREGs distributes over all operations, provided 7767 the inner modes and byte offsets are the same, this is an extraction 7768 of a low-order part, we don't convert an fp operation to int or 7769 vice versa, and we would not be converting a single-word 7770 operation into a multi-word operation. The latter test is not 7771 required, but it prevents generating unneeded multi-word operations. 7772 Some of the previous tests are redundant given the latter test, but 7773 are retained because they are required for correctness. 7774 7775 We produce the result slightly differently in this case. */ 7776 7777 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs)) 7778 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs) 7779 || ! subreg_lowpart_p (lhs) 7780 || (GET_MODE_CLASS (GET_MODE (lhs)) 7781 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) 7782 || (GET_MODE_SIZE (GET_MODE (lhs)) 7783 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) 7784 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD) 7785 return x; 7786 7787 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)), 7788 SUBREG_REG (lhs), SUBREG_REG (rhs)); 7789 return gen_lowpart_for_combine (GET_MODE (x), tem); 7790 7791 default: 7792 return x; 7793 } 7794 7795 /* Set LHS and RHS to the inner operands (A and B in the example 7796 above) and set OTHER to the common operand (C in the example). 7797 These is only one way to do this unless the inner operation is 7798 commutative. */ 7799 if (GET_RTX_CLASS (inner_code) == 'c' 7800 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) 7801 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); 7802 else if (GET_RTX_CLASS (inner_code) == 'c' 7803 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) 7804 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); 7805 else if (GET_RTX_CLASS (inner_code) == 'c' 7806 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) 7807 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); 7808 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) 7809 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); 7810 else 7811 return x; 7812 7813 /* Form the new inner operation, seeing if it simplifies first. */ 7814 tem = gen_binary (code, GET_MODE (x), lhs, rhs); 7815 7816 /* There is one exception to the general way of distributing: 7817 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */ 7818 if (code == XOR && inner_code == IOR) 7819 { 7820 inner_code = AND; 7821 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x)); 7822 } 7823 7824 /* We may be able to continuing distributing the result, so call 7825 ourselves recursively on the inner operation before forming the 7826 outer operation, which we return. */ 7827 return gen_binary (inner_code, GET_MODE (x), 7828 apply_distributive_law (tem), other); 7829} 7830 7831/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done 7832 in MODE. 7833 7834 Return an equivalent form, if different from X. Otherwise, return X. If 7835 X is zero, we are to always construct the equivalent form. */ 7836 7837static rtx 7838simplify_and_const_int (x, mode, varop, constop) 7839 rtx x; 7840 enum machine_mode mode; 7841 rtx varop; 7842 unsigned HOST_WIDE_INT constop; 7843{ 7844 unsigned HOST_WIDE_INT nonzero; 7845 int i; 7846 7847 /* Simplify VAROP knowing that we will be only looking at some of the 7848 bits in it. 7849 7850 Note by passing in CONSTOP, we guarantee that the bits not set in 7851 CONSTOP are not significant and will never be examined. We must 7852 ensure that is the case by explicitly masking out those bits 7853 before returning. */ 7854 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0); 7855 7856 /* If VAROP is a CLOBBER, we will fail so return it. */ 7857 if (GET_CODE (varop) == CLOBBER) 7858 return varop; 7859 7860 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP 7861 to VAROP and return the new constant. */ 7862 if (GET_CODE (varop) == CONST_INT) 7863 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode)); 7864 7865 /* See what bits may be nonzero in VAROP. Unlike the general case of 7866 a call to nonzero_bits, here we don't care about bits outside 7867 MODE. */ 7868 7869 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); 7870 7871 /* Turn off all bits in the constant that are known to already be zero. 7872 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS 7873 which is tested below. */ 7874 7875 constop &= nonzero; 7876 7877 /* If we don't have any bits left, return zero. */ 7878 if (constop == 0) 7879 return const0_rtx; 7880 7881 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is 7882 a power of two, we can replace this with a ASHIFT. */ 7883 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 7884 && (i = exact_log2 (constop)) >= 0) 7885 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); 7886 7887 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR 7888 or XOR, then try to apply the distributive law. This may eliminate 7889 operations if either branch can be simplified because of the AND. 7890 It may also make some cases more complex, but those cases probably 7891 won't match a pattern either with or without this. */ 7892 7893 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) 7894 return 7895 gen_lowpart_for_combine 7896 (mode, 7897 apply_distributive_law 7898 (gen_binary (GET_CODE (varop), GET_MODE (varop), 7899 simplify_and_const_int (NULL_RTX, GET_MODE (varop), 7900 XEXP (varop, 0), constop), 7901 simplify_and_const_int (NULL_RTX, GET_MODE (varop), 7902 XEXP (varop, 1), constop)))); 7903 7904 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute 7905 the AND and see if one of the operands simplifies to zero. If so, we 7906 may eliminate it. */ 7907 7908 if (GET_CODE (varop) == PLUS 7909 && exact_log2 (constop + 1) >= 0) 7910 { 7911 rtx o0, o1; 7912 7913 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop); 7914 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop); 7915 if (o0 == const0_rtx) 7916 return o1; 7917 if (o1 == const0_rtx) 7918 return o0; 7919 } 7920 7921 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG 7922 if we already had one (just check for the simplest cases). */ 7923 if (x && GET_CODE (XEXP (x, 0)) == SUBREG 7924 && GET_MODE (XEXP (x, 0)) == mode 7925 && SUBREG_REG (XEXP (x, 0)) == varop) 7926 varop = XEXP (x, 0); 7927 else 7928 varop = gen_lowpart_for_combine (mode, varop); 7929 7930 /* If we can't make the SUBREG, try to return what we were given. */ 7931 if (GET_CODE (varop) == CLOBBER) 7932 return x ? x : varop; 7933 7934 /* If we are only masking insignificant bits, return VAROP. */ 7935 if (constop == nonzero) 7936 x = varop; 7937 else 7938 { 7939 /* Otherwise, return an AND. */ 7940 constop = trunc_int_for_mode (constop, mode); 7941 /* See how much, if any, of X we can use. */ 7942 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode) 7943 x = gen_binary (AND, mode, varop, GEN_INT (constop)); 7944 7945 else 7946 { 7947 if (GET_CODE (XEXP (x, 1)) != CONST_INT 7948 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop) 7949 SUBST (XEXP (x, 1), GEN_INT (constop)); 7950 7951 SUBST (XEXP (x, 0), varop); 7952 } 7953 } 7954 7955 return x; 7956} 7957 7958/* We let num_sign_bit_copies recur into nonzero_bits as that is useful. 7959 We don't let nonzero_bits recur into num_sign_bit_copies, because that 7960 is less useful. We can't allow both, because that results in exponential 7961 run time recursion. There is a nullstone testcase that triggered 7962 this. This macro avoids accidental uses of num_sign_bit_copies. */ 7963#define num_sign_bit_copies() 7964 7965/* Given an expression, X, compute which bits in X can be non-zero. 7966 We don't care about bits outside of those defined in MODE. 7967 7968 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is 7969 a shift, AND, or zero_extract, we can do better. */ 7970 7971static unsigned HOST_WIDE_INT 7972nonzero_bits (x, mode) 7973 rtx x; 7974 enum machine_mode mode; 7975{ 7976 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode); 7977 unsigned HOST_WIDE_INT inner_nz; 7978 enum rtx_code code; 7979 unsigned int mode_width = GET_MODE_BITSIZE (mode); 7980 rtx tem; 7981 7982 /* For floating-point values, assume all bits are needed. */ 7983 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode)) 7984 return nonzero; 7985 7986 /* If X is wider than MODE, use its mode instead. */ 7987 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width) 7988 { 7989 mode = GET_MODE (x); 7990 nonzero = GET_MODE_MASK (mode); 7991 mode_width = GET_MODE_BITSIZE (mode); 7992 } 7993 7994 if (mode_width > HOST_BITS_PER_WIDE_INT) 7995 /* Our only callers in this case look for single bit values. So 7996 just return the mode mask. Those tests will then be false. */ 7997 return nonzero; 7998 7999#ifndef WORD_REGISTER_OPERATIONS 8000 /* If MODE is wider than X, but both are a single word for both the host 8001 and target machines, we can compute this from which bits of the 8002 object might be nonzero in its own mode, taking into account the fact 8003 that on many CISC machines, accessing an object in a wider mode 8004 causes the high-order bits to become undefined. So they are 8005 not known to be zero. */ 8006 8007 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode 8008 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD 8009 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 8010 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x))) 8011 { 8012 nonzero &= nonzero_bits (x, GET_MODE (x)); 8013 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)); 8014 return nonzero; 8015 } 8016#endif 8017 8018 code = GET_CODE (x); 8019 switch (code) 8020 { 8021 case REG: 8022#if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) 8023 /* If pointers extend unsigned and this is a pointer in Pmode, say that 8024 all the bits above ptr_mode are known to be zero. */ 8025 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode 8026 && REG_POINTER (x)) 8027 nonzero &= GET_MODE_MASK (ptr_mode); 8028#endif 8029 8030 /* Include declared information about alignment of pointers. */ 8031 /* ??? We don't properly preserve REG_POINTER changes across 8032 pointer-to-integer casts, so we can't trust it except for 8033 things that we know must be pointers. See execute/960116-1.c. */ 8034 if ((x == stack_pointer_rtx 8035 || x == frame_pointer_rtx 8036 || x == arg_pointer_rtx) 8037 && REGNO_POINTER_ALIGN (REGNO (x))) 8038 { 8039 unsigned HOST_WIDE_INT alignment 8040 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT; 8041 8042#ifdef PUSH_ROUNDING 8043 /* If PUSH_ROUNDING is defined, it is possible for the 8044 stack to be momentarily aligned only to that amount, 8045 so we pick the least alignment. */ 8046 if (x == stack_pointer_rtx && PUSH_ARGS) 8047 alignment = MIN (PUSH_ROUNDING (1), alignment); 8048#endif 8049 8050 nonzero &= ~(alignment - 1); 8051 } 8052 8053 /* If X is a register whose nonzero bits value is current, use it. 8054 Otherwise, if X is a register whose value we can find, use that 8055 value. Otherwise, use the previously-computed global nonzero bits 8056 for this register. */ 8057 8058 if (reg_last_set_value[REGNO (x)] != 0 8059 && (reg_last_set_mode[REGNO (x)] == mode 8060 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT 8061 && GET_MODE_CLASS (mode) == MODE_INT)) 8062 && (reg_last_set_label[REGNO (x)] == label_tick 8063 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 8064 && REG_N_SETS (REGNO (x)) == 1 8065 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, 8066 REGNO (x)))) 8067 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) 8068 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero; 8069 8070 tem = get_last_value (x); 8071 8072 if (tem) 8073 { 8074#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 8075 /* If X is narrower than MODE and TEM is a non-negative 8076 constant that would appear negative in the mode of X, 8077 sign-extend it for use in reg_nonzero_bits because some 8078 machines (maybe most) will actually do the sign-extension 8079 and this is the conservative approach. 8080 8081 ??? For 2.5, try to tighten up the MD files in this regard 8082 instead of this kludge. */ 8083 8084 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width 8085 && GET_CODE (tem) == CONST_INT 8086 && INTVAL (tem) > 0 8087 && 0 != (INTVAL (tem) 8088 & ((HOST_WIDE_INT) 1 8089 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 8090 tem = GEN_INT (INTVAL (tem) 8091 | ((HOST_WIDE_INT) (-1) 8092 << GET_MODE_BITSIZE (GET_MODE (x)))); 8093#endif 8094 return nonzero_bits (tem, mode) & nonzero; 8095 } 8096 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)]) 8097 { 8098 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)]; 8099 8100 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width) 8101 /* We don't know anything about the upper bits. */ 8102 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x)); 8103 return nonzero & mask; 8104 } 8105 else 8106 return nonzero; 8107 8108 case CONST_INT: 8109#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 8110 /* If X is negative in MODE, sign-extend the value. */ 8111 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD 8112 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1)))) 8113 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width)); 8114#endif 8115 8116 return INTVAL (x); 8117 8118 case MEM: 8119#ifdef LOAD_EXTEND_OP 8120 /* In many, if not most, RISC machines, reading a byte from memory 8121 zeros the rest of the register. Noticing that fact saves a lot 8122 of extra zero-extends. */ 8123 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND) 8124 nonzero &= GET_MODE_MASK (GET_MODE (x)); 8125#endif 8126 break; 8127 8128 case EQ: case NE: 8129 case UNEQ: case LTGT: 8130 case GT: case GTU: case UNGT: 8131 case LT: case LTU: case UNLT: 8132 case GE: case GEU: case UNGE: 8133 case LE: case LEU: case UNLE: 8134 case UNORDERED: case ORDERED: 8135 8136 /* If this produces an integer result, we know which bits are set. 8137 Code here used to clear bits outside the mode of X, but that is 8138 now done above. */ 8139 8140 if (GET_MODE_CLASS (mode) == MODE_INT 8141 && mode_width <= HOST_BITS_PER_WIDE_INT) 8142 nonzero = STORE_FLAG_VALUE; 8143 break; 8144 8145 case NEG: 8146#if 0 8147 /* Disabled to avoid exponential mutual recursion between nonzero_bits 8148 and num_sign_bit_copies. */ 8149 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) 8150 == GET_MODE_BITSIZE (GET_MODE (x))) 8151 nonzero = 1; 8152#endif 8153 8154 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width) 8155 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x))); 8156 break; 8157 8158 case ABS: 8159#if 0 8160 /* Disabled to avoid exponential mutual recursion between nonzero_bits 8161 and num_sign_bit_copies. */ 8162 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) 8163 == GET_MODE_BITSIZE (GET_MODE (x))) 8164 nonzero = 1; 8165#endif 8166 break; 8167 8168 case TRUNCATE: 8169 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode)); 8170 break; 8171 8172 case ZERO_EXTEND: 8173 nonzero &= nonzero_bits (XEXP (x, 0), mode); 8174 if (GET_MODE (XEXP (x, 0)) != VOIDmode) 8175 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); 8176 break; 8177 8178 case SIGN_EXTEND: 8179 /* If the sign bit is known clear, this is the same as ZERO_EXTEND. 8180 Otherwise, show all the bits in the outer mode but not the inner 8181 may be non-zero. */ 8182 inner_nz = nonzero_bits (XEXP (x, 0), mode); 8183 if (GET_MODE (XEXP (x, 0)) != VOIDmode) 8184 { 8185 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); 8186 if (inner_nz 8187 & (((HOST_WIDE_INT) 1 8188 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))) 8189 inner_nz |= (GET_MODE_MASK (mode) 8190 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))); 8191 } 8192 8193 nonzero &= inner_nz; 8194 break; 8195 8196 case AND: 8197 nonzero &= (nonzero_bits (XEXP (x, 0), mode) 8198 & nonzero_bits (XEXP (x, 1), mode)); 8199 break; 8200 8201 case XOR: case IOR: 8202 case UMIN: case UMAX: case SMIN: case SMAX: 8203 { 8204 unsigned HOST_WIDE_INT nonzero0 = nonzero_bits (XEXP (x, 0), mode); 8205 8206 /* Don't call nonzero_bits for the second time if it cannot change 8207 anything. */ 8208 if ((nonzero & nonzero0) != nonzero) 8209 nonzero &= (nonzero0 | nonzero_bits (XEXP (x, 1), mode)); 8210 } 8211 break; 8212 8213 case PLUS: case MINUS: 8214 case MULT: 8215 case DIV: case UDIV: 8216 case MOD: case UMOD: 8217 /* We can apply the rules of arithmetic to compute the number of 8218 high- and low-order zero bits of these operations. We start by 8219 computing the width (position of the highest-order non-zero bit) 8220 and the number of low-order zero bits for each value. */ 8221 { 8222 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode); 8223 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode); 8224 int width0 = floor_log2 (nz0) + 1; 8225 int width1 = floor_log2 (nz1) + 1; 8226 int low0 = floor_log2 (nz0 & -nz0); 8227 int low1 = floor_log2 (nz1 & -nz1); 8228 HOST_WIDE_INT op0_maybe_minusp 8229 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); 8230 HOST_WIDE_INT op1_maybe_minusp 8231 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); 8232 unsigned int result_width = mode_width; 8233 int result_low = 0; 8234 8235 switch (code) 8236 { 8237 case PLUS: 8238 result_width = MAX (width0, width1) + 1; 8239 result_low = MIN (low0, low1); 8240 break; 8241 case MINUS: 8242 result_low = MIN (low0, low1); 8243 break; 8244 case MULT: 8245 result_width = width0 + width1; 8246 result_low = low0 + low1; 8247 break; 8248 case DIV: 8249 if (width1 == 0) 8250 break; 8251 if (! op0_maybe_minusp && ! op1_maybe_minusp) 8252 result_width = width0; 8253 break; 8254 case UDIV: 8255 if (width1 == 0) 8256 break; 8257 result_width = width0; 8258 break; 8259 case MOD: 8260 if (width1 == 0) 8261 break; 8262 if (! op0_maybe_minusp && ! op1_maybe_minusp) 8263 result_width = MIN (width0, width1); 8264 result_low = MIN (low0, low1); 8265 break; 8266 case UMOD: 8267 if (width1 == 0) 8268 break; 8269 result_width = MIN (width0, width1); 8270 result_low = MIN (low0, low1); 8271 break; 8272 default: 8273 abort (); 8274 } 8275 8276 if (result_width < mode_width) 8277 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1; 8278 8279 if (result_low > 0) 8280 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1); 8281 8282#ifdef POINTERS_EXTEND_UNSIGNED 8283 /* If pointers extend unsigned and this is an addition or subtraction 8284 to a pointer in Pmode, all the bits above ptr_mode are known to be 8285 zero. */ 8286 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode 8287 && (code == PLUS || code == MINUS) 8288 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0))) 8289 nonzero &= GET_MODE_MASK (ptr_mode); 8290#endif 8291 } 8292 break; 8293 8294 case ZERO_EXTRACT: 8295 if (GET_CODE (XEXP (x, 1)) == CONST_INT 8296 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 8297 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1; 8298 break; 8299 8300 case SUBREG: 8301 /* If this is a SUBREG formed for a promoted variable that has 8302 been zero-extended, we know that at least the high-order bits 8303 are zero, though others might be too. */ 8304 8305 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x)) 8306 nonzero = (GET_MODE_MASK (GET_MODE (x)) 8307 & nonzero_bits (SUBREG_REG (x), GET_MODE (x))); 8308 8309 /* If the inner mode is a single word for both the host and target 8310 machines, we can compute this from which bits of the inner 8311 object might be nonzero. */ 8312 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD 8313 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) 8314 <= HOST_BITS_PER_WIDE_INT)) 8315 { 8316 nonzero &= nonzero_bits (SUBREG_REG (x), mode); 8317 8318#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP) 8319 /* If this is a typical RISC machine, we only have to worry 8320 about the way loads are extended. */ 8321 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND 8322 ? (((nonzero 8323 & (((unsigned HOST_WIDE_INT) 1 8324 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))) 8325 != 0)) 8326 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND) 8327#endif 8328 { 8329 /* On many CISC machines, accessing an object in a wider mode 8330 causes the high-order bits to become undefined. So they are 8331 not known to be zero. */ 8332 if (GET_MODE_SIZE (GET_MODE (x)) 8333 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 8334 nonzero |= (GET_MODE_MASK (GET_MODE (x)) 8335 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))); 8336 } 8337 } 8338 break; 8339 8340 case ASHIFTRT: 8341 case LSHIFTRT: 8342 case ASHIFT: 8343 case ROTATE: 8344 /* The nonzero bits are in two classes: any bits within MODE 8345 that aren't in GET_MODE (x) are always significant. The rest of the 8346 nonzero bits are those that are significant in the operand of 8347 the shift when shifted the appropriate number of bits. This 8348 shows that high-order bits are cleared by the right shift and 8349 low-order bits by left shifts. */ 8350 if (GET_CODE (XEXP (x, 1)) == CONST_INT 8351 && INTVAL (XEXP (x, 1)) >= 0 8352 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 8353 { 8354 enum machine_mode inner_mode = GET_MODE (x); 8355 unsigned int width = GET_MODE_BITSIZE (inner_mode); 8356 int count = INTVAL (XEXP (x, 1)); 8357 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode); 8358 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode); 8359 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask; 8360 unsigned HOST_WIDE_INT outer = 0; 8361 8362 if (mode_width > width) 8363 outer = (op_nonzero & nonzero & ~mode_mask); 8364 8365 if (code == LSHIFTRT) 8366 inner >>= count; 8367 else if (code == ASHIFTRT) 8368 { 8369 inner >>= count; 8370 8371 /* If the sign bit may have been nonzero before the shift, we 8372 need to mark all the places it could have been copied to 8373 by the shift as possibly nonzero. */ 8374 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count))) 8375 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count); 8376 } 8377 else if (code == ASHIFT) 8378 inner <<= count; 8379 else 8380 inner = ((inner << (count % width) 8381 | (inner >> (width - (count % width)))) & mode_mask); 8382 8383 nonzero &= (outer | inner); 8384 } 8385 break; 8386 8387 case FFS: 8388 /* This is at most the number of bits in the mode. */ 8389 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1; 8390 break; 8391 8392 case IF_THEN_ELSE: 8393 nonzero &= (nonzero_bits (XEXP (x, 1), mode) 8394 | nonzero_bits (XEXP (x, 2), mode)); 8395 break; 8396 8397 default: 8398 break; 8399 } 8400 8401 return nonzero; 8402} 8403 8404/* See the macro definition above. */ 8405#undef num_sign_bit_copies 8406 8407/* Return the number of bits at the high-order end of X that are known to 8408 be equal to the sign bit. X will be used in mode MODE; if MODE is 8409 VOIDmode, X will be used in its own mode. The returned value will always 8410 be between 1 and the number of bits in MODE. */ 8411 8412static unsigned int 8413num_sign_bit_copies (x, mode) 8414 rtx x; 8415 enum machine_mode mode; 8416{ 8417 enum rtx_code code = GET_CODE (x); 8418 unsigned int bitwidth; 8419 int num0, num1, result; 8420 unsigned HOST_WIDE_INT nonzero; 8421 rtx tem; 8422 8423 /* If we weren't given a mode, use the mode of X. If the mode is still 8424 VOIDmode, we don't know anything. Likewise if one of the modes is 8425 floating-point. */ 8426 8427 if (mode == VOIDmode) 8428 mode = GET_MODE (x); 8429 8430 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x))) 8431 return 1; 8432 8433 bitwidth = GET_MODE_BITSIZE (mode); 8434 8435 /* For a smaller object, just ignore the high bits. */ 8436 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x))) 8437 { 8438 num0 = num_sign_bit_copies (x, GET_MODE (x)); 8439 return MAX (1, 8440 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)); 8441 } 8442 8443 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x))) 8444 { 8445#ifndef WORD_REGISTER_OPERATIONS 8446 /* If this machine does not do all register operations on the entire 8447 register and MODE is wider than the mode of X, we can say nothing 8448 at all about the high-order bits. */ 8449 return 1; 8450#else 8451 /* Likewise on machines that do, if the mode of the object is smaller 8452 than a word and loads of that size don't sign extend, we can say 8453 nothing about the high order bits. */ 8454 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD 8455#ifdef LOAD_EXTEND_OP 8456 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND 8457#endif 8458 ) 8459 return 1; 8460#endif 8461 } 8462 8463 switch (code) 8464 { 8465 case REG: 8466 8467#if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) 8468 /* If pointers extend signed and this is a pointer in Pmode, say that 8469 all the bits above ptr_mode are known to be sign bit copies. */ 8470 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode 8471 && REG_POINTER (x)) 8472 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1; 8473#endif 8474 8475 if (reg_last_set_value[REGNO (x)] != 0 8476 && reg_last_set_mode[REGNO (x)] == mode 8477 && (reg_last_set_label[REGNO (x)] == label_tick 8478 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 8479 && REG_N_SETS (REGNO (x)) == 1 8480 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, 8481 REGNO (x)))) 8482 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) 8483 return reg_last_set_sign_bit_copies[REGNO (x)]; 8484 8485 tem = get_last_value (x); 8486 if (tem != 0) 8487 return num_sign_bit_copies (tem, mode); 8488 8489 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0 8490 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth) 8491 return reg_sign_bit_copies[REGNO (x)]; 8492 break; 8493 8494 case MEM: 8495#ifdef LOAD_EXTEND_OP 8496 /* Some RISC machines sign-extend all loads of smaller than a word. */ 8497 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND) 8498 return MAX (1, ((int) bitwidth 8499 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1)); 8500#endif 8501 break; 8502 8503 case CONST_INT: 8504 /* If the constant is negative, take its 1's complement and remask. 8505 Then see how many zero bits we have. */ 8506 nonzero = INTVAL (x) & GET_MODE_MASK (mode); 8507 if (bitwidth <= HOST_BITS_PER_WIDE_INT 8508 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8509 nonzero = (~nonzero) & GET_MODE_MASK (mode); 8510 8511 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); 8512 8513 case SUBREG: 8514 /* If this is a SUBREG for a promoted object that is sign-extended 8515 and we are looking at it in a wider mode, we know that at least the 8516 high-order bits are known to be sign bit copies. */ 8517 8518 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x)) 8519 { 8520 num0 = num_sign_bit_copies (SUBREG_REG (x), mode); 8521 return MAX ((int) bitwidth 8522 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1, 8523 num0); 8524 } 8525 8526 /* For a smaller object, just ignore the high bits. */ 8527 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))) 8528 { 8529 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode); 8530 return MAX (1, (num0 8531 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) 8532 - bitwidth))); 8533 } 8534 8535#ifdef WORD_REGISTER_OPERATIONS 8536#ifdef LOAD_EXTEND_OP 8537 /* For paradoxical SUBREGs on machines where all register operations 8538 affect the entire register, just look inside. Note that we are 8539 passing MODE to the recursive call, so the number of sign bit copies 8540 will remain relative to that mode, not the inner mode. */ 8541 8542 /* This works only if loads sign extend. Otherwise, if we get a 8543 reload for the inner part, it may be loaded from the stack, and 8544 then we lose all sign bit copies that existed before the store 8545 to the stack. */ 8546 8547 if ((GET_MODE_SIZE (GET_MODE (x)) 8548 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 8549 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND) 8550 return num_sign_bit_copies (SUBREG_REG (x), mode); 8551#endif 8552#endif 8553 break; 8554 8555 case SIGN_EXTRACT: 8556 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 8557 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1))); 8558 break; 8559 8560 case SIGN_EXTEND: 8561 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 8562 + num_sign_bit_copies (XEXP (x, 0), VOIDmode)); 8563 8564 case TRUNCATE: 8565 /* For a smaller object, just ignore the high bits. */ 8566 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode); 8567 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 8568 - bitwidth))); 8569 8570 case NOT: 8571 return num_sign_bit_copies (XEXP (x, 0), mode); 8572 8573 case ROTATE: case ROTATERT: 8574 /* If we are rotating left by a number of bits less than the number 8575 of sign bit copies, we can just subtract that amount from the 8576 number. */ 8577 if (GET_CODE (XEXP (x, 1)) == CONST_INT 8578 && INTVAL (XEXP (x, 1)) >= 0 8579 && INTVAL (XEXP (x, 1)) < (int) bitwidth) 8580 { 8581 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8582 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1)) 8583 : (int) bitwidth - INTVAL (XEXP (x, 1)))); 8584 } 8585 break; 8586 8587 case NEG: 8588 /* In general, this subtracts one sign bit copy. But if the value 8589 is known to be positive, the number of sign bit copies is the 8590 same as that of the input. Finally, if the input has just one bit 8591 that might be nonzero, all the bits are copies of the sign bit. */ 8592 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8593 if (bitwidth > HOST_BITS_PER_WIDE_INT) 8594 return num0 > 1 ? num0 - 1 : 1; 8595 8596 nonzero = nonzero_bits (XEXP (x, 0), mode); 8597 if (nonzero == 1) 8598 return bitwidth; 8599 8600 if (num0 > 1 8601 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero)) 8602 num0--; 8603 8604 return num0; 8605 8606 case IOR: case AND: case XOR: 8607 case SMIN: case SMAX: case UMIN: case UMAX: 8608 /* Logical operations will preserve the number of sign-bit copies. 8609 MIN and MAX operations always return one of the operands. */ 8610 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8611 num1 = num_sign_bit_copies (XEXP (x, 1), mode); 8612 return MIN (num0, num1); 8613 8614 case PLUS: case MINUS: 8615 /* For addition and subtraction, we can have a 1-bit carry. However, 8616 if we are subtracting 1 from a positive number, there will not 8617 be such a carry. Furthermore, if the positive number is known to 8618 be 0 or 1, we know the result is either -1 or 0. */ 8619 8620 if (code == PLUS && XEXP (x, 1) == constm1_rtx 8621 && bitwidth <= HOST_BITS_PER_WIDE_INT) 8622 { 8623 nonzero = nonzero_bits (XEXP (x, 0), mode); 8624 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0) 8625 return (nonzero == 1 || nonzero == 0 ? bitwidth 8626 : bitwidth - floor_log2 (nonzero) - 1); 8627 } 8628 8629 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8630 num1 = num_sign_bit_copies (XEXP (x, 1), mode); 8631 result = MAX (1, MIN (num0, num1) - 1); 8632 8633#ifdef POINTERS_EXTEND_UNSIGNED 8634 /* If pointers extend signed and this is an addition or subtraction 8635 to a pointer in Pmode, all the bits above ptr_mode are known to be 8636 sign bit copies. */ 8637 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode 8638 && (code == PLUS || code == MINUS) 8639 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0))) 8640 result = MAX ((int) (GET_MODE_BITSIZE (Pmode) 8641 - GET_MODE_BITSIZE (ptr_mode) + 1), 8642 result); 8643#endif 8644 return result; 8645 8646 case MULT: 8647 /* The number of bits of the product is the sum of the number of 8648 bits of both terms. However, unless one of the terms if known 8649 to be positive, we must allow for an additional bit since negating 8650 a negative number can remove one sign bit copy. */ 8651 8652 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8653 num1 = num_sign_bit_copies (XEXP (x, 1), mode); 8654 8655 result = bitwidth - (bitwidth - num0) - (bitwidth - num1); 8656 if (result > 0 8657 && (bitwidth > HOST_BITS_PER_WIDE_INT 8658 || (((nonzero_bits (XEXP (x, 0), mode) 8659 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8660 && ((nonzero_bits (XEXP (x, 1), mode) 8661 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)))) 8662 result--; 8663 8664 return MAX (1, result); 8665 8666 case UDIV: 8667 /* The result must be <= the first operand. If the first operand 8668 has the high bit set, we know nothing about the number of sign 8669 bit copies. */ 8670 if (bitwidth > HOST_BITS_PER_WIDE_INT) 8671 return 1; 8672 else if ((nonzero_bits (XEXP (x, 0), mode) 8673 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8674 return 1; 8675 else 8676 return num_sign_bit_copies (XEXP (x, 0), mode); 8677 8678 case UMOD: 8679 /* The result must be <= the second operand. */ 8680 return num_sign_bit_copies (XEXP (x, 1), mode); 8681 8682 case DIV: 8683 /* Similar to unsigned division, except that we have to worry about 8684 the case where the divisor is negative, in which case we have 8685 to add 1. */ 8686 result = num_sign_bit_copies (XEXP (x, 0), mode); 8687 if (result > 1 8688 && (bitwidth > HOST_BITS_PER_WIDE_INT 8689 || (nonzero_bits (XEXP (x, 1), mode) 8690 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) 8691 result--; 8692 8693 return result; 8694 8695 case MOD: 8696 result = num_sign_bit_copies (XEXP (x, 1), mode); 8697 if (result > 1 8698 && (bitwidth > HOST_BITS_PER_WIDE_INT 8699 || (nonzero_bits (XEXP (x, 1), mode) 8700 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) 8701 result--; 8702 8703 return result; 8704 8705 case ASHIFTRT: 8706 /* Shifts by a constant add to the number of bits equal to the 8707 sign bit. */ 8708 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8709 if (GET_CODE (XEXP (x, 1)) == CONST_INT 8710 && INTVAL (XEXP (x, 1)) > 0) 8711 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1))); 8712 8713 return num0; 8714 8715 case ASHIFT: 8716 /* Left shifts destroy copies. */ 8717 if (GET_CODE (XEXP (x, 1)) != CONST_INT 8718 || INTVAL (XEXP (x, 1)) < 0 8719 || INTVAL (XEXP (x, 1)) >= (int) bitwidth) 8720 return 1; 8721 8722 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8723 return MAX (1, num0 - INTVAL (XEXP (x, 1))); 8724 8725 case IF_THEN_ELSE: 8726 num0 = num_sign_bit_copies (XEXP (x, 1), mode); 8727 num1 = num_sign_bit_copies (XEXP (x, 2), mode); 8728 return MIN (num0, num1); 8729 8730 case EQ: case NE: case GE: case GT: case LE: case LT: 8731 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT: 8732 case GEU: case GTU: case LEU: case LTU: 8733 case UNORDERED: case ORDERED: 8734 /* If the constant is negative, take its 1's complement and remask. 8735 Then see how many zero bits we have. */ 8736 nonzero = STORE_FLAG_VALUE; 8737 if (bitwidth <= HOST_BITS_PER_WIDE_INT 8738 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8739 nonzero = (~nonzero) & GET_MODE_MASK (mode); 8740 8741 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); 8742 break; 8743 8744 default: 8745 break; 8746 } 8747 8748 /* If we haven't been able to figure it out by one of the above rules, 8749 see if some of the high-order bits are known to be zero. If so, 8750 count those bits and return one less than that amount. If we can't 8751 safely compute the mask for this mode, always return BITWIDTH. */ 8752 8753 if (bitwidth > HOST_BITS_PER_WIDE_INT) 8754 return 1; 8755 8756 nonzero = nonzero_bits (x, mode); 8757 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) 8758 ? 1 : bitwidth - floor_log2 (nonzero) - 1); 8759} 8760 8761/* Return the number of "extended" bits there are in X, when interpreted 8762 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For 8763 unsigned quantities, this is the number of high-order zero bits. 8764 For signed quantities, this is the number of copies of the sign bit 8765 minus 1. In both case, this function returns the number of "spare" 8766 bits. For example, if two quantities for which this function returns 8767 at least 1 are added, the addition is known not to overflow. 8768 8769 This function will always return 0 unless called during combine, which 8770 implies that it must be called from a define_split. */ 8771 8772unsigned int 8773extended_count (x, mode, unsignedp) 8774 rtx x; 8775 enum machine_mode mode; 8776 int unsignedp; 8777{ 8778 if (nonzero_sign_valid == 0) 8779 return 0; 8780 8781 return (unsignedp 8782 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 8783 ? (GET_MODE_BITSIZE (mode) - 1 8784 - floor_log2 (nonzero_bits (x, mode))) 8785 : 0) 8786 : num_sign_bit_copies (x, mode) - 1); 8787} 8788 8789/* This function is called from `simplify_shift_const' to merge two 8790 outer operations. Specifically, we have already found that we need 8791 to perform operation *POP0 with constant *PCONST0 at the outermost 8792 position. We would now like to also perform OP1 with constant CONST1 8793 (with *POP0 being done last). 8794 8795 Return 1 if we can do the operation and update *POP0 and *PCONST0 with 8796 the resulting operation. *PCOMP_P is set to 1 if we would need to 8797 complement the innermost operand, otherwise it is unchanged. 8798 8799 MODE is the mode in which the operation will be done. No bits outside 8800 the width of this mode matter. It is assumed that the width of this mode 8801 is smaller than or equal to HOST_BITS_PER_WIDE_INT. 8802 8803 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS, 8804 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper 8805 result is simply *PCONST0. 8806 8807 If the resulting operation cannot be expressed as one operation, we 8808 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ 8809 8810static int 8811merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p) 8812 enum rtx_code *pop0; 8813 HOST_WIDE_INT *pconst0; 8814 enum rtx_code op1; 8815 HOST_WIDE_INT const1; 8816 enum machine_mode mode; 8817 int *pcomp_p; 8818{ 8819 enum rtx_code op0 = *pop0; 8820 HOST_WIDE_INT const0 = *pconst0; 8821 8822 const0 &= GET_MODE_MASK (mode); 8823 const1 &= GET_MODE_MASK (mode); 8824 8825 /* If OP0 is an AND, clear unimportant bits in CONST1. */ 8826 if (op0 == AND) 8827 const1 &= const0; 8828 8829 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or 8830 if OP0 is SET. */ 8831 8832 if (op1 == NIL || op0 == SET) 8833 return 1; 8834 8835 else if (op0 == NIL) 8836 op0 = op1, const0 = const1; 8837 8838 else if (op0 == op1) 8839 { 8840 switch (op0) 8841 { 8842 case AND: 8843 const0 &= const1; 8844 break; 8845 case IOR: 8846 const0 |= const1; 8847 break; 8848 case XOR: 8849 const0 ^= const1; 8850 break; 8851 case PLUS: 8852 const0 += const1; 8853 break; 8854 case NEG: 8855 op0 = NIL; 8856 break; 8857 default: 8858 break; 8859 } 8860 } 8861 8862 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ 8863 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) 8864 return 0; 8865 8866 /* If the two constants aren't the same, we can't do anything. The 8867 remaining six cases can all be done. */ 8868 else if (const0 != const1) 8869 return 0; 8870 8871 else 8872 switch (op0) 8873 { 8874 case IOR: 8875 if (op1 == AND) 8876 /* (a & b) | b == b */ 8877 op0 = SET; 8878 else /* op1 == XOR */ 8879 /* (a ^ b) | b == a | b */ 8880 {;} 8881 break; 8882 8883 case XOR: 8884 if (op1 == AND) 8885 /* (a & b) ^ b == (~a) & b */ 8886 op0 = AND, *pcomp_p = 1; 8887 else /* op1 == IOR */ 8888 /* (a | b) ^ b == a & ~b */ 8889 op0 = AND, *pconst0 = ~const0; 8890 break; 8891 8892 case AND: 8893 if (op1 == IOR) 8894 /* (a | b) & b == b */ 8895 op0 = SET; 8896 else /* op1 == XOR */ 8897 /* (a ^ b) & b) == (~a) & b */ 8898 *pcomp_p = 1; 8899 break; 8900 default: 8901 break; 8902 } 8903 8904 /* Check for NO-OP cases. */ 8905 const0 &= GET_MODE_MASK (mode); 8906 if (const0 == 0 8907 && (op0 == IOR || op0 == XOR || op0 == PLUS)) 8908 op0 = NIL; 8909 else if (const0 == 0 && op0 == AND) 8910 op0 = SET; 8911 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) 8912 && op0 == AND) 8913 op0 = NIL; 8914 8915 /* ??? Slightly redundant with the above mask, but not entirely. 8916 Moving this above means we'd have to sign-extend the mode mask 8917 for the final test. */ 8918 const0 = trunc_int_for_mode (const0, mode); 8919 8920 *pop0 = op0; 8921 *pconst0 = const0; 8922 8923 return 1; 8924} 8925 8926/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. 8927 The result of the shift is RESULT_MODE. X, if non-zero, is an expression 8928 that we started with. 8929 8930 The shift is normally computed in the widest mode we find in VAROP, as 8931 long as it isn't a different number of words than RESULT_MODE. Exceptions 8932 are ASHIFTRT and ROTATE, which are always done in their original mode, */ 8933 8934static rtx 8935simplify_shift_const (x, code, result_mode, varop, orig_count) 8936 rtx x; 8937 enum rtx_code code; 8938 enum machine_mode result_mode; 8939 rtx varop; 8940 int orig_count; 8941{ 8942 enum rtx_code orig_code = code; 8943 unsigned int count; 8944 int signed_count; 8945 enum machine_mode mode = result_mode; 8946 enum machine_mode shift_mode, tmode; 8947 unsigned int mode_words 8948 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; 8949 /* We form (outer_op (code varop count) (outer_const)). */ 8950 enum rtx_code outer_op = NIL; 8951 HOST_WIDE_INT outer_const = 0; 8952 rtx const_rtx; 8953 int complement_p = 0; 8954 rtx new; 8955 8956 /* Make sure and truncate the "natural" shift on the way in. We don't 8957 want to do this inside the loop as it makes it more difficult to 8958 combine shifts. */ 8959#ifdef SHIFT_COUNT_TRUNCATED 8960 if (SHIFT_COUNT_TRUNCATED) 8961 orig_count &= GET_MODE_BITSIZE (mode) - 1; 8962#endif 8963 8964 /* If we were given an invalid count, don't do anything except exactly 8965 what was requested. */ 8966 8967 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode)) 8968 { 8969 if (x) 8970 return x; 8971 8972 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count)); 8973 } 8974 8975 count = orig_count; 8976 8977 /* Unless one of the branches of the `if' in this loop does a `continue', 8978 we will `break' the loop after the `if'. */ 8979 8980 while (count != 0) 8981 { 8982 /* If we have an operand of (clobber (const_int 0)), just return that 8983 value. */ 8984 if (GET_CODE (varop) == CLOBBER) 8985 return varop; 8986 8987 /* If we discovered we had to complement VAROP, leave. Making a NOT 8988 here would cause an infinite loop. */ 8989 if (complement_p) 8990 break; 8991 8992 /* Convert ROTATERT to ROTATE. */ 8993 if (code == ROTATERT) 8994 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count; 8995 8996 /* We need to determine what mode we will do the shift in. If the 8997 shift is a right shift or a ROTATE, we must always do it in the mode 8998 it was originally done in. Otherwise, we can do it in MODE, the 8999 widest mode encountered. */ 9000 shift_mode 9001 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE 9002 ? result_mode : mode); 9003 9004 /* Handle cases where the count is greater than the size of the mode 9005 minus 1. For ASHIFT, use the size minus one as the count (this can 9006 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, 9007 take the count modulo the size. For other shifts, the result is 9008 zero. 9009 9010 Since these shifts are being produced by the compiler by combining 9011 multiple operations, each of which are defined, we know what the 9012 result is supposed to be. */ 9013 9014 if (count > GET_MODE_BITSIZE (shift_mode) - 1) 9015 { 9016 if (code == ASHIFTRT) 9017 count = GET_MODE_BITSIZE (shift_mode) - 1; 9018 else if (code == ROTATE || code == ROTATERT) 9019 count %= GET_MODE_BITSIZE (shift_mode); 9020 else 9021 { 9022 /* We can't simply return zero because there may be an 9023 outer op. */ 9024 varop = const0_rtx; 9025 count = 0; 9026 break; 9027 } 9028 } 9029 9030 /* An arithmetic right shift of a quantity known to be -1 or 0 9031 is a no-op. */ 9032 if (code == ASHIFTRT 9033 && (num_sign_bit_copies (varop, shift_mode) 9034 == GET_MODE_BITSIZE (shift_mode))) 9035 { 9036 count = 0; 9037 break; 9038 } 9039 9040 /* If we are doing an arithmetic right shift and discarding all but 9041 the sign bit copies, this is equivalent to doing a shift by the 9042 bitsize minus one. Convert it into that shift because it will often 9043 allow other simplifications. */ 9044 9045 if (code == ASHIFTRT 9046 && (count + num_sign_bit_copies (varop, shift_mode) 9047 >= GET_MODE_BITSIZE (shift_mode))) 9048 count = GET_MODE_BITSIZE (shift_mode) - 1; 9049 9050 /* We simplify the tests below and elsewhere by converting 9051 ASHIFTRT to LSHIFTRT if we know the sign bit is clear. 9052 `make_compound_operation' will convert it to a ASHIFTRT for 9053 those machines (such as VAX) that don't have a LSHIFTRT. */ 9054 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT 9055 && code == ASHIFTRT 9056 && ((nonzero_bits (varop, shift_mode) 9057 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1))) 9058 == 0)) 9059 code = LSHIFTRT; 9060 9061 switch (GET_CODE (varop)) 9062 { 9063 case SIGN_EXTEND: 9064 case ZERO_EXTEND: 9065 case SIGN_EXTRACT: 9066 case ZERO_EXTRACT: 9067 new = expand_compound_operation (varop); 9068 if (new != varop) 9069 { 9070 varop = new; 9071 continue; 9072 } 9073 break; 9074 9075 case MEM: 9076 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH 9077 minus the width of a smaller mode, we can do this with a 9078 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ 9079 if ((code == ASHIFTRT || code == LSHIFTRT) 9080 && ! mode_dependent_address_p (XEXP (varop, 0)) 9081 && ! MEM_VOLATILE_P (varop) 9082 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 9083 MODE_INT, 1)) != BLKmode) 9084 { 9085 new = adjust_address_nv (varop, tmode, 9086 BYTES_BIG_ENDIAN ? 0 9087 : count / BITS_PER_UNIT); 9088 9089 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND 9090 : ZERO_EXTEND, mode, new); 9091 count = 0; 9092 continue; 9093 } 9094 break; 9095 9096 case USE: 9097 /* Similar to the case above, except that we can only do this if 9098 the resulting mode is the same as that of the underlying 9099 MEM and adjust the address depending on the *bits* endianness 9100 because of the way that bit-field extract insns are defined. */ 9101 if ((code == ASHIFTRT || code == LSHIFTRT) 9102 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 9103 MODE_INT, 1)) != BLKmode 9104 && tmode == GET_MODE (XEXP (varop, 0))) 9105 { 9106 if (BITS_BIG_ENDIAN) 9107 new = XEXP (varop, 0); 9108 else 9109 { 9110 new = copy_rtx (XEXP (varop, 0)); 9111 SUBST (XEXP (new, 0), 9112 plus_constant (XEXP (new, 0), 9113 count / BITS_PER_UNIT)); 9114 } 9115 9116 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND 9117 : ZERO_EXTEND, mode, new); 9118 count = 0; 9119 continue; 9120 } 9121 break; 9122 9123 case SUBREG: 9124 /* If VAROP is a SUBREG, strip it as long as the inner operand has 9125 the same number of words as what we've seen so far. Then store 9126 the widest mode in MODE. */ 9127 if (subreg_lowpart_p (varop) 9128 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 9129 > GET_MODE_SIZE (GET_MODE (varop))) 9130 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 9131 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 9132 == mode_words)) 9133 { 9134 varop = SUBREG_REG (varop); 9135 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) 9136 mode = GET_MODE (varop); 9137 continue; 9138 } 9139 break; 9140 9141 case MULT: 9142 /* Some machines use MULT instead of ASHIFT because MULT 9143 is cheaper. But it is still better on those machines to 9144 merge two shifts into one. */ 9145 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 9146 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) 9147 { 9148 varop 9149 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0), 9150 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1))))); 9151 continue; 9152 } 9153 break; 9154 9155 case UDIV: 9156 /* Similar, for when divides are cheaper. */ 9157 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 9158 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) 9159 { 9160 varop 9161 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0), 9162 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1))))); 9163 continue; 9164 } 9165 break; 9166 9167 case ASHIFTRT: 9168 /* If we are extracting just the sign bit of an arithmetic 9169 right shift, that shift is not needed. However, the sign 9170 bit of a wider mode may be different from what would be 9171 interpreted as the sign bit in a narrower mode, so, if 9172 the result is narrower, don't discard the shift. */ 9173 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 9174 && (GET_MODE_BITSIZE (result_mode) 9175 >= GET_MODE_BITSIZE (GET_MODE (varop)))) 9176 { 9177 varop = XEXP (varop, 0); 9178 continue; 9179 } 9180 9181 /* ... fall through ... */ 9182 9183 case LSHIFTRT: 9184 case ASHIFT: 9185 case ROTATE: 9186 /* Here we have two nested shifts. The result is usually the 9187 AND of a new shift with a mask. We compute the result below. */ 9188 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 9189 && INTVAL (XEXP (varop, 1)) >= 0 9190 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop)) 9191 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 9192 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 9193 { 9194 enum rtx_code first_code = GET_CODE (varop); 9195 unsigned int first_count = INTVAL (XEXP (varop, 1)); 9196 unsigned HOST_WIDE_INT mask; 9197 rtx mask_rtx; 9198 9199 /* We have one common special case. We can't do any merging if 9200 the inner code is an ASHIFTRT of a smaller mode. However, if 9201 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) 9202 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), 9203 we can convert it to 9204 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1). 9205 This simplifies certain SIGN_EXTEND operations. */ 9206 if (code == ASHIFT && first_code == ASHIFTRT 9207 && (GET_MODE_BITSIZE (result_mode) 9208 - GET_MODE_BITSIZE (GET_MODE (varop))) == count) 9209 { 9210 /* C3 has the low-order C1 bits zero. */ 9211 9212 mask = (GET_MODE_MASK (mode) 9213 & ~(((HOST_WIDE_INT) 1 << first_count) - 1)); 9214 9215 varop = simplify_and_const_int (NULL_RTX, result_mode, 9216 XEXP (varop, 0), mask); 9217 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, 9218 varop, count); 9219 count = first_count; 9220 code = ASHIFTRT; 9221 continue; 9222 } 9223 9224 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more 9225 than C1 high-order bits equal to the sign bit, we can convert 9226 this to either an ASHIFT or a ASHIFTRT depending on the 9227 two counts. 9228 9229 We cannot do this if VAROP's mode is not SHIFT_MODE. */ 9230 9231 if (code == ASHIFTRT && first_code == ASHIFT 9232 && GET_MODE (varop) == shift_mode 9233 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) 9234 > first_count)) 9235 { 9236 varop = XEXP (varop, 0); 9237 9238 signed_count = count - first_count; 9239 if (signed_count < 0) 9240 count = -signed_count, code = ASHIFT; 9241 else 9242 count = signed_count; 9243 9244 continue; 9245 } 9246 9247 /* There are some cases we can't do. If CODE is ASHIFTRT, 9248 we can only do this if FIRST_CODE is also ASHIFTRT. 9249 9250 We can't do the case when CODE is ROTATE and FIRST_CODE is 9251 ASHIFTRT. 9252 9253 If the mode of this shift is not the mode of the outer shift, 9254 we can't do this if either shift is a right shift or ROTATE. 9255 9256 Finally, we can't do any of these if the mode is too wide 9257 unless the codes are the same. 9258 9259 Handle the case where the shift codes are the same 9260 first. */ 9261 9262 if (code == first_code) 9263 { 9264 if (GET_MODE (varop) != result_mode 9265 && (code == ASHIFTRT || code == LSHIFTRT 9266 || code == ROTATE)) 9267 break; 9268 9269 count += first_count; 9270 varop = XEXP (varop, 0); 9271 continue; 9272 } 9273 9274 if (code == ASHIFTRT 9275 || (code == ROTATE && first_code == ASHIFTRT) 9276 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 9277 || (GET_MODE (varop) != result_mode 9278 && (first_code == ASHIFTRT || first_code == LSHIFTRT 9279 || first_code == ROTATE 9280 || code == ROTATE))) 9281 break; 9282 9283 /* To compute the mask to apply after the shift, shift the 9284 nonzero bits of the inner shift the same way the 9285 outer shift will. */ 9286 9287 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop))); 9288 9289 mask_rtx 9290 = simplify_binary_operation (code, result_mode, mask_rtx, 9291 GEN_INT (count)); 9292 9293 /* Give up if we can't compute an outer operation to use. */ 9294 if (mask_rtx == 0 9295 || GET_CODE (mask_rtx) != CONST_INT 9296 || ! merge_outer_ops (&outer_op, &outer_const, AND, 9297 INTVAL (mask_rtx), 9298 result_mode, &complement_p)) 9299 break; 9300 9301 /* If the shifts are in the same direction, we add the 9302 counts. Otherwise, we subtract them. */ 9303 signed_count = count; 9304 if ((code == ASHIFTRT || code == LSHIFTRT) 9305 == (first_code == ASHIFTRT || first_code == LSHIFTRT)) 9306 signed_count += first_count; 9307 else 9308 signed_count -= first_count; 9309 9310 /* If COUNT is positive, the new shift is usually CODE, 9311 except for the two exceptions below, in which case it is 9312 FIRST_CODE. If the count is negative, FIRST_CODE should 9313 always be used */ 9314 if (signed_count > 0 9315 && ((first_code == ROTATE && code == ASHIFT) 9316 || (first_code == ASHIFTRT && code == LSHIFTRT))) 9317 code = first_code, count = signed_count; 9318 else if (signed_count < 0) 9319 code = first_code, count = -signed_count; 9320 else 9321 count = signed_count; 9322 9323 varop = XEXP (varop, 0); 9324 continue; 9325 } 9326 9327 /* If we have (A << B << C) for any shift, we can convert this to 9328 (A << C << B). This wins if A is a constant. Only try this if 9329 B is not a constant. */ 9330 9331 else if (GET_CODE (varop) == code 9332 && GET_CODE (XEXP (varop, 1)) != CONST_INT 9333 && 0 != (new 9334 = simplify_binary_operation (code, mode, 9335 XEXP (varop, 0), 9336 GEN_INT (count)))) 9337 { 9338 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1)); 9339 count = 0; 9340 continue; 9341 } 9342 break; 9343 9344 case NOT: 9345 /* Make this fit the case below. */ 9346 varop = gen_rtx_XOR (mode, XEXP (varop, 0), 9347 GEN_INT (GET_MODE_MASK (mode))); 9348 continue; 9349 9350 case IOR: 9351 case AND: 9352 case XOR: 9353 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) 9354 with C the size of VAROP - 1 and the shift is logical if 9355 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 9356 we have an (le X 0) operation. If we have an arithmetic shift 9357 and STORE_FLAG_VALUE is 1 or we have a logical shift with 9358 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ 9359 9360 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS 9361 && XEXP (XEXP (varop, 0), 1) == constm1_rtx 9362 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 9363 && (code == LSHIFTRT || code == ASHIFTRT) 9364 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 9365 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 9366 { 9367 count = 0; 9368 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1), 9369 const0_rtx); 9370 9371 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 9372 varop = gen_rtx_NEG (GET_MODE (varop), varop); 9373 9374 continue; 9375 } 9376 9377 /* If we have (shift (logical)), move the logical to the outside 9378 to allow it to possibly combine with another logical and the 9379 shift to combine with another shift. This also canonicalizes to 9380 what a ZERO_EXTRACT looks like. Also, some machines have 9381 (and (shift)) insns. */ 9382 9383 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 9384 && (new = simplify_binary_operation (code, result_mode, 9385 XEXP (varop, 1), 9386 GEN_INT (count))) != 0 9387 && GET_CODE (new) == CONST_INT 9388 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), 9389 INTVAL (new), result_mode, &complement_p)) 9390 { 9391 varop = XEXP (varop, 0); 9392 continue; 9393 } 9394 9395 /* If we can't do that, try to simplify the shift in each arm of the 9396 logical expression, make a new logical expression, and apply 9397 the inverse distributive law. */ 9398 { 9399 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, 9400 XEXP (varop, 0), count); 9401 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, 9402 XEXP (varop, 1), count); 9403 9404 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs); 9405 varop = apply_distributive_law (varop); 9406 9407 count = 0; 9408 } 9409 break; 9410 9411 case EQ: 9412 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE 9413 says that the sign bit can be tested, FOO has mode MODE, C is 9414 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit 9415 that may be nonzero. */ 9416 if (code == LSHIFTRT 9417 && XEXP (varop, 1) == const0_rtx 9418 && GET_MODE (XEXP (varop, 0)) == result_mode 9419 && count == GET_MODE_BITSIZE (result_mode) - 1 9420 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 9421 && ((STORE_FLAG_VALUE 9422 & ((HOST_WIDE_INT) 1 9423 < (GET_MODE_BITSIZE (result_mode) - 1)))) 9424 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 9425 && merge_outer_ops (&outer_op, &outer_const, XOR, 9426 (HOST_WIDE_INT) 1, result_mode, 9427 &complement_p)) 9428 { 9429 varop = XEXP (varop, 0); 9430 count = 0; 9431 continue; 9432 } 9433 break; 9434 9435 case NEG: 9436 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less 9437 than the number of bits in the mode is equivalent to A. */ 9438 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 9439 && nonzero_bits (XEXP (varop, 0), result_mode) == 1) 9440 { 9441 varop = XEXP (varop, 0); 9442 count = 0; 9443 continue; 9444 } 9445 9446 /* NEG commutes with ASHIFT since it is multiplication. Move the 9447 NEG outside to allow shifts to combine. */ 9448 if (code == ASHIFT 9449 && merge_outer_ops (&outer_op, &outer_const, NEG, 9450 (HOST_WIDE_INT) 0, result_mode, 9451 &complement_p)) 9452 { 9453 varop = XEXP (varop, 0); 9454 continue; 9455 } 9456 break; 9457 9458 case PLUS: 9459 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C 9460 is one less than the number of bits in the mode is 9461 equivalent to (xor A 1). */ 9462 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 9463 && XEXP (varop, 1) == constm1_rtx 9464 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 9465 && merge_outer_ops (&outer_op, &outer_const, XOR, 9466 (HOST_WIDE_INT) 1, result_mode, 9467 &complement_p)) 9468 { 9469 count = 0; 9470 varop = XEXP (varop, 0); 9471 continue; 9472 } 9473 9474 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits 9475 that might be nonzero in BAR are those being shifted out and those 9476 bits are known zero in FOO, we can replace the PLUS with FOO. 9477 Similarly in the other operand order. This code occurs when 9478 we are computing the size of a variable-size array. */ 9479 9480 if ((code == ASHIFTRT || code == LSHIFTRT) 9481 && count < HOST_BITS_PER_WIDE_INT 9482 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 9483 && (nonzero_bits (XEXP (varop, 1), result_mode) 9484 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) 9485 { 9486 varop = XEXP (varop, 0); 9487 continue; 9488 } 9489 else if ((code == ASHIFTRT || code == LSHIFTRT) 9490 && count < HOST_BITS_PER_WIDE_INT 9491 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 9492 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 9493 >> count) 9494 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 9495 & nonzero_bits (XEXP (varop, 1), 9496 result_mode))) 9497 { 9498 varop = XEXP (varop, 1); 9499 continue; 9500 } 9501 9502 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ 9503 if (code == ASHIFT 9504 && GET_CODE (XEXP (varop, 1)) == CONST_INT 9505 && (new = simplify_binary_operation (ASHIFT, result_mode, 9506 XEXP (varop, 1), 9507 GEN_INT (count))) != 0 9508 && GET_CODE (new) == CONST_INT 9509 && merge_outer_ops (&outer_op, &outer_const, PLUS, 9510 INTVAL (new), result_mode, &complement_p)) 9511 { 9512 varop = XEXP (varop, 0); 9513 continue; 9514 } 9515 break; 9516 9517 case MINUS: 9518 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) 9519 with C the size of VAROP - 1 and the shift is logical if 9520 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 9521 we have a (gt X 0) operation. If the shift is arithmetic with 9522 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, 9523 we have a (neg (gt X 0)) operation. */ 9524 9525 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 9526 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT 9527 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 9528 && (code == LSHIFTRT || code == ASHIFTRT) 9529 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT 9530 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count 9531 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 9532 { 9533 count = 0; 9534 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1), 9535 const0_rtx); 9536 9537 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 9538 varop = gen_rtx_NEG (GET_MODE (varop), varop); 9539 9540 continue; 9541 } 9542 break; 9543 9544 case TRUNCATE: 9545 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) 9546 if the truncate does not affect the value. */ 9547 if (code == LSHIFTRT 9548 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT 9549 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT 9550 && (INTVAL (XEXP (XEXP (varop, 0), 1)) 9551 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0))) 9552 - GET_MODE_BITSIZE (GET_MODE (varop))))) 9553 { 9554 rtx varop_inner = XEXP (varop, 0); 9555 9556 varop_inner 9557 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner), 9558 XEXP (varop_inner, 0), 9559 GEN_INT 9560 (count + INTVAL (XEXP (varop_inner, 1)))); 9561 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner); 9562 count = 0; 9563 continue; 9564 } 9565 break; 9566 9567 default: 9568 break; 9569 } 9570 9571 break; 9572 } 9573 9574 /* We need to determine what mode to do the shift in. If the shift is 9575 a right shift or ROTATE, we must always do it in the mode it was 9576 originally done in. Otherwise, we can do it in MODE, the widest mode 9577 encountered. The code we care about is that of the shift that will 9578 actually be done, not the shift that was originally requested. */ 9579 shift_mode 9580 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE 9581 ? result_mode : mode); 9582 9583 /* We have now finished analyzing the shift. The result should be 9584 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If 9585 OUTER_OP is non-NIL, it is an operation that needs to be applied 9586 to the result of the shift. OUTER_CONST is the relevant constant, 9587 but we must turn off all bits turned off in the shift. 9588 9589 If we were passed a value for X, see if we can use any pieces of 9590 it. If not, make new rtx. */ 9591 9592 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2' 9593 && GET_CODE (XEXP (x, 1)) == CONST_INT 9594 && INTVAL (XEXP (x, 1)) == count) 9595 const_rtx = XEXP (x, 1); 9596 else 9597 const_rtx = GEN_INT (count); 9598 9599 if (x && GET_CODE (XEXP (x, 0)) == SUBREG 9600 && GET_MODE (XEXP (x, 0)) == shift_mode 9601 && SUBREG_REG (XEXP (x, 0)) == varop) 9602 varop = XEXP (x, 0); 9603 else if (GET_MODE (varop) != shift_mode) 9604 varop = gen_lowpart_for_combine (shift_mode, varop); 9605 9606 /* If we can't make the SUBREG, try to return what we were given. */ 9607 if (GET_CODE (varop) == CLOBBER) 9608 return x ? x : varop; 9609 9610 new = simplify_binary_operation (code, shift_mode, varop, const_rtx); 9611 if (new != 0) 9612 x = new; 9613 else 9614 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx); 9615 9616 /* If we have an outer operation and we just made a shift, it is 9617 possible that we could have simplified the shift were it not 9618 for the outer operation. So try to do the simplification 9619 recursively. */ 9620 9621 if (outer_op != NIL && GET_CODE (x) == code 9622 && GET_CODE (XEXP (x, 1)) == CONST_INT) 9623 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0), 9624 INTVAL (XEXP (x, 1))); 9625 9626 /* If we were doing a LSHIFTRT in a wider mode than it was originally, 9627 turn off all the bits that the shift would have turned off. */ 9628 if (orig_code == LSHIFTRT && result_mode != shift_mode) 9629 x = simplify_and_const_int (NULL_RTX, shift_mode, x, 9630 GET_MODE_MASK (result_mode) >> orig_count); 9631 9632 /* Do the remainder of the processing in RESULT_MODE. */ 9633 x = gen_lowpart_for_combine (result_mode, x); 9634 9635 /* If COMPLEMENT_P is set, we have to complement X before doing the outer 9636 operation. */ 9637 if (complement_p) 9638 x =simplify_gen_unary (NOT, result_mode, x, result_mode); 9639 9640 if (outer_op != NIL) 9641 { 9642 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT) 9643 outer_const = trunc_int_for_mode (outer_const, result_mode); 9644 9645 if (outer_op == AND) 9646 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); 9647 else if (outer_op == SET) 9648 /* This means that we have determined that the result is 9649 equivalent to a constant. This should be rare. */ 9650 x = GEN_INT (outer_const); 9651 else if (GET_RTX_CLASS (outer_op) == '1') 9652 x = simplify_gen_unary (outer_op, result_mode, x, result_mode); 9653 else 9654 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const)); 9655 } 9656 9657 return x; 9658} 9659 9660/* Like recog, but we receive the address of a pointer to a new pattern. 9661 We try to match the rtx that the pointer points to. 9662 If that fails, we may try to modify or replace the pattern, 9663 storing the replacement into the same pointer object. 9664 9665 Modifications include deletion or addition of CLOBBERs. 9666 9667 PNOTES is a pointer to a location where any REG_UNUSED notes added for 9668 the CLOBBERs are placed. 9669 9670 The value is the final insn code from the pattern ultimately matched, 9671 or -1. */ 9672 9673static int 9674recog_for_combine (pnewpat, insn, pnotes) 9675 rtx *pnewpat; 9676 rtx insn; 9677 rtx *pnotes; 9678{ 9679 rtx pat = *pnewpat; 9680 int insn_code_number; 9681 int num_clobbers_to_add = 0; 9682 int i; 9683 rtx notes = 0; 9684 rtx dummy_insn; 9685 9686 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER 9687 we use to indicate that something didn't match. If we find such a 9688 thing, force rejection. */ 9689 if (GET_CODE (pat) == PARALLEL) 9690 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) 9691 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER 9692 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) 9693 return -1; 9694 9695 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy 9696 instruction for pattern recognition. */ 9697 dummy_insn = shallow_copy_rtx (insn); 9698 PATTERN (dummy_insn) = pat; 9699 REG_NOTES (dummy_insn) = 0; 9700 9701 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add); 9702 9703 /* If it isn't, there is the possibility that we previously had an insn 9704 that clobbered some register as a side effect, but the combined 9705 insn doesn't need to do that. So try once more without the clobbers 9706 unless this represents an ASM insn. */ 9707 9708 if (insn_code_number < 0 && ! check_asm_operands (pat) 9709 && GET_CODE (pat) == PARALLEL) 9710 { 9711 int pos; 9712 9713 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) 9714 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) 9715 { 9716 if (i != pos) 9717 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); 9718 pos++; 9719 } 9720 9721 SUBST_INT (XVECLEN (pat, 0), pos); 9722 9723 if (pos == 1) 9724 pat = XVECEXP (pat, 0, 0); 9725 9726 PATTERN (dummy_insn) = pat; 9727 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add); 9728 } 9729 9730 /* Recognize all noop sets, these will be killed by followup pass. */ 9731 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat)) 9732 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0; 9733 9734 /* If we had any clobbers to add, make a new pattern than contains 9735 them. Then check to make sure that all of them are dead. */ 9736 if (num_clobbers_to_add) 9737 { 9738 rtx newpat = gen_rtx_PARALLEL (VOIDmode, 9739 rtvec_alloc (GET_CODE (pat) == PARALLEL 9740 ? (XVECLEN (pat, 0) 9741 + num_clobbers_to_add) 9742 : num_clobbers_to_add + 1)); 9743 9744 if (GET_CODE (pat) == PARALLEL) 9745 for (i = 0; i < XVECLEN (pat, 0); i++) 9746 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); 9747 else 9748 XVECEXP (newpat, 0, 0) = pat; 9749 9750 add_clobbers (newpat, insn_code_number); 9751 9752 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; 9753 i < XVECLEN (newpat, 0); i++) 9754 { 9755 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG 9756 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) 9757 return -1; 9758 notes = gen_rtx_EXPR_LIST (REG_UNUSED, 9759 XEXP (XVECEXP (newpat, 0, i), 0), notes); 9760 } 9761 pat = newpat; 9762 } 9763 9764 *pnewpat = pat; 9765 *pnotes = notes; 9766 9767 return insn_code_number; 9768} 9769 9770/* Like gen_lowpart but for use by combine. In combine it is not possible 9771 to create any new pseudoregs. However, it is safe to create 9772 invalid memory addresses, because combine will try to recognize 9773 them and all they will do is make the combine attempt fail. 9774 9775 If for some reason this cannot do its job, an rtx 9776 (clobber (const_int 0)) is returned. 9777 An insn containing that will not be recognized. */ 9778 9779#undef gen_lowpart 9780 9781static rtx 9782gen_lowpart_for_combine (mode, x) 9783 enum machine_mode mode; 9784 rtx x; 9785{ 9786 rtx result; 9787 9788 if (GET_MODE (x) == mode) 9789 return x; 9790 9791 /* We can only support MODE being wider than a word if X is a 9792 constant integer or has a mode the same size. */ 9793 9794 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 9795 && ! ((GET_MODE (x) == VOIDmode 9796 && (GET_CODE (x) == CONST_INT 9797 || GET_CODE (x) == CONST_DOUBLE)) 9798 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode))) 9799 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 9800 9801 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart 9802 won't know what to do. So we will strip off the SUBREG here and 9803 process normally. */ 9804 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM) 9805 { 9806 x = SUBREG_REG (x); 9807 if (GET_MODE (x) == mode) 9808 return x; 9809 } 9810 9811 result = gen_lowpart_common (mode, x); 9812#ifdef CLASS_CANNOT_CHANGE_MODE 9813 if (result != 0 9814 && GET_CODE (result) == SUBREG 9815 && GET_CODE (SUBREG_REG (result)) == REG 9816 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER 9817 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result), 9818 GET_MODE (SUBREG_REG (result)))) 9819 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1; 9820#endif 9821 9822 if (result) 9823 return result; 9824 9825 if (GET_CODE (x) == MEM) 9826 { 9827 int offset = 0; 9828 9829 /* Refuse to work on a volatile memory ref or one with a mode-dependent 9830 address. */ 9831 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0))) 9832 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 9833 9834 /* If we want to refer to something bigger than the original memref, 9835 generate a perverse subreg instead. That will force a reload 9836 of the original memref X. */ 9837 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)) 9838 return gen_rtx_SUBREG (mode, x, 0); 9839 9840 if (WORDS_BIG_ENDIAN) 9841 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) 9842 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); 9843 9844 if (BYTES_BIG_ENDIAN) 9845 { 9846 /* Adjust the address so that the address-after-the-data is 9847 unchanged. */ 9848 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) 9849 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); 9850 } 9851 9852 return adjust_address_nv (x, mode, offset); 9853 } 9854 9855 /* If X is a comparison operator, rewrite it in a new mode. This 9856 probably won't match, but may allow further simplifications. */ 9857 else if (GET_RTX_CLASS (GET_CODE (x)) == '<') 9858 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1)); 9859 9860 /* If we couldn't simplify X any other way, just enclose it in a 9861 SUBREG. Normally, this SUBREG won't match, but some patterns may 9862 include an explicit SUBREG or we may simplify it further in combine. */ 9863 else 9864 { 9865 int offset = 0; 9866 rtx res; 9867 9868 offset = subreg_lowpart_offset (mode, GET_MODE (x)); 9869 res = simplify_gen_subreg (mode, x, GET_MODE (x), offset); 9870 if (res) 9871 return res; 9872 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 9873 } 9874} 9875 9876/* These routines make binary and unary operations by first seeing if they 9877 fold; if not, a new expression is allocated. */ 9878 9879static rtx 9880gen_binary (code, mode, op0, op1) 9881 enum rtx_code code; 9882 enum machine_mode mode; 9883 rtx op0, op1; 9884{ 9885 rtx result; 9886 rtx tem; 9887 9888 if (GET_RTX_CLASS (code) == 'c' 9889 && swap_commutative_operands_p (op0, op1)) 9890 tem = op0, op0 = op1, op1 = tem; 9891 9892 if (GET_RTX_CLASS (code) == '<') 9893 { 9894 enum machine_mode op_mode = GET_MODE (op0); 9895 9896 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get 9897 just (REL_OP X Y). */ 9898 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx) 9899 { 9900 op1 = XEXP (op0, 1); 9901 op0 = XEXP (op0, 0); 9902 op_mode = GET_MODE (op0); 9903 } 9904 9905 if (op_mode == VOIDmode) 9906 op_mode = GET_MODE (op1); 9907 result = simplify_relational_operation (code, op_mode, op0, op1); 9908 } 9909 else 9910 result = simplify_binary_operation (code, mode, op0, op1); 9911 9912 if (result) 9913 return result; 9914 9915 /* Put complex operands first and constants second. */ 9916 if (GET_RTX_CLASS (code) == 'c' 9917 && swap_commutative_operands_p (op0, op1)) 9918 return gen_rtx_fmt_ee (code, mode, op1, op0); 9919 9920 /* If we are turning off bits already known off in OP0, we need not do 9921 an AND. */ 9922 else if (code == AND && GET_CODE (op1) == CONST_INT 9923 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 9924 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0) 9925 return op0; 9926 9927 return gen_rtx_fmt_ee (code, mode, op0, op1); 9928} 9929 9930/* Simplify a comparison between *POP0 and *POP1 where CODE is the 9931 comparison code that will be tested. 9932 9933 The result is a possibly different comparison code to use. *POP0 and 9934 *POP1 may be updated. 9935 9936 It is possible that we might detect that a comparison is either always 9937 true or always false. However, we do not perform general constant 9938 folding in combine, so this knowledge isn't useful. Such tautologies 9939 should have been detected earlier. Hence we ignore all such cases. */ 9940 9941static enum rtx_code 9942simplify_comparison (code, pop0, pop1) 9943 enum rtx_code code; 9944 rtx *pop0; 9945 rtx *pop1; 9946{ 9947 rtx op0 = *pop0; 9948 rtx op1 = *pop1; 9949 rtx tem, tem1; 9950 int i; 9951 enum machine_mode mode, tmode; 9952 9953 /* Try a few ways of applying the same transformation to both operands. */ 9954 while (1) 9955 { 9956#ifndef WORD_REGISTER_OPERATIONS 9957 /* The test below this one won't handle SIGN_EXTENDs on these machines, 9958 so check specially. */ 9959 if (code != GTU && code != GEU && code != LTU && code != LEU 9960 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT 9961 && GET_CODE (XEXP (op0, 0)) == ASHIFT 9962 && GET_CODE (XEXP (op1, 0)) == ASHIFT 9963 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG 9964 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG 9965 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) 9966 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) 9967 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9968 && GET_CODE (XEXP (op1, 1)) == CONST_INT 9969 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 9970 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT 9971 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1)) 9972 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1)) 9973 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1)) 9974 && (INTVAL (XEXP (op0, 1)) 9975 == (GET_MODE_BITSIZE (GET_MODE (op0)) 9976 - (GET_MODE_BITSIZE 9977 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) 9978 { 9979 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); 9980 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); 9981 } 9982#endif 9983 9984 /* If both operands are the same constant shift, see if we can ignore the 9985 shift. We can if the shift is a rotate or if the bits shifted out of 9986 this shift are known to be zero for both inputs and if the type of 9987 comparison is compatible with the shift. */ 9988 if (GET_CODE (op0) == GET_CODE (op1) 9989 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 9990 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) 9991 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) 9992 && (code != GT && code != LT && code != GE && code != LE)) 9993 || (GET_CODE (op0) == ASHIFTRT 9994 && (code != GTU && code != LTU 9995 && code != GEU && code != LEU))) 9996 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9997 && INTVAL (XEXP (op0, 1)) >= 0 9998 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 9999 && XEXP (op0, 1) == XEXP (op1, 1)) 10000 { 10001 enum machine_mode mode = GET_MODE (op0); 10002 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 10003 int shift_count = INTVAL (XEXP (op0, 1)); 10004 10005 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) 10006 mask &= (mask >> shift_count) << shift_count; 10007 else if (GET_CODE (op0) == ASHIFT) 10008 mask = (mask & (mask << shift_count)) >> shift_count; 10009 10010 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0 10011 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0) 10012 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); 10013 else 10014 break; 10015 } 10016 10017 /* If both operands are AND's of a paradoxical SUBREG by constant, the 10018 SUBREGs are of the same mode, and, in both cases, the AND would 10019 be redundant if the comparison was done in the narrower mode, 10020 do the comparison in the narrower mode (e.g., we are AND'ing with 1 10021 and the operand's possibly nonzero bits are 0xffffff01; in that case 10022 if we only care about QImode, we don't need the AND). This case 10023 occurs if the output mode of an scc insn is not SImode and 10024 STORE_FLAG_VALUE == 1 (e.g., the 386). 10025 10026 Similarly, check for a case where the AND's are ZERO_EXTEND 10027 operations from some narrower mode even though a SUBREG is not 10028 present. */ 10029 10030 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND 10031 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10032 && GET_CODE (XEXP (op1, 1)) == CONST_INT) 10033 { 10034 rtx inner_op0 = XEXP (op0, 0); 10035 rtx inner_op1 = XEXP (op1, 0); 10036 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); 10037 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); 10038 int changed = 0; 10039 10040 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG 10041 && (GET_MODE_SIZE (GET_MODE (inner_op0)) 10042 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0)))) 10043 && (GET_MODE (SUBREG_REG (inner_op0)) 10044 == GET_MODE (SUBREG_REG (inner_op1))) 10045 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0))) 10046 <= HOST_BITS_PER_WIDE_INT) 10047 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), 10048 GET_MODE (SUBREG_REG (inner_op0))))) 10049 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), 10050 GET_MODE (SUBREG_REG (inner_op1)))))) 10051 { 10052 op0 = SUBREG_REG (inner_op0); 10053 op1 = SUBREG_REG (inner_op1); 10054 10055 /* The resulting comparison is always unsigned since we masked 10056 off the original sign bit. */ 10057 code = unsigned_condition (code); 10058 10059 changed = 1; 10060 } 10061 10062 else if (c0 == c1) 10063 for (tmode = GET_CLASS_NARROWEST_MODE 10064 (GET_MODE_CLASS (GET_MODE (op0))); 10065 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) 10066 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) 10067 { 10068 op0 = gen_lowpart_for_combine (tmode, inner_op0); 10069 op1 = gen_lowpart_for_combine (tmode, inner_op1); 10070 code = unsigned_condition (code); 10071 changed = 1; 10072 break; 10073 } 10074 10075 if (! changed) 10076 break; 10077 } 10078 10079 /* If both operands are NOT, we can strip off the outer operation 10080 and adjust the comparison code for swapped operands; similarly for 10081 NEG, except that this must be an equality comparison. */ 10082 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) 10083 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG 10084 && (code == EQ || code == NE))) 10085 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); 10086 10087 else 10088 break; 10089 } 10090 10091 /* If the first operand is a constant, swap the operands and adjust the 10092 comparison code appropriately, but don't do this if the second operand 10093 is already a constant integer. */ 10094 if (swap_commutative_operands_p (op0, op1)) 10095 { 10096 tem = op0, op0 = op1, op1 = tem; 10097 code = swap_condition (code); 10098 } 10099 10100 /* We now enter a loop during which we will try to simplify the comparison. 10101 For the most part, we only are concerned with comparisons with zero, 10102 but some things may really be comparisons with zero but not start 10103 out looking that way. */ 10104 10105 while (GET_CODE (op1) == CONST_INT) 10106 { 10107 enum machine_mode mode = GET_MODE (op0); 10108 unsigned int mode_width = GET_MODE_BITSIZE (mode); 10109 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 10110 int equality_comparison_p; 10111 int sign_bit_comparison_p; 10112 int unsigned_comparison_p; 10113 HOST_WIDE_INT const_op; 10114 10115 /* We only want to handle integral modes. This catches VOIDmode, 10116 CCmode, and the floating-point modes. An exception is that we 10117 can handle VOIDmode if OP0 is a COMPARE or a comparison 10118 operation. */ 10119 10120 if (GET_MODE_CLASS (mode) != MODE_INT 10121 && ! (mode == VOIDmode 10122 && (GET_CODE (op0) == COMPARE 10123 || GET_RTX_CLASS (GET_CODE (op0)) == '<'))) 10124 break; 10125 10126 /* Get the constant we are comparing against and turn off all bits 10127 not on in our mode. */ 10128 const_op = trunc_int_for_mode (INTVAL (op1), mode); 10129 op1 = GEN_INT (const_op); 10130 10131 /* If we are comparing against a constant power of two and the value 10132 being compared can only have that single bit nonzero (e.g., it was 10133 `and'ed with that bit), we can replace this with a comparison 10134 with zero. */ 10135 if (const_op 10136 && (code == EQ || code == NE || code == GE || code == GEU 10137 || code == LT || code == LTU) 10138 && mode_width <= HOST_BITS_PER_WIDE_INT 10139 && exact_log2 (const_op) >= 0 10140 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op) 10141 { 10142 code = (code == EQ || code == GE || code == GEU ? NE : EQ); 10143 op1 = const0_rtx, const_op = 0; 10144 } 10145 10146 /* Similarly, if we are comparing a value known to be either -1 or 10147 0 with -1, change it to the opposite comparison against zero. */ 10148 10149 if (const_op == -1 10150 && (code == EQ || code == NE || code == GT || code == LE 10151 || code == GEU || code == LTU) 10152 && num_sign_bit_copies (op0, mode) == mode_width) 10153 { 10154 code = (code == EQ || code == LE || code == GEU ? NE : EQ); 10155 op1 = const0_rtx, const_op = 0; 10156 } 10157 10158 /* Do some canonicalizations based on the comparison code. We prefer 10159 comparisons against zero and then prefer equality comparisons. 10160 If we can reduce the size of a constant, we will do that too. */ 10161 10162 switch (code) 10163 { 10164 case LT: 10165 /* < C is equivalent to <= (C - 1) */ 10166 if (const_op > 0) 10167 { 10168 const_op -= 1; 10169 op1 = GEN_INT (const_op); 10170 code = LE; 10171 /* ... fall through to LE case below. */ 10172 } 10173 else 10174 break; 10175 10176 case LE: 10177 /* <= C is equivalent to < (C + 1); we do this for C < 0 */ 10178 if (const_op < 0) 10179 { 10180 const_op += 1; 10181 op1 = GEN_INT (const_op); 10182 code = LT; 10183 } 10184 10185 /* If we are doing a <= 0 comparison on a value known to have 10186 a zero sign bit, we can replace this with == 0. */ 10187 else if (const_op == 0 10188 && mode_width <= HOST_BITS_PER_WIDE_INT 10189 && (nonzero_bits (op0, mode) 10190 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) 10191 code = EQ; 10192 break; 10193 10194 case GE: 10195 /* >= C is equivalent to > (C - 1). */ 10196 if (const_op > 0) 10197 { 10198 const_op -= 1; 10199 op1 = GEN_INT (const_op); 10200 code = GT; 10201 /* ... fall through to GT below. */ 10202 } 10203 else 10204 break; 10205 10206 case GT: 10207 /* > C is equivalent to >= (C + 1); we do this for C < 0. */ 10208 if (const_op < 0) 10209 { 10210 const_op += 1; 10211 op1 = GEN_INT (const_op); 10212 code = GE; 10213 } 10214 10215 /* If we are doing a > 0 comparison on a value known to have 10216 a zero sign bit, we can replace this with != 0. */ 10217 else if (const_op == 0 10218 && mode_width <= HOST_BITS_PER_WIDE_INT 10219 && (nonzero_bits (op0, mode) 10220 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) 10221 code = NE; 10222 break; 10223 10224 case LTU: 10225 /* < C is equivalent to <= (C - 1). */ 10226 if (const_op > 0) 10227 { 10228 const_op -= 1; 10229 op1 = GEN_INT (const_op); 10230 code = LEU; 10231 /* ... fall through ... */ 10232 } 10233 10234 /* (unsigned) < 0x80000000 is equivalent to >= 0. */ 10235 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 10236 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) 10237 { 10238 const_op = 0, op1 = const0_rtx; 10239 code = GE; 10240 break; 10241 } 10242 else 10243 break; 10244 10245 case LEU: 10246 /* unsigned <= 0 is equivalent to == 0 */ 10247 if (const_op == 0) 10248 code = EQ; 10249 10250 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ 10251 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 10252 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) 10253 { 10254 const_op = 0, op1 = const0_rtx; 10255 code = GE; 10256 } 10257 break; 10258 10259 case GEU: 10260 /* >= C is equivalent to < (C - 1). */ 10261 if (const_op > 1) 10262 { 10263 const_op -= 1; 10264 op1 = GEN_INT (const_op); 10265 code = GTU; 10266 /* ... fall through ... */ 10267 } 10268 10269 /* (unsigned) >= 0x80000000 is equivalent to < 0. */ 10270 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 10271 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) 10272 { 10273 const_op = 0, op1 = const0_rtx; 10274 code = LT; 10275 break; 10276 } 10277 else 10278 break; 10279 10280 case GTU: 10281 /* unsigned > 0 is equivalent to != 0 */ 10282 if (const_op == 0) 10283 code = NE; 10284 10285 /* (unsigned) > 0x7fffffff is equivalent to < 0. */ 10286 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 10287 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) 10288 { 10289 const_op = 0, op1 = const0_rtx; 10290 code = LT; 10291 } 10292 break; 10293 10294 default: 10295 break; 10296 } 10297 10298 /* Compute some predicates to simplify code below. */ 10299 10300 equality_comparison_p = (code == EQ || code == NE); 10301 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); 10302 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU 10303 || code == GEU); 10304 10305 /* If this is a sign bit comparison and we can do arithmetic in 10306 MODE, say that we will only be needing the sign bit of OP0. */ 10307 if (sign_bit_comparison_p 10308 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 10309 op0 = force_to_mode (op0, mode, 10310 ((HOST_WIDE_INT) 1 10311 << (GET_MODE_BITSIZE (mode) - 1)), 10312 NULL_RTX, 0); 10313 10314 /* Now try cases based on the opcode of OP0. If none of the cases 10315 does a "continue", we exit this loop immediately after the 10316 switch. */ 10317 10318 switch (GET_CODE (op0)) 10319 { 10320 case ZERO_EXTRACT: 10321 /* If we are extracting a single bit from a variable position in 10322 a constant that has only a single bit set and are comparing it 10323 with zero, we can convert this into an equality comparison 10324 between the position and the location of the single bit. */ 10325 10326 if (GET_CODE (XEXP (op0, 0)) == CONST_INT 10327 && XEXP (op0, 1) == const1_rtx 10328 && equality_comparison_p && const_op == 0 10329 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0) 10330 { 10331 if (BITS_BIG_ENDIAN) 10332 { 10333 enum machine_mode new_mode 10334 = mode_for_extraction (EP_extzv, 1); 10335 if (new_mode == MAX_MACHINE_MODE) 10336 i = BITS_PER_WORD - 1 - i; 10337 else 10338 { 10339 mode = new_mode; 10340 i = (GET_MODE_BITSIZE (mode) - 1 - i); 10341 } 10342 } 10343 10344 op0 = XEXP (op0, 2); 10345 op1 = GEN_INT (i); 10346 const_op = i; 10347 10348 /* Result is nonzero iff shift count is equal to I. */ 10349 code = reverse_condition (code); 10350 continue; 10351 } 10352 10353 /* ... fall through ... */ 10354 10355 case SIGN_EXTRACT: 10356 tem = expand_compound_operation (op0); 10357 if (tem != op0) 10358 { 10359 op0 = tem; 10360 continue; 10361 } 10362 break; 10363 10364 case NOT: 10365 /* If testing for equality, we can take the NOT of the constant. */ 10366 if (equality_comparison_p 10367 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) 10368 { 10369 op0 = XEXP (op0, 0); 10370 op1 = tem; 10371 continue; 10372 } 10373 10374 /* If just looking at the sign bit, reverse the sense of the 10375 comparison. */ 10376 if (sign_bit_comparison_p) 10377 { 10378 op0 = XEXP (op0, 0); 10379 code = (code == GE ? LT : GE); 10380 continue; 10381 } 10382 break; 10383 10384 case NEG: 10385 /* If testing for equality, we can take the NEG of the constant. */ 10386 if (equality_comparison_p 10387 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) 10388 { 10389 op0 = XEXP (op0, 0); 10390 op1 = tem; 10391 continue; 10392 } 10393 10394 /* The remaining cases only apply to comparisons with zero. */ 10395 if (const_op != 0) 10396 break; 10397 10398 /* When X is ABS or is known positive, 10399 (neg X) is < 0 if and only if X != 0. */ 10400 10401 if (sign_bit_comparison_p 10402 && (GET_CODE (XEXP (op0, 0)) == ABS 10403 || (mode_width <= HOST_BITS_PER_WIDE_INT 10404 && (nonzero_bits (XEXP (op0, 0), mode) 10405 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0))) 10406 { 10407 op0 = XEXP (op0, 0); 10408 code = (code == LT ? NE : EQ); 10409 continue; 10410 } 10411 10412 /* If we have NEG of something whose two high-order bits are the 10413 same, we know that "(-a) < 0" is equivalent to "a > 0". */ 10414 if (num_sign_bit_copies (op0, mode) >= 2) 10415 { 10416 op0 = XEXP (op0, 0); 10417 code = swap_condition (code); 10418 continue; 10419 } 10420 break; 10421 10422 case ROTATE: 10423 /* If we are testing equality and our count is a constant, we 10424 can perform the inverse operation on our RHS. */ 10425 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT 10426 && (tem = simplify_binary_operation (ROTATERT, mode, 10427 op1, XEXP (op0, 1))) != 0) 10428 { 10429 op0 = XEXP (op0, 0); 10430 op1 = tem; 10431 continue; 10432 } 10433 10434 /* If we are doing a < 0 or >= 0 comparison, it means we are testing 10435 a particular bit. Convert it to an AND of a constant of that 10436 bit. This will be converted into a ZERO_EXTRACT. */ 10437 if (const_op == 0 && sign_bit_comparison_p 10438 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10439 && mode_width <= HOST_BITS_PER_WIDE_INT) 10440 { 10441 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10442 ((HOST_WIDE_INT) 1 10443 << (mode_width - 1 10444 - INTVAL (XEXP (op0, 1))))); 10445 code = (code == LT ? NE : EQ); 10446 continue; 10447 } 10448 10449 /* Fall through. */ 10450 10451 case ABS: 10452 /* ABS is ignorable inside an equality comparison with zero. */ 10453 if (const_op == 0 && equality_comparison_p) 10454 { 10455 op0 = XEXP (op0, 0); 10456 continue; 10457 } 10458 break; 10459 10460 case SIGN_EXTEND: 10461 /* Can simplify (compare (zero/sign_extend FOO) CONST) 10462 to (compare FOO CONST) if CONST fits in FOO's mode and we 10463 are either testing inequality or have an unsigned comparison 10464 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */ 10465 if (! unsigned_comparison_p 10466 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) 10467 <= HOST_BITS_PER_WIDE_INT) 10468 && ((unsigned HOST_WIDE_INT) const_op 10469 < (((unsigned HOST_WIDE_INT) 1 10470 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1))))) 10471 { 10472 op0 = XEXP (op0, 0); 10473 continue; 10474 } 10475 break; 10476 10477 case SUBREG: 10478 /* Check for the case where we are comparing A - C1 with C2, 10479 both constants are smaller than 1/2 the maximum positive 10480 value in MODE, and the comparison is equality or unsigned. 10481 In that case, if A is either zero-extended to MODE or has 10482 sufficient sign bits so that the high-order bit in MODE 10483 is a copy of the sign in the inner mode, we can prove that it is 10484 safe to do the operation in the wider mode. This simplifies 10485 many range checks. */ 10486 10487 if (mode_width <= HOST_BITS_PER_WIDE_INT 10488 && subreg_lowpart_p (op0) 10489 && GET_CODE (SUBREG_REG (op0)) == PLUS 10490 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT 10491 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0 10492 && (-INTVAL (XEXP (SUBREG_REG (op0), 1)) 10493 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2)) 10494 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2 10495 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0), 10496 GET_MODE (SUBREG_REG (op0))) 10497 & ~GET_MODE_MASK (mode)) 10498 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0), 10499 GET_MODE (SUBREG_REG (op0))) 10500 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) 10501 - GET_MODE_BITSIZE (mode))))) 10502 { 10503 op0 = SUBREG_REG (op0); 10504 continue; 10505 } 10506 10507 /* If the inner mode is narrower and we are extracting the low part, 10508 we can treat the SUBREG as if it were a ZERO_EXTEND. */ 10509 if (subreg_lowpart_p (op0) 10510 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width) 10511 /* Fall through */ ; 10512 else 10513 break; 10514 10515 /* ... fall through ... */ 10516 10517 case ZERO_EXTEND: 10518 if ((unsigned_comparison_p || equality_comparison_p) 10519 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) 10520 <= HOST_BITS_PER_WIDE_INT) 10521 && ((unsigned HOST_WIDE_INT) const_op 10522 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0))))) 10523 { 10524 op0 = XEXP (op0, 0); 10525 continue; 10526 } 10527 break; 10528 10529 case PLUS: 10530 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do 10531 this for equality comparisons due to pathological cases involving 10532 overflows. */ 10533 if (equality_comparison_p 10534 && 0 != (tem = simplify_binary_operation (MINUS, mode, 10535 op1, XEXP (op0, 1)))) 10536 { 10537 op0 = XEXP (op0, 0); 10538 op1 = tem; 10539 continue; 10540 } 10541 10542 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ 10543 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx 10544 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) 10545 { 10546 op0 = XEXP (XEXP (op0, 0), 0); 10547 code = (code == LT ? EQ : NE); 10548 continue; 10549 } 10550 break; 10551 10552 case MINUS: 10553 /* We used to optimize signed comparisons against zero, but that 10554 was incorrect. Unsigned comparisons against zero (GTU, LEU) 10555 arrive here as equality comparisons, or (GEU, LTU) are 10556 optimized away. No need to special-case them. */ 10557 10558 /* (eq (minus A B) C) -> (eq A (plus B C)) or 10559 (eq B (minus A C)), whichever simplifies. We can only do 10560 this for equality comparisons due to pathological cases involving 10561 overflows. */ 10562 if (equality_comparison_p 10563 && 0 != (tem = simplify_binary_operation (PLUS, mode, 10564 XEXP (op0, 1), op1))) 10565 { 10566 op0 = XEXP (op0, 0); 10567 op1 = tem; 10568 continue; 10569 } 10570 10571 if (equality_comparison_p 10572 && 0 != (tem = simplify_binary_operation (MINUS, mode, 10573 XEXP (op0, 0), op1))) 10574 { 10575 op0 = XEXP (op0, 1); 10576 op1 = tem; 10577 continue; 10578 } 10579 10580 /* The sign bit of (minus (ashiftrt X C) X), where C is the number 10581 of bits in X minus 1, is one iff X > 0. */ 10582 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT 10583 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10584 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1 10585 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 10586 { 10587 op0 = XEXP (op0, 1); 10588 code = (code == GE ? LE : GT); 10589 continue; 10590 } 10591 break; 10592 10593 case XOR: 10594 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification 10595 if C is zero or B is a constant. */ 10596 if (equality_comparison_p 10597 && 0 != (tem = simplify_binary_operation (XOR, mode, 10598 XEXP (op0, 1), op1))) 10599 { 10600 op0 = XEXP (op0, 0); 10601 op1 = tem; 10602 continue; 10603 } 10604 break; 10605 10606 case EQ: case NE: 10607 case UNEQ: case LTGT: 10608 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE: 10609 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE: 10610 case UNORDERED: case ORDERED: 10611 /* We can't do anything if OP0 is a condition code value, rather 10612 than an actual data value. */ 10613 if (const_op != 0 10614#ifdef HAVE_cc0 10615 || XEXP (op0, 0) == cc0_rtx 10616#endif 10617 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) 10618 break; 10619 10620 /* Get the two operands being compared. */ 10621 if (GET_CODE (XEXP (op0, 0)) == COMPARE) 10622 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); 10623 else 10624 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); 10625 10626 /* Check for the cases where we simply want the result of the 10627 earlier test or the opposite of that result. */ 10628 if (code == NE || code == EQ 10629 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 10630 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10631 && (STORE_FLAG_VALUE 10632 & (((HOST_WIDE_INT) 1 10633 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) 10634 && (code == LT || code == GE))) 10635 { 10636 enum rtx_code new_code; 10637 if (code == LT || code == NE) 10638 new_code = GET_CODE (op0); 10639 else 10640 new_code = combine_reversed_comparison_code (op0); 10641 10642 if (new_code != UNKNOWN) 10643 { 10644 code = new_code; 10645 op0 = tem; 10646 op1 = tem1; 10647 continue; 10648 } 10649 } 10650 break; 10651 10652 case IOR: 10653 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero 10654 iff X <= 0. */ 10655 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS 10656 && XEXP (XEXP (op0, 0), 1) == constm1_rtx 10657 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 10658 { 10659 op0 = XEXP (op0, 1); 10660 code = (code == GE ? GT : LE); 10661 continue; 10662 } 10663 break; 10664 10665 case AND: 10666 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This 10667 will be converted to a ZERO_EXTRACT later. */ 10668 if (const_op == 0 && equality_comparison_p 10669 && GET_CODE (XEXP (op0, 0)) == ASHIFT 10670 && XEXP (XEXP (op0, 0), 0) == const1_rtx) 10671 { 10672 op0 = simplify_and_const_int 10673 (op0, mode, gen_rtx_LSHIFTRT (mode, 10674 XEXP (op0, 1), 10675 XEXP (XEXP (op0, 0), 1)), 10676 (HOST_WIDE_INT) 1); 10677 continue; 10678 } 10679 10680 /* If we are comparing (and (lshiftrt X C1) C2) for equality with 10681 zero and X is a comparison and C1 and C2 describe only bits set 10682 in STORE_FLAG_VALUE, we can compare with X. */ 10683 if (const_op == 0 && equality_comparison_p 10684 && mode_width <= HOST_BITS_PER_WIDE_INT 10685 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10686 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT 10687 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10688 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 10689 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) 10690 { 10691 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 10692 << INTVAL (XEXP (XEXP (op0, 0), 1))); 10693 if ((~STORE_FLAG_VALUE & mask) == 0 10694 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<' 10695 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 10696 && GET_RTX_CLASS (GET_CODE (tem)) == '<'))) 10697 { 10698 op0 = XEXP (XEXP (op0, 0), 0); 10699 continue; 10700 } 10701 } 10702 10703 /* If we are doing an equality comparison of an AND of a bit equal 10704 to the sign bit, replace this with a LT or GE comparison of 10705 the underlying value. */ 10706 if (equality_comparison_p 10707 && const_op == 0 10708 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10709 && mode_width <= HOST_BITS_PER_WIDE_INT 10710 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 10711 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) 10712 { 10713 op0 = XEXP (op0, 0); 10714 code = (code == EQ ? GE : LT); 10715 continue; 10716 } 10717 10718 /* If this AND operation is really a ZERO_EXTEND from a narrower 10719 mode, the constant fits within that mode, and this is either an 10720 equality or unsigned comparison, try to do this comparison in 10721 the narrower mode. */ 10722 if ((equality_comparison_p || unsigned_comparison_p) 10723 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10724 && (i = exact_log2 ((INTVAL (XEXP (op0, 1)) 10725 & GET_MODE_MASK (mode)) 10726 + 1)) >= 0 10727 && const_op >> i == 0 10728 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode) 10729 { 10730 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0)); 10731 continue; 10732 } 10733 10734 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits 10735 in both M1 and M2 and the SUBREG is either paradoxical or 10736 represents the low part, permute the SUBREG and the AND and 10737 try again. */ 10738 if (GET_CODE (XEXP (op0, 0)) == SUBREG 10739 && (0 10740#ifdef WORD_REGISTER_OPERATIONS 10741 || ((mode_width 10742 > (GET_MODE_BITSIZE 10743 (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))) 10744 && mode_width <= BITS_PER_WORD) 10745#endif 10746 || ((mode_width 10747 <= (GET_MODE_BITSIZE 10748 (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))) 10749 && subreg_lowpart_p (XEXP (op0, 0)))) 10750#ifndef WORD_REGISTER_OPERATIONS 10751 /* It is unsafe to commute the AND into the SUBREG if the SUBREG 10752 is paradoxical and WORD_REGISTER_OPERATIONS is not defined. 10753 As originally written the upper bits have a defined value 10754 due to the AND operation. However, if we commute the AND 10755 inside the SUBREG then they no longer have defined values 10756 and the meaning of the code has been changed. */ 10757 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) 10758 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))) 10759#endif 10760 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10761 && mode_width <= HOST_BITS_PER_WIDE_INT 10762 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))) 10763 <= HOST_BITS_PER_WIDE_INT) 10764 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0 10765 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0)))) 10766 & INTVAL (XEXP (op0, 1))) 10767 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask 10768 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) 10769 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))) 10770 10771 { 10772 op0 10773 = gen_lowpart_for_combine 10774 (mode, 10775 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))), 10776 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1))); 10777 continue; 10778 } 10779 10780 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to 10781 (eq (and (lshiftrt X) 1) 0). */ 10782 if (const_op == 0 && equality_comparison_p 10783 && XEXP (op0, 1) == const1_rtx 10784 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT 10785 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT) 10786 { 10787 op0 = simplify_and_const_int 10788 (op0, mode, 10789 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0), 10790 XEXP (XEXP (op0, 0), 1)), 10791 (HOST_WIDE_INT) 1); 10792 code = (code == NE ? EQ : NE); 10793 continue; 10794 } 10795 break; 10796 10797 case ASHIFT: 10798 /* If we have (compare (ashift FOO N) (const_int C)) and 10799 the high order N bits of FOO (N+1 if an inequality comparison) 10800 are known to be zero, we can do this by comparing FOO with C 10801 shifted right N bits so long as the low-order N bits of C are 10802 zero. */ 10803 if (GET_CODE (XEXP (op0, 1)) == CONST_INT 10804 && INTVAL (XEXP (op0, 1)) >= 0 10805 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) 10806 < HOST_BITS_PER_WIDE_INT) 10807 && ((const_op 10808 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0) 10809 && mode_width <= HOST_BITS_PER_WIDE_INT 10810 && (nonzero_bits (XEXP (op0, 0), mode) 10811 & ~(mask >> (INTVAL (XEXP (op0, 1)) 10812 + ! equality_comparison_p))) == 0) 10813 { 10814 /* We must perform a logical shift, not an arithmetic one, 10815 as we want the top N bits of C to be zero. */ 10816 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode); 10817 10818 temp >>= INTVAL (XEXP (op0, 1)); 10819 op1 = GEN_INT (trunc_int_for_mode (temp, mode)); 10820 op0 = XEXP (op0, 0); 10821 continue; 10822 } 10823 10824 /* If we are doing a sign bit comparison, it means we are testing 10825 a particular bit. Convert it to the appropriate AND. */ 10826 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT 10827 && mode_width <= HOST_BITS_PER_WIDE_INT) 10828 { 10829 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10830 ((HOST_WIDE_INT) 1 10831 << (mode_width - 1 10832 - INTVAL (XEXP (op0, 1))))); 10833 code = (code == LT ? NE : EQ); 10834 continue; 10835 } 10836 10837 /* If this an equality comparison with zero and we are shifting 10838 the low bit to the sign bit, we can convert this to an AND of the 10839 low-order bit. */ 10840 if (const_op == 0 && equality_comparison_p 10841 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10842 && INTVAL (XEXP (op0, 1)) == mode_width - 1) 10843 { 10844 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10845 (HOST_WIDE_INT) 1); 10846 continue; 10847 } 10848 break; 10849 10850 case ASHIFTRT: 10851 /* If this is an equality comparison with zero, we can do this 10852 as a logical shift, which might be much simpler. */ 10853 if (equality_comparison_p && const_op == 0 10854 && GET_CODE (XEXP (op0, 1)) == CONST_INT) 10855 { 10856 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, 10857 XEXP (op0, 0), 10858 INTVAL (XEXP (op0, 1))); 10859 continue; 10860 } 10861 10862 /* If OP0 is a sign extension and CODE is not an unsigned comparison, 10863 do the comparison in a narrower mode. */ 10864 if (! unsigned_comparison_p 10865 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10866 && GET_CODE (XEXP (op0, 0)) == ASHIFT 10867 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 10868 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 10869 MODE_INT, 1)) != BLKmode 10870 && (((unsigned HOST_WIDE_INT) const_op 10871 + (GET_MODE_MASK (tmode) >> 1) + 1) 10872 <= GET_MODE_MASK (tmode))) 10873 { 10874 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0)); 10875 continue; 10876 } 10877 10878 /* Likewise if OP0 is a PLUS of a sign extension with a 10879 constant, which is usually represented with the PLUS 10880 between the shifts. */ 10881 if (! unsigned_comparison_p 10882 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10883 && GET_CODE (XEXP (op0, 0)) == PLUS 10884 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10885 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT 10886 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1) 10887 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 10888 MODE_INT, 1)) != BLKmode 10889 && (((unsigned HOST_WIDE_INT) const_op 10890 + (GET_MODE_MASK (tmode) >> 1) + 1) 10891 <= GET_MODE_MASK (tmode))) 10892 { 10893 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0); 10894 rtx add_const = XEXP (XEXP (op0, 0), 1); 10895 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const, 10896 XEXP (op0, 1)); 10897 10898 op0 = gen_binary (PLUS, tmode, 10899 gen_lowpart_for_combine (tmode, inner), 10900 new_const); 10901 continue; 10902 } 10903 10904 /* ... fall through ... */ 10905 case LSHIFTRT: 10906 /* If we have (compare (xshiftrt FOO N) (const_int C)) and 10907 the low order N bits of FOO are known to be zero, we can do this 10908 by comparing FOO with C shifted left N bits so long as no 10909 overflow occurs. */ 10910 if (GET_CODE (XEXP (op0, 1)) == CONST_INT 10911 && INTVAL (XEXP (op0, 1)) >= 0 10912 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 10913 && mode_width <= HOST_BITS_PER_WIDE_INT 10914 && (nonzero_bits (XEXP (op0, 0), mode) 10915 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 10916 && (((unsigned HOST_WIDE_INT) const_op 10917 + (GET_CODE (op0) != LSHIFTRT 10918 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1) 10919 + 1) 10920 : 0)) 10921 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)))) 10922 { 10923 /* If the shift was logical, then we must make the condition 10924 unsigned. */ 10925 if (GET_CODE (op0) == LSHIFTRT) 10926 code = unsigned_condition (code); 10927 10928 const_op <<= INTVAL (XEXP (op0, 1)); 10929 op1 = GEN_INT (const_op); 10930 op0 = XEXP (op0, 0); 10931 continue; 10932 } 10933 10934 /* If we are using this shift to extract just the sign bit, we 10935 can replace this with an LT or GE comparison. */ 10936 if (const_op == 0 10937 && (equality_comparison_p || sign_bit_comparison_p) 10938 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10939 && INTVAL (XEXP (op0, 1)) == mode_width - 1) 10940 { 10941 op0 = XEXP (op0, 0); 10942 code = (code == NE || code == GT ? LT : GE); 10943 continue; 10944 } 10945 break; 10946 10947 default: 10948 break; 10949 } 10950 10951 break; 10952 } 10953 10954 /* Now make any compound operations involved in this comparison. Then, 10955 check for an outmost SUBREG on OP0 that is not doing anything or is 10956 paradoxical. The latter transformation must only be performed when 10957 it is known that the "extra" bits will be the same in op0 and op1 or 10958 that they don't matter. There are three cases to consider: 10959 10960 1. SUBREG_REG (op0) is a register. In this case the bits are don't 10961 care bits and we can assume they have any convenient value. So 10962 making the transformation is safe. 10963 10964 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined. 10965 In this case the upper bits of op0 are undefined. We should not make 10966 the simplification in that case as we do not know the contents of 10967 those bits. 10968 10969 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not 10970 NIL. In that case we know those bits are zeros or ones. We must 10971 also be sure that they are the same as the upper bits of op1. 10972 10973 We can never remove a SUBREG for a non-equality comparison because 10974 the sign bit is in a different place in the underlying object. */ 10975 10976 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); 10977 op1 = make_compound_operation (op1, SET); 10978 10979 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 10980 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't 10981 implemented. */ 10982 && GET_CODE (SUBREG_REG (op0)) == REG 10983 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10984 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT 10985 && (code == NE || code == EQ)) 10986 { 10987 if (GET_MODE_SIZE (GET_MODE (op0)) 10988 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))) 10989 { 10990 op0 = SUBREG_REG (op0); 10991 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1); 10992 } 10993 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) 10994 <= HOST_BITS_PER_WIDE_INT) 10995 && (nonzero_bits (SUBREG_REG (op0), 10996 GET_MODE (SUBREG_REG (op0))) 10997 & ~GET_MODE_MASK (GET_MODE (op0))) == 0) 10998 { 10999 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1); 11000 11001 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) 11002 & ~GET_MODE_MASK (GET_MODE (op0))) == 0) 11003 op0 = SUBREG_REG (op0), op1 = tem; 11004 } 11005 } 11006 11007 /* We now do the opposite procedure: Some machines don't have compare 11008 insns in all modes. If OP0's mode is an integer mode smaller than a 11009 word and we can't do a compare in that mode, see if there is a larger 11010 mode for which we can do the compare. There are a number of cases in 11011 which we can use the wider mode. */ 11012 11013 mode = GET_MODE (op0); 11014 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT 11015 && GET_MODE_SIZE (mode) < UNITS_PER_WORD 11016 && ! have_insn_for (COMPARE, mode)) 11017 for (tmode = GET_MODE_WIDER_MODE (mode); 11018 (tmode != VOIDmode 11019 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT); 11020 tmode = GET_MODE_WIDER_MODE (tmode)) 11021 if (have_insn_for (COMPARE, tmode)) 11022 { 11023 int zero_extended; 11024 11025 /* If the only nonzero bits in OP0 and OP1 are those in the 11026 narrower mode and this is an equality or unsigned comparison, 11027 we can use the wider mode. Similarly for sign-extended 11028 values, in which case it is true for all comparisons. */ 11029 zero_extended = ((code == EQ || code == NE 11030 || code == GEU || code == GTU 11031 || code == LEU || code == LTU) 11032 && (nonzero_bits (op0, tmode) 11033 & ~GET_MODE_MASK (mode)) == 0 11034 && ((GET_CODE (op1) == CONST_INT 11035 || (nonzero_bits (op1, tmode) 11036 & ~GET_MODE_MASK (mode)) == 0))); 11037 11038 if (zero_extended 11039 || ((num_sign_bit_copies (op0, tmode) 11040 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode)) 11041 && (num_sign_bit_copies (op1, tmode) 11042 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode)))) 11043 { 11044 /* If OP0 is an AND and we don't have an AND in MODE either, 11045 make a new AND in the proper mode. */ 11046 if (GET_CODE (op0) == AND 11047 && !have_insn_for (AND, mode)) 11048 op0 = gen_binary (AND, tmode, 11049 gen_lowpart_for_combine (tmode, 11050 XEXP (op0, 0)), 11051 gen_lowpart_for_combine (tmode, 11052 XEXP (op0, 1))); 11053 11054 op0 = gen_lowpart_for_combine (tmode, op0); 11055 if (zero_extended && GET_CODE (op1) == CONST_INT) 11056 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode)); 11057 op1 = gen_lowpart_for_combine (tmode, op1); 11058 break; 11059 } 11060 11061 /* If this is a test for negative, we can make an explicit 11062 test of the sign bit. */ 11063 11064 if (op1 == const0_rtx && (code == LT || code == GE) 11065 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 11066 { 11067 op0 = gen_binary (AND, tmode, 11068 gen_lowpart_for_combine (tmode, op0), 11069 GEN_INT ((HOST_WIDE_INT) 1 11070 << (GET_MODE_BITSIZE (mode) - 1))); 11071 code = (code == LT) ? NE : EQ; 11072 break; 11073 } 11074 } 11075 11076#ifdef CANONICALIZE_COMPARISON 11077 /* If this machine only supports a subset of valid comparisons, see if we 11078 can convert an unsupported one into a supported one. */ 11079 CANONICALIZE_COMPARISON (code, op0, op1); 11080#endif 11081 11082 *pop0 = op0; 11083 *pop1 = op1; 11084 11085 return code; 11086} 11087 11088/* Like jump.c' reversed_comparison_code, but use combine infrastructure for 11089 searching backward. */ 11090static enum rtx_code 11091combine_reversed_comparison_code (exp) 11092 rtx exp; 11093{ 11094 enum rtx_code code1 = reversed_comparison_code (exp, NULL); 11095 rtx x; 11096 11097 if (code1 != UNKNOWN 11098 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC) 11099 return code1; 11100 /* Otherwise try and find where the condition codes were last set and 11101 use that. */ 11102 x = get_last_value (XEXP (exp, 0)); 11103 if (!x || GET_CODE (x) != COMPARE) 11104 return UNKNOWN; 11105 return reversed_comparison_code_parts (GET_CODE (exp), 11106 XEXP (x, 0), XEXP (x, 1), NULL); 11107} 11108/* Return comparison with reversed code of EXP and operands OP0 and OP1. 11109 Return NULL_RTX in case we fail to do the reversal. */ 11110static rtx 11111reversed_comparison (exp, mode, op0, op1) 11112 rtx exp, op0, op1; 11113 enum machine_mode mode; 11114{ 11115 enum rtx_code reversed_code = combine_reversed_comparison_code (exp); 11116 if (reversed_code == UNKNOWN) 11117 return NULL_RTX; 11118 else 11119 return gen_binary (reversed_code, mode, op0, op1); 11120} 11121 11122/* Utility function for following routine. Called when X is part of a value 11123 being stored into reg_last_set_value. Sets reg_last_set_table_tick 11124 for each register mentioned. Similar to mention_regs in cse.c */ 11125 11126static void 11127update_table_tick (x) 11128 rtx x; 11129{ 11130 enum rtx_code code = GET_CODE (x); 11131 const char *fmt = GET_RTX_FORMAT (code); 11132 int i; 11133 11134 if (code == REG) 11135 { 11136 unsigned int regno = REGNO (x); 11137 unsigned int endregno 11138 = regno + (regno < FIRST_PSEUDO_REGISTER 11139 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 11140 unsigned int r; 11141 11142 for (r = regno; r < endregno; r++) 11143 reg_last_set_table_tick[r] = label_tick; 11144 11145 return; 11146 } 11147 11148 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 11149 /* Note that we can't have an "E" in values stored; see 11150 get_last_value_validate. */ 11151 if (fmt[i] == 'e') 11152 update_table_tick (XEXP (x, i)); 11153} 11154 11155/* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we 11156 are saying that the register is clobbered and we no longer know its 11157 value. If INSN is zero, don't update reg_last_set; this is only permitted 11158 with VALUE also zero and is used to invalidate the register. */ 11159 11160static void 11161record_value_for_reg (reg, insn, value) 11162 rtx reg; 11163 rtx insn; 11164 rtx value; 11165{ 11166 unsigned int regno = REGNO (reg); 11167 unsigned int endregno 11168 = regno + (regno < FIRST_PSEUDO_REGISTER 11169 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1); 11170 unsigned int i; 11171 11172 /* If VALUE contains REG and we have a previous value for REG, substitute 11173 the previous value. */ 11174 if (value && insn && reg_overlap_mentioned_p (reg, value)) 11175 { 11176 rtx tem; 11177 11178 /* Set things up so get_last_value is allowed to see anything set up to 11179 our insn. */ 11180 subst_low_cuid = INSN_CUID (insn); 11181 tem = get_last_value (reg); 11182 11183 /* If TEM is simply a binary operation with two CLOBBERs as operands, 11184 it isn't going to be useful and will take a lot of time to process, 11185 so just use the CLOBBER. */ 11186 11187 if (tem) 11188 { 11189 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2' 11190 || GET_RTX_CLASS (GET_CODE (tem)) == 'c') 11191 && GET_CODE (XEXP (tem, 0)) == CLOBBER 11192 && GET_CODE (XEXP (tem, 1)) == CLOBBER) 11193 tem = XEXP (tem, 0); 11194 11195 value = replace_rtx (copy_rtx (value), reg, tem); 11196 } 11197 } 11198 11199 /* For each register modified, show we don't know its value, that 11200 we don't know about its bitwise content, that its value has been 11201 updated, and that we don't know the location of the death of the 11202 register. */ 11203 for (i = regno; i < endregno; i++) 11204 { 11205 if (insn) 11206 reg_last_set[i] = insn; 11207 11208 reg_last_set_value[i] = 0; 11209 reg_last_set_mode[i] = 0; 11210 reg_last_set_nonzero_bits[i] = 0; 11211 reg_last_set_sign_bit_copies[i] = 0; 11212 reg_last_death[i] = 0; 11213 } 11214 11215 /* Mark registers that are being referenced in this value. */ 11216 if (value) 11217 update_table_tick (value); 11218 11219 /* Now update the status of each register being set. 11220 If someone is using this register in this block, set this register 11221 to invalid since we will get confused between the two lives in this 11222 basic block. This makes using this register always invalid. In cse, we 11223 scan the table to invalidate all entries using this register, but this 11224 is too much work for us. */ 11225 11226 for (i = regno; i < endregno; i++) 11227 { 11228 reg_last_set_label[i] = label_tick; 11229 if (value && reg_last_set_table_tick[i] == label_tick) 11230 reg_last_set_invalid[i] = 1; 11231 else 11232 reg_last_set_invalid[i] = 0; 11233 } 11234 11235 /* The value being assigned might refer to X (like in "x++;"). In that 11236 case, we must replace it with (clobber (const_int 0)) to prevent 11237 infinite loops. */ 11238 if (value && ! get_last_value_validate (&value, insn, 11239 reg_last_set_label[regno], 0)) 11240 { 11241 value = copy_rtx (value); 11242 if (! get_last_value_validate (&value, insn, 11243 reg_last_set_label[regno], 1)) 11244 value = 0; 11245 } 11246 11247 /* For the main register being modified, update the value, the mode, the 11248 nonzero bits, and the number of sign bit copies. */ 11249 11250 reg_last_set_value[regno] = value; 11251 11252 if (value) 11253 { 11254 enum machine_mode mode = GET_MODE (reg); 11255 subst_low_cuid = INSN_CUID (insn); 11256 reg_last_set_mode[regno] = mode; 11257 if (GET_MODE_CLASS (mode) == MODE_INT 11258 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 11259 mode = nonzero_bits_mode; 11260 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode); 11261 reg_last_set_sign_bit_copies[regno] 11262 = num_sign_bit_copies (value, GET_MODE (reg)); 11263 } 11264} 11265 11266/* Called via note_stores from record_dead_and_set_regs to handle one 11267 SET or CLOBBER in an insn. DATA is the instruction in which the 11268 set is occurring. */ 11269 11270static void 11271record_dead_and_set_regs_1 (dest, setter, data) 11272 rtx dest, setter; 11273 void *data; 11274{ 11275 rtx record_dead_insn = (rtx) data; 11276 11277 if (GET_CODE (dest) == SUBREG) 11278 dest = SUBREG_REG (dest); 11279 11280 if (GET_CODE (dest) == REG) 11281 { 11282 /* If we are setting the whole register, we know its value. Otherwise 11283 show that we don't know the value. We can handle SUBREG in 11284 some cases. */ 11285 if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) 11286 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); 11287 else if (GET_CODE (setter) == SET 11288 && GET_CODE (SET_DEST (setter)) == SUBREG 11289 && SUBREG_REG (SET_DEST (setter)) == dest 11290 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD 11291 && subreg_lowpart_p (SET_DEST (setter))) 11292 record_value_for_reg (dest, record_dead_insn, 11293 gen_lowpart_for_combine (GET_MODE (dest), 11294 SET_SRC (setter))); 11295 else 11296 record_value_for_reg (dest, record_dead_insn, NULL_RTX); 11297 } 11298 else if (GET_CODE (dest) == MEM 11299 /* Ignore pushes, they clobber nothing. */ 11300 && ! push_operand (dest, GET_MODE (dest))) 11301 mem_last_set = INSN_CUID (record_dead_insn); 11302} 11303 11304/* Update the records of when each REG was most recently set or killed 11305 for the things done by INSN. This is the last thing done in processing 11306 INSN in the combiner loop. 11307 11308 We update reg_last_set, reg_last_set_value, reg_last_set_mode, 11309 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death, 11310 and also the similar information mem_last_set (which insn most recently 11311 modified memory) and last_call_cuid (which insn was the most recent 11312 subroutine call). */ 11313 11314static void 11315record_dead_and_set_regs (insn) 11316 rtx insn; 11317{ 11318 rtx link; 11319 unsigned int i; 11320 11321 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 11322 { 11323 if (REG_NOTE_KIND (link) == REG_DEAD 11324 && GET_CODE (XEXP (link, 0)) == REG) 11325 { 11326 unsigned int regno = REGNO (XEXP (link, 0)); 11327 unsigned int endregno 11328 = regno + (regno < FIRST_PSEUDO_REGISTER 11329 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0))) 11330 : 1); 11331 11332 for (i = regno; i < endregno; i++) 11333 reg_last_death[i] = insn; 11334 } 11335 else if (REG_NOTE_KIND (link) == REG_INC) 11336 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); 11337 } 11338 11339 if (GET_CODE (insn) == CALL_INSN) 11340 { 11341 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 11342 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i)) 11343 { 11344 reg_last_set_value[i] = 0; 11345 reg_last_set_mode[i] = 0; 11346 reg_last_set_nonzero_bits[i] = 0; 11347 reg_last_set_sign_bit_copies[i] = 0; 11348 reg_last_death[i] = 0; 11349 } 11350 11351 last_call_cuid = mem_last_set = INSN_CUID (insn); 11352 11353 /* Don't bother recording what this insn does. It might set the 11354 return value register, but we can't combine into a call 11355 pattern anyway, so there's no point trying (and it may cause 11356 a crash, if e.g. we wind up asking for last_set_value of a 11357 SUBREG of the return value register). */ 11358 return; 11359 } 11360 11361 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn); 11362} 11363 11364/* If a SUBREG has the promoted bit set, it is in fact a property of the 11365 register present in the SUBREG, so for each such SUBREG go back and 11366 adjust nonzero and sign bit information of the registers that are 11367 known to have some zero/sign bits set. 11368 11369 This is needed because when combine blows the SUBREGs away, the 11370 information on zero/sign bits is lost and further combines can be 11371 missed because of that. */ 11372 11373static void 11374record_promoted_value (insn, subreg) 11375 rtx insn; 11376 rtx subreg; 11377{ 11378 rtx links, set; 11379 unsigned int regno = REGNO (SUBREG_REG (subreg)); 11380 enum machine_mode mode = GET_MODE (subreg); 11381 11382 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) 11383 return; 11384 11385 for (links = LOG_LINKS (insn); links;) 11386 { 11387 insn = XEXP (links, 0); 11388 set = single_set (insn); 11389 11390 if (! set || GET_CODE (SET_DEST (set)) != REG 11391 || REGNO (SET_DEST (set)) != regno 11392 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg))) 11393 { 11394 links = XEXP (links, 1); 11395 continue; 11396 } 11397 11398 if (reg_last_set[regno] == insn) 11399 { 11400 if (SUBREG_PROMOTED_UNSIGNED_P (subreg)) 11401 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode); 11402 } 11403 11404 if (GET_CODE (SET_SRC (set)) == REG) 11405 { 11406 regno = REGNO (SET_SRC (set)); 11407 links = LOG_LINKS (insn); 11408 } 11409 else 11410 break; 11411 } 11412} 11413 11414/* Scan X for promoted SUBREGs. For each one found, 11415 note what it implies to the registers used in it. */ 11416 11417static void 11418check_promoted_subreg (insn, x) 11419 rtx insn; 11420 rtx x; 11421{ 11422 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x) 11423 && GET_CODE (SUBREG_REG (x)) == REG) 11424 record_promoted_value (insn, x); 11425 else 11426 { 11427 const char *format = GET_RTX_FORMAT (GET_CODE (x)); 11428 int i, j; 11429 11430 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) 11431 switch (format[i]) 11432 { 11433 case 'e': 11434 check_promoted_subreg (insn, XEXP (x, i)); 11435 break; 11436 case 'V': 11437 case 'E': 11438 if (XVEC (x, i) != 0) 11439 for (j = 0; j < XVECLEN (x, i); j++) 11440 check_promoted_subreg (insn, XVECEXP (x, i, j)); 11441 break; 11442 } 11443 } 11444} 11445 11446/* Utility routine for the following function. Verify that all the registers 11447 mentioned in *LOC are valid when *LOC was part of a value set when 11448 label_tick == TICK. Return 0 if some are not. 11449 11450 If REPLACE is non-zero, replace the invalid reference with 11451 (clobber (const_int 0)) and return 1. This replacement is useful because 11452 we often can get useful information about the form of a value (e.g., if 11453 it was produced by a shift that always produces -1 or 0) even though 11454 we don't know exactly what registers it was produced from. */ 11455 11456static int 11457get_last_value_validate (loc, insn, tick, replace) 11458 rtx *loc; 11459 rtx insn; 11460 int tick; 11461 int replace; 11462{ 11463 rtx x = *loc; 11464 const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); 11465 int len = GET_RTX_LENGTH (GET_CODE (x)); 11466 int i; 11467 11468 if (GET_CODE (x) == REG) 11469 { 11470 unsigned int regno = REGNO (x); 11471 unsigned int endregno 11472 = regno + (regno < FIRST_PSEUDO_REGISTER 11473 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 11474 unsigned int j; 11475 11476 for (j = regno; j < endregno; j++) 11477 if (reg_last_set_invalid[j] 11478 /* If this is a pseudo-register that was only set once and not 11479 live at the beginning of the function, it is always valid. */ 11480 || (! (regno >= FIRST_PSEUDO_REGISTER 11481 && REG_N_SETS (regno) == 1 11482 && (! REGNO_REG_SET_P 11483 (BASIC_BLOCK (0)->global_live_at_start, regno))) 11484 && reg_last_set_label[j] > tick)) 11485 { 11486 if (replace) 11487 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 11488 return replace; 11489 } 11490 11491 return 1; 11492 } 11493 /* If this is a memory reference, make sure that there were 11494 no stores after it that might have clobbered the value. We don't 11495 have alias info, so we assume any store invalidates it. */ 11496 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x) 11497 && INSN_CUID (insn) <= mem_last_set) 11498 { 11499 if (replace) 11500 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 11501 return replace; 11502 } 11503 11504 for (i = 0; i < len; i++) 11505 if ((fmt[i] == 'e' 11506 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0) 11507 /* Don't bother with these. They shouldn't occur anyway. */ 11508 || fmt[i] == 'E') 11509 return 0; 11510 11511 /* If we haven't found a reason for it to be invalid, it is valid. */ 11512 return 1; 11513} 11514 11515/* Get the last value assigned to X, if known. Some registers 11516 in the value may be replaced with (clobber (const_int 0)) if their value 11517 is known longer known reliably. */ 11518 11519static rtx 11520get_last_value (x) 11521 rtx x; 11522{ 11523 unsigned int regno; 11524 rtx value; 11525 11526 /* If this is a non-paradoxical SUBREG, get the value of its operand and 11527 then convert it to the desired mode. If this is a paradoxical SUBREG, 11528 we cannot predict what values the "extra" bits might have. */ 11529 if (GET_CODE (x) == SUBREG 11530 && subreg_lowpart_p (x) 11531 && (GET_MODE_SIZE (GET_MODE (x)) 11532 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 11533 && (value = get_last_value (SUBREG_REG (x))) != 0) 11534 return gen_lowpart_for_combine (GET_MODE (x), value); 11535 11536 if (GET_CODE (x) != REG) 11537 return 0; 11538 11539 regno = REGNO (x); 11540 value = reg_last_set_value[regno]; 11541 11542 /* If we don't have a value, or if it isn't for this basic block and 11543 it's either a hard register, set more than once, or it's a live 11544 at the beginning of the function, return 0. 11545 11546 Because if it's not live at the beginning of the function then the reg 11547 is always set before being used (is never used without being set). 11548 And, if it's set only once, and it's always set before use, then all 11549 uses must have the same last value, even if it's not from this basic 11550 block. */ 11551 11552 if (value == 0 11553 || (reg_last_set_label[regno] != label_tick 11554 && (regno < FIRST_PSEUDO_REGISTER 11555 || REG_N_SETS (regno) != 1 11556 || (REGNO_REG_SET_P 11557 (BASIC_BLOCK (0)->global_live_at_start, regno))))) 11558 return 0; 11559 11560 /* If the value was set in a later insn than the ones we are processing, 11561 we can't use it even if the register was only set once. */ 11562 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid) 11563 return 0; 11564 11565 /* If the value has all its registers valid, return it. */ 11566 if (get_last_value_validate (&value, reg_last_set[regno], 11567 reg_last_set_label[regno], 0)) 11568 return value; 11569 11570 /* Otherwise, make a copy and replace any invalid register with 11571 (clobber (const_int 0)). If that fails for some reason, return 0. */ 11572 11573 value = copy_rtx (value); 11574 if (get_last_value_validate (&value, reg_last_set[regno], 11575 reg_last_set_label[regno], 1)) 11576 return value; 11577 11578 return 0; 11579} 11580 11581/* Return nonzero if expression X refers to a REG or to memory 11582 that is set in an instruction more recent than FROM_CUID. */ 11583 11584static int 11585use_crosses_set_p (x, from_cuid) 11586 rtx x; 11587 int from_cuid; 11588{ 11589 const char *fmt; 11590 int i; 11591 enum rtx_code code = GET_CODE (x); 11592 11593 if (code == REG) 11594 { 11595 unsigned int regno = REGNO (x); 11596 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER 11597 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 11598 11599#ifdef PUSH_ROUNDING 11600 /* Don't allow uses of the stack pointer to be moved, 11601 because we don't know whether the move crosses a push insn. */ 11602 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS) 11603 return 1; 11604#endif 11605 for (; regno < endreg; regno++) 11606 if (reg_last_set[regno] 11607 && INSN_CUID (reg_last_set[regno]) > from_cuid) 11608 return 1; 11609 return 0; 11610 } 11611 11612 if (code == MEM && mem_last_set > from_cuid) 11613 return 1; 11614 11615 fmt = GET_RTX_FORMAT (code); 11616 11617 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 11618 { 11619 if (fmt[i] == 'E') 11620 { 11621 int j; 11622 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 11623 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid)) 11624 return 1; 11625 } 11626 else if (fmt[i] == 'e' 11627 && use_crosses_set_p (XEXP (x, i), from_cuid)) 11628 return 1; 11629 } 11630 return 0; 11631} 11632 11633/* Define three variables used for communication between the following 11634 routines. */ 11635 11636static unsigned int reg_dead_regno, reg_dead_endregno; 11637static int reg_dead_flag; 11638 11639/* Function called via note_stores from reg_dead_at_p. 11640 11641 If DEST is within [reg_dead_regno, reg_dead_endregno), set 11642 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ 11643 11644static void 11645reg_dead_at_p_1 (dest, x, data) 11646 rtx dest; 11647 rtx x; 11648 void *data ATTRIBUTE_UNUSED; 11649{ 11650 unsigned int regno, endregno; 11651 11652 if (GET_CODE (dest) != REG) 11653 return; 11654 11655 regno = REGNO (dest); 11656 endregno = regno + (regno < FIRST_PSEUDO_REGISTER 11657 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1); 11658 11659 if (reg_dead_endregno > regno && reg_dead_regno < endregno) 11660 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; 11661} 11662 11663/* Return non-zero if REG is known to be dead at INSN. 11664 11665 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER 11666 referencing REG, it is dead. If we hit a SET referencing REG, it is 11667 live. Otherwise, see if it is live or dead at the start of the basic 11668 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS 11669 must be assumed to be always live. */ 11670 11671static int 11672reg_dead_at_p (reg, insn) 11673 rtx reg; 11674 rtx insn; 11675{ 11676 int block; 11677 unsigned int i; 11678 11679 /* Set variables for reg_dead_at_p_1. */ 11680 reg_dead_regno = REGNO (reg); 11681 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER 11682 ? HARD_REGNO_NREGS (reg_dead_regno, 11683 GET_MODE (reg)) 11684 : 1); 11685 11686 reg_dead_flag = 0; 11687 11688 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */ 11689 if (reg_dead_regno < FIRST_PSEUDO_REGISTER) 11690 { 11691 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 11692 if (TEST_HARD_REG_BIT (newpat_used_regs, i)) 11693 return 0; 11694 } 11695 11696 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or 11697 beginning of function. */ 11698 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER; 11699 insn = prev_nonnote_insn (insn)) 11700 { 11701 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL); 11702 if (reg_dead_flag) 11703 return reg_dead_flag == 1 ? 1 : 0; 11704 11705 if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) 11706 return 1; 11707 } 11708 11709 /* Get the basic block number that we were in. */ 11710 if (insn == 0) 11711 block = 0; 11712 else 11713 { 11714 for (block = 0; block < n_basic_blocks; block++) 11715 if (insn == BLOCK_HEAD (block)) 11716 break; 11717 11718 if (block == n_basic_blocks) 11719 return 0; 11720 } 11721 11722 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 11723 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i)) 11724 return 0; 11725 11726 return 1; 11727} 11728 11729/* Note hard registers in X that are used. This code is similar to 11730 that in flow.c, but much simpler since we don't care about pseudos. */ 11731 11732static void 11733mark_used_regs_combine (x) 11734 rtx x; 11735{ 11736 RTX_CODE code = GET_CODE (x); 11737 unsigned int regno; 11738 int i; 11739 11740 switch (code) 11741 { 11742 case LABEL_REF: 11743 case SYMBOL_REF: 11744 case CONST_INT: 11745 case CONST: 11746 case CONST_DOUBLE: 11747 case CONST_VECTOR: 11748 case PC: 11749 case ADDR_VEC: 11750 case ADDR_DIFF_VEC: 11751 case ASM_INPUT: 11752#ifdef HAVE_cc0 11753 /* CC0 must die in the insn after it is set, so we don't need to take 11754 special note of it here. */ 11755 case CC0: 11756#endif 11757 return; 11758 11759 case CLOBBER: 11760 /* If we are clobbering a MEM, mark any hard registers inside the 11761 address as used. */ 11762 if (GET_CODE (XEXP (x, 0)) == MEM) 11763 mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); 11764 return; 11765 11766 case REG: 11767 regno = REGNO (x); 11768 /* A hard reg in a wide mode may really be multiple registers. 11769 If so, mark all of them just like the first. */ 11770 if (regno < FIRST_PSEUDO_REGISTER) 11771 { 11772 unsigned int endregno, r; 11773 11774 /* None of this applies to the stack, frame or arg pointers */ 11775 if (regno == STACK_POINTER_REGNUM 11776#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM 11777 || regno == HARD_FRAME_POINTER_REGNUM 11778#endif 11779#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 11780 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) 11781#endif 11782 || regno == FRAME_POINTER_REGNUM) 11783 return; 11784 11785 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11786 for (r = regno; r < endregno; r++) 11787 SET_HARD_REG_BIT (newpat_used_regs, r); 11788 } 11789 return; 11790 11791 case SET: 11792 { 11793 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in 11794 the address. */ 11795 rtx testreg = SET_DEST (x); 11796 11797 while (GET_CODE (testreg) == SUBREG 11798 || GET_CODE (testreg) == ZERO_EXTRACT 11799 || GET_CODE (testreg) == SIGN_EXTRACT 11800 || GET_CODE (testreg) == STRICT_LOW_PART) 11801 testreg = XEXP (testreg, 0); 11802 11803 if (GET_CODE (testreg) == MEM) 11804 mark_used_regs_combine (XEXP (testreg, 0)); 11805 11806 mark_used_regs_combine (SET_SRC (x)); 11807 } 11808 return; 11809 11810 default: 11811 break; 11812 } 11813 11814 /* Recursively scan the operands of this expression. */ 11815 11816 { 11817 const char *fmt = GET_RTX_FORMAT (code); 11818 11819 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 11820 { 11821 if (fmt[i] == 'e') 11822 mark_used_regs_combine (XEXP (x, i)); 11823 else if (fmt[i] == 'E') 11824 { 11825 int j; 11826 11827 for (j = 0; j < XVECLEN (x, i); j++) 11828 mark_used_regs_combine (XVECEXP (x, i, j)); 11829 } 11830 } 11831 } 11832} 11833 11834/* Remove register number REGNO from the dead registers list of INSN. 11835 11836 Return the note used to record the death, if there was one. */ 11837 11838rtx 11839remove_death (regno, insn) 11840 unsigned int regno; 11841 rtx insn; 11842{ 11843 rtx note = find_regno_note (insn, REG_DEAD, regno); 11844 11845 if (note) 11846 { 11847 REG_N_DEATHS (regno)--; 11848 remove_note (insn, note); 11849 } 11850 11851 return note; 11852} 11853 11854/* For each register (hardware or pseudo) used within expression X, if its 11855 death is in an instruction with cuid between FROM_CUID (inclusive) and 11856 TO_INSN (exclusive), put a REG_DEAD note for that register in the 11857 list headed by PNOTES. 11858 11859 That said, don't move registers killed by maybe_kill_insn. 11860 11861 This is done when X is being merged by combination into TO_INSN. These 11862 notes will then be distributed as needed. */ 11863 11864static void 11865move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes) 11866 rtx x; 11867 rtx maybe_kill_insn; 11868 int from_cuid; 11869 rtx to_insn; 11870 rtx *pnotes; 11871{ 11872 const char *fmt; 11873 int len, i; 11874 enum rtx_code code = GET_CODE (x); 11875 11876 if (code == REG) 11877 { 11878 unsigned int regno = REGNO (x); 11879 rtx where_dead = reg_last_death[regno]; 11880 rtx before_dead, after_dead; 11881 11882 /* Don't move the register if it gets killed in between from and to */ 11883 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) 11884 && ! reg_referenced_p (x, maybe_kill_insn)) 11885 return; 11886 11887 /* WHERE_DEAD could be a USE insn made by combine, so first we 11888 make sure that we have insns with valid INSN_CUID values. */ 11889 before_dead = where_dead; 11890 while (before_dead && INSN_UID (before_dead) > max_uid_cuid) 11891 before_dead = PREV_INSN (before_dead); 11892 11893 after_dead = where_dead; 11894 while (after_dead && INSN_UID (after_dead) > max_uid_cuid) 11895 after_dead = NEXT_INSN (after_dead); 11896 11897 if (before_dead && after_dead 11898 && INSN_CUID (before_dead) >= from_cuid 11899 && (INSN_CUID (after_dead) < INSN_CUID (to_insn) 11900 || (where_dead != after_dead 11901 && INSN_CUID (after_dead) == INSN_CUID (to_insn)))) 11902 { 11903 rtx note = remove_death (regno, where_dead); 11904 11905 /* It is possible for the call above to return 0. This can occur 11906 when reg_last_death points to I2 or I1 that we combined with. 11907 In that case make a new note. 11908 11909 We must also check for the case where X is a hard register 11910 and NOTE is a death note for a range of hard registers 11911 including X. In that case, we must put REG_DEAD notes for 11912 the remaining registers in place of NOTE. */ 11913 11914 if (note != 0 && regno < FIRST_PSEUDO_REGISTER 11915 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 11916 > GET_MODE_SIZE (GET_MODE (x)))) 11917 { 11918 unsigned int deadregno = REGNO (XEXP (note, 0)); 11919 unsigned int deadend 11920 = (deadregno + HARD_REGNO_NREGS (deadregno, 11921 GET_MODE (XEXP (note, 0)))); 11922 unsigned int ourend 11923 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11924 unsigned int i; 11925 11926 for (i = deadregno; i < deadend; i++) 11927 if (i < regno || i >= ourend) 11928 REG_NOTES (where_dead) 11929 = gen_rtx_EXPR_LIST (REG_DEAD, 11930 gen_rtx_REG (reg_raw_mode[i], i), 11931 REG_NOTES (where_dead)); 11932 } 11933 11934 /* If we didn't find any note, or if we found a REG_DEAD note that 11935 covers only part of the given reg, and we have a multi-reg hard 11936 register, then to be safe we must check for REG_DEAD notes 11937 for each register other than the first. They could have 11938 their own REG_DEAD notes lying around. */ 11939 else if ((note == 0 11940 || (note != 0 11941 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 11942 < GET_MODE_SIZE (GET_MODE (x))))) 11943 && regno < FIRST_PSEUDO_REGISTER 11944 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1) 11945 { 11946 unsigned int ourend 11947 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11948 unsigned int i, offset; 11949 rtx oldnotes = 0; 11950 11951 if (note) 11952 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))); 11953 else 11954 offset = 1; 11955 11956 for (i = regno + offset; i < ourend; i++) 11957 move_deaths (gen_rtx_REG (reg_raw_mode[i], i), 11958 maybe_kill_insn, from_cuid, to_insn, &oldnotes); 11959 } 11960 11961 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) 11962 { 11963 XEXP (note, 1) = *pnotes; 11964 *pnotes = note; 11965 } 11966 else 11967 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes); 11968 11969 REG_N_DEATHS (regno)++; 11970 } 11971 11972 return; 11973 } 11974 11975 else if (GET_CODE (x) == SET) 11976 { 11977 rtx dest = SET_DEST (x); 11978 11979 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes); 11980 11981 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG 11982 that accesses one word of a multi-word item, some 11983 piece of everything register in the expression is used by 11984 this insn, so remove any old death. */ 11985 /* ??? So why do we test for equality of the sizes? */ 11986 11987 if (GET_CODE (dest) == ZERO_EXTRACT 11988 || GET_CODE (dest) == STRICT_LOW_PART 11989 || (GET_CODE (dest) == SUBREG 11990 && (((GET_MODE_SIZE (GET_MODE (dest)) 11991 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 11992 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) 11993 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) 11994 { 11995 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes); 11996 return; 11997 } 11998 11999 /* If this is some other SUBREG, we know it replaces the entire 12000 value, so use that as the destination. */ 12001 if (GET_CODE (dest) == SUBREG) 12002 dest = SUBREG_REG (dest); 12003 12004 /* If this is a MEM, adjust deaths of anything used in the address. 12005 For a REG (the only other possibility), the entire value is 12006 being replaced so the old value is not used in this insn. */ 12007 12008 if (GET_CODE (dest) == MEM) 12009 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid, 12010 to_insn, pnotes); 12011 return; 12012 } 12013 12014 else if (GET_CODE (x) == CLOBBER) 12015 return; 12016 12017 len = GET_RTX_LENGTH (code); 12018 fmt = GET_RTX_FORMAT (code); 12019 12020 for (i = 0; i < len; i++) 12021 { 12022 if (fmt[i] == 'E') 12023 { 12024 int j; 12025 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 12026 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid, 12027 to_insn, pnotes); 12028 } 12029 else if (fmt[i] == 'e') 12030 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes); 12031 } 12032} 12033 12034/* Return 1 if X is the target of a bit-field assignment in BODY, the 12035 pattern of an insn. X must be a REG. */ 12036 12037static int 12038reg_bitfield_target_p (x, body) 12039 rtx x; 12040 rtx body; 12041{ 12042 int i; 12043 12044 if (GET_CODE (body) == SET) 12045 { 12046 rtx dest = SET_DEST (body); 12047 rtx target; 12048 unsigned int regno, tregno, endregno, endtregno; 12049 12050 if (GET_CODE (dest) == ZERO_EXTRACT) 12051 target = XEXP (dest, 0); 12052 else if (GET_CODE (dest) == STRICT_LOW_PART) 12053 target = SUBREG_REG (XEXP (dest, 0)); 12054 else 12055 return 0; 12056 12057 if (GET_CODE (target) == SUBREG) 12058 target = SUBREG_REG (target); 12059 12060 if (GET_CODE (target) != REG) 12061 return 0; 12062 12063 tregno = REGNO (target), regno = REGNO (x); 12064 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) 12065 return target == x; 12066 12067 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target)); 12068 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 12069 12070 return endregno > tregno && regno < endtregno; 12071 } 12072 12073 else if (GET_CODE (body) == PARALLEL) 12074 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 12075 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) 12076 return 1; 12077 12078 return 0; 12079} 12080 12081/* Given a chain of REG_NOTES originally from FROM_INSN, try to place them 12082 as appropriate. I3 and I2 are the insns resulting from the combination 12083 insns including FROM (I2 may be zero). 12084 12085 ELIM_I2 and ELIM_I1 are either zero or registers that we know will 12086 not need REG_DEAD notes because they are being substituted for. This 12087 saves searching in the most common cases. 12088 12089 Each note in the list is either ignored or placed on some insns, depending 12090 on the type of note. */ 12091 12092static void 12093distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1) 12094 rtx notes; 12095 rtx from_insn; 12096 rtx i3, i2; 12097 rtx elim_i2, elim_i1; 12098{ 12099 rtx note, next_note; 12100 rtx tem; 12101 12102 for (note = notes; note; note = next_note) 12103 { 12104 rtx place = 0, place2 = 0; 12105 12106 /* If this NOTE references a pseudo register, ensure it references 12107 the latest copy of that register. */ 12108 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG 12109 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER) 12110 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))]; 12111 12112 next_note = XEXP (note, 1); 12113 switch (REG_NOTE_KIND (note)) 12114 { 12115 case REG_BR_PROB: 12116 case REG_BR_PRED: 12117 case REG_EXEC_COUNT: 12118 /* Doesn't matter much where we put this, as long as it's somewhere. 12119 It is preferable to keep these notes on branches, which is most 12120 likely to be i3. */ 12121 place = i3; 12122 break; 12123 12124 case REG_VTABLE_REF: 12125 /* ??? Should remain with *a particular* memory load. Given the 12126 nature of vtable data, the last insn seems relatively safe. */ 12127 place = i3; 12128 break; 12129 12130 case REG_NON_LOCAL_GOTO: 12131 if (GET_CODE (i3) == JUMP_INSN) 12132 place = i3; 12133 else if (i2 && GET_CODE (i2) == JUMP_INSN) 12134 place = i2; 12135 else 12136 abort (); 12137 break; 12138 12139 case REG_EH_REGION: 12140 /* These notes must remain with the call or trapping instruction. */ 12141 if (GET_CODE (i3) == CALL_INSN) 12142 place = i3; 12143 else if (i2 && GET_CODE (i2) == CALL_INSN) 12144 place = i2; 12145 else if (flag_non_call_exceptions) 12146 { 12147 if (may_trap_p (i3)) 12148 place = i3; 12149 else if (i2 && may_trap_p (i2)) 12150 place = i2; 12151 /* ??? Otherwise assume we've combined things such that we 12152 can now prove that the instructions can't trap. Drop the 12153 note in this case. */ 12154 } 12155 else 12156 abort (); 12157 break; 12158 12159 case REG_NORETURN: 12160 case REG_SETJMP: 12161 /* These notes must remain with the call. It should not be 12162 possible for both I2 and I3 to be a call. */ 12163 if (GET_CODE (i3) == CALL_INSN) 12164 place = i3; 12165 else if (i2 && GET_CODE (i2) == CALL_INSN) 12166 place = i2; 12167 else 12168 abort (); 12169 break; 12170 12171 case REG_UNUSED: 12172 /* Any clobbers for i3 may still exist, and so we must process 12173 REG_UNUSED notes from that insn. 12174 12175 Any clobbers from i2 or i1 can only exist if they were added by 12176 recog_for_combine. In that case, recog_for_combine created the 12177 necessary REG_UNUSED notes. Trying to keep any original 12178 REG_UNUSED notes from these insns can cause incorrect output 12179 if it is for the same register as the original i3 dest. 12180 In that case, we will notice that the register is set in i3, 12181 and then add a REG_UNUSED note for the destination of i3, which 12182 is wrong. However, it is possible to have REG_UNUSED notes from 12183 i2 or i1 for register which were both used and clobbered, so 12184 we keep notes from i2 or i1 if they will turn into REG_DEAD 12185 notes. */ 12186 12187 /* If this register is set or clobbered in I3, put the note there 12188 unless there is one already. */ 12189 if (reg_set_p (XEXP (note, 0), PATTERN (i3))) 12190 { 12191 if (from_insn != i3) 12192 break; 12193 12194 if (! (GET_CODE (XEXP (note, 0)) == REG 12195 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) 12196 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) 12197 place = i3; 12198 } 12199 /* Otherwise, if this register is used by I3, then this register 12200 now dies here, so we must put a REG_DEAD note here unless there 12201 is one already. */ 12202 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) 12203 && ! (GET_CODE (XEXP (note, 0)) == REG 12204 ? find_regno_note (i3, REG_DEAD, 12205 REGNO (XEXP (note, 0))) 12206 : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) 12207 { 12208 PUT_REG_NOTE_KIND (note, REG_DEAD); 12209 place = i3; 12210 } 12211 break; 12212 12213 case REG_EQUAL: 12214 case REG_EQUIV: 12215 case REG_NOALIAS: 12216 /* These notes say something about results of an insn. We can 12217 only support them if they used to be on I3 in which case they 12218 remain on I3. Otherwise they are ignored. 12219 12220 If the note refers to an expression that is not a constant, we 12221 must also ignore the note since we cannot tell whether the 12222 equivalence is still true. It might be possible to do 12223 slightly better than this (we only have a problem if I2DEST 12224 or I1DEST is present in the expression), but it doesn't 12225 seem worth the trouble. */ 12226 12227 if (from_insn == i3 12228 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) 12229 place = i3; 12230 break; 12231 12232 case REG_INC: 12233 case REG_NO_CONFLICT: 12234 /* These notes say something about how a register is used. They must 12235 be present on any use of the register in I2 or I3. */ 12236 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) 12237 place = i3; 12238 12239 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) 12240 { 12241 if (place) 12242 place2 = i2; 12243 else 12244 place = i2; 12245 } 12246 break; 12247 12248 case REG_LABEL: 12249 /* This can show up in several ways -- either directly in the 12250 pattern, or hidden off in the constant pool with (or without?) 12251 a REG_EQUAL note. */ 12252 /* ??? Ignore the without-reg_equal-note problem for now. */ 12253 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) 12254 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX)) 12255 && GET_CODE (XEXP (tem, 0)) == LABEL_REF 12256 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))) 12257 place = i3; 12258 12259 if (i2 12260 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) 12261 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX)) 12262 && GET_CODE (XEXP (tem, 0)) == LABEL_REF 12263 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))) 12264 { 12265 if (place) 12266 place2 = i2; 12267 else 12268 place = i2; 12269 } 12270 12271 /* Don't attach REG_LABEL note to a JUMP_INSN which has 12272 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */ 12273 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place)) 12274 { 12275 if (JUMP_LABEL (place) != XEXP (note, 0)) 12276 abort (); 12277 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL) 12278 LABEL_NUSES (JUMP_LABEL (place))--; 12279 place = 0; 12280 } 12281 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2)) 12282 { 12283 if (JUMP_LABEL (place2) != XEXP (note, 0)) 12284 abort (); 12285 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL) 12286 LABEL_NUSES (JUMP_LABEL (place2))--; 12287 place2 = 0; 12288 } 12289 break; 12290 12291 case REG_NONNEG: 12292 case REG_WAS_0: 12293 /* These notes say something about the value of a register prior 12294 to the execution of an insn. It is too much trouble to see 12295 if the note is still correct in all situations. It is better 12296 to simply delete it. */ 12297 break; 12298 12299 case REG_RETVAL: 12300 /* If the insn previously containing this note still exists, 12301 put it back where it was. Otherwise move it to the previous 12302 insn. Adjust the corresponding REG_LIBCALL note. */ 12303 if (GET_CODE (from_insn) != NOTE) 12304 place = from_insn; 12305 else 12306 { 12307 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX); 12308 place = prev_real_insn (from_insn); 12309 if (tem && place) 12310 XEXP (tem, 0) = place; 12311 /* If we're deleting the last remaining instruction of a 12312 libcall sequence, don't add the notes. */ 12313 else if (XEXP (note, 0) == from_insn) 12314 tem = place = 0; 12315 } 12316 break; 12317 12318 case REG_LIBCALL: 12319 /* This is handled similarly to REG_RETVAL. */ 12320 if (GET_CODE (from_insn) != NOTE) 12321 place = from_insn; 12322 else 12323 { 12324 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX); 12325 place = next_real_insn (from_insn); 12326 if (tem && place) 12327 XEXP (tem, 0) = place; 12328 /* If we're deleting the last remaining instruction of a 12329 libcall sequence, don't add the notes. */ 12330 else if (XEXP (note, 0) == from_insn) 12331 tem = place = 0; 12332 } 12333 break; 12334 12335 case REG_DEAD: 12336 /* If the register is used as an input in I3, it dies there. 12337 Similarly for I2, if it is non-zero and adjacent to I3. 12338 12339 If the register is not used as an input in either I3 or I2 12340 and it is not one of the registers we were supposed to eliminate, 12341 there are two possibilities. We might have a non-adjacent I2 12342 or we might have somehow eliminated an additional register 12343 from a computation. For example, we might have had A & B where 12344 we discover that B will always be zero. In this case we will 12345 eliminate the reference to A. 12346 12347 In both cases, we must search to see if we can find a previous 12348 use of A and put the death note there. */ 12349 12350 if (from_insn 12351 && GET_CODE (from_insn) == CALL_INSN 12352 && find_reg_fusage (from_insn, USE, XEXP (note, 0))) 12353 place = from_insn; 12354 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) 12355 place = i3; 12356 else if (i2 != 0 && next_nonnote_insn (i2) == i3 12357 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 12358 place = i2; 12359 12360 if (rtx_equal_p (XEXP (note, 0), elim_i2) 12361 || rtx_equal_p (XEXP (note, 0), elim_i1)) 12362 break; 12363 12364 if (place == 0) 12365 { 12366 basic_block bb = BASIC_BLOCK (this_basic_block); 12367 12368 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem)) 12369 { 12370 if (! INSN_P (tem)) 12371 { 12372 if (tem == bb->head) 12373 break; 12374 continue; 12375 } 12376 12377 /* If the register is being set at TEM, see if that is all 12378 TEM is doing. If so, delete TEM. Otherwise, make this 12379 into a REG_UNUSED note instead. */ 12380 if (reg_set_p (XEXP (note, 0), PATTERN (tem))) 12381 { 12382 rtx set = single_set (tem); 12383 rtx inner_dest = 0; 12384#ifdef HAVE_cc0 12385 rtx cc0_setter = NULL_RTX; 12386#endif 12387 12388 if (set != 0) 12389 for (inner_dest = SET_DEST (set); 12390 (GET_CODE (inner_dest) == STRICT_LOW_PART 12391 || GET_CODE (inner_dest) == SUBREG 12392 || GET_CODE (inner_dest) == ZERO_EXTRACT); 12393 inner_dest = XEXP (inner_dest, 0)) 12394 ; 12395 12396 /* Verify that it was the set, and not a clobber that 12397 modified the register. 12398 12399 CC0 targets must be careful to maintain setter/user 12400 pairs. If we cannot delete the setter due to side 12401 effects, mark the user with an UNUSED note instead 12402 of deleting it. */ 12403 12404 if (set != 0 && ! side_effects_p (SET_SRC (set)) 12405 && rtx_equal_p (XEXP (note, 0), inner_dest) 12406#ifdef HAVE_cc0 12407 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) 12408 || ((cc0_setter = prev_cc0_setter (tem)) != NULL 12409 && sets_cc0_p (PATTERN (cc0_setter)) > 0)) 12410#endif 12411 ) 12412 { 12413 /* Move the notes and links of TEM elsewhere. 12414 This might delete other dead insns recursively. 12415 First set the pattern to something that won't use 12416 any register. */ 12417 12418 PATTERN (tem) = pc_rtx; 12419 12420 distribute_notes (REG_NOTES (tem), tem, tem, 12421 NULL_RTX, NULL_RTX, NULL_RTX); 12422 distribute_links (LOG_LINKS (tem)); 12423 12424 PUT_CODE (tem, NOTE); 12425 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED; 12426 NOTE_SOURCE_FILE (tem) = 0; 12427 12428#ifdef HAVE_cc0 12429 /* Delete the setter too. */ 12430 if (cc0_setter) 12431 { 12432 PATTERN (cc0_setter) = pc_rtx; 12433 12434 distribute_notes (REG_NOTES (cc0_setter), 12435 cc0_setter, cc0_setter, 12436 NULL_RTX, NULL_RTX, NULL_RTX); 12437 distribute_links (LOG_LINKS (cc0_setter)); 12438 12439 PUT_CODE (cc0_setter, NOTE); 12440 NOTE_LINE_NUMBER (cc0_setter) 12441 = NOTE_INSN_DELETED; 12442 NOTE_SOURCE_FILE (cc0_setter) = 0; 12443 } 12444#endif 12445 } 12446 /* If the register is both set and used here, put the 12447 REG_DEAD note here, but place a REG_UNUSED note 12448 here too unless there already is one. */ 12449 else if (reg_referenced_p (XEXP (note, 0), 12450 PATTERN (tem))) 12451 { 12452 place = tem; 12453 12454 if (! find_regno_note (tem, REG_UNUSED, 12455 REGNO (XEXP (note, 0)))) 12456 REG_NOTES (tem) 12457 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0), 12458 REG_NOTES (tem)); 12459 } 12460 else 12461 { 12462 PUT_REG_NOTE_KIND (note, REG_UNUSED); 12463 12464 /* If there isn't already a REG_UNUSED note, put one 12465 here. */ 12466 if (! find_regno_note (tem, REG_UNUSED, 12467 REGNO (XEXP (note, 0)))) 12468 place = tem; 12469 break; 12470 } 12471 } 12472 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)) 12473 || (GET_CODE (tem) == CALL_INSN 12474 && find_reg_fusage (tem, USE, XEXP (note, 0)))) 12475 { 12476 place = tem; 12477 12478 /* If we are doing a 3->2 combination, and we have a 12479 register which formerly died in i3 and was not used 12480 by i2, which now no longer dies in i3 and is used in 12481 i2 but does not die in i2, and place is between i2 12482 and i3, then we may need to move a link from place to 12483 i2. */ 12484 if (i2 && INSN_UID (place) <= max_uid_cuid 12485 && INSN_CUID (place) > INSN_CUID (i2) 12486 && from_insn 12487 && INSN_CUID (from_insn) > INSN_CUID (i2) 12488 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 12489 { 12490 rtx links = LOG_LINKS (place); 12491 LOG_LINKS (place) = 0; 12492 distribute_links (links); 12493 } 12494 break; 12495 } 12496 12497 if (tem == bb->head) 12498 break; 12499 } 12500 12501 /* We haven't found an insn for the death note and it 12502 is still a REG_DEAD note, but we have hit the beginning 12503 of the block. If the existing life info says the reg 12504 was dead, there's nothing left to do. Otherwise, we'll 12505 need to do a global life update after combine. */ 12506 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 12507 && REGNO_REG_SET_P (bb->global_live_at_start, 12508 REGNO (XEXP (note, 0)))) 12509 { 12510 SET_BIT (refresh_blocks, this_basic_block); 12511 need_refresh = 1; 12512 } 12513 } 12514 12515 /* If the register is set or already dead at PLACE, we needn't do 12516 anything with this note if it is still a REG_DEAD note. 12517 We can here if it is set at all, not if is it totally replace, 12518 which is what `dead_or_set_p' checks, so also check for it being 12519 set partially. */ 12520 12521 if (place && REG_NOTE_KIND (note) == REG_DEAD) 12522 { 12523 unsigned int regno = REGNO (XEXP (note, 0)); 12524 12525 /* Similarly, if the instruction on which we want to place 12526 the note is a noop, we'll need do a global live update 12527 after we remove them in delete_noop_moves. */ 12528 if (noop_move_p (place)) 12529 { 12530 SET_BIT (refresh_blocks, this_basic_block); 12531 need_refresh = 1; 12532 } 12533 12534 if (dead_or_set_p (place, XEXP (note, 0)) 12535 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) 12536 { 12537 /* Unless the register previously died in PLACE, clear 12538 reg_last_death. [I no longer understand why this is 12539 being done.] */ 12540 if (reg_last_death[regno] != place) 12541 reg_last_death[regno] = 0; 12542 place = 0; 12543 } 12544 else 12545 reg_last_death[regno] = place; 12546 12547 /* If this is a death note for a hard reg that is occupying 12548 multiple registers, ensure that we are still using all 12549 parts of the object. If we find a piece of the object 12550 that is unused, we must arrange for an appropriate REG_DEAD 12551 note to be added for it. However, we can't just emit a USE 12552 and tag the note to it, since the register might actually 12553 be dead; so we recourse, and the recursive call then finds 12554 the previous insn that used this register. */ 12555 12556 if (place && regno < FIRST_PSEUDO_REGISTER 12557 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1) 12558 { 12559 unsigned int endregno 12560 = regno + HARD_REGNO_NREGS (regno, 12561 GET_MODE (XEXP (note, 0))); 12562 int all_used = 1; 12563 unsigned int i; 12564 12565 for (i = regno; i < endregno; i++) 12566 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0) 12567 && ! find_regno_fusage (place, USE, i)) 12568 || dead_or_set_regno_p (place, i)) 12569 all_used = 0; 12570 12571 if (! all_used) 12572 { 12573 /* Put only REG_DEAD notes for pieces that are 12574 not already dead or set. */ 12575 12576 for (i = regno; i < endregno; 12577 i += HARD_REGNO_NREGS (i, reg_raw_mode[i])) 12578 { 12579 rtx piece = gen_rtx_REG (reg_raw_mode[i], i); 12580 basic_block bb = BASIC_BLOCK (this_basic_block); 12581 12582 if (! dead_or_set_p (place, piece) 12583 && ! reg_bitfield_target_p (piece, 12584 PATTERN (place))) 12585 { 12586 rtx new_note 12587 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX); 12588 12589 distribute_notes (new_note, place, place, 12590 NULL_RTX, NULL_RTX, NULL_RTX); 12591 } 12592 else if (! refers_to_regno_p (i, i + 1, 12593 PATTERN (place), 0) 12594 && ! find_regno_fusage (place, USE, i)) 12595 for (tem = PREV_INSN (place); ; 12596 tem = PREV_INSN (tem)) 12597 { 12598 if (! INSN_P (tem)) 12599 { 12600 if (tem == bb->head) 12601 { 12602 SET_BIT (refresh_blocks, 12603 this_basic_block); 12604 need_refresh = 1; 12605 break; 12606 } 12607 continue; 12608 } 12609 if (dead_or_set_p (tem, piece) 12610 || reg_bitfield_target_p (piece, 12611 PATTERN (tem))) 12612 { 12613 REG_NOTES (tem) 12614 = gen_rtx_EXPR_LIST (REG_UNUSED, piece, 12615 REG_NOTES (tem)); 12616 break; 12617 } 12618 } 12619 12620 } 12621 12622 place = 0; 12623 } 12624 } 12625 } 12626 break; 12627 12628 default: 12629 /* Any other notes should not be present at this point in the 12630 compilation. */ 12631 abort (); 12632 } 12633 12634 if (place) 12635 { 12636 XEXP (note, 1) = REG_NOTES (place); 12637 REG_NOTES (place) = note; 12638 } 12639 else if ((REG_NOTE_KIND (note) == REG_DEAD 12640 || REG_NOTE_KIND (note) == REG_UNUSED) 12641 && GET_CODE (XEXP (note, 0)) == REG) 12642 REG_N_DEATHS (REGNO (XEXP (note, 0)))--; 12643 12644 if (place2) 12645 { 12646 if ((REG_NOTE_KIND (note) == REG_DEAD 12647 || REG_NOTE_KIND (note) == REG_UNUSED) 12648 && GET_CODE (XEXP (note, 0)) == REG) 12649 REG_N_DEATHS (REGNO (XEXP (note, 0)))++; 12650 12651 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note), 12652 REG_NOTE_KIND (note), 12653 XEXP (note, 0), 12654 REG_NOTES (place2)); 12655 } 12656 } 12657} 12658 12659/* Similarly to above, distribute the LOG_LINKS that used to be present on 12660 I3, I2, and I1 to new locations. This is also called in one case to 12661 add a link pointing at I3 when I3's destination is changed. */ 12662 12663static void 12664distribute_links (links) 12665 rtx links; 12666{ 12667 rtx link, next_link; 12668 12669 for (link = links; link; link = next_link) 12670 { 12671 rtx place = 0; 12672 rtx insn; 12673 rtx set, reg; 12674 12675 next_link = XEXP (link, 1); 12676 12677 /* If the insn that this link points to is a NOTE or isn't a single 12678 set, ignore it. In the latter case, it isn't clear what we 12679 can do other than ignore the link, since we can't tell which 12680 register it was for. Such links wouldn't be used by combine 12681 anyway. 12682 12683 It is not possible for the destination of the target of the link to 12684 have been changed by combine. The only potential of this is if we 12685 replace I3, I2, and I1 by I3 and I2. But in that case the 12686 destination of I2 also remains unchanged. */ 12687 12688 if (GET_CODE (XEXP (link, 0)) == NOTE 12689 || (set = single_set (XEXP (link, 0))) == 0) 12690 continue; 12691 12692 reg = SET_DEST (set); 12693 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT 12694 || GET_CODE (reg) == SIGN_EXTRACT 12695 || GET_CODE (reg) == STRICT_LOW_PART) 12696 reg = XEXP (reg, 0); 12697 12698 /* A LOG_LINK is defined as being placed on the first insn that uses 12699 a register and points to the insn that sets the register. Start 12700 searching at the next insn after the target of the link and stop 12701 when we reach a set of the register or the end of the basic block. 12702 12703 Note that this correctly handles the link that used to point from 12704 I3 to I2. Also note that not much searching is typically done here 12705 since most links don't point very far away. */ 12706 12707 for (insn = NEXT_INSN (XEXP (link, 0)); 12708 (insn && (this_basic_block == n_basic_blocks - 1 12709 || BLOCK_HEAD (this_basic_block + 1) != insn)); 12710 insn = NEXT_INSN (insn)) 12711 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn))) 12712 { 12713 if (reg_referenced_p (reg, PATTERN (insn))) 12714 place = insn; 12715 break; 12716 } 12717 else if (GET_CODE (insn) == CALL_INSN 12718 && find_reg_fusage (insn, USE, reg)) 12719 { 12720 place = insn; 12721 break; 12722 } 12723 12724 /* If we found a place to put the link, place it there unless there 12725 is already a link to the same insn as LINK at that point. */ 12726 12727 if (place) 12728 { 12729 rtx link2; 12730 12731 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1)) 12732 if (XEXP (link2, 0) == XEXP (link, 0)) 12733 break; 12734 12735 if (link2 == 0) 12736 { 12737 XEXP (link, 1) = LOG_LINKS (place); 12738 LOG_LINKS (place) = link; 12739 12740 /* Set added_links_insn to the earliest insn we added a 12741 link to. */ 12742 if (added_links_insn == 0 12743 || INSN_CUID (added_links_insn) > INSN_CUID (place)) 12744 added_links_insn = place; 12745 } 12746 } 12747 } 12748} 12749 12750/* Compute INSN_CUID for INSN, which is an insn made by combine. */ 12751 12752static int 12753insn_cuid (insn) 12754 rtx insn; 12755{ 12756 while (insn != 0 && INSN_UID (insn) > max_uid_cuid 12757 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE) 12758 insn = NEXT_INSN (insn); 12759 12760 if (INSN_UID (insn) > max_uid_cuid) 12761 abort (); 12762 12763 return INSN_CUID (insn); 12764} 12765 12766void 12767dump_combine_stats (file) 12768 FILE *file; 12769{ 12770 fnotice 12771 (file, 12772 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", 12773 combine_attempts, combine_merges, combine_extras, combine_successes); 12774} 12775 12776void 12777dump_combine_total_stats (file) 12778 FILE *file; 12779{ 12780 fnotice 12781 (file, 12782 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", 12783 total_attempts, total_merges, total_extras, total_successes); 12784} 12785