1/* Optimize by combining instructions for GNU compiler. 2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify it under 8the terms of the GNU General Public License as published by the Free 9Software Foundation; either version 2, or (at your option) any later 10version. 11 12GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13WARRANTY; without even the implied warranty of MERCHANTABILITY or 14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to the Free 19Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 2002110-1301, USA. */ 21 22/* This module is essentially the "combiner" phase of the U. of Arizona 23 Portable Optimizer, but redone to work on our list-structured 24 representation for RTL instead of their string representation. 25 26 The LOG_LINKS of each insn identify the most recent assignment 27 to each REG used in the insn. It is a list of previous insns, 28 each of which contains a SET for a REG that is used in this insn 29 and not used or set in between. LOG_LINKs never cross basic blocks. 30 They were set up by the preceding pass (lifetime analysis). 31 32 We try to combine each pair of insns joined by a logical link. 33 We also try to combine triples of insns A, B and C when 34 C has a link back to B and B has a link back to A. 35 36 LOG_LINKS does not have links for use of the CC0. They don't 37 need to, because the insn that sets the CC0 is always immediately 38 before the insn that tests it. So we always regard a branch 39 insn as having a logical link to the preceding insn. The same is true 40 for an insn explicitly using CC0. 41 42 We check (with use_crosses_set_p) to avoid combining in such a way 43 as to move a computation to a place where its value would be different. 44 45 Combination is done by mathematically substituting the previous 46 insn(s) values for the regs they set into the expressions in 47 the later insns that refer to these regs. If the result is a valid insn 48 for our target machine, according to the machine description, 49 we install it, delete the earlier insns, and update the data flow 50 information (LOG_LINKS and REG_NOTES) for what we did. 51 52 There are a few exceptions where the dataflow information created by 53 flow.c aren't completely updated: 54 55 - reg_live_length is not updated 56 - reg_n_refs is not adjusted in the rare case when a register is 57 no longer required in a computation 58 - there are extremely rare cases (see distribute_notes) when a 59 REG_DEAD note is lost 60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be 61 removed because there is no way to know which register it was 62 linking 63 64 To simplify substitution, we combine only when the earlier insn(s) 65 consist of only a single assignment. To simplify updating afterward, 66 we never combine when a subroutine call appears in the middle. 67 68 Since we do not represent assignments to CC0 explicitly except when that 69 is all an insn does, there is no LOG_LINKS entry in an insn that uses 70 the condition code for the insn that set the condition code. 71 Fortunately, these two insns must be consecutive. 72 Therefore, every JUMP_INSN is taken to have an implicit logical link 73 to the preceding insn. This is not quite right, since non-jumps can 74 also use the condition code; but in practice such insns would not 75 combine anyway. */ 76 77#include "config.h" 78#include "system.h" 79#include "coretypes.h" 80#include "tm.h" 81#include "rtl.h" 82#include "tree.h" 83#include "tm_p.h" 84#include "flags.h" 85#include "regs.h" 86#include "hard-reg-set.h" 87#include "basic-block.h" 88#include "insn-config.h" 89#include "function.h" 90/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ 91#include "expr.h" 92#include "insn-attr.h" 93#include "recog.h" 94#include "real.h" 95#include "toplev.h" 96#include "target.h" 97#include "optabs.h" 98#include "insn-codes.h" 99#include "rtlhooks-def.h" 100/* Include output.h for dump_file. */ 101#include "output.h" 102#include "params.h" 103#include "timevar.h" 104#include "tree-pass.h" 105 106/* Number of attempts to combine instructions in this function. */ 107 108static int combine_attempts; 109 110/* Number of attempts that got as far as substitution in this function. */ 111 112static int combine_merges; 113 114/* Number of instructions combined with added SETs in this function. */ 115 116static int combine_extras; 117 118/* Number of instructions combined in this function. */ 119 120static int combine_successes; 121 122/* Totals over entire compilation. */ 123 124static int total_attempts, total_merges, total_extras, total_successes; 125 126/* combine_instructions may try to replace the right hand side of the 127 second instruction with the value of an associated REG_EQUAL note 128 before throwing it at try_combine. That is problematic when there 129 is a REG_DEAD note for a register used in the old right hand side 130 and can cause distribute_notes to do wrong things. This is the 131 second instruction if it has been so modified, null otherwise. */ 132 133static rtx i2mod; 134 135/* When I2MOD is nonnull, this is a copy of the old right hand side. */ 136 137static rtx i2mod_old_rhs; 138 139/* When I2MOD is nonnull, this is a copy of the new right hand side. */ 140 141static rtx i2mod_new_rhs; 142 143/* Vector mapping INSN_UIDs to cuids. 144 The cuids are like uids but increase monotonically always. 145 Combine always uses cuids so that it can compare them. 146 But actually renumbering the uids, which we used to do, 147 proves to be a bad idea because it makes it hard to compare 148 the dumps produced by earlier passes with those from later passes. */ 149 150static int *uid_cuid; 151static int max_uid_cuid; 152 153/* Get the cuid of an insn. */ 154 155#define INSN_CUID(INSN) \ 156(INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)]) 157 158/* Maximum register number, which is the size of the tables below. */ 159 160static unsigned int combine_max_regno; 161 162struct reg_stat { 163 /* Record last point of death of (hard or pseudo) register n. */ 164 rtx last_death; 165 166 /* Record last point of modification of (hard or pseudo) register n. */ 167 rtx last_set; 168 169 /* The next group of fields allows the recording of the last value assigned 170 to (hard or pseudo) register n. We use this information to see if an 171 operation being processed is redundant given a prior operation performed 172 on the register. For example, an `and' with a constant is redundant if 173 all the zero bits are already known to be turned off. 174 175 We use an approach similar to that used by cse, but change it in the 176 following ways: 177 178 (1) We do not want to reinitialize at each label. 179 (2) It is useful, but not critical, to know the actual value assigned 180 to a register. Often just its form is helpful. 181 182 Therefore, we maintain the following fields: 183 184 last_set_value the last value assigned 185 last_set_label records the value of label_tick when the 186 register was assigned 187 last_set_table_tick records the value of label_tick when a 188 value using the register is assigned 189 last_set_invalid set to nonzero when it is not valid 190 to use the value of this register in some 191 register's value 192 193 To understand the usage of these tables, it is important to understand 194 the distinction between the value in last_set_value being valid and 195 the register being validly contained in some other expression in the 196 table. 197 198 (The next two parameters are out of date). 199 200 reg_stat[i].last_set_value is valid if it is nonzero, and either 201 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick. 202 203 Register I may validly appear in any expression returned for the value 204 of another register if reg_n_sets[i] is 1. It may also appear in the 205 value for register J if reg_stat[j].last_set_invalid is zero, or 206 reg_stat[i].last_set_label < reg_stat[j].last_set_label. 207 208 If an expression is found in the table containing a register which may 209 not validly appear in an expression, the register is replaced by 210 something that won't match, (clobber (const_int 0)). */ 211 212 /* Record last value assigned to (hard or pseudo) register n. */ 213 214 rtx last_set_value; 215 216 /* Record the value of label_tick when an expression involving register n 217 is placed in last_set_value. */ 218 219 int last_set_table_tick; 220 221 /* Record the value of label_tick when the value for register n is placed in 222 last_set_value. */ 223 224 int last_set_label; 225 226 /* These fields are maintained in parallel with last_set_value and are 227 used to store the mode in which the register was last set, the bits 228 that were known to be zero when it was last set, and the number of 229 sign bits copies it was known to have when it was last set. */ 230 231 unsigned HOST_WIDE_INT last_set_nonzero_bits; 232 char last_set_sign_bit_copies; 233 ENUM_BITFIELD(machine_mode) last_set_mode : 8; 234 235 /* Set nonzero if references to register n in expressions should not be 236 used. last_set_invalid is set nonzero when this register is being 237 assigned to and last_set_table_tick == label_tick. */ 238 239 char last_set_invalid; 240 241 /* Some registers that are set more than once and used in more than one 242 basic block are nevertheless always set in similar ways. For example, 243 a QImode register may be loaded from memory in two places on a machine 244 where byte loads zero extend. 245 246 We record in the following fields if a register has some leading bits 247 that are always equal to the sign bit, and what we know about the 248 nonzero bits of a register, specifically which bits are known to be 249 zero. 250 251 If an entry is zero, it means that we don't know anything special. */ 252 253 unsigned char sign_bit_copies; 254 255 unsigned HOST_WIDE_INT nonzero_bits; 256 257 /* Record the value of the label_tick when the last truncation 258 happened. The field truncated_to_mode is only valid if 259 truncation_label == label_tick. */ 260 261 int truncation_label; 262 263 /* Record the last truncation seen for this register. If truncation 264 is not a nop to this mode we might be able to save an explicit 265 truncation if we know that value already contains a truncated 266 value. */ 267 268 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8; 269}; 270 271static struct reg_stat *reg_stat; 272 273/* Record the cuid of the last insn that invalidated memory 274 (anything that writes memory, and subroutine calls, but not pushes). */ 275 276static int mem_last_set; 277 278/* Record the cuid of the last CALL_INSN 279 so we can tell whether a potential combination crosses any calls. */ 280 281static int last_call_cuid; 282 283/* When `subst' is called, this is the insn that is being modified 284 (by combining in a previous insn). The PATTERN of this insn 285 is still the old pattern partially modified and it should not be 286 looked at, but this may be used to examine the successors of the insn 287 to judge whether a simplification is valid. */ 288 289static rtx subst_insn; 290 291/* This is the lowest CUID that `subst' is currently dealing with. 292 get_last_value will not return a value if the register was set at or 293 after this CUID. If not for this mechanism, we could get confused if 294 I2 or I1 in try_combine were an insn that used the old value of a register 295 to obtain a new value. In that case, we might erroneously get the 296 new value of the register when we wanted the old one. */ 297 298static int subst_low_cuid; 299 300/* This contains any hard registers that are used in newpat; reg_dead_at_p 301 must consider all these registers to be always live. */ 302 303static HARD_REG_SET newpat_used_regs; 304 305/* This is an insn to which a LOG_LINKS entry has been added. If this 306 insn is the earlier than I2 or I3, combine should rescan starting at 307 that location. */ 308 309static rtx added_links_insn; 310 311/* Basic block in which we are performing combines. */ 312static basic_block this_basic_block; 313 314/* A bitmap indicating which blocks had registers go dead at entry. 315 After combine, we'll need to re-do global life analysis with 316 those blocks as starting points. */ 317static sbitmap refresh_blocks; 318 319/* The following array records the insn_rtx_cost for every insn 320 in the instruction stream. */ 321 322static int *uid_insn_cost; 323 324/* Length of the currently allocated uid_insn_cost array. */ 325 326static int last_insn_cost; 327 328/* Incremented for each label. */ 329 330static int label_tick; 331 332/* Mode used to compute significance in reg_stat[].nonzero_bits. It is the 333 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ 334 335static enum machine_mode nonzero_bits_mode; 336 337/* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can 338 be safely used. It is zero while computing them and after combine has 339 completed. This former test prevents propagating values based on 340 previously set values, which can be incorrect if a variable is modified 341 in a loop. */ 342 343static int nonzero_sign_valid; 344 345 346/* Record one modification to rtl structure 347 to be undone by storing old_contents into *where. */ 348 349struct undo 350{ 351 struct undo *next; 352 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind; 353 union { rtx r; int i; enum machine_mode m; } old_contents; 354 union { rtx *r; int *i; } where; 355}; 356 357/* Record a bunch of changes to be undone, up to MAX_UNDO of them. 358 num_undo says how many are currently recorded. 359 360 other_insn is nonzero if we have modified some other insn in the process 361 of working on subst_insn. It must be verified too. */ 362 363struct undobuf 364{ 365 struct undo *undos; 366 struct undo *frees; 367 rtx other_insn; 368}; 369 370static struct undobuf undobuf; 371 372/* Number of times the pseudo being substituted for 373 was found and replaced. */ 374 375static int n_occurrences; 376 377static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx, 378 enum machine_mode, 379 unsigned HOST_WIDE_INT, 380 unsigned HOST_WIDE_INT *); 381static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx, 382 enum machine_mode, 383 unsigned int, unsigned int *); 384static void do_SUBST (rtx *, rtx); 385static void do_SUBST_INT (int *, int); 386static void init_reg_last (void); 387static void setup_incoming_promotions (void); 388static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *); 389static int cant_combine_insn_p (rtx); 390static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *); 391static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *); 392static int contains_muldiv (rtx); 393static rtx try_combine (rtx, rtx, rtx, int *); 394static void undo_all (void); 395static void undo_commit (void); 396static rtx *find_split_point (rtx *, rtx); 397static rtx subst (rtx, rtx, rtx, int, int); 398static rtx combine_simplify_rtx (rtx, enum machine_mode, int); 399static rtx simplify_if_then_else (rtx); 400static rtx simplify_set (rtx); 401static rtx simplify_logical (rtx); 402static rtx expand_compound_operation (rtx); 403static rtx expand_field_assignment (rtx); 404static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT, 405 rtx, unsigned HOST_WIDE_INT, int, int, int); 406static rtx extract_left_shift (rtx, int); 407static rtx make_compound_operation (rtx, enum rtx_code); 408static int get_pos_from_mask (unsigned HOST_WIDE_INT, 409 unsigned HOST_WIDE_INT *); 410static rtx canon_reg_for_combine (rtx, rtx); 411static rtx force_to_mode (rtx, enum machine_mode, 412 unsigned HOST_WIDE_INT, int); 413static rtx if_then_else_cond (rtx, rtx *, rtx *); 414static rtx known_cond (rtx, enum rtx_code, rtx, rtx); 415static int rtx_equal_for_field_assignment_p (rtx, rtx); 416static rtx make_field_assignment (rtx); 417static rtx apply_distributive_law (rtx); 418static rtx distribute_and_simplify_rtx (rtx, int); 419static rtx simplify_and_const_int_1 (enum machine_mode, rtx, 420 unsigned HOST_WIDE_INT); 421static rtx simplify_and_const_int (rtx, enum machine_mode, rtx, 422 unsigned HOST_WIDE_INT); 423static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code, 424 HOST_WIDE_INT, enum machine_mode, int *); 425static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int); 426static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx, 427 int); 428static int recog_for_combine (rtx *, rtx, rtx *); 429static rtx gen_lowpart_for_combine (enum machine_mode, rtx); 430static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *); 431static void update_table_tick (rtx); 432static void record_value_for_reg (rtx, rtx, rtx); 433static void check_conversions (rtx, rtx); 434static void record_dead_and_set_regs_1 (rtx, rtx, void *); 435static void record_dead_and_set_regs (rtx); 436static int get_last_value_validate (rtx *, rtx, int, int); 437static rtx get_last_value (rtx); 438static int use_crosses_set_p (rtx, int); 439static void reg_dead_at_p_1 (rtx, rtx, void *); 440static int reg_dead_at_p (rtx, rtx); 441static void move_deaths (rtx, rtx, int, rtx, rtx *); 442static int reg_bitfield_target_p (rtx, rtx); 443static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx); 444static void distribute_links (rtx); 445static void mark_used_regs_combine (rtx); 446static int insn_cuid (rtx); 447static void record_promoted_value (rtx, rtx); 448static int unmentioned_reg_p_1 (rtx *, void *); 449static bool unmentioned_reg_p (rtx, rtx); 450static void record_truncated_value (rtx); 451static bool reg_truncated_to_mode (enum machine_mode, rtx); 452static rtx gen_lowpart_or_truncate (enum machine_mode, rtx); 453 454 455/* It is not safe to use ordinary gen_lowpart in combine. 456 See comments in gen_lowpart_for_combine. */ 457#undef RTL_HOOKS_GEN_LOWPART 458#define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine 459 460/* Our implementation of gen_lowpart never emits a new pseudo. */ 461#undef RTL_HOOKS_GEN_LOWPART_NO_EMIT 462#define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine 463 464#undef RTL_HOOKS_REG_NONZERO_REG_BITS 465#define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine 466 467#undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES 468#define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine 469 470#undef RTL_HOOKS_REG_TRUNCATED_TO_MODE 471#define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode 472 473static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER; 474 475 476/* Substitute NEWVAL, an rtx expression, into INTO, a place in some 477 insn. The substitution can be undone by undo_all. If INTO is already 478 set to NEWVAL, do not record this change. Because computing NEWVAL might 479 also call SUBST, we have to compute it before we put anything into 480 the undo table. */ 481 482static void 483do_SUBST (rtx *into, rtx newval) 484{ 485 struct undo *buf; 486 rtx oldval = *into; 487 488 if (oldval == newval) 489 return; 490 491 /* We'd like to catch as many invalid transformations here as 492 possible. Unfortunately, there are way too many mode changes 493 that are perfectly valid, so we'd waste too much effort for 494 little gain doing the checks here. Focus on catching invalid 495 transformations involving integer constants. */ 496 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT 497 && GET_CODE (newval) == CONST_INT) 498 { 499 /* Sanity check that we're replacing oldval with a CONST_INT 500 that is a valid sign-extension for the original mode. */ 501 gcc_assert (INTVAL (newval) 502 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval))); 503 504 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a 505 CONST_INT is not valid, because after the replacement, the 506 original mode would be gone. Unfortunately, we can't tell 507 when do_SUBST is called to replace the operand thereof, so we 508 perform this test on oldval instead, checking whether an 509 invalid replacement took place before we got here. */ 510 gcc_assert (!(GET_CODE (oldval) == SUBREG 511 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)); 512 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND 513 && GET_CODE (XEXP (oldval, 0)) == CONST_INT)); 514 } 515 516 if (undobuf.frees) 517 buf = undobuf.frees, undobuf.frees = buf->next; 518 else 519 buf = XNEW (struct undo); 520 521 buf->kind = UNDO_RTX; 522 buf->where.r = into; 523 buf->old_contents.r = oldval; 524 *into = newval; 525 526 buf->next = undobuf.undos, undobuf.undos = buf; 527} 528 529#define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL)) 530 531/* Similar to SUBST, but NEWVAL is an int expression. Note that substitution 532 for the value of a HOST_WIDE_INT value (including CONST_INT) is 533 not safe. */ 534 535static void 536do_SUBST_INT (int *into, int newval) 537{ 538 struct undo *buf; 539 int oldval = *into; 540 541 if (oldval == newval) 542 return; 543 544 if (undobuf.frees) 545 buf = undobuf.frees, undobuf.frees = buf->next; 546 else 547 buf = XNEW (struct undo); 548 549 buf->kind = UNDO_INT; 550 buf->where.i = into; 551 buf->old_contents.i = oldval; 552 *into = newval; 553 554 buf->next = undobuf.undos, undobuf.undos = buf; 555} 556 557#define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL)) 558 559/* Similar to SUBST, but just substitute the mode. This is used when 560 changing the mode of a pseudo-register, so that any other 561 references to the entry in the regno_reg_rtx array will change as 562 well. */ 563 564static void 565do_SUBST_MODE (rtx *into, enum machine_mode newval) 566{ 567 struct undo *buf; 568 enum machine_mode oldval = GET_MODE (*into); 569 570 if (oldval == newval) 571 return; 572 573 if (undobuf.frees) 574 buf = undobuf.frees, undobuf.frees = buf->next; 575 else 576 buf = XNEW (struct undo); 577 578 buf->kind = UNDO_MODE; 579 buf->where.r = into; 580 buf->old_contents.m = oldval; 581 PUT_MODE (*into, newval); 582 583 buf->next = undobuf.undos, undobuf.undos = buf; 584} 585 586#define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL)) 587 588/* Subroutine of try_combine. Determine whether the combine replacement 589 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost 590 that the original instruction sequence I1, I2 and I3. Note that I1 591 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the 592 costs of all instructions can be estimated, and the replacements are 593 more expensive than the original sequence. */ 594 595static bool 596combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat) 597{ 598 int i1_cost, i2_cost, i3_cost; 599 int new_i2_cost, new_i3_cost; 600 int old_cost, new_cost; 601 602 /* Lookup the original insn_rtx_costs. */ 603 i2_cost = INSN_UID (i2) <= last_insn_cost 604 ? uid_insn_cost[INSN_UID (i2)] : 0; 605 i3_cost = INSN_UID (i3) <= last_insn_cost 606 ? uid_insn_cost[INSN_UID (i3)] : 0; 607 608 if (i1) 609 { 610 i1_cost = INSN_UID (i1) <= last_insn_cost 611 ? uid_insn_cost[INSN_UID (i1)] : 0; 612 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0) 613 ? i1_cost + i2_cost + i3_cost : 0; 614 } 615 else 616 { 617 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0; 618 i1_cost = 0; 619 } 620 621 /* Calculate the replacement insn_rtx_costs. */ 622 new_i3_cost = insn_rtx_cost (newpat); 623 if (newi2pat) 624 { 625 new_i2_cost = insn_rtx_cost (newi2pat); 626 new_cost = (new_i2_cost > 0 && new_i3_cost > 0) 627 ? new_i2_cost + new_i3_cost : 0; 628 } 629 else 630 { 631 new_cost = new_i3_cost; 632 new_i2_cost = 0; 633 } 634 635 if (undobuf.other_insn) 636 { 637 int old_other_cost, new_other_cost; 638 639 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost 640 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0); 641 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn)); 642 if (old_other_cost > 0 && new_other_cost > 0) 643 { 644 old_cost += old_other_cost; 645 new_cost += new_other_cost; 646 } 647 else 648 old_cost = 0; 649 } 650 651 /* Disallow this recombination if both new_cost and old_cost are 652 greater than zero, and new_cost is greater than old cost. */ 653 if (old_cost > 0 654 && new_cost > old_cost) 655 { 656 if (dump_file) 657 { 658 if (i1) 659 { 660 fprintf (dump_file, 661 "rejecting combination of insns %d, %d and %d\n", 662 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); 663 fprintf (dump_file, "original costs %d + %d + %d = %d\n", 664 i1_cost, i2_cost, i3_cost, old_cost); 665 } 666 else 667 { 668 fprintf (dump_file, 669 "rejecting combination of insns %d and %d\n", 670 INSN_UID (i2), INSN_UID (i3)); 671 fprintf (dump_file, "original costs %d + %d = %d\n", 672 i2_cost, i3_cost, old_cost); 673 } 674 675 if (newi2pat) 676 { 677 fprintf (dump_file, "replacement costs %d + %d = %d\n", 678 new_i2_cost, new_i3_cost, new_cost); 679 } 680 else 681 fprintf (dump_file, "replacement cost %d\n", new_cost); 682 } 683 684 return false; 685 } 686 687 /* Update the uid_insn_cost array with the replacement costs. */ 688 uid_insn_cost[INSN_UID (i2)] = new_i2_cost; 689 uid_insn_cost[INSN_UID (i3)] = new_i3_cost; 690 if (i1) 691 uid_insn_cost[INSN_UID (i1)] = 0; 692 693 return true; 694} 695 696/* Main entry point for combiner. F is the first insn of the function. 697 NREGS is the first unused pseudo-reg number. 698 699 Return nonzero if the combiner has turned an indirect jump 700 instruction into a direct jump. */ 701static int 702combine_instructions (rtx f, unsigned int nregs) 703{ 704 rtx insn, next; 705#ifdef HAVE_cc0 706 rtx prev; 707#endif 708 int i; 709 unsigned int j = 0; 710 rtx links, nextlinks; 711 sbitmap_iterator sbi; 712 713 int new_direct_jump_p = 0; 714 715 combine_attempts = 0; 716 combine_merges = 0; 717 combine_extras = 0; 718 combine_successes = 0; 719 720 combine_max_regno = nregs; 721 722 rtl_hooks = combine_rtl_hooks; 723 724 reg_stat = XCNEWVEC (struct reg_stat, nregs); 725 726 init_recog_no_volatile (); 727 728 /* Compute maximum uid value so uid_cuid can be allocated. */ 729 730 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) 731 if (INSN_UID (insn) > i) 732 i = INSN_UID (insn); 733 734 uid_cuid = XNEWVEC (int, i + 1); 735 max_uid_cuid = i; 736 737 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); 738 739 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause 740 problems when, for example, we have j <<= 1 in a loop. */ 741 742 nonzero_sign_valid = 0; 743 744 /* Compute the mapping from uids to cuids. 745 Cuids are numbers assigned to insns, like uids, 746 except that cuids increase monotonically through the code. 747 748 Scan all SETs and see if we can deduce anything about what 749 bits are known to be zero for some registers and how many copies 750 of the sign bit are known to exist for those registers. 751 752 Also set any known values so that we can use it while searching 753 for what bits are known to be set. */ 754 755 label_tick = 1; 756 757 setup_incoming_promotions (); 758 759 refresh_blocks = sbitmap_alloc (last_basic_block); 760 sbitmap_zero (refresh_blocks); 761 762 /* Allocate array of current insn_rtx_costs. */ 763 uid_insn_cost = XCNEWVEC (int, max_uid_cuid + 1); 764 last_insn_cost = max_uid_cuid; 765 766 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) 767 { 768 uid_cuid[INSN_UID (insn)] = ++i; 769 subst_low_cuid = i; 770 subst_insn = insn; 771 772 if (INSN_P (insn)) 773 { 774 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies, 775 NULL); 776 record_dead_and_set_regs (insn); 777 778#ifdef AUTO_INC_DEC 779 for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) 780 if (REG_NOTE_KIND (links) == REG_INC) 781 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX, 782 NULL); 783#endif 784 785 /* Record the current insn_rtx_cost of this instruction. */ 786 if (NONJUMP_INSN_P (insn)) 787 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn)); 788 if (dump_file) 789 fprintf(dump_file, "insn_cost %d: %d\n", 790 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]); 791 } 792 793 if (LABEL_P (insn)) 794 label_tick++; 795 } 796 797 nonzero_sign_valid = 1; 798 799 /* Now scan all the insns in forward order. */ 800 801 label_tick = 1; 802 last_call_cuid = 0; 803 mem_last_set = 0; 804 init_reg_last (); 805 setup_incoming_promotions (); 806 807 FOR_EACH_BB (this_basic_block) 808 { 809 for (insn = BB_HEAD (this_basic_block); 810 insn != NEXT_INSN (BB_END (this_basic_block)); 811 insn = next ? next : NEXT_INSN (insn)) 812 { 813 next = 0; 814 815 if (LABEL_P (insn)) 816 label_tick++; 817 818 else if (INSN_P (insn)) 819 { 820 /* See if we know about function return values before this 821 insn based upon SUBREG flags. */ 822 check_conversions (insn, PATTERN (insn)); 823 824 /* Try this insn with each insn it links back to. */ 825 826 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 827 if ((next = try_combine (insn, XEXP (links, 0), 828 NULL_RTX, &new_direct_jump_p)) != 0) 829 goto retry; 830 831 /* Try each sequence of three linked insns ending with this one. */ 832 833 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 834 { 835 rtx link = XEXP (links, 0); 836 837 /* If the linked insn has been replaced by a note, then there 838 is no point in pursuing this chain any further. */ 839 if (NOTE_P (link)) 840 continue; 841 842 for (nextlinks = LOG_LINKS (link); 843 nextlinks; 844 nextlinks = XEXP (nextlinks, 1)) 845 if ((next = try_combine (insn, link, 846 XEXP (nextlinks, 0), 847 &new_direct_jump_p)) != 0) 848 goto retry; 849 } 850 851#ifdef HAVE_cc0 852 /* Try to combine a jump insn that uses CC0 853 with a preceding insn that sets CC0, and maybe with its 854 logical predecessor as well. 855 This is how we make decrement-and-branch insns. 856 We need this special code because data flow connections 857 via CC0 do not get entered in LOG_LINKS. */ 858 859 if (JUMP_P (insn) 860 && (prev = prev_nonnote_insn (insn)) != 0 861 && NONJUMP_INSN_P (prev) 862 && sets_cc0_p (PATTERN (prev))) 863 { 864 if ((next = try_combine (insn, prev, 865 NULL_RTX, &new_direct_jump_p)) != 0) 866 goto retry; 867 868 for (nextlinks = LOG_LINKS (prev); nextlinks; 869 nextlinks = XEXP (nextlinks, 1)) 870 if ((next = try_combine (insn, prev, 871 XEXP (nextlinks, 0), 872 &new_direct_jump_p)) != 0) 873 goto retry; 874 } 875 876 /* Do the same for an insn that explicitly references CC0. */ 877 if (NONJUMP_INSN_P (insn) 878 && (prev = prev_nonnote_insn (insn)) != 0 879 && NONJUMP_INSN_P (prev) 880 && sets_cc0_p (PATTERN (prev)) 881 && GET_CODE (PATTERN (insn)) == SET 882 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) 883 { 884 if ((next = try_combine (insn, prev, 885 NULL_RTX, &new_direct_jump_p)) != 0) 886 goto retry; 887 888 for (nextlinks = LOG_LINKS (prev); nextlinks; 889 nextlinks = XEXP (nextlinks, 1)) 890 if ((next = try_combine (insn, prev, 891 XEXP (nextlinks, 0), 892 &new_direct_jump_p)) != 0) 893 goto retry; 894 } 895 896 /* Finally, see if any of the insns that this insn links to 897 explicitly references CC0. If so, try this insn, that insn, 898 and its predecessor if it sets CC0. */ 899 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 900 if (NONJUMP_INSN_P (XEXP (links, 0)) 901 && GET_CODE (PATTERN (XEXP (links, 0))) == SET 902 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0)))) 903 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0 904 && NONJUMP_INSN_P (prev) 905 && sets_cc0_p (PATTERN (prev)) 906 && (next = try_combine (insn, XEXP (links, 0), 907 prev, &new_direct_jump_p)) != 0) 908 goto retry; 909#endif 910 911 /* Try combining an insn with two different insns whose results it 912 uses. */ 913 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 914 for (nextlinks = XEXP (links, 1); nextlinks; 915 nextlinks = XEXP (nextlinks, 1)) 916 if ((next = try_combine (insn, XEXP (links, 0), 917 XEXP (nextlinks, 0), 918 &new_direct_jump_p)) != 0) 919 goto retry; 920 921 /* Try this insn with each REG_EQUAL note it links back to. */ 922 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 923 { 924 rtx set, note; 925 rtx temp = XEXP (links, 0); 926 if ((set = single_set (temp)) != 0 927 && (note = find_reg_equal_equiv_note (temp)) != 0 928 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST 929 /* Avoid using a register that may already been marked 930 dead by an earlier instruction. */ 931 && ! unmentioned_reg_p (note, SET_SRC (set)) 932 && (GET_MODE (note) == VOIDmode 933 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set))) 934 : GET_MODE (SET_DEST (set)) == GET_MODE (note))) 935 { 936 /* Temporarily replace the set's source with the 937 contents of the REG_EQUAL note. The insn will 938 be deleted or recognized by try_combine. */ 939 rtx orig = SET_SRC (set); 940 SET_SRC (set) = note; 941 i2mod = temp; 942 i2mod_old_rhs = copy_rtx (orig); 943 i2mod_new_rhs = copy_rtx (note); 944 next = try_combine (insn, i2mod, NULL_RTX, 945 &new_direct_jump_p); 946 i2mod = NULL_RTX; 947 if (next) 948 goto retry; 949 SET_SRC (set) = orig; 950 } 951 } 952 953 if (!NOTE_P (insn)) 954 record_dead_and_set_regs (insn); 955 956 retry: 957 ; 958 } 959 } 960 } 961 clear_bb_flags (); 962 963 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi) 964 BASIC_BLOCK (j)->flags |= BB_DIRTY; 965 new_direct_jump_p |= purge_all_dead_edges (); 966 delete_noop_moves (); 967 968 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES, 969 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE 970 | PROP_KILL_DEAD_CODE); 971 972 /* Clean up. */ 973 sbitmap_free (refresh_blocks); 974 free (uid_insn_cost); 975 free (reg_stat); 976 free (uid_cuid); 977 978 { 979 struct undo *undo, *next; 980 for (undo = undobuf.frees; undo; undo = next) 981 { 982 next = undo->next; 983 free (undo); 984 } 985 undobuf.frees = 0; 986 } 987 988 total_attempts += combine_attempts; 989 total_merges += combine_merges; 990 total_extras += combine_extras; 991 total_successes += combine_successes; 992 993 nonzero_sign_valid = 0; 994 rtl_hooks = general_rtl_hooks; 995 996 /* Make recognizer allow volatile MEMs again. */ 997 init_recog (); 998 999 return new_direct_jump_p; 1000} 1001 1002/* Wipe the last_xxx fields of reg_stat in preparation for another pass. */ 1003 1004static void 1005init_reg_last (void) 1006{ 1007 unsigned int i; 1008 for (i = 0; i < combine_max_regno; i++) 1009 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies)); 1010} 1011 1012/* Set up any promoted values for incoming argument registers. */ 1013 1014static void 1015setup_incoming_promotions (void) 1016{ 1017 unsigned int regno; 1018 rtx reg; 1019 enum machine_mode mode; 1020 int unsignedp; 1021 rtx first = get_insns (); 1022 1023 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl))) 1024 { 1025 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 1026 /* Check whether this register can hold an incoming pointer 1027 argument. FUNCTION_ARG_REGNO_P tests outgoing register 1028 numbers, so translate if necessary due to register windows. */ 1029 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno)) 1030 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0) 1031 { 1032 record_value_for_reg 1033 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND 1034 : SIGN_EXTEND), 1035 GET_MODE (reg), 1036 gen_rtx_CLOBBER (mode, const0_rtx))); 1037 } 1038 } 1039} 1040 1041/* Called via note_stores. If X is a pseudo that is narrower than 1042 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. 1043 1044 If we are setting only a portion of X and we can't figure out what 1045 portion, assume all bits will be used since we don't know what will 1046 be happening. 1047 1048 Similarly, set how many bits of X are known to be copies of the sign bit 1049 at all locations in the function. This is the smallest number implied 1050 by any set of X. */ 1051 1052static void 1053set_nonzero_bits_and_sign_copies (rtx x, rtx set, 1054 void *data ATTRIBUTE_UNUSED) 1055{ 1056 unsigned int num; 1057 1058 if (REG_P (x) 1059 && REGNO (x) >= FIRST_PSEUDO_REGISTER 1060 /* If this register is undefined at the start of the file, we can't 1061 say what its contents were. */ 1062 && ! REGNO_REG_SET_P 1063 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x)) 1064 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) 1065 { 1066 if (set == 0 || GET_CODE (set) == CLOBBER) 1067 { 1068 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x)); 1069 reg_stat[REGNO (x)].sign_bit_copies = 1; 1070 return; 1071 } 1072 1073 /* If this is a complex assignment, see if we can convert it into a 1074 simple assignment. */ 1075 set = expand_field_assignment (set); 1076 1077 /* If this is a simple assignment, or we have a paradoxical SUBREG, 1078 set what we know about X. */ 1079 1080 if (SET_DEST (set) == x 1081 || (GET_CODE (SET_DEST (set)) == SUBREG 1082 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set))) 1083 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set))))) 1084 && SUBREG_REG (SET_DEST (set)) == x)) 1085 { 1086 rtx src = SET_SRC (set); 1087 1088#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 1089 /* If X is narrower than a word and SRC is a non-negative 1090 constant that would appear negative in the mode of X, 1091 sign-extend it for use in reg_stat[].nonzero_bits because some 1092 machines (maybe most) will actually do the sign-extension 1093 and this is the conservative approach. 1094 1095 ??? For 2.5, try to tighten up the MD files in this regard 1096 instead of this kludge. */ 1097 1098 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD 1099 && GET_CODE (src) == CONST_INT 1100 && INTVAL (src) > 0 1101 && 0 != (INTVAL (src) 1102 & ((HOST_WIDE_INT) 1 1103 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 1104 src = GEN_INT (INTVAL (src) 1105 | ((HOST_WIDE_INT) (-1) 1106 << GET_MODE_BITSIZE (GET_MODE (x)))); 1107#endif 1108 1109 /* Don't call nonzero_bits if it cannot change anything. */ 1110 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0) 1111 reg_stat[REGNO (x)].nonzero_bits 1112 |= nonzero_bits (src, nonzero_bits_mode); 1113 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); 1114 if (reg_stat[REGNO (x)].sign_bit_copies == 0 1115 || reg_stat[REGNO (x)].sign_bit_copies > num) 1116 reg_stat[REGNO (x)].sign_bit_copies = num; 1117 } 1118 else 1119 { 1120 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x)); 1121 reg_stat[REGNO (x)].sign_bit_copies = 1; 1122 } 1123 } 1124} 1125 1126/* See if INSN can be combined into I3. PRED and SUCC are optionally 1127 insns that were previously combined into I3 or that will be combined 1128 into the merger of INSN and I3. 1129 1130 Return 0 if the combination is not allowed for any reason. 1131 1132 If the combination is allowed, *PDEST will be set to the single 1133 destination of INSN and *PSRC to the single source, and this function 1134 will return 1. */ 1135 1136static int 1137can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ, 1138 rtx *pdest, rtx *psrc) 1139{ 1140 int i; 1141 rtx set = 0, src, dest; 1142 rtx p; 1143#ifdef AUTO_INC_DEC 1144 rtx link; 1145#endif 1146 int all_adjacent = (succ ? (next_active_insn (insn) == succ 1147 && next_active_insn (succ) == i3) 1148 : next_active_insn (insn) == i3); 1149 1150 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. 1151 or a PARALLEL consisting of such a SET and CLOBBERs. 1152 1153 If INSN has CLOBBER parallel parts, ignore them for our processing. 1154 By definition, these happen during the execution of the insn. When it 1155 is merged with another insn, all bets are off. If they are, in fact, 1156 needed and aren't also supplied in I3, they may be added by 1157 recog_for_combine. Otherwise, it won't match. 1158 1159 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED 1160 note. 1161 1162 Get the source and destination of INSN. If more than one, can't 1163 combine. */ 1164 1165 if (GET_CODE (PATTERN (insn)) == SET) 1166 set = PATTERN (insn); 1167 else if (GET_CODE (PATTERN (insn)) == PARALLEL 1168 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) 1169 { 1170 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) 1171 { 1172 rtx elt = XVECEXP (PATTERN (insn), 0, i); 1173 rtx note; 1174 1175 switch (GET_CODE (elt)) 1176 { 1177 /* This is important to combine floating point insns 1178 for the SH4 port. */ 1179 case USE: 1180 /* Combining an isolated USE doesn't make sense. 1181 We depend here on combinable_i3pat to reject them. */ 1182 /* The code below this loop only verifies that the inputs of 1183 the SET in INSN do not change. We call reg_set_between_p 1184 to verify that the REG in the USE does not change between 1185 I3 and INSN. 1186 If the USE in INSN was for a pseudo register, the matching 1187 insn pattern will likely match any register; combining this 1188 with any other USE would only be safe if we knew that the 1189 used registers have identical values, or if there was 1190 something to tell them apart, e.g. different modes. For 1191 now, we forgo such complicated tests and simply disallow 1192 combining of USES of pseudo registers with any other USE. */ 1193 if (REG_P (XEXP (elt, 0)) 1194 && GET_CODE (PATTERN (i3)) == PARALLEL) 1195 { 1196 rtx i3pat = PATTERN (i3); 1197 int i = XVECLEN (i3pat, 0) - 1; 1198 unsigned int regno = REGNO (XEXP (elt, 0)); 1199 1200 do 1201 { 1202 rtx i3elt = XVECEXP (i3pat, 0, i); 1203 1204 if (GET_CODE (i3elt) == USE 1205 && REG_P (XEXP (i3elt, 0)) 1206 && (REGNO (XEXP (i3elt, 0)) == regno 1207 ? reg_set_between_p (XEXP (elt, 0), 1208 PREV_INSN (insn), i3) 1209 : regno >= FIRST_PSEUDO_REGISTER)) 1210 return 0; 1211 } 1212 while (--i >= 0); 1213 } 1214 break; 1215 1216 /* We can ignore CLOBBERs. */ 1217 case CLOBBER: 1218 break; 1219 1220 case SET: 1221 /* Ignore SETs whose result isn't used but not those that 1222 have side-effects. */ 1223 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) 1224 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX)) 1225 || INTVAL (XEXP (note, 0)) <= 0) 1226 && ! side_effects_p (elt)) 1227 break; 1228 1229 /* If we have already found a SET, this is a second one and 1230 so we cannot combine with this insn. */ 1231 if (set) 1232 return 0; 1233 1234 set = elt; 1235 break; 1236 1237 default: 1238 /* Anything else means we can't combine. */ 1239 return 0; 1240 } 1241 } 1242 1243 if (set == 0 1244 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, 1245 so don't do anything with it. */ 1246 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) 1247 return 0; 1248 } 1249 else 1250 return 0; 1251 1252 if (set == 0) 1253 return 0; 1254 1255 set = expand_field_assignment (set); 1256 src = SET_SRC (set), dest = SET_DEST (set); 1257 1258 /* Don't eliminate a store in the stack pointer. */ 1259 if (dest == stack_pointer_rtx 1260 /* Don't combine with an insn that sets a register to itself if it has 1261 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */ 1262 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) 1263 /* Can't merge an ASM_OPERANDS. */ 1264 || GET_CODE (src) == ASM_OPERANDS 1265 /* Can't merge a function call. */ 1266 || GET_CODE (src) == CALL 1267 /* Don't eliminate a function call argument. */ 1268 || (CALL_P (i3) 1269 && (find_reg_fusage (i3, USE, dest) 1270 || (REG_P (dest) 1271 && REGNO (dest) < FIRST_PSEUDO_REGISTER 1272 && global_regs[REGNO (dest)]))) 1273 /* Don't substitute into an incremented register. */ 1274 || FIND_REG_INC_NOTE (i3, dest) 1275 || (succ && FIND_REG_INC_NOTE (succ, dest)) 1276 /* Don't substitute into a non-local goto, this confuses CFG. */ 1277 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX)) 1278#if 0 1279 /* Don't combine the end of a libcall into anything. */ 1280 /* ??? This gives worse code, and appears to be unnecessary, since no 1281 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does 1282 use REG_RETVAL notes for noconflict blocks, but other code here 1283 makes sure that those insns don't disappear. */ 1284 || find_reg_note (insn, REG_RETVAL, NULL_RTX) 1285#endif 1286 /* Make sure that DEST is not used after SUCC but before I3. */ 1287 || (succ && ! all_adjacent 1288 && reg_used_between_p (dest, succ, i3)) 1289 /* Make sure that the value that is to be substituted for the register 1290 does not use any registers whose values alter in between. However, 1291 If the insns are adjacent, a use can't cross a set even though we 1292 think it might (this can happen for a sequence of insns each setting 1293 the same destination; last_set of that register might point to 1294 a NOTE). If INSN has a REG_EQUIV note, the register is always 1295 equivalent to the memory so the substitution is valid even if there 1296 are intervening stores. Also, don't move a volatile asm or 1297 UNSPEC_VOLATILE across any other insns. */ 1298 || (! all_adjacent 1299 && (((!MEM_P (src) 1300 || ! find_reg_note (insn, REG_EQUIV, src)) 1301 && use_crosses_set_p (src, INSN_CUID (insn))) 1302 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) 1303 || GET_CODE (src) == UNSPEC_VOLATILE)) 1304 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get 1305 better register allocation by not doing the combine. */ 1306 || find_reg_note (i3, REG_NO_CONFLICT, dest) 1307 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest)) 1308 /* Don't combine across a CALL_INSN, because that would possibly 1309 change whether the life span of some REGs crosses calls or not, 1310 and it is a pain to update that information. 1311 Exception: if source is a constant, moving it later can't hurt. 1312 Accept that special case, because it helps -fforce-addr a lot. */ 1313 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src))) 1314 return 0; 1315 1316 /* DEST must either be a REG or CC0. */ 1317 if (REG_P (dest)) 1318 { 1319 /* If register alignment is being enforced for multi-word items in all 1320 cases except for parameters, it is possible to have a register copy 1321 insn referencing a hard register that is not allowed to contain the 1322 mode being copied and which would not be valid as an operand of most 1323 insns. Eliminate this problem by not combining with such an insn. 1324 1325 Also, on some machines we don't want to extend the life of a hard 1326 register. */ 1327 1328 if (REG_P (src) 1329 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER 1330 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) 1331 /* Don't extend the life of a hard register unless it is 1332 user variable (if we have few registers) or it can't 1333 fit into the desired register (meaning something special 1334 is going on). 1335 Also avoid substituting a return register into I3, because 1336 reload can't handle a conflict with constraints of other 1337 inputs. */ 1338 || (REGNO (src) < FIRST_PSEUDO_REGISTER 1339 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))))) 1340 return 0; 1341 } 1342 else if (GET_CODE (dest) != CC0) 1343 return 0; 1344 1345 1346 if (GET_CODE (PATTERN (i3)) == PARALLEL) 1347 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) 1348 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER) 1349 { 1350 /* Don't substitute for a register intended as a clobberable 1351 operand. */ 1352 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0); 1353 if (rtx_equal_p (reg, dest)) 1354 return 0; 1355 1356 /* If the clobber represents an earlyclobber operand, we must not 1357 substitute an expression containing the clobbered register. 1358 As we do not analyze the constraint strings here, we have to 1359 make the conservative assumption. However, if the register is 1360 a fixed hard reg, the clobber cannot represent any operand; 1361 we leave it up to the machine description to either accept or 1362 reject use-and-clobber patterns. */ 1363 if (!REG_P (reg) 1364 || REGNO (reg) >= FIRST_PSEUDO_REGISTER 1365 || !fixed_regs[REGNO (reg)]) 1366 if (reg_overlap_mentioned_p (reg, src)) 1367 return 0; 1368 } 1369 1370 /* If INSN contains anything volatile, or is an `asm' (whether volatile 1371 or not), reject, unless nothing volatile comes between it and I3 */ 1372 1373 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) 1374 { 1375 /* Make sure succ doesn't contain a volatile reference. */ 1376 if (succ != 0 && volatile_refs_p (PATTERN (succ))) 1377 return 0; 1378 1379 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 1380 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p))) 1381 return 0; 1382 } 1383 1384 /* If INSN is an asm, and DEST is a hard register, reject, since it has 1385 to be an explicit register variable, and was chosen for a reason. */ 1386 1387 if (GET_CODE (src) == ASM_OPERANDS 1388 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER) 1389 return 0; 1390 1391 /* If there are any volatile insns between INSN and I3, reject, because 1392 they might affect machine state. */ 1393 1394 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 1395 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p))) 1396 return 0; 1397 1398 /* If INSN contains an autoincrement or autodecrement, make sure that 1399 register is not used between there and I3, and not already used in 1400 I3 either. Neither must it be used in PRED or SUCC, if they exist. 1401 Also insist that I3 not be a jump; if it were one 1402 and the incremented register were spilled, we would lose. */ 1403 1404#ifdef AUTO_INC_DEC 1405 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1406 if (REG_NOTE_KIND (link) == REG_INC 1407 && (JUMP_P (i3) 1408 || reg_used_between_p (XEXP (link, 0), insn, i3) 1409 || (pred != NULL_RTX 1410 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred))) 1411 || (succ != NULL_RTX 1412 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ))) 1413 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) 1414 return 0; 1415#endif 1416 1417#ifdef HAVE_cc0 1418 /* Don't combine an insn that follows a CC0-setting insn. 1419 An insn that uses CC0 must not be separated from the one that sets it. 1420 We do, however, allow I2 to follow a CC0-setting insn if that insn 1421 is passed as I1; in that case it will be deleted also. 1422 We also allow combining in this case if all the insns are adjacent 1423 because that would leave the two CC0 insns adjacent as well. 1424 It would be more logical to test whether CC0 occurs inside I1 or I2, 1425 but that would be much slower, and this ought to be equivalent. */ 1426 1427 p = prev_nonnote_insn (insn); 1428 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p)) 1429 && ! all_adjacent) 1430 return 0; 1431#endif 1432 1433 /* If we get here, we have passed all the tests and the combination is 1434 to be allowed. */ 1435 1436 *pdest = dest; 1437 *psrc = src; 1438 1439 return 1; 1440} 1441 1442/* LOC is the location within I3 that contains its pattern or the component 1443 of a PARALLEL of the pattern. We validate that it is valid for combining. 1444 1445 One problem is if I3 modifies its output, as opposed to replacing it 1446 entirely, we can't allow the output to contain I2DEST or I1DEST as doing 1447 so would produce an insn that is not equivalent to the original insns. 1448 1449 Consider: 1450 1451 (set (reg:DI 101) (reg:DI 100)) 1452 (set (subreg:SI (reg:DI 101) 0) <foo>) 1453 1454 This is NOT equivalent to: 1455 1456 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) 1457 (set (reg:DI 101) (reg:DI 100))]) 1458 1459 Not only does this modify 100 (in which case it might still be valid 1460 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. 1461 1462 We can also run into a problem if I2 sets a register that I1 1463 uses and I1 gets directly substituted into I3 (not via I2). In that 1464 case, we would be getting the wrong value of I2DEST into I3, so we 1465 must reject the combination. This case occurs when I2 and I1 both 1466 feed into I3, rather than when I1 feeds into I2, which feeds into I3. 1467 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source 1468 of a SET must prevent combination from occurring. 1469 1470 Before doing the above check, we first try to expand a field assignment 1471 into a set of logical operations. 1472 1473 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which 1474 we place a register that is both set and used within I3. If more than one 1475 such register is detected, we fail. 1476 1477 Return 1 if the combination is valid, zero otherwise. */ 1478 1479static int 1480combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, 1481 int i1_not_in_src, rtx *pi3dest_killed) 1482{ 1483 rtx x = *loc; 1484 1485 if (GET_CODE (x) == SET) 1486 { 1487 rtx set = x ; 1488 rtx dest = SET_DEST (set); 1489 rtx src = SET_SRC (set); 1490 rtx inner_dest = dest; 1491 rtx subdest; 1492 1493 while (GET_CODE (inner_dest) == STRICT_LOW_PART 1494 || GET_CODE (inner_dest) == SUBREG 1495 || GET_CODE (inner_dest) == ZERO_EXTRACT) 1496 inner_dest = XEXP (inner_dest, 0); 1497 1498 /* Check for the case where I3 modifies its output, as discussed 1499 above. We don't want to prevent pseudos from being combined 1500 into the address of a MEM, so only prevent the combination if 1501 i1 or i2 set the same MEM. */ 1502 if ((inner_dest != dest && 1503 (!MEM_P (inner_dest) 1504 || rtx_equal_p (i2dest, inner_dest) 1505 || (i1dest && rtx_equal_p (i1dest, inner_dest))) 1506 && (reg_overlap_mentioned_p (i2dest, inner_dest) 1507 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) 1508 1509 /* This is the same test done in can_combine_p except we can't test 1510 all_adjacent; we don't have to, since this instruction will stay 1511 in place, thus we are not considering increasing the lifetime of 1512 INNER_DEST. 1513 1514 Also, if this insn sets a function argument, combining it with 1515 something that might need a spill could clobber a previous 1516 function argument; the all_adjacent test in can_combine_p also 1517 checks this; here, we do a more specific test for this case. */ 1518 1519 || (REG_P (inner_dest) 1520 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 1521 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), 1522 GET_MODE (inner_dest)))) 1523 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) 1524 return 0; 1525 1526 /* If DEST is used in I3, it is being killed in this insn, so 1527 record that for later. We have to consider paradoxical 1528 subregs here, since they kill the whole register, but we 1529 ignore partial subregs, STRICT_LOW_PART, etc. 1530 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the 1531 STACK_POINTER_REGNUM, since these are always considered to be 1532 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ 1533 subdest = dest; 1534 if (GET_CODE (subdest) == SUBREG 1535 && (GET_MODE_SIZE (GET_MODE (subdest)) 1536 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest))))) 1537 subdest = SUBREG_REG (subdest); 1538 if (pi3dest_killed 1539 && REG_P (subdest) 1540 && reg_referenced_p (subdest, PATTERN (i3)) 1541 && REGNO (subdest) != FRAME_POINTER_REGNUM 1542#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 1543 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM 1544#endif 1545#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM 1546 && (REGNO (subdest) != ARG_POINTER_REGNUM 1547 || ! fixed_regs [REGNO (subdest)]) 1548#endif 1549 && REGNO (subdest) != STACK_POINTER_REGNUM) 1550 { 1551 if (*pi3dest_killed) 1552 return 0; 1553 1554 *pi3dest_killed = subdest; 1555 } 1556 } 1557 1558 else if (GET_CODE (x) == PARALLEL) 1559 { 1560 int i; 1561 1562 for (i = 0; i < XVECLEN (x, 0); i++) 1563 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, 1564 i1_not_in_src, pi3dest_killed)) 1565 return 0; 1566 } 1567 1568 return 1; 1569} 1570 1571/* Return 1 if X is an arithmetic expression that contains a multiplication 1572 and division. We don't count multiplications by powers of two here. */ 1573 1574static int 1575contains_muldiv (rtx x) 1576{ 1577 switch (GET_CODE (x)) 1578 { 1579 case MOD: case DIV: case UMOD: case UDIV: 1580 return 1; 1581 1582 case MULT: 1583 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT 1584 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0); 1585 default: 1586 if (BINARY_P (x)) 1587 return contains_muldiv (XEXP (x, 0)) 1588 || contains_muldiv (XEXP (x, 1)); 1589 1590 if (UNARY_P (x)) 1591 return contains_muldiv (XEXP (x, 0)); 1592 1593 return 0; 1594 } 1595} 1596 1597/* Determine whether INSN can be used in a combination. Return nonzero if 1598 not. This is used in try_combine to detect early some cases where we 1599 can't perform combinations. */ 1600 1601static int 1602cant_combine_insn_p (rtx insn) 1603{ 1604 rtx set; 1605 rtx src, dest; 1606 1607 /* If this isn't really an insn, we can't do anything. 1608 This can occur when flow deletes an insn that it has merged into an 1609 auto-increment address. */ 1610 if (! INSN_P (insn)) 1611 return 1; 1612 1613 /* Never combine loads and stores involving hard regs that are likely 1614 to be spilled. The register allocator can usually handle such 1615 reg-reg moves by tying. If we allow the combiner to make 1616 substitutions of likely-spilled regs, reload might die. 1617 As an exception, we allow combinations involving fixed regs; these are 1618 not available to the register allocator so there's no risk involved. */ 1619 1620 set = single_set (insn); 1621 if (! set) 1622 return 0; 1623 src = SET_SRC (set); 1624 dest = SET_DEST (set); 1625 if (GET_CODE (src) == SUBREG) 1626 src = SUBREG_REG (src); 1627 if (GET_CODE (dest) == SUBREG) 1628 dest = SUBREG_REG (dest); 1629 if (REG_P (src) && REG_P (dest) 1630 && ((REGNO (src) < FIRST_PSEUDO_REGISTER 1631 && ! fixed_regs[REGNO (src)] 1632 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src)))) 1633 || (REGNO (dest) < FIRST_PSEUDO_REGISTER 1634 && ! fixed_regs[REGNO (dest)] 1635 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest)))))) 1636 return 1; 1637 1638 return 0; 1639} 1640 1641struct likely_spilled_retval_info 1642{ 1643 unsigned regno, nregs; 1644 unsigned mask; 1645}; 1646 1647/* Called via note_stores by likely_spilled_retval_p. Remove from info->mask 1648 hard registers that are known to be written to / clobbered in full. */ 1649static void 1650likely_spilled_retval_1 (rtx x, rtx set, void *data) 1651{ 1652 struct likely_spilled_retval_info *info = data; 1653 unsigned regno, nregs; 1654 unsigned new_mask; 1655 1656 if (!REG_P (XEXP (set, 0))) 1657 return; 1658 regno = REGNO (x); 1659 if (regno >= info->regno + info->nregs) 1660 return; 1661 nregs = hard_regno_nregs[regno][GET_MODE (x)]; 1662 if (regno + nregs <= info->regno) 1663 return; 1664 new_mask = (2U << (nregs - 1)) - 1; 1665 if (regno < info->regno) 1666 new_mask >>= info->regno - regno; 1667 else 1668 new_mask <<= regno - info->regno; 1669 info->mask &= new_mask; 1670} 1671 1672/* Return nonzero iff part of the return value is live during INSN, and 1673 it is likely spilled. This can happen when more than one insn is needed 1674 to copy the return value, e.g. when we consider to combine into the 1675 second copy insn for a complex value. */ 1676 1677static int 1678likely_spilled_retval_p (rtx insn) 1679{ 1680 rtx use = BB_END (this_basic_block); 1681 rtx reg, p; 1682 unsigned regno, nregs; 1683 /* We assume here that no machine mode needs more than 1684 32 hard registers when the value overlaps with a register 1685 for which FUNCTION_VALUE_REGNO_P is true. */ 1686 unsigned mask; 1687 struct likely_spilled_retval_info info; 1688 1689 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use) 1690 return 0; 1691 reg = XEXP (PATTERN (use), 0); 1692 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg))) 1693 return 0; 1694 regno = REGNO (reg); 1695 nregs = hard_regno_nregs[regno][GET_MODE (reg)]; 1696 if (nregs == 1) 1697 return 0; 1698 mask = (2U << (nregs - 1)) - 1; 1699 1700 /* Disregard parts of the return value that are set later. */ 1701 info.regno = regno; 1702 info.nregs = nregs; 1703 info.mask = mask; 1704 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p)) 1705 note_stores (PATTERN (insn), likely_spilled_retval_1, &info); 1706 mask = info.mask; 1707 1708 /* Check if any of the (probably) live return value registers is 1709 likely spilled. */ 1710 nregs --; 1711 do 1712 { 1713 if ((mask & 1 << nregs) 1714 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs))) 1715 return 1; 1716 } while (nregs--); 1717 return 0; 1718} 1719 1720/* Adjust INSN after we made a change to its destination. 1721 1722 Changing the destination can invalidate notes that say something about 1723 the results of the insn and a LOG_LINK pointing to the insn. */ 1724 1725static void 1726adjust_for_new_dest (rtx insn) 1727{ 1728 rtx *loc; 1729 1730 /* For notes, be conservative and simply remove them. */ 1731 loc = ®_NOTES (insn); 1732 while (*loc) 1733 { 1734 enum reg_note kind = REG_NOTE_KIND (*loc); 1735 if (kind == REG_EQUAL || kind == REG_EQUIV) 1736 *loc = XEXP (*loc, 1); 1737 else 1738 loc = &XEXP (*loc, 1); 1739 } 1740 1741 /* The new insn will have a destination that was previously the destination 1742 of an insn just above it. Call distribute_links to make a LOG_LINK from 1743 the next use of that destination. */ 1744 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX)); 1745} 1746 1747/* Return TRUE if combine can reuse reg X in mode MODE. 1748 ADDED_SETS is nonzero if the original set is still required. */ 1749static bool 1750can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode) 1751{ 1752 unsigned int regno; 1753 1754 if (!REG_P(x)) 1755 return false; 1756 1757 regno = REGNO (x); 1758 /* Allow hard registers if the new mode is legal, and occupies no more 1759 registers than the old mode. */ 1760 if (regno < FIRST_PSEUDO_REGISTER) 1761 return (HARD_REGNO_MODE_OK (regno, mode) 1762 && (hard_regno_nregs[regno][GET_MODE (x)] 1763 >= hard_regno_nregs[regno][mode])); 1764 1765 /* Or a pseudo that is only used once. */ 1766 return (REG_N_SETS (regno) == 1 && !added_sets 1767 && !REG_USERVAR_P (x)); 1768} 1769 1770 1771/* Check whether X, the destination of a set, refers to part of 1772 the register specified by REG. */ 1773 1774static bool 1775reg_subword_p (rtx x, rtx reg) 1776{ 1777 /* Check that reg is an integer mode register. */ 1778 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT) 1779 return false; 1780 1781 if (GET_CODE (x) == STRICT_LOW_PART 1782 || GET_CODE (x) == ZERO_EXTRACT) 1783 x = XEXP (x, 0); 1784 1785 return GET_CODE (x) == SUBREG 1786 && SUBREG_REG (x) == reg 1787 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT; 1788} 1789 1790 1791/* Try to combine the insns I1 and I2 into I3. 1792 Here I1 and I2 appear earlier than I3. 1793 I1 can be zero; then we combine just I2 into I3. 1794 1795 If we are combining three insns and the resulting insn is not recognized, 1796 try splitting it into two insns. If that happens, I2 and I3 are retained 1797 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2 1798 are pseudo-deleted. 1799 1800 Return 0 if the combination does not work. Then nothing is changed. 1801 If we did the combination, return the insn at which combine should 1802 resume scanning. 1803 1804 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a 1805 new direct jump instruction. */ 1806 1807static rtx 1808try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p) 1809{ 1810 /* New patterns for I3 and I2, respectively. */ 1811 rtx newpat, newi2pat = 0; 1812 rtvec newpat_vec_with_clobbers = 0; 1813 int substed_i2 = 0, substed_i1 = 0; 1814 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */ 1815 int added_sets_1, added_sets_2; 1816 /* Total number of SETs to put into I3. */ 1817 int total_sets; 1818 /* Nonzero if I2's body now appears in I3. */ 1819 int i2_is_used; 1820 /* INSN_CODEs for new I3, new I2, and user of condition code. */ 1821 int insn_code_number, i2_code_number = 0, other_code_number = 0; 1822 /* Contains I3 if the destination of I3 is used in its source, which means 1823 that the old life of I3 is being killed. If that usage is placed into 1824 I2 and not in I3, a REG_DEAD note must be made. */ 1825 rtx i3dest_killed = 0; 1826 /* SET_DEST and SET_SRC of I2 and I1. */ 1827 rtx i2dest, i2src, i1dest = 0, i1src = 0; 1828 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */ 1829 rtx i1pat = 0, i2pat = 0; 1830 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ 1831 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; 1832 int i2dest_killed = 0, i1dest_killed = 0; 1833 int i1_feeds_i3 = 0; 1834 /* Notes that must be added to REG_NOTES in I3 and I2. */ 1835 rtx new_i3_notes, new_i2_notes; 1836 /* Notes that we substituted I3 into I2 instead of the normal case. */ 1837 int i3_subst_into_i2 = 0; 1838 /* Notes that I1, I2 or I3 is a MULT operation. */ 1839 int have_mult = 0; 1840 int swap_i2i3 = 0; 1841 1842 int maxreg; 1843 rtx temp; 1844 rtx link; 1845 int i; 1846 1847 /* Exit early if one of the insns involved can't be used for 1848 combinations. */ 1849 if (cant_combine_insn_p (i3) 1850 || cant_combine_insn_p (i2) 1851 || (i1 && cant_combine_insn_p (i1)) 1852 || likely_spilled_retval_p (i3) 1853 /* We also can't do anything if I3 has a 1854 REG_LIBCALL note since we don't want to disrupt the contiguity of a 1855 libcall. */ 1856#if 0 1857 /* ??? This gives worse code, and appears to be unnecessary, since no 1858 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */ 1859 || find_reg_note (i3, REG_LIBCALL, NULL_RTX) 1860#endif 1861 ) 1862 return 0; 1863 1864 combine_attempts++; 1865 undobuf.other_insn = 0; 1866 1867 /* Reset the hard register usage information. */ 1868 CLEAR_HARD_REG_SET (newpat_used_regs); 1869 1870 /* If I1 and I2 both feed I3, they can be in any order. To simplify the 1871 code below, set I1 to be the earlier of the two insns. */ 1872 if (i1 && INSN_CUID (i1) > INSN_CUID (i2)) 1873 temp = i1, i1 = i2, i2 = temp; 1874 1875 added_links_insn = 0; 1876 1877 /* First check for one important special-case that the code below will 1878 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL 1879 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, 1880 we may be able to replace that destination with the destination of I3. 1881 This occurs in the common code where we compute both a quotient and 1882 remainder into a structure, in which case we want to do the computation 1883 directly into the structure to avoid register-register copies. 1884 1885 Note that this case handles both multiple sets in I2 and also 1886 cases where I2 has a number of CLOBBER or PARALLELs. 1887 1888 We make very conservative checks below and only try to handle the 1889 most common cases of this. For example, we only handle the case 1890 where I2 and I3 are adjacent to avoid making difficult register 1891 usage tests. */ 1892 1893 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET 1894 && REG_P (SET_SRC (PATTERN (i3))) 1895 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER 1896 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) 1897 && GET_CODE (PATTERN (i2)) == PARALLEL 1898 && ! side_effects_p (SET_DEST (PATTERN (i3))) 1899 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code 1900 below would need to check what is inside (and reg_overlap_mentioned_p 1901 doesn't support those codes anyway). Don't allow those destinations; 1902 the resulting insn isn't likely to be recognized anyway. */ 1903 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT 1904 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART 1905 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), 1906 SET_DEST (PATTERN (i3))) 1907 && next_real_insn (i2) == i3) 1908 { 1909 rtx p2 = PATTERN (i2); 1910 1911 /* Make sure that the destination of I3, 1912 which we are going to substitute into one output of I2, 1913 is not used within another output of I2. We must avoid making this: 1914 (parallel [(set (mem (reg 69)) ...) 1915 (set (reg 69) ...)]) 1916 which is not well-defined as to order of actions. 1917 (Besides, reload can't handle output reloads for this.) 1918 1919 The problem can also happen if the dest of I3 is a memory ref, 1920 if another dest in I2 is an indirect memory ref. */ 1921 for (i = 0; i < XVECLEN (p2, 0); i++) 1922 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET 1923 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) 1924 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), 1925 SET_DEST (XVECEXP (p2, 0, i)))) 1926 break; 1927 1928 if (i == XVECLEN (p2, 0)) 1929 for (i = 0; i < XVECLEN (p2, 0); i++) 1930 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET 1931 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) 1932 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) 1933 { 1934 combine_merges++; 1935 1936 subst_insn = i3; 1937 subst_low_cuid = INSN_CUID (i2); 1938 1939 added_sets_2 = added_sets_1 = 0; 1940 i2dest = SET_SRC (PATTERN (i3)); 1941 i2dest_killed = dead_or_set_p (i2, i2dest); 1942 1943 /* Replace the dest in I2 with our dest and make the resulting 1944 insn the new pattern for I3. Then skip to where we 1945 validate the pattern. Everything was set up above. */ 1946 SUBST (SET_DEST (XVECEXP (p2, 0, i)), 1947 SET_DEST (PATTERN (i3))); 1948 1949 newpat = p2; 1950 i3_subst_into_i2 = 1; 1951 goto validate_replacement; 1952 } 1953 } 1954 1955 /* If I2 is setting a pseudo to a constant and I3 is setting some 1956 sub-part of it to another constant, merge them by making a new 1957 constant. */ 1958 if (i1 == 0 1959 && (temp = single_set (i2)) != 0 1960 && (GET_CODE (SET_SRC (temp)) == CONST_INT 1961 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE) 1962 && GET_CODE (PATTERN (i3)) == SET 1963 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT 1964 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE) 1965 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp))) 1966 { 1967 rtx dest = SET_DEST (PATTERN (i3)); 1968 int offset = -1; 1969 int width = 0; 1970 1971 if (GET_CODE (dest) == ZERO_EXTRACT) 1972 { 1973 if (GET_CODE (XEXP (dest, 1)) == CONST_INT 1974 && GET_CODE (XEXP (dest, 2)) == CONST_INT) 1975 { 1976 width = INTVAL (XEXP (dest, 1)); 1977 offset = INTVAL (XEXP (dest, 2)); 1978 dest = XEXP (dest, 0); 1979 if (BITS_BIG_ENDIAN) 1980 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset; 1981 } 1982 } 1983 else 1984 { 1985 if (GET_CODE (dest) == STRICT_LOW_PART) 1986 dest = XEXP (dest, 0); 1987 width = GET_MODE_BITSIZE (GET_MODE (dest)); 1988 offset = 0; 1989 } 1990 1991 if (offset >= 0) 1992 { 1993 /* If this is the low part, we're done. */ 1994 if (subreg_lowpart_p (dest)) 1995 ; 1996 /* Handle the case where inner is twice the size of outer. */ 1997 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp))) 1998 == 2 * GET_MODE_BITSIZE (GET_MODE (dest))) 1999 offset += GET_MODE_BITSIZE (GET_MODE (dest)); 2000 /* Otherwise give up for now. */ 2001 else 2002 offset = -1; 2003 } 2004 2005 if (offset >= 0) 2006 { 2007 HOST_WIDE_INT mhi, ohi, ihi; 2008 HOST_WIDE_INT mlo, olo, ilo; 2009 rtx inner = SET_SRC (PATTERN (i3)); 2010 rtx outer = SET_SRC (temp); 2011 2012 if (GET_CODE (outer) == CONST_INT) 2013 { 2014 olo = INTVAL (outer); 2015 ohi = olo < 0 ? -1 : 0; 2016 } 2017 else 2018 { 2019 olo = CONST_DOUBLE_LOW (outer); 2020 ohi = CONST_DOUBLE_HIGH (outer); 2021 } 2022 2023 if (GET_CODE (inner) == CONST_INT) 2024 { 2025 ilo = INTVAL (inner); 2026 ihi = ilo < 0 ? -1 : 0; 2027 } 2028 else 2029 { 2030 ilo = CONST_DOUBLE_LOW (inner); 2031 ihi = CONST_DOUBLE_HIGH (inner); 2032 } 2033 2034 if (width < HOST_BITS_PER_WIDE_INT) 2035 { 2036 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1; 2037 mhi = 0; 2038 } 2039 else if (width < HOST_BITS_PER_WIDE_INT * 2) 2040 { 2041 mhi = ((unsigned HOST_WIDE_INT) 1 2042 << (width - HOST_BITS_PER_WIDE_INT)) - 1; 2043 mlo = -1; 2044 } 2045 else 2046 { 2047 mlo = -1; 2048 mhi = -1; 2049 } 2050 2051 ilo &= mlo; 2052 ihi &= mhi; 2053 2054 if (offset >= HOST_BITS_PER_WIDE_INT) 2055 { 2056 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT); 2057 mlo = 0; 2058 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT); 2059 ilo = 0; 2060 } 2061 else if (offset > 0) 2062 { 2063 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo 2064 >> (HOST_BITS_PER_WIDE_INT - offset)); 2065 mlo = mlo << offset; 2066 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo 2067 >> (HOST_BITS_PER_WIDE_INT - offset)); 2068 ilo = ilo << offset; 2069 } 2070 2071 olo = (olo & ~mlo) | ilo; 2072 ohi = (ohi & ~mhi) | ihi; 2073 2074 combine_merges++; 2075 subst_insn = i3; 2076 subst_low_cuid = INSN_CUID (i2); 2077 added_sets_2 = added_sets_1 = 0; 2078 i2dest = SET_DEST (temp); 2079 i2dest_killed = dead_or_set_p (i2, i2dest); 2080 2081 SUBST (SET_SRC (temp), 2082 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp)))); 2083 2084 newpat = PATTERN (i2); 2085 goto validate_replacement; 2086 } 2087 } 2088 2089#ifndef HAVE_cc0 2090 /* If we have no I1 and I2 looks like: 2091 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) 2092 (set Y OP)]) 2093 make up a dummy I1 that is 2094 (set Y OP) 2095 and change I2 to be 2096 (set (reg:CC X) (compare:CC Y (const_int 0))) 2097 2098 (We can ignore any trailing CLOBBERs.) 2099 2100 This undoes a previous combination and allows us to match a branch-and- 2101 decrement insn. */ 2102 2103 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL 2104 && XVECLEN (PATTERN (i2), 0) >= 2 2105 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET 2106 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) 2107 == MODE_CC) 2108 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE 2109 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx 2110 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET 2111 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) 2112 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), 2113 SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) 2114 { 2115 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) 2116 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) 2117 break; 2118 2119 if (i == 1) 2120 { 2121 /* We make I1 with the same INSN_UID as I2. This gives it 2122 the same INSN_CUID for value tracking. Our fake I1 will 2123 never appear in the insn stream so giving it the same INSN_UID 2124 as I2 will not cause a problem. */ 2125 2126 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2, 2127 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2), 2128 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, 2129 NULL_RTX); 2130 2131 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); 2132 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), 2133 SET_DEST (PATTERN (i1))); 2134 } 2135 } 2136#endif 2137 2138 /* Verify that I2 and I1 are valid for combining. */ 2139 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src) 2140 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src))) 2141 { 2142 undo_all (); 2143 return 0; 2144 } 2145 2146 /* Record whether I2DEST is used in I2SRC and similarly for the other 2147 cases. Knowing this will help in register status updating below. */ 2148 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); 2149 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); 2150 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); 2151 i2dest_killed = dead_or_set_p (i2, i2dest); 2152 i1dest_killed = i1 && dead_or_set_p (i1, i1dest); 2153 2154 /* See if I1 directly feeds into I3. It does if I1DEST is not used 2155 in I2SRC. */ 2156 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); 2157 2158 /* Ensure that I3's pattern can be the destination of combines. */ 2159 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, 2160 i1 && i2dest_in_i1src && i1_feeds_i3, 2161 &i3dest_killed)) 2162 { 2163 undo_all (); 2164 return 0; 2165 } 2166 2167 /* See if any of the insns is a MULT operation. Unless one is, we will 2168 reject a combination that is, since it must be slower. Be conservative 2169 here. */ 2170 if (GET_CODE (i2src) == MULT 2171 || (i1 != 0 && GET_CODE (i1src) == MULT) 2172 || (GET_CODE (PATTERN (i3)) == SET 2173 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) 2174 have_mult = 1; 2175 2176 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. 2177 We used to do this EXCEPT in one case: I3 has a post-inc in an 2178 output operand. However, that exception can give rise to insns like 2179 mov r3,(r3)+ 2180 which is a famous insn on the PDP-11 where the value of r3 used as the 2181 source was model-dependent. Avoid this sort of thing. */ 2182 2183#if 0 2184 if (!(GET_CODE (PATTERN (i3)) == SET 2185 && REG_P (SET_SRC (PATTERN (i3))) 2186 && MEM_P (SET_DEST (PATTERN (i3))) 2187 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC 2188 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) 2189 /* It's not the exception. */ 2190#endif 2191#ifdef AUTO_INC_DEC 2192 for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) 2193 if (REG_NOTE_KIND (link) == REG_INC 2194 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) 2195 || (i1 != 0 2196 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) 2197 { 2198 undo_all (); 2199 return 0; 2200 } 2201#endif 2202 2203 /* See if the SETs in I1 or I2 need to be kept around in the merged 2204 instruction: whenever the value set there is still needed past I3. 2205 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3. 2206 2207 For the SET in I1, we have two cases: If I1 and I2 independently 2208 feed into I3, the set in I1 needs to be kept around if I1DEST dies 2209 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set 2210 in I1 needs to be kept around unless I1DEST dies or is set in either 2211 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions 2212 I1DEST. If so, we know I1 feeds into I2. */ 2213 2214 added_sets_2 = ! dead_or_set_p (i3, i2dest); 2215 2216 added_sets_1 2217 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) 2218 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); 2219 2220 /* If the set in I2 needs to be kept around, we must make a copy of 2221 PATTERN (I2), so that when we substitute I1SRC for I1DEST in 2222 PATTERN (I2), we are only substituting for the original I1DEST, not into 2223 an already-substituted copy. This also prevents making self-referential 2224 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to 2225 I2DEST. */ 2226 2227 if (added_sets_2) 2228 { 2229 if (GET_CODE (PATTERN (i2)) == PARALLEL) 2230 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src)); 2231 else 2232 i2pat = copy_rtx (PATTERN (i2)); 2233 } 2234 2235 if (added_sets_1) 2236 { 2237 if (GET_CODE (PATTERN (i1)) == PARALLEL) 2238 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src)); 2239 else 2240 i1pat = copy_rtx (PATTERN (i1)); 2241 } 2242 2243 combine_merges++; 2244 2245 /* Substitute in the latest insn for the regs set by the earlier ones. */ 2246 2247 maxreg = max_reg_num (); 2248 2249 subst_insn = i3; 2250 2251#ifndef HAVE_cc0 2252 /* Many machines that don't use CC0 have insns that can both perform an 2253 arithmetic operation and set the condition code. These operations will 2254 be represented as a PARALLEL with the first element of the vector 2255 being a COMPARE of an arithmetic operation with the constant zero. 2256 The second element of the vector will set some pseudo to the result 2257 of the same arithmetic operation. If we simplify the COMPARE, we won't 2258 match such a pattern and so will generate an extra insn. Here we test 2259 for this case, where both the comparison and the operation result are 2260 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with 2261 I2SRC. Later we will make the PARALLEL that contains I2. */ 2262 2263 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET 2264 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE 2265 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx 2266 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) 2267 { 2268#ifdef SELECT_CC_MODE 2269 rtx *cc_use; 2270 enum machine_mode compare_mode; 2271#endif 2272 2273 newpat = PATTERN (i3); 2274 SUBST (XEXP (SET_SRC (newpat), 0), i2src); 2275 2276 i2_is_used = 1; 2277 2278#ifdef SELECT_CC_MODE 2279 /* See if a COMPARE with the operand we substituted in should be done 2280 with the mode that is currently being used. If not, do the same 2281 processing we do in `subst' for a SET; namely, if the destination 2282 is used only once, try to replace it with a register of the proper 2283 mode and also replace the COMPARE. */ 2284 if (undobuf.other_insn == 0 2285 && (cc_use = find_single_use (SET_DEST (newpat), i3, 2286 &undobuf.other_insn)) 2287 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), 2288 i2src, const0_rtx)) 2289 != GET_MODE (SET_DEST (newpat)))) 2290 { 2291 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2, 2292 compare_mode)) 2293 { 2294 unsigned int regno = REGNO (SET_DEST (newpat)); 2295 rtx new_dest; 2296 2297 if (regno < FIRST_PSEUDO_REGISTER) 2298 new_dest = gen_rtx_REG (compare_mode, regno); 2299 else 2300 { 2301 SUBST_MODE (regno_reg_rtx[regno], compare_mode); 2302 new_dest = regno_reg_rtx[regno]; 2303 } 2304 2305 SUBST (SET_DEST (newpat), new_dest); 2306 SUBST (XEXP (*cc_use, 0), new_dest); 2307 SUBST (SET_SRC (newpat), 2308 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx)); 2309 } 2310 else 2311 undobuf.other_insn = 0; 2312 } 2313#endif 2314 } 2315 else 2316#endif 2317 { 2318 /* It is possible that the source of I2 or I1 may be performing 2319 an unneeded operation, such as a ZERO_EXTEND of something 2320 that is known to have the high part zero. Handle that case 2321 by letting subst look at the innermost one of them. 2322 2323 Another way to do this would be to have a function that tries 2324 to simplify a single insn instead of merging two or more 2325 insns. We don't do this because of the potential of infinite 2326 loops and because of the potential extra memory required. 2327 However, doing it the way we are is a bit of a kludge and 2328 doesn't catch all cases. 2329 2330 But only do this if -fexpensive-optimizations since it slows 2331 things down and doesn't usually win. 2332 2333 This is not done in the COMPARE case above because the 2334 unmodified I2PAT is used in the PARALLEL and so a pattern 2335 with a modified I2SRC would not match. */ 2336 2337 if (flag_expensive_optimizations) 2338 { 2339 /* Pass pc_rtx so no substitutions are done, just 2340 simplifications. */ 2341 if (i1) 2342 { 2343 subst_low_cuid = INSN_CUID (i1); 2344 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); 2345 } 2346 else 2347 { 2348 subst_low_cuid = INSN_CUID (i2); 2349 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); 2350 } 2351 } 2352 2353 n_occurrences = 0; /* `subst' counts here */ 2354 2355 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we 2356 need to make a unique copy of I2SRC each time we substitute it 2357 to avoid self-referential rtl. */ 2358 2359 subst_low_cuid = INSN_CUID (i2); 2360 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 2361 ! i1_feeds_i3 && i1dest_in_i1src); 2362 substed_i2 = 1; 2363 2364 /* Record whether i2's body now appears within i3's body. */ 2365 i2_is_used = n_occurrences; 2366 } 2367 2368 /* If we already got a failure, don't try to do more. Otherwise, 2369 try to substitute in I1 if we have it. */ 2370 2371 if (i1 && GET_CODE (newpat) != CLOBBER) 2372 { 2373 /* Check that an autoincrement side-effect on I1 has not been lost. 2374 This happens if I1DEST is mentioned in I2 and dies there, and 2375 has disappeared from the new pattern. */ 2376 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 2377 && !i1_feeds_i3 2378 && dead_or_set_p (i2, i1dest) 2379 && !reg_overlap_mentioned_p (i1dest, newpat)) 2380 /* Before we can do this substitution, we must redo the test done 2381 above (see detailed comments there) that ensures that I1DEST 2382 isn't mentioned in any SETs in NEWPAT that are field assignments. */ 2383 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0)) 2384 { 2385 undo_all (); 2386 return 0; 2387 } 2388 2389 n_occurrences = 0; 2390 subst_low_cuid = INSN_CUID (i1); 2391 newpat = subst (newpat, i1dest, i1src, 0, 0); 2392 substed_i1 = 1; 2393 } 2394 2395 /* Fail if an autoincrement side-effect has been duplicated. Be careful 2396 to count all the ways that I2SRC and I1SRC can be used. */ 2397 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 2398 && i2_is_used + added_sets_2 > 1) 2399 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 2400 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) 2401 > 1)) 2402 /* Fail if we tried to make a new register. */ 2403 || max_reg_num () != maxreg 2404 /* Fail if we couldn't do something and have a CLOBBER. */ 2405 || GET_CODE (newpat) == CLOBBER 2406 /* Fail if this new pattern is a MULT and we didn't have one before 2407 at the outer level. */ 2408 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT 2409 && ! have_mult)) 2410 { 2411 undo_all (); 2412 return 0; 2413 } 2414 2415 /* If the actions of the earlier insns must be kept 2416 in addition to substituting them into the latest one, 2417 we must make a new PARALLEL for the latest insn 2418 to hold additional the SETs. */ 2419 2420 if (added_sets_1 || added_sets_2) 2421 { 2422 combine_extras++; 2423 2424 if (GET_CODE (newpat) == PARALLEL) 2425 { 2426 rtvec old = XVEC (newpat, 0); 2427 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2; 2428 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 2429 memcpy (XVEC (newpat, 0)->elem, &old->elem[0], 2430 sizeof (old->elem[0]) * old->num_elem); 2431 } 2432 else 2433 { 2434 rtx old = newpat; 2435 total_sets = 1 + added_sets_1 + added_sets_2; 2436 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 2437 XVECEXP (newpat, 0, 0) = old; 2438 } 2439 2440 if (added_sets_1) 2441 XVECEXP (newpat, 0, --total_sets) = i1pat; 2442 2443 if (added_sets_2) 2444 { 2445 /* If there is no I1, use I2's body as is. We used to also not do 2446 the subst call below if I2 was substituted into I3, 2447 but that could lose a simplification. */ 2448 if (i1 == 0) 2449 XVECEXP (newpat, 0, --total_sets) = i2pat; 2450 else 2451 /* See comment where i2pat is assigned. */ 2452 XVECEXP (newpat, 0, --total_sets) 2453 = subst (i2pat, i1dest, i1src, 0, 0); 2454 } 2455 } 2456 2457 /* We come here when we are replacing a destination in I2 with the 2458 destination of I3. */ 2459 validate_replacement: 2460 2461 /* Note which hard regs this insn has as inputs. */ 2462 mark_used_regs_combine (newpat); 2463 2464 /* If recog_for_combine fails, it strips existing clobbers. If we'll 2465 consider splitting this pattern, we might need these clobbers. */ 2466 if (i1 && GET_CODE (newpat) == PARALLEL 2467 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER) 2468 { 2469 int len = XVECLEN (newpat, 0); 2470 2471 newpat_vec_with_clobbers = rtvec_alloc (len); 2472 for (i = 0; i < len; i++) 2473 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i); 2474 } 2475 2476 /* Is the result of combination a valid instruction? */ 2477 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2478 2479 /* If the result isn't valid, see if it is a PARALLEL of two SETs where 2480 the second SET's destination is a register that is unused and isn't 2481 marked as an instruction that might trap in an EH region. In that case, 2482 we just need the first SET. This can occur when simplifying a divmod 2483 insn. We *must* test for this case here because the code below that 2484 splits two independent SETs doesn't handle this case correctly when it 2485 updates the register status. 2486 2487 It's pointless doing this if we originally had two sets, one from 2488 i3, and one from i2. Combining then splitting the parallel results 2489 in the original i2 again plus an invalid insn (which we delete). 2490 The net effect is only to move instructions around, which makes 2491 debug info less accurate. 2492 2493 Also check the case where the first SET's destination is unused. 2494 That would not cause incorrect code, but does cause an unneeded 2495 insn to remain. */ 2496 2497 if (insn_code_number < 0 2498 && !(added_sets_2 && i1 == 0) 2499 && GET_CODE (newpat) == PARALLEL 2500 && XVECLEN (newpat, 0) == 2 2501 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2502 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2503 && asm_noperands (newpat) < 0) 2504 { 2505 rtx set0 = XVECEXP (newpat, 0, 0); 2506 rtx set1 = XVECEXP (newpat, 0, 1); 2507 rtx note; 2508 2509 if (((REG_P (SET_DEST (set1)) 2510 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1))) 2511 || (GET_CODE (SET_DEST (set1)) == SUBREG 2512 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1))))) 2513 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX)) 2514 || INTVAL (XEXP (note, 0)) <= 0) 2515 && ! side_effects_p (SET_SRC (set1))) 2516 { 2517 newpat = set0; 2518 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2519 } 2520 2521 else if (((REG_P (SET_DEST (set0)) 2522 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0))) 2523 || (GET_CODE (SET_DEST (set0)) == SUBREG 2524 && find_reg_note (i3, REG_UNUSED, 2525 SUBREG_REG (SET_DEST (set0))))) 2526 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX)) 2527 || INTVAL (XEXP (note, 0)) <= 0) 2528 && ! side_effects_p (SET_SRC (set0))) 2529 { 2530 newpat = set1; 2531 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2532 2533 if (insn_code_number >= 0) 2534 { 2535 /* If we will be able to accept this, we have made a 2536 change to the destination of I3. This requires us to 2537 do a few adjustments. */ 2538 2539 PATTERN (i3) = newpat; 2540 adjust_for_new_dest (i3); 2541 } 2542 } 2543 } 2544 2545 /* If we were combining three insns and the result is a simple SET 2546 with no ASM_OPERANDS that wasn't recognized, try to split it into two 2547 insns. There are two ways to do this. It can be split using a 2548 machine-specific method (like when you have an addition of a large 2549 constant) or by combine in the function find_split_point. */ 2550 2551 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET 2552 && asm_noperands (newpat) < 0) 2553 { 2554 rtx m_split, *split; 2555 2556 /* See if the MD file can split NEWPAT. If it can't, see if letting it 2557 use I2DEST as a scratch register will help. In the latter case, 2558 convert I2DEST to the mode of the source of NEWPAT if we can. */ 2559 2560 m_split = split_insns (newpat, i3); 2561 2562 /* We can only use I2DEST as a scratch reg if it doesn't overlap any 2563 inputs of NEWPAT. */ 2564 2565 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be 2566 possible to try that as a scratch reg. This would require adding 2567 more code to make it work though. */ 2568 2569 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat)) 2570 { 2571 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat)); 2572 2573 /* First try to split using the original register as a 2574 scratch register. */ 2575 m_split = split_insns (gen_rtx_PARALLEL 2576 (VOIDmode, 2577 gen_rtvec (2, newpat, 2578 gen_rtx_CLOBBER (VOIDmode, 2579 i2dest))), 2580 i3); 2581 2582 /* If that didn't work, try changing the mode of I2DEST if 2583 we can. */ 2584 if (m_split == 0 2585 && new_mode != GET_MODE (i2dest) 2586 && new_mode != VOIDmode 2587 && can_change_dest_mode (i2dest, added_sets_2, new_mode)) 2588 { 2589 enum machine_mode old_mode = GET_MODE (i2dest); 2590 rtx ni2dest; 2591 2592 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER) 2593 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest)); 2594 else 2595 { 2596 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode); 2597 ni2dest = regno_reg_rtx[REGNO (i2dest)]; 2598 } 2599 2600 m_split = split_insns (gen_rtx_PARALLEL 2601 (VOIDmode, 2602 gen_rtvec (2, newpat, 2603 gen_rtx_CLOBBER (VOIDmode, 2604 ni2dest))), 2605 i3); 2606 2607 if (m_split == 0 2608 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 2609 { 2610 struct undo *buf; 2611 2612 PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode); 2613 buf = undobuf.undos; 2614 undobuf.undos = buf->next; 2615 buf->next = undobuf.frees; 2616 undobuf.frees = buf; 2617 } 2618 } 2619 } 2620 2621 /* If recog_for_combine has discarded clobbers, try to use them 2622 again for the split. */ 2623 if (m_split == 0 && newpat_vec_with_clobbers) 2624 m_split 2625 = split_insns (gen_rtx_PARALLEL (VOIDmode, 2626 newpat_vec_with_clobbers), i3); 2627 2628 if (m_split && NEXT_INSN (m_split) == NULL_RTX) 2629 { 2630 m_split = PATTERN (m_split); 2631 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes); 2632 if (insn_code_number >= 0) 2633 newpat = m_split; 2634 } 2635 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX 2636 && (next_real_insn (i2) == i3 2637 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2)))) 2638 { 2639 rtx i2set, i3set; 2640 rtx newi3pat = PATTERN (NEXT_INSN (m_split)); 2641 newi2pat = PATTERN (m_split); 2642 2643 i3set = single_set (NEXT_INSN (m_split)); 2644 i2set = single_set (m_split); 2645 2646 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2647 2648 /* If I2 or I3 has multiple SETs, we won't know how to track 2649 register status, so don't use these insns. If I2's destination 2650 is used between I2 and I3, we also can't use these insns. */ 2651 2652 if (i2_code_number >= 0 && i2set && i3set 2653 && (next_real_insn (i2) == i3 2654 || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) 2655 insn_code_number = recog_for_combine (&newi3pat, i3, 2656 &new_i3_notes); 2657 if (insn_code_number >= 0) 2658 newpat = newi3pat; 2659 2660 /* It is possible that both insns now set the destination of I3. 2661 If so, we must show an extra use of it. */ 2662 2663 if (insn_code_number >= 0) 2664 { 2665 rtx new_i3_dest = SET_DEST (i3set); 2666 rtx new_i2_dest = SET_DEST (i2set); 2667 2668 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT 2669 || GET_CODE (new_i3_dest) == STRICT_LOW_PART 2670 || GET_CODE (new_i3_dest) == SUBREG) 2671 new_i3_dest = XEXP (new_i3_dest, 0); 2672 2673 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT 2674 || GET_CODE (new_i2_dest) == STRICT_LOW_PART 2675 || GET_CODE (new_i2_dest) == SUBREG) 2676 new_i2_dest = XEXP (new_i2_dest, 0); 2677 2678 if (REG_P (new_i3_dest) 2679 && REG_P (new_i2_dest) 2680 && REGNO (new_i3_dest) == REGNO (new_i2_dest)) 2681 REG_N_SETS (REGNO (new_i2_dest))++; 2682 } 2683 } 2684 2685 /* If we can split it and use I2DEST, go ahead and see if that 2686 helps things be recognized. Verify that none of the registers 2687 are set between I2 and I3. */ 2688 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0 2689#ifdef HAVE_cc0 2690 && REG_P (i2dest) 2691#endif 2692 /* We need I2DEST in the proper mode. If it is a hard register 2693 or the only use of a pseudo, we can change its mode. 2694 Make sure we don't change a hard register to have a mode that 2695 isn't valid for it, or change the number of registers. */ 2696 && (GET_MODE (*split) == GET_MODE (i2dest) 2697 || GET_MODE (*split) == VOIDmode 2698 || can_change_dest_mode (i2dest, added_sets_2, 2699 GET_MODE (*split))) 2700 && (next_real_insn (i2) == i3 2701 || ! use_crosses_set_p (*split, INSN_CUID (i2))) 2702 /* We can't overwrite I2DEST if its value is still used by 2703 NEWPAT. */ 2704 && ! reg_referenced_p (i2dest, newpat)) 2705 { 2706 rtx newdest = i2dest; 2707 enum rtx_code split_code = GET_CODE (*split); 2708 enum machine_mode split_mode = GET_MODE (*split); 2709 bool subst_done = false; 2710 newi2pat = NULL_RTX; 2711 2712 /* Get NEWDEST as a register in the proper mode. We have already 2713 validated that we can do this. */ 2714 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) 2715 { 2716 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER) 2717 newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); 2718 else 2719 { 2720 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode); 2721 newdest = regno_reg_rtx[REGNO (i2dest)]; 2722 } 2723 } 2724 2725 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to 2726 an ASHIFT. This can occur if it was inside a PLUS and hence 2727 appeared to be a memory address. This is a kludge. */ 2728 if (split_code == MULT 2729 && GET_CODE (XEXP (*split, 1)) == CONST_INT 2730 && INTVAL (XEXP (*split, 1)) > 0 2731 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0) 2732 { 2733 SUBST (*split, gen_rtx_ASHIFT (split_mode, 2734 XEXP (*split, 0), GEN_INT (i))); 2735 /* Update split_code because we may not have a multiply 2736 anymore. */ 2737 split_code = GET_CODE (*split); 2738 } 2739 2740#ifdef INSN_SCHEDULING 2741 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should 2742 be written as a ZERO_EXTEND. */ 2743 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split))) 2744 { 2745#ifdef LOAD_EXTEND_OP 2746 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's 2747 what it really is. */ 2748 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split))) 2749 == SIGN_EXTEND) 2750 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode, 2751 SUBREG_REG (*split))); 2752 else 2753#endif 2754 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode, 2755 SUBREG_REG (*split))); 2756 } 2757#endif 2758 2759 /* Attempt to split binary operators using arithmetic identities. */ 2760 if (BINARY_P (SET_SRC (newpat)) 2761 && split_mode == GET_MODE (SET_SRC (newpat)) 2762 && ! side_effects_p (SET_SRC (newpat))) 2763 { 2764 rtx setsrc = SET_SRC (newpat); 2765 enum machine_mode mode = GET_MODE (setsrc); 2766 enum rtx_code code = GET_CODE (setsrc); 2767 rtx src_op0 = XEXP (setsrc, 0); 2768 rtx src_op1 = XEXP (setsrc, 1); 2769 2770 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */ 2771 if (rtx_equal_p (src_op0, src_op1)) 2772 { 2773 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0); 2774 SUBST (XEXP (setsrc, 0), newdest); 2775 SUBST (XEXP (setsrc, 1), newdest); 2776 subst_done = true; 2777 } 2778 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */ 2779 else if ((code == PLUS || code == MULT) 2780 && GET_CODE (src_op0) == code 2781 && GET_CODE (XEXP (src_op0, 0)) == code 2782 && (INTEGRAL_MODE_P (mode) 2783 || (FLOAT_MODE_P (mode) 2784 && flag_unsafe_math_optimizations))) 2785 { 2786 rtx p = XEXP (XEXP (src_op0, 0), 0); 2787 rtx q = XEXP (XEXP (src_op0, 0), 1); 2788 rtx r = XEXP (src_op0, 1); 2789 rtx s = src_op1; 2790 2791 /* Split both "((X op Y) op X) op Y" and 2792 "((X op Y) op Y) op X" as "T op T" where T is 2793 "X op Y". */ 2794 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s)) 2795 || (rtx_equal_p (p,s) && rtx_equal_p (q,r))) 2796 { 2797 newi2pat = gen_rtx_SET (VOIDmode, newdest, 2798 XEXP (src_op0, 0)); 2799 SUBST (XEXP (setsrc, 0), newdest); 2800 SUBST (XEXP (setsrc, 1), newdest); 2801 subst_done = true; 2802 } 2803 /* Split "((X op X) op Y) op Y)" as "T op T" where 2804 T is "X op Y". */ 2805 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s)) 2806 { 2807 rtx tmp = simplify_gen_binary (code, mode, p, r); 2808 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp); 2809 SUBST (XEXP (setsrc, 0), newdest); 2810 SUBST (XEXP (setsrc, 1), newdest); 2811 subst_done = true; 2812 } 2813 } 2814 } 2815 2816 if (!subst_done) 2817 { 2818 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split); 2819 SUBST (*split, newdest); 2820 } 2821 2822 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2823 2824 /* recog_for_combine might have added CLOBBERs to newi2pat. 2825 Make sure NEWPAT does not depend on the clobbered regs. */ 2826 if (GET_CODE (newi2pat) == PARALLEL) 2827 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--) 2828 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER) 2829 { 2830 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0); 2831 if (reg_overlap_mentioned_p (reg, newpat)) 2832 { 2833 undo_all (); 2834 return 0; 2835 } 2836 } 2837 2838 /* If the split point was a MULT and we didn't have one before, 2839 don't use one now. */ 2840 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) 2841 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2842 } 2843 } 2844 2845 /* Check for a case where we loaded from memory in a narrow mode and 2846 then sign extended it, but we need both registers. In that case, 2847 we have a PARALLEL with both loads from the same memory location. 2848 We can split this into a load from memory followed by a register-register 2849 copy. This saves at least one insn, more if register allocation can 2850 eliminate the copy. 2851 2852 We cannot do this if the destination of the first assignment is a 2853 condition code register or cc0. We eliminate this case by making sure 2854 the SET_DEST and SET_SRC have the same mode. 2855 2856 We cannot do this if the destination of the second assignment is 2857 a register that we have already assumed is zero-extended. Similarly 2858 for a SUBREG of such a register. */ 2859 2860 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 2861 && GET_CODE (newpat) == PARALLEL 2862 && XVECLEN (newpat, 0) == 2 2863 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2864 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND 2865 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))) 2866 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))) 2867 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2868 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2869 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) 2870 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2871 INSN_CUID (i2)) 2872 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 2873 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 2874 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)), 2875 (REG_P (temp) 2876 && reg_stat[REGNO (temp)].nonzero_bits != 0 2877 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD 2878 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT 2879 && (reg_stat[REGNO (temp)].nonzero_bits 2880 != GET_MODE_MASK (word_mode)))) 2881 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG 2882 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), 2883 (REG_P (temp) 2884 && reg_stat[REGNO (temp)].nonzero_bits != 0 2885 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD 2886 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT 2887 && (reg_stat[REGNO (temp)].nonzero_bits 2888 != GET_MODE_MASK (word_mode))))) 2889 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), 2890 SET_SRC (XVECEXP (newpat, 0, 1))) 2891 && ! find_reg_note (i3, REG_UNUSED, 2892 SET_DEST (XVECEXP (newpat, 0, 0)))) 2893 { 2894 rtx ni2dest; 2895 2896 newi2pat = XVECEXP (newpat, 0, 0); 2897 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); 2898 newpat = XVECEXP (newpat, 0, 1); 2899 SUBST (SET_SRC (newpat), 2900 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest)); 2901 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2902 2903 if (i2_code_number >= 0) 2904 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2905 2906 if (insn_code_number >= 0) 2907 swap_i2i3 = 1; 2908 } 2909 2910 /* Similarly, check for a case where we have a PARALLEL of two independent 2911 SETs but we started with three insns. In this case, we can do the sets 2912 as two separate insns. This case occurs when some SET allows two 2913 other insns to combine, but the destination of that SET is still live. */ 2914 2915 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 2916 && GET_CODE (newpat) == PARALLEL 2917 && XVECLEN (newpat, 0) == 2 2918 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2919 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT 2920 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART 2921 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2922 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 2923 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 2924 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2925 INSN_CUID (i2)) 2926 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), 2927 XVECEXP (newpat, 0, 0)) 2928 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), 2929 XVECEXP (newpat, 0, 1)) 2930 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))) 2931 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))) 2932#ifdef HAVE_cc0 2933 /* We cannot split the parallel into two sets if both sets 2934 reference cc0. */ 2935 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)) 2936 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))) 2937#endif 2938 ) 2939 { 2940 /* Normally, it doesn't matter which of the two is done first, 2941 but it does if one references cc0. In that case, it has to 2942 be first. */ 2943#ifdef HAVE_cc0 2944 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))) 2945 { 2946 newi2pat = XVECEXP (newpat, 0, 0); 2947 newpat = XVECEXP (newpat, 0, 1); 2948 } 2949 else 2950#endif 2951 { 2952 newi2pat = XVECEXP (newpat, 0, 1); 2953 newpat = XVECEXP (newpat, 0, 0); 2954 } 2955 2956 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2957 2958 if (i2_code_number >= 0) 2959 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2960 } 2961 2962 /* If it still isn't recognized, fail and change things back the way they 2963 were. */ 2964 if ((insn_code_number < 0 2965 /* Is the result a reasonable ASM_OPERANDS? */ 2966 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) 2967 { 2968 undo_all (); 2969 return 0; 2970 } 2971 2972 /* If we had to change another insn, make sure it is valid also. */ 2973 if (undobuf.other_insn) 2974 { 2975 rtx other_pat = PATTERN (undobuf.other_insn); 2976 rtx new_other_notes; 2977 rtx note, next; 2978 2979 CLEAR_HARD_REG_SET (newpat_used_regs); 2980 2981 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, 2982 &new_other_notes); 2983 2984 if (other_code_number < 0 && ! check_asm_operands (other_pat)) 2985 { 2986 undo_all (); 2987 return 0; 2988 } 2989 2990 PATTERN (undobuf.other_insn) = other_pat; 2991 2992 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they 2993 are still valid. Then add any non-duplicate notes added by 2994 recog_for_combine. */ 2995 for (note = REG_NOTES (undobuf.other_insn); note; note = next) 2996 { 2997 next = XEXP (note, 1); 2998 2999 if (REG_NOTE_KIND (note) == REG_UNUSED 3000 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) 3001 { 3002 if (REG_P (XEXP (note, 0))) 3003 REG_N_DEATHS (REGNO (XEXP (note, 0)))--; 3004 3005 remove_note (undobuf.other_insn, note); 3006 } 3007 } 3008 3009 for (note = new_other_notes; note; note = XEXP (note, 1)) 3010 if (REG_P (XEXP (note, 0))) 3011 REG_N_DEATHS (REGNO (XEXP (note, 0)))++; 3012 3013 distribute_notes (new_other_notes, undobuf.other_insn, 3014 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX); 3015 } 3016#ifdef HAVE_cc0 3017 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether 3018 they are adjacent to each other or not. */ 3019 { 3020 rtx p = prev_nonnote_insn (i3); 3021 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat 3022 && sets_cc0_p (newi2pat)) 3023 { 3024 undo_all (); 3025 return 0; 3026 } 3027 } 3028#endif 3029 3030 /* Only allow this combination if insn_rtx_costs reports that the 3031 replacement instructions are cheaper than the originals. */ 3032 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat)) 3033 { 3034 undo_all (); 3035 return 0; 3036 } 3037 3038 /* We now know that we can do this combination. Merge the insns and 3039 update the status of registers and LOG_LINKS. */ 3040 3041 if (swap_i2i3) 3042 { 3043 rtx insn; 3044 rtx link; 3045 rtx ni2dest; 3046 3047 /* I3 now uses what used to be its destination and which is now 3048 I2's destination. This requires us to do a few adjustments. */ 3049 PATTERN (i3) = newpat; 3050 adjust_for_new_dest (i3); 3051 3052 /* We need a LOG_LINK from I3 to I2. But we used to have one, 3053 so we still will. 3054 3055 However, some later insn might be using I2's dest and have 3056 a LOG_LINK pointing at I3. We must remove this link. 3057 The simplest way to remove the link is to point it at I1, 3058 which we know will be a NOTE. */ 3059 3060 /* newi2pat is usually a SET here; however, recog_for_combine might 3061 have added some clobbers. */ 3062 if (GET_CODE (newi2pat) == PARALLEL) 3063 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0)); 3064 else 3065 ni2dest = SET_DEST (newi2pat); 3066 3067 for (insn = NEXT_INSN (i3); 3068 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR 3069 || insn != BB_HEAD (this_basic_block->next_bb)); 3070 insn = NEXT_INSN (insn)) 3071 { 3072 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn))) 3073 { 3074 for (link = LOG_LINKS (insn); link; 3075 link = XEXP (link, 1)) 3076 if (XEXP (link, 0) == i3) 3077 XEXP (link, 0) = i1; 3078 3079 break; 3080 } 3081 } 3082 } 3083 3084 { 3085 rtx i3notes, i2notes, i1notes = 0; 3086 rtx i3links, i2links, i1links = 0; 3087 rtx midnotes = 0; 3088 unsigned int regno; 3089 /* Compute which registers we expect to eliminate. newi2pat may be setting 3090 either i3dest or i2dest, so we must check it. Also, i1dest may be the 3091 same as i3dest, in which case newi2pat may be setting i1dest. */ 3092 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat)) 3093 || i2dest_in_i2src || i2dest_in_i1src 3094 || !i2dest_killed 3095 ? 0 : i2dest); 3096 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src 3097 || (newi2pat && reg_set_p (i1dest, newi2pat)) 3098 || !i1dest_killed 3099 ? 0 : i1dest); 3100 3101 /* Get the old REG_NOTES and LOG_LINKS from all our insns and 3102 clear them. */ 3103 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); 3104 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); 3105 if (i1) 3106 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); 3107 3108 /* Ensure that we do not have something that should not be shared but 3109 occurs multiple times in the new insns. Check this by first 3110 resetting all the `used' flags and then copying anything is shared. */ 3111 3112 reset_used_flags (i3notes); 3113 reset_used_flags (i2notes); 3114 reset_used_flags (i1notes); 3115 reset_used_flags (newpat); 3116 reset_used_flags (newi2pat); 3117 if (undobuf.other_insn) 3118 reset_used_flags (PATTERN (undobuf.other_insn)); 3119 3120 i3notes = copy_rtx_if_shared (i3notes); 3121 i2notes = copy_rtx_if_shared (i2notes); 3122 i1notes = copy_rtx_if_shared (i1notes); 3123 newpat = copy_rtx_if_shared (newpat); 3124 newi2pat = copy_rtx_if_shared (newi2pat); 3125 if (undobuf.other_insn) 3126 reset_used_flags (PATTERN (undobuf.other_insn)); 3127 3128 INSN_CODE (i3) = insn_code_number; 3129 PATTERN (i3) = newpat; 3130 3131 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3)) 3132 { 3133 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3); 3134 3135 reset_used_flags (call_usage); 3136 call_usage = copy_rtx (call_usage); 3137 3138 if (substed_i2) 3139 replace_rtx (call_usage, i2dest, i2src); 3140 3141 if (substed_i1) 3142 replace_rtx (call_usage, i1dest, i1src); 3143 3144 CALL_INSN_FUNCTION_USAGE (i3) = call_usage; 3145 } 3146 3147 if (undobuf.other_insn) 3148 INSN_CODE (undobuf.other_insn) = other_code_number; 3149 3150 /* We had one special case above where I2 had more than one set and 3151 we replaced a destination of one of those sets with the destination 3152 of I3. In that case, we have to update LOG_LINKS of insns later 3153 in this basic block. Note that this (expensive) case is rare. 3154 3155 Also, in this case, we must pretend that all REG_NOTEs for I2 3156 actually came from I3, so that REG_UNUSED notes from I2 will be 3157 properly handled. */ 3158 3159 if (i3_subst_into_i2) 3160 { 3161 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) 3162 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET 3163 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER) 3164 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) 3165 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest 3166 && ! find_reg_note (i2, REG_UNUSED, 3167 SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) 3168 for (temp = NEXT_INSN (i2); 3169 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR 3170 || BB_HEAD (this_basic_block) != temp); 3171 temp = NEXT_INSN (temp)) 3172 if (temp != i3 && INSN_P (temp)) 3173 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1)) 3174 if (XEXP (link, 0) == i2) 3175 XEXP (link, 0) = i3; 3176 3177 if (i3notes) 3178 { 3179 rtx link = i3notes; 3180 while (XEXP (link, 1)) 3181 link = XEXP (link, 1); 3182 XEXP (link, 1) = i2notes; 3183 } 3184 else 3185 i3notes = i2notes; 3186 i2notes = 0; 3187 } 3188 3189 LOG_LINKS (i3) = 0; 3190 REG_NOTES (i3) = 0; 3191 LOG_LINKS (i2) = 0; 3192 REG_NOTES (i2) = 0; 3193 3194 if (newi2pat) 3195 { 3196 INSN_CODE (i2) = i2_code_number; 3197 PATTERN (i2) = newi2pat; 3198 } 3199 else 3200 SET_INSN_DELETED (i2); 3201 3202 if (i1) 3203 { 3204 LOG_LINKS (i1) = 0; 3205 REG_NOTES (i1) = 0; 3206 SET_INSN_DELETED (i1); 3207 } 3208 3209 /* Get death notes for everything that is now used in either I3 or 3210 I2 and used to die in a previous insn. If we built two new 3211 patterns, move from I1 to I2 then I2 to I3 so that we get the 3212 proper movement on registers that I2 modifies. */ 3213 3214 if (newi2pat) 3215 { 3216 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes); 3217 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes); 3218 } 3219 else 3220 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2), 3221 i3, &midnotes); 3222 3223 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ 3224 if (i3notes) 3225 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX, 3226 elim_i2, elim_i1); 3227 if (i2notes) 3228 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX, 3229 elim_i2, elim_i1); 3230 if (i1notes) 3231 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX, 3232 elim_i2, elim_i1); 3233 if (midnotes) 3234 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 3235 elim_i2, elim_i1); 3236 3237 /* Distribute any notes added to I2 or I3 by recog_for_combine. We 3238 know these are REG_UNUSED and want them to go to the desired insn, 3239 so we always pass it as i3. We have not counted the notes in 3240 reg_n_deaths yet, so we need to do so now. */ 3241 3242 if (newi2pat && new_i2_notes) 3243 { 3244 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1)) 3245 if (REG_P (XEXP (temp, 0))) 3246 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; 3247 3248 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX); 3249 } 3250 3251 if (new_i3_notes) 3252 { 3253 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1)) 3254 if (REG_P (XEXP (temp, 0))) 3255 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; 3256 3257 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX); 3258 } 3259 3260 /* If I3DEST was used in I3SRC, it really died in I3. We may need to 3261 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets 3262 I3DEST, the death must be somewhere before I2, not I3. If we passed I3 3263 in that case, it might delete I2. Similarly for I2 and I1. 3264 Show an additional death due to the REG_DEAD note we make here. If 3265 we discard it in distribute_notes, we will decrement it again. */ 3266 3267 if (i3dest_killed) 3268 { 3269 if (REG_P (i3dest_killed)) 3270 REG_N_DEATHS (REGNO (i3dest_killed))++; 3271 3272 if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) 3273 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, 3274 NULL_RTX), 3275 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1); 3276 else 3277 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, 3278 NULL_RTX), 3279 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 3280 elim_i2, elim_i1); 3281 } 3282 3283 if (i2dest_in_i2src) 3284 { 3285 if (REG_P (i2dest)) 3286 REG_N_DEATHS (REGNO (i2dest))++; 3287 3288 if (newi2pat && reg_set_p (i2dest, newi2pat)) 3289 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), 3290 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); 3291 else 3292 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), 3293 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 3294 NULL_RTX, NULL_RTX); 3295 } 3296 3297 if (i1dest_in_i1src) 3298 { 3299 if (REG_P (i1dest)) 3300 REG_N_DEATHS (REGNO (i1dest))++; 3301 3302 if (newi2pat && reg_set_p (i1dest, newi2pat)) 3303 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), 3304 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); 3305 else 3306 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), 3307 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 3308 NULL_RTX, NULL_RTX); 3309 } 3310 3311 distribute_links (i3links); 3312 distribute_links (i2links); 3313 distribute_links (i1links); 3314 3315 if (REG_P (i2dest)) 3316 { 3317 rtx link; 3318 rtx i2_insn = 0, i2_val = 0, set; 3319 3320 /* The insn that used to set this register doesn't exist, and 3321 this life of the register may not exist either. See if one of 3322 I3's links points to an insn that sets I2DEST. If it does, 3323 that is now the last known value for I2DEST. If we don't update 3324 this and I2 set the register to a value that depended on its old 3325 contents, we will get confused. If this insn is used, thing 3326 will be set correctly in combine_instructions. */ 3327 3328 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) 3329 if ((set = single_set (XEXP (link, 0))) != 0 3330 && rtx_equal_p (i2dest, SET_DEST (set))) 3331 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set); 3332 3333 record_value_for_reg (i2dest, i2_insn, i2_val); 3334 3335 /* If the reg formerly set in I2 died only once and that was in I3, 3336 zero its use count so it won't make `reload' do any work. */ 3337 if (! added_sets_2 3338 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) 3339 && ! i2dest_in_i2src) 3340 { 3341 regno = REGNO (i2dest); 3342 REG_N_SETS (regno)--; 3343 } 3344 } 3345 3346 if (i1 && REG_P (i1dest)) 3347 { 3348 rtx link; 3349 rtx i1_insn = 0, i1_val = 0, set; 3350 3351 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) 3352 if ((set = single_set (XEXP (link, 0))) != 0 3353 && rtx_equal_p (i1dest, SET_DEST (set))) 3354 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set); 3355 3356 record_value_for_reg (i1dest, i1_insn, i1_val); 3357 3358 regno = REGNO (i1dest); 3359 if (! added_sets_1 && ! i1dest_in_i1src) 3360 REG_N_SETS (regno)--; 3361 } 3362 3363 /* Update reg_stat[].nonzero_bits et al for any changes that may have 3364 been made to this insn. The order of 3365 set_nonzero_bits_and_sign_copies() is important. Because newi2pat 3366 can affect nonzero_bits of newpat */ 3367 if (newi2pat) 3368 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL); 3369 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL); 3370 3371 /* Set new_direct_jump_p if a new return or simple jump instruction 3372 has been created. 3373 3374 If I3 is now an unconditional jump, ensure that it has a 3375 BARRIER following it since it may have initially been a 3376 conditional jump. It may also be the last nonnote insn. */ 3377 3378 if (returnjump_p (i3) || any_uncondjump_p (i3)) 3379 { 3380 *new_direct_jump_p = 1; 3381 mark_jump_label (PATTERN (i3), i3, 0); 3382 3383 if ((temp = next_nonnote_insn (i3)) == NULL_RTX 3384 || !BARRIER_P (temp)) 3385 emit_barrier_after (i3); 3386 } 3387 3388 if (undobuf.other_insn != NULL_RTX 3389 && (returnjump_p (undobuf.other_insn) 3390 || any_uncondjump_p (undobuf.other_insn))) 3391 { 3392 *new_direct_jump_p = 1; 3393 3394 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX 3395 || !BARRIER_P (temp)) 3396 emit_barrier_after (undobuf.other_insn); 3397 } 3398 3399 /* An NOOP jump does not need barrier, but it does need cleaning up 3400 of CFG. */ 3401 if (GET_CODE (newpat) == SET 3402 && SET_SRC (newpat) == pc_rtx 3403 && SET_DEST (newpat) == pc_rtx) 3404 *new_direct_jump_p = 1; 3405 } 3406 3407 combine_successes++; 3408 undo_commit (); 3409 3410 if (added_links_insn 3411 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2)) 3412 && INSN_CUID (added_links_insn) < INSN_CUID (i3)) 3413 return added_links_insn; 3414 else 3415 return newi2pat ? i2 : i3; 3416} 3417 3418/* Undo all the modifications recorded in undobuf. */ 3419 3420static void 3421undo_all (void) 3422{ 3423 struct undo *undo, *next; 3424 3425 for (undo = undobuf.undos; undo; undo = next) 3426 { 3427 next = undo->next; 3428 switch (undo->kind) 3429 { 3430 case UNDO_RTX: 3431 *undo->where.r = undo->old_contents.r; 3432 break; 3433 case UNDO_INT: 3434 *undo->where.i = undo->old_contents.i; 3435 break; 3436 case UNDO_MODE: 3437 PUT_MODE (*undo->where.r, undo->old_contents.m); 3438 break; 3439 default: 3440 gcc_unreachable (); 3441 } 3442 3443 undo->next = undobuf.frees; 3444 undobuf.frees = undo; 3445 } 3446 3447 undobuf.undos = 0; 3448} 3449 3450/* We've committed to accepting the changes we made. Move all 3451 of the undos to the free list. */ 3452 3453static void 3454undo_commit (void) 3455{ 3456 struct undo *undo, *next; 3457 3458 for (undo = undobuf.undos; undo; undo = next) 3459 { 3460 next = undo->next; 3461 undo->next = undobuf.frees; 3462 undobuf.frees = undo; 3463 } 3464 undobuf.undos = 0; 3465} 3466 3467/* Find the innermost point within the rtx at LOC, possibly LOC itself, 3468 where we have an arithmetic expression and return that point. LOC will 3469 be inside INSN. 3470 3471 try_combine will call this function to see if an insn can be split into 3472 two insns. */ 3473 3474static rtx * 3475find_split_point (rtx *loc, rtx insn) 3476{ 3477 rtx x = *loc; 3478 enum rtx_code code = GET_CODE (x); 3479 rtx *split; 3480 unsigned HOST_WIDE_INT len = 0; 3481 HOST_WIDE_INT pos = 0; 3482 int unsignedp = 0; 3483 rtx inner = NULL_RTX; 3484 3485 /* First special-case some codes. */ 3486 switch (code) 3487 { 3488 case SUBREG: 3489#ifdef INSN_SCHEDULING 3490 /* If we are making a paradoxical SUBREG invalid, it becomes a split 3491 point. */ 3492 if (MEM_P (SUBREG_REG (x))) 3493 return loc; 3494#endif 3495 return find_split_point (&SUBREG_REG (x), insn); 3496 3497 case MEM: 3498#ifdef HAVE_lo_sum 3499 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it 3500 using LO_SUM and HIGH. */ 3501 if (GET_CODE (XEXP (x, 0)) == CONST 3502 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) 3503 { 3504 SUBST (XEXP (x, 0), 3505 gen_rtx_LO_SUM (Pmode, 3506 gen_rtx_HIGH (Pmode, XEXP (x, 0)), 3507 XEXP (x, 0))); 3508 return &XEXP (XEXP (x, 0), 0); 3509 } 3510#endif 3511 3512 /* If we have a PLUS whose second operand is a constant and the 3513 address is not valid, perhaps will can split it up using 3514 the machine-specific way to split large constants. We use 3515 the first pseudo-reg (one of the virtual regs) as a placeholder; 3516 it will not remain in the result. */ 3517 if (GET_CODE (XEXP (x, 0)) == PLUS 3518 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3519 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) 3520 { 3521 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; 3522 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)), 3523 subst_insn); 3524 3525 /* This should have produced two insns, each of which sets our 3526 placeholder. If the source of the second is a valid address, 3527 we can make put both sources together and make a split point 3528 in the middle. */ 3529 3530 if (seq 3531 && NEXT_INSN (seq) != NULL_RTX 3532 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX 3533 && NONJUMP_INSN_P (seq) 3534 && GET_CODE (PATTERN (seq)) == SET 3535 && SET_DEST (PATTERN (seq)) == reg 3536 && ! reg_mentioned_p (reg, 3537 SET_SRC (PATTERN (seq))) 3538 && NONJUMP_INSN_P (NEXT_INSN (seq)) 3539 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET 3540 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg 3541 && memory_address_p (GET_MODE (x), 3542 SET_SRC (PATTERN (NEXT_INSN (seq))))) 3543 { 3544 rtx src1 = SET_SRC (PATTERN (seq)); 3545 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq))); 3546 3547 /* Replace the placeholder in SRC2 with SRC1. If we can 3548 find where in SRC2 it was placed, that can become our 3549 split point and we can replace this address with SRC2. 3550 Just try two obvious places. */ 3551 3552 src2 = replace_rtx (src2, reg, src1); 3553 split = 0; 3554 if (XEXP (src2, 0) == src1) 3555 split = &XEXP (src2, 0); 3556 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' 3557 && XEXP (XEXP (src2, 0), 0) == src1) 3558 split = &XEXP (XEXP (src2, 0), 0); 3559 3560 if (split) 3561 { 3562 SUBST (XEXP (x, 0), src2); 3563 return split; 3564 } 3565 } 3566 3567 /* If that didn't work, perhaps the first operand is complex and 3568 needs to be computed separately, so make a split point there. 3569 This will occur on machines that just support REG + CONST 3570 and have a constant moved through some previous computation. */ 3571 3572 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0)) 3573 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG 3574 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) 3575 return &XEXP (XEXP (x, 0), 0); 3576 } 3577 break; 3578 3579 case SET: 3580#ifdef HAVE_cc0 3581 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a 3582 ZERO_EXTRACT, the most likely reason why this doesn't match is that 3583 we need to put the operand into a register. So split at that 3584 point. */ 3585 3586 if (SET_DEST (x) == cc0_rtx 3587 && GET_CODE (SET_SRC (x)) != COMPARE 3588 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT 3589 && !OBJECT_P (SET_SRC (x)) 3590 && ! (GET_CODE (SET_SRC (x)) == SUBREG 3591 && OBJECT_P (SUBREG_REG (SET_SRC (x))))) 3592 return &SET_SRC (x); 3593#endif 3594 3595 /* See if we can split SET_SRC as it stands. */ 3596 split = find_split_point (&SET_SRC (x), insn); 3597 if (split && split != &SET_SRC (x)) 3598 return split; 3599 3600 /* See if we can split SET_DEST as it stands. */ 3601 split = find_split_point (&SET_DEST (x), insn); 3602 if (split && split != &SET_DEST (x)) 3603 return split; 3604 3605 /* See if this is a bitfield assignment with everything constant. If 3606 so, this is an IOR of an AND, so split it into that. */ 3607 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 3608 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))) 3609 <= HOST_BITS_PER_WIDE_INT) 3610 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT 3611 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT 3612 && GET_CODE (SET_SRC (x)) == CONST_INT 3613 && ((INTVAL (XEXP (SET_DEST (x), 1)) 3614 + INTVAL (XEXP (SET_DEST (x), 2))) 3615 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))) 3616 && ! side_effects_p (XEXP (SET_DEST (x), 0))) 3617 { 3618 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2)); 3619 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1)); 3620 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)); 3621 rtx dest = XEXP (SET_DEST (x), 0); 3622 enum machine_mode mode = GET_MODE (dest); 3623 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1; 3624 rtx or_mask; 3625 3626 if (BITS_BIG_ENDIAN) 3627 pos = GET_MODE_BITSIZE (mode) - len - pos; 3628 3629 or_mask = gen_int_mode (src << pos, mode); 3630 if (src == mask) 3631 SUBST (SET_SRC (x), 3632 simplify_gen_binary (IOR, mode, dest, or_mask)); 3633 else 3634 { 3635 rtx negmask = gen_int_mode (~(mask << pos), mode); 3636 SUBST (SET_SRC (x), 3637 simplify_gen_binary (IOR, mode, 3638 simplify_gen_binary (AND, mode, 3639 dest, negmask), 3640 or_mask)); 3641 } 3642 3643 SUBST (SET_DEST (x), dest); 3644 3645 split = find_split_point (&SET_SRC (x), insn); 3646 if (split && split != &SET_SRC (x)) 3647 return split; 3648 } 3649 3650 /* Otherwise, see if this is an operation that we can split into two. 3651 If so, try to split that. */ 3652 code = GET_CODE (SET_SRC (x)); 3653 3654 switch (code) 3655 { 3656 case AND: 3657 /* If we are AND'ing with a large constant that is only a single 3658 bit and the result is only being used in a context where we 3659 need to know if it is zero or nonzero, replace it with a bit 3660 extraction. This will avoid the large constant, which might 3661 have taken more than one insn to make. If the constant were 3662 not a valid argument to the AND but took only one insn to make, 3663 this is no worse, but if it took more than one insn, it will 3664 be better. */ 3665 3666 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 3667 && REG_P (XEXP (SET_SRC (x), 0)) 3668 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7 3669 && REG_P (SET_DEST (x)) 3670 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0 3671 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) 3672 && XEXP (*split, 0) == SET_DEST (x) 3673 && XEXP (*split, 1) == const0_rtx) 3674 { 3675 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), 3676 XEXP (SET_SRC (x), 0), 3677 pos, NULL_RTX, 1, 1, 0, 0); 3678 if (extraction != 0) 3679 { 3680 SUBST (SET_SRC (x), extraction); 3681 return find_split_point (loc, insn); 3682 } 3683 } 3684 break; 3685 3686 case NE: 3687 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X 3688 is known to be on, this can be converted into a NEG of a shift. */ 3689 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx 3690 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) 3691 && 1 <= (pos = exact_log2 3692 (nonzero_bits (XEXP (SET_SRC (x), 0), 3693 GET_MODE (XEXP (SET_SRC (x), 0)))))) 3694 { 3695 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); 3696 3697 SUBST (SET_SRC (x), 3698 gen_rtx_NEG (mode, 3699 gen_rtx_LSHIFTRT (mode, 3700 XEXP (SET_SRC (x), 0), 3701 GEN_INT (pos)))); 3702 3703 split = find_split_point (&SET_SRC (x), insn); 3704 if (split && split != &SET_SRC (x)) 3705 return split; 3706 } 3707 break; 3708 3709 case SIGN_EXTEND: 3710 inner = XEXP (SET_SRC (x), 0); 3711 3712 /* We can't optimize if either mode is a partial integer 3713 mode as we don't know how many bits are significant 3714 in those modes. */ 3715 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT 3716 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) 3717 break; 3718 3719 pos = 0; 3720 len = GET_MODE_BITSIZE (GET_MODE (inner)); 3721 unsignedp = 0; 3722 break; 3723 3724 case SIGN_EXTRACT: 3725 case ZERO_EXTRACT: 3726 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 3727 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT) 3728 { 3729 inner = XEXP (SET_SRC (x), 0); 3730 len = INTVAL (XEXP (SET_SRC (x), 1)); 3731 pos = INTVAL (XEXP (SET_SRC (x), 2)); 3732 3733 if (BITS_BIG_ENDIAN) 3734 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos; 3735 unsignedp = (code == ZERO_EXTRACT); 3736 } 3737 break; 3738 3739 default: 3740 break; 3741 } 3742 3743 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner))) 3744 { 3745 enum machine_mode mode = GET_MODE (SET_SRC (x)); 3746 3747 /* For unsigned, we have a choice of a shift followed by an 3748 AND or two shifts. Use two shifts for field sizes where the 3749 constant might be too large. We assume here that we can 3750 always at least get 8-bit constants in an AND insn, which is 3751 true for every current RISC. */ 3752 3753 if (unsignedp && len <= 8) 3754 { 3755 SUBST (SET_SRC (x), 3756 gen_rtx_AND (mode, 3757 gen_rtx_LSHIFTRT 3758 (mode, gen_lowpart (mode, inner), 3759 GEN_INT (pos)), 3760 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1))); 3761 3762 split = find_split_point (&SET_SRC (x), insn); 3763 if (split && split != &SET_SRC (x)) 3764 return split; 3765 } 3766 else 3767 { 3768 SUBST (SET_SRC (x), 3769 gen_rtx_fmt_ee 3770 (unsignedp ? LSHIFTRT : ASHIFTRT, mode, 3771 gen_rtx_ASHIFT (mode, 3772 gen_lowpart (mode, inner), 3773 GEN_INT (GET_MODE_BITSIZE (mode) 3774 - len - pos)), 3775 GEN_INT (GET_MODE_BITSIZE (mode) - len))); 3776 3777 split = find_split_point (&SET_SRC (x), insn); 3778 if (split && split != &SET_SRC (x)) 3779 return split; 3780 } 3781 } 3782 3783 /* See if this is a simple operation with a constant as the second 3784 operand. It might be that this constant is out of range and hence 3785 could be used as a split point. */ 3786 if (BINARY_P (SET_SRC (x)) 3787 && CONSTANT_P (XEXP (SET_SRC (x), 1)) 3788 && (OBJECT_P (XEXP (SET_SRC (x), 0)) 3789 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG 3790 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0)))))) 3791 return &XEXP (SET_SRC (x), 1); 3792 3793 /* Finally, see if this is a simple operation with its first operand 3794 not in a register. The operation might require this operand in a 3795 register, so return it as a split point. We can always do this 3796 because if the first operand were another operation, we would have 3797 already found it as a split point. */ 3798 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x))) 3799 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) 3800 return &XEXP (SET_SRC (x), 0); 3801 3802 return 0; 3803 3804 case AND: 3805 case IOR: 3806 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, 3807 it is better to write this as (not (ior A B)) so we can split it. 3808 Similarly for IOR. */ 3809 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) 3810 { 3811 SUBST (*loc, 3812 gen_rtx_NOT (GET_MODE (x), 3813 gen_rtx_fmt_ee (code == IOR ? AND : IOR, 3814 GET_MODE (x), 3815 XEXP (XEXP (x, 0), 0), 3816 XEXP (XEXP (x, 1), 0)))); 3817 return find_split_point (loc, insn); 3818 } 3819 3820 /* Many RISC machines have a large set of logical insns. If the 3821 second operand is a NOT, put it first so we will try to split the 3822 other operand first. */ 3823 if (GET_CODE (XEXP (x, 1)) == NOT) 3824 { 3825 rtx tem = XEXP (x, 0); 3826 SUBST (XEXP (x, 0), XEXP (x, 1)); 3827 SUBST (XEXP (x, 1), tem); 3828 } 3829 break; 3830 3831 default: 3832 break; 3833 } 3834 3835 /* Otherwise, select our actions depending on our rtx class. */ 3836 switch (GET_RTX_CLASS (code)) 3837 { 3838 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ 3839 case RTX_TERNARY: 3840 split = find_split_point (&XEXP (x, 2), insn); 3841 if (split) 3842 return split; 3843 /* ... fall through ... */ 3844 case RTX_BIN_ARITH: 3845 case RTX_COMM_ARITH: 3846 case RTX_COMPARE: 3847 case RTX_COMM_COMPARE: 3848 split = find_split_point (&XEXP (x, 1), insn); 3849 if (split) 3850 return split; 3851 /* ... fall through ... */ 3852 case RTX_UNARY: 3853 /* Some machines have (and (shift ...) ...) insns. If X is not 3854 an AND, but XEXP (X, 0) is, use it as our split point. */ 3855 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) 3856 return &XEXP (x, 0); 3857 3858 split = find_split_point (&XEXP (x, 0), insn); 3859 if (split) 3860 return split; 3861 return loc; 3862 3863 default: 3864 /* Otherwise, we don't have a split point. */ 3865 return 0; 3866 } 3867} 3868 3869/* Throughout X, replace FROM with TO, and return the result. 3870 The result is TO if X is FROM; 3871 otherwise the result is X, but its contents may have been modified. 3872 If they were modified, a record was made in undobuf so that 3873 undo_all will (among other things) return X to its original state. 3874 3875 If the number of changes necessary is too much to record to undo, 3876 the excess changes are not made, so the result is invalid. 3877 The changes already made can still be undone. 3878 undobuf.num_undo is incremented for such changes, so by testing that 3879 the caller can tell whether the result is valid. 3880 3881 `n_occurrences' is incremented each time FROM is replaced. 3882 3883 IN_DEST is nonzero if we are processing the SET_DEST of a SET. 3884 3885 UNIQUE_COPY is nonzero if each substitution must be unique. We do this 3886 by copying if `n_occurrences' is nonzero. */ 3887 3888static rtx 3889subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy) 3890{ 3891 enum rtx_code code = GET_CODE (x); 3892 enum machine_mode op0_mode = VOIDmode; 3893 const char *fmt; 3894 int len, i; 3895 rtx new; 3896 3897/* Two expressions are equal if they are identical copies of a shared 3898 RTX or if they are both registers with the same register number 3899 and mode. */ 3900 3901#define COMBINE_RTX_EQUAL_P(X,Y) \ 3902 ((X) == (Y) \ 3903 || (REG_P (X) && REG_P (Y) \ 3904 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) 3905 3906 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) 3907 { 3908 n_occurrences++; 3909 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); 3910 } 3911 3912 /* If X and FROM are the same register but different modes, they will 3913 not have been seen as equal above. However, flow.c will make a 3914 LOG_LINKS entry for that case. If we do nothing, we will try to 3915 rerecognize our original insn and, when it succeeds, we will 3916 delete the feeding insn, which is incorrect. 3917 3918 So force this insn not to match in this (rare) case. */ 3919 if (! in_dest && code == REG && REG_P (from) 3920 && REGNO (x) == REGNO (from)) 3921 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 3922 3923 /* If this is an object, we are done unless it is a MEM or LO_SUM, both 3924 of which may contain things that can be combined. */ 3925 if (code != MEM && code != LO_SUM && OBJECT_P (x)) 3926 return x; 3927 3928 /* It is possible to have a subexpression appear twice in the insn. 3929 Suppose that FROM is a register that appears within TO. 3930 Then, after that subexpression has been scanned once by `subst', 3931 the second time it is scanned, TO may be found. If we were 3932 to scan TO here, we would find FROM within it and create a 3933 self-referent rtl structure which is completely wrong. */ 3934 if (COMBINE_RTX_EQUAL_P (x, to)) 3935 return to; 3936 3937 /* Parallel asm_operands need special attention because all of the 3938 inputs are shared across the arms. Furthermore, unsharing the 3939 rtl results in recognition failures. Failure to handle this case 3940 specially can result in circular rtl. 3941 3942 Solve this by doing a normal pass across the first entry of the 3943 parallel, and only processing the SET_DESTs of the subsequent 3944 entries. Ug. */ 3945 3946 if (code == PARALLEL 3947 && GET_CODE (XVECEXP (x, 0, 0)) == SET 3948 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) 3949 { 3950 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy); 3951 3952 /* If this substitution failed, this whole thing fails. */ 3953 if (GET_CODE (new) == CLOBBER 3954 && XEXP (new, 0) == const0_rtx) 3955 return new; 3956 3957 SUBST (XVECEXP (x, 0, 0), new); 3958 3959 for (i = XVECLEN (x, 0) - 1; i >= 1; i--) 3960 { 3961 rtx dest = SET_DEST (XVECEXP (x, 0, i)); 3962 3963 if (!REG_P (dest) 3964 && GET_CODE (dest) != CC0 3965 && GET_CODE (dest) != PC) 3966 { 3967 new = subst (dest, from, to, 0, unique_copy); 3968 3969 /* If this substitution failed, this whole thing fails. */ 3970 if (GET_CODE (new) == CLOBBER 3971 && XEXP (new, 0) == const0_rtx) 3972 return new; 3973 3974 SUBST (SET_DEST (XVECEXP (x, 0, i)), new); 3975 } 3976 } 3977 } 3978 else 3979 { 3980 len = GET_RTX_LENGTH (code); 3981 fmt = GET_RTX_FORMAT (code); 3982 3983 /* We don't need to process a SET_DEST that is a register, CC0, 3984 or PC, so set up to skip this common case. All other cases 3985 where we want to suppress replacing something inside a 3986 SET_SRC are handled via the IN_DEST operand. */ 3987 if (code == SET 3988 && (REG_P (SET_DEST (x)) 3989 || GET_CODE (SET_DEST (x)) == CC0 3990 || GET_CODE (SET_DEST (x)) == PC)) 3991 fmt = "ie"; 3992 3993 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a 3994 constant. */ 3995 if (fmt[0] == 'e') 3996 op0_mode = GET_MODE (XEXP (x, 0)); 3997 3998 for (i = 0; i < len; i++) 3999 { 4000 if (fmt[i] == 'E') 4001 { 4002 int j; 4003 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 4004 { 4005 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) 4006 { 4007 new = (unique_copy && n_occurrences 4008 ? copy_rtx (to) : to); 4009 n_occurrences++; 4010 } 4011 else 4012 { 4013 new = subst (XVECEXP (x, i, j), from, to, 0, 4014 unique_copy); 4015 4016 /* If this substitution failed, this whole thing 4017 fails. */ 4018 if (GET_CODE (new) == CLOBBER 4019 && XEXP (new, 0) == const0_rtx) 4020 return new; 4021 } 4022 4023 SUBST (XVECEXP (x, i, j), new); 4024 } 4025 } 4026 else if (fmt[i] == 'e') 4027 { 4028 /* If this is a register being set, ignore it. */ 4029 new = XEXP (x, i); 4030 if (in_dest 4031 && i == 0 4032 && (((code == SUBREG || code == ZERO_EXTRACT) 4033 && REG_P (new)) 4034 || code == STRICT_LOW_PART)) 4035 ; 4036 4037 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) 4038 { 4039 /* In general, don't install a subreg involving two 4040 modes not tieable. It can worsen register 4041 allocation, and can even make invalid reload 4042 insns, since the reg inside may need to be copied 4043 from in the outside mode, and that may be invalid 4044 if it is an fp reg copied in integer mode. 4045 4046 We allow two exceptions to this: It is valid if 4047 it is inside another SUBREG and the mode of that 4048 SUBREG and the mode of the inside of TO is 4049 tieable and it is valid if X is a SET that copies 4050 FROM to CC0. */ 4051 4052 if (GET_CODE (to) == SUBREG 4053 && ! MODES_TIEABLE_P (GET_MODE (to), 4054 GET_MODE (SUBREG_REG (to))) 4055 && ! (code == SUBREG 4056 && MODES_TIEABLE_P (GET_MODE (x), 4057 GET_MODE (SUBREG_REG (to)))) 4058#ifdef HAVE_cc0 4059 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx) 4060#endif 4061 ) 4062 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 4063 4064#ifdef CANNOT_CHANGE_MODE_CLASS 4065 if (code == SUBREG 4066 && REG_P (to) 4067 && REGNO (to) < FIRST_PSEUDO_REGISTER 4068 && REG_CANNOT_CHANGE_MODE_P (REGNO (to), 4069 GET_MODE (to), 4070 GET_MODE (x))) 4071 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 4072#endif 4073 4074 new = (unique_copy && n_occurrences ? copy_rtx (to) : to); 4075 n_occurrences++; 4076 } 4077 else 4078 /* If we are in a SET_DEST, suppress most cases unless we 4079 have gone inside a MEM, in which case we want to 4080 simplify the address. We assume here that things that 4081 are actually part of the destination have their inner 4082 parts in the first expression. This is true for SUBREG, 4083 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only 4084 things aside from REG and MEM that should appear in a 4085 SET_DEST. */ 4086 new = subst (XEXP (x, i), from, to, 4087 (((in_dest 4088 && (code == SUBREG || code == STRICT_LOW_PART 4089 || code == ZERO_EXTRACT)) 4090 || code == SET) 4091 && i == 0), unique_copy); 4092 4093 /* If we found that we will have to reject this combination, 4094 indicate that by returning the CLOBBER ourselves, rather than 4095 an expression containing it. This will speed things up as 4096 well as prevent accidents where two CLOBBERs are considered 4097 to be equal, thus producing an incorrect simplification. */ 4098 4099 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) 4100 return new; 4101 4102 if (GET_CODE (x) == SUBREG 4103 && (GET_CODE (new) == CONST_INT 4104 || GET_CODE (new) == CONST_DOUBLE)) 4105 { 4106 enum machine_mode mode = GET_MODE (x); 4107 4108 x = simplify_subreg (GET_MODE (x), new, 4109 GET_MODE (SUBREG_REG (x)), 4110 SUBREG_BYTE (x)); 4111 if (! x) 4112 x = gen_rtx_CLOBBER (mode, const0_rtx); 4113 } 4114 else if (GET_CODE (new) == CONST_INT 4115 && GET_CODE (x) == ZERO_EXTEND) 4116 { 4117 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), 4118 new, GET_MODE (XEXP (x, 0))); 4119 gcc_assert (x); 4120 } 4121 else 4122 SUBST (XEXP (x, i), new); 4123 } 4124 } 4125 } 4126 4127 /* Try to simplify X. If the simplification changed the code, it is likely 4128 that further simplification will help, so loop, but limit the number 4129 of repetitions that will be performed. */ 4130 4131 for (i = 0; i < 4; i++) 4132 { 4133 /* If X is sufficiently simple, don't bother trying to do anything 4134 with it. */ 4135 if (code != CONST_INT && code != REG && code != CLOBBER) 4136 x = combine_simplify_rtx (x, op0_mode, in_dest); 4137 4138 if (GET_CODE (x) == code) 4139 break; 4140 4141 code = GET_CODE (x); 4142 4143 /* We no longer know the original mode of operand 0 since we 4144 have changed the form of X) */ 4145 op0_mode = VOIDmode; 4146 } 4147 4148 return x; 4149} 4150 4151/* Simplify X, a piece of RTL. We just operate on the expression at the 4152 outer level; call `subst' to simplify recursively. Return the new 4153 expression. 4154 4155 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero 4156 if we are inside a SET_DEST. */ 4157 4158static rtx 4159combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest) 4160{ 4161 enum rtx_code code = GET_CODE (x); 4162 enum machine_mode mode = GET_MODE (x); 4163 rtx temp; 4164 int i; 4165 4166 /* If this is a commutative operation, put a constant last and a complex 4167 expression first. We don't need to do this for comparisons here. */ 4168 if (COMMUTATIVE_ARITH_P (x) 4169 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 4170 { 4171 temp = XEXP (x, 0); 4172 SUBST (XEXP (x, 0), XEXP (x, 1)); 4173 SUBST (XEXP (x, 1), temp); 4174 } 4175 4176 /* If this is a simple operation applied to an IF_THEN_ELSE, try 4177 applying it to the arms of the IF_THEN_ELSE. This often simplifies 4178 things. Check for cases where both arms are testing the same 4179 condition. 4180 4181 Don't do anything if all operands are very simple. */ 4182 4183 if ((BINARY_P (x) 4184 && ((!OBJECT_P (XEXP (x, 0)) 4185 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 4186 && OBJECT_P (SUBREG_REG (XEXP (x, 0))))) 4187 || (!OBJECT_P (XEXP (x, 1)) 4188 && ! (GET_CODE (XEXP (x, 1)) == SUBREG 4189 && OBJECT_P (SUBREG_REG (XEXP (x, 1))))))) 4190 || (UNARY_P (x) 4191 && (!OBJECT_P (XEXP (x, 0)) 4192 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 4193 && OBJECT_P (SUBREG_REG (XEXP (x, 0))))))) 4194 { 4195 rtx cond, true_rtx, false_rtx; 4196 4197 cond = if_then_else_cond (x, &true_rtx, &false_rtx); 4198 if (cond != 0 4199 /* If everything is a comparison, what we have is highly unlikely 4200 to be simpler, so don't use it. */ 4201 && ! (COMPARISON_P (x) 4202 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))) 4203 { 4204 rtx cop1 = const0_rtx; 4205 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); 4206 4207 if (cond_code == NE && COMPARISON_P (cond)) 4208 return x; 4209 4210 /* Simplify the alternative arms; this may collapse the true and 4211 false arms to store-flag values. Be careful to use copy_rtx 4212 here since true_rtx or false_rtx might share RTL with x as a 4213 result of the if_then_else_cond call above. */ 4214 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0); 4215 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0); 4216 4217 /* If true_rtx and false_rtx are not general_operands, an if_then_else 4218 is unlikely to be simpler. */ 4219 if (general_operand (true_rtx, VOIDmode) 4220 && general_operand (false_rtx, VOIDmode)) 4221 { 4222 enum rtx_code reversed; 4223 4224 /* Restarting if we generate a store-flag expression will cause 4225 us to loop. Just drop through in this case. */ 4226 4227 /* If the result values are STORE_FLAG_VALUE and zero, we can 4228 just make the comparison operation. */ 4229 if (true_rtx == const_true_rtx && false_rtx == const0_rtx) 4230 x = simplify_gen_relational (cond_code, mode, VOIDmode, 4231 cond, cop1); 4232 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx 4233 && ((reversed = reversed_comparison_code_parts 4234 (cond_code, cond, cop1, NULL)) 4235 != UNKNOWN)) 4236 x = simplify_gen_relational (reversed, mode, VOIDmode, 4237 cond, cop1); 4238 4239 /* Likewise, we can make the negate of a comparison operation 4240 if the result values are - STORE_FLAG_VALUE and zero. */ 4241 else if (GET_CODE (true_rtx) == CONST_INT 4242 && INTVAL (true_rtx) == - STORE_FLAG_VALUE 4243 && false_rtx == const0_rtx) 4244 x = simplify_gen_unary (NEG, mode, 4245 simplify_gen_relational (cond_code, 4246 mode, VOIDmode, 4247 cond, cop1), 4248 mode); 4249 else if (GET_CODE (false_rtx) == CONST_INT 4250 && INTVAL (false_rtx) == - STORE_FLAG_VALUE 4251 && true_rtx == const0_rtx 4252 && ((reversed = reversed_comparison_code_parts 4253 (cond_code, cond, cop1, NULL)) 4254 != UNKNOWN)) 4255 x = simplify_gen_unary (NEG, mode, 4256 simplify_gen_relational (reversed, 4257 mode, VOIDmode, 4258 cond, cop1), 4259 mode); 4260 else 4261 return gen_rtx_IF_THEN_ELSE (mode, 4262 simplify_gen_relational (cond_code, 4263 mode, 4264 VOIDmode, 4265 cond, 4266 cop1), 4267 true_rtx, false_rtx); 4268 4269 code = GET_CODE (x); 4270 op0_mode = VOIDmode; 4271 } 4272 } 4273 } 4274 4275 /* Try to fold this expression in case we have constants that weren't 4276 present before. */ 4277 temp = 0; 4278 switch (GET_RTX_CLASS (code)) 4279 { 4280 case RTX_UNARY: 4281 if (op0_mode == VOIDmode) 4282 op0_mode = GET_MODE (XEXP (x, 0)); 4283 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); 4284 break; 4285 case RTX_COMPARE: 4286 case RTX_COMM_COMPARE: 4287 { 4288 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0)); 4289 if (cmp_mode == VOIDmode) 4290 { 4291 cmp_mode = GET_MODE (XEXP (x, 1)); 4292 if (cmp_mode == VOIDmode) 4293 cmp_mode = op0_mode; 4294 } 4295 temp = simplify_relational_operation (code, mode, cmp_mode, 4296 XEXP (x, 0), XEXP (x, 1)); 4297 } 4298 break; 4299 case RTX_COMM_ARITH: 4300 case RTX_BIN_ARITH: 4301 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); 4302 break; 4303 case RTX_BITFIELD_OPS: 4304 case RTX_TERNARY: 4305 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), 4306 XEXP (x, 1), XEXP (x, 2)); 4307 break; 4308 default: 4309 break; 4310 } 4311 4312 if (temp) 4313 { 4314 x = temp; 4315 code = GET_CODE (temp); 4316 op0_mode = VOIDmode; 4317 mode = GET_MODE (temp); 4318 } 4319 4320 /* First see if we can apply the inverse distributive law. */ 4321 if (code == PLUS || code == MINUS 4322 || code == AND || code == IOR || code == XOR) 4323 { 4324 x = apply_distributive_law (x); 4325 code = GET_CODE (x); 4326 op0_mode = VOIDmode; 4327 } 4328 4329 /* If CODE is an associative operation not otherwise handled, see if we 4330 can associate some operands. This can win if they are constants or 4331 if they are logically related (i.e. (a & b) & a). */ 4332 if ((code == PLUS || code == MINUS || code == MULT || code == DIV 4333 || code == AND || code == IOR || code == XOR 4334 || code == SMAX || code == SMIN || code == UMAX || code == UMIN) 4335 && ((INTEGRAL_MODE_P (mode) && code != DIV) 4336 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode)))) 4337 { 4338 if (GET_CODE (XEXP (x, 0)) == code) 4339 { 4340 rtx other = XEXP (XEXP (x, 0), 0); 4341 rtx inner_op0 = XEXP (XEXP (x, 0), 1); 4342 rtx inner_op1 = XEXP (x, 1); 4343 rtx inner; 4344 4345 /* Make sure we pass the constant operand if any as the second 4346 one if this is a commutative operation. */ 4347 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x)) 4348 { 4349 rtx tem = inner_op0; 4350 inner_op0 = inner_op1; 4351 inner_op1 = tem; 4352 } 4353 inner = simplify_binary_operation (code == MINUS ? PLUS 4354 : code == DIV ? MULT 4355 : code, 4356 mode, inner_op0, inner_op1); 4357 4358 /* For commutative operations, try the other pair if that one 4359 didn't simplify. */ 4360 if (inner == 0 && COMMUTATIVE_ARITH_P (x)) 4361 { 4362 other = XEXP (XEXP (x, 0), 1); 4363 inner = simplify_binary_operation (code, mode, 4364 XEXP (XEXP (x, 0), 0), 4365 XEXP (x, 1)); 4366 } 4367 4368 if (inner) 4369 return simplify_gen_binary (code, mode, other, inner); 4370 } 4371 } 4372 4373 /* A little bit of algebraic simplification here. */ 4374 switch (code) 4375 { 4376 case MEM: 4377 /* Ensure that our address has any ASHIFTs converted to MULT in case 4378 address-recognizing predicates are called later. */ 4379 temp = make_compound_operation (XEXP (x, 0), MEM); 4380 SUBST (XEXP (x, 0), temp); 4381 break; 4382 4383 case SUBREG: 4384 if (op0_mode == VOIDmode) 4385 op0_mode = GET_MODE (SUBREG_REG (x)); 4386 4387 /* See if this can be moved to simplify_subreg. */ 4388 if (CONSTANT_P (SUBREG_REG (x)) 4389 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x) 4390 /* Don't call gen_lowpart if the inner mode 4391 is VOIDmode and we cannot simplify it, as SUBREG without 4392 inner mode is invalid. */ 4393 && (GET_MODE (SUBREG_REG (x)) != VOIDmode 4394 || gen_lowpart_common (mode, SUBREG_REG (x)))) 4395 return gen_lowpart (mode, SUBREG_REG (x)); 4396 4397 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC) 4398 break; 4399 { 4400 rtx temp; 4401 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode, 4402 SUBREG_BYTE (x)); 4403 if (temp) 4404 return temp; 4405 } 4406 4407 /* Don't change the mode of the MEM if that would change the meaning 4408 of the address. */ 4409 if (MEM_P (SUBREG_REG (x)) 4410 && (MEM_VOLATILE_P (SUBREG_REG (x)) 4411 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0)))) 4412 return gen_rtx_CLOBBER (mode, const0_rtx); 4413 4414 /* Note that we cannot do any narrowing for non-constants since 4415 we might have been counting on using the fact that some bits were 4416 zero. We now do this in the SET. */ 4417 4418 break; 4419 4420 case NEG: 4421 temp = expand_compound_operation (XEXP (x, 0)); 4422 4423 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be 4424 replaced by (lshiftrt X C). This will convert 4425 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ 4426 4427 if (GET_CODE (temp) == ASHIFTRT 4428 && GET_CODE (XEXP (temp, 1)) == CONST_INT 4429 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1) 4430 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0), 4431 INTVAL (XEXP (temp, 1))); 4432 4433 /* If X has only a single bit that might be nonzero, say, bit I, convert 4434 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of 4435 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to 4436 (sign_extract X 1 Y). But only do this if TEMP isn't a register 4437 or a SUBREG of one since we'd be making the expression more 4438 complex if it was just a register. */ 4439 4440 if (!REG_P (temp) 4441 && ! (GET_CODE (temp) == SUBREG 4442 && REG_P (SUBREG_REG (temp))) 4443 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) 4444 { 4445 rtx temp1 = simplify_shift_const 4446 (NULL_RTX, ASHIFTRT, mode, 4447 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, 4448 GET_MODE_BITSIZE (mode) - 1 - i), 4449 GET_MODE_BITSIZE (mode) - 1 - i); 4450 4451 /* If all we did was surround TEMP with the two shifts, we 4452 haven't improved anything, so don't use it. Otherwise, 4453 we are better off with TEMP1. */ 4454 if (GET_CODE (temp1) != ASHIFTRT 4455 || GET_CODE (XEXP (temp1, 0)) != ASHIFT 4456 || XEXP (XEXP (temp1, 0), 0) != temp) 4457 return temp1; 4458 } 4459 break; 4460 4461 case TRUNCATE: 4462 /* We can't handle truncation to a partial integer mode here 4463 because we don't know the real bitsize of the partial 4464 integer mode. */ 4465 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) 4466 break; 4467 4468 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4469 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 4470 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))) 4471 SUBST (XEXP (x, 0), 4472 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), 4473 GET_MODE_MASK (mode), 0)); 4474 4475 /* Similarly to what we do in simplify-rtx.c, a truncate of a register 4476 whose value is a comparison can be replaced with a subreg if 4477 STORE_FLAG_VALUE permits. */ 4478 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4479 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0 4480 && (temp = get_last_value (XEXP (x, 0))) 4481 && COMPARISON_P (temp)) 4482 return gen_lowpart (mode, XEXP (x, 0)); 4483 break; 4484 4485#ifdef HAVE_cc0 4486 case COMPARE: 4487 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't 4488 using cc0, in which case we want to leave it as a COMPARE 4489 so we can distinguish it from a register-register-copy. */ 4490 if (XEXP (x, 1) == const0_rtx) 4491 return XEXP (x, 0); 4492 4493 /* x - 0 is the same as x unless x's mode has signed zeros and 4494 allows rounding towards -infinity. Under those conditions, 4495 0 - 0 is -0. */ 4496 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0))) 4497 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0)))) 4498 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0)))) 4499 return XEXP (x, 0); 4500 break; 4501#endif 4502 4503 case CONST: 4504 /* (const (const X)) can become (const X). Do it this way rather than 4505 returning the inner CONST since CONST can be shared with a 4506 REG_EQUAL note. */ 4507 if (GET_CODE (XEXP (x, 0)) == CONST) 4508 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4509 break; 4510 4511#ifdef HAVE_lo_sum 4512 case LO_SUM: 4513 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we 4514 can add in an offset. find_split_point will split this address up 4515 again if it doesn't match. */ 4516 if (GET_CODE (XEXP (x, 0)) == HIGH 4517 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) 4518 return XEXP (x, 1); 4519 break; 4520#endif 4521 4522 case PLUS: 4523 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) 4524 when c is (const_int (pow2 + 1) / 2) is a sign extension of a 4525 bit-field and can be replaced by either a sign_extend or a 4526 sign_extract. The `and' may be a zero_extend and the two 4527 <c>, -<c> constants may be reversed. */ 4528 if (GET_CODE (XEXP (x, 0)) == XOR 4529 && GET_CODE (XEXP (x, 1)) == CONST_INT 4530 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 4531 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1)) 4532 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 4533 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) 4534 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4535 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND 4536 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT 4537 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) 4538 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1)) 4539 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND 4540 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) 4541 == (unsigned int) i + 1)))) 4542 return simplify_shift_const 4543 (NULL_RTX, ASHIFTRT, mode, 4544 simplify_shift_const (NULL_RTX, ASHIFT, mode, 4545 XEXP (XEXP (XEXP (x, 0), 0), 0), 4546 GET_MODE_BITSIZE (mode) - (i + 1)), 4547 GET_MODE_BITSIZE (mode) - (i + 1)); 4548 4549 /* If only the low-order bit of X is possibly nonzero, (plus x -1) 4550 can become (ashiftrt (ashift (xor x 1) C) C) where C is 4551 the bitsize of the mode - 1. This allows simplification of 4552 "a = (b & 8) == 0;" */ 4553 if (XEXP (x, 1) == constm1_rtx 4554 && !REG_P (XEXP (x, 0)) 4555 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 4556 && REG_P (SUBREG_REG (XEXP (x, 0)))) 4557 && nonzero_bits (XEXP (x, 0), mode) == 1) 4558 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, 4559 simplify_shift_const (NULL_RTX, ASHIFT, mode, 4560 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx), 4561 GET_MODE_BITSIZE (mode) - 1), 4562 GET_MODE_BITSIZE (mode) - 1); 4563 4564 /* If we are adding two things that have no bits in common, convert 4565 the addition into an IOR. This will often be further simplified, 4566 for example in cases like ((a & 1) + (a & 2)), which can 4567 become a & 3. */ 4568 4569 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4570 && (nonzero_bits (XEXP (x, 0), mode) 4571 & nonzero_bits (XEXP (x, 1), mode)) == 0) 4572 { 4573 /* Try to simplify the expression further. */ 4574 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); 4575 temp = combine_simplify_rtx (tor, mode, in_dest); 4576 4577 /* If we could, great. If not, do not go ahead with the IOR 4578 replacement, since PLUS appears in many special purpose 4579 address arithmetic instructions. */ 4580 if (GET_CODE (temp) != CLOBBER && temp != tor) 4581 return temp; 4582 } 4583 break; 4584 4585 case MINUS: 4586 /* (minus <foo> (and <foo> (const_int -pow2))) becomes 4587 (and <foo> (const_int pow2-1)) */ 4588 if (GET_CODE (XEXP (x, 1)) == AND 4589 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 4590 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0 4591 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) 4592 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), 4593 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1); 4594 break; 4595 4596 case MULT: 4597 /* If we have (mult (plus A B) C), apply the distributive law and then 4598 the inverse distributive law to see if things simplify. This 4599 occurs mostly in addresses, often when unrolling loops. */ 4600 4601 if (GET_CODE (XEXP (x, 0)) == PLUS) 4602 { 4603 rtx result = distribute_and_simplify_rtx (x, 0); 4604 if (result) 4605 return result; 4606 } 4607 4608 /* Try simplify a*(b/c) as (a*b)/c. */ 4609 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations 4610 && GET_CODE (XEXP (x, 0)) == DIV) 4611 { 4612 rtx tem = simplify_binary_operation (MULT, mode, 4613 XEXP (XEXP (x, 0), 0), 4614 XEXP (x, 1)); 4615 if (tem) 4616 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1)); 4617 } 4618 break; 4619 4620 case UDIV: 4621 /* If this is a divide by a power of two, treat it as a shift if 4622 its first operand is a shift. */ 4623 if (GET_CODE (XEXP (x, 1)) == CONST_INT 4624 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 4625 && (GET_CODE (XEXP (x, 0)) == ASHIFT 4626 || GET_CODE (XEXP (x, 0)) == LSHIFTRT 4627 || GET_CODE (XEXP (x, 0)) == ASHIFTRT 4628 || GET_CODE (XEXP (x, 0)) == ROTATE 4629 || GET_CODE (XEXP (x, 0)) == ROTATERT)) 4630 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); 4631 break; 4632 4633 case EQ: case NE: 4634 case GT: case GTU: case GE: case GEU: 4635 case LT: case LTU: case LE: case LEU: 4636 case UNEQ: case LTGT: 4637 case UNGT: case UNGE: 4638 case UNLT: case UNLE: 4639 case UNORDERED: case ORDERED: 4640 /* If the first operand is a condition code, we can't do anything 4641 with it. */ 4642 if (GET_CODE (XEXP (x, 0)) == COMPARE 4643 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC 4644 && ! CC0_P (XEXP (x, 0)))) 4645 { 4646 rtx op0 = XEXP (x, 0); 4647 rtx op1 = XEXP (x, 1); 4648 enum rtx_code new_code; 4649 4650 if (GET_CODE (op0) == COMPARE) 4651 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); 4652 4653 /* Simplify our comparison, if possible. */ 4654 new_code = simplify_comparison (code, &op0, &op1); 4655 4656 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X 4657 if only the low-order bit is possibly nonzero in X (such as when 4658 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to 4659 (xor X 1) or (minus 1 X); we use the former. Finally, if X is 4660 known to be either 0 or -1, NE becomes a NEG and EQ becomes 4661 (plus X 1). 4662 4663 Remove any ZERO_EXTRACT we made when thinking this was a 4664 comparison. It may now be simpler to use, e.g., an AND. If a 4665 ZERO_EXTRACT is indeed appropriate, it will be placed back by 4666 the call to make_compound_operation in the SET case. */ 4667 4668 if (STORE_FLAG_VALUE == 1 4669 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4670 && op1 == const0_rtx 4671 && mode == GET_MODE (op0) 4672 && nonzero_bits (op0, mode) == 1) 4673 return gen_lowpart (mode, 4674 expand_compound_operation (op0)); 4675 4676 else if (STORE_FLAG_VALUE == 1 4677 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4678 && op1 == const0_rtx 4679 && mode == GET_MODE (op0) 4680 && (num_sign_bit_copies (op0, mode) 4681 == GET_MODE_BITSIZE (mode))) 4682 { 4683 op0 = expand_compound_operation (op0); 4684 return simplify_gen_unary (NEG, mode, 4685 gen_lowpart (mode, op0), 4686 mode); 4687 } 4688 4689 else if (STORE_FLAG_VALUE == 1 4690 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4691 && op1 == const0_rtx 4692 && mode == GET_MODE (op0) 4693 && nonzero_bits (op0, mode) == 1) 4694 { 4695 op0 = expand_compound_operation (op0); 4696 return simplify_gen_binary (XOR, mode, 4697 gen_lowpart (mode, op0), 4698 const1_rtx); 4699 } 4700 4701 else if (STORE_FLAG_VALUE == 1 4702 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4703 && op1 == const0_rtx 4704 && mode == GET_MODE (op0) 4705 && (num_sign_bit_copies (op0, mode) 4706 == GET_MODE_BITSIZE (mode))) 4707 { 4708 op0 = expand_compound_operation (op0); 4709 return plus_constant (gen_lowpart (mode, op0), 1); 4710 } 4711 4712 /* If STORE_FLAG_VALUE is -1, we have cases similar to 4713 those above. */ 4714 if (STORE_FLAG_VALUE == -1 4715 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4716 && op1 == const0_rtx 4717 && (num_sign_bit_copies (op0, mode) 4718 == GET_MODE_BITSIZE (mode))) 4719 return gen_lowpart (mode, 4720 expand_compound_operation (op0)); 4721 4722 else if (STORE_FLAG_VALUE == -1 4723 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4724 && op1 == const0_rtx 4725 && mode == GET_MODE (op0) 4726 && nonzero_bits (op0, mode) == 1) 4727 { 4728 op0 = expand_compound_operation (op0); 4729 return simplify_gen_unary (NEG, mode, 4730 gen_lowpart (mode, op0), 4731 mode); 4732 } 4733 4734 else if (STORE_FLAG_VALUE == -1 4735 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4736 && op1 == const0_rtx 4737 && mode == GET_MODE (op0) 4738 && (num_sign_bit_copies (op0, mode) 4739 == GET_MODE_BITSIZE (mode))) 4740 { 4741 op0 = expand_compound_operation (op0); 4742 return simplify_gen_unary (NOT, mode, 4743 gen_lowpart (mode, op0), 4744 mode); 4745 } 4746 4747 /* If X is 0/1, (eq X 0) is X-1. */ 4748 else if (STORE_FLAG_VALUE == -1 4749 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4750 && op1 == const0_rtx 4751 && mode == GET_MODE (op0) 4752 && nonzero_bits (op0, mode) == 1) 4753 { 4754 op0 = expand_compound_operation (op0); 4755 return plus_constant (gen_lowpart (mode, op0), -1); 4756 } 4757 4758 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just 4759 one bit that might be nonzero, we can convert (ne x 0) to 4760 (ashift x c) where C puts the bit in the sign bit. Remove any 4761 AND with STORE_FLAG_VALUE when we are done, since we are only 4762 going to test the sign bit. */ 4763 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4764 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4765 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) 4766 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) 4767 && op1 == const0_rtx 4768 && mode == GET_MODE (op0) 4769 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) 4770 { 4771 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, 4772 expand_compound_operation (op0), 4773 GET_MODE_BITSIZE (mode) - 1 - i); 4774 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) 4775 return XEXP (x, 0); 4776 else 4777 return x; 4778 } 4779 4780 /* If the code changed, return a whole new comparison. */ 4781 if (new_code != code) 4782 return gen_rtx_fmt_ee (new_code, mode, op0, op1); 4783 4784 /* Otherwise, keep this operation, but maybe change its operands. 4785 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ 4786 SUBST (XEXP (x, 0), op0); 4787 SUBST (XEXP (x, 1), op1); 4788 } 4789 break; 4790 4791 case IF_THEN_ELSE: 4792 return simplify_if_then_else (x); 4793 4794 case ZERO_EXTRACT: 4795 case SIGN_EXTRACT: 4796 case ZERO_EXTEND: 4797 case SIGN_EXTEND: 4798 /* If we are processing SET_DEST, we are done. */ 4799 if (in_dest) 4800 return x; 4801 4802 return expand_compound_operation (x); 4803 4804 case SET: 4805 return simplify_set (x); 4806 4807 case AND: 4808 case IOR: 4809 return simplify_logical (x); 4810 4811 case ASHIFT: 4812 case LSHIFTRT: 4813 case ASHIFTRT: 4814 case ROTATE: 4815 case ROTATERT: 4816 /* If this is a shift by a constant amount, simplify it. */ 4817 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 4818 return simplify_shift_const (x, code, mode, XEXP (x, 0), 4819 INTVAL (XEXP (x, 1))); 4820 4821 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1))) 4822 SUBST (XEXP (x, 1), 4823 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)), 4824 ((HOST_WIDE_INT) 1 4825 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) 4826 - 1, 4827 0)); 4828 break; 4829 4830 default: 4831 break; 4832 } 4833 4834 return x; 4835} 4836 4837/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ 4838 4839static rtx 4840simplify_if_then_else (rtx x) 4841{ 4842 enum machine_mode mode = GET_MODE (x); 4843 rtx cond = XEXP (x, 0); 4844 rtx true_rtx = XEXP (x, 1); 4845 rtx false_rtx = XEXP (x, 2); 4846 enum rtx_code true_code = GET_CODE (cond); 4847 int comparison_p = COMPARISON_P (cond); 4848 rtx temp; 4849 int i; 4850 enum rtx_code false_code; 4851 rtx reversed; 4852 4853 /* Simplify storing of the truth value. */ 4854 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx) 4855 return simplify_gen_relational (true_code, mode, VOIDmode, 4856 XEXP (cond, 0), XEXP (cond, 1)); 4857 4858 /* Also when the truth value has to be reversed. */ 4859 if (comparison_p 4860 && true_rtx == const0_rtx && false_rtx == const_true_rtx 4861 && (reversed = reversed_comparison (cond, mode))) 4862 return reversed; 4863 4864 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used 4865 in it is being compared against certain values. Get the true and false 4866 comparisons and see if that says anything about the value of each arm. */ 4867 4868 if (comparison_p 4869 && ((false_code = reversed_comparison_code (cond, NULL)) 4870 != UNKNOWN) 4871 && REG_P (XEXP (cond, 0))) 4872 { 4873 HOST_WIDE_INT nzb; 4874 rtx from = XEXP (cond, 0); 4875 rtx true_val = XEXP (cond, 1); 4876 rtx false_val = true_val; 4877 int swapped = 0; 4878 4879 /* If FALSE_CODE is EQ, swap the codes and arms. */ 4880 4881 if (false_code == EQ) 4882 { 4883 swapped = 1, true_code = EQ, false_code = NE; 4884 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; 4885 } 4886 4887 /* If we are comparing against zero and the expression being tested has 4888 only a single bit that might be nonzero, that is its value when it is 4889 not equal to zero. Similarly if it is known to be -1 or 0. */ 4890 4891 if (true_code == EQ && true_val == const0_rtx 4892 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) 4893 false_code = EQ, false_val = GEN_INT (nzb); 4894 else if (true_code == EQ && true_val == const0_rtx 4895 && (num_sign_bit_copies (from, GET_MODE (from)) 4896 == GET_MODE_BITSIZE (GET_MODE (from)))) 4897 false_code = EQ, false_val = constm1_rtx; 4898 4899 /* Now simplify an arm if we know the value of the register in the 4900 branch and it is used in the arm. Be careful due to the potential 4901 of locally-shared RTL. */ 4902 4903 if (reg_mentioned_p (from, true_rtx)) 4904 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, 4905 from, true_val), 4906 pc_rtx, pc_rtx, 0, 0); 4907 if (reg_mentioned_p (from, false_rtx)) 4908 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, 4909 from, false_val), 4910 pc_rtx, pc_rtx, 0, 0); 4911 4912 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); 4913 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); 4914 4915 true_rtx = XEXP (x, 1); 4916 false_rtx = XEXP (x, 2); 4917 true_code = GET_CODE (cond); 4918 } 4919 4920 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be 4921 reversed, do so to avoid needing two sets of patterns for 4922 subtract-and-branch insns. Similarly if we have a constant in the true 4923 arm, the false arm is the same as the first operand of the comparison, or 4924 the false arm is more complicated than the true arm. */ 4925 4926 if (comparison_p 4927 && reversed_comparison_code (cond, NULL) != UNKNOWN 4928 && (true_rtx == pc_rtx 4929 || (CONSTANT_P (true_rtx) 4930 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx) 4931 || true_rtx == const0_rtx 4932 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx)) 4933 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx)) 4934 && !OBJECT_P (false_rtx)) 4935 || reg_mentioned_p (true_rtx, false_rtx) 4936 || rtx_equal_p (false_rtx, XEXP (cond, 0)))) 4937 { 4938 true_code = reversed_comparison_code (cond, NULL); 4939 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond))); 4940 SUBST (XEXP (x, 1), false_rtx); 4941 SUBST (XEXP (x, 2), true_rtx); 4942 4943 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; 4944 cond = XEXP (x, 0); 4945 4946 /* It is possible that the conditional has been simplified out. */ 4947 true_code = GET_CODE (cond); 4948 comparison_p = COMPARISON_P (cond); 4949 } 4950 4951 /* If the two arms are identical, we don't need the comparison. */ 4952 4953 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond)) 4954 return true_rtx; 4955 4956 /* Convert a == b ? b : a to "a". */ 4957 if (true_code == EQ && ! side_effects_p (cond) 4958 && !HONOR_NANS (mode) 4959 && rtx_equal_p (XEXP (cond, 0), false_rtx) 4960 && rtx_equal_p (XEXP (cond, 1), true_rtx)) 4961 return false_rtx; 4962 else if (true_code == NE && ! side_effects_p (cond) 4963 && !HONOR_NANS (mode) 4964 && rtx_equal_p (XEXP (cond, 0), true_rtx) 4965 && rtx_equal_p (XEXP (cond, 1), false_rtx)) 4966 return true_rtx; 4967 4968 /* Look for cases where we have (abs x) or (neg (abs X)). */ 4969 4970 if (GET_MODE_CLASS (mode) == MODE_INT 4971 && GET_CODE (false_rtx) == NEG 4972 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0)) 4973 && comparison_p 4974 && rtx_equal_p (true_rtx, XEXP (cond, 0)) 4975 && ! side_effects_p (true_rtx)) 4976 switch (true_code) 4977 { 4978 case GT: 4979 case GE: 4980 return simplify_gen_unary (ABS, mode, true_rtx, mode); 4981 case LT: 4982 case LE: 4983 return 4984 simplify_gen_unary (NEG, mode, 4985 simplify_gen_unary (ABS, mode, true_rtx, mode), 4986 mode); 4987 default: 4988 break; 4989 } 4990 4991 /* Look for MIN or MAX. */ 4992 4993 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) 4994 && comparison_p 4995 && rtx_equal_p (XEXP (cond, 0), true_rtx) 4996 && rtx_equal_p (XEXP (cond, 1), false_rtx) 4997 && ! side_effects_p (cond)) 4998 switch (true_code) 4999 { 5000 case GE: 5001 case GT: 5002 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx); 5003 case LE: 5004 case LT: 5005 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx); 5006 case GEU: 5007 case GTU: 5008 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx); 5009 case LEU: 5010 case LTU: 5011 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx); 5012 default: 5013 break; 5014 } 5015 5016 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its 5017 second operand is zero, this can be done as (OP Z (mult COND C2)) where 5018 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or 5019 SIGN_EXTEND as long as Z is already extended (so we don't destroy it). 5020 We can do this kind of thing in some cases when STORE_FLAG_VALUE is 5021 neither 1 or -1, but it isn't worth checking for. */ 5022 5023 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 5024 && comparison_p 5025 && GET_MODE_CLASS (mode) == MODE_INT 5026 && ! side_effects_p (x)) 5027 { 5028 rtx t = make_compound_operation (true_rtx, SET); 5029 rtx f = make_compound_operation (false_rtx, SET); 5030 rtx cond_op0 = XEXP (cond, 0); 5031 rtx cond_op1 = XEXP (cond, 1); 5032 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN; 5033 enum machine_mode m = mode; 5034 rtx z = 0, c1 = NULL_RTX; 5035 5036 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS 5037 || GET_CODE (t) == IOR || GET_CODE (t) == XOR 5038 || GET_CODE (t) == ASHIFT 5039 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) 5040 && rtx_equal_p (XEXP (t, 0), f)) 5041 c1 = XEXP (t, 1), op = GET_CODE (t), z = f; 5042 5043 /* If an identity-zero op is commutative, check whether there 5044 would be a match if we swapped the operands. */ 5045 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR 5046 || GET_CODE (t) == XOR) 5047 && rtx_equal_p (XEXP (t, 1), f)) 5048 c1 = XEXP (t, 0), op = GET_CODE (t), z = f; 5049 else if (GET_CODE (t) == SIGN_EXTEND 5050 && (GET_CODE (XEXP (t, 0)) == PLUS 5051 || GET_CODE (XEXP (t, 0)) == MINUS 5052 || GET_CODE (XEXP (t, 0)) == IOR 5053 || GET_CODE (XEXP (t, 0)) == XOR 5054 || GET_CODE (XEXP (t, 0)) == ASHIFT 5055 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 5056 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 5057 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 5058 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 5059 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 5060 && (num_sign_bit_copies (f, GET_MODE (f)) 5061 > (unsigned int) 5062 (GET_MODE_BITSIZE (mode) 5063 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0)))))) 5064 { 5065 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 5066 extend_op = SIGN_EXTEND; 5067 m = GET_MODE (XEXP (t, 0)); 5068 } 5069 else if (GET_CODE (t) == SIGN_EXTEND 5070 && (GET_CODE (XEXP (t, 0)) == PLUS 5071 || GET_CODE (XEXP (t, 0)) == IOR 5072 || GET_CODE (XEXP (t, 0)) == XOR) 5073 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 5074 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 5075 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 5076 && (num_sign_bit_copies (f, GET_MODE (f)) 5077 > (unsigned int) 5078 (GET_MODE_BITSIZE (mode) 5079 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1)))))) 5080 { 5081 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 5082 extend_op = SIGN_EXTEND; 5083 m = GET_MODE (XEXP (t, 0)); 5084 } 5085 else if (GET_CODE (t) == ZERO_EXTEND 5086 && (GET_CODE (XEXP (t, 0)) == PLUS 5087 || GET_CODE (XEXP (t, 0)) == MINUS 5088 || GET_CODE (XEXP (t, 0)) == IOR 5089 || GET_CODE (XEXP (t, 0)) == XOR 5090 || GET_CODE (XEXP (t, 0)) == ASHIFT 5091 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 5092 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 5093 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 5094 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5095 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 5096 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 5097 && ((nonzero_bits (f, GET_MODE (f)) 5098 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) 5099 == 0)) 5100 { 5101 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 5102 extend_op = ZERO_EXTEND; 5103 m = GET_MODE (XEXP (t, 0)); 5104 } 5105 else if (GET_CODE (t) == ZERO_EXTEND 5106 && (GET_CODE (XEXP (t, 0)) == PLUS 5107 || GET_CODE (XEXP (t, 0)) == IOR 5108 || GET_CODE (XEXP (t, 0)) == XOR) 5109 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 5110 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5111 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 5112 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 5113 && ((nonzero_bits (f, GET_MODE (f)) 5114 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) 5115 == 0)) 5116 { 5117 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 5118 extend_op = ZERO_EXTEND; 5119 m = GET_MODE (XEXP (t, 0)); 5120 } 5121 5122 if (z) 5123 { 5124 temp = subst (simplify_gen_relational (true_code, m, VOIDmode, 5125 cond_op0, cond_op1), 5126 pc_rtx, pc_rtx, 0, 0); 5127 temp = simplify_gen_binary (MULT, m, temp, 5128 simplify_gen_binary (MULT, m, c1, 5129 const_true_rtx)); 5130 temp = subst (temp, pc_rtx, pc_rtx, 0, 0); 5131 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp); 5132 5133 if (extend_op != UNKNOWN) 5134 temp = simplify_gen_unary (extend_op, mode, temp, m); 5135 5136 return temp; 5137 } 5138 } 5139 5140 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or 5141 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the 5142 negation of a single bit, we can convert this operation to a shift. We 5143 can actually do this more generally, but it doesn't seem worth it. */ 5144 5145 if (true_code == NE && XEXP (cond, 1) == const0_rtx 5146 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT 5147 && ((1 == nonzero_bits (XEXP (cond, 0), mode) 5148 && (i = exact_log2 (INTVAL (true_rtx))) >= 0) 5149 || ((num_sign_bit_copies (XEXP (cond, 0), mode) 5150 == GET_MODE_BITSIZE (mode)) 5151 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0))) 5152 return 5153 simplify_shift_const (NULL_RTX, ASHIFT, mode, 5154 gen_lowpart (mode, XEXP (cond, 0)), i); 5155 5156 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */ 5157 if (true_code == NE && XEXP (cond, 1) == const0_rtx 5158 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT 5159 && GET_MODE (XEXP (cond, 0)) == mode 5160 && (INTVAL (true_rtx) & GET_MODE_MASK (mode)) 5161 == nonzero_bits (XEXP (cond, 0), mode) 5162 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0) 5163 return XEXP (cond, 0); 5164 5165 return x; 5166} 5167 5168/* Simplify X, a SET expression. Return the new expression. */ 5169 5170static rtx 5171simplify_set (rtx x) 5172{ 5173 rtx src = SET_SRC (x); 5174 rtx dest = SET_DEST (x); 5175 enum machine_mode mode 5176 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); 5177 rtx other_insn; 5178 rtx *cc_use; 5179 5180 /* (set (pc) (return)) gets written as (return). */ 5181 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN) 5182 return src; 5183 5184 /* Now that we know for sure which bits of SRC we are using, see if we can 5185 simplify the expression for the object knowing that we only need the 5186 low-order bits. */ 5187 5188 if (GET_MODE_CLASS (mode) == MODE_INT 5189 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 5190 { 5191 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0); 5192 SUBST (SET_SRC (x), src); 5193 } 5194 5195 /* If we are setting CC0 or if the source is a COMPARE, look for the use of 5196 the comparison result and try to simplify it unless we already have used 5197 undobuf.other_insn. */ 5198 if ((GET_MODE_CLASS (mode) == MODE_CC 5199 || GET_CODE (src) == COMPARE 5200 || CC0_P (dest)) 5201 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 5202 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) 5203 && COMPARISON_P (*cc_use) 5204 && rtx_equal_p (XEXP (*cc_use, 0), dest)) 5205 { 5206 enum rtx_code old_code = GET_CODE (*cc_use); 5207 enum rtx_code new_code; 5208 rtx op0, op1, tmp; 5209 int other_changed = 0; 5210 enum machine_mode compare_mode = GET_MODE (dest); 5211 5212 if (GET_CODE (src) == COMPARE) 5213 op0 = XEXP (src, 0), op1 = XEXP (src, 1); 5214 else 5215 op0 = src, op1 = CONST0_RTX (GET_MODE (src)); 5216 5217 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode, 5218 op0, op1); 5219 if (!tmp) 5220 new_code = old_code; 5221 else if (!CONSTANT_P (tmp)) 5222 { 5223 new_code = GET_CODE (tmp); 5224 op0 = XEXP (tmp, 0); 5225 op1 = XEXP (tmp, 1); 5226 } 5227 else 5228 { 5229 rtx pat = PATTERN (other_insn); 5230 undobuf.other_insn = other_insn; 5231 SUBST (*cc_use, tmp); 5232 5233 /* Attempt to simplify CC user. */ 5234 if (GET_CODE (pat) == SET) 5235 { 5236 rtx new = simplify_rtx (SET_SRC (pat)); 5237 if (new != NULL_RTX) 5238 SUBST (SET_SRC (pat), new); 5239 } 5240 5241 /* Convert X into a no-op move. */ 5242 SUBST (SET_DEST (x), pc_rtx); 5243 SUBST (SET_SRC (x), pc_rtx); 5244 return x; 5245 } 5246 5247 /* Simplify our comparison, if possible. */ 5248 new_code = simplify_comparison (new_code, &op0, &op1); 5249 5250#ifdef SELECT_CC_MODE 5251 /* If this machine has CC modes other than CCmode, check to see if we 5252 need to use a different CC mode here. */ 5253 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) 5254 compare_mode = GET_MODE (op0); 5255 else 5256 compare_mode = SELECT_CC_MODE (new_code, op0, op1); 5257 5258#ifndef HAVE_cc0 5259 /* If the mode changed, we have to change SET_DEST, the mode in the 5260 compare, and the mode in the place SET_DEST is used. If SET_DEST is 5261 a hard register, just build new versions with the proper mode. If it 5262 is a pseudo, we lose unless it is only time we set the pseudo, in 5263 which case we can safely change its mode. */ 5264 if (compare_mode != GET_MODE (dest)) 5265 { 5266 if (can_change_dest_mode (dest, 0, compare_mode)) 5267 { 5268 unsigned int regno = REGNO (dest); 5269 rtx new_dest; 5270 5271 if (regno < FIRST_PSEUDO_REGISTER) 5272 new_dest = gen_rtx_REG (compare_mode, regno); 5273 else 5274 { 5275 SUBST_MODE (regno_reg_rtx[regno], compare_mode); 5276 new_dest = regno_reg_rtx[regno]; 5277 } 5278 5279 SUBST (SET_DEST (x), new_dest); 5280 SUBST (XEXP (*cc_use, 0), new_dest); 5281 other_changed = 1; 5282 5283 dest = new_dest; 5284 } 5285 } 5286#endif /* cc0 */ 5287#endif /* SELECT_CC_MODE */ 5288 5289 /* If the code changed, we have to build a new comparison in 5290 undobuf.other_insn. */ 5291 if (new_code != old_code) 5292 { 5293 int other_changed_previously = other_changed; 5294 unsigned HOST_WIDE_INT mask; 5295 5296 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use), 5297 dest, const0_rtx)); 5298 other_changed = 1; 5299 5300 /* If the only change we made was to change an EQ into an NE or 5301 vice versa, OP0 has only one bit that might be nonzero, and OP1 5302 is zero, check if changing the user of the condition code will 5303 produce a valid insn. If it won't, we can keep the original code 5304 in that insn by surrounding our operation with an XOR. */ 5305 5306 if (((old_code == NE && new_code == EQ) 5307 || (old_code == EQ && new_code == NE)) 5308 && ! other_changed_previously && op1 == const0_rtx 5309 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 5310 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0) 5311 { 5312 rtx pat = PATTERN (other_insn), note = 0; 5313 5314 if ((recog_for_combine (&pat, other_insn, ¬e) < 0 5315 && ! check_asm_operands (pat))) 5316 { 5317 PUT_CODE (*cc_use, old_code); 5318 other_changed = 0; 5319 5320 op0 = simplify_gen_binary (XOR, GET_MODE (op0), 5321 op0, GEN_INT (mask)); 5322 } 5323 } 5324 } 5325 5326 if (other_changed) 5327 undobuf.other_insn = other_insn; 5328 5329#ifdef HAVE_cc0 5330 /* If we are now comparing against zero, change our source if 5331 needed. If we do not use cc0, we always have a COMPARE. */ 5332 if (op1 == const0_rtx && dest == cc0_rtx) 5333 { 5334 SUBST (SET_SRC (x), op0); 5335 src = op0; 5336 } 5337 else 5338#endif 5339 5340 /* Otherwise, if we didn't previously have a COMPARE in the 5341 correct mode, we need one. */ 5342 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode) 5343 { 5344 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); 5345 src = SET_SRC (x); 5346 } 5347 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx) 5348 { 5349 SUBST (SET_SRC (x), op0); 5350 src = SET_SRC (x); 5351 } 5352 /* Otherwise, update the COMPARE if needed. */ 5353 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1) 5354 { 5355 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); 5356 src = SET_SRC (x); 5357 } 5358 } 5359 else 5360 { 5361 /* Get SET_SRC in a form where we have placed back any 5362 compound expressions. Then do the checks below. */ 5363 src = make_compound_operation (src, SET); 5364 SUBST (SET_SRC (x), src); 5365 } 5366 5367 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, 5368 and X being a REG or (subreg (reg)), we may be able to convert this to 5369 (set (subreg:m2 x) (op)). 5370 5371 We can always do this if M1 is narrower than M2 because that means that 5372 we only care about the low bits of the result. 5373 5374 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot 5375 perform a narrower operation than requested since the high-order bits will 5376 be undefined. On machine where it is defined, this transformation is safe 5377 as long as M1 and M2 have the same number of words. */ 5378 5379 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 5380 && !OBJECT_P (SUBREG_REG (src)) 5381 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) 5382 / UNITS_PER_WORD) 5383 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) 5384 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) 5385#ifndef WORD_REGISTER_OPERATIONS 5386 && (GET_MODE_SIZE (GET_MODE (src)) 5387 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) 5388#endif 5389#ifdef CANNOT_CHANGE_MODE_CLASS 5390 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER 5391 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest), 5392 GET_MODE (SUBREG_REG (src)), 5393 GET_MODE (src))) 5394#endif 5395 && (REG_P (dest) 5396 || (GET_CODE (dest) == SUBREG 5397 && REG_P (SUBREG_REG (dest))))) 5398 { 5399 SUBST (SET_DEST (x), 5400 gen_lowpart (GET_MODE (SUBREG_REG (src)), 5401 dest)); 5402 SUBST (SET_SRC (x), SUBREG_REG (src)); 5403 5404 src = SET_SRC (x), dest = SET_DEST (x); 5405 } 5406 5407#ifdef HAVE_cc0 5408 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg 5409 in SRC. */ 5410 if (dest == cc0_rtx 5411 && GET_CODE (src) == SUBREG 5412 && subreg_lowpart_p (src) 5413 && (GET_MODE_BITSIZE (GET_MODE (src)) 5414 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src))))) 5415 { 5416 rtx inner = SUBREG_REG (src); 5417 enum machine_mode inner_mode = GET_MODE (inner); 5418 5419 /* Here we make sure that we don't have a sign bit on. */ 5420 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT 5421 && (nonzero_bits (inner, inner_mode) 5422 < ((unsigned HOST_WIDE_INT) 1 5423 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1)))) 5424 { 5425 SUBST (SET_SRC (x), inner); 5426 src = SET_SRC (x); 5427 } 5428 } 5429#endif 5430 5431#ifdef LOAD_EXTEND_OP 5432 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this 5433 would require a paradoxical subreg. Replace the subreg with a 5434 zero_extend to avoid the reload that would otherwise be required. */ 5435 5436 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 5437 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN 5438 && SUBREG_BYTE (src) == 0 5439 && (GET_MODE_SIZE (GET_MODE (src)) 5440 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) 5441 && MEM_P (SUBREG_REG (src))) 5442 { 5443 SUBST (SET_SRC (x), 5444 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))), 5445 GET_MODE (src), SUBREG_REG (src))); 5446 5447 src = SET_SRC (x); 5448 } 5449#endif 5450 5451 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we 5452 are comparing an item known to be 0 or -1 against 0, use a logical 5453 operation instead. Check for one of the arms being an IOR of the other 5454 arm with some value. We compute three terms to be IOR'ed together. In 5455 practice, at most two will be nonzero. Then we do the IOR's. */ 5456 5457 if (GET_CODE (dest) != PC 5458 && GET_CODE (src) == IF_THEN_ELSE 5459 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT 5460 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) 5461 && XEXP (XEXP (src, 0), 1) == const0_rtx 5462 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) 5463#ifdef HAVE_conditional_move 5464 && ! can_conditionally_move_p (GET_MODE (src)) 5465#endif 5466 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), 5467 GET_MODE (XEXP (XEXP (src, 0), 0))) 5468 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0)))) 5469 && ! side_effects_p (src)) 5470 { 5471 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE 5472 ? XEXP (src, 1) : XEXP (src, 2)); 5473 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE 5474 ? XEXP (src, 2) : XEXP (src, 1)); 5475 rtx term1 = const0_rtx, term2, term3; 5476 5477 if (GET_CODE (true_rtx) == IOR 5478 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx)) 5479 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx; 5480 else if (GET_CODE (true_rtx) == IOR 5481 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx)) 5482 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx; 5483 else if (GET_CODE (false_rtx) == IOR 5484 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx)) 5485 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx; 5486 else if (GET_CODE (false_rtx) == IOR 5487 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx)) 5488 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx; 5489 5490 term2 = simplify_gen_binary (AND, GET_MODE (src), 5491 XEXP (XEXP (src, 0), 0), true_rtx); 5492 term3 = simplify_gen_binary (AND, GET_MODE (src), 5493 simplify_gen_unary (NOT, GET_MODE (src), 5494 XEXP (XEXP (src, 0), 0), 5495 GET_MODE (src)), 5496 false_rtx); 5497 5498 SUBST (SET_SRC (x), 5499 simplify_gen_binary (IOR, GET_MODE (src), 5500 simplify_gen_binary (IOR, GET_MODE (src), 5501 term1, term2), 5502 term3)); 5503 5504 src = SET_SRC (x); 5505 } 5506 5507 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this 5508 whole thing fail. */ 5509 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) 5510 return src; 5511 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) 5512 return dest; 5513 else 5514 /* Convert this into a field assignment operation, if possible. */ 5515 return make_field_assignment (x); 5516} 5517 5518/* Simplify, X, and AND, IOR, or XOR operation, and return the simplified 5519 result. */ 5520 5521static rtx 5522simplify_logical (rtx x) 5523{ 5524 enum machine_mode mode = GET_MODE (x); 5525 rtx op0 = XEXP (x, 0); 5526 rtx op1 = XEXP (x, 1); 5527 5528 switch (GET_CODE (x)) 5529 { 5530 case AND: 5531 /* We can call simplify_and_const_int only if we don't lose 5532 any (sign) bits when converting INTVAL (op1) to 5533 "unsigned HOST_WIDE_INT". */ 5534 if (GET_CODE (op1) == CONST_INT 5535 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5536 || INTVAL (op1) > 0)) 5537 { 5538 x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); 5539 if (GET_CODE (x) != AND) 5540 return x; 5541 5542 op0 = XEXP (x, 0); 5543 op1 = XEXP (x, 1); 5544 } 5545 5546 /* If we have any of (and (ior A B) C) or (and (xor A B) C), 5547 apply the distributive law and then the inverse distributive 5548 law to see if things simplify. */ 5549 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) 5550 { 5551 rtx result = distribute_and_simplify_rtx (x, 0); 5552 if (result) 5553 return result; 5554 } 5555 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) 5556 { 5557 rtx result = distribute_and_simplify_rtx (x, 1); 5558 if (result) 5559 return result; 5560 } 5561 break; 5562 5563 case IOR: 5564 /* If we have (ior (and A B) C), apply the distributive law and then 5565 the inverse distributive law to see if things simplify. */ 5566 5567 if (GET_CODE (op0) == AND) 5568 { 5569 rtx result = distribute_and_simplify_rtx (x, 0); 5570 if (result) 5571 return result; 5572 } 5573 5574 if (GET_CODE (op1) == AND) 5575 { 5576 rtx result = distribute_and_simplify_rtx (x, 1); 5577 if (result) 5578 return result; 5579 } 5580 break; 5581 5582 default: 5583 gcc_unreachable (); 5584 } 5585 5586 return x; 5587} 5588 5589/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound 5590 operations" because they can be replaced with two more basic operations. 5591 ZERO_EXTEND is also considered "compound" because it can be replaced with 5592 an AND operation, which is simpler, though only one operation. 5593 5594 The function expand_compound_operation is called with an rtx expression 5595 and will convert it to the appropriate shifts and AND operations, 5596 simplifying at each stage. 5597 5598 The function make_compound_operation is called to convert an expression 5599 consisting of shifts and ANDs into the equivalent compound expression. 5600 It is the inverse of this function, loosely speaking. */ 5601 5602static rtx 5603expand_compound_operation (rtx x) 5604{ 5605 unsigned HOST_WIDE_INT pos = 0, len; 5606 int unsignedp = 0; 5607 unsigned int modewidth; 5608 rtx tem; 5609 5610 switch (GET_CODE (x)) 5611 { 5612 case ZERO_EXTEND: 5613 unsignedp = 1; 5614 case SIGN_EXTEND: 5615 /* We can't necessarily use a const_int for a multiword mode; 5616 it depends on implicitly extending the value. 5617 Since we don't know the right way to extend it, 5618 we can't tell whether the implicit way is right. 5619 5620 Even for a mode that is no wider than a const_int, 5621 we can't win, because we need to sign extend one of its bits through 5622 the rest of it, and we don't know which bit. */ 5623 if (GET_CODE (XEXP (x, 0)) == CONST_INT) 5624 return x; 5625 5626 /* Return if (subreg:MODE FROM 0) is not a safe replacement for 5627 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM 5628 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be 5629 reloaded. If not for that, MEM's would very rarely be safe. 5630 5631 Reject MODEs bigger than a word, because we might not be able 5632 to reference a two-register group starting with an arbitrary register 5633 (and currently gen_lowpart might crash for a SUBREG). */ 5634 5635 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) 5636 return x; 5637 5638 /* Reject MODEs that aren't scalar integers because turning vector 5639 or complex modes into shifts causes problems. */ 5640 5641 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) 5642 return x; 5643 5644 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))); 5645 /* If the inner object has VOIDmode (the only way this can happen 5646 is if it is an ASM_OPERANDS), we can't do anything since we don't 5647 know how much masking to do. */ 5648 if (len == 0) 5649 return x; 5650 5651 break; 5652 5653 case ZERO_EXTRACT: 5654 unsignedp = 1; 5655 5656 /* ... fall through ... */ 5657 5658 case SIGN_EXTRACT: 5659 /* If the operand is a CLOBBER, just return it. */ 5660 if (GET_CODE (XEXP (x, 0)) == CLOBBER) 5661 return XEXP (x, 0); 5662 5663 if (GET_CODE (XEXP (x, 1)) != CONST_INT 5664 || GET_CODE (XEXP (x, 2)) != CONST_INT 5665 || GET_MODE (XEXP (x, 0)) == VOIDmode) 5666 return x; 5667 5668 /* Reject MODEs that aren't scalar integers because turning vector 5669 or complex modes into shifts causes problems. */ 5670 5671 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) 5672 return x; 5673 5674 len = INTVAL (XEXP (x, 1)); 5675 pos = INTVAL (XEXP (x, 2)); 5676 5677 /* This should stay within the object being extracted, fail otherwise. */ 5678 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) 5679 return x; 5680 5681 if (BITS_BIG_ENDIAN) 5682 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos; 5683 5684 break; 5685 5686 default: 5687 return x; 5688 } 5689 /* Convert sign extension to zero extension, if we know that the high 5690 bit is not set, as this is easier to optimize. It will be converted 5691 back to cheaper alternative in make_extraction. */ 5692 if (GET_CODE (x) == SIGN_EXTEND 5693 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5694 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 5695 & ~(((unsigned HOST_WIDE_INT) 5696 GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) 5697 >> 1)) 5698 == 0))) 5699 { 5700 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0)); 5701 rtx temp2 = expand_compound_operation (temp); 5702 5703 /* Make sure this is a profitable operation. */ 5704 if (rtx_cost (x, SET) > rtx_cost (temp2, SET)) 5705 return temp2; 5706 else if (rtx_cost (x, SET) > rtx_cost (temp, SET)) 5707 return temp; 5708 else 5709 return x; 5710 } 5711 5712 /* We can optimize some special cases of ZERO_EXTEND. */ 5713 if (GET_CODE (x) == ZERO_EXTEND) 5714 { 5715 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we 5716 know that the last value didn't have any inappropriate bits 5717 set. */ 5718 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 5719 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 5720 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5721 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x)) 5722 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5723 return XEXP (XEXP (x, 0), 0); 5724 5725 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 5726 if (GET_CODE (XEXP (x, 0)) == SUBREG 5727 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 5728 && subreg_lowpart_p (XEXP (x, 0)) 5729 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5730 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x)) 5731 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5732 return SUBREG_REG (XEXP (x, 0)); 5733 5734 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo 5735 is a comparison and STORE_FLAG_VALUE permits. This is like 5736 the first case, but it works even when GET_MODE (x) is larger 5737 than HOST_WIDE_INT. */ 5738 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 5739 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 5740 && COMPARISON_P (XEXP (XEXP (x, 0), 0)) 5741 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 5742 <= HOST_BITS_PER_WIDE_INT) 5743 && ((HOST_WIDE_INT) STORE_FLAG_VALUE 5744 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5745 return XEXP (XEXP (x, 0), 0); 5746 5747 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 5748 if (GET_CODE (XEXP (x, 0)) == SUBREG 5749 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 5750 && subreg_lowpart_p (XEXP (x, 0)) 5751 && COMPARISON_P (SUBREG_REG (XEXP (x, 0))) 5752 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 5753 <= HOST_BITS_PER_WIDE_INT) 5754 && ((HOST_WIDE_INT) STORE_FLAG_VALUE 5755 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5756 return SUBREG_REG (XEXP (x, 0)); 5757 5758 } 5759 5760 /* If we reach here, we want to return a pair of shifts. The inner 5761 shift is a left shift of BITSIZE - POS - LEN bits. The outer 5762 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or 5763 logical depending on the value of UNSIGNEDP. 5764 5765 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be 5766 converted into an AND of a shift. 5767 5768 We must check for the case where the left shift would have a negative 5769 count. This can happen in a case like (x >> 31) & 255 on machines 5770 that can't shift by a constant. On those machines, we would first 5771 combine the shift with the AND to produce a variable-position 5772 extraction. Then the constant of 31 would be substituted in to produce 5773 a such a position. */ 5774 5775 modewidth = GET_MODE_BITSIZE (GET_MODE (x)); 5776 if (modewidth + len >= pos) 5777 { 5778 enum machine_mode mode = GET_MODE (x); 5779 tem = gen_lowpart (mode, XEXP (x, 0)); 5780 if (!tem || GET_CODE (tem) == CLOBBER) 5781 return x; 5782 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode, 5783 tem, modewidth - pos - len); 5784 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, 5785 mode, tem, modewidth - len); 5786 } 5787 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) 5788 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), 5789 simplify_shift_const (NULL_RTX, LSHIFTRT, 5790 GET_MODE (x), 5791 XEXP (x, 0), pos), 5792 ((HOST_WIDE_INT) 1 << len) - 1); 5793 else 5794 /* Any other cases we can't handle. */ 5795 return x; 5796 5797 /* If we couldn't do this for some reason, return the original 5798 expression. */ 5799 if (GET_CODE (tem) == CLOBBER) 5800 return x; 5801 5802 return tem; 5803} 5804 5805/* X is a SET which contains an assignment of one object into 5806 a part of another (such as a bit-field assignment, STRICT_LOW_PART, 5807 or certain SUBREGS). If possible, convert it into a series of 5808 logical operations. 5809 5810 We half-heartedly support variable positions, but do not at all 5811 support variable lengths. */ 5812 5813static rtx 5814expand_field_assignment (rtx x) 5815{ 5816 rtx inner; 5817 rtx pos; /* Always counts from low bit. */ 5818 int len; 5819 rtx mask, cleared, masked; 5820 enum machine_mode compute_mode; 5821 5822 /* Loop until we find something we can't simplify. */ 5823 while (1) 5824 { 5825 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART 5826 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) 5827 { 5828 inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); 5829 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))); 5830 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0))); 5831 } 5832 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 5833 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT) 5834 { 5835 inner = XEXP (SET_DEST (x), 0); 5836 len = INTVAL (XEXP (SET_DEST (x), 1)); 5837 pos = XEXP (SET_DEST (x), 2); 5838 5839 /* A constant position should stay within the width of INNER. */ 5840 if (GET_CODE (pos) == CONST_INT 5841 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner))) 5842 break; 5843 5844 if (BITS_BIG_ENDIAN) 5845 { 5846 if (GET_CODE (pos) == CONST_INT) 5847 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len 5848 - INTVAL (pos)); 5849 else if (GET_CODE (pos) == MINUS 5850 && GET_CODE (XEXP (pos, 1)) == CONST_INT 5851 && (INTVAL (XEXP (pos, 1)) 5852 == GET_MODE_BITSIZE (GET_MODE (inner)) - len)) 5853 /* If position is ADJUST - X, new position is X. */ 5854 pos = XEXP (pos, 0); 5855 else 5856 pos = simplify_gen_binary (MINUS, GET_MODE (pos), 5857 GEN_INT (GET_MODE_BITSIZE ( 5858 GET_MODE (inner)) 5859 - len), 5860 pos); 5861 } 5862 } 5863 5864 /* A SUBREG between two modes that occupy the same numbers of words 5865 can be done by moving the SUBREG to the source. */ 5866 else if (GET_CODE (SET_DEST (x)) == SUBREG 5867 /* We need SUBREGs to compute nonzero_bits properly. */ 5868 && nonzero_sign_valid 5869 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) 5870 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 5871 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) 5872 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) 5873 { 5874 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)), 5875 gen_lowpart 5876 (GET_MODE (SUBREG_REG (SET_DEST (x))), 5877 SET_SRC (x))); 5878 continue; 5879 } 5880 else 5881 break; 5882 5883 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 5884 inner = SUBREG_REG (inner); 5885 5886 compute_mode = GET_MODE (inner); 5887 5888 /* Don't attempt bitwise arithmetic on non scalar integer modes. */ 5889 if (! SCALAR_INT_MODE_P (compute_mode)) 5890 { 5891 enum machine_mode imode; 5892 5893 /* Don't do anything for vector or complex integral types. */ 5894 if (! FLOAT_MODE_P (compute_mode)) 5895 break; 5896 5897 /* Try to find an integral mode to pun with. */ 5898 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0); 5899 if (imode == BLKmode) 5900 break; 5901 5902 compute_mode = imode; 5903 inner = gen_lowpart (imode, inner); 5904 } 5905 5906 /* Compute a mask of LEN bits, if we can do this on the host machine. */ 5907 if (len >= HOST_BITS_PER_WIDE_INT) 5908 break; 5909 5910 /* Now compute the equivalent expression. Make a copy of INNER 5911 for the SET_DEST in case it is a MEM into which we will substitute; 5912 we don't want shared RTL in that case. */ 5913 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1); 5914 cleared = simplify_gen_binary (AND, compute_mode, 5915 simplify_gen_unary (NOT, compute_mode, 5916 simplify_gen_binary (ASHIFT, 5917 compute_mode, 5918 mask, pos), 5919 compute_mode), 5920 inner); 5921 masked = simplify_gen_binary (ASHIFT, compute_mode, 5922 simplify_gen_binary ( 5923 AND, compute_mode, 5924 gen_lowpart (compute_mode, SET_SRC (x)), 5925 mask), 5926 pos); 5927 5928 x = gen_rtx_SET (VOIDmode, copy_rtx (inner), 5929 simplify_gen_binary (IOR, compute_mode, 5930 cleared, masked)); 5931 } 5932 5933 return x; 5934} 5935 5936/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, 5937 it is an RTX that represents a variable starting position; otherwise, 5938 POS is the (constant) starting bit position (counted from the LSB). 5939 5940 UNSIGNEDP is nonzero for an unsigned reference and zero for a 5941 signed reference. 5942 5943 IN_DEST is nonzero if this is a reference in the destination of a 5944 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero, 5945 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will 5946 be used. 5947 5948 IN_COMPARE is nonzero if we are in a COMPARE. This means that a 5949 ZERO_EXTRACT should be built even for bits starting at bit 0. 5950 5951 MODE is the desired mode of the result (if IN_DEST == 0). 5952 5953 The result is an RTX for the extraction or NULL_RTX if the target 5954 can't handle it. */ 5955 5956static rtx 5957make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos, 5958 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp, 5959 int in_dest, int in_compare) 5960{ 5961 /* This mode describes the size of the storage area 5962 to fetch the overall value from. Within that, we 5963 ignore the POS lowest bits, etc. */ 5964 enum machine_mode is_mode = GET_MODE (inner); 5965 enum machine_mode inner_mode; 5966 enum machine_mode wanted_inner_mode; 5967 enum machine_mode wanted_inner_reg_mode = word_mode; 5968 enum machine_mode pos_mode = word_mode; 5969 enum machine_mode extraction_mode = word_mode; 5970 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); 5971 rtx new = 0; 5972 rtx orig_pos_rtx = pos_rtx; 5973 HOST_WIDE_INT orig_pos; 5974 5975 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 5976 { 5977 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), 5978 consider just the QI as the memory to extract from. 5979 The subreg adds or removes high bits; its mode is 5980 irrelevant to the meaning of this extraction, 5981 since POS and LEN count from the lsb. */ 5982 if (MEM_P (SUBREG_REG (inner))) 5983 is_mode = GET_MODE (SUBREG_REG (inner)); 5984 inner = SUBREG_REG (inner); 5985 } 5986 else if (GET_CODE (inner) == ASHIFT 5987 && GET_CODE (XEXP (inner, 1)) == CONST_INT 5988 && pos_rtx == 0 && pos == 0 5989 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1))) 5990 { 5991 /* We're extracting the least significant bits of an rtx 5992 (ashift X (const_int C)), where LEN > C. Extract the 5993 least significant (LEN - C) bits of X, giving an rtx 5994 whose mode is MODE, then shift it left C times. */ 5995 new = make_extraction (mode, XEXP (inner, 0), 5996 0, 0, len - INTVAL (XEXP (inner, 1)), 5997 unsignedp, in_dest, in_compare); 5998 if (new != 0) 5999 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1)); 6000 } 6001 6002 inner_mode = GET_MODE (inner); 6003 6004 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT) 6005 pos = INTVAL (pos_rtx), pos_rtx = 0; 6006 6007 /* See if this can be done without an extraction. We never can if the 6008 width of the field is not the same as that of some integer mode. For 6009 registers, we can only avoid the extraction if the position is at the 6010 low-order bit and this is either not in the destination or we have the 6011 appropriate STRICT_LOW_PART operation available. 6012 6013 For MEM, we can avoid an extract if the field starts on an appropriate 6014 boundary and we can change the mode of the memory reference. */ 6015 6016 if (tmode != BLKmode 6017 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 6018 && !MEM_P (inner) 6019 && (inner_mode == tmode 6020 || !REG_P (inner) 6021 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode), 6022 GET_MODE_BITSIZE (inner_mode)) 6023 || reg_truncated_to_mode (tmode, inner)) 6024 && (! in_dest 6025 || (REG_P (inner) 6026 && have_insn_for (STRICT_LOW_PART, tmode)))) 6027 || (MEM_P (inner) && pos_rtx == 0 6028 && (pos 6029 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) 6030 : BITS_PER_UNIT)) == 0 6031 /* We can't do this if we are widening INNER_MODE (it 6032 may not be aligned, for one thing). */ 6033 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode) 6034 && (inner_mode == tmode 6035 || (! mode_dependent_address_p (XEXP (inner, 0)) 6036 && ! MEM_VOLATILE_P (inner)))))) 6037 { 6038 /* If INNER is a MEM, make a new MEM that encompasses just the desired 6039 field. If the original and current mode are the same, we need not 6040 adjust the offset. Otherwise, we do if bytes big endian. 6041 6042 If INNER is not a MEM, get a piece consisting of just the field 6043 of interest (in this case POS % BITS_PER_WORD must be 0). */ 6044 6045 if (MEM_P (inner)) 6046 { 6047 HOST_WIDE_INT offset; 6048 6049 /* POS counts from lsb, but make OFFSET count in memory order. */ 6050 if (BYTES_BIG_ENDIAN) 6051 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT; 6052 else 6053 offset = pos / BITS_PER_UNIT; 6054 6055 new = adjust_address_nv (inner, tmode, offset); 6056 } 6057 else if (REG_P (inner)) 6058 { 6059 if (tmode != inner_mode) 6060 { 6061 /* We can't call gen_lowpart in a DEST since we 6062 always want a SUBREG (see below) and it would sometimes 6063 return a new hard register. */ 6064 if (pos || in_dest) 6065 { 6066 HOST_WIDE_INT final_word = pos / BITS_PER_WORD; 6067 6068 if (WORDS_BIG_ENDIAN 6069 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD) 6070 final_word = ((GET_MODE_SIZE (inner_mode) 6071 - GET_MODE_SIZE (tmode)) 6072 / UNITS_PER_WORD) - final_word; 6073 6074 final_word *= UNITS_PER_WORD; 6075 if (BYTES_BIG_ENDIAN && 6076 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode)) 6077 final_word += (GET_MODE_SIZE (inner_mode) 6078 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD; 6079 6080 /* Avoid creating invalid subregs, for example when 6081 simplifying (x>>32)&255. */ 6082 if (!validate_subreg (tmode, inner_mode, inner, final_word)) 6083 return NULL_RTX; 6084 6085 new = gen_rtx_SUBREG (tmode, inner, final_word); 6086 } 6087 else 6088 new = gen_lowpart (tmode, inner); 6089 } 6090 else 6091 new = inner; 6092 } 6093 else 6094 new = force_to_mode (inner, tmode, 6095 len >= HOST_BITS_PER_WIDE_INT 6096 ? ~(unsigned HOST_WIDE_INT) 0 6097 : ((unsigned HOST_WIDE_INT) 1 << len) - 1, 6098 0); 6099 6100 /* If this extraction is going into the destination of a SET, 6101 make a STRICT_LOW_PART unless we made a MEM. */ 6102 6103 if (in_dest) 6104 return (MEM_P (new) ? new 6105 : (GET_CODE (new) != SUBREG 6106 ? gen_rtx_CLOBBER (tmode, const0_rtx) 6107 : gen_rtx_STRICT_LOW_PART (VOIDmode, new))); 6108 6109 if (mode == tmode) 6110 return new; 6111 6112 if (GET_CODE (new) == CONST_INT) 6113 return gen_int_mode (INTVAL (new), mode); 6114 6115 /* If we know that no extraneous bits are set, and that the high 6116 bit is not set, convert the extraction to the cheaper of 6117 sign and zero extension, that are equivalent in these cases. */ 6118 if (flag_expensive_optimizations 6119 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT 6120 && ((nonzero_bits (new, tmode) 6121 & ~(((unsigned HOST_WIDE_INT) 6122 GET_MODE_MASK (tmode)) 6123 >> 1)) 6124 == 0))) 6125 { 6126 rtx temp = gen_rtx_ZERO_EXTEND (mode, new); 6127 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new); 6128 6129 /* Prefer ZERO_EXTENSION, since it gives more information to 6130 backends. */ 6131 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET)) 6132 return temp; 6133 return temp1; 6134 } 6135 6136 /* Otherwise, sign- or zero-extend unless we already are in the 6137 proper mode. */ 6138 6139 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 6140 mode, new)); 6141 } 6142 6143 /* Unless this is a COMPARE or we have a funny memory reference, 6144 don't do anything with zero-extending field extracts starting at 6145 the low-order bit since they are simple AND operations. */ 6146 if (pos_rtx == 0 && pos == 0 && ! in_dest 6147 && ! in_compare && unsignedp) 6148 return 0; 6149 6150 /* Unless INNER is not MEM, reject this if we would be spanning bytes or 6151 if the position is not a constant and the length is not 1. In all 6152 other cases, we would only be going outside our object in cases when 6153 an original shift would have been undefined. */ 6154 if (MEM_P (inner) 6155 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode)) 6156 || (pos_rtx != 0 && len != 1))) 6157 return 0; 6158 6159 /* Get the mode to use should INNER not be a MEM, the mode for the position, 6160 and the mode for the result. */ 6161 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE) 6162 { 6163 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0); 6164 pos_mode = mode_for_extraction (EP_insv, 2); 6165 extraction_mode = mode_for_extraction (EP_insv, 3); 6166 } 6167 6168 if (! in_dest && unsignedp 6169 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE) 6170 { 6171 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1); 6172 pos_mode = mode_for_extraction (EP_extzv, 3); 6173 extraction_mode = mode_for_extraction (EP_extzv, 0); 6174 } 6175 6176 if (! in_dest && ! unsignedp 6177 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE) 6178 { 6179 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1); 6180 pos_mode = mode_for_extraction (EP_extv, 3); 6181 extraction_mode = mode_for_extraction (EP_extv, 0); 6182 } 6183 6184 /* Never narrow an object, since that might not be safe. */ 6185 6186 if (mode != VOIDmode 6187 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) 6188 extraction_mode = mode; 6189 6190 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode 6191 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) 6192 pos_mode = GET_MODE (pos_rtx); 6193 6194 /* If this is not from memory, the desired mode is the preferred mode 6195 for an extraction pattern's first input operand, or word_mode if there 6196 is none. */ 6197 if (!MEM_P (inner)) 6198 wanted_inner_mode = wanted_inner_reg_mode; 6199 else 6200 { 6201 /* Be careful not to go beyond the extracted object and maintain the 6202 natural alignment of the memory. */ 6203 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT); 6204 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len 6205 > GET_MODE_BITSIZE (wanted_inner_mode)) 6206 { 6207 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode); 6208 gcc_assert (wanted_inner_mode != VOIDmode); 6209 } 6210 6211 /* If we have to change the mode of memory and cannot, the desired mode 6212 is EXTRACTION_MODE. */ 6213 if (inner_mode != wanted_inner_mode 6214 && (mode_dependent_address_p (XEXP (inner, 0)) 6215 || MEM_VOLATILE_P (inner) 6216 || pos_rtx)) 6217 wanted_inner_mode = extraction_mode; 6218 } 6219 6220 orig_pos = pos; 6221 6222 if (BITS_BIG_ENDIAN) 6223 { 6224 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to 6225 BITS_BIG_ENDIAN style. If position is constant, compute new 6226 position. Otherwise, build subtraction. 6227 Note that POS is relative to the mode of the original argument. 6228 If it's a MEM we need to recompute POS relative to that. 6229 However, if we're extracting from (or inserting into) a register, 6230 we want to recompute POS relative to wanted_inner_mode. */ 6231 int width = (MEM_P (inner) 6232 ? GET_MODE_BITSIZE (is_mode) 6233 : GET_MODE_BITSIZE (wanted_inner_mode)); 6234 6235 if (pos_rtx == 0) 6236 pos = width - len - pos; 6237 else 6238 pos_rtx 6239 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx); 6240 /* POS may be less than 0 now, but we check for that below. 6241 Note that it can only be less than 0 if !MEM_P (inner). */ 6242 } 6243 6244 /* If INNER has a wider mode, and this is a constant extraction, try to 6245 make it smaller and adjust the byte to point to the byte containing 6246 the value. */ 6247 if (wanted_inner_mode != VOIDmode 6248 && inner_mode != wanted_inner_mode 6249 && ! pos_rtx 6250 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode) 6251 && MEM_P (inner) 6252 && ! mode_dependent_address_p (XEXP (inner, 0)) 6253 && ! MEM_VOLATILE_P (inner)) 6254 { 6255 int offset = 0; 6256 6257 /* The computations below will be correct if the machine is big 6258 endian in both bits and bytes or little endian in bits and bytes. 6259 If it is mixed, we must adjust. */ 6260 6261 /* If bytes are big endian and we had a paradoxical SUBREG, we must 6262 adjust OFFSET to compensate. */ 6263 if (BYTES_BIG_ENDIAN 6264 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) 6265 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); 6266 6267 /* We can now move to the desired byte. */ 6268 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode)) 6269 * GET_MODE_SIZE (wanted_inner_mode); 6270 pos %= GET_MODE_BITSIZE (wanted_inner_mode); 6271 6272 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN 6273 && is_mode != wanted_inner_mode) 6274 offset = (GET_MODE_SIZE (is_mode) 6275 - GET_MODE_SIZE (wanted_inner_mode) - offset); 6276 6277 inner = adjust_address_nv (inner, wanted_inner_mode, offset); 6278 } 6279 6280 /* If INNER is not memory, we can always get it into the proper mode. If we 6281 are changing its mode, POS must be a constant and smaller than the size 6282 of the new mode. */ 6283 else if (!MEM_P (inner)) 6284 { 6285 if (GET_MODE (inner) != wanted_inner_mode 6286 && (pos_rtx != 0 6287 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) 6288 return 0; 6289 6290 if (orig_pos < 0) 6291 return 0; 6292 6293 inner = force_to_mode (inner, wanted_inner_mode, 6294 pos_rtx 6295 || len + orig_pos >= HOST_BITS_PER_WIDE_INT 6296 ? ~(unsigned HOST_WIDE_INT) 0 6297 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1) 6298 << orig_pos), 6299 0); 6300 } 6301 6302 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we 6303 have to zero extend. Otherwise, we can just use a SUBREG. */ 6304 if (pos_rtx != 0 6305 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) 6306 { 6307 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx); 6308 6309 /* If we know that no extraneous bits are set, and that the high 6310 bit is not set, convert extraction to cheaper one - either 6311 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these 6312 cases. */ 6313 if (flag_expensive_optimizations 6314 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT 6315 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx)) 6316 & ~(((unsigned HOST_WIDE_INT) 6317 GET_MODE_MASK (GET_MODE (pos_rtx))) 6318 >> 1)) 6319 == 0))) 6320 { 6321 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx); 6322 6323 /* Prefer ZERO_EXTENSION, since it gives more information to 6324 backends. */ 6325 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET)) 6326 temp = temp1; 6327 } 6328 pos_rtx = temp; 6329 } 6330 else if (pos_rtx != 0 6331 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) 6332 pos_rtx = gen_lowpart (pos_mode, pos_rtx); 6333 6334 /* Make POS_RTX unless we already have it and it is correct. If we don't 6335 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must 6336 be a CONST_INT. */ 6337 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) 6338 pos_rtx = orig_pos_rtx; 6339 6340 else if (pos_rtx == 0) 6341 pos_rtx = GEN_INT (pos); 6342 6343 /* Make the required operation. See if we can use existing rtx. */ 6344 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, 6345 extraction_mode, inner, GEN_INT (len), pos_rtx); 6346 if (! in_dest) 6347 new = gen_lowpart (mode, new); 6348 6349 return new; 6350} 6351 6352/* See if X contains an ASHIFT of COUNT or more bits that can be commuted 6353 with any other operations in X. Return X without that shift if so. */ 6354 6355static rtx 6356extract_left_shift (rtx x, int count) 6357{ 6358 enum rtx_code code = GET_CODE (x); 6359 enum machine_mode mode = GET_MODE (x); 6360 rtx tem; 6361 6362 switch (code) 6363 { 6364 case ASHIFT: 6365 /* This is the shift itself. If it is wide enough, we will return 6366 either the value being shifted if the shift count is equal to 6367 COUNT or a shift for the difference. */ 6368 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6369 && INTVAL (XEXP (x, 1)) >= count) 6370 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), 6371 INTVAL (XEXP (x, 1)) - count); 6372 break; 6373 6374 case NEG: case NOT: 6375 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) 6376 return simplify_gen_unary (code, mode, tem, mode); 6377 6378 break; 6379 6380 case PLUS: case IOR: case XOR: case AND: 6381 /* If we can safely shift this constant and we find the inner shift, 6382 make a new operation. */ 6383 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6384 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0 6385 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) 6386 return simplify_gen_binary (code, mode, tem, 6387 GEN_INT (INTVAL (XEXP (x, 1)) >> count)); 6388 6389 break; 6390 6391 default: 6392 break; 6393 } 6394 6395 return 0; 6396} 6397 6398/* Look at the expression rooted at X. Look for expressions 6399 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. 6400 Form these expressions. 6401 6402 Return the new rtx, usually just X. 6403 6404 Also, for machines like the VAX that don't have logical shift insns, 6405 try to convert logical to arithmetic shift operations in cases where 6406 they are equivalent. This undoes the canonicalizations to logical 6407 shifts done elsewhere. 6408 6409 We try, as much as possible, to re-use rtl expressions to save memory. 6410 6411 IN_CODE says what kind of expression we are processing. Normally, it is 6412 SET. In a memory address (inside a MEM, PLUS or minus, the latter two 6413 being kludges), it is MEM. When processing the arguments of a comparison 6414 or a COMPARE against zero, it is COMPARE. */ 6415 6416static rtx 6417make_compound_operation (rtx x, enum rtx_code in_code) 6418{ 6419 enum rtx_code code = GET_CODE (x); 6420 enum machine_mode mode = GET_MODE (x); 6421 int mode_width = GET_MODE_BITSIZE (mode); 6422 rtx rhs, lhs; 6423 enum rtx_code next_code; 6424 int i; 6425 rtx new = 0; 6426 rtx tem; 6427 const char *fmt; 6428 6429 /* Select the code to be used in recursive calls. Once we are inside an 6430 address, we stay there. If we have a comparison, set to COMPARE, 6431 but once inside, go back to our default of SET. */ 6432 6433 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM 6434 : ((code == COMPARE || COMPARISON_P (x)) 6435 && XEXP (x, 1) == const0_rtx) ? COMPARE 6436 : in_code == COMPARE ? SET : in_code); 6437 6438 /* Process depending on the code of this operation. If NEW is set 6439 nonzero, it will be returned. */ 6440 6441 switch (code) 6442 { 6443 case ASHIFT: 6444 /* Convert shifts by constants into multiplications if inside 6445 an address. */ 6446 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT 6447 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 6448 && INTVAL (XEXP (x, 1)) >= 0) 6449 { 6450 new = make_compound_operation (XEXP (x, 0), next_code); 6451 new = gen_rtx_MULT (mode, new, 6452 GEN_INT ((HOST_WIDE_INT) 1 6453 << INTVAL (XEXP (x, 1)))); 6454 } 6455 break; 6456 6457 case AND: 6458 /* If the second operand is not a constant, we can't do anything 6459 with it. */ 6460 if (GET_CODE (XEXP (x, 1)) != CONST_INT) 6461 break; 6462 6463 /* If the constant is a power of two minus one and the first operand 6464 is a logical right shift, make an extraction. */ 6465 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6466 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6467 { 6468 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 6469 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1, 6470 0, in_code == COMPARE); 6471 } 6472 6473 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ 6474 else if (GET_CODE (XEXP (x, 0)) == SUBREG 6475 && subreg_lowpart_p (XEXP (x, 0)) 6476 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT 6477 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6478 { 6479 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), 6480 next_code); 6481 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0, 6482 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, 6483 0, in_code == COMPARE); 6484 } 6485 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ 6486 else if ((GET_CODE (XEXP (x, 0)) == XOR 6487 || GET_CODE (XEXP (x, 0)) == IOR) 6488 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT 6489 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT 6490 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6491 { 6492 /* Apply the distributive law, and then try to make extractions. */ 6493 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode, 6494 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), 6495 XEXP (x, 1)), 6496 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), 6497 XEXP (x, 1))); 6498 new = make_compound_operation (new, in_code); 6499 } 6500 6501 /* If we are have (and (rotate X C) M) and C is larger than the number 6502 of bits in M, this is an extraction. */ 6503 6504 else if (GET_CODE (XEXP (x, 0)) == ROTATE 6505 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6506 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 6507 && i <= INTVAL (XEXP (XEXP (x, 0), 1))) 6508 { 6509 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 6510 new = make_extraction (mode, new, 6511 (GET_MODE_BITSIZE (mode) 6512 - INTVAL (XEXP (XEXP (x, 0), 1))), 6513 NULL_RTX, i, 1, 0, in_code == COMPARE); 6514 } 6515 6516 /* On machines without logical shifts, if the operand of the AND is 6517 a logical shift and our mask turns off all the propagated sign 6518 bits, we can replace the logical shift with an arithmetic shift. */ 6519 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6520 && !have_insn_for (LSHIFTRT, mode) 6521 && have_insn_for (ASHIFTRT, mode) 6522 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6523 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 6524 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 6525 && mode_width <= HOST_BITS_PER_WIDE_INT) 6526 { 6527 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 6528 6529 mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); 6530 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) 6531 SUBST (XEXP (x, 0), 6532 gen_rtx_ASHIFTRT (mode, 6533 make_compound_operation 6534 (XEXP (XEXP (x, 0), 0), next_code), 6535 XEXP (XEXP (x, 0), 1))); 6536 } 6537 6538 /* If the constant is one less than a power of two, this might be 6539 representable by an extraction even if no shift is present. 6540 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless 6541 we are in a COMPARE. */ 6542 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6543 new = make_extraction (mode, 6544 make_compound_operation (XEXP (x, 0), 6545 next_code), 6546 0, NULL_RTX, i, 1, 0, in_code == COMPARE); 6547 6548 /* If we are in a comparison and this is an AND with a power of two, 6549 convert this into the appropriate bit extract. */ 6550 else if (in_code == COMPARE 6551 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) 6552 new = make_extraction (mode, 6553 make_compound_operation (XEXP (x, 0), 6554 next_code), 6555 i, NULL_RTX, 1, 1, 0, 1); 6556 6557 break; 6558 6559 case LSHIFTRT: 6560 /* If the sign bit is known to be zero, replace this with an 6561 arithmetic shift. */ 6562 if (have_insn_for (ASHIFTRT, mode) 6563 && ! have_insn_for (LSHIFTRT, mode) 6564 && mode_width <= HOST_BITS_PER_WIDE_INT 6565 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) 6566 { 6567 new = gen_rtx_ASHIFTRT (mode, 6568 make_compound_operation (XEXP (x, 0), 6569 next_code), 6570 XEXP (x, 1)); 6571 break; 6572 } 6573 6574 /* ... fall through ... */ 6575 6576 case ASHIFTRT: 6577 lhs = XEXP (x, 0); 6578 rhs = XEXP (x, 1); 6579 6580 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, 6581 this is a SIGN_EXTRACT. */ 6582 if (GET_CODE (rhs) == CONST_INT 6583 && GET_CODE (lhs) == ASHIFT 6584 && GET_CODE (XEXP (lhs, 1)) == CONST_INT 6585 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))) 6586 { 6587 new = make_compound_operation (XEXP (lhs, 0), next_code); 6588 new = make_extraction (mode, new, 6589 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), 6590 NULL_RTX, mode_width - INTVAL (rhs), 6591 code == LSHIFTRT, 0, in_code == COMPARE); 6592 break; 6593 } 6594 6595 /* See if we have operations between an ASHIFTRT and an ASHIFT. 6596 If so, try to merge the shifts into a SIGN_EXTEND. We could 6597 also do this for some cases of SIGN_EXTRACT, but it doesn't 6598 seem worth the effort; the case checked for occurs on Alpha. */ 6599 6600 if (!OBJECT_P (lhs) 6601 && ! (GET_CODE (lhs) == SUBREG 6602 && (OBJECT_P (SUBREG_REG (lhs)))) 6603 && GET_CODE (rhs) == CONST_INT 6604 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT 6605 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0) 6606 new = make_extraction (mode, make_compound_operation (new, next_code), 6607 0, NULL_RTX, mode_width - INTVAL (rhs), 6608 code == LSHIFTRT, 0, in_code == COMPARE); 6609 6610 break; 6611 6612 case SUBREG: 6613 /* Call ourselves recursively on the inner expression. If we are 6614 narrowing the object and it has a different RTL code from 6615 what it originally did, do this SUBREG as a force_to_mode. */ 6616 6617 tem = make_compound_operation (SUBREG_REG (x), in_code); 6618 6619 { 6620 rtx simplified; 6621 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem), 6622 SUBREG_BYTE (x)); 6623 6624 if (simplified) 6625 tem = simplified; 6626 6627 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x)) 6628 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem)) 6629 && subreg_lowpart_p (x)) 6630 { 6631 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0, 6632 0); 6633 6634 /* If we have something other than a SUBREG, we might have 6635 done an expansion, so rerun ourselves. */ 6636 if (GET_CODE (newer) != SUBREG) 6637 newer = make_compound_operation (newer, in_code); 6638 6639 return newer; 6640 } 6641 6642 if (simplified) 6643 return tem; 6644 } 6645 break; 6646 6647 default: 6648 break; 6649 } 6650 6651 if (new) 6652 { 6653 x = gen_lowpart (mode, new); 6654 code = GET_CODE (x); 6655 } 6656 6657 /* Now recursively process each operand of this operation. */ 6658 fmt = GET_RTX_FORMAT (code); 6659 for (i = 0; i < GET_RTX_LENGTH (code); i++) 6660 if (fmt[i] == 'e') 6661 { 6662 new = make_compound_operation (XEXP (x, i), next_code); 6663 SUBST (XEXP (x, i), new); 6664 } 6665 6666 /* If this is a commutative operation, the changes to the operands 6667 may have made it noncanonical. */ 6668 if (COMMUTATIVE_ARITH_P (x) 6669 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 6670 { 6671 tem = XEXP (x, 0); 6672 SUBST (XEXP (x, 0), XEXP (x, 1)); 6673 SUBST (XEXP (x, 1), tem); 6674 } 6675 6676 return x; 6677} 6678 6679/* Given M see if it is a value that would select a field of bits 6680 within an item, but not the entire word. Return -1 if not. 6681 Otherwise, return the starting position of the field, where 0 is the 6682 low-order bit. 6683 6684 *PLEN is set to the length of the field. */ 6685 6686static int 6687get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen) 6688{ 6689 /* Get the bit number of the first 1 bit from the right, -1 if none. */ 6690 int pos = exact_log2 (m & -m); 6691 int len = 0; 6692 6693 if (pos >= 0) 6694 /* Now shift off the low-order zero bits and see if we have a 6695 power of two minus 1. */ 6696 len = exact_log2 ((m >> pos) + 1); 6697 6698 if (len <= 0) 6699 pos = -1; 6700 6701 *plen = len; 6702 return pos; 6703} 6704 6705/* If X refers to a register that equals REG in value, replace these 6706 references with REG. */ 6707static rtx 6708canon_reg_for_combine (rtx x, rtx reg) 6709{ 6710 rtx op0, op1, op2; 6711 const char *fmt; 6712 int i; 6713 bool copied; 6714 6715 enum rtx_code code = GET_CODE (x); 6716 switch (GET_RTX_CLASS (code)) 6717 { 6718 case RTX_UNARY: 6719 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 6720 if (op0 != XEXP (x, 0)) 6721 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0, 6722 GET_MODE (reg)); 6723 break; 6724 6725 case RTX_BIN_ARITH: 6726 case RTX_COMM_ARITH: 6727 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 6728 op1 = canon_reg_for_combine (XEXP (x, 1), reg); 6729 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 6730 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1); 6731 break; 6732 6733 case RTX_COMPARE: 6734 case RTX_COMM_COMPARE: 6735 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 6736 op1 = canon_reg_for_combine (XEXP (x, 1), reg); 6737 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 6738 return simplify_gen_relational (GET_CODE (x), GET_MODE (x), 6739 GET_MODE (op0), op0, op1); 6740 break; 6741 6742 case RTX_TERNARY: 6743 case RTX_BITFIELD_OPS: 6744 op0 = canon_reg_for_combine (XEXP (x, 0), reg); 6745 op1 = canon_reg_for_combine (XEXP (x, 1), reg); 6746 op2 = canon_reg_for_combine (XEXP (x, 2), reg); 6747 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2)) 6748 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x), 6749 GET_MODE (op0), op0, op1, op2); 6750 6751 case RTX_OBJ: 6752 if (REG_P (x)) 6753 { 6754 if (rtx_equal_p (get_last_value (reg), x) 6755 || rtx_equal_p (reg, get_last_value (x))) 6756 return reg; 6757 else 6758 break; 6759 } 6760 6761 /* fall through */ 6762 6763 default: 6764 fmt = GET_RTX_FORMAT (code); 6765 copied = false; 6766 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 6767 if (fmt[i] == 'e') 6768 { 6769 rtx op = canon_reg_for_combine (XEXP (x, i), reg); 6770 if (op != XEXP (x, i)) 6771 { 6772 if (!copied) 6773 { 6774 copied = true; 6775 x = copy_rtx (x); 6776 } 6777 XEXP (x, i) = op; 6778 } 6779 } 6780 else if (fmt[i] == 'E') 6781 { 6782 int j; 6783 for (j = 0; j < XVECLEN (x, i); j++) 6784 { 6785 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg); 6786 if (op != XVECEXP (x, i, j)) 6787 { 6788 if (!copied) 6789 { 6790 copied = true; 6791 x = copy_rtx (x); 6792 } 6793 XVECEXP (x, i, j) = op; 6794 } 6795 } 6796 } 6797 6798 break; 6799 } 6800 6801 return x; 6802} 6803 6804/* Return X converted to MODE. If the value is already truncated to 6805 MODE we can just return a subreg even though in the general case we 6806 would need an explicit truncation. */ 6807 6808static rtx 6809gen_lowpart_or_truncate (enum machine_mode mode, rtx x) 6810{ 6811 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode) 6812 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 6813 GET_MODE_BITSIZE (GET_MODE (x))) 6814 || (REG_P (x) && reg_truncated_to_mode (mode, x))) 6815 return gen_lowpart (mode, x); 6816 else 6817 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x)); 6818} 6819 6820/* See if X can be simplified knowing that we will only refer to it in 6821 MODE and will only refer to those bits that are nonzero in MASK. 6822 If other bits are being computed or if masking operations are done 6823 that select a superset of the bits in MASK, they can sometimes be 6824 ignored. 6825 6826 Return a possibly simplified expression, but always convert X to 6827 MODE. If X is a CONST_INT, AND the CONST_INT with MASK. 6828 6829 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK 6830 are all off in X. This is used when X will be complemented, by either 6831 NOT, NEG, or XOR. */ 6832 6833static rtx 6834force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask, 6835 int just_select) 6836{ 6837 enum rtx_code code = GET_CODE (x); 6838 int next_select = just_select || code == XOR || code == NOT || code == NEG; 6839 enum machine_mode op_mode; 6840 unsigned HOST_WIDE_INT fuller_mask, nonzero; 6841 rtx op0, op1, temp; 6842 6843 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the 6844 code below will do the wrong thing since the mode of such an 6845 expression is VOIDmode. 6846 6847 Also do nothing if X is a CLOBBER; this can happen if X was 6848 the return value from a call to gen_lowpart. */ 6849 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) 6850 return x; 6851 6852 /* We want to perform the operation is its present mode unless we know 6853 that the operation is valid in MODE, in which case we do the operation 6854 in MODE. */ 6855 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) 6856 && have_insn_for (code, mode)) 6857 ? mode : GET_MODE (x)); 6858 6859 /* It is not valid to do a right-shift in a narrower mode 6860 than the one it came in with. */ 6861 if ((code == LSHIFTRT || code == ASHIFTRT) 6862 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x))) 6863 op_mode = GET_MODE (x); 6864 6865 /* Truncate MASK to fit OP_MODE. */ 6866 if (op_mode) 6867 mask &= GET_MODE_MASK (op_mode); 6868 6869 /* When we have an arithmetic operation, or a shift whose count we 6870 do not know, we need to assume that all bits up to the highest-order 6871 bit in MASK will be needed. This is how we form such a mask. */ 6872 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) 6873 fuller_mask = ~(unsigned HOST_WIDE_INT) 0; 6874 else 6875 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) 6876 - 1); 6877 6878 /* Determine what bits of X are guaranteed to be (non)zero. */ 6879 nonzero = nonzero_bits (x, mode); 6880 6881 /* If none of the bits in X are needed, return a zero. */ 6882 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x)) 6883 x = const0_rtx; 6884 6885 /* If X is a CONST_INT, return a new one. Do this here since the 6886 test below will fail. */ 6887 if (GET_CODE (x) == CONST_INT) 6888 { 6889 if (SCALAR_INT_MODE_P (mode)) 6890 return gen_int_mode (INTVAL (x) & mask, mode); 6891 else 6892 { 6893 x = GEN_INT (INTVAL (x) & mask); 6894 return gen_lowpart_common (mode, x); 6895 } 6896 } 6897 6898 /* If X is narrower than MODE and we want all the bits in X's mode, just 6899 get X in the proper mode. */ 6900 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) 6901 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0) 6902 return gen_lowpart (mode, x); 6903 6904 switch (code) 6905 { 6906 case CLOBBER: 6907 /* If X is a (clobber (const_int)), return it since we know we are 6908 generating something that won't match. */ 6909 return x; 6910 6911 case SIGN_EXTEND: 6912 case ZERO_EXTEND: 6913 case ZERO_EXTRACT: 6914 case SIGN_EXTRACT: 6915 x = expand_compound_operation (x); 6916 if (GET_CODE (x) != code) 6917 return force_to_mode (x, mode, mask, next_select); 6918 break; 6919 6920 case SUBREG: 6921 if (subreg_lowpart_p (x) 6922 /* We can ignore the effect of this SUBREG if it narrows the mode or 6923 if the constant masks to zero all the bits the mode doesn't 6924 have. */ 6925 && ((GET_MODE_SIZE (GET_MODE (x)) 6926 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 6927 || (0 == (mask 6928 & GET_MODE_MASK (GET_MODE (x)) 6929 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) 6930 return force_to_mode (SUBREG_REG (x), mode, mask, next_select); 6931 break; 6932 6933 case AND: 6934 /* If this is an AND with a constant, convert it into an AND 6935 whose constant is the AND of that constant with MASK. If it 6936 remains an AND of MASK, delete it since it is redundant. */ 6937 6938 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 6939 { 6940 x = simplify_and_const_int (x, op_mode, XEXP (x, 0), 6941 mask & INTVAL (XEXP (x, 1))); 6942 6943 /* If X is still an AND, see if it is an AND with a mask that 6944 is just some low-order bits. If so, and it is MASK, we don't 6945 need it. */ 6946 6947 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT 6948 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x))) 6949 == mask)) 6950 x = XEXP (x, 0); 6951 6952 /* If it remains an AND, try making another AND with the bits 6953 in the mode mask that aren't in MASK turned on. If the 6954 constant in the AND is wide enough, this might make a 6955 cheaper constant. */ 6956 6957 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT 6958 && GET_MODE_MASK (GET_MODE (x)) != mask 6959 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) 6960 { 6961 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1)) 6962 | (GET_MODE_MASK (GET_MODE (x)) & ~mask)); 6963 int width = GET_MODE_BITSIZE (GET_MODE (x)); 6964 rtx y; 6965 6966 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative 6967 number, sign extend it. */ 6968 if (width > 0 && width < HOST_BITS_PER_WIDE_INT 6969 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6970 cval |= (HOST_WIDE_INT) -1 << width; 6971 6972 y = simplify_gen_binary (AND, GET_MODE (x), 6973 XEXP (x, 0), GEN_INT (cval)); 6974 if (rtx_cost (y, SET) < rtx_cost (x, SET)) 6975 x = y; 6976 } 6977 6978 break; 6979 } 6980 6981 goto binop; 6982 6983 case PLUS: 6984 /* In (and (plus FOO C1) M), if M is a mask that just turns off 6985 low-order bits (as in an alignment operation) and FOO is already 6986 aligned to that boundary, mask C1 to that boundary as well. 6987 This may eliminate that PLUS and, later, the AND. */ 6988 6989 { 6990 unsigned int width = GET_MODE_BITSIZE (mode); 6991 unsigned HOST_WIDE_INT smask = mask; 6992 6993 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative 6994 number, sign extend it. */ 6995 6996 if (width < HOST_BITS_PER_WIDE_INT 6997 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6998 smask |= (HOST_WIDE_INT) -1 << width; 6999 7000 if (GET_CODE (XEXP (x, 1)) == CONST_INT 7001 && exact_log2 (- smask) >= 0 7002 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0 7003 && (INTVAL (XEXP (x, 1)) & ~smask) != 0) 7004 return force_to_mode (plus_constant (XEXP (x, 0), 7005 (INTVAL (XEXP (x, 1)) & smask)), 7006 mode, smask, next_select); 7007 } 7008 7009 /* ... fall through ... */ 7010 7011 case MULT: 7012 /* For PLUS, MINUS and MULT, we need any bits less significant than the 7013 most significant bit in MASK since carries from those bits will 7014 affect the bits we are interested in. */ 7015 mask = fuller_mask; 7016 goto binop; 7017 7018 case MINUS: 7019 /* If X is (minus C Y) where C's least set bit is larger than any bit 7020 in the mask, then we may replace with (neg Y). */ 7021 if (GET_CODE (XEXP (x, 0)) == CONST_INT 7022 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0)) 7023 & -INTVAL (XEXP (x, 0)))) 7024 > mask)) 7025 { 7026 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1), 7027 GET_MODE (x)); 7028 return force_to_mode (x, mode, mask, next_select); 7029 } 7030 7031 /* Similarly, if C contains every bit in the fuller_mask, then we may 7032 replace with (not Y). */ 7033 if (GET_CODE (XEXP (x, 0)) == CONST_INT 7034 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask) 7035 == INTVAL (XEXP (x, 0)))) 7036 { 7037 x = simplify_gen_unary (NOT, GET_MODE (x), 7038 XEXP (x, 1), GET_MODE (x)); 7039 return force_to_mode (x, mode, mask, next_select); 7040 } 7041 7042 mask = fuller_mask; 7043 goto binop; 7044 7045 case IOR: 7046 case XOR: 7047 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and 7048 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) 7049 operation which may be a bitfield extraction. Ensure that the 7050 constant we form is not wider than the mode of X. */ 7051 7052 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 7053 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 7054 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 7055 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 7056 && GET_CODE (XEXP (x, 1)) == CONST_INT 7057 && ((INTVAL (XEXP (XEXP (x, 0), 1)) 7058 + floor_log2 (INTVAL (XEXP (x, 1)))) 7059 < GET_MODE_BITSIZE (GET_MODE (x))) 7060 && (INTVAL (XEXP (x, 1)) 7061 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0) 7062 { 7063 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask) 7064 << INTVAL (XEXP (XEXP (x, 0), 1))); 7065 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x), 7066 XEXP (XEXP (x, 0), 0), temp); 7067 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp, 7068 XEXP (XEXP (x, 0), 1)); 7069 return force_to_mode (x, mode, mask, next_select); 7070 } 7071 7072 binop: 7073 /* For most binary operations, just propagate into the operation and 7074 change the mode if we have an operation of that mode. */ 7075 7076 op0 = gen_lowpart_or_truncate (op_mode, 7077 force_to_mode (XEXP (x, 0), mode, mask, 7078 next_select)); 7079 op1 = gen_lowpart_or_truncate (op_mode, 7080 force_to_mode (XEXP (x, 1), mode, mask, 7081 next_select)); 7082 7083 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 7084 x = simplify_gen_binary (code, op_mode, op0, op1); 7085 break; 7086 7087 case ASHIFT: 7088 /* For left shifts, do the same, but just for the first operand. 7089 However, we cannot do anything with shifts where we cannot 7090 guarantee that the counts are smaller than the size of the mode 7091 because such a count will have a different meaning in a 7092 wider mode. */ 7093 7094 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT 7095 && INTVAL (XEXP (x, 1)) >= 0 7096 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode)) 7097 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode 7098 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) 7099 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))) 7100 break; 7101 7102 /* If the shift count is a constant and we can do arithmetic in 7103 the mode of the shift, refine which bits we need. Otherwise, use the 7104 conservative form of the mask. */ 7105 if (GET_CODE (XEXP (x, 1)) == CONST_INT 7106 && INTVAL (XEXP (x, 1)) >= 0 7107 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode) 7108 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) 7109 mask >>= INTVAL (XEXP (x, 1)); 7110 else 7111 mask = fuller_mask; 7112 7113 op0 = gen_lowpart_or_truncate (op_mode, 7114 force_to_mode (XEXP (x, 0), op_mode, 7115 mask, next_select)); 7116 7117 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 7118 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1)); 7119 break; 7120 7121 case LSHIFTRT: 7122 /* Here we can only do something if the shift count is a constant, 7123 this shift constant is valid for the host, and we can do arithmetic 7124 in OP_MODE. */ 7125 7126 if (GET_CODE (XEXP (x, 1)) == CONST_INT 7127 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 7128 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) 7129 { 7130 rtx inner = XEXP (x, 0); 7131 unsigned HOST_WIDE_INT inner_mask; 7132 7133 /* Select the mask of the bits we need for the shift operand. */ 7134 inner_mask = mask << INTVAL (XEXP (x, 1)); 7135 7136 /* We can only change the mode of the shift if we can do arithmetic 7137 in the mode of the shift and INNER_MASK is no wider than the 7138 width of X's mode. */ 7139 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0) 7140 op_mode = GET_MODE (x); 7141 7142 inner = force_to_mode (inner, op_mode, inner_mask, next_select); 7143 7144 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) 7145 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); 7146 } 7147 7148 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the 7149 shift and AND produces only copies of the sign bit (C2 is one less 7150 than a power of two), we can do this with just a shift. */ 7151 7152 if (GET_CODE (x) == LSHIFTRT 7153 && GET_CODE (XEXP (x, 1)) == CONST_INT 7154 /* The shift puts one of the sign bit copies in the least significant 7155 bit. */ 7156 && ((INTVAL (XEXP (x, 1)) 7157 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) 7158 >= GET_MODE_BITSIZE (GET_MODE (x))) 7159 && exact_log2 (mask + 1) >= 0 7160 /* Number of bits left after the shift must be more than the mask 7161 needs. */ 7162 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1)) 7163 <= GET_MODE_BITSIZE (GET_MODE (x))) 7164 /* Must be more sign bit copies than the mask needs. */ 7165 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 7166 >= exact_log2 (mask + 1))) 7167 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), 7168 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x)) 7169 - exact_log2 (mask + 1))); 7170 7171 goto shiftrt; 7172 7173 case ASHIFTRT: 7174 /* If we are just looking for the sign bit, we don't need this shift at 7175 all, even if it has a variable count. */ 7176 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 7177 && (mask == ((unsigned HOST_WIDE_INT) 1 7178 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 7179 return force_to_mode (XEXP (x, 0), mode, mask, next_select); 7180 7181 /* If this is a shift by a constant, get a mask that contains those bits 7182 that are not copies of the sign bit. We then have two cases: If 7183 MASK only includes those bits, this can be a logical shift, which may 7184 allow simplifications. If MASK is a single-bit field not within 7185 those bits, we are requesting a copy of the sign bit and hence can 7186 shift the sign bit to the appropriate location. */ 7187 7188 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0 7189 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 7190 { 7191 int i; 7192 7193 /* If the considered data is wider than HOST_WIDE_INT, we can't 7194 represent a mask for all its bits in a single scalar. 7195 But we only care about the lower bits, so calculate these. */ 7196 7197 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT) 7198 { 7199 nonzero = ~(HOST_WIDE_INT) 0; 7200 7201 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 7202 is the number of bits a full-width mask would have set. 7203 We need only shift if these are fewer than nonzero can 7204 hold. If not, we must keep all bits set in nonzero. */ 7205 7206 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 7207 < HOST_BITS_PER_WIDE_INT) 7208 nonzero >>= INTVAL (XEXP (x, 1)) 7209 + HOST_BITS_PER_WIDE_INT 7210 - GET_MODE_BITSIZE (GET_MODE (x)) ; 7211 } 7212 else 7213 { 7214 nonzero = GET_MODE_MASK (GET_MODE (x)); 7215 nonzero >>= INTVAL (XEXP (x, 1)); 7216 } 7217 7218 if ((mask & ~nonzero) == 0) 7219 { 7220 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x), 7221 XEXP (x, 0), INTVAL (XEXP (x, 1))); 7222 if (GET_CODE (x) != ASHIFTRT) 7223 return force_to_mode (x, mode, mask, next_select); 7224 } 7225 7226 else if ((i = exact_log2 (mask)) >= 0) 7227 { 7228 x = simplify_shift_const 7229 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0), 7230 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i); 7231 7232 if (GET_CODE (x) != ASHIFTRT) 7233 return force_to_mode (x, mode, mask, next_select); 7234 } 7235 } 7236 7237 /* If MASK is 1, convert this to an LSHIFTRT. This can be done 7238 even if the shift count isn't a constant. */ 7239 if (mask == 1) 7240 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), 7241 XEXP (x, 0), XEXP (x, 1)); 7242 7243 shiftrt: 7244 7245 /* If this is a zero- or sign-extension operation that just affects bits 7246 we don't care about, remove it. Be sure the call above returned 7247 something that is still a shift. */ 7248 7249 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) 7250 && GET_CODE (XEXP (x, 1)) == CONST_INT 7251 && INTVAL (XEXP (x, 1)) >= 0 7252 && (INTVAL (XEXP (x, 1)) 7253 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1)) 7254 && GET_CODE (XEXP (x, 0)) == ASHIFT 7255 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1)) 7256 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, 7257 next_select); 7258 7259 break; 7260 7261 case ROTATE: 7262 case ROTATERT: 7263 /* If the shift count is constant and we can do computations 7264 in the mode of X, compute where the bits we care about are. 7265 Otherwise, we can't do anything. Don't change the mode of 7266 the shift or propagate MODE into the shift, though. */ 7267 if (GET_CODE (XEXP (x, 1)) == CONST_INT 7268 && INTVAL (XEXP (x, 1)) >= 0) 7269 { 7270 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, 7271 GET_MODE (x), GEN_INT (mask), 7272 XEXP (x, 1)); 7273 if (temp && GET_CODE (temp) == CONST_INT) 7274 SUBST (XEXP (x, 0), 7275 force_to_mode (XEXP (x, 0), GET_MODE (x), 7276 INTVAL (temp), next_select)); 7277 } 7278 break; 7279 7280 case NEG: 7281 /* If we just want the low-order bit, the NEG isn't needed since it 7282 won't change the low-order bit. */ 7283 if (mask == 1) 7284 return force_to_mode (XEXP (x, 0), mode, mask, just_select); 7285 7286 /* We need any bits less significant than the most significant bit in 7287 MASK since carries from those bits will affect the bits we are 7288 interested in. */ 7289 mask = fuller_mask; 7290 goto unop; 7291 7292 case NOT: 7293 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the 7294 same as the XOR case above. Ensure that the constant we form is not 7295 wider than the mode of X. */ 7296 7297 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 7298 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 7299 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 7300 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) 7301 < GET_MODE_BITSIZE (GET_MODE (x))) 7302 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) 7303 { 7304 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), 7305 GET_MODE (x)); 7306 temp = simplify_gen_binary (XOR, GET_MODE (x), 7307 XEXP (XEXP (x, 0), 0), temp); 7308 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), 7309 temp, XEXP (XEXP (x, 0), 1)); 7310 7311 return force_to_mode (x, mode, mask, next_select); 7312 } 7313 7314 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must 7315 use the full mask inside the NOT. */ 7316 mask = fuller_mask; 7317 7318 unop: 7319 op0 = gen_lowpart_or_truncate (op_mode, 7320 force_to_mode (XEXP (x, 0), mode, mask, 7321 next_select)); 7322 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 7323 x = simplify_gen_unary (code, op_mode, op0, op_mode); 7324 break; 7325 7326 case NE: 7327 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included 7328 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, 7329 which is equal to STORE_FLAG_VALUE. */ 7330 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx 7331 && GET_MODE (XEXP (x, 0)) == mode 7332 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0 7333 && (nonzero_bits (XEXP (x, 0), mode) 7334 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE)) 7335 return force_to_mode (XEXP (x, 0), mode, mask, next_select); 7336 7337 break; 7338 7339 case IF_THEN_ELSE: 7340 /* We have no way of knowing if the IF_THEN_ELSE can itself be 7341 written in a narrower mode. We play it safe and do not do so. */ 7342 7343 SUBST (XEXP (x, 1), 7344 gen_lowpart_or_truncate (GET_MODE (x), 7345 force_to_mode (XEXP (x, 1), mode, 7346 mask, next_select))); 7347 SUBST (XEXP (x, 2), 7348 gen_lowpart_or_truncate (GET_MODE (x), 7349 force_to_mode (XEXP (x, 2), mode, 7350 mask, next_select))); 7351 break; 7352 7353 default: 7354 break; 7355 } 7356 7357 /* Ensure we return a value of the proper mode. */ 7358 return gen_lowpart_or_truncate (mode, x); 7359} 7360 7361/* Return nonzero if X is an expression that has one of two values depending on 7362 whether some other value is zero or nonzero. In that case, we return the 7363 value that is being tested, *PTRUE is set to the value if the rtx being 7364 returned has a nonzero value, and *PFALSE is set to the other alternative. 7365 7366 If we return zero, we set *PTRUE and *PFALSE to X. */ 7367 7368static rtx 7369if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse) 7370{ 7371 enum machine_mode mode = GET_MODE (x); 7372 enum rtx_code code = GET_CODE (x); 7373 rtx cond0, cond1, true0, true1, false0, false1; 7374 unsigned HOST_WIDE_INT nz; 7375 7376 /* If we are comparing a value against zero, we are done. */ 7377 if ((code == NE || code == EQ) 7378 && XEXP (x, 1) == const0_rtx) 7379 { 7380 *ptrue = (code == NE) ? const_true_rtx : const0_rtx; 7381 *pfalse = (code == NE) ? const0_rtx : const_true_rtx; 7382 return XEXP (x, 0); 7383 } 7384 7385 /* If this is a unary operation whose operand has one of two values, apply 7386 our opcode to compute those values. */ 7387 else if (UNARY_P (x) 7388 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) 7389 { 7390 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0))); 7391 *pfalse = simplify_gen_unary (code, mode, false0, 7392 GET_MODE (XEXP (x, 0))); 7393 return cond0; 7394 } 7395 7396 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would 7397 make can't possibly match and would suppress other optimizations. */ 7398 else if (code == COMPARE) 7399 ; 7400 7401 /* If this is a binary operation, see if either side has only one of two 7402 values. If either one does or if both do and they are conditional on 7403 the same value, compute the new true and false values. */ 7404 else if (BINARY_P (x)) 7405 { 7406 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0); 7407 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1); 7408 7409 if ((cond0 != 0 || cond1 != 0) 7410 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1))) 7411 { 7412 /* If if_then_else_cond returned zero, then true/false are the 7413 same rtl. We must copy one of them to prevent invalid rtl 7414 sharing. */ 7415 if (cond0 == 0) 7416 true0 = copy_rtx (true0); 7417 else if (cond1 == 0) 7418 true1 = copy_rtx (true1); 7419 7420 if (COMPARISON_P (x)) 7421 { 7422 *ptrue = simplify_gen_relational (code, mode, VOIDmode, 7423 true0, true1); 7424 *pfalse = simplify_gen_relational (code, mode, VOIDmode, 7425 false0, false1); 7426 } 7427 else 7428 { 7429 *ptrue = simplify_gen_binary (code, mode, true0, true1); 7430 *pfalse = simplify_gen_binary (code, mode, false0, false1); 7431 } 7432 7433 return cond0 ? cond0 : cond1; 7434 } 7435 7436 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the 7437 operands is zero when the other is nonzero, and vice-versa, 7438 and STORE_FLAG_VALUE is 1 or -1. */ 7439 7440 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 7441 && (code == PLUS || code == IOR || code == XOR || code == MINUS 7442 || code == UMAX) 7443 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 7444 { 7445 rtx op0 = XEXP (XEXP (x, 0), 1); 7446 rtx op1 = XEXP (XEXP (x, 1), 1); 7447 7448 cond0 = XEXP (XEXP (x, 0), 0); 7449 cond1 = XEXP (XEXP (x, 1), 0); 7450 7451 if (COMPARISON_P (cond0) 7452 && COMPARISON_P (cond1) 7453 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) 7454 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 7455 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 7456 || ((swap_condition (GET_CODE (cond0)) 7457 == reversed_comparison_code (cond1, NULL)) 7458 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 7459 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 7460 && ! side_effects_p (x)) 7461 { 7462 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx); 7463 *pfalse = simplify_gen_binary (MULT, mode, 7464 (code == MINUS 7465 ? simplify_gen_unary (NEG, mode, 7466 op1, mode) 7467 : op1), 7468 const_true_rtx); 7469 return cond0; 7470 } 7471 } 7472 7473 /* Similarly for MULT, AND and UMIN, except that for these the result 7474 is always zero. */ 7475 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 7476 && (code == MULT || code == AND || code == UMIN) 7477 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 7478 { 7479 cond0 = XEXP (XEXP (x, 0), 0); 7480 cond1 = XEXP (XEXP (x, 1), 0); 7481 7482 if (COMPARISON_P (cond0) 7483 && COMPARISON_P (cond1) 7484 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) 7485 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 7486 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 7487 || ((swap_condition (GET_CODE (cond0)) 7488 == reversed_comparison_code (cond1, NULL)) 7489 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 7490 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 7491 && ! side_effects_p (x)) 7492 { 7493 *ptrue = *pfalse = const0_rtx; 7494 return cond0; 7495 } 7496 } 7497 } 7498 7499 else if (code == IF_THEN_ELSE) 7500 { 7501 /* If we have IF_THEN_ELSE already, extract the condition and 7502 canonicalize it if it is NE or EQ. */ 7503 cond0 = XEXP (x, 0); 7504 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); 7505 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) 7506 return XEXP (cond0, 0); 7507 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) 7508 { 7509 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); 7510 return XEXP (cond0, 0); 7511 } 7512 else 7513 return cond0; 7514 } 7515 7516 /* If X is a SUBREG, we can narrow both the true and false values 7517 if the inner expression, if there is a condition. */ 7518 else if (code == SUBREG 7519 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), 7520 &true0, &false0))) 7521 { 7522 true0 = simplify_gen_subreg (mode, true0, 7523 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 7524 false0 = simplify_gen_subreg (mode, false0, 7525 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 7526 if (true0 && false0) 7527 { 7528 *ptrue = true0; 7529 *pfalse = false0; 7530 return cond0; 7531 } 7532 } 7533 7534 /* If X is a constant, this isn't special and will cause confusions 7535 if we treat it as such. Likewise if it is equivalent to a constant. */ 7536 else if (CONSTANT_P (x) 7537 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) 7538 ; 7539 7540 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that 7541 will be least confusing to the rest of the compiler. */ 7542 else if (mode == BImode) 7543 { 7544 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx; 7545 return x; 7546 } 7547 7548 /* If X is known to be either 0 or -1, those are the true and 7549 false values when testing X. */ 7550 else if (x == constm1_rtx || x == const0_rtx 7551 || (mode != VOIDmode 7552 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode))) 7553 { 7554 *ptrue = constm1_rtx, *pfalse = const0_rtx; 7555 return x; 7556 } 7557 7558 /* Likewise for 0 or a single bit. */ 7559 else if (SCALAR_INT_MODE_P (mode) 7560 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 7561 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0) 7562 { 7563 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx; 7564 return x; 7565 } 7566 7567 /* Otherwise fail; show no condition with true and false values the same. */ 7568 *ptrue = *pfalse = x; 7569 return 0; 7570} 7571 7572/* Return the value of expression X given the fact that condition COND 7573 is known to be true when applied to REG as its first operand and VAL 7574 as its second. X is known to not be shared and so can be modified in 7575 place. 7576 7577 We only handle the simplest cases, and specifically those cases that 7578 arise with IF_THEN_ELSE expressions. */ 7579 7580static rtx 7581known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val) 7582{ 7583 enum rtx_code code = GET_CODE (x); 7584 rtx temp; 7585 const char *fmt; 7586 int i, j; 7587 7588 if (side_effects_p (x)) 7589 return x; 7590 7591 /* If either operand of the condition is a floating point value, 7592 then we have to avoid collapsing an EQ comparison. */ 7593 if (cond == EQ 7594 && rtx_equal_p (x, reg) 7595 && ! FLOAT_MODE_P (GET_MODE (x)) 7596 && ! FLOAT_MODE_P (GET_MODE (val))) 7597 return val; 7598 7599 if (cond == UNEQ && rtx_equal_p (x, reg)) 7600 return val; 7601 7602 /* If X is (abs REG) and we know something about REG's relationship 7603 with zero, we may be able to simplify this. */ 7604 7605 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) 7606 switch (cond) 7607 { 7608 case GE: case GT: case EQ: 7609 return XEXP (x, 0); 7610 case LT: case LE: 7611 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)), 7612 XEXP (x, 0), 7613 GET_MODE (XEXP (x, 0))); 7614 default: 7615 break; 7616 } 7617 7618 /* The only other cases we handle are MIN, MAX, and comparisons if the 7619 operands are the same as REG and VAL. */ 7620 7621 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x)) 7622 { 7623 if (rtx_equal_p (XEXP (x, 0), val)) 7624 cond = swap_condition (cond), temp = val, val = reg, reg = temp; 7625 7626 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) 7627 { 7628 if (COMPARISON_P (x)) 7629 { 7630 if (comparison_dominates_p (cond, code)) 7631 return const_true_rtx; 7632 7633 code = reversed_comparison_code (x, NULL); 7634 if (code != UNKNOWN 7635 && comparison_dominates_p (cond, code)) 7636 return const0_rtx; 7637 else 7638 return x; 7639 } 7640 else if (code == SMAX || code == SMIN 7641 || code == UMIN || code == UMAX) 7642 { 7643 int unsignedp = (code == UMIN || code == UMAX); 7644 7645 /* Do not reverse the condition when it is NE or EQ. 7646 This is because we cannot conclude anything about 7647 the value of 'SMAX (x, y)' when x is not equal to y, 7648 but we can when x equals y. */ 7649 if ((code == SMAX || code == UMAX) 7650 && ! (cond == EQ || cond == NE)) 7651 cond = reverse_condition (cond); 7652 7653 switch (cond) 7654 { 7655 case GE: case GT: 7656 return unsignedp ? x : XEXP (x, 1); 7657 case LE: case LT: 7658 return unsignedp ? x : XEXP (x, 0); 7659 case GEU: case GTU: 7660 return unsignedp ? XEXP (x, 1) : x; 7661 case LEU: case LTU: 7662 return unsignedp ? XEXP (x, 0) : x; 7663 default: 7664 break; 7665 } 7666 } 7667 } 7668 } 7669 else if (code == SUBREG) 7670 { 7671 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x)); 7672 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val); 7673 7674 if (SUBREG_REG (x) != r) 7675 { 7676 /* We must simplify subreg here, before we lose track of the 7677 original inner_mode. */ 7678 new = simplify_subreg (GET_MODE (x), r, 7679 inner_mode, SUBREG_BYTE (x)); 7680 if (new) 7681 return new; 7682 else 7683 SUBST (SUBREG_REG (x), r); 7684 } 7685 7686 return x; 7687 } 7688 /* We don't have to handle SIGN_EXTEND here, because even in the 7689 case of replacing something with a modeless CONST_INT, a 7690 CONST_INT is already (supposed to be) a valid sign extension for 7691 its narrower mode, which implies it's already properly 7692 sign-extended for the wider mode. Now, for ZERO_EXTEND, the 7693 story is different. */ 7694 else if (code == ZERO_EXTEND) 7695 { 7696 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0)); 7697 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val); 7698 7699 if (XEXP (x, 0) != r) 7700 { 7701 /* We must simplify the zero_extend here, before we lose 7702 track of the original inner_mode. */ 7703 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), 7704 r, inner_mode); 7705 if (new) 7706 return new; 7707 else 7708 SUBST (XEXP (x, 0), r); 7709 } 7710 7711 return x; 7712 } 7713 7714 fmt = GET_RTX_FORMAT (code); 7715 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 7716 { 7717 if (fmt[i] == 'e') 7718 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); 7719 else if (fmt[i] == 'E') 7720 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 7721 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), 7722 cond, reg, val)); 7723 } 7724 7725 return x; 7726} 7727 7728/* See if X and Y are equal for the purposes of seeing if we can rewrite an 7729 assignment as a field assignment. */ 7730 7731static int 7732rtx_equal_for_field_assignment_p (rtx x, rtx y) 7733{ 7734 if (x == y || rtx_equal_p (x, y)) 7735 return 1; 7736 7737 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) 7738 return 0; 7739 7740 /* Check for a paradoxical SUBREG of a MEM compared with the MEM. 7741 Note that all SUBREGs of MEM are paradoxical; otherwise they 7742 would have been rewritten. */ 7743 if (MEM_P (x) && GET_CODE (y) == SUBREG 7744 && MEM_P (SUBREG_REG (y)) 7745 && rtx_equal_p (SUBREG_REG (y), 7746 gen_lowpart (GET_MODE (SUBREG_REG (y)), x))) 7747 return 1; 7748 7749 if (MEM_P (y) && GET_CODE (x) == SUBREG 7750 && MEM_P (SUBREG_REG (x)) 7751 && rtx_equal_p (SUBREG_REG (x), 7752 gen_lowpart (GET_MODE (SUBREG_REG (x)), y))) 7753 return 1; 7754 7755 /* We used to see if get_last_value of X and Y were the same but that's 7756 not correct. In one direction, we'll cause the assignment to have 7757 the wrong destination and in the case, we'll import a register into this 7758 insn that might have already have been dead. So fail if none of the 7759 above cases are true. */ 7760 return 0; 7761} 7762 7763/* See if X, a SET operation, can be rewritten as a bit-field assignment. 7764 Return that assignment if so. 7765 7766 We only handle the most common cases. */ 7767 7768static rtx 7769make_field_assignment (rtx x) 7770{ 7771 rtx dest = SET_DEST (x); 7772 rtx src = SET_SRC (x); 7773 rtx assign; 7774 rtx rhs, lhs; 7775 HOST_WIDE_INT c1; 7776 HOST_WIDE_INT pos; 7777 unsigned HOST_WIDE_INT len; 7778 rtx other; 7779 enum machine_mode mode; 7780 7781 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is 7782 a clear of a one-bit field. We will have changed it to 7783 (and (rotate (const_int -2) POS) DEST), so check for that. Also check 7784 for a SUBREG. */ 7785 7786 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE 7787 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT 7788 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 7789 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7790 { 7791 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 7792 1, 1, 1, 0); 7793 if (assign != 0) 7794 return gen_rtx_SET (VOIDmode, assign, const0_rtx); 7795 return x; 7796 } 7797 7798 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG 7799 && subreg_lowpart_p (XEXP (src, 0)) 7800 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) 7801 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) 7802 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE 7803 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT 7804 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 7805 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7806 { 7807 assign = make_extraction (VOIDmode, dest, 0, 7808 XEXP (SUBREG_REG (XEXP (src, 0)), 1), 7809 1, 1, 1, 0); 7810 if (assign != 0) 7811 return gen_rtx_SET (VOIDmode, assign, const0_rtx); 7812 return x; 7813 } 7814 7815 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a 7816 one-bit field. */ 7817 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT 7818 && XEXP (XEXP (src, 0), 0) == const1_rtx 7819 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7820 { 7821 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 7822 1, 1, 1, 0); 7823 if (assign != 0) 7824 return gen_rtx_SET (VOIDmode, assign, const1_rtx); 7825 return x; 7826 } 7827 7828 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the 7829 SRC is an AND with all bits of that field set, then we can discard 7830 the AND. */ 7831 if (GET_CODE (dest) == ZERO_EXTRACT 7832 && GET_CODE (XEXP (dest, 1)) == CONST_INT 7833 && GET_CODE (src) == AND 7834 && GET_CODE (XEXP (src, 1)) == CONST_INT) 7835 { 7836 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1)); 7837 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1)); 7838 unsigned HOST_WIDE_INT ze_mask; 7839 7840 if (width >= HOST_BITS_PER_WIDE_INT) 7841 ze_mask = -1; 7842 else 7843 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1; 7844 7845 /* Complete overlap. We can remove the source AND. */ 7846 if ((and_mask & ze_mask) == ze_mask) 7847 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0)); 7848 7849 /* Partial overlap. We can reduce the source AND. */ 7850 if ((and_mask & ze_mask) != and_mask) 7851 { 7852 mode = GET_MODE (src); 7853 src = gen_rtx_AND (mode, XEXP (src, 0), 7854 gen_int_mode (and_mask & ze_mask, mode)); 7855 return gen_rtx_SET (VOIDmode, dest, src); 7856 } 7857 } 7858 7859 /* The other case we handle is assignments into a constant-position 7860 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents 7861 a mask that has all one bits except for a group of zero bits and 7862 OTHER is known to have zeros where C1 has ones, this is such an 7863 assignment. Compute the position and length from C1. Shift OTHER 7864 to the appropriate position, force it to the required mode, and 7865 make the extraction. Check for the AND in both operands. */ 7866 7867 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) 7868 return x; 7869 7870 rhs = expand_compound_operation (XEXP (src, 0)); 7871 lhs = expand_compound_operation (XEXP (src, 1)); 7872 7873 if (GET_CODE (rhs) == AND 7874 && GET_CODE (XEXP (rhs, 1)) == CONST_INT 7875 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) 7876 c1 = INTVAL (XEXP (rhs, 1)), other = lhs; 7877 else if (GET_CODE (lhs) == AND 7878 && GET_CODE (XEXP (lhs, 1)) == CONST_INT 7879 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) 7880 c1 = INTVAL (XEXP (lhs, 1)), other = rhs; 7881 else 7882 return x; 7883 7884 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len); 7885 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest)) 7886 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT 7887 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0) 7888 return x; 7889 7890 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); 7891 if (assign == 0) 7892 return x; 7893 7894 /* The mode to use for the source is the mode of the assignment, or of 7895 what is inside a possible STRICT_LOW_PART. */ 7896 mode = (GET_CODE (assign) == STRICT_LOW_PART 7897 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); 7898 7899 /* Shift OTHER right POS places and make it the source, restricting it 7900 to the proper length and mode. */ 7901 7902 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT, 7903 GET_MODE (src), 7904 other, pos), 7905 dest); 7906 src = force_to_mode (src, mode, 7907 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT 7908 ? ~(unsigned HOST_WIDE_INT) 0 7909 : ((unsigned HOST_WIDE_INT) 1 << len) - 1, 7910 0); 7911 7912 /* If SRC is masked by an AND that does not make a difference in 7913 the value being stored, strip it. */ 7914 if (GET_CODE (assign) == ZERO_EXTRACT 7915 && GET_CODE (XEXP (assign, 1)) == CONST_INT 7916 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT 7917 && GET_CODE (src) == AND 7918 && GET_CODE (XEXP (src, 1)) == CONST_INT 7919 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1)) 7920 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)) 7921 src = XEXP (src, 0); 7922 7923 return gen_rtx_SET (VOIDmode, assign, src); 7924} 7925 7926/* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) 7927 if so. */ 7928 7929static rtx 7930apply_distributive_law (rtx x) 7931{ 7932 enum rtx_code code = GET_CODE (x); 7933 enum rtx_code inner_code; 7934 rtx lhs, rhs, other; 7935 rtx tem; 7936 7937 /* Distributivity is not true for floating point as it can change the 7938 value. So we don't do it unless -funsafe-math-optimizations. */ 7939 if (FLOAT_MODE_P (GET_MODE (x)) 7940 && ! flag_unsafe_math_optimizations) 7941 return x; 7942 7943 /* The outer operation can only be one of the following: */ 7944 if (code != IOR && code != AND && code != XOR 7945 && code != PLUS && code != MINUS) 7946 return x; 7947 7948 lhs = XEXP (x, 0); 7949 rhs = XEXP (x, 1); 7950 7951 /* If either operand is a primitive we can't do anything, so get out 7952 fast. */ 7953 if (OBJECT_P (lhs) || OBJECT_P (rhs)) 7954 return x; 7955 7956 lhs = expand_compound_operation (lhs); 7957 rhs = expand_compound_operation (rhs); 7958 inner_code = GET_CODE (lhs); 7959 if (inner_code != GET_CODE (rhs)) 7960 return x; 7961 7962 /* See if the inner and outer operations distribute. */ 7963 switch (inner_code) 7964 { 7965 case LSHIFTRT: 7966 case ASHIFTRT: 7967 case AND: 7968 case IOR: 7969 /* These all distribute except over PLUS. */ 7970 if (code == PLUS || code == MINUS) 7971 return x; 7972 break; 7973 7974 case MULT: 7975 if (code != PLUS && code != MINUS) 7976 return x; 7977 break; 7978 7979 case ASHIFT: 7980 /* This is also a multiply, so it distributes over everything. */ 7981 break; 7982 7983 case SUBREG: 7984 /* Non-paradoxical SUBREGs distributes over all operations, 7985 provided the inner modes and byte offsets are the same, this 7986 is an extraction of a low-order part, we don't convert an fp 7987 operation to int or vice versa, this is not a vector mode, 7988 and we would not be converting a single-word operation into a 7989 multi-word operation. The latter test is not required, but 7990 it prevents generating unneeded multi-word operations. Some 7991 of the previous tests are redundant given the latter test, 7992 but are retained because they are required for correctness. 7993 7994 We produce the result slightly differently in this case. */ 7995 7996 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs)) 7997 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs) 7998 || ! subreg_lowpart_p (lhs) 7999 || (GET_MODE_CLASS (GET_MODE (lhs)) 8000 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) 8001 || (GET_MODE_SIZE (GET_MODE (lhs)) 8002 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) 8003 || VECTOR_MODE_P (GET_MODE (lhs)) 8004 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD 8005 /* Result might need to be truncated. Don't change mode if 8006 explicit truncation is needed. */ 8007 || !TRULY_NOOP_TRUNCATION 8008 (GET_MODE_BITSIZE (GET_MODE (x)), 8009 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs))))) 8010 return x; 8011 8012 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)), 8013 SUBREG_REG (lhs), SUBREG_REG (rhs)); 8014 return gen_lowpart (GET_MODE (x), tem); 8015 8016 default: 8017 return x; 8018 } 8019 8020 /* Set LHS and RHS to the inner operands (A and B in the example 8021 above) and set OTHER to the common operand (C in the example). 8022 There is only one way to do this unless the inner operation is 8023 commutative. */ 8024 if (COMMUTATIVE_ARITH_P (lhs) 8025 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) 8026 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); 8027 else if (COMMUTATIVE_ARITH_P (lhs) 8028 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) 8029 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); 8030 else if (COMMUTATIVE_ARITH_P (lhs) 8031 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) 8032 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); 8033 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) 8034 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); 8035 else 8036 return x; 8037 8038 /* Form the new inner operation, seeing if it simplifies first. */ 8039 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs); 8040 8041 /* There is one exception to the general way of distributing: 8042 (a | c) ^ (b | c) -> (a ^ b) & ~c */ 8043 if (code == XOR && inner_code == IOR) 8044 { 8045 inner_code = AND; 8046 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x)); 8047 } 8048 8049 /* We may be able to continuing distributing the result, so call 8050 ourselves recursively on the inner operation before forming the 8051 outer operation, which we return. */ 8052 return simplify_gen_binary (inner_code, GET_MODE (x), 8053 apply_distributive_law (tem), other); 8054} 8055 8056/* See if X is of the form (* (+ A B) C), and if so convert to 8057 (+ (* A C) (* B C)) and try to simplify. 8058 8059 Most of the time, this results in no change. However, if some of 8060 the operands are the same or inverses of each other, simplifications 8061 will result. 8062 8063 For example, (and (ior A B) (not B)) can occur as the result of 8064 expanding a bit field assignment. When we apply the distributive 8065 law to this, we get (ior (and (A (not B))) (and (B (not B)))), 8066 which then simplifies to (and (A (not B))). 8067 8068 Note that no checks happen on the validity of applying the inverse 8069 distributive law. This is pointless since we can do it in the 8070 few places where this routine is called. 8071 8072 N is the index of the term that is decomposed (the arithmetic operation, 8073 i.e. (+ A B) in the first example above). !N is the index of the term that 8074 is distributed, i.e. of C in the first example above. */ 8075static rtx 8076distribute_and_simplify_rtx (rtx x, int n) 8077{ 8078 enum machine_mode mode; 8079 enum rtx_code outer_code, inner_code; 8080 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp; 8081 8082 decomposed = XEXP (x, n); 8083 if (!ARITHMETIC_P (decomposed)) 8084 return NULL_RTX; 8085 8086 mode = GET_MODE (x); 8087 outer_code = GET_CODE (x); 8088 distributed = XEXP (x, !n); 8089 8090 inner_code = GET_CODE (decomposed); 8091 inner_op0 = XEXP (decomposed, 0); 8092 inner_op1 = XEXP (decomposed, 1); 8093 8094 /* Special case (and (xor B C) (not A)), which is equivalent to 8095 (xor (ior A B) (ior A C)) */ 8096 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT) 8097 { 8098 distributed = XEXP (distributed, 0); 8099 outer_code = IOR; 8100 } 8101 8102 if (n == 0) 8103 { 8104 /* Distribute the second term. */ 8105 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed); 8106 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed); 8107 } 8108 else 8109 { 8110 /* Distribute the first term. */ 8111 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0); 8112 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1); 8113 } 8114 8115 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode, 8116 new_op0, new_op1)); 8117 if (GET_CODE (tmp) != outer_code 8118 && rtx_cost (tmp, SET) < rtx_cost (x, SET)) 8119 return tmp; 8120 8121 return NULL_RTX; 8122} 8123 8124/* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done 8125 in MODE. Return an equivalent form, if different from (and VAROP 8126 (const_int CONSTOP)). Otherwise, return NULL_RTX. */ 8127 8128static rtx 8129simplify_and_const_int_1 (enum machine_mode mode, rtx varop, 8130 unsigned HOST_WIDE_INT constop) 8131{ 8132 unsigned HOST_WIDE_INT nonzero; 8133 unsigned HOST_WIDE_INT orig_constop; 8134 rtx orig_varop; 8135 int i; 8136 8137 orig_varop = varop; 8138 orig_constop = constop; 8139 if (GET_CODE (varop) == CLOBBER) 8140 return NULL_RTX; 8141 8142 /* Simplify VAROP knowing that we will be only looking at some of the 8143 bits in it. 8144 8145 Note by passing in CONSTOP, we guarantee that the bits not set in 8146 CONSTOP are not significant and will never be examined. We must 8147 ensure that is the case by explicitly masking out those bits 8148 before returning. */ 8149 varop = force_to_mode (varop, mode, constop, 0); 8150 8151 /* If VAROP is a CLOBBER, we will fail so return it. */ 8152 if (GET_CODE (varop) == CLOBBER) 8153 return varop; 8154 8155 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP 8156 to VAROP and return the new constant. */ 8157 if (GET_CODE (varop) == CONST_INT) 8158 return gen_int_mode (INTVAL (varop) & constop, mode); 8159 8160 /* See what bits may be nonzero in VAROP. Unlike the general case of 8161 a call to nonzero_bits, here we don't care about bits outside 8162 MODE. */ 8163 8164 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); 8165 8166 /* Turn off all bits in the constant that are known to already be zero. 8167 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS 8168 which is tested below. */ 8169 8170 constop &= nonzero; 8171 8172 /* If we don't have any bits left, return zero. */ 8173 if (constop == 0) 8174 return const0_rtx; 8175 8176 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is 8177 a power of two, we can replace this with an ASHIFT. */ 8178 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 8179 && (i = exact_log2 (constop)) >= 0) 8180 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); 8181 8182 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR 8183 or XOR, then try to apply the distributive law. This may eliminate 8184 operations if either branch can be simplified because of the AND. 8185 It may also make some cases more complex, but those cases probably 8186 won't match a pattern either with or without this. */ 8187 8188 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) 8189 return 8190 gen_lowpart 8191 (mode, 8192 apply_distributive_law 8193 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop), 8194 simplify_and_const_int (NULL_RTX, 8195 GET_MODE (varop), 8196 XEXP (varop, 0), 8197 constop), 8198 simplify_and_const_int (NULL_RTX, 8199 GET_MODE (varop), 8200 XEXP (varop, 1), 8201 constop)))); 8202 8203 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute 8204 the AND and see if one of the operands simplifies to zero. If so, we 8205 may eliminate it. */ 8206 8207 if (GET_CODE (varop) == PLUS 8208 && exact_log2 (constop + 1) >= 0) 8209 { 8210 rtx o0, o1; 8211 8212 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop); 8213 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop); 8214 if (o0 == const0_rtx) 8215 return o1; 8216 if (o1 == const0_rtx) 8217 return o0; 8218 } 8219 8220 /* Make a SUBREG if necessary. If we can't make it, fail. */ 8221 varop = gen_lowpart (mode, varop); 8222 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER) 8223 return NULL_RTX; 8224 8225 /* If we are only masking insignificant bits, return VAROP. */ 8226 if (constop == nonzero) 8227 return varop; 8228 8229 if (varop == orig_varop && constop == orig_constop) 8230 return NULL_RTX; 8231 8232 /* Otherwise, return an AND. */ 8233 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode)); 8234} 8235 8236 8237/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done 8238 in MODE. 8239 8240 Return an equivalent form, if different from X. Otherwise, return X. If 8241 X is zero, we are to always construct the equivalent form. */ 8242 8243static rtx 8244simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop, 8245 unsigned HOST_WIDE_INT constop) 8246{ 8247 rtx tem = simplify_and_const_int_1 (mode, varop, constop); 8248 if (tem) 8249 return tem; 8250 8251 if (!x) 8252 x = simplify_gen_binary (AND, GET_MODE (varop), varop, 8253 gen_int_mode (constop, mode)); 8254 if (GET_MODE (x) != mode) 8255 x = gen_lowpart (mode, x); 8256 return x; 8257} 8258 8259/* Given a REG, X, compute which bits in X can be nonzero. 8260 We don't care about bits outside of those defined in MODE. 8261 8262 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is 8263 a shift, AND, or zero_extract, we can do better. */ 8264 8265static rtx 8266reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode, 8267 rtx known_x ATTRIBUTE_UNUSED, 8268 enum machine_mode known_mode ATTRIBUTE_UNUSED, 8269 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED, 8270 unsigned HOST_WIDE_INT *nonzero) 8271{ 8272 rtx tem; 8273 8274 /* If X is a register whose nonzero bits value is current, use it. 8275 Otherwise, if X is a register whose value we can find, use that 8276 value. Otherwise, use the previously-computed global nonzero bits 8277 for this register. */ 8278 8279 if (reg_stat[REGNO (x)].last_set_value != 0 8280 && (reg_stat[REGNO (x)].last_set_mode == mode 8281 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT 8282 && GET_MODE_CLASS (mode) == MODE_INT)) 8283 && (reg_stat[REGNO (x)].last_set_label == label_tick 8284 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 8285 && REG_N_SETS (REGNO (x)) == 1 8286 && ! REGNO_REG_SET_P 8287 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, 8288 REGNO (x)))) 8289 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid) 8290 { 8291 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits; 8292 return NULL; 8293 } 8294 8295 tem = get_last_value (x); 8296 8297 if (tem) 8298 { 8299#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 8300 /* If X is narrower than MODE and TEM is a non-negative 8301 constant that would appear negative in the mode of X, 8302 sign-extend it for use in reg_nonzero_bits because some 8303 machines (maybe most) will actually do the sign-extension 8304 and this is the conservative approach. 8305 8306 ??? For 2.5, try to tighten up the MD files in this regard 8307 instead of this kludge. */ 8308 8309 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode) 8310 && GET_CODE (tem) == CONST_INT 8311 && INTVAL (tem) > 0 8312 && 0 != (INTVAL (tem) 8313 & ((HOST_WIDE_INT) 1 8314 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 8315 tem = GEN_INT (INTVAL (tem) 8316 | ((HOST_WIDE_INT) (-1) 8317 << GET_MODE_BITSIZE (GET_MODE (x)))); 8318#endif 8319 return tem; 8320 } 8321 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits) 8322 { 8323 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits; 8324 8325 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)) 8326 /* We don't know anything about the upper bits. */ 8327 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x)); 8328 *nonzero &= mask; 8329 } 8330 8331 return NULL; 8332} 8333 8334/* Return the number of bits at the high-order end of X that are known to 8335 be equal to the sign bit. X will be used in mode MODE; if MODE is 8336 VOIDmode, X will be used in its own mode. The returned value will always 8337 be between 1 and the number of bits in MODE. */ 8338 8339static rtx 8340reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode, 8341 rtx known_x ATTRIBUTE_UNUSED, 8342 enum machine_mode known_mode 8343 ATTRIBUTE_UNUSED, 8344 unsigned int known_ret ATTRIBUTE_UNUSED, 8345 unsigned int *result) 8346{ 8347 rtx tem; 8348 8349 if (reg_stat[REGNO (x)].last_set_value != 0 8350 && reg_stat[REGNO (x)].last_set_mode == mode 8351 && (reg_stat[REGNO (x)].last_set_label == label_tick 8352 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 8353 && REG_N_SETS (REGNO (x)) == 1 8354 && ! REGNO_REG_SET_P 8355 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, 8356 REGNO (x)))) 8357 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid) 8358 { 8359 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies; 8360 return NULL; 8361 } 8362 8363 tem = get_last_value (x); 8364 if (tem != 0) 8365 return tem; 8366 8367 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0 8368 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode)) 8369 *result = reg_stat[REGNO (x)].sign_bit_copies; 8370 8371 return NULL; 8372} 8373 8374/* Return the number of "extended" bits there are in X, when interpreted 8375 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For 8376 unsigned quantities, this is the number of high-order zero bits. 8377 For signed quantities, this is the number of copies of the sign bit 8378 minus 1. In both case, this function returns the number of "spare" 8379 bits. For example, if two quantities for which this function returns 8380 at least 1 are added, the addition is known not to overflow. 8381 8382 This function will always return 0 unless called during combine, which 8383 implies that it must be called from a define_split. */ 8384 8385unsigned int 8386extended_count (rtx x, enum machine_mode mode, int unsignedp) 8387{ 8388 if (nonzero_sign_valid == 0) 8389 return 0; 8390 8391 return (unsignedp 8392 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 8393 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1 8394 - floor_log2 (nonzero_bits (x, mode))) 8395 : 0) 8396 : num_sign_bit_copies (x, mode) - 1); 8397} 8398 8399/* This function is called from `simplify_shift_const' to merge two 8400 outer operations. Specifically, we have already found that we need 8401 to perform operation *POP0 with constant *PCONST0 at the outermost 8402 position. We would now like to also perform OP1 with constant CONST1 8403 (with *POP0 being done last). 8404 8405 Return 1 if we can do the operation and update *POP0 and *PCONST0 with 8406 the resulting operation. *PCOMP_P is set to 1 if we would need to 8407 complement the innermost operand, otherwise it is unchanged. 8408 8409 MODE is the mode in which the operation will be done. No bits outside 8410 the width of this mode matter. It is assumed that the width of this mode 8411 is smaller than or equal to HOST_BITS_PER_WIDE_INT. 8412 8413 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS, 8414 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper 8415 result is simply *PCONST0. 8416 8417 If the resulting operation cannot be expressed as one operation, we 8418 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ 8419 8420static int 8421merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p) 8422{ 8423 enum rtx_code op0 = *pop0; 8424 HOST_WIDE_INT const0 = *pconst0; 8425 8426 const0 &= GET_MODE_MASK (mode); 8427 const1 &= GET_MODE_MASK (mode); 8428 8429 /* If OP0 is an AND, clear unimportant bits in CONST1. */ 8430 if (op0 == AND) 8431 const1 &= const0; 8432 8433 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or 8434 if OP0 is SET. */ 8435 8436 if (op1 == UNKNOWN || op0 == SET) 8437 return 1; 8438 8439 else if (op0 == UNKNOWN) 8440 op0 = op1, const0 = const1; 8441 8442 else if (op0 == op1) 8443 { 8444 switch (op0) 8445 { 8446 case AND: 8447 const0 &= const1; 8448 break; 8449 case IOR: 8450 const0 |= const1; 8451 break; 8452 case XOR: 8453 const0 ^= const1; 8454 break; 8455 case PLUS: 8456 const0 += const1; 8457 break; 8458 case NEG: 8459 op0 = UNKNOWN; 8460 break; 8461 default: 8462 break; 8463 } 8464 } 8465 8466 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ 8467 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) 8468 return 0; 8469 8470 /* If the two constants aren't the same, we can't do anything. The 8471 remaining six cases can all be done. */ 8472 else if (const0 != const1) 8473 return 0; 8474 8475 else 8476 switch (op0) 8477 { 8478 case IOR: 8479 if (op1 == AND) 8480 /* (a & b) | b == b */ 8481 op0 = SET; 8482 else /* op1 == XOR */ 8483 /* (a ^ b) | b == a | b */ 8484 {;} 8485 break; 8486 8487 case XOR: 8488 if (op1 == AND) 8489 /* (a & b) ^ b == (~a) & b */ 8490 op0 = AND, *pcomp_p = 1; 8491 else /* op1 == IOR */ 8492 /* (a | b) ^ b == a & ~b */ 8493 op0 = AND, const0 = ~const0; 8494 break; 8495 8496 case AND: 8497 if (op1 == IOR) 8498 /* (a | b) & b == b */ 8499 op0 = SET; 8500 else /* op1 == XOR */ 8501 /* (a ^ b) & b) == (~a) & b */ 8502 *pcomp_p = 1; 8503 break; 8504 default: 8505 break; 8506 } 8507 8508 /* Check for NO-OP cases. */ 8509 const0 &= GET_MODE_MASK (mode); 8510 if (const0 == 0 8511 && (op0 == IOR || op0 == XOR || op0 == PLUS)) 8512 op0 = UNKNOWN; 8513 else if (const0 == 0 && op0 == AND) 8514 op0 = SET; 8515 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) 8516 && op0 == AND) 8517 op0 = UNKNOWN; 8518 8519 /* ??? Slightly redundant with the above mask, but not entirely. 8520 Moving this above means we'd have to sign-extend the mode mask 8521 for the final test. */ 8522 const0 = trunc_int_for_mode (const0, mode); 8523 8524 *pop0 = op0; 8525 *pconst0 = const0; 8526 8527 return 1; 8528} 8529 8530/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. 8531 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot 8532 simplify it. Otherwise, return a simplified value. 8533 8534 The shift is normally computed in the widest mode we find in VAROP, as 8535 long as it isn't a different number of words than RESULT_MODE. Exceptions 8536 are ASHIFTRT and ROTATE, which are always done in their original mode. */ 8537 8538static rtx 8539simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode, 8540 rtx varop, int orig_count) 8541{ 8542 enum rtx_code orig_code = code; 8543 rtx orig_varop = varop; 8544 int count; 8545 enum machine_mode mode = result_mode; 8546 enum machine_mode shift_mode, tmode; 8547 unsigned int mode_words 8548 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; 8549 /* We form (outer_op (code varop count) (outer_const)). */ 8550 enum rtx_code outer_op = UNKNOWN; 8551 HOST_WIDE_INT outer_const = 0; 8552 int complement_p = 0; 8553 rtx new, x; 8554 8555 /* Make sure and truncate the "natural" shift on the way in. We don't 8556 want to do this inside the loop as it makes it more difficult to 8557 combine shifts. */ 8558 if (SHIFT_COUNT_TRUNCATED) 8559 orig_count &= GET_MODE_BITSIZE (mode) - 1; 8560 8561 /* If we were given an invalid count, don't do anything except exactly 8562 what was requested. */ 8563 8564 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode)) 8565 return NULL_RTX; 8566 8567 count = orig_count; 8568 8569 /* Unless one of the branches of the `if' in this loop does a `continue', 8570 we will `break' the loop after the `if'. */ 8571 8572 while (count != 0) 8573 { 8574 /* If we have an operand of (clobber (const_int 0)), fail. */ 8575 if (GET_CODE (varop) == CLOBBER) 8576 return NULL_RTX; 8577 8578 /* If we discovered we had to complement VAROP, leave. Making a NOT 8579 here would cause an infinite loop. */ 8580 if (complement_p) 8581 break; 8582 8583 /* Convert ROTATERT to ROTATE. */ 8584 if (code == ROTATERT) 8585 { 8586 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);; 8587 code = ROTATE; 8588 if (VECTOR_MODE_P (result_mode)) 8589 count = bitsize / GET_MODE_NUNITS (result_mode) - count; 8590 else 8591 count = bitsize - count; 8592 } 8593 8594 /* We need to determine what mode we will do the shift in. If the 8595 shift is a right shift or a ROTATE, we must always do it in the mode 8596 it was originally done in. Otherwise, we can do it in MODE, the 8597 widest mode encountered. */ 8598 shift_mode 8599 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE 8600 ? result_mode : mode); 8601 8602 /* Handle cases where the count is greater than the size of the mode 8603 minus 1. For ASHIFT, use the size minus one as the count (this can 8604 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, 8605 take the count modulo the size. For other shifts, the result is 8606 zero. 8607 8608 Since these shifts are being produced by the compiler by combining 8609 multiple operations, each of which are defined, we know what the 8610 result is supposed to be. */ 8611 8612 if (count > (GET_MODE_BITSIZE (shift_mode) - 1)) 8613 { 8614 if (code == ASHIFTRT) 8615 count = GET_MODE_BITSIZE (shift_mode) - 1; 8616 else if (code == ROTATE || code == ROTATERT) 8617 count %= GET_MODE_BITSIZE (shift_mode); 8618 else 8619 { 8620 /* We can't simply return zero because there may be an 8621 outer op. */ 8622 varop = const0_rtx; 8623 count = 0; 8624 break; 8625 } 8626 } 8627 8628 /* An arithmetic right shift of a quantity known to be -1 or 0 8629 is a no-op. */ 8630 if (code == ASHIFTRT 8631 && (num_sign_bit_copies (varop, shift_mode) 8632 == GET_MODE_BITSIZE (shift_mode))) 8633 { 8634 count = 0; 8635 break; 8636 } 8637 8638 /* If we are doing an arithmetic right shift and discarding all but 8639 the sign bit copies, this is equivalent to doing a shift by the 8640 bitsize minus one. Convert it into that shift because it will often 8641 allow other simplifications. */ 8642 8643 if (code == ASHIFTRT 8644 && (count + num_sign_bit_copies (varop, shift_mode) 8645 >= GET_MODE_BITSIZE (shift_mode))) 8646 count = GET_MODE_BITSIZE (shift_mode) - 1; 8647 8648 /* We simplify the tests below and elsewhere by converting 8649 ASHIFTRT to LSHIFTRT if we know the sign bit is clear. 8650 `make_compound_operation' will convert it to an ASHIFTRT for 8651 those machines (such as VAX) that don't have an LSHIFTRT. */ 8652 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT 8653 && code == ASHIFTRT 8654 && ((nonzero_bits (varop, shift_mode) 8655 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1))) 8656 == 0)) 8657 code = LSHIFTRT; 8658 8659 if (((code == LSHIFTRT 8660 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT 8661 && !(nonzero_bits (varop, shift_mode) >> count)) 8662 || (code == ASHIFT 8663 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT 8664 && !((nonzero_bits (varop, shift_mode) << count) 8665 & GET_MODE_MASK (shift_mode)))) 8666 && !side_effects_p (varop)) 8667 varop = const0_rtx; 8668 8669 switch (GET_CODE (varop)) 8670 { 8671 case SIGN_EXTEND: 8672 case ZERO_EXTEND: 8673 case SIGN_EXTRACT: 8674 case ZERO_EXTRACT: 8675 new = expand_compound_operation (varop); 8676 if (new != varop) 8677 { 8678 varop = new; 8679 continue; 8680 } 8681 break; 8682 8683 case MEM: 8684 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH 8685 minus the width of a smaller mode, we can do this with a 8686 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ 8687 if ((code == ASHIFTRT || code == LSHIFTRT) 8688 && ! mode_dependent_address_p (XEXP (varop, 0)) 8689 && ! MEM_VOLATILE_P (varop) 8690 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 8691 MODE_INT, 1)) != BLKmode) 8692 { 8693 new = adjust_address_nv (varop, tmode, 8694 BYTES_BIG_ENDIAN ? 0 8695 : count / BITS_PER_UNIT); 8696 8697 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND 8698 : ZERO_EXTEND, mode, new); 8699 count = 0; 8700 continue; 8701 } 8702 break; 8703 8704 case SUBREG: 8705 /* If VAROP is a SUBREG, strip it as long as the inner operand has 8706 the same number of words as what we've seen so far. Then store 8707 the widest mode in MODE. */ 8708 if (subreg_lowpart_p (varop) 8709 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 8710 > GET_MODE_SIZE (GET_MODE (varop))) 8711 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 8712 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 8713 == mode_words) 8714 { 8715 varop = SUBREG_REG (varop); 8716 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) 8717 mode = GET_MODE (varop); 8718 continue; 8719 } 8720 break; 8721 8722 case MULT: 8723 /* Some machines use MULT instead of ASHIFT because MULT 8724 is cheaper. But it is still better on those machines to 8725 merge two shifts into one. */ 8726 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8727 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) 8728 { 8729 varop 8730 = simplify_gen_binary (ASHIFT, GET_MODE (varop), 8731 XEXP (varop, 0), 8732 GEN_INT (exact_log2 ( 8733 INTVAL (XEXP (varop, 1))))); 8734 continue; 8735 } 8736 break; 8737 8738 case UDIV: 8739 /* Similar, for when divides are cheaper. */ 8740 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8741 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) 8742 { 8743 varop 8744 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop), 8745 XEXP (varop, 0), 8746 GEN_INT (exact_log2 ( 8747 INTVAL (XEXP (varop, 1))))); 8748 continue; 8749 } 8750 break; 8751 8752 case ASHIFTRT: 8753 /* If we are extracting just the sign bit of an arithmetic 8754 right shift, that shift is not needed. However, the sign 8755 bit of a wider mode may be different from what would be 8756 interpreted as the sign bit in a narrower mode, so, if 8757 the result is narrower, don't discard the shift. */ 8758 if (code == LSHIFTRT 8759 && count == (GET_MODE_BITSIZE (result_mode) - 1) 8760 && (GET_MODE_BITSIZE (result_mode) 8761 >= GET_MODE_BITSIZE (GET_MODE (varop)))) 8762 { 8763 varop = XEXP (varop, 0); 8764 continue; 8765 } 8766 8767 /* ... fall through ... */ 8768 8769 case LSHIFTRT: 8770 case ASHIFT: 8771 case ROTATE: 8772 /* Here we have two nested shifts. The result is usually the 8773 AND of a new shift with a mask. We compute the result below. */ 8774 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8775 && INTVAL (XEXP (varop, 1)) >= 0 8776 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop)) 8777 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 8778 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 8779 && !VECTOR_MODE_P (result_mode)) 8780 { 8781 enum rtx_code first_code = GET_CODE (varop); 8782 unsigned int first_count = INTVAL (XEXP (varop, 1)); 8783 unsigned HOST_WIDE_INT mask; 8784 rtx mask_rtx; 8785 8786 /* We have one common special case. We can't do any merging if 8787 the inner code is an ASHIFTRT of a smaller mode. However, if 8788 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) 8789 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), 8790 we can convert it to 8791 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1). 8792 This simplifies certain SIGN_EXTEND operations. */ 8793 if (code == ASHIFT && first_code == ASHIFTRT 8794 && count == (GET_MODE_BITSIZE (result_mode) 8795 - GET_MODE_BITSIZE (GET_MODE (varop)))) 8796 { 8797 /* C3 has the low-order C1 bits zero. */ 8798 8799 mask = (GET_MODE_MASK (mode) 8800 & ~(((HOST_WIDE_INT) 1 << first_count) - 1)); 8801 8802 varop = simplify_and_const_int (NULL_RTX, result_mode, 8803 XEXP (varop, 0), mask); 8804 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, 8805 varop, count); 8806 count = first_count; 8807 code = ASHIFTRT; 8808 continue; 8809 } 8810 8811 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more 8812 than C1 high-order bits equal to the sign bit, we can convert 8813 this to either an ASHIFT or an ASHIFTRT depending on the 8814 two counts. 8815 8816 We cannot do this if VAROP's mode is not SHIFT_MODE. */ 8817 8818 if (code == ASHIFTRT && first_code == ASHIFT 8819 && GET_MODE (varop) == shift_mode 8820 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) 8821 > first_count)) 8822 { 8823 varop = XEXP (varop, 0); 8824 count -= first_count; 8825 if (count < 0) 8826 { 8827 count = -count; 8828 code = ASHIFT; 8829 } 8830 8831 continue; 8832 } 8833 8834 /* There are some cases we can't do. If CODE is ASHIFTRT, 8835 we can only do this if FIRST_CODE is also ASHIFTRT. 8836 8837 We can't do the case when CODE is ROTATE and FIRST_CODE is 8838 ASHIFTRT. 8839 8840 If the mode of this shift is not the mode of the outer shift, 8841 we can't do this if either shift is a right shift or ROTATE. 8842 8843 Finally, we can't do any of these if the mode is too wide 8844 unless the codes are the same. 8845 8846 Handle the case where the shift codes are the same 8847 first. */ 8848 8849 if (code == first_code) 8850 { 8851 if (GET_MODE (varop) != result_mode 8852 && (code == ASHIFTRT || code == LSHIFTRT 8853 || code == ROTATE)) 8854 break; 8855 8856 count += first_count; 8857 varop = XEXP (varop, 0); 8858 continue; 8859 } 8860 8861 if (code == ASHIFTRT 8862 || (code == ROTATE && first_code == ASHIFTRT) 8863 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 8864 || (GET_MODE (varop) != result_mode 8865 && (first_code == ASHIFTRT || first_code == LSHIFTRT 8866 || first_code == ROTATE 8867 || code == ROTATE))) 8868 break; 8869 8870 /* To compute the mask to apply after the shift, shift the 8871 nonzero bits of the inner shift the same way the 8872 outer shift will. */ 8873 8874 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop))); 8875 8876 mask_rtx 8877 = simplify_const_binary_operation (code, result_mode, mask_rtx, 8878 GEN_INT (count)); 8879 8880 /* Give up if we can't compute an outer operation to use. */ 8881 if (mask_rtx == 0 8882 || GET_CODE (mask_rtx) != CONST_INT 8883 || ! merge_outer_ops (&outer_op, &outer_const, AND, 8884 INTVAL (mask_rtx), 8885 result_mode, &complement_p)) 8886 break; 8887 8888 /* If the shifts are in the same direction, we add the 8889 counts. Otherwise, we subtract them. */ 8890 if ((code == ASHIFTRT || code == LSHIFTRT) 8891 == (first_code == ASHIFTRT || first_code == LSHIFTRT)) 8892 count += first_count; 8893 else 8894 count -= first_count; 8895 8896 /* If COUNT is positive, the new shift is usually CODE, 8897 except for the two exceptions below, in which case it is 8898 FIRST_CODE. If the count is negative, FIRST_CODE should 8899 always be used */ 8900 if (count > 0 8901 && ((first_code == ROTATE && code == ASHIFT) 8902 || (first_code == ASHIFTRT && code == LSHIFTRT))) 8903 code = first_code; 8904 else if (count < 0) 8905 code = first_code, count = -count; 8906 8907 varop = XEXP (varop, 0); 8908 continue; 8909 } 8910 8911 /* If we have (A << B << C) for any shift, we can convert this to 8912 (A << C << B). This wins if A is a constant. Only try this if 8913 B is not a constant. */ 8914 8915 else if (GET_CODE (varop) == code 8916 && GET_CODE (XEXP (varop, 0)) == CONST_INT 8917 && GET_CODE (XEXP (varop, 1)) != CONST_INT) 8918 { 8919 rtx new = simplify_const_binary_operation (code, mode, 8920 XEXP (varop, 0), 8921 GEN_INT (count)); 8922 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1)); 8923 count = 0; 8924 continue; 8925 } 8926 break; 8927 8928 case NOT: 8929 /* Make this fit the case below. */ 8930 varop = gen_rtx_XOR (mode, XEXP (varop, 0), 8931 GEN_INT (GET_MODE_MASK (mode))); 8932 continue; 8933 8934 case IOR: 8935 case AND: 8936 case XOR: 8937 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) 8938 with C the size of VAROP - 1 and the shift is logical if 8939 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 8940 we have an (le X 0) operation. If we have an arithmetic shift 8941 and STORE_FLAG_VALUE is 1 or we have a logical shift with 8942 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ 8943 8944 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS 8945 && XEXP (XEXP (varop, 0), 1) == constm1_rtx 8946 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 8947 && (code == LSHIFTRT || code == ASHIFTRT) 8948 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1) 8949 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 8950 { 8951 count = 0; 8952 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1), 8953 const0_rtx); 8954 8955 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 8956 varop = gen_rtx_NEG (GET_MODE (varop), varop); 8957 8958 continue; 8959 } 8960 8961 /* If we have (shift (logical)), move the logical to the outside 8962 to allow it to possibly combine with another logical and the 8963 shift to combine with another shift. This also canonicalizes to 8964 what a ZERO_EXTRACT looks like. Also, some machines have 8965 (and (shift)) insns. */ 8966 8967 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8968 /* We can't do this if we have (ashiftrt (xor)) and the 8969 constant has its sign bit set in shift_mode. */ 8970 && !(code == ASHIFTRT && GET_CODE (varop) == XOR 8971 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), 8972 shift_mode)) 8973 && (new = simplify_const_binary_operation (code, result_mode, 8974 XEXP (varop, 1), 8975 GEN_INT (count))) != 0 8976 && GET_CODE (new) == CONST_INT 8977 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), 8978 INTVAL (new), result_mode, &complement_p)) 8979 { 8980 varop = XEXP (varop, 0); 8981 continue; 8982 } 8983 8984 /* If we can't do that, try to simplify the shift in each arm of the 8985 logical expression, make a new logical expression, and apply 8986 the inverse distributive law. This also can't be done 8987 for some (ashiftrt (xor)). */ 8988 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8989 && !(code == ASHIFTRT && GET_CODE (varop) == XOR 8990 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), 8991 shift_mode))) 8992 { 8993 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, 8994 XEXP (varop, 0), count); 8995 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, 8996 XEXP (varop, 1), count); 8997 8998 varop = simplify_gen_binary (GET_CODE (varop), shift_mode, 8999 lhs, rhs); 9000 varop = apply_distributive_law (varop); 9001 9002 count = 0; 9003 continue; 9004 } 9005 break; 9006 9007 case EQ: 9008 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE 9009 says that the sign bit can be tested, FOO has mode MODE, C is 9010 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit 9011 that may be nonzero. */ 9012 if (code == LSHIFTRT 9013 && XEXP (varop, 1) == const0_rtx 9014 && GET_MODE (XEXP (varop, 0)) == result_mode 9015 && count == (GET_MODE_BITSIZE (result_mode) - 1) 9016 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 9017 && STORE_FLAG_VALUE == -1 9018 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 9019 && merge_outer_ops (&outer_op, &outer_const, XOR, 9020 (HOST_WIDE_INT) 1, result_mode, 9021 &complement_p)) 9022 { 9023 varop = XEXP (varop, 0); 9024 count = 0; 9025 continue; 9026 } 9027 break; 9028 9029 case NEG: 9030 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less 9031 than the number of bits in the mode is equivalent to A. */ 9032 if (code == LSHIFTRT 9033 && count == (GET_MODE_BITSIZE (result_mode) - 1) 9034 && nonzero_bits (XEXP (varop, 0), result_mode) == 1) 9035 { 9036 varop = XEXP (varop, 0); 9037 count = 0; 9038 continue; 9039 } 9040 9041 /* NEG commutes with ASHIFT since it is multiplication. Move the 9042 NEG outside to allow shifts to combine. */ 9043 if (code == ASHIFT 9044 && merge_outer_ops (&outer_op, &outer_const, NEG, 9045 (HOST_WIDE_INT) 0, result_mode, 9046 &complement_p)) 9047 { 9048 varop = XEXP (varop, 0); 9049 continue; 9050 } 9051 break; 9052 9053 case PLUS: 9054 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C 9055 is one less than the number of bits in the mode is 9056 equivalent to (xor A 1). */ 9057 if (code == LSHIFTRT 9058 && count == (GET_MODE_BITSIZE (result_mode) - 1) 9059 && XEXP (varop, 1) == constm1_rtx 9060 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 9061 && merge_outer_ops (&outer_op, &outer_const, XOR, 9062 (HOST_WIDE_INT) 1, result_mode, 9063 &complement_p)) 9064 { 9065 count = 0; 9066 varop = XEXP (varop, 0); 9067 continue; 9068 } 9069 9070 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits 9071 that might be nonzero in BAR are those being shifted out and those 9072 bits are known zero in FOO, we can replace the PLUS with FOO. 9073 Similarly in the other operand order. This code occurs when 9074 we are computing the size of a variable-size array. */ 9075 9076 if ((code == ASHIFTRT || code == LSHIFTRT) 9077 && count < HOST_BITS_PER_WIDE_INT 9078 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 9079 && (nonzero_bits (XEXP (varop, 1), result_mode) 9080 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) 9081 { 9082 varop = XEXP (varop, 0); 9083 continue; 9084 } 9085 else if ((code == ASHIFTRT || code == LSHIFTRT) 9086 && count < HOST_BITS_PER_WIDE_INT 9087 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 9088 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 9089 >> count) 9090 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 9091 & nonzero_bits (XEXP (varop, 1), 9092 result_mode))) 9093 { 9094 varop = XEXP (varop, 1); 9095 continue; 9096 } 9097 9098 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ 9099 if (code == ASHIFT 9100 && GET_CODE (XEXP (varop, 1)) == CONST_INT 9101 && (new = simplify_const_binary_operation (ASHIFT, result_mode, 9102 XEXP (varop, 1), 9103 GEN_INT (count))) != 0 9104 && GET_CODE (new) == CONST_INT 9105 && merge_outer_ops (&outer_op, &outer_const, PLUS, 9106 INTVAL (new), result_mode, &complement_p)) 9107 { 9108 varop = XEXP (varop, 0); 9109 continue; 9110 } 9111 9112 /* Check for 'PLUS signbit', which is the canonical form of 'XOR 9113 signbit', and attempt to change the PLUS to an XOR and move it to 9114 the outer operation as is done above in the AND/IOR/XOR case 9115 leg for shift(logical). See details in logical handling above 9116 for reasoning in doing so. */ 9117 if (code == LSHIFTRT 9118 && GET_CODE (XEXP (varop, 1)) == CONST_INT 9119 && mode_signbit_p (result_mode, XEXP (varop, 1)) 9120 && (new = simplify_const_binary_operation (code, result_mode, 9121 XEXP (varop, 1), 9122 GEN_INT (count))) != 0 9123 && GET_CODE (new) == CONST_INT 9124 && merge_outer_ops (&outer_op, &outer_const, XOR, 9125 INTVAL (new), result_mode, &complement_p)) 9126 { 9127 varop = XEXP (varop, 0); 9128 continue; 9129 } 9130 9131 break; 9132 9133 case MINUS: 9134 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) 9135 with C the size of VAROP - 1 and the shift is logical if 9136 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 9137 we have a (gt X 0) operation. If the shift is arithmetic with 9138 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, 9139 we have a (neg (gt X 0)) operation. */ 9140 9141 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 9142 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT 9143 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1) 9144 && (code == LSHIFTRT || code == ASHIFTRT) 9145 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT 9146 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count 9147 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 9148 { 9149 count = 0; 9150 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1), 9151 const0_rtx); 9152 9153 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 9154 varop = gen_rtx_NEG (GET_MODE (varop), varop); 9155 9156 continue; 9157 } 9158 break; 9159 9160 case TRUNCATE: 9161 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) 9162 if the truncate does not affect the value. */ 9163 if (code == LSHIFTRT 9164 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT 9165 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT 9166 && (INTVAL (XEXP (XEXP (varop, 0), 1)) 9167 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0))) 9168 - GET_MODE_BITSIZE (GET_MODE (varop))))) 9169 { 9170 rtx varop_inner = XEXP (varop, 0); 9171 9172 varop_inner 9173 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner), 9174 XEXP (varop_inner, 0), 9175 GEN_INT 9176 (count + INTVAL (XEXP (varop_inner, 1)))); 9177 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner); 9178 count = 0; 9179 continue; 9180 } 9181 break; 9182 9183 default: 9184 break; 9185 } 9186 9187 break; 9188 } 9189 9190 /* We need to determine what mode to do the shift in. If the shift is 9191 a right shift or ROTATE, we must always do it in the mode it was 9192 originally done in. Otherwise, we can do it in MODE, the widest mode 9193 encountered. The code we care about is that of the shift that will 9194 actually be done, not the shift that was originally requested. */ 9195 shift_mode 9196 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE 9197 ? result_mode : mode); 9198 9199 /* We have now finished analyzing the shift. The result should be 9200 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If 9201 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied 9202 to the result of the shift. OUTER_CONST is the relevant constant, 9203 but we must turn off all bits turned off in the shift. */ 9204 9205 if (outer_op == UNKNOWN 9206 && orig_code == code && orig_count == count 9207 && varop == orig_varop 9208 && shift_mode == GET_MODE (varop)) 9209 return NULL_RTX; 9210 9211 /* Make a SUBREG if necessary. If we can't make it, fail. */ 9212 varop = gen_lowpart (shift_mode, varop); 9213 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER) 9214 return NULL_RTX; 9215 9216 /* If we have an outer operation and we just made a shift, it is 9217 possible that we could have simplified the shift were it not 9218 for the outer operation. So try to do the simplification 9219 recursively. */ 9220 9221 if (outer_op != UNKNOWN) 9222 x = simplify_shift_const_1 (code, shift_mode, varop, count); 9223 else 9224 x = NULL_RTX; 9225 9226 if (x == NULL_RTX) 9227 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count)); 9228 9229 /* If we were doing an LSHIFTRT in a wider mode than it was originally, 9230 turn off all the bits that the shift would have turned off. */ 9231 if (orig_code == LSHIFTRT && result_mode != shift_mode) 9232 x = simplify_and_const_int (NULL_RTX, shift_mode, x, 9233 GET_MODE_MASK (result_mode) >> orig_count); 9234 9235 /* Do the remainder of the processing in RESULT_MODE. */ 9236 x = gen_lowpart_or_truncate (result_mode, x); 9237 9238 /* If COMPLEMENT_P is set, we have to complement X before doing the outer 9239 operation. */ 9240 if (complement_p) 9241 x = simplify_gen_unary (NOT, result_mode, x, result_mode); 9242 9243 if (outer_op != UNKNOWN) 9244 { 9245 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT) 9246 outer_const = trunc_int_for_mode (outer_const, result_mode); 9247 9248 if (outer_op == AND) 9249 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); 9250 else if (outer_op == SET) 9251 { 9252 /* This means that we have determined that the result is 9253 equivalent to a constant. This should be rare. */ 9254 if (!side_effects_p (x)) 9255 x = GEN_INT (outer_const); 9256 } 9257 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY) 9258 x = simplify_gen_unary (outer_op, result_mode, x, result_mode); 9259 else 9260 x = simplify_gen_binary (outer_op, result_mode, x, 9261 GEN_INT (outer_const)); 9262 } 9263 9264 return x; 9265} 9266 9267/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. 9268 The result of the shift is RESULT_MODE. If we cannot simplify it, 9269 return X or, if it is NULL, synthesize the expression with 9270 simplify_gen_binary. Otherwise, return a simplified value. 9271 9272 The shift is normally computed in the widest mode we find in VAROP, as 9273 long as it isn't a different number of words than RESULT_MODE. Exceptions 9274 are ASHIFTRT and ROTATE, which are always done in their original mode. */ 9275 9276static rtx 9277simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode, 9278 rtx varop, int count) 9279{ 9280 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count); 9281 if (tem) 9282 return tem; 9283 9284 if (!x) 9285 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count)); 9286 if (GET_MODE (x) != result_mode) 9287 x = gen_lowpart (result_mode, x); 9288 return x; 9289} 9290 9291 9292/* Like recog, but we receive the address of a pointer to a new pattern. 9293 We try to match the rtx that the pointer points to. 9294 If that fails, we may try to modify or replace the pattern, 9295 storing the replacement into the same pointer object. 9296 9297 Modifications include deletion or addition of CLOBBERs. 9298 9299 PNOTES is a pointer to a location where any REG_UNUSED notes added for 9300 the CLOBBERs are placed. 9301 9302 The value is the final insn code from the pattern ultimately matched, 9303 or -1. */ 9304 9305static int 9306recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes) 9307{ 9308 rtx pat = *pnewpat; 9309 int insn_code_number; 9310 int num_clobbers_to_add = 0; 9311 int i; 9312 rtx notes = 0; 9313 rtx old_notes, old_pat; 9314 9315 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER 9316 we use to indicate that something didn't match. If we find such a 9317 thing, force rejection. */ 9318 if (GET_CODE (pat) == PARALLEL) 9319 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) 9320 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER 9321 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) 9322 return -1; 9323 9324 old_pat = PATTERN (insn); 9325 old_notes = REG_NOTES (insn); 9326 PATTERN (insn) = pat; 9327 REG_NOTES (insn) = 0; 9328 9329 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 9330 9331 /* If it isn't, there is the possibility that we previously had an insn 9332 that clobbered some register as a side effect, but the combined 9333 insn doesn't need to do that. So try once more without the clobbers 9334 unless this represents an ASM insn. */ 9335 9336 if (insn_code_number < 0 && ! check_asm_operands (pat) 9337 && GET_CODE (pat) == PARALLEL) 9338 { 9339 int pos; 9340 9341 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) 9342 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) 9343 { 9344 if (i != pos) 9345 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); 9346 pos++; 9347 } 9348 9349 SUBST_INT (XVECLEN (pat, 0), pos); 9350 9351 if (pos == 1) 9352 pat = XVECEXP (pat, 0, 0); 9353 9354 PATTERN (insn) = pat; 9355 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 9356 } 9357 PATTERN (insn) = old_pat; 9358 REG_NOTES (insn) = old_notes; 9359 9360 /* Recognize all noop sets, these will be killed by followup pass. */ 9361 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat)) 9362 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0; 9363 9364 /* If we had any clobbers to add, make a new pattern than contains 9365 them. Then check to make sure that all of them are dead. */ 9366 if (num_clobbers_to_add) 9367 { 9368 rtx newpat = gen_rtx_PARALLEL (VOIDmode, 9369 rtvec_alloc (GET_CODE (pat) == PARALLEL 9370 ? (XVECLEN (pat, 0) 9371 + num_clobbers_to_add) 9372 : num_clobbers_to_add + 1)); 9373 9374 if (GET_CODE (pat) == PARALLEL) 9375 for (i = 0; i < XVECLEN (pat, 0); i++) 9376 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); 9377 else 9378 XVECEXP (newpat, 0, 0) = pat; 9379 9380 add_clobbers (newpat, insn_code_number); 9381 9382 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; 9383 i < XVECLEN (newpat, 0); i++) 9384 { 9385 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)) 9386 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) 9387 return -1; 9388 notes = gen_rtx_EXPR_LIST (REG_UNUSED, 9389 XEXP (XVECEXP (newpat, 0, i), 0), notes); 9390 } 9391 pat = newpat; 9392 } 9393 9394 *pnewpat = pat; 9395 *pnotes = notes; 9396 9397 return insn_code_number; 9398} 9399 9400/* Like gen_lowpart_general but for use by combine. In combine it 9401 is not possible to create any new pseudoregs. However, it is 9402 safe to create invalid memory addresses, because combine will 9403 try to recognize them and all they will do is make the combine 9404 attempt fail. 9405 9406 If for some reason this cannot do its job, an rtx 9407 (clobber (const_int 0)) is returned. 9408 An insn containing that will not be recognized. */ 9409 9410static rtx 9411gen_lowpart_for_combine (enum machine_mode omode, rtx x) 9412{ 9413 enum machine_mode imode = GET_MODE (x); 9414 unsigned int osize = GET_MODE_SIZE (omode); 9415 unsigned int isize = GET_MODE_SIZE (imode); 9416 rtx result; 9417 9418 if (omode == imode) 9419 return x; 9420 9421 /* Return identity if this is a CONST or symbolic reference. */ 9422 if (omode == Pmode 9423 && (GET_CODE (x) == CONST 9424 || GET_CODE (x) == SYMBOL_REF 9425 || GET_CODE (x) == LABEL_REF)) 9426 return x; 9427 9428 /* We can only support MODE being wider than a word if X is a 9429 constant integer or has a mode the same size. */ 9430 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD 9431 && ! ((imode == VOIDmode 9432 && (GET_CODE (x) == CONST_INT 9433 || GET_CODE (x) == CONST_DOUBLE)) 9434 || isize == osize)) 9435 goto fail; 9436 9437 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart 9438 won't know what to do. So we will strip off the SUBREG here and 9439 process normally. */ 9440 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x))) 9441 { 9442 x = SUBREG_REG (x); 9443 9444 /* For use in case we fall down into the address adjustments 9445 further below, we need to adjust the known mode and size of 9446 x; imode and isize, since we just adjusted x. */ 9447 imode = GET_MODE (x); 9448 9449 if (imode == omode) 9450 return x; 9451 9452 isize = GET_MODE_SIZE (imode); 9453 } 9454 9455 result = gen_lowpart_common (omode, x); 9456 9457#ifdef CANNOT_CHANGE_MODE_CLASS 9458 if (result != 0 && GET_CODE (result) == SUBREG) 9459 record_subregs_of_mode (result); 9460#endif 9461 9462 if (result) 9463 return result; 9464 9465 if (MEM_P (x)) 9466 { 9467 int offset = 0; 9468 9469 /* Refuse to work on a volatile memory ref or one with a mode-dependent 9470 address. */ 9471 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0))) 9472 goto fail; 9473 9474 /* If we want to refer to something bigger than the original memref, 9475 generate a paradoxical subreg instead. That will force a reload 9476 of the original memref X. */ 9477 if (isize < osize) 9478 return gen_rtx_SUBREG (omode, x, 0); 9479 9480 if (WORDS_BIG_ENDIAN) 9481 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD); 9482 9483 /* Adjust the address so that the address-after-the-data is 9484 unchanged. */ 9485 if (BYTES_BIG_ENDIAN) 9486 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize); 9487 9488 return adjust_address_nv (x, omode, offset); 9489 } 9490 9491 /* If X is a comparison operator, rewrite it in a new mode. This 9492 probably won't match, but may allow further simplifications. */ 9493 else if (COMPARISON_P (x)) 9494 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1)); 9495 9496 /* If we couldn't simplify X any other way, just enclose it in a 9497 SUBREG. Normally, this SUBREG won't match, but some patterns may 9498 include an explicit SUBREG or we may simplify it further in combine. */ 9499 else 9500 { 9501 int offset = 0; 9502 rtx res; 9503 9504 offset = subreg_lowpart_offset (omode, imode); 9505 if (imode == VOIDmode) 9506 { 9507 imode = int_mode_for_mode (omode); 9508 x = gen_lowpart_common (imode, x); 9509 if (x == NULL) 9510 goto fail; 9511 } 9512 res = simplify_gen_subreg (omode, x, imode, offset); 9513 if (res) 9514 return res; 9515 } 9516 9517 fail: 9518 return gen_rtx_CLOBBER (imode, const0_rtx); 9519} 9520 9521/* Simplify a comparison between *POP0 and *POP1 where CODE is the 9522 comparison code that will be tested. 9523 9524 The result is a possibly different comparison code to use. *POP0 and 9525 *POP1 may be updated. 9526 9527 It is possible that we might detect that a comparison is either always 9528 true or always false. However, we do not perform general constant 9529 folding in combine, so this knowledge isn't useful. Such tautologies 9530 should have been detected earlier. Hence we ignore all such cases. */ 9531 9532static enum rtx_code 9533simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) 9534{ 9535 rtx op0 = *pop0; 9536 rtx op1 = *pop1; 9537 rtx tem, tem1; 9538 int i; 9539 enum machine_mode mode, tmode; 9540 9541 /* Try a few ways of applying the same transformation to both operands. */ 9542 while (1) 9543 { 9544#ifndef WORD_REGISTER_OPERATIONS 9545 /* The test below this one won't handle SIGN_EXTENDs on these machines, 9546 so check specially. */ 9547 if (code != GTU && code != GEU && code != LTU && code != LEU 9548 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT 9549 && GET_CODE (XEXP (op0, 0)) == ASHIFT 9550 && GET_CODE (XEXP (op1, 0)) == ASHIFT 9551 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG 9552 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG 9553 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) 9554 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) 9555 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9556 && XEXP (op0, 1) == XEXP (op1, 1) 9557 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 9558 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1) 9559 && (INTVAL (XEXP (op0, 1)) 9560 == (GET_MODE_BITSIZE (GET_MODE (op0)) 9561 - (GET_MODE_BITSIZE 9562 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) 9563 { 9564 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); 9565 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); 9566 } 9567#endif 9568 9569 /* If both operands are the same constant shift, see if we can ignore the 9570 shift. We can if the shift is a rotate or if the bits shifted out of 9571 this shift are known to be zero for both inputs and if the type of 9572 comparison is compatible with the shift. */ 9573 if (GET_CODE (op0) == GET_CODE (op1) 9574 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 9575 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) 9576 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) 9577 && (code != GT && code != LT && code != GE && code != LE)) 9578 || (GET_CODE (op0) == ASHIFTRT 9579 && (code != GTU && code != LTU 9580 && code != GEU && code != LEU))) 9581 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9582 && INTVAL (XEXP (op0, 1)) >= 0 9583 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 9584 && XEXP (op0, 1) == XEXP (op1, 1)) 9585 { 9586 enum machine_mode mode = GET_MODE (op0); 9587 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 9588 int shift_count = INTVAL (XEXP (op0, 1)); 9589 9590 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) 9591 mask &= (mask >> shift_count) << shift_count; 9592 else if (GET_CODE (op0) == ASHIFT) 9593 mask = (mask & (mask << shift_count)) >> shift_count; 9594 9595 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0 9596 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0) 9597 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); 9598 else 9599 break; 9600 } 9601 9602 /* If both operands are AND's of a paradoxical SUBREG by constant, the 9603 SUBREGs are of the same mode, and, in both cases, the AND would 9604 be redundant if the comparison was done in the narrower mode, 9605 do the comparison in the narrower mode (e.g., we are AND'ing with 1 9606 and the operand's possibly nonzero bits are 0xffffff01; in that case 9607 if we only care about QImode, we don't need the AND). This case 9608 occurs if the output mode of an scc insn is not SImode and 9609 STORE_FLAG_VALUE == 1 (e.g., the 386). 9610 9611 Similarly, check for a case where the AND's are ZERO_EXTEND 9612 operations from some narrower mode even though a SUBREG is not 9613 present. */ 9614 9615 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND 9616 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9617 && GET_CODE (XEXP (op1, 1)) == CONST_INT) 9618 { 9619 rtx inner_op0 = XEXP (op0, 0); 9620 rtx inner_op1 = XEXP (op1, 0); 9621 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); 9622 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); 9623 int changed = 0; 9624 9625 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG 9626 && (GET_MODE_SIZE (GET_MODE (inner_op0)) 9627 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0)))) 9628 && (GET_MODE (SUBREG_REG (inner_op0)) 9629 == GET_MODE (SUBREG_REG (inner_op1))) 9630 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0))) 9631 <= HOST_BITS_PER_WIDE_INT) 9632 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), 9633 GET_MODE (SUBREG_REG (inner_op0))))) 9634 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), 9635 GET_MODE (SUBREG_REG (inner_op1)))))) 9636 { 9637 op0 = SUBREG_REG (inner_op0); 9638 op1 = SUBREG_REG (inner_op1); 9639 9640 /* The resulting comparison is always unsigned since we masked 9641 off the original sign bit. */ 9642 code = unsigned_condition (code); 9643 9644 changed = 1; 9645 } 9646 9647 else if (c0 == c1) 9648 for (tmode = GET_CLASS_NARROWEST_MODE 9649 (GET_MODE_CLASS (GET_MODE (op0))); 9650 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) 9651 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) 9652 { 9653 op0 = gen_lowpart (tmode, inner_op0); 9654 op1 = gen_lowpart (tmode, inner_op1); 9655 code = unsigned_condition (code); 9656 changed = 1; 9657 break; 9658 } 9659 9660 if (! changed) 9661 break; 9662 } 9663 9664 /* If both operands are NOT, we can strip off the outer operation 9665 and adjust the comparison code for swapped operands; similarly for 9666 NEG, except that this must be an equality comparison. */ 9667 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) 9668 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG 9669 && (code == EQ || code == NE))) 9670 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); 9671 9672 else 9673 break; 9674 } 9675 9676 /* If the first operand is a constant, swap the operands and adjust the 9677 comparison code appropriately, but don't do this if the second operand 9678 is already a constant integer. */ 9679 if (swap_commutative_operands_p (op0, op1)) 9680 { 9681 tem = op0, op0 = op1, op1 = tem; 9682 code = swap_condition (code); 9683 } 9684 9685 /* We now enter a loop during which we will try to simplify the comparison. 9686 For the most part, we only are concerned with comparisons with zero, 9687 but some things may really be comparisons with zero but not start 9688 out looking that way. */ 9689 9690 while (GET_CODE (op1) == CONST_INT) 9691 { 9692 enum machine_mode mode = GET_MODE (op0); 9693 unsigned int mode_width = GET_MODE_BITSIZE (mode); 9694 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 9695 int equality_comparison_p; 9696 int sign_bit_comparison_p; 9697 int unsigned_comparison_p; 9698 HOST_WIDE_INT const_op; 9699 9700 /* We only want to handle integral modes. This catches VOIDmode, 9701 CCmode, and the floating-point modes. An exception is that we 9702 can handle VOIDmode if OP0 is a COMPARE or a comparison 9703 operation. */ 9704 9705 if (GET_MODE_CLASS (mode) != MODE_INT 9706 && ! (mode == VOIDmode 9707 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0)))) 9708 break; 9709 9710 /* Get the constant we are comparing against and turn off all bits 9711 not on in our mode. */ 9712 const_op = INTVAL (op1); 9713 if (mode != VOIDmode) 9714 const_op = trunc_int_for_mode (const_op, mode); 9715 op1 = GEN_INT (const_op); 9716 9717 /* If we are comparing against a constant power of two and the value 9718 being compared can only have that single bit nonzero (e.g., it was 9719 `and'ed with that bit), we can replace this with a comparison 9720 with zero. */ 9721 if (const_op 9722 && (code == EQ || code == NE || code == GE || code == GEU 9723 || code == LT || code == LTU) 9724 && mode_width <= HOST_BITS_PER_WIDE_INT 9725 && exact_log2 (const_op) >= 0 9726 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op) 9727 { 9728 code = (code == EQ || code == GE || code == GEU ? NE : EQ); 9729 op1 = const0_rtx, const_op = 0; 9730 } 9731 9732 /* Similarly, if we are comparing a value known to be either -1 or 9733 0 with -1, change it to the opposite comparison against zero. */ 9734 9735 if (const_op == -1 9736 && (code == EQ || code == NE || code == GT || code == LE 9737 || code == GEU || code == LTU) 9738 && num_sign_bit_copies (op0, mode) == mode_width) 9739 { 9740 code = (code == EQ || code == LE || code == GEU ? NE : EQ); 9741 op1 = const0_rtx, const_op = 0; 9742 } 9743 9744 /* Do some canonicalizations based on the comparison code. We prefer 9745 comparisons against zero and then prefer equality comparisons. 9746 If we can reduce the size of a constant, we will do that too. */ 9747 9748 switch (code) 9749 { 9750 case LT: 9751 /* < C is equivalent to <= (C - 1) */ 9752 if (const_op > 0) 9753 { 9754 const_op -= 1; 9755 op1 = GEN_INT (const_op); 9756 code = LE; 9757 /* ... fall through to LE case below. */ 9758 } 9759 else 9760 break; 9761 9762 case LE: 9763 /* <= C is equivalent to < (C + 1); we do this for C < 0 */ 9764 if (const_op < 0) 9765 { 9766 const_op += 1; 9767 op1 = GEN_INT (const_op); 9768 code = LT; 9769 } 9770 9771 /* If we are doing a <= 0 comparison on a value known to have 9772 a zero sign bit, we can replace this with == 0. */ 9773 else if (const_op == 0 9774 && mode_width <= HOST_BITS_PER_WIDE_INT 9775 && (nonzero_bits (op0, mode) 9776 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) 9777 code = EQ; 9778 break; 9779 9780 case GE: 9781 /* >= C is equivalent to > (C - 1). */ 9782 if (const_op > 0) 9783 { 9784 const_op -= 1; 9785 op1 = GEN_INT (const_op); 9786 code = GT; 9787 /* ... fall through to GT below. */ 9788 } 9789 else 9790 break; 9791 9792 case GT: 9793 /* > C is equivalent to >= (C + 1); we do this for C < 0. */ 9794 if (const_op < 0) 9795 { 9796 const_op += 1; 9797 op1 = GEN_INT (const_op); 9798 code = GE; 9799 } 9800 9801 /* If we are doing a > 0 comparison on a value known to have 9802 a zero sign bit, we can replace this with != 0. */ 9803 else if (const_op == 0 9804 && mode_width <= HOST_BITS_PER_WIDE_INT 9805 && (nonzero_bits (op0, mode) 9806 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) 9807 code = NE; 9808 break; 9809 9810 case LTU: 9811 /* < C is equivalent to <= (C - 1). */ 9812 if (const_op > 0) 9813 { 9814 const_op -= 1; 9815 op1 = GEN_INT (const_op); 9816 code = LEU; 9817 /* ... fall through ... */ 9818 } 9819 9820 /* (unsigned) < 0x80000000 is equivalent to >= 0. */ 9821 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 9822 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) 9823 { 9824 const_op = 0, op1 = const0_rtx; 9825 code = GE; 9826 break; 9827 } 9828 else 9829 break; 9830 9831 case LEU: 9832 /* unsigned <= 0 is equivalent to == 0 */ 9833 if (const_op == 0) 9834 code = EQ; 9835 9836 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ 9837 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 9838 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) 9839 { 9840 const_op = 0, op1 = const0_rtx; 9841 code = GE; 9842 } 9843 break; 9844 9845 case GEU: 9846 /* >= C is equivalent to > (C - 1). */ 9847 if (const_op > 1) 9848 { 9849 const_op -= 1; 9850 op1 = GEN_INT (const_op); 9851 code = GTU; 9852 /* ... fall through ... */ 9853 } 9854 9855 /* (unsigned) >= 0x80000000 is equivalent to < 0. */ 9856 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 9857 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) 9858 { 9859 const_op = 0, op1 = const0_rtx; 9860 code = LT; 9861 break; 9862 } 9863 else 9864 break; 9865 9866 case GTU: 9867 /* unsigned > 0 is equivalent to != 0 */ 9868 if (const_op == 0) 9869 code = NE; 9870 9871 /* (unsigned) > 0x7fffffff is equivalent to < 0. */ 9872 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 9873 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) 9874 { 9875 const_op = 0, op1 = const0_rtx; 9876 code = LT; 9877 } 9878 break; 9879 9880 default: 9881 break; 9882 } 9883 9884 /* Compute some predicates to simplify code below. */ 9885 9886 equality_comparison_p = (code == EQ || code == NE); 9887 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); 9888 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU 9889 || code == GEU); 9890 9891 /* If this is a sign bit comparison and we can do arithmetic in 9892 MODE, say that we will only be needing the sign bit of OP0. */ 9893 if (sign_bit_comparison_p 9894 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 9895 op0 = force_to_mode (op0, mode, 9896 ((HOST_WIDE_INT) 1 9897 << (GET_MODE_BITSIZE (mode) - 1)), 9898 0); 9899 9900 /* Now try cases based on the opcode of OP0. If none of the cases 9901 does a "continue", we exit this loop immediately after the 9902 switch. */ 9903 9904 switch (GET_CODE (op0)) 9905 { 9906 case ZERO_EXTRACT: 9907 /* If we are extracting a single bit from a variable position in 9908 a constant that has only a single bit set and are comparing it 9909 with zero, we can convert this into an equality comparison 9910 between the position and the location of the single bit. */ 9911 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might 9912 have already reduced the shift count modulo the word size. */ 9913 if (!SHIFT_COUNT_TRUNCATED 9914 && GET_CODE (XEXP (op0, 0)) == CONST_INT 9915 && XEXP (op0, 1) == const1_rtx 9916 && equality_comparison_p && const_op == 0 9917 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0) 9918 { 9919 if (BITS_BIG_ENDIAN) 9920 { 9921 enum machine_mode new_mode 9922 = mode_for_extraction (EP_extzv, 1); 9923 if (new_mode == MAX_MACHINE_MODE) 9924 i = BITS_PER_WORD - 1 - i; 9925 else 9926 { 9927 mode = new_mode; 9928 i = (GET_MODE_BITSIZE (mode) - 1 - i); 9929 } 9930 } 9931 9932 op0 = XEXP (op0, 2); 9933 op1 = GEN_INT (i); 9934 const_op = i; 9935 9936 /* Result is nonzero iff shift count is equal to I. */ 9937 code = reverse_condition (code); 9938 continue; 9939 } 9940 9941 /* ... fall through ... */ 9942 9943 case SIGN_EXTRACT: 9944 tem = expand_compound_operation (op0); 9945 if (tem != op0) 9946 { 9947 op0 = tem; 9948 continue; 9949 } 9950 break; 9951 9952 case NOT: 9953 /* If testing for equality, we can take the NOT of the constant. */ 9954 if (equality_comparison_p 9955 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) 9956 { 9957 op0 = XEXP (op0, 0); 9958 op1 = tem; 9959 continue; 9960 } 9961 9962 /* If just looking at the sign bit, reverse the sense of the 9963 comparison. */ 9964 if (sign_bit_comparison_p) 9965 { 9966 op0 = XEXP (op0, 0); 9967 code = (code == GE ? LT : GE); 9968 continue; 9969 } 9970 break; 9971 9972 case NEG: 9973 /* If testing for equality, we can take the NEG of the constant. */ 9974 if (equality_comparison_p 9975 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) 9976 { 9977 op0 = XEXP (op0, 0); 9978 op1 = tem; 9979 continue; 9980 } 9981 9982 /* The remaining cases only apply to comparisons with zero. */ 9983 if (const_op != 0) 9984 break; 9985 9986 /* When X is ABS or is known positive, 9987 (neg X) is < 0 if and only if X != 0. */ 9988 9989 if (sign_bit_comparison_p 9990 && (GET_CODE (XEXP (op0, 0)) == ABS 9991 || (mode_width <= HOST_BITS_PER_WIDE_INT 9992 && (nonzero_bits (XEXP (op0, 0), mode) 9993 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0))) 9994 { 9995 op0 = XEXP (op0, 0); 9996 code = (code == LT ? NE : EQ); 9997 continue; 9998 } 9999 10000 /* If we have NEG of something whose two high-order bits are the 10001 same, we know that "(-a) < 0" is equivalent to "a > 0". */ 10002 if (num_sign_bit_copies (op0, mode) >= 2) 10003 { 10004 op0 = XEXP (op0, 0); 10005 code = swap_condition (code); 10006 continue; 10007 } 10008 break; 10009 10010 case ROTATE: 10011 /* If we are testing equality and our count is a constant, we 10012 can perform the inverse operation on our RHS. */ 10013 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT 10014 && (tem = simplify_binary_operation (ROTATERT, mode, 10015 op1, XEXP (op0, 1))) != 0) 10016 { 10017 op0 = XEXP (op0, 0); 10018 op1 = tem; 10019 continue; 10020 } 10021 10022 /* If we are doing a < 0 or >= 0 comparison, it means we are testing 10023 a particular bit. Convert it to an AND of a constant of that 10024 bit. This will be converted into a ZERO_EXTRACT. */ 10025 if (const_op == 0 && sign_bit_comparison_p 10026 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10027 && mode_width <= HOST_BITS_PER_WIDE_INT) 10028 { 10029 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10030 ((HOST_WIDE_INT) 1 10031 << (mode_width - 1 10032 - INTVAL (XEXP (op0, 1))))); 10033 code = (code == LT ? NE : EQ); 10034 continue; 10035 } 10036 10037 /* Fall through. */ 10038 10039 case ABS: 10040 /* ABS is ignorable inside an equality comparison with zero. */ 10041 if (const_op == 0 && equality_comparison_p) 10042 { 10043 op0 = XEXP (op0, 0); 10044 continue; 10045 } 10046 break; 10047 10048 case SIGN_EXTEND: 10049 /* Can simplify (compare (zero/sign_extend FOO) CONST) to 10050 (compare FOO CONST) if CONST fits in FOO's mode and we 10051 are either testing inequality or have an unsigned 10052 comparison with ZERO_EXTEND or a signed comparison with 10053 SIGN_EXTEND. But don't do it if we don't have a compare 10054 insn of the given mode, since we'd have to revert it 10055 later on, and then we wouldn't know whether to sign- or 10056 zero-extend. */ 10057 mode = GET_MODE (XEXP (op0, 0)); 10058 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT 10059 && ! unsigned_comparison_p 10060 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 10061 && ((unsigned HOST_WIDE_INT) const_op 10062 < (((unsigned HOST_WIDE_INT) 1 10063 << (GET_MODE_BITSIZE (mode) - 1)))) 10064 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) 10065 { 10066 op0 = XEXP (op0, 0); 10067 continue; 10068 } 10069 break; 10070 10071 case SUBREG: 10072 /* Check for the case where we are comparing A - C1 with C2, that is 10073 10074 (subreg:MODE (plus (A) (-C1))) op (C2) 10075 10076 with C1 a constant, and try to lift the SUBREG, i.e. to do the 10077 comparison in the wider mode. One of the following two conditions 10078 must be true in order for this to be valid: 10079 10080 1. The mode extension results in the same bit pattern being added 10081 on both sides and the comparison is equality or unsigned. As 10082 C2 has been truncated to fit in MODE, the pattern can only be 10083 all 0s or all 1s. 10084 10085 2. The mode extension results in the sign bit being copied on 10086 each side. 10087 10088 The difficulty here is that we have predicates for A but not for 10089 (A - C1) so we need to check that C1 is within proper bounds so 10090 as to perturbate A as little as possible. */ 10091 10092 if (mode_width <= HOST_BITS_PER_WIDE_INT 10093 && subreg_lowpart_p (op0) 10094 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width 10095 && GET_CODE (SUBREG_REG (op0)) == PLUS 10096 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT) 10097 { 10098 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); 10099 rtx a = XEXP (SUBREG_REG (op0), 0); 10100 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1)); 10101 10102 if ((c1 > 0 10103 && (unsigned HOST_WIDE_INT) c1 10104 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1) 10105 && (equality_comparison_p || unsigned_comparison_p) 10106 /* (A - C1) zero-extends if it is positive and sign-extends 10107 if it is negative, C2 both zero- and sign-extends. */ 10108 && ((0 == (nonzero_bits (a, inner_mode) 10109 & ~GET_MODE_MASK (mode)) 10110 && const_op >= 0) 10111 /* (A - C1) sign-extends if it is positive and 1-extends 10112 if it is negative, C2 both sign- and 1-extends. */ 10113 || (num_sign_bit_copies (a, inner_mode) 10114 > (unsigned int) (GET_MODE_BITSIZE (inner_mode) 10115 - mode_width) 10116 && const_op < 0))) 10117 || ((unsigned HOST_WIDE_INT) c1 10118 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2) 10119 /* (A - C1) always sign-extends, like C2. */ 10120 && num_sign_bit_copies (a, inner_mode) 10121 > (unsigned int) (GET_MODE_BITSIZE (inner_mode) 10122 - (mode_width - 1)))) 10123 { 10124 op0 = SUBREG_REG (op0); 10125 continue; 10126 } 10127 } 10128 10129 /* If the inner mode is narrower and we are extracting the low part, 10130 we can treat the SUBREG as if it were a ZERO_EXTEND. */ 10131 if (subreg_lowpart_p (op0) 10132 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width) 10133 /* Fall through */ ; 10134 else 10135 break; 10136 10137 /* ... fall through ... */ 10138 10139 case ZERO_EXTEND: 10140 mode = GET_MODE (XEXP (op0, 0)); 10141 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT 10142 && (unsigned_comparison_p || equality_comparison_p) 10143 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 10144 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode)) 10145 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) 10146 { 10147 op0 = XEXP (op0, 0); 10148 continue; 10149 } 10150 break; 10151 10152 case PLUS: 10153 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do 10154 this for equality comparisons due to pathological cases involving 10155 overflows. */ 10156 if (equality_comparison_p 10157 && 0 != (tem = simplify_binary_operation (MINUS, mode, 10158 op1, XEXP (op0, 1)))) 10159 { 10160 op0 = XEXP (op0, 0); 10161 op1 = tem; 10162 continue; 10163 } 10164 10165 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ 10166 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx 10167 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) 10168 { 10169 op0 = XEXP (XEXP (op0, 0), 0); 10170 code = (code == LT ? EQ : NE); 10171 continue; 10172 } 10173 break; 10174 10175 case MINUS: 10176 /* We used to optimize signed comparisons against zero, but that 10177 was incorrect. Unsigned comparisons against zero (GTU, LEU) 10178 arrive here as equality comparisons, or (GEU, LTU) are 10179 optimized away. No need to special-case them. */ 10180 10181 /* (eq (minus A B) C) -> (eq A (plus B C)) or 10182 (eq B (minus A C)), whichever simplifies. We can only do 10183 this for equality comparisons due to pathological cases involving 10184 overflows. */ 10185 if (equality_comparison_p 10186 && 0 != (tem = simplify_binary_operation (PLUS, mode, 10187 XEXP (op0, 1), op1))) 10188 { 10189 op0 = XEXP (op0, 0); 10190 op1 = tem; 10191 continue; 10192 } 10193 10194 if (equality_comparison_p 10195 && 0 != (tem = simplify_binary_operation (MINUS, mode, 10196 XEXP (op0, 0), op1))) 10197 { 10198 op0 = XEXP (op0, 1); 10199 op1 = tem; 10200 continue; 10201 } 10202 10203 /* The sign bit of (minus (ashiftrt X C) X), where C is the number 10204 of bits in X minus 1, is one iff X > 0. */ 10205 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT 10206 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10207 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1)) 10208 == mode_width - 1 10209 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 10210 { 10211 op0 = XEXP (op0, 1); 10212 code = (code == GE ? LE : GT); 10213 continue; 10214 } 10215 break; 10216 10217 case XOR: 10218 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification 10219 if C is zero or B is a constant. */ 10220 if (equality_comparison_p 10221 && 0 != (tem = simplify_binary_operation (XOR, mode, 10222 XEXP (op0, 1), op1))) 10223 { 10224 op0 = XEXP (op0, 0); 10225 op1 = tem; 10226 continue; 10227 } 10228 break; 10229 10230 case EQ: case NE: 10231 case UNEQ: case LTGT: 10232 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE: 10233 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE: 10234 case UNORDERED: case ORDERED: 10235 /* We can't do anything if OP0 is a condition code value, rather 10236 than an actual data value. */ 10237 if (const_op != 0 10238 || CC0_P (XEXP (op0, 0)) 10239 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) 10240 break; 10241 10242 /* Get the two operands being compared. */ 10243 if (GET_CODE (XEXP (op0, 0)) == COMPARE) 10244 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); 10245 else 10246 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); 10247 10248 /* Check for the cases where we simply want the result of the 10249 earlier test or the opposite of that result. */ 10250 if (code == NE || code == EQ 10251 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 10252 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10253 && (STORE_FLAG_VALUE 10254 & (((HOST_WIDE_INT) 1 10255 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) 10256 && (code == LT || code == GE))) 10257 { 10258 enum rtx_code new_code; 10259 if (code == LT || code == NE) 10260 new_code = GET_CODE (op0); 10261 else 10262 new_code = reversed_comparison_code (op0, NULL); 10263 10264 if (new_code != UNKNOWN) 10265 { 10266 code = new_code; 10267 op0 = tem; 10268 op1 = tem1; 10269 continue; 10270 } 10271 } 10272 break; 10273 10274 case IOR: 10275 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero 10276 iff X <= 0. */ 10277 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS 10278 && XEXP (XEXP (op0, 0), 1) == constm1_rtx 10279 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 10280 { 10281 op0 = XEXP (op0, 1); 10282 code = (code == GE ? GT : LE); 10283 continue; 10284 } 10285 break; 10286 10287 case AND: 10288 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This 10289 will be converted to a ZERO_EXTRACT later. */ 10290 if (const_op == 0 && equality_comparison_p 10291 && GET_CODE (XEXP (op0, 0)) == ASHIFT 10292 && XEXP (XEXP (op0, 0), 0) == const1_rtx) 10293 { 10294 op0 = simplify_and_const_int 10295 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode, 10296 XEXP (op0, 1), 10297 XEXP (XEXP (op0, 0), 1)), 10298 (HOST_WIDE_INT) 1); 10299 continue; 10300 } 10301 10302 /* If we are comparing (and (lshiftrt X C1) C2) for equality with 10303 zero and X is a comparison and C1 and C2 describe only bits set 10304 in STORE_FLAG_VALUE, we can compare with X. */ 10305 if (const_op == 0 && equality_comparison_p 10306 && mode_width <= HOST_BITS_PER_WIDE_INT 10307 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10308 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT 10309 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10310 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 10311 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) 10312 { 10313 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 10314 << INTVAL (XEXP (XEXP (op0, 0), 1))); 10315 if ((~STORE_FLAG_VALUE & mask) == 0 10316 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0)) 10317 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 10318 && COMPARISON_P (tem)))) 10319 { 10320 op0 = XEXP (XEXP (op0, 0), 0); 10321 continue; 10322 } 10323 } 10324 10325 /* If we are doing an equality comparison of an AND of a bit equal 10326 to the sign bit, replace this with a LT or GE comparison of 10327 the underlying value. */ 10328 if (equality_comparison_p 10329 && const_op == 0 10330 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10331 && mode_width <= HOST_BITS_PER_WIDE_INT 10332 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 10333 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) 10334 { 10335 op0 = XEXP (op0, 0); 10336 code = (code == EQ ? GE : LT); 10337 continue; 10338 } 10339 10340 /* If this AND operation is really a ZERO_EXTEND from a narrower 10341 mode, the constant fits within that mode, and this is either an 10342 equality or unsigned comparison, try to do this comparison in 10343 the narrower mode. 10344 10345 Note that in: 10346 10347 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0)) 10348 -> (ne:DI (reg:SI 4) (const_int 0)) 10349 10350 unless TRULY_NOOP_TRUNCATION allows it or the register is 10351 known to hold a value of the required mode the 10352 transformation is invalid. */ 10353 if ((equality_comparison_p || unsigned_comparison_p) 10354 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10355 && (i = exact_log2 ((INTVAL (XEXP (op0, 1)) 10356 & GET_MODE_MASK (mode)) 10357 + 1)) >= 0 10358 && const_op >> i == 0 10359 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode 10360 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode), 10361 GET_MODE_BITSIZE (GET_MODE (op0))) 10362 || (REG_P (XEXP (op0, 0)) 10363 && reg_truncated_to_mode (tmode, XEXP (op0, 0))))) 10364 { 10365 op0 = gen_lowpart (tmode, XEXP (op0, 0)); 10366 continue; 10367 } 10368 10369 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 10370 fits in both M1 and M2 and the SUBREG is either paradoxical 10371 or represents the low part, permute the SUBREG and the AND 10372 and try again. */ 10373 if (GET_CODE (XEXP (op0, 0)) == SUBREG) 10374 { 10375 unsigned HOST_WIDE_INT c1; 10376 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0))); 10377 /* Require an integral mode, to avoid creating something like 10378 (AND:SF ...). */ 10379 if (SCALAR_INT_MODE_P (tmode) 10380 /* It is unsafe to commute the AND into the SUBREG if the 10381 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is 10382 not defined. As originally written the upper bits 10383 have a defined value due to the AND operation. 10384 However, if we commute the AND inside the SUBREG then 10385 they no longer have defined values and the meaning of 10386 the code has been changed. */ 10387 && (0 10388#ifdef WORD_REGISTER_OPERATIONS 10389 || (mode_width > GET_MODE_BITSIZE (tmode) 10390 && mode_width <= BITS_PER_WORD) 10391#endif 10392 || (mode_width <= GET_MODE_BITSIZE (tmode) 10393 && subreg_lowpart_p (XEXP (op0, 0)))) 10394 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10395 && mode_width <= HOST_BITS_PER_WIDE_INT 10396 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT 10397 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0 10398 && (c1 & ~GET_MODE_MASK (tmode)) == 0 10399 && c1 != mask 10400 && c1 != GET_MODE_MASK (tmode)) 10401 { 10402 op0 = simplify_gen_binary (AND, tmode, 10403 SUBREG_REG (XEXP (op0, 0)), 10404 gen_int_mode (c1, tmode)); 10405 op0 = gen_lowpart (mode, op0); 10406 continue; 10407 } 10408 } 10409 10410 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */ 10411 if (const_op == 0 && equality_comparison_p 10412 && XEXP (op0, 1) == const1_rtx 10413 && GET_CODE (XEXP (op0, 0)) == NOT) 10414 { 10415 op0 = simplify_and_const_int 10416 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1); 10417 code = (code == NE ? EQ : NE); 10418 continue; 10419 } 10420 10421 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to 10422 (eq (and (lshiftrt X) 1) 0). 10423 Also handle the case where (not X) is expressed using xor. */ 10424 if (const_op == 0 && equality_comparison_p 10425 && XEXP (op0, 1) == const1_rtx 10426 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT) 10427 { 10428 rtx shift_op = XEXP (XEXP (op0, 0), 0); 10429 rtx shift_count = XEXP (XEXP (op0, 0), 1); 10430 10431 if (GET_CODE (shift_op) == NOT 10432 || (GET_CODE (shift_op) == XOR 10433 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT 10434 && GET_CODE (shift_count) == CONST_INT 10435 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 10436 && (INTVAL (XEXP (shift_op, 1)) 10437 == (HOST_WIDE_INT) 1 << INTVAL (shift_count)))) 10438 { 10439 op0 = simplify_and_const_int 10440 (NULL_RTX, mode, 10441 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count), 10442 (HOST_WIDE_INT) 1); 10443 code = (code == NE ? EQ : NE); 10444 continue; 10445 } 10446 } 10447 break; 10448 10449 case ASHIFT: 10450 /* If we have (compare (ashift FOO N) (const_int C)) and 10451 the high order N bits of FOO (N+1 if an inequality comparison) 10452 are known to be zero, we can do this by comparing FOO with C 10453 shifted right N bits so long as the low-order N bits of C are 10454 zero. */ 10455 if (GET_CODE (XEXP (op0, 1)) == CONST_INT 10456 && INTVAL (XEXP (op0, 1)) >= 0 10457 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) 10458 < HOST_BITS_PER_WIDE_INT) 10459 && ((const_op 10460 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0) 10461 && mode_width <= HOST_BITS_PER_WIDE_INT 10462 && (nonzero_bits (XEXP (op0, 0), mode) 10463 & ~(mask >> (INTVAL (XEXP (op0, 1)) 10464 + ! equality_comparison_p))) == 0) 10465 { 10466 /* We must perform a logical shift, not an arithmetic one, 10467 as we want the top N bits of C to be zero. */ 10468 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode); 10469 10470 temp >>= INTVAL (XEXP (op0, 1)); 10471 op1 = gen_int_mode (temp, mode); 10472 op0 = XEXP (op0, 0); 10473 continue; 10474 } 10475 10476 /* If we are doing a sign bit comparison, it means we are testing 10477 a particular bit. Convert it to the appropriate AND. */ 10478 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT 10479 && mode_width <= HOST_BITS_PER_WIDE_INT) 10480 { 10481 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10482 ((HOST_WIDE_INT) 1 10483 << (mode_width - 1 10484 - INTVAL (XEXP (op0, 1))))); 10485 code = (code == LT ? NE : EQ); 10486 continue; 10487 } 10488 10489 /* If this an equality comparison with zero and we are shifting 10490 the low bit to the sign bit, we can convert this to an AND of the 10491 low-order bit. */ 10492 if (const_op == 0 && equality_comparison_p 10493 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10494 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) 10495 == mode_width - 1) 10496 { 10497 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10498 (HOST_WIDE_INT) 1); 10499 continue; 10500 } 10501 break; 10502 10503 case ASHIFTRT: 10504 /* If this is an equality comparison with zero, we can do this 10505 as a logical shift, which might be much simpler. */ 10506 if (equality_comparison_p && const_op == 0 10507 && GET_CODE (XEXP (op0, 1)) == CONST_INT) 10508 { 10509 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, 10510 XEXP (op0, 0), 10511 INTVAL (XEXP (op0, 1))); 10512 continue; 10513 } 10514 10515 /* If OP0 is a sign extension and CODE is not an unsigned comparison, 10516 do the comparison in a narrower mode. */ 10517 if (! unsigned_comparison_p 10518 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10519 && GET_CODE (XEXP (op0, 0)) == ASHIFT 10520 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 10521 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 10522 MODE_INT, 1)) != BLKmode 10523 && (((unsigned HOST_WIDE_INT) const_op 10524 + (GET_MODE_MASK (tmode) >> 1) + 1) 10525 <= GET_MODE_MASK (tmode))) 10526 { 10527 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0)); 10528 continue; 10529 } 10530 10531 /* Likewise if OP0 is a PLUS of a sign extension with a 10532 constant, which is usually represented with the PLUS 10533 between the shifts. */ 10534 if (! unsigned_comparison_p 10535 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10536 && GET_CODE (XEXP (op0, 0)) == PLUS 10537 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10538 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT 10539 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1) 10540 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 10541 MODE_INT, 1)) != BLKmode 10542 && (((unsigned HOST_WIDE_INT) const_op 10543 + (GET_MODE_MASK (tmode) >> 1) + 1) 10544 <= GET_MODE_MASK (tmode))) 10545 { 10546 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0); 10547 rtx add_const = XEXP (XEXP (op0, 0), 1); 10548 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0), 10549 add_const, XEXP (op0, 1)); 10550 10551 op0 = simplify_gen_binary (PLUS, tmode, 10552 gen_lowpart (tmode, inner), 10553 new_const); 10554 continue; 10555 } 10556 10557 /* ... fall through ... */ 10558 case LSHIFTRT: 10559 /* If we have (compare (xshiftrt FOO N) (const_int C)) and 10560 the low order N bits of FOO are known to be zero, we can do this 10561 by comparing FOO with C shifted left N bits so long as no 10562 overflow occurs. */ 10563 if (GET_CODE (XEXP (op0, 1)) == CONST_INT 10564 && INTVAL (XEXP (op0, 1)) >= 0 10565 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 10566 && mode_width <= HOST_BITS_PER_WIDE_INT 10567 && (nonzero_bits (XEXP (op0, 0), mode) 10568 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 10569 && (((unsigned HOST_WIDE_INT) const_op 10570 + (GET_CODE (op0) != LSHIFTRT 10571 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1) 10572 + 1) 10573 : 0)) 10574 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)))) 10575 { 10576 /* If the shift was logical, then we must make the condition 10577 unsigned. */ 10578 if (GET_CODE (op0) == LSHIFTRT) 10579 code = unsigned_condition (code); 10580 10581 const_op <<= INTVAL (XEXP (op0, 1)); 10582 op1 = GEN_INT (const_op); 10583 op0 = XEXP (op0, 0); 10584 continue; 10585 } 10586 10587 /* If we are using this shift to extract just the sign bit, we 10588 can replace this with an LT or GE comparison. */ 10589 if (const_op == 0 10590 && (equality_comparison_p || sign_bit_comparison_p) 10591 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10592 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) 10593 == mode_width - 1) 10594 { 10595 op0 = XEXP (op0, 0); 10596 code = (code == NE || code == GT ? LT : GE); 10597 continue; 10598 } 10599 break; 10600 10601 default: 10602 break; 10603 } 10604 10605 break; 10606 } 10607 10608 /* Now make any compound operations involved in this comparison. Then, 10609 check for an outmost SUBREG on OP0 that is not doing anything or is 10610 paradoxical. The latter transformation must only be performed when 10611 it is known that the "extra" bits will be the same in op0 and op1 or 10612 that they don't matter. There are three cases to consider: 10613 10614 1. SUBREG_REG (op0) is a register. In this case the bits are don't 10615 care bits and we can assume they have any convenient value. So 10616 making the transformation is safe. 10617 10618 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined. 10619 In this case the upper bits of op0 are undefined. We should not make 10620 the simplification in that case as we do not know the contents of 10621 those bits. 10622 10623 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not 10624 UNKNOWN. In that case we know those bits are zeros or ones. We must 10625 also be sure that they are the same as the upper bits of op1. 10626 10627 We can never remove a SUBREG for a non-equality comparison because 10628 the sign bit is in a different place in the underlying object. */ 10629 10630 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); 10631 op1 = make_compound_operation (op1, SET); 10632 10633 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 10634 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10635 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT 10636 && (code == NE || code == EQ)) 10637 { 10638 if (GET_MODE_SIZE (GET_MODE (op0)) 10639 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))) 10640 { 10641 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't 10642 implemented. */ 10643 if (REG_P (SUBREG_REG (op0))) 10644 { 10645 op0 = SUBREG_REG (op0); 10646 op1 = gen_lowpart (GET_MODE (op0), op1); 10647 } 10648 } 10649 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) 10650 <= HOST_BITS_PER_WIDE_INT) 10651 && (nonzero_bits (SUBREG_REG (op0), 10652 GET_MODE (SUBREG_REG (op0))) 10653 & ~GET_MODE_MASK (GET_MODE (op0))) == 0) 10654 { 10655 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1); 10656 10657 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) 10658 & ~GET_MODE_MASK (GET_MODE (op0))) == 0) 10659 op0 = SUBREG_REG (op0), op1 = tem; 10660 } 10661 } 10662 10663 /* We now do the opposite procedure: Some machines don't have compare 10664 insns in all modes. If OP0's mode is an integer mode smaller than a 10665 word and we can't do a compare in that mode, see if there is a larger 10666 mode for which we can do the compare. There are a number of cases in 10667 which we can use the wider mode. */ 10668 10669 mode = GET_MODE (op0); 10670 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT 10671 && GET_MODE_SIZE (mode) < UNITS_PER_WORD 10672 && ! have_insn_for (COMPARE, mode)) 10673 for (tmode = GET_MODE_WIDER_MODE (mode); 10674 (tmode != VOIDmode 10675 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT); 10676 tmode = GET_MODE_WIDER_MODE (tmode)) 10677 if (have_insn_for (COMPARE, tmode)) 10678 { 10679 int zero_extended; 10680 10681 /* If the only nonzero bits in OP0 and OP1 are those in the 10682 narrower mode and this is an equality or unsigned comparison, 10683 we can use the wider mode. Similarly for sign-extended 10684 values, in which case it is true for all comparisons. */ 10685 zero_extended = ((code == EQ || code == NE 10686 || code == GEU || code == GTU 10687 || code == LEU || code == LTU) 10688 && (nonzero_bits (op0, tmode) 10689 & ~GET_MODE_MASK (mode)) == 0 10690 && ((GET_CODE (op1) == CONST_INT 10691 || (nonzero_bits (op1, tmode) 10692 & ~GET_MODE_MASK (mode)) == 0))); 10693 10694 if (zero_extended 10695 || ((num_sign_bit_copies (op0, tmode) 10696 > (unsigned int) (GET_MODE_BITSIZE (tmode) 10697 - GET_MODE_BITSIZE (mode))) 10698 && (num_sign_bit_copies (op1, tmode) 10699 > (unsigned int) (GET_MODE_BITSIZE (tmode) 10700 - GET_MODE_BITSIZE (mode))))) 10701 { 10702 /* If OP0 is an AND and we don't have an AND in MODE either, 10703 make a new AND in the proper mode. */ 10704 if (GET_CODE (op0) == AND 10705 && !have_insn_for (AND, mode)) 10706 op0 = simplify_gen_binary (AND, tmode, 10707 gen_lowpart (tmode, 10708 XEXP (op0, 0)), 10709 gen_lowpart (tmode, 10710 XEXP (op0, 1))); 10711 10712 op0 = gen_lowpart (tmode, op0); 10713 if (zero_extended && GET_CODE (op1) == CONST_INT) 10714 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode)); 10715 op1 = gen_lowpart (tmode, op1); 10716 break; 10717 } 10718 10719 /* If this is a test for negative, we can make an explicit 10720 test of the sign bit. */ 10721 10722 if (op1 == const0_rtx && (code == LT || code == GE) 10723 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 10724 { 10725 op0 = simplify_gen_binary (AND, tmode, 10726 gen_lowpart (tmode, op0), 10727 GEN_INT ((HOST_WIDE_INT) 1 10728 << (GET_MODE_BITSIZE (mode) 10729 - 1))); 10730 code = (code == LT) ? NE : EQ; 10731 break; 10732 } 10733 } 10734 10735#ifdef CANONICALIZE_COMPARISON 10736 /* If this machine only supports a subset of valid comparisons, see if we 10737 can convert an unsupported one into a supported one. */ 10738 CANONICALIZE_COMPARISON (code, op0, op1); 10739#endif 10740 10741 *pop0 = op0; 10742 *pop1 = op1; 10743 10744 return code; 10745} 10746 10747/* Utility function for record_value_for_reg. Count number of 10748 rtxs in X. */ 10749static int 10750count_rtxs (rtx x) 10751{ 10752 enum rtx_code code = GET_CODE (x); 10753 const char *fmt; 10754 int i, ret = 1; 10755 10756 if (GET_RTX_CLASS (code) == '2' 10757 || GET_RTX_CLASS (code) == 'c') 10758 { 10759 rtx x0 = XEXP (x, 0); 10760 rtx x1 = XEXP (x, 1); 10761 10762 if (x0 == x1) 10763 return 1 + 2 * count_rtxs (x0); 10764 10765 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2' 10766 || GET_RTX_CLASS (GET_CODE (x1)) == 'c') 10767 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 10768 return 2 + 2 * count_rtxs (x0) 10769 + count_rtxs (x == XEXP (x1, 0) 10770 ? XEXP (x1, 1) : XEXP (x1, 0)); 10771 10772 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2' 10773 || GET_RTX_CLASS (GET_CODE (x0)) == 'c') 10774 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 10775 return 2 + 2 * count_rtxs (x1) 10776 + count_rtxs (x == XEXP (x0, 0) 10777 ? XEXP (x0, 1) : XEXP (x0, 0)); 10778 } 10779 10780 fmt = GET_RTX_FORMAT (code); 10781 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 10782 if (fmt[i] == 'e') 10783 ret += count_rtxs (XEXP (x, i)); 10784 10785 return ret; 10786} 10787 10788/* Utility function for following routine. Called when X is part of a value 10789 being stored into last_set_value. Sets last_set_table_tick 10790 for each register mentioned. Similar to mention_regs in cse.c */ 10791 10792static void 10793update_table_tick (rtx x) 10794{ 10795 enum rtx_code code = GET_CODE (x); 10796 const char *fmt = GET_RTX_FORMAT (code); 10797 int i; 10798 10799 if (code == REG) 10800 { 10801 unsigned int regno = REGNO (x); 10802 unsigned int endregno 10803 = regno + (regno < FIRST_PSEUDO_REGISTER 10804 ? hard_regno_nregs[regno][GET_MODE (x)] : 1); 10805 unsigned int r; 10806 10807 for (r = regno; r < endregno; r++) 10808 reg_stat[r].last_set_table_tick = label_tick; 10809 10810 return; 10811 } 10812 10813 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 10814 /* Note that we can't have an "E" in values stored; see 10815 get_last_value_validate. */ 10816 if (fmt[i] == 'e') 10817 { 10818 /* Check for identical subexpressions. If x contains 10819 identical subexpression we only have to traverse one of 10820 them. */ 10821 if (i == 0 && ARITHMETIC_P (x)) 10822 { 10823 /* Note that at this point x1 has already been 10824 processed. */ 10825 rtx x0 = XEXP (x, 0); 10826 rtx x1 = XEXP (x, 1); 10827 10828 /* If x0 and x1 are identical then there is no need to 10829 process x0. */ 10830 if (x0 == x1) 10831 break; 10832 10833 /* If x0 is identical to a subexpression of x1 then while 10834 processing x1, x0 has already been processed. Thus we 10835 are done with x. */ 10836 if (ARITHMETIC_P (x1) 10837 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 10838 break; 10839 10840 /* If x1 is identical to a subexpression of x0 then we 10841 still have to process the rest of x0. */ 10842 if (ARITHMETIC_P (x0) 10843 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 10844 { 10845 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0)); 10846 break; 10847 } 10848 } 10849 10850 update_table_tick (XEXP (x, i)); 10851 } 10852} 10853 10854/* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we 10855 are saying that the register is clobbered and we no longer know its 10856 value. If INSN is zero, don't update reg_stat[].last_set; this is 10857 only permitted with VALUE also zero and is used to invalidate the 10858 register. */ 10859 10860static void 10861record_value_for_reg (rtx reg, rtx insn, rtx value) 10862{ 10863 unsigned int regno = REGNO (reg); 10864 unsigned int endregno 10865 = regno + (regno < FIRST_PSEUDO_REGISTER 10866 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1); 10867 unsigned int i; 10868 10869 /* If VALUE contains REG and we have a previous value for REG, substitute 10870 the previous value. */ 10871 if (value && insn && reg_overlap_mentioned_p (reg, value)) 10872 { 10873 rtx tem; 10874 10875 /* Set things up so get_last_value is allowed to see anything set up to 10876 our insn. */ 10877 subst_low_cuid = INSN_CUID (insn); 10878 tem = get_last_value (reg); 10879 10880 /* If TEM is simply a binary operation with two CLOBBERs as operands, 10881 it isn't going to be useful and will take a lot of time to process, 10882 so just use the CLOBBER. */ 10883 10884 if (tem) 10885 { 10886 if (ARITHMETIC_P (tem) 10887 && GET_CODE (XEXP (tem, 0)) == CLOBBER 10888 && GET_CODE (XEXP (tem, 1)) == CLOBBER) 10889 tem = XEXP (tem, 0); 10890 else if (count_occurrences (value, reg, 1) >= 2) 10891 { 10892 /* If there are two or more occurrences of REG in VALUE, 10893 prevent the value from growing too much. */ 10894 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL) 10895 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx); 10896 } 10897 10898 value = replace_rtx (copy_rtx (value), reg, tem); 10899 } 10900 } 10901 10902 /* For each register modified, show we don't know its value, that 10903 we don't know about its bitwise content, that its value has been 10904 updated, and that we don't know the location of the death of the 10905 register. */ 10906 for (i = regno; i < endregno; i++) 10907 { 10908 if (insn) 10909 reg_stat[i].last_set = insn; 10910 10911 reg_stat[i].last_set_value = 0; 10912 reg_stat[i].last_set_mode = 0; 10913 reg_stat[i].last_set_nonzero_bits = 0; 10914 reg_stat[i].last_set_sign_bit_copies = 0; 10915 reg_stat[i].last_death = 0; 10916 reg_stat[i].truncated_to_mode = 0; 10917 } 10918 10919 /* Mark registers that are being referenced in this value. */ 10920 if (value) 10921 update_table_tick (value); 10922 10923 /* Now update the status of each register being set. 10924 If someone is using this register in this block, set this register 10925 to invalid since we will get confused between the two lives in this 10926 basic block. This makes using this register always invalid. In cse, we 10927 scan the table to invalidate all entries using this register, but this 10928 is too much work for us. */ 10929 10930 for (i = regno; i < endregno; i++) 10931 { 10932 reg_stat[i].last_set_label = label_tick; 10933 if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick)) 10934 reg_stat[i].last_set_invalid = 1; 10935 else 10936 reg_stat[i].last_set_invalid = 0; 10937 } 10938 10939 /* The value being assigned might refer to X (like in "x++;"). In that 10940 case, we must replace it with (clobber (const_int 0)) to prevent 10941 infinite loops. */ 10942 if (value && ! get_last_value_validate (&value, insn, 10943 reg_stat[regno].last_set_label, 0)) 10944 { 10945 value = copy_rtx (value); 10946 if (! get_last_value_validate (&value, insn, 10947 reg_stat[regno].last_set_label, 1)) 10948 value = 0; 10949 } 10950 10951 /* For the main register being modified, update the value, the mode, the 10952 nonzero bits, and the number of sign bit copies. */ 10953 10954 reg_stat[regno].last_set_value = value; 10955 10956 if (value) 10957 { 10958 enum machine_mode mode = GET_MODE (reg); 10959 subst_low_cuid = INSN_CUID (insn); 10960 reg_stat[regno].last_set_mode = mode; 10961 if (GET_MODE_CLASS (mode) == MODE_INT 10962 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 10963 mode = nonzero_bits_mode; 10964 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode); 10965 reg_stat[regno].last_set_sign_bit_copies 10966 = num_sign_bit_copies (value, GET_MODE (reg)); 10967 } 10968} 10969 10970/* Called via note_stores from record_dead_and_set_regs to handle one 10971 SET or CLOBBER in an insn. DATA is the instruction in which the 10972 set is occurring. */ 10973 10974static void 10975record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data) 10976{ 10977 rtx record_dead_insn = (rtx) data; 10978 10979 if (GET_CODE (dest) == SUBREG) 10980 dest = SUBREG_REG (dest); 10981 10982 if (!record_dead_insn) 10983 { 10984 if (REG_P (dest)) 10985 record_value_for_reg (dest, NULL_RTX, NULL_RTX); 10986 return; 10987 } 10988 10989 if (REG_P (dest)) 10990 { 10991 /* If we are setting the whole register, we know its value. Otherwise 10992 show that we don't know the value. We can handle SUBREG in 10993 some cases. */ 10994 if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) 10995 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); 10996 else if (GET_CODE (setter) == SET 10997 && GET_CODE (SET_DEST (setter)) == SUBREG 10998 && SUBREG_REG (SET_DEST (setter)) == dest 10999 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD 11000 && subreg_lowpart_p (SET_DEST (setter))) 11001 record_value_for_reg (dest, record_dead_insn, 11002 gen_lowpart (GET_MODE (dest), 11003 SET_SRC (setter))); 11004 else 11005 record_value_for_reg (dest, record_dead_insn, NULL_RTX); 11006 } 11007 else if (MEM_P (dest) 11008 /* Ignore pushes, they clobber nothing. */ 11009 && ! push_operand (dest, GET_MODE (dest))) 11010 mem_last_set = INSN_CUID (record_dead_insn); 11011} 11012 11013/* Update the records of when each REG was most recently set or killed 11014 for the things done by INSN. This is the last thing done in processing 11015 INSN in the combiner loop. 11016 11017 We update reg_stat[], in particular fields last_set, last_set_value, 11018 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies, 11019 last_death, and also the similar information mem_last_set (which insn 11020 most recently modified memory) and last_call_cuid (which insn was the 11021 most recent subroutine call). */ 11022 11023static void 11024record_dead_and_set_regs (rtx insn) 11025{ 11026 rtx link; 11027 unsigned int i; 11028 11029 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 11030 { 11031 if (REG_NOTE_KIND (link) == REG_DEAD 11032 && REG_P (XEXP (link, 0))) 11033 { 11034 unsigned int regno = REGNO (XEXP (link, 0)); 11035 unsigned int endregno 11036 = regno + (regno < FIRST_PSEUDO_REGISTER 11037 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))] 11038 : 1); 11039 11040 for (i = regno; i < endregno; i++) 11041 reg_stat[i].last_death = insn; 11042 } 11043 else if (REG_NOTE_KIND (link) == REG_INC) 11044 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); 11045 } 11046 11047 if (CALL_P (insn)) 11048 { 11049 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 11050 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i)) 11051 { 11052 reg_stat[i].last_set_value = 0; 11053 reg_stat[i].last_set_mode = 0; 11054 reg_stat[i].last_set_nonzero_bits = 0; 11055 reg_stat[i].last_set_sign_bit_copies = 0; 11056 reg_stat[i].last_death = 0; 11057 reg_stat[i].truncated_to_mode = 0; 11058 } 11059 11060 last_call_cuid = mem_last_set = INSN_CUID (insn); 11061 11062 /* We can't combine into a call pattern. Remember, though, that 11063 the return value register is set at this CUID. We could 11064 still replace a register with the return value from the 11065 wrong subroutine call! */ 11066 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX); 11067 } 11068 else 11069 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn); 11070} 11071 11072/* If a SUBREG has the promoted bit set, it is in fact a property of the 11073 register present in the SUBREG, so for each such SUBREG go back and 11074 adjust nonzero and sign bit information of the registers that are 11075 known to have some zero/sign bits set. 11076 11077 This is needed because when combine blows the SUBREGs away, the 11078 information on zero/sign bits is lost and further combines can be 11079 missed because of that. */ 11080 11081static void 11082record_promoted_value (rtx insn, rtx subreg) 11083{ 11084 rtx links, set; 11085 unsigned int regno = REGNO (SUBREG_REG (subreg)); 11086 enum machine_mode mode = GET_MODE (subreg); 11087 11088 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) 11089 return; 11090 11091 for (links = LOG_LINKS (insn); links;) 11092 { 11093 insn = XEXP (links, 0); 11094 set = single_set (insn); 11095 11096 if (! set || !REG_P (SET_DEST (set)) 11097 || REGNO (SET_DEST (set)) != regno 11098 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg))) 11099 { 11100 links = XEXP (links, 1); 11101 continue; 11102 } 11103 11104 if (reg_stat[regno].last_set == insn) 11105 { 11106 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0) 11107 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode); 11108 } 11109 11110 if (REG_P (SET_SRC (set))) 11111 { 11112 regno = REGNO (SET_SRC (set)); 11113 links = LOG_LINKS (insn); 11114 } 11115 else 11116 break; 11117 } 11118} 11119 11120/* Check if X, a register, is known to contain a value already 11121 truncated to MODE. In this case we can use a subreg to refer to 11122 the truncated value even though in the generic case we would need 11123 an explicit truncation. */ 11124 11125static bool 11126reg_truncated_to_mode (enum machine_mode mode, rtx x) 11127{ 11128 enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode; 11129 11130 if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick) 11131 return false; 11132 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode)) 11133 return true; 11134 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 11135 GET_MODE_BITSIZE (truncated))) 11136 return true; 11137 return false; 11138} 11139 11140/* X is a REG or a SUBREG. If X is some sort of a truncation record 11141 it. For non-TRULY_NOOP_TRUNCATION targets we might be able to turn 11142 a truncate into a subreg using this information. */ 11143 11144static void 11145record_truncated_value (rtx x) 11146{ 11147 enum machine_mode truncated_mode; 11148 11149 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))) 11150 { 11151 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x)); 11152 truncated_mode = GET_MODE (x); 11153 11154 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode)) 11155 return; 11156 11157 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode), 11158 GET_MODE_BITSIZE (original_mode))) 11159 return; 11160 11161 x = SUBREG_REG (x); 11162 } 11163 /* ??? For hard-regs we now record everything. We might be able to 11164 optimize this using last_set_mode. */ 11165 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) 11166 truncated_mode = GET_MODE (x); 11167 else 11168 return; 11169 11170 if (reg_stat[REGNO (x)].truncated_to_mode == 0 11171 || reg_stat[REGNO (x)].truncation_label < label_tick 11172 || (GET_MODE_SIZE (truncated_mode) 11173 < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode))) 11174 { 11175 reg_stat[REGNO (x)].truncated_to_mode = truncated_mode; 11176 reg_stat[REGNO (x)].truncation_label = label_tick; 11177 } 11178} 11179 11180/* Scan X for promoted SUBREGs and truncated REGs. For each one 11181 found, note what it implies to the registers used in it. */ 11182 11183static void 11184check_conversions (rtx insn, rtx x) 11185{ 11186 if (GET_CODE (x) == SUBREG || REG_P (x)) 11187 { 11188 if (GET_CODE (x) == SUBREG 11189 && SUBREG_PROMOTED_VAR_P (x) 11190 && REG_P (SUBREG_REG (x))) 11191 record_promoted_value (insn, x); 11192 11193 record_truncated_value (x); 11194 } 11195 else 11196 { 11197 const char *format = GET_RTX_FORMAT (GET_CODE (x)); 11198 int i, j; 11199 11200 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) 11201 switch (format[i]) 11202 { 11203 case 'e': 11204 check_conversions (insn, XEXP (x, i)); 11205 break; 11206 case 'V': 11207 case 'E': 11208 if (XVEC (x, i) != 0) 11209 for (j = 0; j < XVECLEN (x, i); j++) 11210 check_conversions (insn, XVECEXP (x, i, j)); 11211 break; 11212 } 11213 } 11214} 11215 11216/* Utility routine for the following function. Verify that all the registers 11217 mentioned in *LOC are valid when *LOC was part of a value set when 11218 label_tick == TICK. Return 0 if some are not. 11219 11220 If REPLACE is nonzero, replace the invalid reference with 11221 (clobber (const_int 0)) and return 1. This replacement is useful because 11222 we often can get useful information about the form of a value (e.g., if 11223 it was produced by a shift that always produces -1 or 0) even though 11224 we don't know exactly what registers it was produced from. */ 11225 11226static int 11227get_last_value_validate (rtx *loc, rtx insn, int tick, int replace) 11228{ 11229 rtx x = *loc; 11230 const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); 11231 int len = GET_RTX_LENGTH (GET_CODE (x)); 11232 int i; 11233 11234 if (REG_P (x)) 11235 { 11236 unsigned int regno = REGNO (x); 11237 unsigned int endregno 11238 = regno + (regno < FIRST_PSEUDO_REGISTER 11239 ? hard_regno_nregs[regno][GET_MODE (x)] : 1); 11240 unsigned int j; 11241 11242 for (j = regno; j < endregno; j++) 11243 if (reg_stat[j].last_set_invalid 11244 /* If this is a pseudo-register that was only set once and not 11245 live at the beginning of the function, it is always valid. */ 11246 || (! (regno >= FIRST_PSEUDO_REGISTER 11247 && REG_N_SETS (regno) == 1 11248 && (! REGNO_REG_SET_P 11249 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, 11250 regno))) 11251 && reg_stat[j].last_set_label > tick)) 11252 { 11253 if (replace) 11254 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 11255 return replace; 11256 } 11257 11258 return 1; 11259 } 11260 /* If this is a memory reference, make sure that there were 11261 no stores after it that might have clobbered the value. We don't 11262 have alias info, so we assume any store invalidates it. */ 11263 else if (MEM_P (x) && !MEM_READONLY_P (x) 11264 && INSN_CUID (insn) <= mem_last_set) 11265 { 11266 if (replace) 11267 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 11268 return replace; 11269 } 11270 11271 for (i = 0; i < len; i++) 11272 { 11273 if (fmt[i] == 'e') 11274 { 11275 /* Check for identical subexpressions. If x contains 11276 identical subexpression we only have to traverse one of 11277 them. */ 11278 if (i == 1 && ARITHMETIC_P (x)) 11279 { 11280 /* Note that at this point x0 has already been checked 11281 and found valid. */ 11282 rtx x0 = XEXP (x, 0); 11283 rtx x1 = XEXP (x, 1); 11284 11285 /* If x0 and x1 are identical then x is also valid. */ 11286 if (x0 == x1) 11287 return 1; 11288 11289 /* If x1 is identical to a subexpression of x0 then 11290 while checking x0, x1 has already been checked. Thus 11291 it is valid and so as x. */ 11292 if (ARITHMETIC_P (x0) 11293 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 11294 return 1; 11295 11296 /* If x0 is identical to a subexpression of x1 then x is 11297 valid iff the rest of x1 is valid. */ 11298 if (ARITHMETIC_P (x1) 11299 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 11300 return 11301 get_last_value_validate (&XEXP (x1, 11302 x0 == XEXP (x1, 0) ? 1 : 0), 11303 insn, tick, replace); 11304 } 11305 11306 if (get_last_value_validate (&XEXP (x, i), insn, tick, 11307 replace) == 0) 11308 return 0; 11309 } 11310 /* Don't bother with these. They shouldn't occur anyway. */ 11311 else if (fmt[i] == 'E') 11312 return 0; 11313 } 11314 11315 /* If we haven't found a reason for it to be invalid, it is valid. */ 11316 return 1; 11317} 11318 11319/* Get the last value assigned to X, if known. Some registers 11320 in the value may be replaced with (clobber (const_int 0)) if their value 11321 is known longer known reliably. */ 11322 11323static rtx 11324get_last_value (rtx x) 11325{ 11326 unsigned int regno; 11327 rtx value; 11328 11329 /* If this is a non-paradoxical SUBREG, get the value of its operand and 11330 then convert it to the desired mode. If this is a paradoxical SUBREG, 11331 we cannot predict what values the "extra" bits might have. */ 11332 if (GET_CODE (x) == SUBREG 11333 && subreg_lowpart_p (x) 11334 && (GET_MODE_SIZE (GET_MODE (x)) 11335 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 11336 && (value = get_last_value (SUBREG_REG (x))) != 0) 11337 return gen_lowpart (GET_MODE (x), value); 11338 11339 if (!REG_P (x)) 11340 return 0; 11341 11342 regno = REGNO (x); 11343 value = reg_stat[regno].last_set_value; 11344 11345 /* If we don't have a value, or if it isn't for this basic block and 11346 it's either a hard register, set more than once, or it's a live 11347 at the beginning of the function, return 0. 11348 11349 Because if it's not live at the beginning of the function then the reg 11350 is always set before being used (is never used without being set). 11351 And, if it's set only once, and it's always set before use, then all 11352 uses must have the same last value, even if it's not from this basic 11353 block. */ 11354 11355 if (value == 0 11356 || (reg_stat[regno].last_set_label != label_tick 11357 && (regno < FIRST_PSEUDO_REGISTER 11358 || REG_N_SETS (regno) != 1 11359 || (REGNO_REG_SET_P 11360 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, 11361 regno))))) 11362 return 0; 11363 11364 /* If the value was set in a later insn than the ones we are processing, 11365 we can't use it even if the register was only set once. */ 11366 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid) 11367 return 0; 11368 11369 /* If the value has all its registers valid, return it. */ 11370 if (get_last_value_validate (&value, reg_stat[regno].last_set, 11371 reg_stat[regno].last_set_label, 0)) 11372 return value; 11373 11374 /* Otherwise, make a copy and replace any invalid register with 11375 (clobber (const_int 0)). If that fails for some reason, return 0. */ 11376 11377 value = copy_rtx (value); 11378 if (get_last_value_validate (&value, reg_stat[regno].last_set, 11379 reg_stat[regno].last_set_label, 1)) 11380 return value; 11381 11382 return 0; 11383} 11384 11385/* Return nonzero if expression X refers to a REG or to memory 11386 that is set in an instruction more recent than FROM_CUID. */ 11387 11388static int 11389use_crosses_set_p (rtx x, int from_cuid) 11390{ 11391 const char *fmt; 11392 int i; 11393 enum rtx_code code = GET_CODE (x); 11394 11395 if (code == REG) 11396 { 11397 unsigned int regno = REGNO (x); 11398 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER 11399 ? hard_regno_nregs[regno][GET_MODE (x)] : 1); 11400 11401#ifdef PUSH_ROUNDING 11402 /* Don't allow uses of the stack pointer to be moved, 11403 because we don't know whether the move crosses a push insn. */ 11404 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS) 11405 return 1; 11406#endif 11407 for (; regno < endreg; regno++) 11408 if (reg_stat[regno].last_set 11409 && INSN_CUID (reg_stat[regno].last_set) > from_cuid) 11410 return 1; 11411 return 0; 11412 } 11413 11414 if (code == MEM && mem_last_set > from_cuid) 11415 return 1; 11416 11417 fmt = GET_RTX_FORMAT (code); 11418 11419 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 11420 { 11421 if (fmt[i] == 'E') 11422 { 11423 int j; 11424 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 11425 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid)) 11426 return 1; 11427 } 11428 else if (fmt[i] == 'e' 11429 && use_crosses_set_p (XEXP (x, i), from_cuid)) 11430 return 1; 11431 } 11432 return 0; 11433} 11434 11435/* Define three variables used for communication between the following 11436 routines. */ 11437 11438static unsigned int reg_dead_regno, reg_dead_endregno; 11439static int reg_dead_flag; 11440 11441/* Function called via note_stores from reg_dead_at_p. 11442 11443 If DEST is within [reg_dead_regno, reg_dead_endregno), set 11444 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ 11445 11446static void 11447reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED) 11448{ 11449 unsigned int regno, endregno; 11450 11451 if (!REG_P (dest)) 11452 return; 11453 11454 regno = REGNO (dest); 11455 endregno = regno + (regno < FIRST_PSEUDO_REGISTER 11456 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1); 11457 11458 if (reg_dead_endregno > regno && reg_dead_regno < endregno) 11459 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; 11460} 11461 11462/* Return nonzero if REG is known to be dead at INSN. 11463 11464 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER 11465 referencing REG, it is dead. If we hit a SET referencing REG, it is 11466 live. Otherwise, see if it is live or dead at the start of the basic 11467 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS 11468 must be assumed to be always live. */ 11469 11470static int 11471reg_dead_at_p (rtx reg, rtx insn) 11472{ 11473 basic_block block; 11474 unsigned int i; 11475 11476 /* Set variables for reg_dead_at_p_1. */ 11477 reg_dead_regno = REGNO (reg); 11478 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER 11479 ? hard_regno_nregs[reg_dead_regno] 11480 [GET_MODE (reg)] 11481 : 1); 11482 11483 reg_dead_flag = 0; 11484 11485 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers 11486 we allow the machine description to decide whether use-and-clobber 11487 patterns are OK. */ 11488 if (reg_dead_regno < FIRST_PSEUDO_REGISTER) 11489 { 11490 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 11491 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i)) 11492 return 0; 11493 } 11494 11495 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or 11496 beginning of function. */ 11497 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn); 11498 insn = prev_nonnote_insn (insn)) 11499 { 11500 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL); 11501 if (reg_dead_flag) 11502 return reg_dead_flag == 1 ? 1 : 0; 11503 11504 if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) 11505 return 1; 11506 } 11507 11508 /* Get the basic block that we were in. */ 11509 if (insn == 0) 11510 block = ENTRY_BLOCK_PTR->next_bb; 11511 else 11512 { 11513 FOR_EACH_BB (block) 11514 if (insn == BB_HEAD (block)) 11515 break; 11516 11517 if (block == EXIT_BLOCK_PTR) 11518 return 0; 11519 } 11520 11521 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 11522 if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i)) 11523 return 0; 11524 11525 return 1; 11526} 11527 11528/* Note hard registers in X that are used. This code is similar to 11529 that in flow.c, but much simpler since we don't care about pseudos. */ 11530 11531static void 11532mark_used_regs_combine (rtx x) 11533{ 11534 RTX_CODE code = GET_CODE (x); 11535 unsigned int regno; 11536 int i; 11537 11538 switch (code) 11539 { 11540 case LABEL_REF: 11541 case SYMBOL_REF: 11542 case CONST_INT: 11543 case CONST: 11544 case CONST_DOUBLE: 11545 case CONST_VECTOR: 11546 case PC: 11547 case ADDR_VEC: 11548 case ADDR_DIFF_VEC: 11549 case ASM_INPUT: 11550#ifdef HAVE_cc0 11551 /* CC0 must die in the insn after it is set, so we don't need to take 11552 special note of it here. */ 11553 case CC0: 11554#endif 11555 return; 11556 11557 case CLOBBER: 11558 /* If we are clobbering a MEM, mark any hard registers inside the 11559 address as used. */ 11560 if (MEM_P (XEXP (x, 0))) 11561 mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); 11562 return; 11563 11564 case REG: 11565 regno = REGNO (x); 11566 /* A hard reg in a wide mode may really be multiple registers. 11567 If so, mark all of them just like the first. */ 11568 if (regno < FIRST_PSEUDO_REGISTER) 11569 { 11570 unsigned int endregno, r; 11571 11572 /* None of this applies to the stack, frame or arg pointers. */ 11573 if (regno == STACK_POINTER_REGNUM 11574#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM 11575 || regno == HARD_FRAME_POINTER_REGNUM 11576#endif 11577#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 11578 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) 11579#endif 11580 || regno == FRAME_POINTER_REGNUM) 11581 return; 11582 11583 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)]; 11584 for (r = regno; r < endregno; r++) 11585 SET_HARD_REG_BIT (newpat_used_regs, r); 11586 } 11587 return; 11588 11589 case SET: 11590 { 11591 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in 11592 the address. */ 11593 rtx testreg = SET_DEST (x); 11594 11595 while (GET_CODE (testreg) == SUBREG 11596 || GET_CODE (testreg) == ZERO_EXTRACT 11597 || GET_CODE (testreg) == STRICT_LOW_PART) 11598 testreg = XEXP (testreg, 0); 11599 11600 if (MEM_P (testreg)) 11601 mark_used_regs_combine (XEXP (testreg, 0)); 11602 11603 mark_used_regs_combine (SET_SRC (x)); 11604 } 11605 return; 11606 11607 default: 11608 break; 11609 } 11610 11611 /* Recursively scan the operands of this expression. */ 11612 11613 { 11614 const char *fmt = GET_RTX_FORMAT (code); 11615 11616 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 11617 { 11618 if (fmt[i] == 'e') 11619 mark_used_regs_combine (XEXP (x, i)); 11620 else if (fmt[i] == 'E') 11621 { 11622 int j; 11623 11624 for (j = 0; j < XVECLEN (x, i); j++) 11625 mark_used_regs_combine (XVECEXP (x, i, j)); 11626 } 11627 } 11628 } 11629} 11630 11631/* Remove register number REGNO from the dead registers list of INSN. 11632 11633 Return the note used to record the death, if there was one. */ 11634 11635rtx 11636remove_death (unsigned int regno, rtx insn) 11637{ 11638 rtx note = find_regno_note (insn, REG_DEAD, regno); 11639 11640 if (note) 11641 { 11642 REG_N_DEATHS (regno)--; 11643 remove_note (insn, note); 11644 } 11645 11646 return note; 11647} 11648 11649/* For each register (hardware or pseudo) used within expression X, if its 11650 death is in an instruction with cuid between FROM_CUID (inclusive) and 11651 TO_INSN (exclusive), put a REG_DEAD note for that register in the 11652 list headed by PNOTES. 11653 11654 That said, don't move registers killed by maybe_kill_insn. 11655 11656 This is done when X is being merged by combination into TO_INSN. These 11657 notes will then be distributed as needed. */ 11658 11659static void 11660move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn, 11661 rtx *pnotes) 11662{ 11663 const char *fmt; 11664 int len, i; 11665 enum rtx_code code = GET_CODE (x); 11666 11667 if (code == REG) 11668 { 11669 unsigned int regno = REGNO (x); 11670 rtx where_dead = reg_stat[regno].last_death; 11671 rtx before_dead, after_dead; 11672 11673 /* Don't move the register if it gets killed in between from and to. */ 11674 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) 11675 && ! reg_referenced_p (x, maybe_kill_insn)) 11676 return; 11677 11678 /* WHERE_DEAD could be a USE insn made by combine, so first we 11679 make sure that we have insns with valid INSN_CUID values. */ 11680 before_dead = where_dead; 11681 while (before_dead && INSN_UID (before_dead) > max_uid_cuid) 11682 before_dead = PREV_INSN (before_dead); 11683 11684 after_dead = where_dead; 11685 while (after_dead && INSN_UID (after_dead) > max_uid_cuid) 11686 after_dead = NEXT_INSN (after_dead); 11687 11688 if (before_dead && after_dead 11689 && INSN_CUID (before_dead) >= from_cuid 11690 && (INSN_CUID (after_dead) < INSN_CUID (to_insn) 11691 || (where_dead != after_dead 11692 && INSN_CUID (after_dead) == INSN_CUID (to_insn)))) 11693 { 11694 rtx note = remove_death (regno, where_dead); 11695 11696 /* It is possible for the call above to return 0. This can occur 11697 when last_death points to I2 or I1 that we combined with. 11698 In that case make a new note. 11699 11700 We must also check for the case where X is a hard register 11701 and NOTE is a death note for a range of hard registers 11702 including X. In that case, we must put REG_DEAD notes for 11703 the remaining registers in place of NOTE. */ 11704 11705 if (note != 0 && regno < FIRST_PSEUDO_REGISTER 11706 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 11707 > GET_MODE_SIZE (GET_MODE (x)))) 11708 { 11709 unsigned int deadregno = REGNO (XEXP (note, 0)); 11710 unsigned int deadend 11711 = (deadregno + hard_regno_nregs[deadregno] 11712 [GET_MODE (XEXP (note, 0))]); 11713 unsigned int ourend 11714 = regno + hard_regno_nregs[regno][GET_MODE (x)]; 11715 unsigned int i; 11716 11717 for (i = deadregno; i < deadend; i++) 11718 if (i < regno || i >= ourend) 11719 REG_NOTES (where_dead) 11720 = gen_rtx_EXPR_LIST (REG_DEAD, 11721 regno_reg_rtx[i], 11722 REG_NOTES (where_dead)); 11723 } 11724 11725 /* If we didn't find any note, or if we found a REG_DEAD note that 11726 covers only part of the given reg, and we have a multi-reg hard 11727 register, then to be safe we must check for REG_DEAD notes 11728 for each register other than the first. They could have 11729 their own REG_DEAD notes lying around. */ 11730 else if ((note == 0 11731 || (note != 0 11732 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 11733 < GET_MODE_SIZE (GET_MODE (x))))) 11734 && regno < FIRST_PSEUDO_REGISTER 11735 && hard_regno_nregs[regno][GET_MODE (x)] > 1) 11736 { 11737 unsigned int ourend 11738 = regno + hard_regno_nregs[regno][GET_MODE (x)]; 11739 unsigned int i, offset; 11740 rtx oldnotes = 0; 11741 11742 if (note) 11743 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))]; 11744 else 11745 offset = 1; 11746 11747 for (i = regno + offset; i < ourend; i++) 11748 move_deaths (regno_reg_rtx[i], 11749 maybe_kill_insn, from_cuid, to_insn, &oldnotes); 11750 } 11751 11752 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) 11753 { 11754 XEXP (note, 1) = *pnotes; 11755 *pnotes = note; 11756 } 11757 else 11758 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes); 11759 11760 REG_N_DEATHS (regno)++; 11761 } 11762 11763 return; 11764 } 11765 11766 else if (GET_CODE (x) == SET) 11767 { 11768 rtx dest = SET_DEST (x); 11769 11770 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes); 11771 11772 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG 11773 that accesses one word of a multi-word item, some 11774 piece of everything register in the expression is used by 11775 this insn, so remove any old death. */ 11776 /* ??? So why do we test for equality of the sizes? */ 11777 11778 if (GET_CODE (dest) == ZERO_EXTRACT 11779 || GET_CODE (dest) == STRICT_LOW_PART 11780 || (GET_CODE (dest) == SUBREG 11781 && (((GET_MODE_SIZE (GET_MODE (dest)) 11782 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 11783 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) 11784 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) 11785 { 11786 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes); 11787 return; 11788 } 11789 11790 /* If this is some other SUBREG, we know it replaces the entire 11791 value, so use that as the destination. */ 11792 if (GET_CODE (dest) == SUBREG) 11793 dest = SUBREG_REG (dest); 11794 11795 /* If this is a MEM, adjust deaths of anything used in the address. 11796 For a REG (the only other possibility), the entire value is 11797 being replaced so the old value is not used in this insn. */ 11798 11799 if (MEM_P (dest)) 11800 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid, 11801 to_insn, pnotes); 11802 return; 11803 } 11804 11805 else if (GET_CODE (x) == CLOBBER) 11806 return; 11807 11808 len = GET_RTX_LENGTH (code); 11809 fmt = GET_RTX_FORMAT (code); 11810 11811 for (i = 0; i < len; i++) 11812 { 11813 if (fmt[i] == 'E') 11814 { 11815 int j; 11816 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 11817 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid, 11818 to_insn, pnotes); 11819 } 11820 else if (fmt[i] == 'e') 11821 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes); 11822 } 11823} 11824 11825/* Return 1 if X is the target of a bit-field assignment in BODY, the 11826 pattern of an insn. X must be a REG. */ 11827 11828static int 11829reg_bitfield_target_p (rtx x, rtx body) 11830{ 11831 int i; 11832 11833 if (GET_CODE (body) == SET) 11834 { 11835 rtx dest = SET_DEST (body); 11836 rtx target; 11837 unsigned int regno, tregno, endregno, endtregno; 11838 11839 if (GET_CODE (dest) == ZERO_EXTRACT) 11840 target = XEXP (dest, 0); 11841 else if (GET_CODE (dest) == STRICT_LOW_PART) 11842 target = SUBREG_REG (XEXP (dest, 0)); 11843 else 11844 return 0; 11845 11846 if (GET_CODE (target) == SUBREG) 11847 target = SUBREG_REG (target); 11848 11849 if (!REG_P (target)) 11850 return 0; 11851 11852 tregno = REGNO (target), regno = REGNO (x); 11853 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) 11854 return target == x; 11855 11856 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)]; 11857 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)]; 11858 11859 return endregno > tregno && regno < endtregno; 11860 } 11861 11862 else if (GET_CODE (body) == PARALLEL) 11863 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 11864 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) 11865 return 1; 11866 11867 return 0; 11868} 11869 11870/* Given a chain of REG_NOTES originally from FROM_INSN, try to place them 11871 as appropriate. I3 and I2 are the insns resulting from the combination 11872 insns including FROM (I2 may be zero). 11873 11874 ELIM_I2 and ELIM_I1 are either zero or registers that we know will 11875 not need REG_DEAD notes because they are being substituted for. This 11876 saves searching in the most common cases. 11877 11878 Each note in the list is either ignored or placed on some insns, depending 11879 on the type of note. */ 11880 11881static void 11882distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2, 11883 rtx elim_i1) 11884{ 11885 rtx note, next_note; 11886 rtx tem; 11887 11888 for (note = notes; note; note = next_note) 11889 { 11890 rtx place = 0, place2 = 0; 11891 11892 next_note = XEXP (note, 1); 11893 switch (REG_NOTE_KIND (note)) 11894 { 11895 case REG_BR_PROB: 11896 case REG_BR_PRED: 11897 /* Doesn't matter much where we put this, as long as it's somewhere. 11898 It is preferable to keep these notes on branches, which is most 11899 likely to be i3. */ 11900 place = i3; 11901 break; 11902 11903 case REG_VALUE_PROFILE: 11904 /* Just get rid of this note, as it is unused later anyway. */ 11905 break; 11906 11907 case REG_NON_LOCAL_GOTO: 11908 if (JUMP_P (i3)) 11909 place = i3; 11910 else 11911 { 11912 gcc_assert (i2 && JUMP_P (i2)); 11913 place = i2; 11914 } 11915 break; 11916 11917 case REG_EH_REGION: 11918 /* These notes must remain with the call or trapping instruction. */ 11919 if (CALL_P (i3)) 11920 place = i3; 11921 else if (i2 && CALL_P (i2)) 11922 place = i2; 11923 else 11924 { 11925 gcc_assert (flag_non_call_exceptions); 11926 if (may_trap_p (i3)) 11927 place = i3; 11928 else if (i2 && may_trap_p (i2)) 11929 place = i2; 11930 /* ??? Otherwise assume we've combined things such that we 11931 can now prove that the instructions can't trap. Drop the 11932 note in this case. */ 11933 } 11934 break; 11935 11936 case REG_NORETURN: 11937 case REG_SETJMP: 11938 /* These notes must remain with the call. It should not be 11939 possible for both I2 and I3 to be a call. */ 11940 if (CALL_P (i3)) 11941 place = i3; 11942 else 11943 { 11944 gcc_assert (i2 && CALL_P (i2)); 11945 place = i2; 11946 } 11947 break; 11948 11949 case REG_UNUSED: 11950 /* Any clobbers for i3 may still exist, and so we must process 11951 REG_UNUSED notes from that insn. 11952 11953 Any clobbers from i2 or i1 can only exist if they were added by 11954 recog_for_combine. In that case, recog_for_combine created the 11955 necessary REG_UNUSED notes. Trying to keep any original 11956 REG_UNUSED notes from these insns can cause incorrect output 11957 if it is for the same register as the original i3 dest. 11958 In that case, we will notice that the register is set in i3, 11959 and then add a REG_UNUSED note for the destination of i3, which 11960 is wrong. However, it is possible to have REG_UNUSED notes from 11961 i2 or i1 for register which were both used and clobbered, so 11962 we keep notes from i2 or i1 if they will turn into REG_DEAD 11963 notes. */ 11964 11965 /* If this register is set or clobbered in I3, put the note there 11966 unless there is one already. */ 11967 if (reg_set_p (XEXP (note, 0), PATTERN (i3))) 11968 { 11969 if (from_insn != i3) 11970 break; 11971 11972 if (! (REG_P (XEXP (note, 0)) 11973 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) 11974 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) 11975 place = i3; 11976 } 11977 /* Otherwise, if this register is used by I3, then this register 11978 now dies here, so we must put a REG_DEAD note here unless there 11979 is one already. */ 11980 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) 11981 && ! (REG_P (XEXP (note, 0)) 11982 ? find_regno_note (i3, REG_DEAD, 11983 REGNO (XEXP (note, 0))) 11984 : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) 11985 { 11986 PUT_REG_NOTE_KIND (note, REG_DEAD); 11987 place = i3; 11988 } 11989 break; 11990 11991 case REG_EQUAL: 11992 case REG_EQUIV: 11993 case REG_NOALIAS: 11994 /* These notes say something about results of an insn. We can 11995 only support them if they used to be on I3 in which case they 11996 remain on I3. Otherwise they are ignored. 11997 11998 If the note refers to an expression that is not a constant, we 11999 must also ignore the note since we cannot tell whether the 12000 equivalence is still true. It might be possible to do 12001 slightly better than this (we only have a problem if I2DEST 12002 or I1DEST is present in the expression), but it doesn't 12003 seem worth the trouble. */ 12004 12005 if (from_insn == i3 12006 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) 12007 place = i3; 12008 break; 12009 12010 case REG_INC: 12011 case REG_NO_CONFLICT: 12012 /* These notes say something about how a register is used. They must 12013 be present on any use of the register in I2 or I3. */ 12014 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) 12015 place = i3; 12016 12017 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) 12018 { 12019 if (place) 12020 place2 = i2; 12021 else 12022 place = i2; 12023 } 12024 break; 12025 12026 case REG_LABEL: 12027 /* This can show up in several ways -- either directly in the 12028 pattern, or hidden off in the constant pool with (or without?) 12029 a REG_EQUAL note. */ 12030 /* ??? Ignore the without-reg_equal-note problem for now. */ 12031 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) 12032 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX)) 12033 && GET_CODE (XEXP (tem, 0)) == LABEL_REF 12034 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))) 12035 place = i3; 12036 12037 if (i2 12038 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) 12039 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX)) 12040 && GET_CODE (XEXP (tem, 0)) == LABEL_REF 12041 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))) 12042 { 12043 if (place) 12044 place2 = i2; 12045 else 12046 place = i2; 12047 } 12048 12049 /* Don't attach REG_LABEL note to a JUMP_INSN. Add 12050 a JUMP_LABEL instead or decrement LABEL_NUSES. */ 12051 if (place && JUMP_P (place)) 12052 { 12053 rtx label = JUMP_LABEL (place); 12054 12055 if (!label) 12056 JUMP_LABEL (place) = XEXP (note, 0); 12057 else 12058 { 12059 gcc_assert (label == XEXP (note, 0)); 12060 if (LABEL_P (label)) 12061 LABEL_NUSES (label)--; 12062 } 12063 place = 0; 12064 } 12065 if (place2 && JUMP_P (place2)) 12066 { 12067 rtx label = JUMP_LABEL (place2); 12068 12069 if (!label) 12070 JUMP_LABEL (place2) = XEXP (note, 0); 12071 else 12072 { 12073 gcc_assert (label == XEXP (note, 0)); 12074 if (LABEL_P (label)) 12075 LABEL_NUSES (label)--; 12076 } 12077 place2 = 0; 12078 } 12079 break; 12080 12081 case REG_NONNEG: 12082 /* This note says something about the value of a register prior 12083 to the execution of an insn. It is too much trouble to see 12084 if the note is still correct in all situations. It is better 12085 to simply delete it. */ 12086 break; 12087 12088 case REG_RETVAL: 12089 /* If the insn previously containing this note still exists, 12090 put it back where it was. Otherwise move it to the previous 12091 insn. Adjust the corresponding REG_LIBCALL note. */ 12092 if (!NOTE_P (from_insn)) 12093 place = from_insn; 12094 else 12095 { 12096 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX); 12097 place = prev_real_insn (from_insn); 12098 if (tem && place) 12099 XEXP (tem, 0) = place; 12100 /* If we're deleting the last remaining instruction of a 12101 libcall sequence, don't add the notes. */ 12102 else if (XEXP (note, 0) == from_insn) 12103 tem = place = 0; 12104 /* Don't add the dangling REG_RETVAL note. */ 12105 else if (! tem) 12106 place = 0; 12107 } 12108 break; 12109 12110 case REG_LIBCALL: 12111 /* This is handled similarly to REG_RETVAL. */ 12112 if (!NOTE_P (from_insn)) 12113 place = from_insn; 12114 else 12115 { 12116 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX); 12117 place = next_real_insn (from_insn); 12118 if (tem && place) 12119 XEXP (tem, 0) = place; 12120 /* If we're deleting the last remaining instruction of a 12121 libcall sequence, don't add the notes. */ 12122 else if (XEXP (note, 0) == from_insn) 12123 tem = place = 0; 12124 /* Don't add the dangling REG_LIBCALL note. */ 12125 else if (! tem) 12126 place = 0; 12127 } 12128 break; 12129 12130 case REG_DEAD: 12131 /* If we replaced the right hand side of FROM_INSN with a 12132 REG_EQUAL note, the original use of the dying register 12133 will not have been combined into I3 and I2. In such cases, 12134 FROM_INSN is guaranteed to be the first of the combined 12135 instructions, so we simply need to search back before 12136 FROM_INSN for the previous use or set of this register, 12137 then alter the notes there appropriately. 12138 12139 If the register is used as an input in I3, it dies there. 12140 Similarly for I2, if it is nonzero and adjacent to I3. 12141 12142 If the register is not used as an input in either I3 or I2 12143 and it is not one of the registers we were supposed to eliminate, 12144 there are two possibilities. We might have a non-adjacent I2 12145 or we might have somehow eliminated an additional register 12146 from a computation. For example, we might have had A & B where 12147 we discover that B will always be zero. In this case we will 12148 eliminate the reference to A. 12149 12150 In both cases, we must search to see if we can find a previous 12151 use of A and put the death note there. */ 12152 12153 if (from_insn 12154 && from_insn == i2mod 12155 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs)) 12156 tem = from_insn; 12157 else 12158 { 12159 if (from_insn 12160 && CALL_P (from_insn) 12161 && find_reg_fusage (from_insn, USE, XEXP (note, 0))) 12162 place = from_insn; 12163 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) 12164 place = i3; 12165 else if (i2 != 0 && next_nonnote_insn (i2) == i3 12166 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 12167 place = i2; 12168 else if ((rtx_equal_p (XEXP (note, 0), elim_i2) 12169 && !(i2mod 12170 && reg_overlap_mentioned_p (XEXP (note, 0), 12171 i2mod_old_rhs))) 12172 || rtx_equal_p (XEXP (note, 0), elim_i1)) 12173 break; 12174 tem = i3; 12175 } 12176 12177 if (place == 0) 12178 { 12179 basic_block bb = this_basic_block; 12180 12181 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem)) 12182 { 12183 if (! INSN_P (tem)) 12184 { 12185 if (tem == BB_HEAD (bb)) 12186 break; 12187 continue; 12188 } 12189 12190 /* If the register is being set at TEM, see if that is all 12191 TEM is doing. If so, delete TEM. Otherwise, make this 12192 into a REG_UNUSED note instead. Don't delete sets to 12193 global register vars. */ 12194 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER 12195 || !global_regs[REGNO (XEXP (note, 0))]) 12196 && reg_set_p (XEXP (note, 0), PATTERN (tem))) 12197 { 12198 rtx set = single_set (tem); 12199 rtx inner_dest = 0; 12200#ifdef HAVE_cc0 12201 rtx cc0_setter = NULL_RTX; 12202#endif 12203 12204 if (set != 0) 12205 for (inner_dest = SET_DEST (set); 12206 (GET_CODE (inner_dest) == STRICT_LOW_PART 12207 || GET_CODE (inner_dest) == SUBREG 12208 || GET_CODE (inner_dest) == ZERO_EXTRACT); 12209 inner_dest = XEXP (inner_dest, 0)) 12210 ; 12211 12212 /* Verify that it was the set, and not a clobber that 12213 modified the register. 12214 12215 CC0 targets must be careful to maintain setter/user 12216 pairs. If we cannot delete the setter due to side 12217 effects, mark the user with an UNUSED note instead 12218 of deleting it. */ 12219 12220 if (set != 0 && ! side_effects_p (SET_SRC (set)) 12221 && rtx_equal_p (XEXP (note, 0), inner_dest) 12222#ifdef HAVE_cc0 12223 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) 12224 || ((cc0_setter = prev_cc0_setter (tem)) != NULL 12225 && sets_cc0_p (PATTERN (cc0_setter)) > 0)) 12226#endif 12227 ) 12228 { 12229 /* Move the notes and links of TEM elsewhere. 12230 This might delete other dead insns recursively. 12231 First set the pattern to something that won't use 12232 any register. */ 12233 rtx old_notes = REG_NOTES (tem); 12234 12235 PATTERN (tem) = pc_rtx; 12236 REG_NOTES (tem) = NULL; 12237 12238 distribute_notes (old_notes, tem, tem, NULL_RTX, 12239 NULL_RTX, NULL_RTX); 12240 distribute_links (LOG_LINKS (tem)); 12241 12242 SET_INSN_DELETED (tem); 12243 12244#ifdef HAVE_cc0 12245 /* Delete the setter too. */ 12246 if (cc0_setter) 12247 { 12248 PATTERN (cc0_setter) = pc_rtx; 12249 old_notes = REG_NOTES (cc0_setter); 12250 REG_NOTES (cc0_setter) = NULL; 12251 12252 distribute_notes (old_notes, cc0_setter, 12253 cc0_setter, NULL_RTX, 12254 NULL_RTX, NULL_RTX); 12255 distribute_links (LOG_LINKS (cc0_setter)); 12256 12257 SET_INSN_DELETED (cc0_setter); 12258 } 12259#endif 12260 } 12261 else 12262 { 12263 PUT_REG_NOTE_KIND (note, REG_UNUSED); 12264 12265 /* If there isn't already a REG_UNUSED note, put one 12266 here. Do not place a REG_DEAD note, even if 12267 the register is also used here; that would not 12268 match the algorithm used in lifetime analysis 12269 and can cause the consistency check in the 12270 scheduler to fail. */ 12271 if (! find_regno_note (tem, REG_UNUSED, 12272 REGNO (XEXP (note, 0)))) 12273 place = tem; 12274 break; 12275 } 12276 } 12277 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)) 12278 || (CALL_P (tem) 12279 && find_reg_fusage (tem, USE, XEXP (note, 0)))) 12280 { 12281 place = tem; 12282 12283 /* If we are doing a 3->2 combination, and we have a 12284 register which formerly died in i3 and was not used 12285 by i2, which now no longer dies in i3 and is used in 12286 i2 but does not die in i2, and place is between i2 12287 and i3, then we may need to move a link from place to 12288 i2. */ 12289 if (i2 && INSN_UID (place) <= max_uid_cuid 12290 && INSN_CUID (place) > INSN_CUID (i2) 12291 && from_insn 12292 && INSN_CUID (from_insn) > INSN_CUID (i2) 12293 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 12294 { 12295 rtx links = LOG_LINKS (place); 12296 LOG_LINKS (place) = 0; 12297 distribute_links (links); 12298 } 12299 break; 12300 } 12301 12302 if (tem == BB_HEAD (bb)) 12303 break; 12304 } 12305 12306 /* We haven't found an insn for the death note and it 12307 is still a REG_DEAD note, but we have hit the beginning 12308 of the block. If the existing life info says the reg 12309 was dead, there's nothing left to do. Otherwise, we'll 12310 need to do a global life update after combine. */ 12311 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 12312 && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start, 12313 REGNO (XEXP (note, 0)))) 12314 SET_BIT (refresh_blocks, this_basic_block->index); 12315 } 12316 12317 /* If the register is set or already dead at PLACE, we needn't do 12318 anything with this note if it is still a REG_DEAD note. 12319 We check here if it is set at all, not if is it totally replaced, 12320 which is what `dead_or_set_p' checks, so also check for it being 12321 set partially. */ 12322 12323 if (place && REG_NOTE_KIND (note) == REG_DEAD) 12324 { 12325 unsigned int regno = REGNO (XEXP (note, 0)); 12326 12327 /* Similarly, if the instruction on which we want to place 12328 the note is a noop, we'll need do a global live update 12329 after we remove them in delete_noop_moves. */ 12330 if (noop_move_p (place)) 12331 SET_BIT (refresh_blocks, this_basic_block->index); 12332 12333 if (dead_or_set_p (place, XEXP (note, 0)) 12334 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) 12335 { 12336 /* Unless the register previously died in PLACE, clear 12337 last_death. [I no longer understand why this is 12338 being done.] */ 12339 if (reg_stat[regno].last_death != place) 12340 reg_stat[regno].last_death = 0; 12341 place = 0; 12342 } 12343 else 12344 reg_stat[regno].last_death = place; 12345 12346 /* If this is a death note for a hard reg that is occupying 12347 multiple registers, ensure that we are still using all 12348 parts of the object. If we find a piece of the object 12349 that is unused, we must arrange for an appropriate REG_DEAD 12350 note to be added for it. However, we can't just emit a USE 12351 and tag the note to it, since the register might actually 12352 be dead; so we recourse, and the recursive call then finds 12353 the previous insn that used this register. */ 12354 12355 if (place && regno < FIRST_PSEUDO_REGISTER 12356 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1) 12357 { 12358 unsigned int endregno 12359 = regno + hard_regno_nregs[regno] 12360 [GET_MODE (XEXP (note, 0))]; 12361 int all_used = 1; 12362 unsigned int i; 12363 12364 for (i = regno; i < endregno; i++) 12365 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0) 12366 && ! find_regno_fusage (place, USE, i)) 12367 || dead_or_set_regno_p (place, i)) 12368 all_used = 0; 12369 12370 if (! all_used) 12371 { 12372 /* Put only REG_DEAD notes for pieces that are 12373 not already dead or set. */ 12374 12375 for (i = regno; i < endregno; 12376 i += hard_regno_nregs[i][reg_raw_mode[i]]) 12377 { 12378 rtx piece = regno_reg_rtx[i]; 12379 basic_block bb = this_basic_block; 12380 12381 if (! dead_or_set_p (place, piece) 12382 && ! reg_bitfield_target_p (piece, 12383 PATTERN (place))) 12384 { 12385 rtx new_note 12386 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX); 12387 12388 distribute_notes (new_note, place, place, 12389 NULL_RTX, NULL_RTX, NULL_RTX); 12390 } 12391 else if (! refers_to_regno_p (i, i + 1, 12392 PATTERN (place), 0) 12393 && ! find_regno_fusage (place, USE, i)) 12394 for (tem = PREV_INSN (place); ; 12395 tem = PREV_INSN (tem)) 12396 { 12397 if (! INSN_P (tem)) 12398 { 12399 if (tem == BB_HEAD (bb)) 12400 { 12401 SET_BIT (refresh_blocks, 12402 this_basic_block->index); 12403 break; 12404 } 12405 continue; 12406 } 12407 if (dead_or_set_p (tem, piece) 12408 || reg_bitfield_target_p (piece, 12409 PATTERN (tem))) 12410 { 12411 REG_NOTES (tem) 12412 = gen_rtx_EXPR_LIST (REG_UNUSED, piece, 12413 REG_NOTES (tem)); 12414 break; 12415 } 12416 } 12417 12418 } 12419 12420 place = 0; 12421 } 12422 } 12423 } 12424 break; 12425 12426 default: 12427 /* Any other notes should not be present at this point in the 12428 compilation. */ 12429 gcc_unreachable (); 12430 } 12431 12432 if (place) 12433 { 12434 XEXP (note, 1) = REG_NOTES (place); 12435 REG_NOTES (place) = note; 12436 } 12437 else if ((REG_NOTE_KIND (note) == REG_DEAD 12438 || REG_NOTE_KIND (note) == REG_UNUSED) 12439 && REG_P (XEXP (note, 0))) 12440 REG_N_DEATHS (REGNO (XEXP (note, 0)))--; 12441 12442 if (place2) 12443 { 12444 if ((REG_NOTE_KIND (note) == REG_DEAD 12445 || REG_NOTE_KIND (note) == REG_UNUSED) 12446 && REG_P (XEXP (note, 0))) 12447 REG_N_DEATHS (REGNO (XEXP (note, 0)))++; 12448 12449 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note), 12450 GET_MODE (note), 12451 XEXP (note, 0), 12452 REG_NOTES (place2)); 12453 } 12454 } 12455} 12456 12457/* Similarly to above, distribute the LOG_LINKS that used to be present on 12458 I3, I2, and I1 to new locations. This is also called to add a link 12459 pointing at I3 when I3's destination is changed. */ 12460 12461static void 12462distribute_links (rtx links) 12463{ 12464 rtx link, next_link; 12465 12466 for (link = links; link; link = next_link) 12467 { 12468 rtx place = 0; 12469 rtx insn; 12470 rtx set, reg; 12471 12472 next_link = XEXP (link, 1); 12473 12474 /* If the insn that this link points to is a NOTE or isn't a single 12475 set, ignore it. In the latter case, it isn't clear what we 12476 can do other than ignore the link, since we can't tell which 12477 register it was for. Such links wouldn't be used by combine 12478 anyway. 12479 12480 It is not possible for the destination of the target of the link to 12481 have been changed by combine. The only potential of this is if we 12482 replace I3, I2, and I1 by I3 and I2. But in that case the 12483 destination of I2 also remains unchanged. */ 12484 12485 if (NOTE_P (XEXP (link, 0)) 12486 || (set = single_set (XEXP (link, 0))) == 0) 12487 continue; 12488 12489 reg = SET_DEST (set); 12490 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT 12491 || GET_CODE (reg) == STRICT_LOW_PART) 12492 reg = XEXP (reg, 0); 12493 12494 /* A LOG_LINK is defined as being placed on the first insn that uses 12495 a register and points to the insn that sets the register. Start 12496 searching at the next insn after the target of the link and stop 12497 when we reach a set of the register or the end of the basic block. 12498 12499 Note that this correctly handles the link that used to point from 12500 I3 to I2. Also note that not much searching is typically done here 12501 since most links don't point very far away. */ 12502 12503 for (insn = NEXT_INSN (XEXP (link, 0)); 12504 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR 12505 || BB_HEAD (this_basic_block->next_bb) != insn)); 12506 insn = NEXT_INSN (insn)) 12507 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn))) 12508 { 12509 if (reg_referenced_p (reg, PATTERN (insn))) 12510 place = insn; 12511 break; 12512 } 12513 else if (CALL_P (insn) 12514 && find_reg_fusage (insn, USE, reg)) 12515 { 12516 place = insn; 12517 break; 12518 } 12519 else if (INSN_P (insn) && reg_set_p (reg, insn)) 12520 break; 12521 12522 /* If we found a place to put the link, place it there unless there 12523 is already a link to the same insn as LINK at that point. */ 12524 12525 if (place) 12526 { 12527 rtx link2; 12528 12529 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1)) 12530 if (XEXP (link2, 0) == XEXP (link, 0)) 12531 break; 12532 12533 if (link2 == 0) 12534 { 12535 XEXP (link, 1) = LOG_LINKS (place); 12536 LOG_LINKS (place) = link; 12537 12538 /* Set added_links_insn to the earliest insn we added a 12539 link to. */ 12540 if (added_links_insn == 0 12541 || INSN_CUID (added_links_insn) > INSN_CUID (place)) 12542 added_links_insn = place; 12543 } 12544 } 12545 } 12546} 12547 12548/* Subroutine of unmentioned_reg_p and callback from for_each_rtx. 12549 Check whether the expression pointer to by LOC is a register or 12550 memory, and if so return 1 if it isn't mentioned in the rtx EXPR. 12551 Otherwise return zero. */ 12552 12553static int 12554unmentioned_reg_p_1 (rtx *loc, void *expr) 12555{ 12556 rtx x = *loc; 12557 12558 if (x != NULL_RTX 12559 && (REG_P (x) || MEM_P (x)) 12560 && ! reg_mentioned_p (x, (rtx) expr)) 12561 return 1; 12562 return 0; 12563} 12564 12565/* Check for any register or memory mentioned in EQUIV that is not 12566 mentioned in EXPR. This is used to restrict EQUIV to "specializations" 12567 of EXPR where some registers may have been replaced by constants. */ 12568 12569static bool 12570unmentioned_reg_p (rtx equiv, rtx expr) 12571{ 12572 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr); 12573} 12574 12575/* Compute INSN_CUID for INSN, which is an insn made by combine. */ 12576 12577static int 12578insn_cuid (rtx insn) 12579{ 12580 while (insn != 0 && INSN_UID (insn) > max_uid_cuid 12581 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE) 12582 insn = NEXT_INSN (insn); 12583 12584 gcc_assert (INSN_UID (insn) <= max_uid_cuid); 12585 12586 return INSN_CUID (insn); 12587} 12588 12589void 12590dump_combine_stats (FILE *file) 12591{ 12592 fprintf 12593 (file, 12594 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", 12595 combine_attempts, combine_merges, combine_extras, combine_successes); 12596} 12597 12598void 12599dump_combine_total_stats (FILE *file) 12600{ 12601 fprintf 12602 (file, 12603 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", 12604 total_attempts, total_merges, total_extras, total_successes); 12605} 12606 12607 12608static bool 12609gate_handle_combine (void) 12610{ 12611 return (optimize > 0); 12612} 12613 12614/* Try combining insns through substitution. */ 12615static unsigned int 12616rest_of_handle_combine (void) 12617{ 12618 int rebuild_jump_labels_after_combine 12619 = combine_instructions (get_insns (), max_reg_num ()); 12620 12621 /* Combining insns may have turned an indirect jump into a 12622 direct jump. Rebuild the JUMP_LABEL fields of jumping 12623 instructions. */ 12624 if (rebuild_jump_labels_after_combine) 12625 { 12626 timevar_push (TV_JUMP); 12627 rebuild_jump_labels (get_insns ()); 12628 timevar_pop (TV_JUMP); 12629 12630 delete_dead_jumptables (); 12631 cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE); 12632 } 12633 return 0; 12634} 12635 12636struct tree_opt_pass pass_combine = 12637{ 12638 "combine", /* name */ 12639 gate_handle_combine, /* gate */ 12640 rest_of_handle_combine, /* execute */ 12641 NULL, /* sub */ 12642 NULL, /* next */ 12643 0, /* static_pass_number */ 12644 TV_COMBINE, /* tv_id */ 12645 0, /* properties_required */ 12646 0, /* properties_provided */ 12647 0, /* properties_destroyed */ 12648 0, /* todo_flags_start */ 12649 TODO_dump_func | 12650 TODO_ggc_collect, /* todo_flags_finish */ 12651 'c' /* letter */ 12652}; 12653 12654