combine.c revision 90075
1/* Optimize by combining instructions for GNU compiler. 2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002 Free Software Foundation, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify it under 8the terms of the GNU General Public License as published by the Free 9Software Foundation; either version 2, or (at your option) any later 10version. 11 12GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13WARRANTY; without even the implied warranty of MERCHANTABILITY or 14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to the Free 19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2002111-1307, USA. */ 21 22/* This module is essentially the "combiner" phase of the U. of Arizona 23 Portable Optimizer, but redone to work on our list-structured 24 representation for RTL instead of their string representation. 25 26 The LOG_LINKS of each insn identify the most recent assignment 27 to each REG used in the insn. It is a list of previous insns, 28 each of which contains a SET for a REG that is used in this insn 29 and not used or set in between. LOG_LINKs never cross basic blocks. 30 They were set up by the preceding pass (lifetime analysis). 31 32 We try to combine each pair of insns joined by a logical link. 33 We also try to combine triples of insns A, B and C when 34 C has a link back to B and B has a link back to A. 35 36 LOG_LINKS does not have links for use of the CC0. They don't 37 need to, because the insn that sets the CC0 is always immediately 38 before the insn that tests it. So we always regard a branch 39 insn as having a logical link to the preceding insn. The same is true 40 for an insn explicitly using CC0. 41 42 We check (with use_crosses_set_p) to avoid combining in such a way 43 as to move a computation to a place where its value would be different. 44 45 Combination is done by mathematically substituting the previous 46 insn(s) values for the regs they set into the expressions in 47 the later insns that refer to these regs. If the result is a valid insn 48 for our target machine, according to the machine description, 49 we install it, delete the earlier insns, and update the data flow 50 information (LOG_LINKS and REG_NOTES) for what we did. 51 52 There are a few exceptions where the dataflow information created by 53 flow.c aren't completely updated: 54 55 - reg_live_length is not updated 56 - reg_n_refs is not adjusted in the rare case when a register is 57 no longer required in a computation 58 - there are extremely rare cases (see distribute_regnotes) when a 59 REG_DEAD note is lost 60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be 61 removed because there is no way to know which register it was 62 linking 63 64 To simplify substitution, we combine only when the earlier insn(s) 65 consist of only a single assignment. To simplify updating afterward, 66 we never combine when a subroutine call appears in the middle. 67 68 Since we do not represent assignments to CC0 explicitly except when that 69 is all an insn does, there is no LOG_LINKS entry in an insn that uses 70 the condition code for the insn that set the condition code. 71 Fortunately, these two insns must be consecutive. 72 Therefore, every JUMP_INSN is taken to have an implicit logical link 73 to the preceding insn. This is not quite right, since non-jumps can 74 also use the condition code; but in practice such insns would not 75 combine anyway. */ 76 77#include "config.h" 78#include "system.h" 79#include "rtl.h" 80#include "tm_p.h" 81#include "flags.h" 82#include "regs.h" 83#include "hard-reg-set.h" 84#include "basic-block.h" 85#include "insn-config.h" 86#include "function.h" 87/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ 88#include "expr.h" 89#include "insn-attr.h" 90#include "recog.h" 91#include "real.h" 92#include "toplev.h" 93 94/* It is not safe to use ordinary gen_lowpart in combine. 95 Use gen_lowpart_for_combine instead. See comments there. */ 96#define gen_lowpart dont_use_gen_lowpart_you_dummy 97 98/* Number of attempts to combine instructions in this function. */ 99 100static int combine_attempts; 101 102/* Number of attempts that got as far as substitution in this function. */ 103 104static int combine_merges; 105 106/* Number of instructions combined with added SETs in this function. */ 107 108static int combine_extras; 109 110/* Number of instructions combined in this function. */ 111 112static int combine_successes; 113 114/* Totals over entire compilation. */ 115 116static int total_attempts, total_merges, total_extras, total_successes; 117 118 119/* Vector mapping INSN_UIDs to cuids. 120 The cuids are like uids but increase monotonically always. 121 Combine always uses cuids so that it can compare them. 122 But actually renumbering the uids, which we used to do, 123 proves to be a bad idea because it makes it hard to compare 124 the dumps produced by earlier passes with those from later passes. */ 125 126static int *uid_cuid; 127static int max_uid_cuid; 128 129/* Get the cuid of an insn. */ 130 131#define INSN_CUID(INSN) \ 132(INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)]) 133 134/* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by 135 BITS_PER_WORD would invoke undefined behavior. Work around it. */ 136 137#define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \ 138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1) 139 140/* Maximum register number, which is the size of the tables below. */ 141 142static unsigned int combine_max_regno; 143 144/* Record last point of death of (hard or pseudo) register n. */ 145 146static rtx *reg_last_death; 147 148/* Record last point of modification of (hard or pseudo) register n. */ 149 150static rtx *reg_last_set; 151 152/* Record the cuid of the last insn that invalidated memory 153 (anything that writes memory, and subroutine calls, but not pushes). */ 154 155static int mem_last_set; 156 157/* Record the cuid of the last CALL_INSN 158 so we can tell whether a potential combination crosses any calls. */ 159 160static int last_call_cuid; 161 162/* When `subst' is called, this is the insn that is being modified 163 (by combining in a previous insn). The PATTERN of this insn 164 is still the old pattern partially modified and it should not be 165 looked at, but this may be used to examine the successors of the insn 166 to judge whether a simplification is valid. */ 167 168static rtx subst_insn; 169 170/* This is an insn that belongs before subst_insn, but is not currently 171 on the insn chain. */ 172 173static rtx subst_prev_insn; 174 175/* This is the lowest CUID that `subst' is currently dealing with. 176 get_last_value will not return a value if the register was set at or 177 after this CUID. If not for this mechanism, we could get confused if 178 I2 or I1 in try_combine were an insn that used the old value of a register 179 to obtain a new value. In that case, we might erroneously get the 180 new value of the register when we wanted the old one. */ 181 182static int subst_low_cuid; 183 184/* This contains any hard registers that are used in newpat; reg_dead_at_p 185 must consider all these registers to be always live. */ 186 187static HARD_REG_SET newpat_used_regs; 188 189/* This is an insn to which a LOG_LINKS entry has been added. If this 190 insn is the earlier than I2 or I3, combine should rescan starting at 191 that location. */ 192 193static rtx added_links_insn; 194 195/* Basic block number of the block in which we are performing combines. */ 196static int this_basic_block; 197 198/* A bitmap indicating which blocks had registers go dead at entry. 199 After combine, we'll need to re-do global life analysis with 200 those blocks as starting points. */ 201static sbitmap refresh_blocks; 202static int need_refresh; 203 204/* The next group of arrays allows the recording of the last value assigned 205 to (hard or pseudo) register n. We use this information to see if a 206 operation being processed is redundant given a prior operation performed 207 on the register. For example, an `and' with a constant is redundant if 208 all the zero bits are already known to be turned off. 209 210 We use an approach similar to that used by cse, but change it in the 211 following ways: 212 213 (1) We do not want to reinitialize at each label. 214 (2) It is useful, but not critical, to know the actual value assigned 215 to a register. Often just its form is helpful. 216 217 Therefore, we maintain the following arrays: 218 219 reg_last_set_value the last value assigned 220 reg_last_set_label records the value of label_tick when the 221 register was assigned 222 reg_last_set_table_tick records the value of label_tick when a 223 value using the register is assigned 224 reg_last_set_invalid set to non-zero when it is not valid 225 to use the value of this register in some 226 register's value 227 228 To understand the usage of these tables, it is important to understand 229 the distinction between the value in reg_last_set_value being valid 230 and the register being validly contained in some other expression in the 231 table. 232 233 Entry I in reg_last_set_value is valid if it is non-zero, and either 234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick. 235 236 Register I may validly appear in any expression returned for the value 237 of another register if reg_n_sets[i] is 1. It may also appear in the 238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or 239 reg_last_set_invalid[j] is zero. 240 241 If an expression is found in the table containing a register which may 242 not validly appear in an expression, the register is replaced by 243 something that won't match, (clobber (const_int 0)). 244 245 reg_last_set_invalid[i] is set non-zero when register I is being assigned 246 to and reg_last_set_table_tick[i] == label_tick. */ 247 248/* Record last value assigned to (hard or pseudo) register n. */ 249 250static rtx *reg_last_set_value; 251 252/* Record the value of label_tick when the value for register n is placed in 253 reg_last_set_value[n]. */ 254 255static int *reg_last_set_label; 256 257/* Record the value of label_tick when an expression involving register n 258 is placed in reg_last_set_value. */ 259 260static int *reg_last_set_table_tick; 261 262/* Set non-zero if references to register n in expressions should not be 263 used. */ 264 265static char *reg_last_set_invalid; 266 267/* Incremented for each label. */ 268 269static int label_tick; 270 271/* Some registers that are set more than once and used in more than one 272 basic block are nevertheless always set in similar ways. For example, 273 a QImode register may be loaded from memory in two places on a machine 274 where byte loads zero extend. 275 276 We record in the following array what we know about the nonzero 277 bits of a register, specifically which bits are known to be zero. 278 279 If an entry is zero, it means that we don't know anything special. */ 280 281static unsigned HOST_WIDE_INT *reg_nonzero_bits; 282 283/* Mode used to compute significance in reg_nonzero_bits. It is the largest 284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ 285 286static enum machine_mode nonzero_bits_mode; 287 288/* Nonzero if we know that a register has some leading bits that are always 289 equal to the sign bit. */ 290 291static unsigned char *reg_sign_bit_copies; 292 293/* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used. 294 It is zero while computing them and after combine has completed. This 295 former test prevents propagating values based on previously set values, 296 which can be incorrect if a variable is modified in a loop. */ 297 298static int nonzero_sign_valid; 299 300/* These arrays are maintained in parallel with reg_last_set_value 301 and are used to store the mode in which the register was last set, 302 the bits that were known to be zero when it was last set, and the 303 number of sign bits copies it was known to have when it was last set. */ 304 305static enum machine_mode *reg_last_set_mode; 306static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits; 307static char *reg_last_set_sign_bit_copies; 308 309/* Record one modification to rtl structure 310 to be undone by storing old_contents into *where. 311 is_int is 1 if the contents are an int. */ 312 313struct undo 314{ 315 struct undo *next; 316 int is_int; 317 union {rtx r; unsigned int i;} old_contents; 318 union {rtx *r; unsigned int *i;} where; 319}; 320 321/* Record a bunch of changes to be undone, up to MAX_UNDO of them. 322 num_undo says how many are currently recorded. 323 324 other_insn is nonzero if we have modified some other insn in the process 325 of working on subst_insn. It must be verified too. */ 326 327struct undobuf 328{ 329 struct undo *undos; 330 struct undo *frees; 331 rtx other_insn; 332}; 333 334static struct undobuf undobuf; 335 336/* Number of times the pseudo being substituted for 337 was found and replaced. */ 338 339static int n_occurrences; 340 341static void do_SUBST PARAMS ((rtx *, rtx)); 342static void do_SUBST_INT PARAMS ((unsigned int *, 343 unsigned int)); 344static void init_reg_last_arrays PARAMS ((void)); 345static void setup_incoming_promotions PARAMS ((void)); 346static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *)); 347static int cant_combine_insn_p PARAMS ((rtx)); 348static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *)); 349static int sets_function_arg_p PARAMS ((rtx)); 350static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *)); 351static int contains_muldiv PARAMS ((rtx)); 352static rtx try_combine PARAMS ((rtx, rtx, rtx, int *)); 353static void undo_all PARAMS ((void)); 354static void undo_commit PARAMS ((void)); 355static rtx *find_split_point PARAMS ((rtx *, rtx)); 356static rtx subst PARAMS ((rtx, rtx, rtx, int, int)); 357static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int)); 358static rtx simplify_if_then_else PARAMS ((rtx)); 359static rtx simplify_set PARAMS ((rtx)); 360static rtx simplify_logical PARAMS ((rtx, int)); 361static rtx expand_compound_operation PARAMS ((rtx)); 362static rtx expand_field_assignment PARAMS ((rtx)); 363static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT, 364 rtx, unsigned HOST_WIDE_INT, int, 365 int, int)); 366static rtx extract_left_shift PARAMS ((rtx, int)); 367static rtx make_compound_operation PARAMS ((rtx, enum rtx_code)); 368static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT, 369 unsigned HOST_WIDE_INT *)); 370static rtx force_to_mode PARAMS ((rtx, enum machine_mode, 371 unsigned HOST_WIDE_INT, rtx, int)); 372static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *)); 373static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx)); 374static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx)); 375static rtx make_field_assignment PARAMS ((rtx)); 376static rtx apply_distributive_law PARAMS ((rtx)); 377static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx, 378 unsigned HOST_WIDE_INT)); 379static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode)); 380static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode)); 381static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *, 382 enum rtx_code, HOST_WIDE_INT, 383 enum machine_mode, int *)); 384static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode, 385 rtx, int)); 386static int recog_for_combine PARAMS ((rtx *, rtx, rtx *)); 387static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx)); 388static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode, 389 rtx, rtx)); 390static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *)); 391static void update_table_tick PARAMS ((rtx)); 392static void record_value_for_reg PARAMS ((rtx, rtx, rtx)); 393static void check_promoted_subreg PARAMS ((rtx, rtx)); 394static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *)); 395static void record_dead_and_set_regs PARAMS ((rtx)); 396static int get_last_value_validate PARAMS ((rtx *, rtx, int, int)); 397static rtx get_last_value PARAMS ((rtx)); 398static int use_crosses_set_p PARAMS ((rtx, int)); 399static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *)); 400static int reg_dead_at_p PARAMS ((rtx, rtx)); 401static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *)); 402static int reg_bitfield_target_p PARAMS ((rtx, rtx)); 403static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx)); 404static void distribute_links PARAMS ((rtx)); 405static void mark_used_regs_combine PARAMS ((rtx)); 406static int insn_cuid PARAMS ((rtx)); 407static void record_promoted_value PARAMS ((rtx, rtx)); 408static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx)); 409static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx)); 410 411/* Substitute NEWVAL, an rtx expression, into INTO, a place in some 412 insn. The substitution can be undone by undo_all. If INTO is already 413 set to NEWVAL, do not record this change. Because computing NEWVAL might 414 also call SUBST, we have to compute it before we put anything into 415 the undo table. */ 416 417static void 418do_SUBST (into, newval) 419 rtx *into, newval; 420{ 421 struct undo *buf; 422 rtx oldval = *into; 423 424 if (oldval == newval) 425 return; 426 427 if (undobuf.frees) 428 buf = undobuf.frees, undobuf.frees = buf->next; 429 else 430 buf = (struct undo *) xmalloc (sizeof (struct undo)); 431 432 buf->is_int = 0; 433 buf->where.r = into; 434 buf->old_contents.r = oldval; 435 *into = newval; 436 437 buf->next = undobuf.undos, undobuf.undos = buf; 438} 439 440#define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL)) 441 442/* Similar to SUBST, but NEWVAL is an int expression. Note that substitution 443 for the value of a HOST_WIDE_INT value (including CONST_INT) is 444 not safe. */ 445 446static void 447do_SUBST_INT (into, newval) 448 unsigned int *into, newval; 449{ 450 struct undo *buf; 451 unsigned int oldval = *into; 452 453 if (oldval == newval) 454 return; 455 456 if (undobuf.frees) 457 buf = undobuf.frees, undobuf.frees = buf->next; 458 else 459 buf = (struct undo *) xmalloc (sizeof (struct undo)); 460 461 buf->is_int = 1; 462 buf->where.i = into; 463 buf->old_contents.i = oldval; 464 *into = newval; 465 466 buf->next = undobuf.undos, undobuf.undos = buf; 467} 468 469#define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL)) 470 471/* Main entry point for combiner. F is the first insn of the function. 472 NREGS is the first unused pseudo-reg number. 473 474 Return non-zero if the combiner has turned an indirect jump 475 instruction into a direct jump. */ 476int 477combine_instructions (f, nregs) 478 rtx f; 479 unsigned int nregs; 480{ 481 rtx insn, next; 482#ifdef HAVE_cc0 483 rtx prev; 484#endif 485 int i; 486 rtx links, nextlinks; 487 488 int new_direct_jump_p = 0; 489 490 combine_attempts = 0; 491 combine_merges = 0; 492 combine_extras = 0; 493 combine_successes = 0; 494 495 combine_max_regno = nregs; 496 497 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *) 498 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT))); 499 reg_sign_bit_copies 500 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char)); 501 502 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx)); 503 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx)); 504 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx)); 505 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int)); 506 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int)); 507 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char)); 508 reg_last_set_mode 509 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode)); 510 reg_last_set_nonzero_bits 511 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT)); 512 reg_last_set_sign_bit_copies 513 = (char *) xmalloc (nregs * sizeof (char)); 514 515 init_reg_last_arrays (); 516 517 init_recog_no_volatile (); 518 519 /* Compute maximum uid value so uid_cuid can be allocated. */ 520 521 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) 522 if (INSN_UID (insn) > i) 523 i = INSN_UID (insn); 524 525 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int)); 526 max_uid_cuid = i; 527 528 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); 529 530 /* Don't use reg_nonzero_bits when computing it. This can cause problems 531 when, for example, we have j <<= 1 in a loop. */ 532 533 nonzero_sign_valid = 0; 534 535 /* Compute the mapping from uids to cuids. 536 Cuids are numbers assigned to insns, like uids, 537 except that cuids increase monotonically through the code. 538 539 Scan all SETs and see if we can deduce anything about what 540 bits are known to be zero for some registers and how many copies 541 of the sign bit are known to exist for those registers. 542 543 Also set any known values so that we can use it while searching 544 for what bits are known to be set. */ 545 546 label_tick = 1; 547 548 /* We need to initialize it here, because record_dead_and_set_regs may call 549 get_last_value. */ 550 subst_prev_insn = NULL_RTX; 551 552 setup_incoming_promotions (); 553 554 refresh_blocks = sbitmap_alloc (n_basic_blocks); 555 sbitmap_zero (refresh_blocks); 556 need_refresh = 0; 557 558 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) 559 { 560 uid_cuid[INSN_UID (insn)] = ++i; 561 subst_low_cuid = i; 562 subst_insn = insn; 563 564 if (INSN_P (insn)) 565 { 566 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies, 567 NULL); 568 record_dead_and_set_regs (insn); 569 570#ifdef AUTO_INC_DEC 571 for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) 572 if (REG_NOTE_KIND (links) == REG_INC) 573 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX, 574 NULL); 575#endif 576 } 577 578 if (GET_CODE (insn) == CODE_LABEL) 579 label_tick++; 580 } 581 582 nonzero_sign_valid = 1; 583 584 /* Now scan all the insns in forward order. */ 585 586 this_basic_block = -1; 587 label_tick = 1; 588 last_call_cuid = 0; 589 mem_last_set = 0; 590 init_reg_last_arrays (); 591 setup_incoming_promotions (); 592 593 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn)) 594 { 595 next = 0; 596 597 /* If INSN starts a new basic block, update our basic block number. */ 598 if (this_basic_block + 1 < n_basic_blocks 599 && BLOCK_HEAD (this_basic_block + 1) == insn) 600 this_basic_block++; 601 602 if (GET_CODE (insn) == CODE_LABEL) 603 label_tick++; 604 605 else if (INSN_P (insn)) 606 { 607 /* See if we know about function return values before this 608 insn based upon SUBREG flags. */ 609 check_promoted_subreg (insn, PATTERN (insn)); 610 611 /* Try this insn with each insn it links back to. */ 612 613 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 614 if ((next = try_combine (insn, XEXP (links, 0), 615 NULL_RTX, &new_direct_jump_p)) != 0) 616 goto retry; 617 618 /* Try each sequence of three linked insns ending with this one. */ 619 620 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 621 { 622 rtx link = XEXP (links, 0); 623 624 /* If the linked insn has been replaced by a note, then there 625 is no point in pursuing this chain any further. */ 626 if (GET_CODE (link) == NOTE) 627 continue; 628 629 for (nextlinks = LOG_LINKS (link); 630 nextlinks; 631 nextlinks = XEXP (nextlinks, 1)) 632 if ((next = try_combine (insn, link, 633 XEXP (nextlinks, 0), 634 &new_direct_jump_p)) != 0) 635 goto retry; 636 } 637 638#ifdef HAVE_cc0 639 /* Try to combine a jump insn that uses CC0 640 with a preceding insn that sets CC0, and maybe with its 641 logical predecessor as well. 642 This is how we make decrement-and-branch insns. 643 We need this special code because data flow connections 644 via CC0 do not get entered in LOG_LINKS. */ 645 646 if (GET_CODE (insn) == JUMP_INSN 647 && (prev = prev_nonnote_insn (insn)) != 0 648 && GET_CODE (prev) == INSN 649 && sets_cc0_p (PATTERN (prev))) 650 { 651 if ((next = try_combine (insn, prev, 652 NULL_RTX, &new_direct_jump_p)) != 0) 653 goto retry; 654 655 for (nextlinks = LOG_LINKS (prev); nextlinks; 656 nextlinks = XEXP (nextlinks, 1)) 657 if ((next = try_combine (insn, prev, 658 XEXP (nextlinks, 0), 659 &new_direct_jump_p)) != 0) 660 goto retry; 661 } 662 663 /* Do the same for an insn that explicitly references CC0. */ 664 if (GET_CODE (insn) == INSN 665 && (prev = prev_nonnote_insn (insn)) != 0 666 && GET_CODE (prev) == INSN 667 && sets_cc0_p (PATTERN (prev)) 668 && GET_CODE (PATTERN (insn)) == SET 669 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) 670 { 671 if ((next = try_combine (insn, prev, 672 NULL_RTX, &new_direct_jump_p)) != 0) 673 goto retry; 674 675 for (nextlinks = LOG_LINKS (prev); nextlinks; 676 nextlinks = XEXP (nextlinks, 1)) 677 if ((next = try_combine (insn, prev, 678 XEXP (nextlinks, 0), 679 &new_direct_jump_p)) != 0) 680 goto retry; 681 } 682 683 /* Finally, see if any of the insns that this insn links to 684 explicitly references CC0. If so, try this insn, that insn, 685 and its predecessor if it sets CC0. */ 686 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 687 if (GET_CODE (XEXP (links, 0)) == INSN 688 && GET_CODE (PATTERN (XEXP (links, 0))) == SET 689 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0)))) 690 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0 691 && GET_CODE (prev) == INSN 692 && sets_cc0_p (PATTERN (prev)) 693 && (next = try_combine (insn, XEXP (links, 0), 694 prev, &new_direct_jump_p)) != 0) 695 goto retry; 696#endif 697 698 /* Try combining an insn with two different insns whose results it 699 uses. */ 700 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 701 for (nextlinks = XEXP (links, 1); nextlinks; 702 nextlinks = XEXP (nextlinks, 1)) 703 if ((next = try_combine (insn, XEXP (links, 0), 704 XEXP (nextlinks, 0), 705 &new_direct_jump_p)) != 0) 706 goto retry; 707 708 if (GET_CODE (insn) != NOTE) 709 record_dead_and_set_regs (insn); 710 711 retry: 712 ; 713 } 714 } 715 716 delete_noop_moves (f); 717 718 if (need_refresh) 719 { 720 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES, 721 PROP_DEATH_NOTES); 722 } 723 724 /* Clean up. */ 725 sbitmap_free (refresh_blocks); 726 free (reg_nonzero_bits); 727 free (reg_sign_bit_copies); 728 free (reg_last_death); 729 free (reg_last_set); 730 free (reg_last_set_value); 731 free (reg_last_set_table_tick); 732 free (reg_last_set_label); 733 free (reg_last_set_invalid); 734 free (reg_last_set_mode); 735 free (reg_last_set_nonzero_bits); 736 free (reg_last_set_sign_bit_copies); 737 free (uid_cuid); 738 739 { 740 struct undo *undo, *next; 741 for (undo = undobuf.frees; undo; undo = next) 742 { 743 next = undo->next; 744 free (undo); 745 } 746 undobuf.frees = 0; 747 } 748 749 total_attempts += combine_attempts; 750 total_merges += combine_merges; 751 total_extras += combine_extras; 752 total_successes += combine_successes; 753 754 nonzero_sign_valid = 0; 755 756 /* Make recognizer allow volatile MEMs again. */ 757 init_recog (); 758 759 return new_direct_jump_p; 760} 761 762/* Wipe the reg_last_xxx arrays in preparation for another pass. */ 763 764static void 765init_reg_last_arrays () 766{ 767 unsigned int nregs = combine_max_regno; 768 769 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx)); 770 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx)); 771 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx)); 772 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int)); 773 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int)); 774 memset (reg_last_set_invalid, 0, nregs * sizeof (char)); 775 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode)); 776 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT)); 777 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char)); 778} 779 780/* Set up any promoted values for incoming argument registers. */ 781 782static void 783setup_incoming_promotions () 784{ 785#ifdef PROMOTE_FUNCTION_ARGS 786 unsigned int regno; 787 rtx reg; 788 enum machine_mode mode; 789 int unsignedp; 790 rtx first = get_insns (); 791 792#ifndef OUTGOING_REGNO 793#define OUTGOING_REGNO(N) N 794#endif 795 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 796 /* Check whether this register can hold an incoming pointer 797 argument. FUNCTION_ARG_REGNO_P tests outgoing register 798 numbers, so translate if necessary due to register windows. */ 799 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno)) 800 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0) 801 { 802 record_value_for_reg 803 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND 804 : SIGN_EXTEND), 805 GET_MODE (reg), 806 gen_rtx_CLOBBER (mode, const0_rtx))); 807 } 808#endif 809} 810 811/* Called via note_stores. If X is a pseudo that is narrower than 812 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. 813 814 If we are setting only a portion of X and we can't figure out what 815 portion, assume all bits will be used since we don't know what will 816 be happening. 817 818 Similarly, set how many bits of X are known to be copies of the sign bit 819 at all locations in the function. This is the smallest number implied 820 by any set of X. */ 821 822static void 823set_nonzero_bits_and_sign_copies (x, set, data) 824 rtx x; 825 rtx set; 826 void *data ATTRIBUTE_UNUSED; 827{ 828 unsigned int num; 829 830 if (GET_CODE (x) == REG 831 && REGNO (x) >= FIRST_PSEUDO_REGISTER 832 /* If this register is undefined at the start of the file, we can't 833 say what its contents were. */ 834 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x)) 835 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) 836 { 837 if (set == 0 || GET_CODE (set) == CLOBBER) 838 { 839 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); 840 reg_sign_bit_copies[REGNO (x)] = 1; 841 return; 842 } 843 844 /* If this is a complex assignment, see if we can convert it into a 845 simple assignment. */ 846 set = expand_field_assignment (set); 847 848 /* If this is a simple assignment, or we have a paradoxical SUBREG, 849 set what we know about X. */ 850 851 if (SET_DEST (set) == x 852 || (GET_CODE (SET_DEST (set)) == SUBREG 853 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set))) 854 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set))))) 855 && SUBREG_REG (SET_DEST (set)) == x)) 856 { 857 rtx src = SET_SRC (set); 858 859#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 860 /* If X is narrower than a word and SRC is a non-negative 861 constant that would appear negative in the mode of X, 862 sign-extend it for use in reg_nonzero_bits because some 863 machines (maybe most) will actually do the sign-extension 864 and this is the conservative approach. 865 866 ??? For 2.5, try to tighten up the MD files in this regard 867 instead of this kludge. */ 868 869 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD 870 && GET_CODE (src) == CONST_INT 871 && INTVAL (src) > 0 872 && 0 != (INTVAL (src) 873 & ((HOST_WIDE_INT) 1 874 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 875 src = GEN_INT (INTVAL (src) 876 | ((HOST_WIDE_INT) (-1) 877 << GET_MODE_BITSIZE (GET_MODE (x)))); 878#endif 879 880 reg_nonzero_bits[REGNO (x)] 881 |= nonzero_bits (src, nonzero_bits_mode); 882 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); 883 if (reg_sign_bit_copies[REGNO (x)] == 0 884 || reg_sign_bit_copies[REGNO (x)] > num) 885 reg_sign_bit_copies[REGNO (x)] = num; 886 } 887 else 888 { 889 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); 890 reg_sign_bit_copies[REGNO (x)] = 1; 891 } 892 } 893} 894 895/* See if INSN can be combined into I3. PRED and SUCC are optionally 896 insns that were previously combined into I3 or that will be combined 897 into the merger of INSN and I3. 898 899 Return 0 if the combination is not allowed for any reason. 900 901 If the combination is allowed, *PDEST will be set to the single 902 destination of INSN and *PSRC to the single source, and this function 903 will return 1. */ 904 905static int 906can_combine_p (insn, i3, pred, succ, pdest, psrc) 907 rtx insn; 908 rtx i3; 909 rtx pred ATTRIBUTE_UNUSED; 910 rtx succ; 911 rtx *pdest, *psrc; 912{ 913 int i; 914 rtx set = 0, src, dest; 915 rtx p; 916#ifdef AUTO_INC_DEC 917 rtx link; 918#endif 919 int all_adjacent = (succ ? (next_active_insn (insn) == succ 920 && next_active_insn (succ) == i3) 921 : next_active_insn (insn) == i3); 922 923 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. 924 or a PARALLEL consisting of such a SET and CLOBBERs. 925 926 If INSN has CLOBBER parallel parts, ignore them for our processing. 927 By definition, these happen during the execution of the insn. When it 928 is merged with another insn, all bets are off. If they are, in fact, 929 needed and aren't also supplied in I3, they may be added by 930 recog_for_combine. Otherwise, it won't match. 931 932 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED 933 note. 934 935 Get the source and destination of INSN. If more than one, can't 936 combine. */ 937 938 if (GET_CODE (PATTERN (insn)) == SET) 939 set = PATTERN (insn); 940 else if (GET_CODE (PATTERN (insn)) == PARALLEL 941 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) 942 { 943 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) 944 { 945 rtx elt = XVECEXP (PATTERN (insn), 0, i); 946 947 switch (GET_CODE (elt)) 948 { 949 /* This is important to combine floating point insns 950 for the SH4 port. */ 951 case USE: 952 /* Combining an isolated USE doesn't make sense. 953 We depend here on combinable_i3pat to reject them. */ 954 /* The code below this loop only verifies that the inputs of 955 the SET in INSN do not change. We call reg_set_between_p 956 to verify that the REG in the USE does not change between 957 I3 and INSN. 958 If the USE in INSN was for a pseudo register, the matching 959 insn pattern will likely match any register; combining this 960 with any other USE would only be safe if we knew that the 961 used registers have identical values, or if there was 962 something to tell them apart, e.g. different modes. For 963 now, we forgo such complicated tests and simply disallow 964 combining of USES of pseudo registers with any other USE. */ 965 if (GET_CODE (XEXP (elt, 0)) == REG 966 && GET_CODE (PATTERN (i3)) == PARALLEL) 967 { 968 rtx i3pat = PATTERN (i3); 969 int i = XVECLEN (i3pat, 0) - 1; 970 unsigned int regno = REGNO (XEXP (elt, 0)); 971 972 do 973 { 974 rtx i3elt = XVECEXP (i3pat, 0, i); 975 976 if (GET_CODE (i3elt) == USE 977 && GET_CODE (XEXP (i3elt, 0)) == REG 978 && (REGNO (XEXP (i3elt, 0)) == regno 979 ? reg_set_between_p (XEXP (elt, 0), 980 PREV_INSN (insn), i3) 981 : regno >= FIRST_PSEUDO_REGISTER)) 982 return 0; 983 } 984 while (--i >= 0); 985 } 986 break; 987 988 /* We can ignore CLOBBERs. */ 989 case CLOBBER: 990 break; 991 992 case SET: 993 /* Ignore SETs whose result isn't used but not those that 994 have side-effects. */ 995 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) 996 && ! side_effects_p (elt)) 997 break; 998 999 /* If we have already found a SET, this is a second one and 1000 so we cannot combine with this insn. */ 1001 if (set) 1002 return 0; 1003 1004 set = elt; 1005 break; 1006 1007 default: 1008 /* Anything else means we can't combine. */ 1009 return 0; 1010 } 1011 } 1012 1013 if (set == 0 1014 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, 1015 so don't do anything with it. */ 1016 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) 1017 return 0; 1018 } 1019 else 1020 return 0; 1021 1022 if (set == 0) 1023 return 0; 1024 1025 set = expand_field_assignment (set); 1026 src = SET_SRC (set), dest = SET_DEST (set); 1027 1028 /* Don't eliminate a store in the stack pointer. */ 1029 if (dest == stack_pointer_rtx 1030 /* If we couldn't eliminate a field assignment, we can't combine. */ 1031 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART 1032 /* Don't combine with an insn that sets a register to itself if it has 1033 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */ 1034 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) 1035 /* Can't merge an ASM_OPERANDS. */ 1036 || GET_CODE (src) == ASM_OPERANDS 1037 /* Can't merge a function call. */ 1038 || GET_CODE (src) == CALL 1039 /* Don't eliminate a function call argument. */ 1040 || (GET_CODE (i3) == CALL_INSN 1041 && (find_reg_fusage (i3, USE, dest) 1042 || (GET_CODE (dest) == REG 1043 && REGNO (dest) < FIRST_PSEUDO_REGISTER 1044 && global_regs[REGNO (dest)]))) 1045 /* Don't substitute into an incremented register. */ 1046 || FIND_REG_INC_NOTE (i3, dest) 1047 || (succ && FIND_REG_INC_NOTE (succ, dest)) 1048#if 0 1049 /* Don't combine the end of a libcall into anything. */ 1050 /* ??? This gives worse code, and appears to be unnecessary, since no 1051 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does 1052 use REG_RETVAL notes for noconflict blocks, but other code here 1053 makes sure that those insns don't disappear. */ 1054 || find_reg_note (insn, REG_RETVAL, NULL_RTX) 1055#endif 1056 /* Make sure that DEST is not used after SUCC but before I3. */ 1057 || (succ && ! all_adjacent 1058 && reg_used_between_p (dest, succ, i3)) 1059 /* Make sure that the value that is to be substituted for the register 1060 does not use any registers whose values alter in between. However, 1061 If the insns are adjacent, a use can't cross a set even though we 1062 think it might (this can happen for a sequence of insns each setting 1063 the same destination; reg_last_set of that register might point to 1064 a NOTE). If INSN has a REG_EQUIV note, the register is always 1065 equivalent to the memory so the substitution is valid even if there 1066 are intervening stores. Also, don't move a volatile asm or 1067 UNSPEC_VOLATILE across any other insns. */ 1068 || (! all_adjacent 1069 && (((GET_CODE (src) != MEM 1070 || ! find_reg_note (insn, REG_EQUIV, src)) 1071 && use_crosses_set_p (src, INSN_CUID (insn))) 1072 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) 1073 || GET_CODE (src) == UNSPEC_VOLATILE)) 1074 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get 1075 better register allocation by not doing the combine. */ 1076 || find_reg_note (i3, REG_NO_CONFLICT, dest) 1077 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest)) 1078 /* Don't combine across a CALL_INSN, because that would possibly 1079 change whether the life span of some REGs crosses calls or not, 1080 and it is a pain to update that information. 1081 Exception: if source is a constant, moving it later can't hurt. 1082 Accept that special case, because it helps -fforce-addr a lot. */ 1083 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src))) 1084 return 0; 1085 1086 /* DEST must either be a REG or CC0. */ 1087 if (GET_CODE (dest) == REG) 1088 { 1089 /* If register alignment is being enforced for multi-word items in all 1090 cases except for parameters, it is possible to have a register copy 1091 insn referencing a hard register that is not allowed to contain the 1092 mode being copied and which would not be valid as an operand of most 1093 insns. Eliminate this problem by not combining with such an insn. 1094 1095 Also, on some machines we don't want to extend the life of a hard 1096 register. */ 1097 1098 if (GET_CODE (src) == REG 1099 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER 1100 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) 1101 /* Don't extend the life of a hard register unless it is 1102 user variable (if we have few registers) or it can't 1103 fit into the desired register (meaning something special 1104 is going on). 1105 Also avoid substituting a return register into I3, because 1106 reload can't handle a conflict with constraints of other 1107 inputs. */ 1108 || (REGNO (src) < FIRST_PSEUDO_REGISTER 1109 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))))) 1110 return 0; 1111 } 1112 else if (GET_CODE (dest) != CC0) 1113 return 0; 1114 1115 /* Don't substitute for a register intended as a clobberable operand. 1116 Similarly, don't substitute an expression containing a register that 1117 will be clobbered in I3. */ 1118 if (GET_CODE (PATTERN (i3)) == PARALLEL) 1119 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) 1120 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER 1121 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), 1122 src) 1123 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest))) 1124 return 0; 1125 1126 /* If INSN contains anything volatile, or is an `asm' (whether volatile 1127 or not), reject, unless nothing volatile comes between it and I3 */ 1128 1129 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) 1130 { 1131 /* Make sure succ doesn't contain a volatile reference. */ 1132 if (succ != 0 && volatile_refs_p (PATTERN (succ))) 1133 return 0; 1134 1135 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 1136 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p))) 1137 return 0; 1138 } 1139 1140 /* If INSN is an asm, and DEST is a hard register, reject, since it has 1141 to be an explicit register variable, and was chosen for a reason. */ 1142 1143 if (GET_CODE (src) == ASM_OPERANDS 1144 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER) 1145 return 0; 1146 1147 /* If there are any volatile insns between INSN and I3, reject, because 1148 they might affect machine state. */ 1149 1150 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 1151 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p))) 1152 return 0; 1153 1154 /* If INSN or I2 contains an autoincrement or autodecrement, 1155 make sure that register is not used between there and I3, 1156 and not already used in I3 either. 1157 Also insist that I3 not be a jump; if it were one 1158 and the incremented register were spilled, we would lose. */ 1159 1160#ifdef AUTO_INC_DEC 1161 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1162 if (REG_NOTE_KIND (link) == REG_INC 1163 && (GET_CODE (i3) == JUMP_INSN 1164 || reg_used_between_p (XEXP (link, 0), insn, i3) 1165 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) 1166 return 0; 1167#endif 1168 1169#ifdef HAVE_cc0 1170 /* Don't combine an insn that follows a CC0-setting insn. 1171 An insn that uses CC0 must not be separated from the one that sets it. 1172 We do, however, allow I2 to follow a CC0-setting insn if that insn 1173 is passed as I1; in that case it will be deleted also. 1174 We also allow combining in this case if all the insns are adjacent 1175 because that would leave the two CC0 insns adjacent as well. 1176 It would be more logical to test whether CC0 occurs inside I1 or I2, 1177 but that would be much slower, and this ought to be equivalent. */ 1178 1179 p = prev_nonnote_insn (insn); 1180 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p)) 1181 && ! all_adjacent) 1182 return 0; 1183#endif 1184 1185 /* If we get here, we have passed all the tests and the combination is 1186 to be allowed. */ 1187 1188 *pdest = dest; 1189 *psrc = src; 1190 1191 return 1; 1192} 1193 1194/* Check if PAT is an insn - or a part of it - used to set up an 1195 argument for a function in a hard register. */ 1196 1197static int 1198sets_function_arg_p (pat) 1199 rtx pat; 1200{ 1201 int i; 1202 rtx inner_dest; 1203 1204 switch (GET_CODE (pat)) 1205 { 1206 case INSN: 1207 return sets_function_arg_p (PATTERN (pat)); 1208 1209 case PARALLEL: 1210 for (i = XVECLEN (pat, 0); --i >= 0;) 1211 if (sets_function_arg_p (XVECEXP (pat, 0, i))) 1212 return 1; 1213 1214 break; 1215 1216 case SET: 1217 inner_dest = SET_DEST (pat); 1218 while (GET_CODE (inner_dest) == STRICT_LOW_PART 1219 || GET_CODE (inner_dest) == SUBREG 1220 || GET_CODE (inner_dest) == ZERO_EXTRACT) 1221 inner_dest = XEXP (inner_dest, 0); 1222 1223 return (GET_CODE (inner_dest) == REG 1224 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 1225 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest))); 1226 1227 default: 1228 break; 1229 } 1230 1231 return 0; 1232} 1233 1234/* LOC is the location within I3 that contains its pattern or the component 1235 of a PARALLEL of the pattern. We validate that it is valid for combining. 1236 1237 One problem is if I3 modifies its output, as opposed to replacing it 1238 entirely, we can't allow the output to contain I2DEST or I1DEST as doing 1239 so would produce an insn that is not equivalent to the original insns. 1240 1241 Consider: 1242 1243 (set (reg:DI 101) (reg:DI 100)) 1244 (set (subreg:SI (reg:DI 101) 0) <foo>) 1245 1246 This is NOT equivalent to: 1247 1248 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) 1249 (set (reg:DI 101) (reg:DI 100))]) 1250 1251 Not only does this modify 100 (in which case it might still be valid 1252 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. 1253 1254 We can also run into a problem if I2 sets a register that I1 1255 uses and I1 gets directly substituted into I3 (not via I2). In that 1256 case, we would be getting the wrong value of I2DEST into I3, so we 1257 must reject the combination. This case occurs when I2 and I1 both 1258 feed into I3, rather than when I1 feeds into I2, which feeds into I3. 1259 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source 1260 of a SET must prevent combination from occurring. 1261 1262 Before doing the above check, we first try to expand a field assignment 1263 into a set of logical operations. 1264 1265 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which 1266 we place a register that is both set and used within I3. If more than one 1267 such register is detected, we fail. 1268 1269 Return 1 if the combination is valid, zero otherwise. */ 1270 1271static int 1272combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed) 1273 rtx i3; 1274 rtx *loc; 1275 rtx i2dest; 1276 rtx i1dest; 1277 int i1_not_in_src; 1278 rtx *pi3dest_killed; 1279{ 1280 rtx x = *loc; 1281 1282 if (GET_CODE (x) == SET) 1283 { 1284 rtx set = expand_field_assignment (x); 1285 rtx dest = SET_DEST (set); 1286 rtx src = SET_SRC (set); 1287 rtx inner_dest = dest; 1288 1289#if 0 1290 rtx inner_src = src; 1291#endif 1292 1293 SUBST (*loc, set); 1294 1295 while (GET_CODE (inner_dest) == STRICT_LOW_PART 1296 || GET_CODE (inner_dest) == SUBREG 1297 || GET_CODE (inner_dest) == ZERO_EXTRACT) 1298 inner_dest = XEXP (inner_dest, 0); 1299 1300 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS 1301 was added. */ 1302#if 0 1303 while (GET_CODE (inner_src) == STRICT_LOW_PART 1304 || GET_CODE (inner_src) == SUBREG 1305 || GET_CODE (inner_src) == ZERO_EXTRACT) 1306 inner_src = XEXP (inner_src, 0); 1307 1308 /* If it is better that two different modes keep two different pseudos, 1309 avoid combining them. This avoids producing the following pattern 1310 on a 386: 1311 (set (subreg:SI (reg/v:QI 21) 0) 1312 (lshiftrt:SI (reg/v:SI 20) 1313 (const_int 24))) 1314 If that were made, reload could not handle the pair of 1315 reg 20/21, since it would try to get any GENERAL_REGS 1316 but some of them don't handle QImode. */ 1317 1318 if (rtx_equal_p (inner_src, i2dest) 1319 && GET_CODE (inner_dest) == REG 1320 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest))) 1321 return 0; 1322#endif 1323 1324 /* Check for the case where I3 modifies its output, as 1325 discussed above. */ 1326 if ((inner_dest != dest 1327 && (reg_overlap_mentioned_p (i2dest, inner_dest) 1328 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) 1329 1330 /* This is the same test done in can_combine_p except we can't test 1331 all_adjacent; we don't have to, since this instruction will stay 1332 in place, thus we are not considering increasing the lifetime of 1333 INNER_DEST. 1334 1335 Also, if this insn sets a function argument, combining it with 1336 something that might need a spill could clobber a previous 1337 function argument; the all_adjacent test in can_combine_p also 1338 checks this; here, we do a more specific test for this case. */ 1339 1340 || (GET_CODE (inner_dest) == REG 1341 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 1342 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), 1343 GET_MODE (inner_dest)))) 1344 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) 1345 return 0; 1346 1347 /* If DEST is used in I3, it is being killed in this insn, 1348 so record that for later. 1349 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the 1350 STACK_POINTER_REGNUM, since these are always considered to be 1351 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ 1352 if (pi3dest_killed && GET_CODE (dest) == REG 1353 && reg_referenced_p (dest, PATTERN (i3)) 1354 && REGNO (dest) != FRAME_POINTER_REGNUM 1355#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 1356 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM 1357#endif 1358#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM 1359 && (REGNO (dest) != ARG_POINTER_REGNUM 1360 || ! fixed_regs [REGNO (dest)]) 1361#endif 1362 && REGNO (dest) != STACK_POINTER_REGNUM) 1363 { 1364 if (*pi3dest_killed) 1365 return 0; 1366 1367 *pi3dest_killed = dest; 1368 } 1369 } 1370 1371 else if (GET_CODE (x) == PARALLEL) 1372 { 1373 int i; 1374 1375 for (i = 0; i < XVECLEN (x, 0); i++) 1376 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, 1377 i1_not_in_src, pi3dest_killed)) 1378 return 0; 1379 } 1380 1381 return 1; 1382} 1383 1384/* Return 1 if X is an arithmetic expression that contains a multiplication 1385 and division. We don't count multiplications by powers of two here. */ 1386 1387static int 1388contains_muldiv (x) 1389 rtx x; 1390{ 1391 switch (GET_CODE (x)) 1392 { 1393 case MOD: case DIV: case UMOD: case UDIV: 1394 return 1; 1395 1396 case MULT: 1397 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT 1398 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0); 1399 default: 1400 switch (GET_RTX_CLASS (GET_CODE (x))) 1401 { 1402 case 'c': case '<': case '2': 1403 return contains_muldiv (XEXP (x, 0)) 1404 || contains_muldiv (XEXP (x, 1)); 1405 1406 case '1': 1407 return contains_muldiv (XEXP (x, 0)); 1408 1409 default: 1410 return 0; 1411 } 1412 } 1413} 1414 1415/* Determine whether INSN can be used in a combination. Return nonzero if 1416 not. This is used in try_combine to detect early some cases where we 1417 can't perform combinations. */ 1418 1419static int 1420cant_combine_insn_p (insn) 1421 rtx insn; 1422{ 1423 rtx set; 1424 rtx src, dest; 1425 1426 /* If this isn't really an insn, we can't do anything. 1427 This can occur when flow deletes an insn that it has merged into an 1428 auto-increment address. */ 1429 if (! INSN_P (insn)) 1430 return 1; 1431 1432 /* Never combine loads and stores involving hard regs. The register 1433 allocator can usually handle such reg-reg moves by tying. If we allow 1434 the combiner to make substitutions of hard regs, we risk aborting in 1435 reload on machines that have SMALL_REGISTER_CLASSES. 1436 As an exception, we allow combinations involving fixed regs; these are 1437 not available to the register allocator so there's no risk involved. */ 1438 1439 set = single_set (insn); 1440 if (! set) 1441 return 0; 1442 src = SET_SRC (set); 1443 dest = SET_DEST (set); 1444 if (GET_CODE (src) == SUBREG) 1445 src = SUBREG_REG (src); 1446 if (GET_CODE (dest) == SUBREG) 1447 dest = SUBREG_REG (dest); 1448 if (REG_P (src) && REG_P (dest) 1449 && ((REGNO (src) < FIRST_PSEUDO_REGISTER 1450 && ! fixed_regs[REGNO (src)]) 1451 || (REGNO (dest) < FIRST_PSEUDO_REGISTER 1452 && ! fixed_regs[REGNO (dest)]))) 1453 return 1; 1454 1455 return 0; 1456} 1457 1458/* Try to combine the insns I1 and I2 into I3. 1459 Here I1 and I2 appear earlier than I3. 1460 I1 can be zero; then we combine just I2 into I3. 1461 1462 If we are combining three insns and the resulting insn is not recognized, 1463 try splitting it into two insns. If that happens, I2 and I3 are retained 1464 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2 1465 are pseudo-deleted. 1466 1467 Return 0 if the combination does not work. Then nothing is changed. 1468 If we did the combination, return the insn at which combine should 1469 resume scanning. 1470 1471 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a 1472 new direct jump instruction. */ 1473 1474static rtx 1475try_combine (i3, i2, i1, new_direct_jump_p) 1476 rtx i3, i2, i1; 1477 int *new_direct_jump_p; 1478{ 1479 /* New patterns for I3 and I2, respectively. */ 1480 rtx newpat, newi2pat = 0; 1481 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */ 1482 int added_sets_1, added_sets_2; 1483 /* Total number of SETs to put into I3. */ 1484 int total_sets; 1485 /* Nonzero is I2's body now appears in I3. */ 1486 int i2_is_used; 1487 /* INSN_CODEs for new I3, new I2, and user of condition code. */ 1488 int insn_code_number, i2_code_number = 0, other_code_number = 0; 1489 /* Contains I3 if the destination of I3 is used in its source, which means 1490 that the old life of I3 is being killed. If that usage is placed into 1491 I2 and not in I3, a REG_DEAD note must be made. */ 1492 rtx i3dest_killed = 0; 1493 /* SET_DEST and SET_SRC of I2 and I1. */ 1494 rtx i2dest, i2src, i1dest = 0, i1src = 0; 1495 /* PATTERN (I2), or a copy of it in certain cases. */ 1496 rtx i2pat; 1497 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ 1498 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; 1499 int i1_feeds_i3 = 0; 1500 /* Notes that must be added to REG_NOTES in I3 and I2. */ 1501 rtx new_i3_notes, new_i2_notes; 1502 /* Notes that we substituted I3 into I2 instead of the normal case. */ 1503 int i3_subst_into_i2 = 0; 1504 /* Notes that I1, I2 or I3 is a MULT operation. */ 1505 int have_mult = 0; 1506 1507 int maxreg; 1508 rtx temp; 1509 rtx link; 1510 int i; 1511 1512 /* Exit early if one of the insns involved can't be used for 1513 combinations. */ 1514 if (cant_combine_insn_p (i3) 1515 || cant_combine_insn_p (i2) 1516 || (i1 && cant_combine_insn_p (i1)) 1517 /* We also can't do anything if I3 has a 1518 REG_LIBCALL note since we don't want to disrupt the contiguity of a 1519 libcall. */ 1520#if 0 1521 /* ??? This gives worse code, and appears to be unnecessary, since no 1522 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */ 1523 || find_reg_note (i3, REG_LIBCALL, NULL_RTX) 1524#endif 1525 ) 1526 return 0; 1527 1528 combine_attempts++; 1529 undobuf.other_insn = 0; 1530 1531 /* Reset the hard register usage information. */ 1532 CLEAR_HARD_REG_SET (newpat_used_regs); 1533 1534 /* If I1 and I2 both feed I3, they can be in any order. To simplify the 1535 code below, set I1 to be the earlier of the two insns. */ 1536 if (i1 && INSN_CUID (i1) > INSN_CUID (i2)) 1537 temp = i1, i1 = i2, i2 = temp; 1538 1539 added_links_insn = 0; 1540 1541 /* First check for one important special-case that the code below will 1542 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL 1543 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, 1544 we may be able to replace that destination with the destination of I3. 1545 This occurs in the common code where we compute both a quotient and 1546 remainder into a structure, in which case we want to do the computation 1547 directly into the structure to avoid register-register copies. 1548 1549 Note that this case handles both multiple sets in I2 and also 1550 cases where I2 has a number of CLOBBER or PARALLELs. 1551 1552 We make very conservative checks below and only try to handle the 1553 most common cases of this. For example, we only handle the case 1554 where I2 and I3 are adjacent to avoid making difficult register 1555 usage tests. */ 1556 1557 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET 1558 && GET_CODE (SET_SRC (PATTERN (i3))) == REG 1559 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER 1560 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) 1561 && GET_CODE (PATTERN (i2)) == PARALLEL 1562 && ! side_effects_p (SET_DEST (PATTERN (i3))) 1563 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code 1564 below would need to check what is inside (and reg_overlap_mentioned_p 1565 doesn't support those codes anyway). Don't allow those destinations; 1566 the resulting insn isn't likely to be recognized anyway. */ 1567 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT 1568 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART 1569 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), 1570 SET_DEST (PATTERN (i3))) 1571 && next_real_insn (i2) == i3) 1572 { 1573 rtx p2 = PATTERN (i2); 1574 1575 /* Make sure that the destination of I3, 1576 which we are going to substitute into one output of I2, 1577 is not used within another output of I2. We must avoid making this: 1578 (parallel [(set (mem (reg 69)) ...) 1579 (set (reg 69) ...)]) 1580 which is not well-defined as to order of actions. 1581 (Besides, reload can't handle output reloads for this.) 1582 1583 The problem can also happen if the dest of I3 is a memory ref, 1584 if another dest in I2 is an indirect memory ref. */ 1585 for (i = 0; i < XVECLEN (p2, 0); i++) 1586 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET 1587 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) 1588 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), 1589 SET_DEST (XVECEXP (p2, 0, i)))) 1590 break; 1591 1592 if (i == XVECLEN (p2, 0)) 1593 for (i = 0; i < XVECLEN (p2, 0); i++) 1594 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET 1595 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) 1596 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) 1597 { 1598 combine_merges++; 1599 1600 subst_insn = i3; 1601 subst_low_cuid = INSN_CUID (i2); 1602 1603 added_sets_2 = added_sets_1 = 0; 1604 i2dest = SET_SRC (PATTERN (i3)); 1605 1606 /* Replace the dest in I2 with our dest and make the resulting 1607 insn the new pattern for I3. Then skip to where we 1608 validate the pattern. Everything was set up above. */ 1609 SUBST (SET_DEST (XVECEXP (p2, 0, i)), 1610 SET_DEST (PATTERN (i3))); 1611 1612 newpat = p2; 1613 i3_subst_into_i2 = 1; 1614 goto validate_replacement; 1615 } 1616 } 1617 1618 /* If I2 is setting a double-word pseudo to a constant and I3 is setting 1619 one of those words to another constant, merge them by making a new 1620 constant. */ 1621 if (i1 == 0 1622 && (temp = single_set (i2)) != 0 1623 && (GET_CODE (SET_SRC (temp)) == CONST_INT 1624 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE) 1625 && GET_CODE (SET_DEST (temp)) == REG 1626 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT 1627 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD 1628 && GET_CODE (PATTERN (i3)) == SET 1629 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG 1630 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp) 1631 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT 1632 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD 1633 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT) 1634 { 1635 HOST_WIDE_INT lo, hi; 1636 1637 if (GET_CODE (SET_SRC (temp)) == CONST_INT) 1638 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0; 1639 else 1640 { 1641 lo = CONST_DOUBLE_LOW (SET_SRC (temp)); 1642 hi = CONST_DOUBLE_HIGH (SET_SRC (temp)); 1643 } 1644 1645 if (subreg_lowpart_p (SET_DEST (PATTERN (i3)))) 1646 { 1647 /* We don't handle the case of the target word being wider 1648 than a host wide int. */ 1649 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD) 1650 abort (); 1651 1652 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1); 1653 lo |= (INTVAL (SET_SRC (PATTERN (i3))) 1654 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1)); 1655 } 1656 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) 1657 hi = INTVAL (SET_SRC (PATTERN (i3))); 1658 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD) 1659 { 1660 int sign = -(int) ((unsigned HOST_WIDE_INT) lo 1661 >> (HOST_BITS_PER_WIDE_INT - 1)); 1662 1663 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD 1664 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1)); 1665 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD 1666 (INTVAL (SET_SRC (PATTERN (i3))))); 1667 if (hi == sign) 1668 hi = lo < 0 ? -1 : 0; 1669 } 1670 else 1671 /* We don't handle the case of the higher word not fitting 1672 entirely in either hi or lo. */ 1673 abort (); 1674 1675 combine_merges++; 1676 subst_insn = i3; 1677 subst_low_cuid = INSN_CUID (i2); 1678 added_sets_2 = added_sets_1 = 0; 1679 i2dest = SET_DEST (temp); 1680 1681 SUBST (SET_SRC (temp), 1682 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp)))); 1683 1684 newpat = PATTERN (i2); 1685 goto validate_replacement; 1686 } 1687 1688#ifndef HAVE_cc0 1689 /* If we have no I1 and I2 looks like: 1690 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) 1691 (set Y OP)]) 1692 make up a dummy I1 that is 1693 (set Y OP) 1694 and change I2 to be 1695 (set (reg:CC X) (compare:CC Y (const_int 0))) 1696 1697 (We can ignore any trailing CLOBBERs.) 1698 1699 This undoes a previous combination and allows us to match a branch-and- 1700 decrement insn. */ 1701 1702 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL 1703 && XVECLEN (PATTERN (i2), 0) >= 2 1704 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET 1705 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) 1706 == MODE_CC) 1707 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE 1708 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx 1709 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET 1710 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG 1711 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), 1712 SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) 1713 { 1714 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) 1715 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) 1716 break; 1717 1718 if (i == 1) 1719 { 1720 /* We make I1 with the same INSN_UID as I2. This gives it 1721 the same INSN_CUID for value tracking. Our fake I1 will 1722 never appear in the insn stream so giving it the same INSN_UID 1723 as I2 will not cause a problem. */ 1724 1725 subst_prev_insn = i1 1726 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2, 1727 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, 1728 NULL_RTX); 1729 1730 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); 1731 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), 1732 SET_DEST (PATTERN (i1))); 1733 } 1734 } 1735#endif 1736 1737 /* Verify that I2 and I1 are valid for combining. */ 1738 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src) 1739 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src))) 1740 { 1741 undo_all (); 1742 return 0; 1743 } 1744 1745 /* Record whether I2DEST is used in I2SRC and similarly for the other 1746 cases. Knowing this will help in register status updating below. */ 1747 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); 1748 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); 1749 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); 1750 1751 /* See if I1 directly feeds into I3. It does if I1DEST is not used 1752 in I2SRC. */ 1753 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); 1754 1755 /* Ensure that I3's pattern can be the destination of combines. */ 1756 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, 1757 i1 && i2dest_in_i1src && i1_feeds_i3, 1758 &i3dest_killed)) 1759 { 1760 undo_all (); 1761 return 0; 1762 } 1763 1764 /* See if any of the insns is a MULT operation. Unless one is, we will 1765 reject a combination that is, since it must be slower. Be conservative 1766 here. */ 1767 if (GET_CODE (i2src) == MULT 1768 || (i1 != 0 && GET_CODE (i1src) == MULT) 1769 || (GET_CODE (PATTERN (i3)) == SET 1770 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) 1771 have_mult = 1; 1772 1773 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. 1774 We used to do this EXCEPT in one case: I3 has a post-inc in an 1775 output operand. However, that exception can give rise to insns like 1776 mov r3,(r3)+ 1777 which is a famous insn on the PDP-11 where the value of r3 used as the 1778 source was model-dependent. Avoid this sort of thing. */ 1779 1780#if 0 1781 if (!(GET_CODE (PATTERN (i3)) == SET 1782 && GET_CODE (SET_SRC (PATTERN (i3))) == REG 1783 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM 1784 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC 1785 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) 1786 /* It's not the exception. */ 1787#endif 1788#ifdef AUTO_INC_DEC 1789 for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) 1790 if (REG_NOTE_KIND (link) == REG_INC 1791 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) 1792 || (i1 != 0 1793 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) 1794 { 1795 undo_all (); 1796 return 0; 1797 } 1798#endif 1799 1800 /* See if the SETs in I1 or I2 need to be kept around in the merged 1801 instruction: whenever the value set there is still needed past I3. 1802 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3. 1803 1804 For the SET in I1, we have two cases: If I1 and I2 independently 1805 feed into I3, the set in I1 needs to be kept around if I1DEST dies 1806 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set 1807 in I1 needs to be kept around unless I1DEST dies or is set in either 1808 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions 1809 I1DEST. If so, we know I1 feeds into I2. */ 1810 1811 added_sets_2 = ! dead_or_set_p (i3, i2dest); 1812 1813 added_sets_1 1814 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) 1815 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); 1816 1817 /* If the set in I2 needs to be kept around, we must make a copy of 1818 PATTERN (I2), so that when we substitute I1SRC for I1DEST in 1819 PATTERN (I2), we are only substituting for the original I1DEST, not into 1820 an already-substituted copy. This also prevents making self-referential 1821 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to 1822 I2DEST. */ 1823 1824 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL 1825 ? gen_rtx_SET (VOIDmode, i2dest, i2src) 1826 : PATTERN (i2)); 1827 1828 if (added_sets_2) 1829 i2pat = copy_rtx (i2pat); 1830 1831 combine_merges++; 1832 1833 /* Substitute in the latest insn for the regs set by the earlier ones. */ 1834 1835 maxreg = max_reg_num (); 1836 1837 subst_insn = i3; 1838 1839 /* It is possible that the source of I2 or I1 may be performing an 1840 unneeded operation, such as a ZERO_EXTEND of something that is known 1841 to have the high part zero. Handle that case by letting subst look at 1842 the innermost one of them. 1843 1844 Another way to do this would be to have a function that tries to 1845 simplify a single insn instead of merging two or more insns. We don't 1846 do this because of the potential of infinite loops and because 1847 of the potential extra memory required. However, doing it the way 1848 we are is a bit of a kludge and doesn't catch all cases. 1849 1850 But only do this if -fexpensive-optimizations since it slows things down 1851 and doesn't usually win. */ 1852 1853 if (flag_expensive_optimizations) 1854 { 1855 /* Pass pc_rtx so no substitutions are done, just simplifications. 1856 The cases that we are interested in here do not involve the few 1857 cases were is_replaced is checked. */ 1858 if (i1) 1859 { 1860 subst_low_cuid = INSN_CUID (i1); 1861 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); 1862 } 1863 else 1864 { 1865 subst_low_cuid = INSN_CUID (i2); 1866 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); 1867 } 1868 } 1869 1870#ifndef HAVE_cc0 1871 /* Many machines that don't use CC0 have insns that can both perform an 1872 arithmetic operation and set the condition code. These operations will 1873 be represented as a PARALLEL with the first element of the vector 1874 being a COMPARE of an arithmetic operation with the constant zero. 1875 The second element of the vector will set some pseudo to the result 1876 of the same arithmetic operation. If we simplify the COMPARE, we won't 1877 match such a pattern and so will generate an extra insn. Here we test 1878 for this case, where both the comparison and the operation result are 1879 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with 1880 I2SRC. Later we will make the PARALLEL that contains I2. */ 1881 1882 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET 1883 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE 1884 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx 1885 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) 1886 { 1887#ifdef EXTRA_CC_MODES 1888 rtx *cc_use; 1889 enum machine_mode compare_mode; 1890#endif 1891 1892 newpat = PATTERN (i3); 1893 SUBST (XEXP (SET_SRC (newpat), 0), i2src); 1894 1895 i2_is_used = 1; 1896 1897#ifdef EXTRA_CC_MODES 1898 /* See if a COMPARE with the operand we substituted in should be done 1899 with the mode that is currently being used. If not, do the same 1900 processing we do in `subst' for a SET; namely, if the destination 1901 is used only once, try to replace it with a register of the proper 1902 mode and also replace the COMPARE. */ 1903 if (undobuf.other_insn == 0 1904 && (cc_use = find_single_use (SET_DEST (newpat), i3, 1905 &undobuf.other_insn)) 1906 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), 1907 i2src, const0_rtx)) 1908 != GET_MODE (SET_DEST (newpat)))) 1909 { 1910 unsigned int regno = REGNO (SET_DEST (newpat)); 1911 rtx new_dest = gen_rtx_REG (compare_mode, regno); 1912 1913 if (regno < FIRST_PSEUDO_REGISTER 1914 || (REG_N_SETS (regno) == 1 && ! added_sets_2 1915 && ! REG_USERVAR_P (SET_DEST (newpat)))) 1916 { 1917 if (regno >= FIRST_PSEUDO_REGISTER) 1918 SUBST (regno_reg_rtx[regno], new_dest); 1919 1920 SUBST (SET_DEST (newpat), new_dest); 1921 SUBST (XEXP (*cc_use, 0), new_dest); 1922 SUBST (SET_SRC (newpat), 1923 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx)); 1924 } 1925 else 1926 undobuf.other_insn = 0; 1927 } 1928#endif 1929 } 1930 else 1931#endif 1932 { 1933 n_occurrences = 0; /* `subst' counts here */ 1934 1935 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we 1936 need to make a unique copy of I2SRC each time we substitute it 1937 to avoid self-referential rtl. */ 1938 1939 subst_low_cuid = INSN_CUID (i2); 1940 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 1941 ! i1_feeds_i3 && i1dest_in_i1src); 1942 1943 /* Record whether i2's body now appears within i3's body. */ 1944 i2_is_used = n_occurrences; 1945 } 1946 1947 /* If we already got a failure, don't try to do more. Otherwise, 1948 try to substitute in I1 if we have it. */ 1949 1950 if (i1 && GET_CODE (newpat) != CLOBBER) 1951 { 1952 /* Before we can do this substitution, we must redo the test done 1953 above (see detailed comments there) that ensures that I1DEST 1954 isn't mentioned in any SETs in NEWPAT that are field assignments. */ 1955 1956 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 1957 0, (rtx*) 0)) 1958 { 1959 undo_all (); 1960 return 0; 1961 } 1962 1963 n_occurrences = 0; 1964 subst_low_cuid = INSN_CUID (i1); 1965 newpat = subst (newpat, i1dest, i1src, 0, 0); 1966 } 1967 1968 /* Fail if an autoincrement side-effect has been duplicated. Be careful 1969 to count all the ways that I2SRC and I1SRC can be used. */ 1970 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 1971 && i2_is_used + added_sets_2 > 1) 1972 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 1973 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) 1974 > 1)) 1975 /* Fail if we tried to make a new register (we used to abort, but there's 1976 really no reason to). */ 1977 || max_reg_num () != maxreg 1978 /* Fail if we couldn't do something and have a CLOBBER. */ 1979 || GET_CODE (newpat) == CLOBBER 1980 /* Fail if this new pattern is a MULT and we didn't have one before 1981 at the outer level. */ 1982 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT 1983 && ! have_mult)) 1984 { 1985 undo_all (); 1986 return 0; 1987 } 1988 1989 /* If the actions of the earlier insns must be kept 1990 in addition to substituting them into the latest one, 1991 we must make a new PARALLEL for the latest insn 1992 to hold additional the SETs. */ 1993 1994 if (added_sets_1 || added_sets_2) 1995 { 1996 combine_extras++; 1997 1998 if (GET_CODE (newpat) == PARALLEL) 1999 { 2000 rtvec old = XVEC (newpat, 0); 2001 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2; 2002 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 2003 memcpy (XVEC (newpat, 0)->elem, &old->elem[0], 2004 sizeof (old->elem[0]) * old->num_elem); 2005 } 2006 else 2007 { 2008 rtx old = newpat; 2009 total_sets = 1 + added_sets_1 + added_sets_2; 2010 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 2011 XVECEXP (newpat, 0, 0) = old; 2012 } 2013 2014 if (added_sets_1) 2015 XVECEXP (newpat, 0, --total_sets) 2016 = (GET_CODE (PATTERN (i1)) == PARALLEL 2017 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1)); 2018 2019 if (added_sets_2) 2020 { 2021 /* If there is no I1, use I2's body as is. We used to also not do 2022 the subst call below if I2 was substituted into I3, 2023 but that could lose a simplification. */ 2024 if (i1 == 0) 2025 XVECEXP (newpat, 0, --total_sets) = i2pat; 2026 else 2027 /* See comment where i2pat is assigned. */ 2028 XVECEXP (newpat, 0, --total_sets) 2029 = subst (i2pat, i1dest, i1src, 0, 0); 2030 } 2031 } 2032 2033 /* We come here when we are replacing a destination in I2 with the 2034 destination of I3. */ 2035 validate_replacement: 2036 2037 /* Note which hard regs this insn has as inputs. */ 2038 mark_used_regs_combine (newpat); 2039 2040 /* Is the result of combination a valid instruction? */ 2041 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2042 2043 /* If the result isn't valid, see if it is a PARALLEL of two SETs where 2044 the second SET's destination is a register that is unused. In that case, 2045 we just need the first SET. This can occur when simplifying a divmod 2046 insn. We *must* test for this case here because the code below that 2047 splits two independent SETs doesn't handle this case correctly when it 2048 updates the register status. Also check the case where the first 2049 SET's destination is unused. That would not cause incorrect code, but 2050 does cause an unneeded insn to remain. */ 2051 2052 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL 2053 && XVECLEN (newpat, 0) == 2 2054 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2055 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2056 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG 2057 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1))) 2058 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1))) 2059 && asm_noperands (newpat) < 0) 2060 { 2061 newpat = XVECEXP (newpat, 0, 0); 2062 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2063 } 2064 2065 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL 2066 && XVECLEN (newpat, 0) == 2 2067 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2068 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2069 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG 2070 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0))) 2071 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0))) 2072 && asm_noperands (newpat) < 0) 2073 { 2074 newpat = XVECEXP (newpat, 0, 1); 2075 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2076 } 2077 2078 /* If we were combining three insns and the result is a simple SET 2079 with no ASM_OPERANDS that wasn't recognized, try to split it into two 2080 insns. There are two ways to do this. It can be split using a 2081 machine-specific method (like when you have an addition of a large 2082 constant) or by combine in the function find_split_point. */ 2083 2084 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET 2085 && asm_noperands (newpat) < 0) 2086 { 2087 rtx m_split, *split; 2088 rtx ni2dest = i2dest; 2089 2090 /* See if the MD file can split NEWPAT. If it can't, see if letting it 2091 use I2DEST as a scratch register will help. In the latter case, 2092 convert I2DEST to the mode of the source of NEWPAT if we can. */ 2093 2094 m_split = split_insns (newpat, i3); 2095 2096 /* We can only use I2DEST as a scratch reg if it doesn't overlap any 2097 inputs of NEWPAT. */ 2098 2099 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be 2100 possible to try that as a scratch reg. This would require adding 2101 more code to make it work though. */ 2102 2103 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat)) 2104 { 2105 /* If I2DEST is a hard register or the only use of a pseudo, 2106 we can change its mode. */ 2107 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest) 2108 && GET_MODE (SET_DEST (newpat)) != VOIDmode 2109 && GET_CODE (i2dest) == REG 2110 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER 2111 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2 2112 && ! REG_USERVAR_P (i2dest)))) 2113 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)), 2114 REGNO (i2dest)); 2115 2116 m_split = split_insns (gen_rtx_PARALLEL 2117 (VOIDmode, 2118 gen_rtvec (2, newpat, 2119 gen_rtx_CLOBBER (VOIDmode, 2120 ni2dest))), 2121 i3); 2122 /* If the split with the mode-changed register didn't work, try 2123 the original register. */ 2124 if (! m_split && ni2dest != i2dest) 2125 { 2126 ni2dest = i2dest; 2127 m_split = split_insns (gen_rtx_PARALLEL 2128 (VOIDmode, 2129 gen_rtvec (2, newpat, 2130 gen_rtx_CLOBBER (VOIDmode, 2131 i2dest))), 2132 i3); 2133 } 2134 } 2135 2136 /* If we've split a jump pattern, we'll wind up with a sequence even 2137 with one instruction. We can handle that below, so extract it. */ 2138 if (m_split && GET_CODE (m_split) == SEQUENCE 2139 && XVECLEN (m_split, 0) == 1) 2140 m_split = PATTERN (XVECEXP (m_split, 0, 0)); 2141 2142 if (m_split && GET_CODE (m_split) != SEQUENCE) 2143 { 2144 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes); 2145 if (insn_code_number >= 0) 2146 newpat = m_split; 2147 } 2148 else if (m_split && GET_CODE (m_split) == SEQUENCE 2149 && XVECLEN (m_split, 0) == 2 2150 && (next_real_insn (i2) == i3 2151 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)), 2152 INSN_CUID (i2)))) 2153 { 2154 rtx i2set, i3set; 2155 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1)); 2156 newi2pat = PATTERN (XVECEXP (m_split, 0, 0)); 2157 2158 i3set = single_set (XVECEXP (m_split, 0, 1)); 2159 i2set = single_set (XVECEXP (m_split, 0, 0)); 2160 2161 /* In case we changed the mode of I2DEST, replace it in the 2162 pseudo-register table here. We can't do it above in case this 2163 code doesn't get executed and we do a split the other way. */ 2164 2165 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 2166 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest); 2167 2168 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2169 2170 /* If I2 or I3 has multiple SETs, we won't know how to track 2171 register status, so don't use these insns. If I2's destination 2172 is used between I2 and I3, we also can't use these insns. */ 2173 2174 if (i2_code_number >= 0 && i2set && i3set 2175 && (next_real_insn (i2) == i3 2176 || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) 2177 insn_code_number = recog_for_combine (&newi3pat, i3, 2178 &new_i3_notes); 2179 if (insn_code_number >= 0) 2180 newpat = newi3pat; 2181 2182 /* It is possible that both insns now set the destination of I3. 2183 If so, we must show an extra use of it. */ 2184 2185 if (insn_code_number >= 0) 2186 { 2187 rtx new_i3_dest = SET_DEST (i3set); 2188 rtx new_i2_dest = SET_DEST (i2set); 2189 2190 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT 2191 || GET_CODE (new_i3_dest) == STRICT_LOW_PART 2192 || GET_CODE (new_i3_dest) == SUBREG) 2193 new_i3_dest = XEXP (new_i3_dest, 0); 2194 2195 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT 2196 || GET_CODE (new_i2_dest) == STRICT_LOW_PART 2197 || GET_CODE (new_i2_dest) == SUBREG) 2198 new_i2_dest = XEXP (new_i2_dest, 0); 2199 2200 if (GET_CODE (new_i3_dest) == REG 2201 && GET_CODE (new_i2_dest) == REG 2202 && REGNO (new_i3_dest) == REGNO (new_i2_dest)) 2203 REG_N_SETS (REGNO (new_i2_dest))++; 2204 } 2205 } 2206 2207 /* If we can split it and use I2DEST, go ahead and see if that 2208 helps things be recognized. Verify that none of the registers 2209 are set between I2 and I3. */ 2210 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0 2211#ifdef HAVE_cc0 2212 && GET_CODE (i2dest) == REG 2213#endif 2214 /* We need I2DEST in the proper mode. If it is a hard register 2215 or the only use of a pseudo, we can change its mode. */ 2216 && (GET_MODE (*split) == GET_MODE (i2dest) 2217 || GET_MODE (*split) == VOIDmode 2218 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER 2219 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2 2220 && ! REG_USERVAR_P (i2dest))) 2221 && (next_real_insn (i2) == i3 2222 || ! use_crosses_set_p (*split, INSN_CUID (i2))) 2223 /* We can't overwrite I2DEST if its value is still used by 2224 NEWPAT. */ 2225 && ! reg_referenced_p (i2dest, newpat)) 2226 { 2227 rtx newdest = i2dest; 2228 enum rtx_code split_code = GET_CODE (*split); 2229 enum machine_mode split_mode = GET_MODE (*split); 2230 2231 /* Get NEWDEST as a register in the proper mode. We have already 2232 validated that we can do this. */ 2233 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) 2234 { 2235 newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); 2236 2237 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 2238 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest); 2239 } 2240 2241 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to 2242 an ASHIFT. This can occur if it was inside a PLUS and hence 2243 appeared to be a memory address. This is a kludge. */ 2244 if (split_code == MULT 2245 && GET_CODE (XEXP (*split, 1)) == CONST_INT 2246 && INTVAL (XEXP (*split, 1)) > 0 2247 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0) 2248 { 2249 SUBST (*split, gen_rtx_ASHIFT (split_mode, 2250 XEXP (*split, 0), GEN_INT (i))); 2251 /* Update split_code because we may not have a multiply 2252 anymore. */ 2253 split_code = GET_CODE (*split); 2254 } 2255 2256#ifdef INSN_SCHEDULING 2257 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should 2258 be written as a ZERO_EXTEND. */ 2259 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM) 2260 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode, 2261 SUBREG_REG (*split))); 2262#endif 2263 2264 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split); 2265 SUBST (*split, newdest); 2266 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2267 2268 /* If the split point was a MULT and we didn't have one before, 2269 don't use one now. */ 2270 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) 2271 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2272 } 2273 } 2274 2275 /* Check for a case where we loaded from memory in a narrow mode and 2276 then sign extended it, but we need both registers. In that case, 2277 we have a PARALLEL with both loads from the same memory location. 2278 We can split this into a load from memory followed by a register-register 2279 copy. This saves at least one insn, more if register allocation can 2280 eliminate the copy. 2281 2282 We cannot do this if the destination of the second assignment is 2283 a register that we have already assumed is zero-extended. Similarly 2284 for a SUBREG of such a register. */ 2285 2286 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 2287 && GET_CODE (newpat) == PARALLEL 2288 && XVECLEN (newpat, 0) == 2 2289 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2290 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND 2291 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2292 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2293 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) 2294 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2295 INSN_CUID (i2)) 2296 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 2297 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 2298 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)), 2299 (GET_CODE (temp) == REG 2300 && reg_nonzero_bits[REGNO (temp)] != 0 2301 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD 2302 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT 2303 && (reg_nonzero_bits[REGNO (temp)] 2304 != GET_MODE_MASK (word_mode)))) 2305 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG 2306 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), 2307 (GET_CODE (temp) == REG 2308 && reg_nonzero_bits[REGNO (temp)] != 0 2309 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD 2310 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT 2311 && (reg_nonzero_bits[REGNO (temp)] 2312 != GET_MODE_MASK (word_mode))))) 2313 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), 2314 SET_SRC (XVECEXP (newpat, 0, 1))) 2315 && ! find_reg_note (i3, REG_UNUSED, 2316 SET_DEST (XVECEXP (newpat, 0, 0)))) 2317 { 2318 rtx ni2dest; 2319 2320 newi2pat = XVECEXP (newpat, 0, 0); 2321 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); 2322 newpat = XVECEXP (newpat, 0, 1); 2323 SUBST (SET_SRC (newpat), 2324 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest)); 2325 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2326 2327 if (i2_code_number >= 0) 2328 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2329 2330 if (insn_code_number >= 0) 2331 { 2332 rtx insn; 2333 rtx link; 2334 2335 /* If we will be able to accept this, we have made a change to the 2336 destination of I3. This can invalidate a LOG_LINKS pointing 2337 to I3. No other part of combine.c makes such a transformation. 2338 2339 The new I3 will have a destination that was previously the 2340 destination of I1 or I2 and which was used in i2 or I3. Call 2341 distribute_links to make a LOG_LINK from the next use of 2342 that destination. */ 2343 2344 PATTERN (i3) = newpat; 2345 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX)); 2346 2347 /* I3 now uses what used to be its destination and which is 2348 now I2's destination. That means we need a LOG_LINK from 2349 I3 to I2. But we used to have one, so we still will. 2350 2351 However, some later insn might be using I2's dest and have 2352 a LOG_LINK pointing at I3. We must remove this link. 2353 The simplest way to remove the link is to point it at I1, 2354 which we know will be a NOTE. */ 2355 2356 for (insn = NEXT_INSN (i3); 2357 insn && (this_basic_block == n_basic_blocks - 1 2358 || insn != BLOCK_HEAD (this_basic_block + 1)); 2359 insn = NEXT_INSN (insn)) 2360 { 2361 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn))) 2362 { 2363 for (link = LOG_LINKS (insn); link; 2364 link = XEXP (link, 1)) 2365 if (XEXP (link, 0) == i3) 2366 XEXP (link, 0) = i1; 2367 2368 break; 2369 } 2370 } 2371 } 2372 } 2373 2374 /* Similarly, check for a case where we have a PARALLEL of two independent 2375 SETs but we started with three insns. In this case, we can do the sets 2376 as two separate insns. This case occurs when some SET allows two 2377 other insns to combine, but the destination of that SET is still live. */ 2378 2379 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 2380 && GET_CODE (newpat) == PARALLEL 2381 && XVECLEN (newpat, 0) == 2 2382 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2383 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT 2384 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART 2385 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2386 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 2387 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 2388 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2389 INSN_CUID (i2)) 2390 /* Don't pass sets with (USE (MEM ...)) dests to the following. */ 2391 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE 2392 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE 2393 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), 2394 XVECEXP (newpat, 0, 0)) 2395 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), 2396 XVECEXP (newpat, 0, 1)) 2397 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))) 2398 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))) 2399 { 2400 /* Normally, it doesn't matter which of the two is done first, 2401 but it does if one references cc0. In that case, it has to 2402 be first. */ 2403#ifdef HAVE_cc0 2404 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))) 2405 { 2406 newi2pat = XVECEXP (newpat, 0, 0); 2407 newpat = XVECEXP (newpat, 0, 1); 2408 } 2409 else 2410#endif 2411 { 2412 newi2pat = XVECEXP (newpat, 0, 1); 2413 newpat = XVECEXP (newpat, 0, 0); 2414 } 2415 2416 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2417 2418 if (i2_code_number >= 0) 2419 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2420 } 2421 2422 /* If it still isn't recognized, fail and change things back the way they 2423 were. */ 2424 if ((insn_code_number < 0 2425 /* Is the result a reasonable ASM_OPERANDS? */ 2426 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) 2427 { 2428 undo_all (); 2429 return 0; 2430 } 2431 2432 /* If we had to change another insn, make sure it is valid also. */ 2433 if (undobuf.other_insn) 2434 { 2435 rtx other_pat = PATTERN (undobuf.other_insn); 2436 rtx new_other_notes; 2437 rtx note, next; 2438 2439 CLEAR_HARD_REG_SET (newpat_used_regs); 2440 2441 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, 2442 &new_other_notes); 2443 2444 if (other_code_number < 0 && ! check_asm_operands (other_pat)) 2445 { 2446 undo_all (); 2447 return 0; 2448 } 2449 2450 PATTERN (undobuf.other_insn) = other_pat; 2451 2452 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they 2453 are still valid. Then add any non-duplicate notes added by 2454 recog_for_combine. */ 2455 for (note = REG_NOTES (undobuf.other_insn); note; note = next) 2456 { 2457 next = XEXP (note, 1); 2458 2459 if (REG_NOTE_KIND (note) == REG_UNUSED 2460 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) 2461 { 2462 if (GET_CODE (XEXP (note, 0)) == REG) 2463 REG_N_DEATHS (REGNO (XEXP (note, 0)))--; 2464 2465 remove_note (undobuf.other_insn, note); 2466 } 2467 } 2468 2469 for (note = new_other_notes; note; note = XEXP (note, 1)) 2470 if (GET_CODE (XEXP (note, 0)) == REG) 2471 REG_N_DEATHS (REGNO (XEXP (note, 0)))++; 2472 2473 distribute_notes (new_other_notes, undobuf.other_insn, 2474 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX); 2475 } 2476#ifdef HAVE_cc0 2477 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether 2478 they are adjacent to each other or not. */ 2479 { 2480 rtx p = prev_nonnote_insn (i3); 2481 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat 2482 && sets_cc0_p (newi2pat)) 2483 { 2484 undo_all (); 2485 return 0; 2486 } 2487 } 2488#endif 2489 2490 /* We now know that we can do this combination. Merge the insns and 2491 update the status of registers and LOG_LINKS. */ 2492 2493 { 2494 rtx i3notes, i2notes, i1notes = 0; 2495 rtx i3links, i2links, i1links = 0; 2496 rtx midnotes = 0; 2497 unsigned int regno; 2498 /* Compute which registers we expect to eliminate. newi2pat may be setting 2499 either i3dest or i2dest, so we must check it. Also, i1dest may be the 2500 same as i3dest, in which case newi2pat may be setting i1dest. */ 2501 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat)) 2502 || i2dest_in_i2src || i2dest_in_i1src 2503 ? 0 : i2dest); 2504 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src 2505 || (newi2pat && reg_set_p (i1dest, newi2pat)) 2506 ? 0 : i1dest); 2507 2508 /* Get the old REG_NOTES and LOG_LINKS from all our insns and 2509 clear them. */ 2510 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); 2511 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); 2512 if (i1) 2513 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); 2514 2515 /* Ensure that we do not have something that should not be shared but 2516 occurs multiple times in the new insns. Check this by first 2517 resetting all the `used' flags and then copying anything is shared. */ 2518 2519 reset_used_flags (i3notes); 2520 reset_used_flags (i2notes); 2521 reset_used_flags (i1notes); 2522 reset_used_flags (newpat); 2523 reset_used_flags (newi2pat); 2524 if (undobuf.other_insn) 2525 reset_used_flags (PATTERN (undobuf.other_insn)); 2526 2527 i3notes = copy_rtx_if_shared (i3notes); 2528 i2notes = copy_rtx_if_shared (i2notes); 2529 i1notes = copy_rtx_if_shared (i1notes); 2530 newpat = copy_rtx_if_shared (newpat); 2531 newi2pat = copy_rtx_if_shared (newi2pat); 2532 if (undobuf.other_insn) 2533 reset_used_flags (PATTERN (undobuf.other_insn)); 2534 2535 INSN_CODE (i3) = insn_code_number; 2536 PATTERN (i3) = newpat; 2537 if (undobuf.other_insn) 2538 INSN_CODE (undobuf.other_insn) = other_code_number; 2539 2540 /* We had one special case above where I2 had more than one set and 2541 we replaced a destination of one of those sets with the destination 2542 of I3. In that case, we have to update LOG_LINKS of insns later 2543 in this basic block. Note that this (expensive) case is rare. 2544 2545 Also, in this case, we must pretend that all REG_NOTEs for I2 2546 actually came from I3, so that REG_UNUSED notes from I2 will be 2547 properly handled. */ 2548 2549 if (i3_subst_into_i2) 2550 { 2551 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) 2552 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE 2553 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG 2554 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest 2555 && ! find_reg_note (i2, REG_UNUSED, 2556 SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) 2557 for (temp = NEXT_INSN (i2); 2558 temp && (this_basic_block == n_basic_blocks - 1 2559 || BLOCK_HEAD (this_basic_block) != temp); 2560 temp = NEXT_INSN (temp)) 2561 if (temp != i3 && INSN_P (temp)) 2562 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1)) 2563 if (XEXP (link, 0) == i2) 2564 XEXP (link, 0) = i3; 2565 2566 if (i3notes) 2567 { 2568 rtx link = i3notes; 2569 while (XEXP (link, 1)) 2570 link = XEXP (link, 1); 2571 XEXP (link, 1) = i2notes; 2572 } 2573 else 2574 i3notes = i2notes; 2575 i2notes = 0; 2576 } 2577 2578 LOG_LINKS (i3) = 0; 2579 REG_NOTES (i3) = 0; 2580 LOG_LINKS (i2) = 0; 2581 REG_NOTES (i2) = 0; 2582 2583 if (newi2pat) 2584 { 2585 INSN_CODE (i2) = i2_code_number; 2586 PATTERN (i2) = newi2pat; 2587 } 2588 else 2589 { 2590 PUT_CODE (i2, NOTE); 2591 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; 2592 NOTE_SOURCE_FILE (i2) = 0; 2593 } 2594 2595 if (i1) 2596 { 2597 LOG_LINKS (i1) = 0; 2598 REG_NOTES (i1) = 0; 2599 PUT_CODE (i1, NOTE); 2600 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED; 2601 NOTE_SOURCE_FILE (i1) = 0; 2602 } 2603 2604 /* Get death notes for everything that is now used in either I3 or 2605 I2 and used to die in a previous insn. If we built two new 2606 patterns, move from I1 to I2 then I2 to I3 so that we get the 2607 proper movement on registers that I2 modifies. */ 2608 2609 if (newi2pat) 2610 { 2611 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes); 2612 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes); 2613 } 2614 else 2615 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2), 2616 i3, &midnotes); 2617 2618 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ 2619 if (i3notes) 2620 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX, 2621 elim_i2, elim_i1); 2622 if (i2notes) 2623 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX, 2624 elim_i2, elim_i1); 2625 if (i1notes) 2626 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX, 2627 elim_i2, elim_i1); 2628 if (midnotes) 2629 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2630 elim_i2, elim_i1); 2631 2632 /* Distribute any notes added to I2 or I3 by recog_for_combine. We 2633 know these are REG_UNUSED and want them to go to the desired insn, 2634 so we always pass it as i3. We have not counted the notes in 2635 reg_n_deaths yet, so we need to do so now. */ 2636 2637 if (newi2pat && new_i2_notes) 2638 { 2639 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1)) 2640 if (GET_CODE (XEXP (temp, 0)) == REG) 2641 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; 2642 2643 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2644 } 2645 2646 if (new_i3_notes) 2647 { 2648 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1)) 2649 if (GET_CODE (XEXP (temp, 0)) == REG) 2650 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; 2651 2652 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX); 2653 } 2654 2655 /* If I3DEST was used in I3SRC, it really died in I3. We may need to 2656 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets 2657 I3DEST, the death must be somewhere before I2, not I3. If we passed I3 2658 in that case, it might delete I2. Similarly for I2 and I1. 2659 Show an additional death due to the REG_DEAD note we make here. If 2660 we discard it in distribute_notes, we will decrement it again. */ 2661 2662 if (i3dest_killed) 2663 { 2664 if (GET_CODE (i3dest_killed) == REG) 2665 REG_N_DEATHS (REGNO (i3dest_killed))++; 2666 2667 if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) 2668 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, 2669 NULL_RTX), 2670 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1); 2671 else 2672 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, 2673 NULL_RTX), 2674 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2675 elim_i2, elim_i1); 2676 } 2677 2678 if (i2dest_in_i2src) 2679 { 2680 if (GET_CODE (i2dest) == REG) 2681 REG_N_DEATHS (REGNO (i2dest))++; 2682 2683 if (newi2pat && reg_set_p (i2dest, newi2pat)) 2684 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), 2685 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2686 else 2687 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), 2688 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2689 NULL_RTX, NULL_RTX); 2690 } 2691 2692 if (i1dest_in_i1src) 2693 { 2694 if (GET_CODE (i1dest) == REG) 2695 REG_N_DEATHS (REGNO (i1dest))++; 2696 2697 if (newi2pat && reg_set_p (i1dest, newi2pat)) 2698 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), 2699 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2700 else 2701 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), 2702 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2703 NULL_RTX, NULL_RTX); 2704 } 2705 2706 distribute_links (i3links); 2707 distribute_links (i2links); 2708 distribute_links (i1links); 2709 2710 if (GET_CODE (i2dest) == REG) 2711 { 2712 rtx link; 2713 rtx i2_insn = 0, i2_val = 0, set; 2714 2715 /* The insn that used to set this register doesn't exist, and 2716 this life of the register may not exist either. See if one of 2717 I3's links points to an insn that sets I2DEST. If it does, 2718 that is now the last known value for I2DEST. If we don't update 2719 this and I2 set the register to a value that depended on its old 2720 contents, we will get confused. If this insn is used, thing 2721 will be set correctly in combine_instructions. */ 2722 2723 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) 2724 if ((set = single_set (XEXP (link, 0))) != 0 2725 && rtx_equal_p (i2dest, SET_DEST (set))) 2726 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set); 2727 2728 record_value_for_reg (i2dest, i2_insn, i2_val); 2729 2730 /* If the reg formerly set in I2 died only once and that was in I3, 2731 zero its use count so it won't make `reload' do any work. */ 2732 if (! added_sets_2 2733 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) 2734 && ! i2dest_in_i2src) 2735 { 2736 regno = REGNO (i2dest); 2737 REG_N_SETS (regno)--; 2738 } 2739 } 2740 2741 if (i1 && GET_CODE (i1dest) == REG) 2742 { 2743 rtx link; 2744 rtx i1_insn = 0, i1_val = 0, set; 2745 2746 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) 2747 if ((set = single_set (XEXP (link, 0))) != 0 2748 && rtx_equal_p (i1dest, SET_DEST (set))) 2749 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set); 2750 2751 record_value_for_reg (i1dest, i1_insn, i1_val); 2752 2753 regno = REGNO (i1dest); 2754 if (! added_sets_1 && ! i1dest_in_i1src) 2755 REG_N_SETS (regno)--; 2756 } 2757 2758 /* Update reg_nonzero_bits et al for any changes that may have been made 2759 to this insn. The order of set_nonzero_bits_and_sign_copies() is 2760 important. Because newi2pat can affect nonzero_bits of newpat */ 2761 if (newi2pat) 2762 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL); 2763 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL); 2764 2765 /* Set new_direct_jump_p if a new return or simple jump instruction 2766 has been created. 2767 2768 If I3 is now an unconditional jump, ensure that it has a 2769 BARRIER following it since it may have initially been a 2770 conditional jump. It may also be the last nonnote insn. */ 2771 2772 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3)) 2773 { 2774 *new_direct_jump_p = 1; 2775 2776 if ((temp = next_nonnote_insn (i3)) == NULL_RTX 2777 || GET_CODE (temp) != BARRIER) 2778 emit_barrier_after (i3); 2779 } 2780 /* An NOOP jump does not need barrier, but it does need cleaning up 2781 of CFG. */ 2782 if (GET_CODE (newpat) == SET 2783 && SET_SRC (newpat) == pc_rtx 2784 && SET_DEST (newpat) == pc_rtx) 2785 *new_direct_jump_p = 1; 2786 } 2787 2788 combine_successes++; 2789 undo_commit (); 2790 2791 /* Clear this here, so that subsequent get_last_value calls are not 2792 affected. */ 2793 subst_prev_insn = NULL_RTX; 2794 2795 if (added_links_insn 2796 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2)) 2797 && INSN_CUID (added_links_insn) < INSN_CUID (i3)) 2798 return added_links_insn; 2799 else 2800 return newi2pat ? i2 : i3; 2801} 2802 2803/* Undo all the modifications recorded in undobuf. */ 2804 2805static void 2806undo_all () 2807{ 2808 struct undo *undo, *next; 2809 2810 for (undo = undobuf.undos; undo; undo = next) 2811 { 2812 next = undo->next; 2813 if (undo->is_int) 2814 *undo->where.i = undo->old_contents.i; 2815 else 2816 *undo->where.r = undo->old_contents.r; 2817 2818 undo->next = undobuf.frees; 2819 undobuf.frees = undo; 2820 } 2821 2822 undobuf.undos = 0; 2823 2824 /* Clear this here, so that subsequent get_last_value calls are not 2825 affected. */ 2826 subst_prev_insn = NULL_RTX; 2827} 2828 2829/* We've committed to accepting the changes we made. Move all 2830 of the undos to the free list. */ 2831 2832static void 2833undo_commit () 2834{ 2835 struct undo *undo, *next; 2836 2837 for (undo = undobuf.undos; undo; undo = next) 2838 { 2839 next = undo->next; 2840 undo->next = undobuf.frees; 2841 undobuf.frees = undo; 2842 } 2843 undobuf.undos = 0; 2844} 2845 2846 2847/* Find the innermost point within the rtx at LOC, possibly LOC itself, 2848 where we have an arithmetic expression and return that point. LOC will 2849 be inside INSN. 2850 2851 try_combine will call this function to see if an insn can be split into 2852 two insns. */ 2853 2854static rtx * 2855find_split_point (loc, insn) 2856 rtx *loc; 2857 rtx insn; 2858{ 2859 rtx x = *loc; 2860 enum rtx_code code = GET_CODE (x); 2861 rtx *split; 2862 unsigned HOST_WIDE_INT len = 0; 2863 HOST_WIDE_INT pos = 0; 2864 int unsignedp = 0; 2865 rtx inner = NULL_RTX; 2866 2867 /* First special-case some codes. */ 2868 switch (code) 2869 { 2870 case SUBREG: 2871#ifdef INSN_SCHEDULING 2872 /* If we are making a paradoxical SUBREG invalid, it becomes a split 2873 point. */ 2874 if (GET_CODE (SUBREG_REG (x)) == MEM) 2875 return loc; 2876#endif 2877 return find_split_point (&SUBREG_REG (x), insn); 2878 2879 case MEM: 2880#ifdef HAVE_lo_sum 2881 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it 2882 using LO_SUM and HIGH. */ 2883 if (GET_CODE (XEXP (x, 0)) == CONST 2884 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) 2885 { 2886 SUBST (XEXP (x, 0), 2887 gen_rtx_LO_SUM (Pmode, 2888 gen_rtx_HIGH (Pmode, XEXP (x, 0)), 2889 XEXP (x, 0))); 2890 return &XEXP (XEXP (x, 0), 0); 2891 } 2892#endif 2893 2894 /* If we have a PLUS whose second operand is a constant and the 2895 address is not valid, perhaps will can split it up using 2896 the machine-specific way to split large constants. We use 2897 the first pseudo-reg (one of the virtual regs) as a placeholder; 2898 it will not remain in the result. */ 2899 if (GET_CODE (XEXP (x, 0)) == PLUS 2900 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 2901 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) 2902 { 2903 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; 2904 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)), 2905 subst_insn); 2906 2907 /* This should have produced two insns, each of which sets our 2908 placeholder. If the source of the second is a valid address, 2909 we can make put both sources together and make a split point 2910 in the middle. */ 2911 2912 if (seq && XVECLEN (seq, 0) == 2 2913 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN 2914 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET 2915 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg 2916 && ! reg_mentioned_p (reg, 2917 SET_SRC (PATTERN (XVECEXP (seq, 0, 0)))) 2918 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN 2919 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET 2920 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg 2921 && memory_address_p (GET_MODE (x), 2922 SET_SRC (PATTERN (XVECEXP (seq, 0, 1))))) 2923 { 2924 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0))); 2925 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1))); 2926 2927 /* Replace the placeholder in SRC2 with SRC1. If we can 2928 find where in SRC2 it was placed, that can become our 2929 split point and we can replace this address with SRC2. 2930 Just try two obvious places. */ 2931 2932 src2 = replace_rtx (src2, reg, src1); 2933 split = 0; 2934 if (XEXP (src2, 0) == src1) 2935 split = &XEXP (src2, 0); 2936 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' 2937 && XEXP (XEXP (src2, 0), 0) == src1) 2938 split = &XEXP (XEXP (src2, 0), 0); 2939 2940 if (split) 2941 { 2942 SUBST (XEXP (x, 0), src2); 2943 return split; 2944 } 2945 } 2946 2947 /* If that didn't work, perhaps the first operand is complex and 2948 needs to be computed separately, so make a split point there. 2949 This will occur on machines that just support REG + CONST 2950 and have a constant moved through some previous computation. */ 2951 2952 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o' 2953 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG 2954 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0)))) 2955 == 'o'))) 2956 return &XEXP (XEXP (x, 0), 0); 2957 } 2958 break; 2959 2960 case SET: 2961#ifdef HAVE_cc0 2962 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a 2963 ZERO_EXTRACT, the most likely reason why this doesn't match is that 2964 we need to put the operand into a register. So split at that 2965 point. */ 2966 2967 if (SET_DEST (x) == cc0_rtx 2968 && GET_CODE (SET_SRC (x)) != COMPARE 2969 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT 2970 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o' 2971 && ! (GET_CODE (SET_SRC (x)) == SUBREG 2972 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o')) 2973 return &SET_SRC (x); 2974#endif 2975 2976 /* See if we can split SET_SRC as it stands. */ 2977 split = find_split_point (&SET_SRC (x), insn); 2978 if (split && split != &SET_SRC (x)) 2979 return split; 2980 2981 /* See if we can split SET_DEST as it stands. */ 2982 split = find_split_point (&SET_DEST (x), insn); 2983 if (split && split != &SET_DEST (x)) 2984 return split; 2985 2986 /* See if this is a bitfield assignment with everything constant. If 2987 so, this is an IOR of an AND, so split it into that. */ 2988 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 2989 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))) 2990 <= HOST_BITS_PER_WIDE_INT) 2991 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT 2992 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT 2993 && GET_CODE (SET_SRC (x)) == CONST_INT 2994 && ((INTVAL (XEXP (SET_DEST (x), 1)) 2995 + INTVAL (XEXP (SET_DEST (x), 2))) 2996 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))) 2997 && ! side_effects_p (XEXP (SET_DEST (x), 0))) 2998 { 2999 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2)); 3000 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1)); 3001 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)); 3002 rtx dest = XEXP (SET_DEST (x), 0); 3003 enum machine_mode mode = GET_MODE (dest); 3004 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1; 3005 3006 if (BITS_BIG_ENDIAN) 3007 pos = GET_MODE_BITSIZE (mode) - len - pos; 3008 3009 if (src == mask) 3010 SUBST (SET_SRC (x), 3011 gen_binary (IOR, mode, dest, GEN_INT (src << pos))); 3012 else 3013 SUBST (SET_SRC (x), 3014 gen_binary (IOR, mode, 3015 gen_binary (AND, mode, dest, 3016 GEN_INT (~(mask << pos) 3017 & GET_MODE_MASK (mode))), 3018 GEN_INT (src << pos))); 3019 3020 SUBST (SET_DEST (x), dest); 3021 3022 split = find_split_point (&SET_SRC (x), insn); 3023 if (split && split != &SET_SRC (x)) 3024 return split; 3025 } 3026 3027 /* Otherwise, see if this is an operation that we can split into two. 3028 If so, try to split that. */ 3029 code = GET_CODE (SET_SRC (x)); 3030 3031 switch (code) 3032 { 3033 case AND: 3034 /* If we are AND'ing with a large constant that is only a single 3035 bit and the result is only being used in a context where we 3036 need to know if it is zero or non-zero, replace it with a bit 3037 extraction. This will avoid the large constant, which might 3038 have taken more than one insn to make. If the constant were 3039 not a valid argument to the AND but took only one insn to make, 3040 this is no worse, but if it took more than one insn, it will 3041 be better. */ 3042 3043 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 3044 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 3045 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7 3046 && GET_CODE (SET_DEST (x)) == REG 3047 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0 3048 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) 3049 && XEXP (*split, 0) == SET_DEST (x) 3050 && XEXP (*split, 1) == const0_rtx) 3051 { 3052 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), 3053 XEXP (SET_SRC (x), 0), 3054 pos, NULL_RTX, 1, 1, 0, 0); 3055 if (extraction != 0) 3056 { 3057 SUBST (SET_SRC (x), extraction); 3058 return find_split_point (loc, insn); 3059 } 3060 } 3061 break; 3062 3063 case NE: 3064 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X 3065 is known to be on, this can be converted into a NEG of a shift. */ 3066 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx 3067 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) 3068 && 1 <= (pos = exact_log2 3069 (nonzero_bits (XEXP (SET_SRC (x), 0), 3070 GET_MODE (XEXP (SET_SRC (x), 0)))))) 3071 { 3072 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); 3073 3074 SUBST (SET_SRC (x), 3075 gen_rtx_NEG (mode, 3076 gen_rtx_LSHIFTRT (mode, 3077 XEXP (SET_SRC (x), 0), 3078 GEN_INT (pos)))); 3079 3080 split = find_split_point (&SET_SRC (x), insn); 3081 if (split && split != &SET_SRC (x)) 3082 return split; 3083 } 3084 break; 3085 3086 case SIGN_EXTEND: 3087 inner = XEXP (SET_SRC (x), 0); 3088 3089 /* We can't optimize if either mode is a partial integer 3090 mode as we don't know how many bits are significant 3091 in those modes. */ 3092 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT 3093 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) 3094 break; 3095 3096 pos = 0; 3097 len = GET_MODE_BITSIZE (GET_MODE (inner)); 3098 unsignedp = 0; 3099 break; 3100 3101 case SIGN_EXTRACT: 3102 case ZERO_EXTRACT: 3103 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 3104 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT) 3105 { 3106 inner = XEXP (SET_SRC (x), 0); 3107 len = INTVAL (XEXP (SET_SRC (x), 1)); 3108 pos = INTVAL (XEXP (SET_SRC (x), 2)); 3109 3110 if (BITS_BIG_ENDIAN) 3111 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos; 3112 unsignedp = (code == ZERO_EXTRACT); 3113 } 3114 break; 3115 3116 default: 3117 break; 3118 } 3119 3120 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner))) 3121 { 3122 enum machine_mode mode = GET_MODE (SET_SRC (x)); 3123 3124 /* For unsigned, we have a choice of a shift followed by an 3125 AND or two shifts. Use two shifts for field sizes where the 3126 constant might be too large. We assume here that we can 3127 always at least get 8-bit constants in an AND insn, which is 3128 true for every current RISC. */ 3129 3130 if (unsignedp && len <= 8) 3131 { 3132 SUBST (SET_SRC (x), 3133 gen_rtx_AND (mode, 3134 gen_rtx_LSHIFTRT 3135 (mode, gen_lowpart_for_combine (mode, inner), 3136 GEN_INT (pos)), 3137 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1))); 3138 3139 split = find_split_point (&SET_SRC (x), insn); 3140 if (split && split != &SET_SRC (x)) 3141 return split; 3142 } 3143 else 3144 { 3145 SUBST (SET_SRC (x), 3146 gen_rtx_fmt_ee 3147 (unsignedp ? LSHIFTRT : ASHIFTRT, mode, 3148 gen_rtx_ASHIFT (mode, 3149 gen_lowpart_for_combine (mode, inner), 3150 GEN_INT (GET_MODE_BITSIZE (mode) 3151 - len - pos)), 3152 GEN_INT (GET_MODE_BITSIZE (mode) - len))); 3153 3154 split = find_split_point (&SET_SRC (x), insn); 3155 if (split && split != &SET_SRC (x)) 3156 return split; 3157 } 3158 } 3159 3160 /* See if this is a simple operation with a constant as the second 3161 operand. It might be that this constant is out of range and hence 3162 could be used as a split point. */ 3163 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' 3164 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' 3165 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<') 3166 && CONSTANT_P (XEXP (SET_SRC (x), 1)) 3167 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o' 3168 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG 3169 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0)))) 3170 == 'o')))) 3171 return &XEXP (SET_SRC (x), 1); 3172 3173 /* Finally, see if this is a simple operation with its first operand 3174 not in a register. The operation might require this operand in a 3175 register, so return it as a split point. We can always do this 3176 because if the first operand were another operation, we would have 3177 already found it as a split point. */ 3178 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' 3179 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' 3180 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<' 3181 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1') 3182 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) 3183 return &XEXP (SET_SRC (x), 0); 3184 3185 return 0; 3186 3187 case AND: 3188 case IOR: 3189 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, 3190 it is better to write this as (not (ior A B)) so we can split it. 3191 Similarly for IOR. */ 3192 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) 3193 { 3194 SUBST (*loc, 3195 gen_rtx_NOT (GET_MODE (x), 3196 gen_rtx_fmt_ee (code == IOR ? AND : IOR, 3197 GET_MODE (x), 3198 XEXP (XEXP (x, 0), 0), 3199 XEXP (XEXP (x, 1), 0)))); 3200 return find_split_point (loc, insn); 3201 } 3202 3203 /* Many RISC machines have a large set of logical insns. If the 3204 second operand is a NOT, put it first so we will try to split the 3205 other operand first. */ 3206 if (GET_CODE (XEXP (x, 1)) == NOT) 3207 { 3208 rtx tem = XEXP (x, 0); 3209 SUBST (XEXP (x, 0), XEXP (x, 1)); 3210 SUBST (XEXP (x, 1), tem); 3211 } 3212 break; 3213 3214 default: 3215 break; 3216 } 3217 3218 /* Otherwise, select our actions depending on our rtx class. */ 3219 switch (GET_RTX_CLASS (code)) 3220 { 3221 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ 3222 case '3': 3223 split = find_split_point (&XEXP (x, 2), insn); 3224 if (split) 3225 return split; 3226 /* ... fall through ... */ 3227 case '2': 3228 case 'c': 3229 case '<': 3230 split = find_split_point (&XEXP (x, 1), insn); 3231 if (split) 3232 return split; 3233 /* ... fall through ... */ 3234 case '1': 3235 /* Some machines have (and (shift ...) ...) insns. If X is not 3236 an AND, but XEXP (X, 0) is, use it as our split point. */ 3237 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) 3238 return &XEXP (x, 0); 3239 3240 split = find_split_point (&XEXP (x, 0), insn); 3241 if (split) 3242 return split; 3243 return loc; 3244 } 3245 3246 /* Otherwise, we don't have a split point. */ 3247 return 0; 3248} 3249 3250/* Throughout X, replace FROM with TO, and return the result. 3251 The result is TO if X is FROM; 3252 otherwise the result is X, but its contents may have been modified. 3253 If they were modified, a record was made in undobuf so that 3254 undo_all will (among other things) return X to its original state. 3255 3256 If the number of changes necessary is too much to record to undo, 3257 the excess changes are not made, so the result is invalid. 3258 The changes already made can still be undone. 3259 undobuf.num_undo is incremented for such changes, so by testing that 3260 the caller can tell whether the result is valid. 3261 3262 `n_occurrences' is incremented each time FROM is replaced. 3263 3264 IN_DEST is non-zero if we are processing the SET_DEST of a SET. 3265 3266 UNIQUE_COPY is non-zero if each substitution must be unique. We do this 3267 by copying if `n_occurrences' is non-zero. */ 3268 3269static rtx 3270subst (x, from, to, in_dest, unique_copy) 3271 rtx x, from, to; 3272 int in_dest; 3273 int unique_copy; 3274{ 3275 enum rtx_code code = GET_CODE (x); 3276 enum machine_mode op0_mode = VOIDmode; 3277 const char *fmt; 3278 int len, i; 3279 rtx new; 3280 3281/* Two expressions are equal if they are identical copies of a shared 3282 RTX or if they are both registers with the same register number 3283 and mode. */ 3284 3285#define COMBINE_RTX_EQUAL_P(X,Y) \ 3286 ((X) == (Y) \ 3287 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \ 3288 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) 3289 3290 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) 3291 { 3292 n_occurrences++; 3293 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); 3294 } 3295 3296 /* If X and FROM are the same register but different modes, they will 3297 not have been seen as equal above. However, flow.c will make a 3298 LOG_LINKS entry for that case. If we do nothing, we will try to 3299 rerecognize our original insn and, when it succeeds, we will 3300 delete the feeding insn, which is incorrect. 3301 3302 So force this insn not to match in this (rare) case. */ 3303 if (! in_dest && code == REG && GET_CODE (from) == REG 3304 && REGNO (x) == REGNO (from)) 3305 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 3306 3307 /* If this is an object, we are done unless it is a MEM or LO_SUM, both 3308 of which may contain things that can be combined. */ 3309 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o') 3310 return x; 3311 3312 /* It is possible to have a subexpression appear twice in the insn. 3313 Suppose that FROM is a register that appears within TO. 3314 Then, after that subexpression has been scanned once by `subst', 3315 the second time it is scanned, TO may be found. If we were 3316 to scan TO here, we would find FROM within it and create a 3317 self-referent rtl structure which is completely wrong. */ 3318 if (COMBINE_RTX_EQUAL_P (x, to)) 3319 return to; 3320 3321 /* Parallel asm_operands need special attention because all of the 3322 inputs are shared across the arms. Furthermore, unsharing the 3323 rtl results in recognition failures. Failure to handle this case 3324 specially can result in circular rtl. 3325 3326 Solve this by doing a normal pass across the first entry of the 3327 parallel, and only processing the SET_DESTs of the subsequent 3328 entries. Ug. */ 3329 3330 if (code == PARALLEL 3331 && GET_CODE (XVECEXP (x, 0, 0)) == SET 3332 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) 3333 { 3334 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy); 3335 3336 /* If this substitution failed, this whole thing fails. */ 3337 if (GET_CODE (new) == CLOBBER 3338 && XEXP (new, 0) == const0_rtx) 3339 return new; 3340 3341 SUBST (XVECEXP (x, 0, 0), new); 3342 3343 for (i = XVECLEN (x, 0) - 1; i >= 1; i--) 3344 { 3345 rtx dest = SET_DEST (XVECEXP (x, 0, i)); 3346 3347 if (GET_CODE (dest) != REG 3348 && GET_CODE (dest) != CC0 3349 && GET_CODE (dest) != PC) 3350 { 3351 new = subst (dest, from, to, 0, unique_copy); 3352 3353 /* If this substitution failed, this whole thing fails. */ 3354 if (GET_CODE (new) == CLOBBER 3355 && XEXP (new, 0) == const0_rtx) 3356 return new; 3357 3358 SUBST (SET_DEST (XVECEXP (x, 0, i)), new); 3359 } 3360 } 3361 } 3362 else 3363 { 3364 len = GET_RTX_LENGTH (code); 3365 fmt = GET_RTX_FORMAT (code); 3366 3367 /* We don't need to process a SET_DEST that is a register, CC0, 3368 or PC, so set up to skip this common case. All other cases 3369 where we want to suppress replacing something inside a 3370 SET_SRC are handled via the IN_DEST operand. */ 3371 if (code == SET 3372 && (GET_CODE (SET_DEST (x)) == REG 3373 || GET_CODE (SET_DEST (x)) == CC0 3374 || GET_CODE (SET_DEST (x)) == PC)) 3375 fmt = "ie"; 3376 3377 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a 3378 constant. */ 3379 if (fmt[0] == 'e') 3380 op0_mode = GET_MODE (XEXP (x, 0)); 3381 3382 for (i = 0; i < len; i++) 3383 { 3384 if (fmt[i] == 'E') 3385 { 3386 int j; 3387 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3388 { 3389 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) 3390 { 3391 new = (unique_copy && n_occurrences 3392 ? copy_rtx (to) : to); 3393 n_occurrences++; 3394 } 3395 else 3396 { 3397 new = subst (XVECEXP (x, i, j), from, to, 0, 3398 unique_copy); 3399 3400 /* If this substitution failed, this whole thing 3401 fails. */ 3402 if (GET_CODE (new) == CLOBBER 3403 && XEXP (new, 0) == const0_rtx) 3404 return new; 3405 } 3406 3407 SUBST (XVECEXP (x, i, j), new); 3408 } 3409 } 3410 else if (fmt[i] == 'e') 3411 { 3412 /* If this is a register being set, ignore it. */ 3413 new = XEXP (x, i); 3414 if (in_dest 3415 && (code == SUBREG || code == STRICT_LOW_PART 3416 || code == ZERO_EXTRACT) 3417 && i == 0 3418 && GET_CODE (new) == REG) 3419 ; 3420 3421 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) 3422 { 3423 /* In general, don't install a subreg involving two 3424 modes not tieable. It can worsen register 3425 allocation, and can even make invalid reload 3426 insns, since the reg inside may need to be copied 3427 from in the outside mode, and that may be invalid 3428 if it is an fp reg copied in integer mode. 3429 3430 We allow two exceptions to this: It is valid if 3431 it is inside another SUBREG and the mode of that 3432 SUBREG and the mode of the inside of TO is 3433 tieable and it is valid if X is a SET that copies 3434 FROM to CC0. */ 3435 3436 if (GET_CODE (to) == SUBREG 3437 && ! MODES_TIEABLE_P (GET_MODE (to), 3438 GET_MODE (SUBREG_REG (to))) 3439 && ! (code == SUBREG 3440 && MODES_TIEABLE_P (GET_MODE (x), 3441 GET_MODE (SUBREG_REG (to)))) 3442#ifdef HAVE_cc0 3443 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx) 3444#endif 3445 ) 3446 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 3447 3448#ifdef CLASS_CANNOT_CHANGE_MODE 3449 if (code == SUBREG 3450 && GET_CODE (to) == REG 3451 && REGNO (to) < FIRST_PSEUDO_REGISTER 3452 && (TEST_HARD_REG_BIT 3453 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], 3454 REGNO (to))) 3455 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to), 3456 GET_MODE (x))) 3457 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 3458#endif 3459 3460 new = (unique_copy && n_occurrences ? copy_rtx (to) : to); 3461 n_occurrences++; 3462 } 3463 else 3464 /* If we are in a SET_DEST, suppress most cases unless we 3465 have gone inside a MEM, in which case we want to 3466 simplify the address. We assume here that things that 3467 are actually part of the destination have their inner 3468 parts in the first expression. This is true for SUBREG, 3469 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only 3470 things aside from REG and MEM that should appear in a 3471 SET_DEST. */ 3472 new = subst (XEXP (x, i), from, to, 3473 (((in_dest 3474 && (code == SUBREG || code == STRICT_LOW_PART 3475 || code == ZERO_EXTRACT)) 3476 || code == SET) 3477 && i == 0), unique_copy); 3478 3479 /* If we found that we will have to reject this combination, 3480 indicate that by returning the CLOBBER ourselves, rather than 3481 an expression containing it. This will speed things up as 3482 well as prevent accidents where two CLOBBERs are considered 3483 to be equal, thus producing an incorrect simplification. */ 3484 3485 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) 3486 return new; 3487 3488 SUBST (XEXP (x, i), new); 3489 } 3490 } 3491 } 3492 3493 /* Try to simplify X. If the simplification changed the code, it is likely 3494 that further simplification will help, so loop, but limit the number 3495 of repetitions that will be performed. */ 3496 3497 for (i = 0; i < 4; i++) 3498 { 3499 /* If X is sufficiently simple, don't bother trying to do anything 3500 with it. */ 3501 if (code != CONST_INT && code != REG && code != CLOBBER) 3502 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest); 3503 3504 if (GET_CODE (x) == code) 3505 break; 3506 3507 code = GET_CODE (x); 3508 3509 /* We no longer know the original mode of operand 0 since we 3510 have changed the form of X) */ 3511 op0_mode = VOIDmode; 3512 } 3513 3514 return x; 3515} 3516 3517/* Simplify X, a piece of RTL. We just operate on the expression at the 3518 outer level; call `subst' to simplify recursively. Return the new 3519 expression. 3520 3521 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this 3522 will be the iteration even if an expression with a code different from 3523 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */ 3524 3525static rtx 3526combine_simplify_rtx (x, op0_mode, last, in_dest) 3527 rtx x; 3528 enum machine_mode op0_mode; 3529 int last; 3530 int in_dest; 3531{ 3532 enum rtx_code code = GET_CODE (x); 3533 enum machine_mode mode = GET_MODE (x); 3534 rtx temp; 3535 rtx reversed; 3536 int i; 3537 3538 /* If this is a commutative operation, put a constant last and a complex 3539 expression first. We don't need to do this for comparisons here. */ 3540 if (GET_RTX_CLASS (code) == 'c' 3541 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 3542 { 3543 temp = XEXP (x, 0); 3544 SUBST (XEXP (x, 0), XEXP (x, 1)); 3545 SUBST (XEXP (x, 1), temp); 3546 } 3547 3548 /* If this is a PLUS, MINUS, or MULT, and the first operand is the 3549 sign extension of a PLUS with a constant, reverse the order of the sign 3550 extension and the addition. Note that this not the same as the original 3551 code, but overflow is undefined for signed values. Also note that the 3552 PLUS will have been partially moved "inside" the sign-extension, so that 3553 the first operand of X will really look like: 3554 (ashiftrt (plus (ashift A C4) C5) C4). 3555 We convert this to 3556 (plus (ashiftrt (ashift A C4) C2) C4) 3557 and replace the first operand of X with that expression. Later parts 3558 of this function may simplify the expression further. 3559 3560 For example, if we start with (mult (sign_extend (plus A C1)) C2), 3561 we swap the SIGN_EXTEND and PLUS. Later code will apply the 3562 distributive law to produce (plus (mult (sign_extend X) C1) C3). 3563 3564 We do this to simplify address expressions. */ 3565 3566 if ((code == PLUS || code == MINUS || code == MULT) 3567 && GET_CODE (XEXP (x, 0)) == ASHIFTRT 3568 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS 3569 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT 3570 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT 3571 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3572 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1) 3573 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT 3574 && (temp = simplify_binary_operation (ASHIFTRT, mode, 3575 XEXP (XEXP (XEXP (x, 0), 0), 1), 3576 XEXP (XEXP (x, 0), 1))) != 0) 3577 { 3578 rtx new 3579 = simplify_shift_const (NULL_RTX, ASHIFT, mode, 3580 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0), 3581 INTVAL (XEXP (XEXP (x, 0), 1))); 3582 3583 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new, 3584 INTVAL (XEXP (XEXP (x, 0), 1))); 3585 3586 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp)); 3587 } 3588 3589 /* If this is a simple operation applied to an IF_THEN_ELSE, try 3590 applying it to the arms of the IF_THEN_ELSE. This often simplifies 3591 things. Check for cases where both arms are testing the same 3592 condition. 3593 3594 Don't do anything if all operands are very simple. */ 3595 3596 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c' 3597 || GET_RTX_CLASS (code) == '<') 3598 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' 3599 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 3600 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) 3601 == 'o'))) 3602 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o' 3603 && ! (GET_CODE (XEXP (x, 1)) == SUBREG 3604 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1)))) 3605 == 'o'))))) 3606 || (GET_RTX_CLASS (code) == '1' 3607 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' 3608 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 3609 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) 3610 == 'o')))))) 3611 { 3612 rtx cond, true_rtx, false_rtx; 3613 3614 cond = if_then_else_cond (x, &true_rtx, &false_rtx); 3615 if (cond != 0 3616 /* If everything is a comparison, what we have is highly unlikely 3617 to be simpler, so don't use it. */ 3618 && ! (GET_RTX_CLASS (code) == '<' 3619 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<' 3620 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<'))) 3621 { 3622 rtx cop1 = const0_rtx; 3623 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); 3624 3625 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<') 3626 return x; 3627 3628 /* Simplify the alternative arms; this may collapse the true and 3629 false arms to store-flag values. */ 3630 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0); 3631 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0); 3632 3633 /* If true_rtx and false_rtx are not general_operands, an if_then_else 3634 is unlikely to be simpler. */ 3635 if (general_operand (true_rtx, VOIDmode) 3636 && general_operand (false_rtx, VOIDmode)) 3637 { 3638 /* Restarting if we generate a store-flag expression will cause 3639 us to loop. Just drop through in this case. */ 3640 3641 /* If the result values are STORE_FLAG_VALUE and zero, we can 3642 just make the comparison operation. */ 3643 if (true_rtx == const_true_rtx && false_rtx == const0_rtx) 3644 x = gen_binary (cond_code, mode, cond, cop1); 3645 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx 3646 && reverse_condition (cond_code) != UNKNOWN) 3647 x = gen_binary (reverse_condition (cond_code), 3648 mode, cond, cop1); 3649 3650 /* Likewise, we can make the negate of a comparison operation 3651 if the result values are - STORE_FLAG_VALUE and zero. */ 3652 else if (GET_CODE (true_rtx) == CONST_INT 3653 && INTVAL (true_rtx) == - STORE_FLAG_VALUE 3654 && false_rtx == const0_rtx) 3655 x = simplify_gen_unary (NEG, mode, 3656 gen_binary (cond_code, mode, cond, 3657 cop1), 3658 mode); 3659 else if (GET_CODE (false_rtx) == CONST_INT 3660 && INTVAL (false_rtx) == - STORE_FLAG_VALUE 3661 && true_rtx == const0_rtx) 3662 x = simplify_gen_unary (NEG, mode, 3663 gen_binary (reverse_condition 3664 (cond_code), 3665 mode, cond, cop1), 3666 mode); 3667 else 3668 return gen_rtx_IF_THEN_ELSE (mode, 3669 gen_binary (cond_code, VOIDmode, 3670 cond, cop1), 3671 true_rtx, false_rtx); 3672 3673 code = GET_CODE (x); 3674 op0_mode = VOIDmode; 3675 } 3676 } 3677 } 3678 3679 /* Try to fold this expression in case we have constants that weren't 3680 present before. */ 3681 temp = 0; 3682 switch (GET_RTX_CLASS (code)) 3683 { 3684 case '1': 3685 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); 3686 break; 3687 case '<': 3688 { 3689 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0)); 3690 if (cmp_mode == VOIDmode) 3691 { 3692 cmp_mode = GET_MODE (XEXP (x, 1)); 3693 if (cmp_mode == VOIDmode) 3694 cmp_mode = op0_mode; 3695 } 3696 temp = simplify_relational_operation (code, cmp_mode, 3697 XEXP (x, 0), XEXP (x, 1)); 3698 } 3699#ifdef FLOAT_STORE_FLAG_VALUE 3700 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT) 3701 { 3702 if (temp == const0_rtx) 3703 temp = CONST0_RTX (mode); 3704 else 3705 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode); 3706 } 3707#endif 3708 break; 3709 case 'c': 3710 case '2': 3711 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); 3712 break; 3713 case 'b': 3714 case '3': 3715 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), 3716 XEXP (x, 1), XEXP (x, 2)); 3717 break; 3718 } 3719 3720 if (temp) 3721 { 3722 x = temp; 3723 code = GET_CODE (temp); 3724 op0_mode = VOIDmode; 3725 mode = GET_MODE (temp); 3726 } 3727 3728 /* First see if we can apply the inverse distributive law. */ 3729 if (code == PLUS || code == MINUS 3730 || code == AND || code == IOR || code == XOR) 3731 { 3732 x = apply_distributive_law (x); 3733 code = GET_CODE (x); 3734 op0_mode = VOIDmode; 3735 } 3736 3737 /* If CODE is an associative operation not otherwise handled, see if we 3738 can associate some operands. This can win if they are constants or 3739 if they are logically related (i.e. (a & b) & a). */ 3740 if ((code == PLUS || code == MINUS || code == MULT || code == DIV 3741 || code == AND || code == IOR || code == XOR 3742 || code == SMAX || code == SMIN || code == UMAX || code == UMIN) 3743 && ((INTEGRAL_MODE_P (mode) && code != DIV) 3744 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode)))) 3745 { 3746 if (GET_CODE (XEXP (x, 0)) == code) 3747 { 3748 rtx other = XEXP (XEXP (x, 0), 0); 3749 rtx inner_op0 = XEXP (XEXP (x, 0), 1); 3750 rtx inner_op1 = XEXP (x, 1); 3751 rtx inner; 3752 3753 /* Make sure we pass the constant operand if any as the second 3754 one if this is a commutative operation. */ 3755 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c') 3756 { 3757 rtx tem = inner_op0; 3758 inner_op0 = inner_op1; 3759 inner_op1 = tem; 3760 } 3761 inner = simplify_binary_operation (code == MINUS ? PLUS 3762 : code == DIV ? MULT 3763 : code, 3764 mode, inner_op0, inner_op1); 3765 3766 /* For commutative operations, try the other pair if that one 3767 didn't simplify. */ 3768 if (inner == 0 && GET_RTX_CLASS (code) == 'c') 3769 { 3770 other = XEXP (XEXP (x, 0), 1); 3771 inner = simplify_binary_operation (code, mode, 3772 XEXP (XEXP (x, 0), 0), 3773 XEXP (x, 1)); 3774 } 3775 3776 if (inner) 3777 return gen_binary (code, mode, other, inner); 3778 } 3779 } 3780 3781 /* A little bit of algebraic simplification here. */ 3782 switch (code) 3783 { 3784 case MEM: 3785 /* Ensure that our address has any ASHIFTs converted to MULT in case 3786 address-recognizing predicates are called later. */ 3787 temp = make_compound_operation (XEXP (x, 0), MEM); 3788 SUBST (XEXP (x, 0), temp); 3789 break; 3790 3791 case SUBREG: 3792 if (op0_mode == VOIDmode) 3793 op0_mode = GET_MODE (SUBREG_REG (x)); 3794 3795 /* simplify_subreg can't use gen_lowpart_for_combine. */ 3796 if (CONSTANT_P (SUBREG_REG (x)) 3797 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)) 3798 return gen_lowpart_for_combine (mode, SUBREG_REG (x)); 3799 3800 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC) 3801 break; 3802 { 3803 rtx temp; 3804 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode, 3805 SUBREG_BYTE (x)); 3806 if (temp) 3807 return temp; 3808 } 3809 3810 /* Note that we cannot do any narrowing for non-constants since 3811 we might have been counting on using the fact that some bits were 3812 zero. We now do this in the SET. */ 3813 3814 break; 3815 3816 case NOT: 3817 /* (not (plus X -1)) can become (neg X). */ 3818 if (GET_CODE (XEXP (x, 0)) == PLUS 3819 && XEXP (XEXP (x, 0), 1) == constm1_rtx) 3820 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0)); 3821 3822 /* Similarly, (not (neg X)) is (plus X -1). */ 3823 if (GET_CODE (XEXP (x, 0)) == NEG) 3824 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx); 3825 3826 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */ 3827 if (GET_CODE (XEXP (x, 0)) == XOR 3828 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3829 && (temp = simplify_unary_operation (NOT, mode, 3830 XEXP (XEXP (x, 0), 1), 3831 mode)) != 0) 3832 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp); 3833 3834 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands 3835 other than 1, but that is not valid. We could do a similar 3836 simplification for (not (lshiftrt C X)) where C is just the sign bit, 3837 but this doesn't seem common enough to bother with. */ 3838 if (GET_CODE (XEXP (x, 0)) == ASHIFT 3839 && XEXP (XEXP (x, 0), 0) == const1_rtx) 3840 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode, 3841 const1_rtx, mode), 3842 XEXP (XEXP (x, 0), 1)); 3843 3844 if (GET_CODE (XEXP (x, 0)) == SUBREG 3845 && subreg_lowpart_p (XEXP (x, 0)) 3846 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) 3847 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0))))) 3848 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT 3849 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx) 3850 { 3851 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0))); 3852 3853 x = gen_rtx_ROTATE (inner_mode, 3854 simplify_gen_unary (NOT, inner_mode, const1_rtx, 3855 inner_mode), 3856 XEXP (SUBREG_REG (XEXP (x, 0)), 1)); 3857 return gen_lowpart_for_combine (mode, x); 3858 } 3859 3860 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by 3861 reversing the comparison code if valid. */ 3862 if (STORE_FLAG_VALUE == -1 3863 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 3864 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0), 3865 XEXP (XEXP (x, 0), 1)))) 3866 return reversed; 3867 3868 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1 3869 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can 3870 perform the above simplification. */ 3871 3872 if (STORE_FLAG_VALUE == -1 3873 && GET_CODE (XEXP (x, 0)) == ASHIFTRT 3874 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3875 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1) 3876 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx); 3877 3878 /* Apply De Morgan's laws to reduce number of patterns for machines 3879 with negating logical insns (and-not, nand, etc.). If result has 3880 only one NOT, put it first, since that is how the patterns are 3881 coded. */ 3882 3883 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND) 3884 { 3885 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1); 3886 enum machine_mode op_mode; 3887 3888 op_mode = GET_MODE (in1); 3889 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode); 3890 3891 op_mode = GET_MODE (in2); 3892 if (op_mode == VOIDmode) 3893 op_mode = mode; 3894 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode); 3895 3896 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT) 3897 { 3898 rtx tem = in2; 3899 in2 = in1; in1 = tem; 3900 } 3901 3902 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR, 3903 mode, in1, in2); 3904 } 3905 break; 3906 3907 case NEG: 3908 /* (neg (plus X 1)) can become (not X). */ 3909 if (GET_CODE (XEXP (x, 0)) == PLUS 3910 && XEXP (XEXP (x, 0), 1) == const1_rtx) 3911 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0)); 3912 3913 /* Similarly, (neg (not X)) is (plus X 1). */ 3914 if (GET_CODE (XEXP (x, 0)) == NOT) 3915 return plus_constant (XEXP (XEXP (x, 0), 0), 1); 3916 3917 /* (neg (minus X Y)) can become (minus Y X). */ 3918 if (GET_CODE (XEXP (x, 0)) == MINUS 3919 && (! FLOAT_MODE_P (mode) 3920 /* x-y != -(y-x) with IEEE floating point. */ 3921 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT 3922 || flag_unsafe_math_optimizations)) 3923 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1), 3924 XEXP (XEXP (x, 0), 0)); 3925 3926 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */ 3927 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx 3928 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1) 3929 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx); 3930 3931 /* NEG commutes with ASHIFT since it is multiplication. Only do this 3932 if we can then eliminate the NEG (e.g., 3933 if the operand is a constant). */ 3934 3935 if (GET_CODE (XEXP (x, 0)) == ASHIFT) 3936 { 3937 temp = simplify_unary_operation (NEG, mode, 3938 XEXP (XEXP (x, 0), 0), mode); 3939 if (temp) 3940 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1)); 3941 } 3942 3943 temp = expand_compound_operation (XEXP (x, 0)); 3944 3945 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be 3946 replaced by (lshiftrt X C). This will convert 3947 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ 3948 3949 if (GET_CODE (temp) == ASHIFTRT 3950 && GET_CODE (XEXP (temp, 1)) == CONST_INT 3951 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1) 3952 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0), 3953 INTVAL (XEXP (temp, 1))); 3954 3955 /* If X has only a single bit that might be nonzero, say, bit I, convert 3956 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of 3957 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to 3958 (sign_extract X 1 Y). But only do this if TEMP isn't a register 3959 or a SUBREG of one since we'd be making the expression more 3960 complex if it was just a register. */ 3961 3962 if (GET_CODE (temp) != REG 3963 && ! (GET_CODE (temp) == SUBREG 3964 && GET_CODE (SUBREG_REG (temp)) == REG) 3965 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) 3966 { 3967 rtx temp1 = simplify_shift_const 3968 (NULL_RTX, ASHIFTRT, mode, 3969 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, 3970 GET_MODE_BITSIZE (mode) - 1 - i), 3971 GET_MODE_BITSIZE (mode) - 1 - i); 3972 3973 /* If all we did was surround TEMP with the two shifts, we 3974 haven't improved anything, so don't use it. Otherwise, 3975 we are better off with TEMP1. */ 3976 if (GET_CODE (temp1) != ASHIFTRT 3977 || GET_CODE (XEXP (temp1, 0)) != ASHIFT 3978 || XEXP (XEXP (temp1, 0), 0) != temp) 3979 return temp1; 3980 } 3981 break; 3982 3983 case TRUNCATE: 3984 /* We can't handle truncation to a partial integer mode here 3985 because we don't know the real bitsize of the partial 3986 integer mode. */ 3987 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) 3988 break; 3989 3990 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 3991 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 3992 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))) 3993 SUBST (XEXP (x, 0), 3994 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), 3995 GET_MODE_MASK (mode), NULL_RTX, 0)); 3996 3997 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */ 3998 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND 3999 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) 4000 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) 4001 return XEXP (XEXP (x, 0), 0); 4002 4003 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is 4004 (OP:SI foo:SI) if OP is NEG or ABS. */ 4005 if ((GET_CODE (XEXP (x, 0)) == ABS 4006 || GET_CODE (XEXP (x, 0)) == NEG) 4007 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND 4008 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND) 4009 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) 4010 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode, 4011 XEXP (XEXP (XEXP (x, 0), 0), 0), mode); 4012 4013 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is 4014 (truncate:SI x). */ 4015 if (GET_CODE (XEXP (x, 0)) == SUBREG 4016 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE 4017 && subreg_lowpart_p (XEXP (x, 0))) 4018 return SUBREG_REG (XEXP (x, 0)); 4019 4020 /* If we know that the value is already truncated, we can 4021 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION 4022 is nonzero for the corresponding modes. But don't do this 4023 for an (LSHIFTRT (MULT ...)) since this will cause problems 4024 with the umulXi3_highpart patterns. */ 4025 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 4026 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) 4027 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 4028 >= GET_MODE_BITSIZE (mode) + 1 4029 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT 4030 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)) 4031 return gen_lowpart_for_combine (mode, XEXP (x, 0)); 4032 4033 /* A truncate of a comparison can be replaced with a subreg if 4034 STORE_FLAG_VALUE permits. This is like the previous test, 4035 but it works even if the comparison is done in a mode larger 4036 than HOST_BITS_PER_WIDE_INT. */ 4037 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4038 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 4039 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0) 4040 return gen_lowpart_for_combine (mode, XEXP (x, 0)); 4041 4042 /* Similarly, a truncate of a register whose value is a 4043 comparison can be replaced with a subreg if STORE_FLAG_VALUE 4044 permits. */ 4045 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4046 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0 4047 && (temp = get_last_value (XEXP (x, 0))) 4048 && GET_RTX_CLASS (GET_CODE (temp)) == '<') 4049 return gen_lowpart_for_combine (mode, XEXP (x, 0)); 4050 4051 break; 4052 4053 case FLOAT_TRUNCATE: 4054 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */ 4055 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND 4056 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) 4057 return XEXP (XEXP (x, 0), 0); 4058 4059 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is 4060 (OP:SF foo:SF) if OP is NEG or ABS. */ 4061 if ((GET_CODE (XEXP (x, 0)) == ABS 4062 || GET_CODE (XEXP (x, 0)) == NEG) 4063 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND 4064 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) 4065 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode, 4066 XEXP (XEXP (XEXP (x, 0), 0), 0), mode); 4067 4068 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0)) 4069 is (float_truncate:SF x). */ 4070 if (GET_CODE (XEXP (x, 0)) == SUBREG 4071 && subreg_lowpart_p (XEXP (x, 0)) 4072 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE) 4073 return SUBREG_REG (XEXP (x, 0)); 4074 break; 4075 4076#ifdef HAVE_cc0 4077 case COMPARE: 4078 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't 4079 using cc0, in which case we want to leave it as a COMPARE 4080 so we can distinguish it from a register-register-copy. */ 4081 if (XEXP (x, 1) == const0_rtx) 4082 return XEXP (x, 0); 4083 4084 /* In IEEE floating point, x-0 is not the same as x. */ 4085 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT 4086 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))) 4087 || flag_unsafe_math_optimizations) 4088 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0)))) 4089 return XEXP (x, 0); 4090 break; 4091#endif 4092 4093 case CONST: 4094 /* (const (const X)) can become (const X). Do it this way rather than 4095 returning the inner CONST since CONST can be shared with a 4096 REG_EQUAL note. */ 4097 if (GET_CODE (XEXP (x, 0)) == CONST) 4098 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4099 break; 4100 4101#ifdef HAVE_lo_sum 4102 case LO_SUM: 4103 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we 4104 can add in an offset. find_split_point will split this address up 4105 again if it doesn't match. */ 4106 if (GET_CODE (XEXP (x, 0)) == HIGH 4107 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) 4108 return XEXP (x, 1); 4109 break; 4110#endif 4111 4112 case PLUS: 4113 /* If we have (plus (plus (A const) B)), associate it so that CONST is 4114 outermost. That's because that's the way indexed addresses are 4115 supposed to appear. This code used to check many more cases, but 4116 they are now checked elsewhere. */ 4117 if (GET_CODE (XEXP (x, 0)) == PLUS 4118 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1))) 4119 return gen_binary (PLUS, mode, 4120 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), 4121 XEXP (x, 1)), 4122 XEXP (XEXP (x, 0), 1)); 4123 4124 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) 4125 when c is (const_int (pow2 + 1) / 2) is a sign extension of a 4126 bit-field and can be replaced by either a sign_extend or a 4127 sign_extract. The `and' may be a zero_extend and the two 4128 <c>, -<c> constants may be reversed. */ 4129 if (GET_CODE (XEXP (x, 0)) == XOR 4130 && GET_CODE (XEXP (x, 1)) == CONST_INT 4131 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 4132 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1)) 4133 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 4134 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) 4135 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4136 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND 4137 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT 4138 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) 4139 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1)) 4140 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND 4141 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) 4142 == (unsigned int) i + 1)))) 4143 return simplify_shift_const 4144 (NULL_RTX, ASHIFTRT, mode, 4145 simplify_shift_const (NULL_RTX, ASHIFT, mode, 4146 XEXP (XEXP (XEXP (x, 0), 0), 0), 4147 GET_MODE_BITSIZE (mode) - (i + 1)), 4148 GET_MODE_BITSIZE (mode) - (i + 1)); 4149 4150 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if 4151 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE 4152 is 1. This produces better code than the alternative immediately 4153 below. */ 4154 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 4155 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx) 4156 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)) 4157 && (reversed = reversed_comparison (XEXP (x, 0), mode, 4158 XEXP (XEXP (x, 0), 0), 4159 XEXP (XEXP (x, 0), 1)))) 4160 return 4161 simplify_gen_unary (NEG, mode, reversed, mode); 4162 4163 /* If only the low-order bit of X is possibly nonzero, (plus x -1) 4164 can become (ashiftrt (ashift (xor x 1) C) C) where C is 4165 the bitsize of the mode - 1. This allows simplification of 4166 "a = (b & 8) == 0;" */ 4167 if (XEXP (x, 1) == constm1_rtx 4168 && GET_CODE (XEXP (x, 0)) != REG 4169 && ! (GET_CODE (XEXP (x,0)) == SUBREG 4170 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG) 4171 && nonzero_bits (XEXP (x, 0), mode) == 1) 4172 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, 4173 simplify_shift_const (NULL_RTX, ASHIFT, mode, 4174 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx), 4175 GET_MODE_BITSIZE (mode) - 1), 4176 GET_MODE_BITSIZE (mode) - 1); 4177 4178 /* If we are adding two things that have no bits in common, convert 4179 the addition into an IOR. This will often be further simplified, 4180 for example in cases like ((a & 1) + (a & 2)), which can 4181 become a & 3. */ 4182 4183 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4184 && (nonzero_bits (XEXP (x, 0), mode) 4185 & nonzero_bits (XEXP (x, 1), mode)) == 0) 4186 { 4187 /* Try to simplify the expression further. */ 4188 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); 4189 temp = combine_simplify_rtx (tor, mode, last, in_dest); 4190 4191 /* If we could, great. If not, do not go ahead with the IOR 4192 replacement, since PLUS appears in many special purpose 4193 address arithmetic instructions. */ 4194 if (GET_CODE (temp) != CLOBBER && temp != tor) 4195 return temp; 4196 } 4197 break; 4198 4199 case MINUS: 4200 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done 4201 by reversing the comparison code if valid. */ 4202 if (STORE_FLAG_VALUE == 1 4203 && XEXP (x, 0) == const1_rtx 4204 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<' 4205 && (reversed = reversed_comparison (XEXP (x, 1), mode, 4206 XEXP (XEXP (x, 1), 0), 4207 XEXP (XEXP (x, 1), 1)))) 4208 return reversed; 4209 4210 /* (minus <foo> (and <foo> (const_int -pow2))) becomes 4211 (and <foo> (const_int pow2-1)) */ 4212 if (GET_CODE (XEXP (x, 1)) == AND 4213 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 4214 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0 4215 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) 4216 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), 4217 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1); 4218 4219 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for 4220 integers. */ 4221 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode)) 4222 return gen_binary (MINUS, mode, 4223 gen_binary (MINUS, mode, XEXP (x, 0), 4224 XEXP (XEXP (x, 1), 0)), 4225 XEXP (XEXP (x, 1), 1)); 4226 break; 4227 4228 case MULT: 4229 /* If we have (mult (plus A B) C), apply the distributive law and then 4230 the inverse distributive law to see if things simplify. This 4231 occurs mostly in addresses, often when unrolling loops. */ 4232 4233 if (GET_CODE (XEXP (x, 0)) == PLUS) 4234 { 4235 x = apply_distributive_law 4236 (gen_binary (PLUS, mode, 4237 gen_binary (MULT, mode, 4238 XEXP (XEXP (x, 0), 0), XEXP (x, 1)), 4239 gen_binary (MULT, mode, 4240 XEXP (XEXP (x, 0), 1), 4241 copy_rtx (XEXP (x, 1))))); 4242 4243 if (GET_CODE (x) != MULT) 4244 return x; 4245 } 4246 /* Try simplify a*(b/c) as (a*b)/c. */ 4247 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations 4248 && GET_CODE (XEXP (x, 0)) == DIV) 4249 { 4250 rtx tem = simplify_binary_operation (MULT, mode, 4251 XEXP (XEXP (x, 0), 0), 4252 XEXP (x, 1)); 4253 if (tem) 4254 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1)); 4255 } 4256 break; 4257 4258 case UDIV: 4259 /* If this is a divide by a power of two, treat it as a shift if 4260 its first operand is a shift. */ 4261 if (GET_CODE (XEXP (x, 1)) == CONST_INT 4262 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 4263 && (GET_CODE (XEXP (x, 0)) == ASHIFT 4264 || GET_CODE (XEXP (x, 0)) == LSHIFTRT 4265 || GET_CODE (XEXP (x, 0)) == ASHIFTRT 4266 || GET_CODE (XEXP (x, 0)) == ROTATE 4267 || GET_CODE (XEXP (x, 0)) == ROTATERT)) 4268 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); 4269 break; 4270 4271 case EQ: case NE: 4272 case GT: case GTU: case GE: case GEU: 4273 case LT: case LTU: case LE: case LEU: 4274 case UNEQ: case LTGT: 4275 case UNGT: case UNGE: 4276 case UNLT: case UNLE: 4277 case UNORDERED: case ORDERED: 4278 /* If the first operand is a condition code, we can't do anything 4279 with it. */ 4280 if (GET_CODE (XEXP (x, 0)) == COMPARE 4281 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC 4282#ifdef HAVE_cc0 4283 && XEXP (x, 0) != cc0_rtx 4284#endif 4285 )) 4286 { 4287 rtx op0 = XEXP (x, 0); 4288 rtx op1 = XEXP (x, 1); 4289 enum rtx_code new_code; 4290 4291 if (GET_CODE (op0) == COMPARE) 4292 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); 4293 4294 /* Simplify our comparison, if possible. */ 4295 new_code = simplify_comparison (code, &op0, &op1); 4296 4297 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X 4298 if only the low-order bit is possibly nonzero in X (such as when 4299 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to 4300 (xor X 1) or (minus 1 X); we use the former. Finally, if X is 4301 known to be either 0 or -1, NE becomes a NEG and EQ becomes 4302 (plus X 1). 4303 4304 Remove any ZERO_EXTRACT we made when thinking this was a 4305 comparison. It may now be simpler to use, e.g., an AND. If a 4306 ZERO_EXTRACT is indeed appropriate, it will be placed back by 4307 the call to make_compound_operation in the SET case. */ 4308 4309 if (STORE_FLAG_VALUE == 1 4310 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4311 && op1 == const0_rtx 4312 && mode == GET_MODE (op0) 4313 && nonzero_bits (op0, mode) == 1) 4314 return gen_lowpart_for_combine (mode, 4315 expand_compound_operation (op0)); 4316 4317 else if (STORE_FLAG_VALUE == 1 4318 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4319 && op1 == const0_rtx 4320 && mode == GET_MODE (op0) 4321 && (num_sign_bit_copies (op0, mode) 4322 == GET_MODE_BITSIZE (mode))) 4323 { 4324 op0 = expand_compound_operation (op0); 4325 return simplify_gen_unary (NEG, mode, 4326 gen_lowpart_for_combine (mode, op0), 4327 mode); 4328 } 4329 4330 else if (STORE_FLAG_VALUE == 1 4331 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4332 && op1 == const0_rtx 4333 && mode == GET_MODE (op0) 4334 && nonzero_bits (op0, mode) == 1) 4335 { 4336 op0 = expand_compound_operation (op0); 4337 return gen_binary (XOR, mode, 4338 gen_lowpart_for_combine (mode, op0), 4339 const1_rtx); 4340 } 4341 4342 else if (STORE_FLAG_VALUE == 1 4343 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4344 && op1 == const0_rtx 4345 && mode == GET_MODE (op0) 4346 && (num_sign_bit_copies (op0, mode) 4347 == GET_MODE_BITSIZE (mode))) 4348 { 4349 op0 = expand_compound_operation (op0); 4350 return plus_constant (gen_lowpart_for_combine (mode, op0), 1); 4351 } 4352 4353 /* If STORE_FLAG_VALUE is -1, we have cases similar to 4354 those above. */ 4355 if (STORE_FLAG_VALUE == -1 4356 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4357 && op1 == const0_rtx 4358 && (num_sign_bit_copies (op0, mode) 4359 == GET_MODE_BITSIZE (mode))) 4360 return gen_lowpart_for_combine (mode, 4361 expand_compound_operation (op0)); 4362 4363 else if (STORE_FLAG_VALUE == -1 4364 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4365 && op1 == const0_rtx 4366 && mode == GET_MODE (op0) 4367 && nonzero_bits (op0, mode) == 1) 4368 { 4369 op0 = expand_compound_operation (op0); 4370 return simplify_gen_unary (NEG, mode, 4371 gen_lowpart_for_combine (mode, op0), 4372 mode); 4373 } 4374 4375 else if (STORE_FLAG_VALUE == -1 4376 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4377 && op1 == const0_rtx 4378 && mode == GET_MODE (op0) 4379 && (num_sign_bit_copies (op0, mode) 4380 == GET_MODE_BITSIZE (mode))) 4381 { 4382 op0 = expand_compound_operation (op0); 4383 return simplify_gen_unary (NOT, mode, 4384 gen_lowpart_for_combine (mode, op0), 4385 mode); 4386 } 4387 4388 /* If X is 0/1, (eq X 0) is X-1. */ 4389 else if (STORE_FLAG_VALUE == -1 4390 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4391 && op1 == const0_rtx 4392 && mode == GET_MODE (op0) 4393 && nonzero_bits (op0, mode) == 1) 4394 { 4395 op0 = expand_compound_operation (op0); 4396 return plus_constant (gen_lowpart_for_combine (mode, op0), -1); 4397 } 4398 4399 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just 4400 one bit that might be nonzero, we can convert (ne x 0) to 4401 (ashift x c) where C puts the bit in the sign bit. Remove any 4402 AND with STORE_FLAG_VALUE when we are done, since we are only 4403 going to test the sign bit. */ 4404 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4405 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4406 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) 4407 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1)) 4408 && op1 == const0_rtx 4409 && mode == GET_MODE (op0) 4410 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) 4411 { 4412 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, 4413 expand_compound_operation (op0), 4414 GET_MODE_BITSIZE (mode) - 1 - i); 4415 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) 4416 return XEXP (x, 0); 4417 else 4418 return x; 4419 } 4420 4421 /* If the code changed, return a whole new comparison. */ 4422 if (new_code != code) 4423 return gen_rtx_fmt_ee (new_code, mode, op0, op1); 4424 4425 /* Otherwise, keep this operation, but maybe change its operands. 4426 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ 4427 SUBST (XEXP (x, 0), op0); 4428 SUBST (XEXP (x, 1), op1); 4429 } 4430 break; 4431 4432 case IF_THEN_ELSE: 4433 return simplify_if_then_else (x); 4434 4435 case ZERO_EXTRACT: 4436 case SIGN_EXTRACT: 4437 case ZERO_EXTEND: 4438 case SIGN_EXTEND: 4439 /* If we are processing SET_DEST, we are done. */ 4440 if (in_dest) 4441 return x; 4442 4443 return expand_compound_operation (x); 4444 4445 case SET: 4446 return simplify_set (x); 4447 4448 case AND: 4449 case IOR: 4450 case XOR: 4451 return simplify_logical (x, last); 4452 4453 case ABS: 4454 /* (abs (neg <foo>)) -> (abs <foo>) */ 4455 if (GET_CODE (XEXP (x, 0)) == NEG) 4456 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4457 4458 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS), 4459 do nothing. */ 4460 if (GET_MODE (XEXP (x, 0)) == VOIDmode) 4461 break; 4462 4463 /* If operand is something known to be positive, ignore the ABS. */ 4464 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS 4465 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 4466 <= HOST_BITS_PER_WIDE_INT) 4467 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 4468 & ((HOST_WIDE_INT) 1 4469 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))) 4470 == 0))) 4471 return XEXP (x, 0); 4472 4473 /* If operand is known to be only -1 or 0, convert ABS to NEG. */ 4474 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode)) 4475 return gen_rtx_NEG (mode, XEXP (x, 0)); 4476 4477 break; 4478 4479 case FFS: 4480 /* (ffs (*_extend <X>)) = (ffs <X>) */ 4481 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND 4482 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) 4483 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4484 break; 4485 4486 case FLOAT: 4487 /* (float (sign_extend <X>)) = (float <X>). */ 4488 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) 4489 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4490 break; 4491 4492 case ASHIFT: 4493 case LSHIFTRT: 4494 case ASHIFTRT: 4495 case ROTATE: 4496 case ROTATERT: 4497 /* If this is a shift by a constant amount, simplify it. */ 4498 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 4499 return simplify_shift_const (x, code, mode, XEXP (x, 0), 4500 INTVAL (XEXP (x, 1))); 4501 4502#ifdef SHIFT_COUNT_TRUNCATED 4503 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG) 4504 SUBST (XEXP (x, 1), 4505 force_to_mode (XEXP (x, 1), GET_MODE (x), 4506 ((HOST_WIDE_INT) 1 4507 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) 4508 - 1, 4509 NULL_RTX, 0)); 4510#endif 4511 4512 break; 4513 4514 case VEC_SELECT: 4515 { 4516 rtx op0 = XEXP (x, 0); 4517 rtx op1 = XEXP (x, 1); 4518 int len; 4519 4520 if (GET_CODE (op1) != PARALLEL) 4521 abort (); 4522 len = XVECLEN (op1, 0); 4523 if (len == 1 4524 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT 4525 && GET_CODE (op0) == VEC_CONCAT) 4526 { 4527 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x)); 4528 4529 /* Try to find the element in the VEC_CONCAT. */ 4530 for (;;) 4531 { 4532 if (GET_MODE (op0) == GET_MODE (x)) 4533 return op0; 4534 if (GET_CODE (op0) == VEC_CONCAT) 4535 { 4536 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))); 4537 if (op0_size < offset) 4538 op0 = XEXP (op0, 0); 4539 else 4540 { 4541 offset -= op0_size; 4542 op0 = XEXP (op0, 1); 4543 } 4544 } 4545 else 4546 break; 4547 } 4548 } 4549 } 4550 4551 break; 4552 4553 default: 4554 break; 4555 } 4556 4557 return x; 4558} 4559 4560/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ 4561 4562static rtx 4563simplify_if_then_else (x) 4564 rtx x; 4565{ 4566 enum machine_mode mode = GET_MODE (x); 4567 rtx cond = XEXP (x, 0); 4568 rtx true_rtx = XEXP (x, 1); 4569 rtx false_rtx = XEXP (x, 2); 4570 enum rtx_code true_code = GET_CODE (cond); 4571 int comparison_p = GET_RTX_CLASS (true_code) == '<'; 4572 rtx temp; 4573 int i; 4574 enum rtx_code false_code; 4575 rtx reversed; 4576 4577 /* Simplify storing of the truth value. */ 4578 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx) 4579 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1)); 4580 4581 /* Also when the truth value has to be reversed. */ 4582 if (comparison_p 4583 && true_rtx == const0_rtx && false_rtx == const_true_rtx 4584 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0), 4585 XEXP (cond, 1)))) 4586 return reversed; 4587 4588 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used 4589 in it is being compared against certain values. Get the true and false 4590 comparisons and see if that says anything about the value of each arm. */ 4591 4592 if (comparison_p 4593 && ((false_code = combine_reversed_comparison_code (cond)) 4594 != UNKNOWN) 4595 && GET_CODE (XEXP (cond, 0)) == REG) 4596 { 4597 HOST_WIDE_INT nzb; 4598 rtx from = XEXP (cond, 0); 4599 rtx true_val = XEXP (cond, 1); 4600 rtx false_val = true_val; 4601 int swapped = 0; 4602 4603 /* If FALSE_CODE is EQ, swap the codes and arms. */ 4604 4605 if (false_code == EQ) 4606 { 4607 swapped = 1, true_code = EQ, false_code = NE; 4608 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; 4609 } 4610 4611 /* If we are comparing against zero and the expression being tested has 4612 only a single bit that might be nonzero, that is its value when it is 4613 not equal to zero. Similarly if it is known to be -1 or 0. */ 4614 4615 if (true_code == EQ && true_val == const0_rtx 4616 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) 4617 false_code = EQ, false_val = GEN_INT (nzb); 4618 else if (true_code == EQ && true_val == const0_rtx 4619 && (num_sign_bit_copies (from, GET_MODE (from)) 4620 == GET_MODE_BITSIZE (GET_MODE (from)))) 4621 false_code = EQ, false_val = constm1_rtx; 4622 4623 /* Now simplify an arm if we know the value of the register in the 4624 branch and it is used in the arm. Be careful due to the potential 4625 of locally-shared RTL. */ 4626 4627 if (reg_mentioned_p (from, true_rtx)) 4628 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, 4629 from, true_val), 4630 pc_rtx, pc_rtx, 0, 0); 4631 if (reg_mentioned_p (from, false_rtx)) 4632 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, 4633 from, false_val), 4634 pc_rtx, pc_rtx, 0, 0); 4635 4636 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); 4637 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); 4638 4639 true_rtx = XEXP (x, 1); 4640 false_rtx = XEXP (x, 2); 4641 true_code = GET_CODE (cond); 4642 } 4643 4644 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be 4645 reversed, do so to avoid needing two sets of patterns for 4646 subtract-and-branch insns. Similarly if we have a constant in the true 4647 arm, the false arm is the same as the first operand of the comparison, or 4648 the false arm is more complicated than the true arm. */ 4649 4650 if (comparison_p 4651 && combine_reversed_comparison_code (cond) != UNKNOWN 4652 && (true_rtx == pc_rtx 4653 || (CONSTANT_P (true_rtx) 4654 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx) 4655 || true_rtx == const0_rtx 4656 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o' 4657 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o') 4658 || (GET_CODE (true_rtx) == SUBREG 4659 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o' 4660 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o') 4661 || reg_mentioned_p (true_rtx, false_rtx) 4662 || rtx_equal_p (false_rtx, XEXP (cond, 0)))) 4663 { 4664 true_code = reversed_comparison_code (cond, NULL); 4665 SUBST (XEXP (x, 0), 4666 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0), 4667 XEXP (cond, 1))); 4668 4669 SUBST (XEXP (x, 1), false_rtx); 4670 SUBST (XEXP (x, 2), true_rtx); 4671 4672 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; 4673 cond = XEXP (x, 0); 4674 4675 /* It is possible that the conditional has been simplified out. */ 4676 true_code = GET_CODE (cond); 4677 comparison_p = GET_RTX_CLASS (true_code) == '<'; 4678 } 4679 4680 /* If the two arms are identical, we don't need the comparison. */ 4681 4682 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond)) 4683 return true_rtx; 4684 4685 /* Convert a == b ? b : a to "a". */ 4686 if (true_code == EQ && ! side_effects_p (cond) 4687 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) 4688 && rtx_equal_p (XEXP (cond, 0), false_rtx) 4689 && rtx_equal_p (XEXP (cond, 1), true_rtx)) 4690 return false_rtx; 4691 else if (true_code == NE && ! side_effects_p (cond) 4692 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) 4693 && rtx_equal_p (XEXP (cond, 0), true_rtx) 4694 && rtx_equal_p (XEXP (cond, 1), false_rtx)) 4695 return true_rtx; 4696 4697 /* Look for cases where we have (abs x) or (neg (abs X)). */ 4698 4699 if (GET_MODE_CLASS (mode) == MODE_INT 4700 && GET_CODE (false_rtx) == NEG 4701 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0)) 4702 && comparison_p 4703 && rtx_equal_p (true_rtx, XEXP (cond, 0)) 4704 && ! side_effects_p (true_rtx)) 4705 switch (true_code) 4706 { 4707 case GT: 4708 case GE: 4709 return simplify_gen_unary (ABS, mode, true_rtx, mode); 4710 case LT: 4711 case LE: 4712 return 4713 simplify_gen_unary (NEG, mode, 4714 simplify_gen_unary (ABS, mode, true_rtx, mode), 4715 mode); 4716 default: 4717 break; 4718 } 4719 4720 /* Look for MIN or MAX. */ 4721 4722 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) 4723 && comparison_p 4724 && rtx_equal_p (XEXP (cond, 0), true_rtx) 4725 && rtx_equal_p (XEXP (cond, 1), false_rtx) 4726 && ! side_effects_p (cond)) 4727 switch (true_code) 4728 { 4729 case GE: 4730 case GT: 4731 return gen_binary (SMAX, mode, true_rtx, false_rtx); 4732 case LE: 4733 case LT: 4734 return gen_binary (SMIN, mode, true_rtx, false_rtx); 4735 case GEU: 4736 case GTU: 4737 return gen_binary (UMAX, mode, true_rtx, false_rtx); 4738 case LEU: 4739 case LTU: 4740 return gen_binary (UMIN, mode, true_rtx, false_rtx); 4741 default: 4742 break; 4743 } 4744 4745 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its 4746 second operand is zero, this can be done as (OP Z (mult COND C2)) where 4747 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or 4748 SIGN_EXTEND as long as Z is already extended (so we don't destroy it). 4749 We can do this kind of thing in some cases when STORE_FLAG_VALUE is 4750 neither 1 or -1, but it isn't worth checking for. */ 4751 4752 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 4753 && comparison_p && mode != VOIDmode && ! side_effects_p (x)) 4754 { 4755 rtx t = make_compound_operation (true_rtx, SET); 4756 rtx f = make_compound_operation (false_rtx, SET); 4757 rtx cond_op0 = XEXP (cond, 0); 4758 rtx cond_op1 = XEXP (cond, 1); 4759 enum rtx_code op = NIL, extend_op = NIL; 4760 enum machine_mode m = mode; 4761 rtx z = 0, c1 = NULL_RTX; 4762 4763 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS 4764 || GET_CODE (t) == IOR || GET_CODE (t) == XOR 4765 || GET_CODE (t) == ASHIFT 4766 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) 4767 && rtx_equal_p (XEXP (t, 0), f)) 4768 c1 = XEXP (t, 1), op = GET_CODE (t), z = f; 4769 4770 /* If an identity-zero op is commutative, check whether there 4771 would be a match if we swapped the operands. */ 4772 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR 4773 || GET_CODE (t) == XOR) 4774 && rtx_equal_p (XEXP (t, 1), f)) 4775 c1 = XEXP (t, 0), op = GET_CODE (t), z = f; 4776 else if (GET_CODE (t) == SIGN_EXTEND 4777 && (GET_CODE (XEXP (t, 0)) == PLUS 4778 || GET_CODE (XEXP (t, 0)) == MINUS 4779 || GET_CODE (XEXP (t, 0)) == IOR 4780 || GET_CODE (XEXP (t, 0)) == XOR 4781 || GET_CODE (XEXP (t, 0)) == ASHIFT 4782 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 4783 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 4784 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 4785 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 4786 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 4787 && (num_sign_bit_copies (f, GET_MODE (f)) 4788 > (GET_MODE_BITSIZE (mode) 4789 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0)))))) 4790 { 4791 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 4792 extend_op = SIGN_EXTEND; 4793 m = GET_MODE (XEXP (t, 0)); 4794 } 4795 else if (GET_CODE (t) == SIGN_EXTEND 4796 && (GET_CODE (XEXP (t, 0)) == PLUS 4797 || GET_CODE (XEXP (t, 0)) == IOR 4798 || GET_CODE (XEXP (t, 0)) == XOR) 4799 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 4800 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 4801 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 4802 && (num_sign_bit_copies (f, GET_MODE (f)) 4803 > (GET_MODE_BITSIZE (mode) 4804 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1)))))) 4805 { 4806 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 4807 extend_op = SIGN_EXTEND; 4808 m = GET_MODE (XEXP (t, 0)); 4809 } 4810 else if (GET_CODE (t) == ZERO_EXTEND 4811 && (GET_CODE (XEXP (t, 0)) == PLUS 4812 || GET_CODE (XEXP (t, 0)) == MINUS 4813 || GET_CODE (XEXP (t, 0)) == IOR 4814 || GET_CODE (XEXP (t, 0)) == XOR 4815 || GET_CODE (XEXP (t, 0)) == ASHIFT 4816 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 4817 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 4818 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 4819 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4820 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 4821 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 4822 && ((nonzero_bits (f, GET_MODE (f)) 4823 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) 4824 == 0)) 4825 { 4826 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 4827 extend_op = ZERO_EXTEND; 4828 m = GET_MODE (XEXP (t, 0)); 4829 } 4830 else if (GET_CODE (t) == ZERO_EXTEND 4831 && (GET_CODE (XEXP (t, 0)) == PLUS 4832 || GET_CODE (XEXP (t, 0)) == IOR 4833 || GET_CODE (XEXP (t, 0)) == XOR) 4834 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 4835 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4836 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 4837 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 4838 && ((nonzero_bits (f, GET_MODE (f)) 4839 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) 4840 == 0)) 4841 { 4842 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 4843 extend_op = ZERO_EXTEND; 4844 m = GET_MODE (XEXP (t, 0)); 4845 } 4846 4847 if (z) 4848 { 4849 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1), 4850 pc_rtx, pc_rtx, 0, 0); 4851 temp = gen_binary (MULT, m, temp, 4852 gen_binary (MULT, m, c1, const_true_rtx)); 4853 temp = subst (temp, pc_rtx, pc_rtx, 0, 0); 4854 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp); 4855 4856 if (extend_op != NIL) 4857 temp = simplify_gen_unary (extend_op, mode, temp, m); 4858 4859 return temp; 4860 } 4861 } 4862 4863 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or 4864 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the 4865 negation of a single bit, we can convert this operation to a shift. We 4866 can actually do this more generally, but it doesn't seem worth it. */ 4867 4868 if (true_code == NE && XEXP (cond, 1) == const0_rtx 4869 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT 4870 && ((1 == nonzero_bits (XEXP (cond, 0), mode) 4871 && (i = exact_log2 (INTVAL (true_rtx))) >= 0) 4872 || ((num_sign_bit_copies (XEXP (cond, 0), mode) 4873 == GET_MODE_BITSIZE (mode)) 4874 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0))) 4875 return 4876 simplify_shift_const (NULL_RTX, ASHIFT, mode, 4877 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i); 4878 4879 return x; 4880} 4881 4882/* Simplify X, a SET expression. Return the new expression. */ 4883 4884static rtx 4885simplify_set (x) 4886 rtx x; 4887{ 4888 rtx src = SET_SRC (x); 4889 rtx dest = SET_DEST (x); 4890 enum machine_mode mode 4891 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); 4892 rtx other_insn; 4893 rtx *cc_use; 4894 4895 /* (set (pc) (return)) gets written as (return). */ 4896 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN) 4897 return src; 4898 4899 /* Now that we know for sure which bits of SRC we are using, see if we can 4900 simplify the expression for the object knowing that we only need the 4901 low-order bits. */ 4902 4903 if (GET_MODE_CLASS (mode) == MODE_INT) 4904 { 4905 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0); 4906 SUBST (SET_SRC (x), src); 4907 } 4908 4909 /* If we are setting CC0 or if the source is a COMPARE, look for the use of 4910 the comparison result and try to simplify it unless we already have used 4911 undobuf.other_insn. */ 4912 if ((GET_CODE (src) == COMPARE 4913#ifdef HAVE_cc0 4914 || dest == cc0_rtx 4915#endif 4916 ) 4917 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 4918 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) 4919 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<' 4920 && rtx_equal_p (XEXP (*cc_use, 0), dest)) 4921 { 4922 enum rtx_code old_code = GET_CODE (*cc_use); 4923 enum rtx_code new_code; 4924 rtx op0, op1; 4925 int other_changed = 0; 4926 enum machine_mode compare_mode = GET_MODE (dest); 4927 4928 if (GET_CODE (src) == COMPARE) 4929 op0 = XEXP (src, 0), op1 = XEXP (src, 1); 4930 else 4931 op0 = src, op1 = const0_rtx; 4932 4933 /* Simplify our comparison, if possible. */ 4934 new_code = simplify_comparison (old_code, &op0, &op1); 4935 4936#ifdef EXTRA_CC_MODES 4937 /* If this machine has CC modes other than CCmode, check to see if we 4938 need to use a different CC mode here. */ 4939 compare_mode = SELECT_CC_MODE (new_code, op0, op1); 4940#endif /* EXTRA_CC_MODES */ 4941 4942#if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES) 4943 /* If the mode changed, we have to change SET_DEST, the mode in the 4944 compare, and the mode in the place SET_DEST is used. If SET_DEST is 4945 a hard register, just build new versions with the proper mode. If it 4946 is a pseudo, we lose unless it is only time we set the pseudo, in 4947 which case we can safely change its mode. */ 4948 if (compare_mode != GET_MODE (dest)) 4949 { 4950 unsigned int regno = REGNO (dest); 4951 rtx new_dest = gen_rtx_REG (compare_mode, regno); 4952 4953 if (regno < FIRST_PSEUDO_REGISTER 4954 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest))) 4955 { 4956 if (regno >= FIRST_PSEUDO_REGISTER) 4957 SUBST (regno_reg_rtx[regno], new_dest); 4958 4959 SUBST (SET_DEST (x), new_dest); 4960 SUBST (XEXP (*cc_use, 0), new_dest); 4961 other_changed = 1; 4962 4963 dest = new_dest; 4964 } 4965 } 4966#endif 4967 4968 /* If the code changed, we have to build a new comparison in 4969 undobuf.other_insn. */ 4970 if (new_code != old_code) 4971 { 4972 unsigned HOST_WIDE_INT mask; 4973 4974 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use), 4975 dest, const0_rtx)); 4976 4977 /* If the only change we made was to change an EQ into an NE or 4978 vice versa, OP0 has only one bit that might be nonzero, and OP1 4979 is zero, check if changing the user of the condition code will 4980 produce a valid insn. If it won't, we can keep the original code 4981 in that insn by surrounding our operation with an XOR. */ 4982 4983 if (((old_code == NE && new_code == EQ) 4984 || (old_code == EQ && new_code == NE)) 4985 && ! other_changed && op1 == const0_rtx 4986 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 4987 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0) 4988 { 4989 rtx pat = PATTERN (other_insn), note = 0; 4990 4991 if ((recog_for_combine (&pat, other_insn, ¬e) < 0 4992 && ! check_asm_operands (pat))) 4993 { 4994 PUT_CODE (*cc_use, old_code); 4995 other_insn = 0; 4996 4997 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask)); 4998 } 4999 } 5000 5001 other_changed = 1; 5002 } 5003 5004 if (other_changed) 5005 undobuf.other_insn = other_insn; 5006 5007#ifdef HAVE_cc0 5008 /* If we are now comparing against zero, change our source if 5009 needed. If we do not use cc0, we always have a COMPARE. */ 5010 if (op1 == const0_rtx && dest == cc0_rtx) 5011 { 5012 SUBST (SET_SRC (x), op0); 5013 src = op0; 5014 } 5015 else 5016#endif 5017 5018 /* Otherwise, if we didn't previously have a COMPARE in the 5019 correct mode, we need one. */ 5020 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode) 5021 { 5022 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); 5023 src = SET_SRC (x); 5024 } 5025 else 5026 { 5027 /* Otherwise, update the COMPARE if needed. */ 5028 SUBST (XEXP (src, 0), op0); 5029 SUBST (XEXP (src, 1), op1); 5030 } 5031 } 5032 else 5033 { 5034 /* Get SET_SRC in a form where we have placed back any 5035 compound expressions. Then do the checks below. */ 5036 src = make_compound_operation (src, SET); 5037 SUBST (SET_SRC (x), src); 5038 } 5039 5040 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, 5041 and X being a REG or (subreg (reg)), we may be able to convert this to 5042 (set (subreg:m2 x) (op)). 5043 5044 We can always do this if M1 is narrower than M2 because that means that 5045 we only care about the low bits of the result. 5046 5047 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot 5048 perform a narrower operation than requested since the high-order bits will 5049 be undefined. On machine where it is defined, this transformation is safe 5050 as long as M1 and M2 have the same number of words. */ 5051 5052 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 5053 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o' 5054 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) 5055 / UNITS_PER_WORD) 5056 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) 5057 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) 5058#ifndef WORD_REGISTER_OPERATIONS 5059 && (GET_MODE_SIZE (GET_MODE (src)) 5060 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) 5061#endif 5062#ifdef CLASS_CANNOT_CHANGE_MODE 5063 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER 5064 && (TEST_HARD_REG_BIT 5065 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], 5066 REGNO (dest))) 5067 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src), 5068 GET_MODE (SUBREG_REG (src)))) 5069#endif 5070 && (GET_CODE (dest) == REG 5071 || (GET_CODE (dest) == SUBREG 5072 && GET_CODE (SUBREG_REG (dest)) == REG))) 5073 { 5074 SUBST (SET_DEST (x), 5075 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)), 5076 dest)); 5077 SUBST (SET_SRC (x), SUBREG_REG (src)); 5078 5079 src = SET_SRC (x), dest = SET_DEST (x); 5080 } 5081 5082#ifdef LOAD_EXTEND_OP 5083 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this 5084 would require a paradoxical subreg. Replace the subreg with a 5085 zero_extend to avoid the reload that would otherwise be required. */ 5086 5087 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 5088 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL 5089 && SUBREG_BYTE (src) == 0 5090 && (GET_MODE_SIZE (GET_MODE (src)) 5091 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) 5092 && GET_CODE (SUBREG_REG (src)) == MEM) 5093 { 5094 SUBST (SET_SRC (x), 5095 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))), 5096 GET_MODE (src), SUBREG_REG (src))); 5097 5098 src = SET_SRC (x); 5099 } 5100#endif 5101 5102 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we 5103 are comparing an item known to be 0 or -1 against 0, use a logical 5104 operation instead. Check for one of the arms being an IOR of the other 5105 arm with some value. We compute three terms to be IOR'ed together. In 5106 practice, at most two will be nonzero. Then we do the IOR's. */ 5107 5108 if (GET_CODE (dest) != PC 5109 && GET_CODE (src) == IF_THEN_ELSE 5110 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT 5111 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) 5112 && XEXP (XEXP (src, 0), 1) == const0_rtx 5113 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) 5114#ifdef HAVE_conditional_move 5115 && ! can_conditionally_move_p (GET_MODE (src)) 5116#endif 5117 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), 5118 GET_MODE (XEXP (XEXP (src, 0), 0))) 5119 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0)))) 5120 && ! side_effects_p (src)) 5121 { 5122 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE 5123 ? XEXP (src, 1) : XEXP (src, 2)); 5124 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE 5125 ? XEXP (src, 2) : XEXP (src, 1)); 5126 rtx term1 = const0_rtx, term2, term3; 5127 5128 if (GET_CODE (true_rtx) == IOR 5129 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx)) 5130 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx; 5131 else if (GET_CODE (true_rtx) == IOR 5132 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx)) 5133 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx; 5134 else if (GET_CODE (false_rtx) == IOR 5135 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx)) 5136 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx; 5137 else if (GET_CODE (false_rtx) == IOR 5138 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx)) 5139 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx; 5140 5141 term2 = gen_binary (AND, GET_MODE (src), 5142 XEXP (XEXP (src, 0), 0), true_rtx); 5143 term3 = gen_binary (AND, GET_MODE (src), 5144 simplify_gen_unary (NOT, GET_MODE (src), 5145 XEXP (XEXP (src, 0), 0), 5146 GET_MODE (src)), 5147 false_rtx); 5148 5149 SUBST (SET_SRC (x), 5150 gen_binary (IOR, GET_MODE (src), 5151 gen_binary (IOR, GET_MODE (src), term1, term2), 5152 term3)); 5153 5154 src = SET_SRC (x); 5155 } 5156 5157 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this 5158 whole thing fail. */ 5159 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) 5160 return src; 5161 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) 5162 return dest; 5163 else 5164 /* Convert this into a field assignment operation, if possible. */ 5165 return make_field_assignment (x); 5166} 5167 5168/* Simplify, X, and AND, IOR, or XOR operation, and return the simplified 5169 result. LAST is nonzero if this is the last retry. */ 5170 5171static rtx 5172simplify_logical (x, last) 5173 rtx x; 5174 int last; 5175{ 5176 enum machine_mode mode = GET_MODE (x); 5177 rtx op0 = XEXP (x, 0); 5178 rtx op1 = XEXP (x, 1); 5179 rtx reversed; 5180 5181 switch (GET_CODE (x)) 5182 { 5183 case AND: 5184 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single 5185 insn (and may simplify more). */ 5186 if (GET_CODE (op0) == XOR 5187 && rtx_equal_p (XEXP (op0, 0), op1) 5188 && ! side_effects_p (op1)) 5189 x = gen_binary (AND, mode, 5190 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode), 5191 op1); 5192 5193 if (GET_CODE (op0) == XOR 5194 && rtx_equal_p (XEXP (op0, 1), op1) 5195 && ! side_effects_p (op1)) 5196 x = gen_binary (AND, mode, 5197 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode), 5198 op1); 5199 5200 /* Similarly for (~(A ^ B)) & A. */ 5201 if (GET_CODE (op0) == NOT 5202 && GET_CODE (XEXP (op0, 0)) == XOR 5203 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1) 5204 && ! side_effects_p (op1)) 5205 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1); 5206 5207 if (GET_CODE (op0) == NOT 5208 && GET_CODE (XEXP (op0, 0)) == XOR 5209 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1) 5210 && ! side_effects_p (op1)) 5211 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1); 5212 5213 /* We can call simplify_and_const_int only if we don't lose 5214 any (sign) bits when converting INTVAL (op1) to 5215 "unsigned HOST_WIDE_INT". */ 5216 if (GET_CODE (op1) == CONST_INT 5217 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5218 || INTVAL (op1) > 0)) 5219 { 5220 x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); 5221 5222 /* If we have (ior (and (X C1) C2)) and the next restart would be 5223 the last, simplify this by making C1 as small as possible 5224 and then exit. */ 5225 if (last 5226 && GET_CODE (x) == IOR && GET_CODE (op0) == AND 5227 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5228 && GET_CODE (op1) == CONST_INT) 5229 return gen_binary (IOR, mode, 5230 gen_binary (AND, mode, XEXP (op0, 0), 5231 GEN_INT (INTVAL (XEXP (op0, 1)) 5232 & ~INTVAL (op1))), op1); 5233 5234 if (GET_CODE (x) != AND) 5235 return x; 5236 5237 if (GET_RTX_CLASS (GET_CODE (x)) == 'c' 5238 || GET_RTX_CLASS (GET_CODE (x)) == '2') 5239 op0 = XEXP (x, 0), op1 = XEXP (x, 1); 5240 } 5241 5242 /* Convert (A | B) & A to A. */ 5243 if (GET_CODE (op0) == IOR 5244 && (rtx_equal_p (XEXP (op0, 0), op1) 5245 || rtx_equal_p (XEXP (op0, 1), op1)) 5246 && ! side_effects_p (XEXP (op0, 0)) 5247 && ! side_effects_p (XEXP (op0, 1))) 5248 return op1; 5249 5250 /* In the following group of tests (and those in case IOR below), 5251 we start with some combination of logical operations and apply 5252 the distributive law followed by the inverse distributive law. 5253 Most of the time, this results in no change. However, if some of 5254 the operands are the same or inverses of each other, simplifications 5255 will result. 5256 5257 For example, (and (ior A B) (not B)) can occur as the result of 5258 expanding a bit field assignment. When we apply the distributive 5259 law to this, we get (ior (and (A (not B))) (and (B (not B)))), 5260 which then simplifies to (and (A (not B))). 5261 5262 If we have (and (ior A B) C), apply the distributive law and then 5263 the inverse distributive law to see if things simplify. */ 5264 5265 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) 5266 { 5267 x = apply_distributive_law 5268 (gen_binary (GET_CODE (op0), mode, 5269 gen_binary (AND, mode, XEXP (op0, 0), op1), 5270 gen_binary (AND, mode, XEXP (op0, 1), 5271 copy_rtx (op1)))); 5272 if (GET_CODE (x) != AND) 5273 return x; 5274 } 5275 5276 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) 5277 return apply_distributive_law 5278 (gen_binary (GET_CODE (op1), mode, 5279 gen_binary (AND, mode, XEXP (op1, 0), op0), 5280 gen_binary (AND, mode, XEXP (op1, 1), 5281 copy_rtx (op0)))); 5282 5283 /* Similarly, taking advantage of the fact that 5284 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */ 5285 5286 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR) 5287 return apply_distributive_law 5288 (gen_binary (XOR, mode, 5289 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)), 5290 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)), 5291 XEXP (op1, 1)))); 5292 5293 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR) 5294 return apply_distributive_law 5295 (gen_binary (XOR, mode, 5296 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)), 5297 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1)))); 5298 break; 5299 5300 case IOR: 5301 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ 5302 if (GET_CODE (op1) == CONST_INT 5303 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5304 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0) 5305 return op1; 5306 5307 /* Convert (A & B) | A to A. */ 5308 if (GET_CODE (op0) == AND 5309 && (rtx_equal_p (XEXP (op0, 0), op1) 5310 || rtx_equal_p (XEXP (op0, 1), op1)) 5311 && ! side_effects_p (XEXP (op0, 0)) 5312 && ! side_effects_p (XEXP (op0, 1))) 5313 return op1; 5314 5315 /* If we have (ior (and A B) C), apply the distributive law and then 5316 the inverse distributive law to see if things simplify. */ 5317 5318 if (GET_CODE (op0) == AND) 5319 { 5320 x = apply_distributive_law 5321 (gen_binary (AND, mode, 5322 gen_binary (IOR, mode, XEXP (op0, 0), op1), 5323 gen_binary (IOR, mode, XEXP (op0, 1), 5324 copy_rtx (op1)))); 5325 5326 if (GET_CODE (x) != IOR) 5327 return x; 5328 } 5329 5330 if (GET_CODE (op1) == AND) 5331 { 5332 x = apply_distributive_law 5333 (gen_binary (AND, mode, 5334 gen_binary (IOR, mode, XEXP (op1, 0), op0), 5335 gen_binary (IOR, mode, XEXP (op1, 1), 5336 copy_rtx (op0)))); 5337 5338 if (GET_CODE (x) != IOR) 5339 return x; 5340 } 5341 5342 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the 5343 mode size to (rotate A CX). */ 5344 5345 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT) 5346 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT)) 5347 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0)) 5348 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5349 && GET_CODE (XEXP (op1, 1)) == CONST_INT 5350 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1)) 5351 == GET_MODE_BITSIZE (mode))) 5352 return gen_rtx_ROTATE (mode, XEXP (op0, 0), 5353 (GET_CODE (op0) == ASHIFT 5354 ? XEXP (op0, 1) : XEXP (op1, 1))); 5355 5356 /* If OP0 is (ashiftrt (plus ...) C), it might actually be 5357 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS 5358 does not affect any of the bits in OP1, it can really be done 5359 as a PLUS and we can associate. We do this by seeing if OP1 5360 can be safely shifted left C bits. */ 5361 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT 5362 && GET_CODE (XEXP (op0, 0)) == PLUS 5363 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 5364 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5365 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT) 5366 { 5367 int count = INTVAL (XEXP (op0, 1)); 5368 HOST_WIDE_INT mask = INTVAL (op1) << count; 5369 5370 if (mask >> count == INTVAL (op1) 5371 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0) 5372 { 5373 SUBST (XEXP (XEXP (op0, 0), 1), 5374 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask)); 5375 return op0; 5376 } 5377 } 5378 break; 5379 5380 case XOR: 5381 /* If we are XORing two things that have no bits in common, 5382 convert them into an IOR. This helps to detect rotation encoded 5383 using those methods and possibly other simplifications. */ 5384 5385 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5386 && (nonzero_bits (op0, mode) 5387 & nonzero_bits (op1, mode)) == 0) 5388 return (gen_binary (IOR, mode, op0, op1)); 5389 5390 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y). 5391 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for 5392 (NOT y). */ 5393 { 5394 int num_negated = 0; 5395 5396 if (GET_CODE (op0) == NOT) 5397 num_negated++, op0 = XEXP (op0, 0); 5398 if (GET_CODE (op1) == NOT) 5399 num_negated++, op1 = XEXP (op1, 0); 5400 5401 if (num_negated == 2) 5402 { 5403 SUBST (XEXP (x, 0), op0); 5404 SUBST (XEXP (x, 1), op1); 5405 } 5406 else if (num_negated == 1) 5407 return 5408 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1), 5409 mode); 5410 } 5411 5412 /* Convert (xor (and A B) B) to (and (not A) B). The latter may 5413 correspond to a machine insn or result in further simplifications 5414 if B is a constant. */ 5415 5416 if (GET_CODE (op0) == AND 5417 && rtx_equal_p (XEXP (op0, 1), op1) 5418 && ! side_effects_p (op1)) 5419 return gen_binary (AND, mode, 5420 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode), 5421 op1); 5422 5423 else if (GET_CODE (op0) == AND 5424 && rtx_equal_p (XEXP (op0, 0), op1) 5425 && ! side_effects_p (op1)) 5426 return gen_binary (AND, mode, 5427 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode), 5428 op1); 5429 5430 /* (xor (comparison foo bar) (const_int 1)) can become the reversed 5431 comparison if STORE_FLAG_VALUE is 1. */ 5432 if (STORE_FLAG_VALUE == 1 5433 && op1 == const1_rtx 5434 && GET_RTX_CLASS (GET_CODE (op0)) == '<' 5435 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0), 5436 XEXP (op0, 1)))) 5437 return reversed; 5438 5439 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1 5440 is (lt foo (const_int 0)), so we can perform the above 5441 simplification if STORE_FLAG_VALUE is 1. */ 5442 5443 if (STORE_FLAG_VALUE == 1 5444 && op1 == const1_rtx 5445 && GET_CODE (op0) == LSHIFTRT 5446 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5447 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1) 5448 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx); 5449 5450 /* (xor (comparison foo bar) (const_int sign-bit)) 5451 when STORE_FLAG_VALUE is the sign bit. */ 5452 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5453 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) 5454 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) 5455 && op1 == const_true_rtx 5456 && GET_RTX_CLASS (GET_CODE (op0)) == '<' 5457 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0), 5458 XEXP (op0, 1)))) 5459 return reversed; 5460 5461 break; 5462 5463 default: 5464 abort (); 5465 } 5466 5467 return x; 5468} 5469 5470/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound 5471 operations" because they can be replaced with two more basic operations. 5472 ZERO_EXTEND is also considered "compound" because it can be replaced with 5473 an AND operation, which is simpler, though only one operation. 5474 5475 The function expand_compound_operation is called with an rtx expression 5476 and will convert it to the appropriate shifts and AND operations, 5477 simplifying at each stage. 5478 5479 The function make_compound_operation is called to convert an expression 5480 consisting of shifts and ANDs into the equivalent compound expression. 5481 It is the inverse of this function, loosely speaking. */ 5482 5483static rtx 5484expand_compound_operation (x) 5485 rtx x; 5486{ 5487 unsigned HOST_WIDE_INT pos = 0, len; 5488 int unsignedp = 0; 5489 unsigned int modewidth; 5490 rtx tem; 5491 5492 switch (GET_CODE (x)) 5493 { 5494 case ZERO_EXTEND: 5495 unsignedp = 1; 5496 case SIGN_EXTEND: 5497 /* We can't necessarily use a const_int for a multiword mode; 5498 it depends on implicitly extending the value. 5499 Since we don't know the right way to extend it, 5500 we can't tell whether the implicit way is right. 5501 5502 Even for a mode that is no wider than a const_int, 5503 we can't win, because we need to sign extend one of its bits through 5504 the rest of it, and we don't know which bit. */ 5505 if (GET_CODE (XEXP (x, 0)) == CONST_INT) 5506 return x; 5507 5508 /* Return if (subreg:MODE FROM 0) is not a safe replacement for 5509 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM 5510 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be 5511 reloaded. If not for that, MEM's would very rarely be safe. 5512 5513 Reject MODEs bigger than a word, because we might not be able 5514 to reference a two-register group starting with an arbitrary register 5515 (and currently gen_lowpart might crash for a SUBREG). */ 5516 5517 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) 5518 return x; 5519 5520 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))); 5521 /* If the inner object has VOIDmode (the only way this can happen 5522 is if it is a ASM_OPERANDS), we can't do anything since we don't 5523 know how much masking to do. */ 5524 if (len == 0) 5525 return x; 5526 5527 break; 5528 5529 case ZERO_EXTRACT: 5530 unsignedp = 1; 5531 case SIGN_EXTRACT: 5532 /* If the operand is a CLOBBER, just return it. */ 5533 if (GET_CODE (XEXP (x, 0)) == CLOBBER) 5534 return XEXP (x, 0); 5535 5536 if (GET_CODE (XEXP (x, 1)) != CONST_INT 5537 || GET_CODE (XEXP (x, 2)) != CONST_INT 5538 || GET_MODE (XEXP (x, 0)) == VOIDmode) 5539 return x; 5540 5541 len = INTVAL (XEXP (x, 1)); 5542 pos = INTVAL (XEXP (x, 2)); 5543 5544 /* If this goes outside the object being extracted, replace the object 5545 with a (use (mem ...)) construct that only combine understands 5546 and is used only for this purpose. */ 5547 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) 5548 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0))); 5549 5550 if (BITS_BIG_ENDIAN) 5551 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos; 5552 5553 break; 5554 5555 default: 5556 return x; 5557 } 5558 /* Convert sign extension to zero extension, if we know that the high 5559 bit is not set, as this is easier to optimize. It will be converted 5560 back to cheaper alternative in make_extraction. */ 5561 if (GET_CODE (x) == SIGN_EXTEND 5562 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5563 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 5564 & ~(((unsigned HOST_WIDE_INT) 5565 GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) 5566 >> 1)) 5567 == 0))) 5568 { 5569 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0)); 5570 return expand_compound_operation (temp); 5571 } 5572 5573 /* We can optimize some special cases of ZERO_EXTEND. */ 5574 if (GET_CODE (x) == ZERO_EXTEND) 5575 { 5576 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we 5577 know that the last value didn't have any inappropriate bits 5578 set. */ 5579 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 5580 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 5581 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5582 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x)) 5583 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5584 return XEXP (XEXP (x, 0), 0); 5585 5586 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 5587 if (GET_CODE (XEXP (x, 0)) == SUBREG 5588 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 5589 && subreg_lowpart_p (XEXP (x, 0)) 5590 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5591 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x)) 5592 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5593 return SUBREG_REG (XEXP (x, 0)); 5594 5595 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo 5596 is a comparison and STORE_FLAG_VALUE permits. This is like 5597 the first case, but it works even when GET_MODE (x) is larger 5598 than HOST_WIDE_INT. */ 5599 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 5600 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 5601 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<' 5602 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 5603 <= HOST_BITS_PER_WIDE_INT) 5604 && ((HOST_WIDE_INT) STORE_FLAG_VALUE 5605 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5606 return XEXP (XEXP (x, 0), 0); 5607 5608 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 5609 if (GET_CODE (XEXP (x, 0)) == SUBREG 5610 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 5611 && subreg_lowpart_p (XEXP (x, 0)) 5612 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<' 5613 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 5614 <= HOST_BITS_PER_WIDE_INT) 5615 && ((HOST_WIDE_INT) STORE_FLAG_VALUE 5616 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5617 return SUBREG_REG (XEXP (x, 0)); 5618 5619 } 5620 5621 /* If we reach here, we want to return a pair of shifts. The inner 5622 shift is a left shift of BITSIZE - POS - LEN bits. The outer 5623 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or 5624 logical depending on the value of UNSIGNEDP. 5625 5626 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be 5627 converted into an AND of a shift. 5628 5629 We must check for the case where the left shift would have a negative 5630 count. This can happen in a case like (x >> 31) & 255 on machines 5631 that can't shift by a constant. On those machines, we would first 5632 combine the shift with the AND to produce a variable-position 5633 extraction. Then the constant of 31 would be substituted in to produce 5634 a such a position. */ 5635 5636 modewidth = GET_MODE_BITSIZE (GET_MODE (x)); 5637 if (modewidth + len >= pos) 5638 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, 5639 GET_MODE (x), 5640 simplify_shift_const (NULL_RTX, ASHIFT, 5641 GET_MODE (x), 5642 XEXP (x, 0), 5643 modewidth - pos - len), 5644 modewidth - len); 5645 5646 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) 5647 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), 5648 simplify_shift_const (NULL_RTX, LSHIFTRT, 5649 GET_MODE (x), 5650 XEXP (x, 0), pos), 5651 ((HOST_WIDE_INT) 1 << len) - 1); 5652 else 5653 /* Any other cases we can't handle. */ 5654 return x; 5655 5656 /* If we couldn't do this for some reason, return the original 5657 expression. */ 5658 if (GET_CODE (tem) == CLOBBER) 5659 return x; 5660 5661 return tem; 5662} 5663 5664/* X is a SET which contains an assignment of one object into 5665 a part of another (such as a bit-field assignment, STRICT_LOW_PART, 5666 or certain SUBREGS). If possible, convert it into a series of 5667 logical operations. 5668 5669 We half-heartedly support variable positions, but do not at all 5670 support variable lengths. */ 5671 5672static rtx 5673expand_field_assignment (x) 5674 rtx x; 5675{ 5676 rtx inner; 5677 rtx pos; /* Always counts from low bit. */ 5678 int len; 5679 rtx mask; 5680 enum machine_mode compute_mode; 5681 5682 /* Loop until we find something we can't simplify. */ 5683 while (1) 5684 { 5685 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART 5686 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) 5687 { 5688 inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); 5689 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))); 5690 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0))); 5691 } 5692 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 5693 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT) 5694 { 5695 inner = XEXP (SET_DEST (x), 0); 5696 len = INTVAL (XEXP (SET_DEST (x), 1)); 5697 pos = XEXP (SET_DEST (x), 2); 5698 5699 /* If the position is constant and spans the width of INNER, 5700 surround INNER with a USE to indicate this. */ 5701 if (GET_CODE (pos) == CONST_INT 5702 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner))) 5703 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner); 5704 5705 if (BITS_BIG_ENDIAN) 5706 { 5707 if (GET_CODE (pos) == CONST_INT) 5708 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len 5709 - INTVAL (pos)); 5710 else if (GET_CODE (pos) == MINUS 5711 && GET_CODE (XEXP (pos, 1)) == CONST_INT 5712 && (INTVAL (XEXP (pos, 1)) 5713 == GET_MODE_BITSIZE (GET_MODE (inner)) - len)) 5714 /* If position is ADJUST - X, new position is X. */ 5715 pos = XEXP (pos, 0); 5716 else 5717 pos = gen_binary (MINUS, GET_MODE (pos), 5718 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) 5719 - len), 5720 pos); 5721 } 5722 } 5723 5724 /* A SUBREG between two modes that occupy the same numbers of words 5725 can be done by moving the SUBREG to the source. */ 5726 else if (GET_CODE (SET_DEST (x)) == SUBREG 5727 /* We need SUBREGs to compute nonzero_bits properly. */ 5728 && nonzero_sign_valid 5729 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) 5730 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 5731 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) 5732 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) 5733 { 5734 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)), 5735 gen_lowpart_for_combine 5736 (GET_MODE (SUBREG_REG (SET_DEST (x))), 5737 SET_SRC (x))); 5738 continue; 5739 } 5740 else 5741 break; 5742 5743 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 5744 inner = SUBREG_REG (inner); 5745 5746 compute_mode = GET_MODE (inner); 5747 5748 /* Don't attempt bitwise arithmetic on non-integral modes. */ 5749 if (! INTEGRAL_MODE_P (compute_mode)) 5750 { 5751 enum machine_mode imode; 5752 5753 /* Something is probably seriously wrong if this matches. */ 5754 if (! FLOAT_MODE_P (compute_mode)) 5755 break; 5756 5757 /* Try to find an integral mode to pun with. */ 5758 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0); 5759 if (imode == BLKmode) 5760 break; 5761 5762 compute_mode = imode; 5763 inner = gen_lowpart_for_combine (imode, inner); 5764 } 5765 5766 /* Compute a mask of LEN bits, if we can do this on the host machine. */ 5767 if (len < HOST_BITS_PER_WIDE_INT) 5768 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1); 5769 else 5770 break; 5771 5772 /* Now compute the equivalent expression. Make a copy of INNER 5773 for the SET_DEST in case it is a MEM into which we will substitute; 5774 we don't want shared RTL in that case. */ 5775 x = gen_rtx_SET 5776 (VOIDmode, copy_rtx (inner), 5777 gen_binary (IOR, compute_mode, 5778 gen_binary (AND, compute_mode, 5779 simplify_gen_unary (NOT, compute_mode, 5780 gen_binary (ASHIFT, 5781 compute_mode, 5782 mask, pos), 5783 compute_mode), 5784 inner), 5785 gen_binary (ASHIFT, compute_mode, 5786 gen_binary (AND, compute_mode, 5787 gen_lowpart_for_combine 5788 (compute_mode, SET_SRC (x)), 5789 mask), 5790 pos))); 5791 } 5792 5793 return x; 5794} 5795 5796/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, 5797 it is an RTX that represents a variable starting position; otherwise, 5798 POS is the (constant) starting bit position (counted from the LSB). 5799 5800 INNER may be a USE. This will occur when we started with a bitfield 5801 that went outside the boundary of the object in memory, which is 5802 allowed on most machines. To isolate this case, we produce a USE 5803 whose mode is wide enough and surround the MEM with it. The only 5804 code that understands the USE is this routine. If it is not removed, 5805 it will cause the resulting insn not to match. 5806 5807 UNSIGNEDP is non-zero for an unsigned reference and zero for a 5808 signed reference. 5809 5810 IN_DEST is non-zero if this is a reference in the destination of a 5811 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero, 5812 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will 5813 be used. 5814 5815 IN_COMPARE is non-zero if we are in a COMPARE. This means that a 5816 ZERO_EXTRACT should be built even for bits starting at bit 0. 5817 5818 MODE is the desired mode of the result (if IN_DEST == 0). 5819 5820 The result is an RTX for the extraction or NULL_RTX if the target 5821 can't handle it. */ 5822 5823static rtx 5824make_extraction (mode, inner, pos, pos_rtx, len, 5825 unsignedp, in_dest, in_compare) 5826 enum machine_mode mode; 5827 rtx inner; 5828 HOST_WIDE_INT pos; 5829 rtx pos_rtx; 5830 unsigned HOST_WIDE_INT len; 5831 int unsignedp; 5832 int in_dest, in_compare; 5833{ 5834 /* This mode describes the size of the storage area 5835 to fetch the overall value from. Within that, we 5836 ignore the POS lowest bits, etc. */ 5837 enum machine_mode is_mode = GET_MODE (inner); 5838 enum machine_mode inner_mode; 5839 enum machine_mode wanted_inner_mode = byte_mode; 5840 enum machine_mode wanted_inner_reg_mode = word_mode; 5841 enum machine_mode pos_mode = word_mode; 5842 enum machine_mode extraction_mode = word_mode; 5843 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); 5844 int spans_byte = 0; 5845 rtx new = 0; 5846 rtx orig_pos_rtx = pos_rtx; 5847 HOST_WIDE_INT orig_pos; 5848 5849 /* Get some information about INNER and get the innermost object. */ 5850 if (GET_CODE (inner) == USE) 5851 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */ 5852 /* We don't need to adjust the position because we set up the USE 5853 to pretend that it was a full-word object. */ 5854 spans_byte = 1, inner = XEXP (inner, 0); 5855 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 5856 { 5857 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), 5858 consider just the QI as the memory to extract from. 5859 The subreg adds or removes high bits; its mode is 5860 irrelevant to the meaning of this extraction, 5861 since POS and LEN count from the lsb. */ 5862 if (GET_CODE (SUBREG_REG (inner)) == MEM) 5863 is_mode = GET_MODE (SUBREG_REG (inner)); 5864 inner = SUBREG_REG (inner); 5865 } 5866 5867 inner_mode = GET_MODE (inner); 5868 5869 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT) 5870 pos = INTVAL (pos_rtx), pos_rtx = 0; 5871 5872 /* See if this can be done without an extraction. We never can if the 5873 width of the field is not the same as that of some integer mode. For 5874 registers, we can only avoid the extraction if the position is at the 5875 low-order bit and this is either not in the destination or we have the 5876 appropriate STRICT_LOW_PART operation available. 5877 5878 For MEM, we can avoid an extract if the field starts on an appropriate 5879 boundary and we can change the mode of the memory reference. However, 5880 we cannot directly access the MEM if we have a USE and the underlying 5881 MEM is not TMODE. This combination means that MEM was being used in a 5882 context where bits outside its mode were being referenced; that is only 5883 valid in bit-field insns. */ 5884 5885 if (tmode != BLKmode 5886 && ! (spans_byte && inner_mode != tmode) 5887 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 5888 && GET_CODE (inner) != MEM 5889 && (! in_dest 5890 || (GET_CODE (inner) == REG 5891 && have_insn_for (STRICT_LOW_PART, tmode)))) 5892 || (GET_CODE (inner) == MEM && pos_rtx == 0 5893 && (pos 5894 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) 5895 : BITS_PER_UNIT)) == 0 5896 /* We can't do this if we are widening INNER_MODE (it 5897 may not be aligned, for one thing). */ 5898 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode) 5899 && (inner_mode == tmode 5900 || (! mode_dependent_address_p (XEXP (inner, 0)) 5901 && ! MEM_VOLATILE_P (inner)))))) 5902 { 5903 /* If INNER is a MEM, make a new MEM that encompasses just the desired 5904 field. If the original and current mode are the same, we need not 5905 adjust the offset. Otherwise, we do if bytes big endian. 5906 5907 If INNER is not a MEM, get a piece consisting of just the field 5908 of interest (in this case POS % BITS_PER_WORD must be 0). */ 5909 5910 if (GET_CODE (inner) == MEM) 5911 { 5912 HOST_WIDE_INT offset; 5913 5914 /* POS counts from lsb, but make OFFSET count in memory order. */ 5915 if (BYTES_BIG_ENDIAN) 5916 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT; 5917 else 5918 offset = pos / BITS_PER_UNIT; 5919 5920 new = adjust_address_nv (inner, tmode, offset); 5921 } 5922 else if (GET_CODE (inner) == REG) 5923 { 5924 /* We can't call gen_lowpart_for_combine here since we always want 5925 a SUBREG and it would sometimes return a new hard register. */ 5926 if (tmode != inner_mode) 5927 { 5928 HOST_WIDE_INT final_word = pos / BITS_PER_WORD; 5929 5930 if (WORDS_BIG_ENDIAN 5931 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD) 5932 final_word = ((GET_MODE_SIZE (inner_mode) 5933 - GET_MODE_SIZE (tmode)) 5934 / UNITS_PER_WORD) - final_word; 5935 5936 final_word *= UNITS_PER_WORD; 5937 if (BYTES_BIG_ENDIAN && 5938 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode)) 5939 final_word += (GET_MODE_SIZE (inner_mode) 5940 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD; 5941 5942 new = gen_rtx_SUBREG (tmode, inner, final_word); 5943 } 5944 else 5945 new = inner; 5946 } 5947 else 5948 new = force_to_mode (inner, tmode, 5949 len >= HOST_BITS_PER_WIDE_INT 5950 ? ~(unsigned HOST_WIDE_INT) 0 5951 : ((unsigned HOST_WIDE_INT) 1 << len) - 1, 5952 NULL_RTX, 0); 5953 5954 /* If this extraction is going into the destination of a SET, 5955 make a STRICT_LOW_PART unless we made a MEM. */ 5956 5957 if (in_dest) 5958 return (GET_CODE (new) == MEM ? new 5959 : (GET_CODE (new) != SUBREG 5960 ? gen_rtx_CLOBBER (tmode, const0_rtx) 5961 : gen_rtx_STRICT_LOW_PART (VOIDmode, new))); 5962 5963 if (mode == tmode) 5964 return new; 5965 5966 /* If we know that no extraneous bits are set, and that the high 5967 bit is not set, convert the extraction to the cheaper of 5968 sign and zero extension, that are equivalent in these cases. */ 5969 if (flag_expensive_optimizations 5970 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT 5971 && ((nonzero_bits (new, tmode) 5972 & ~(((unsigned HOST_WIDE_INT) 5973 GET_MODE_MASK (tmode)) 5974 >> 1)) 5975 == 0))) 5976 { 5977 rtx temp = gen_rtx_ZERO_EXTEND (mode, new); 5978 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new); 5979 5980 /* Prefer ZERO_EXTENSION, since it gives more information to 5981 backends. */ 5982 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET)) 5983 return temp; 5984 return temp1; 5985 } 5986 5987 /* Otherwise, sign- or zero-extend unless we already are in the 5988 proper mode. */ 5989 5990 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 5991 mode, new)); 5992 } 5993 5994 /* Unless this is a COMPARE or we have a funny memory reference, 5995 don't do anything with zero-extending field extracts starting at 5996 the low-order bit since they are simple AND operations. */ 5997 if (pos_rtx == 0 && pos == 0 && ! in_dest 5998 && ! in_compare && ! spans_byte && unsignedp) 5999 return 0; 6000 6001 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if 6002 we would be spanning bytes or if the position is not a constant and the 6003 length is not 1. In all other cases, we would only be going outside 6004 our object in cases when an original shift would have been 6005 undefined. */ 6006 if (! spans_byte && GET_CODE (inner) == MEM 6007 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode)) 6008 || (pos_rtx != 0 && len != 1))) 6009 return 0; 6010 6011 /* Get the mode to use should INNER not be a MEM, the mode for the position, 6012 and the mode for the result. */ 6013 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE) 6014 { 6015 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0); 6016 pos_mode = mode_for_extraction (EP_insv, 2); 6017 extraction_mode = mode_for_extraction (EP_insv, 3); 6018 } 6019 6020 if (! in_dest && unsignedp 6021 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE) 6022 { 6023 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1); 6024 pos_mode = mode_for_extraction (EP_extzv, 3); 6025 extraction_mode = mode_for_extraction (EP_extzv, 0); 6026 } 6027 6028 if (! in_dest && ! unsignedp 6029 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE) 6030 { 6031 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1); 6032 pos_mode = mode_for_extraction (EP_extv, 3); 6033 extraction_mode = mode_for_extraction (EP_extv, 0); 6034 } 6035 6036 /* Never narrow an object, since that might not be safe. */ 6037 6038 if (mode != VOIDmode 6039 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) 6040 extraction_mode = mode; 6041 6042 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode 6043 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) 6044 pos_mode = GET_MODE (pos_rtx); 6045 6046 /* If this is not from memory, the desired mode is wanted_inner_reg_mode; 6047 if we have to change the mode of memory and cannot, the desired mode is 6048 EXTRACTION_MODE. */ 6049 if (GET_CODE (inner) != MEM) 6050 wanted_inner_mode = wanted_inner_reg_mode; 6051 else if (inner_mode != wanted_inner_mode 6052 && (mode_dependent_address_p (XEXP (inner, 0)) 6053 || MEM_VOLATILE_P (inner))) 6054 wanted_inner_mode = extraction_mode; 6055 6056 orig_pos = pos; 6057 6058 if (BITS_BIG_ENDIAN) 6059 { 6060 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to 6061 BITS_BIG_ENDIAN style. If position is constant, compute new 6062 position. Otherwise, build subtraction. 6063 Note that POS is relative to the mode of the original argument. 6064 If it's a MEM we need to recompute POS relative to that. 6065 However, if we're extracting from (or inserting into) a register, 6066 we want to recompute POS relative to wanted_inner_mode. */ 6067 int width = (GET_CODE (inner) == MEM 6068 ? GET_MODE_BITSIZE (is_mode) 6069 : GET_MODE_BITSIZE (wanted_inner_mode)); 6070 6071 if (pos_rtx == 0) 6072 pos = width - len - pos; 6073 else 6074 pos_rtx 6075 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx); 6076 /* POS may be less than 0 now, but we check for that below. 6077 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */ 6078 } 6079 6080 /* If INNER has a wider mode, make it smaller. If this is a constant 6081 extract, try to adjust the byte to point to the byte containing 6082 the value. */ 6083 if (wanted_inner_mode != VOIDmode 6084 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode) 6085 && ((GET_CODE (inner) == MEM 6086 && (inner_mode == wanted_inner_mode 6087 || (! mode_dependent_address_p (XEXP (inner, 0)) 6088 && ! MEM_VOLATILE_P (inner)))))) 6089 { 6090 int offset = 0; 6091 6092 /* The computations below will be correct if the machine is big 6093 endian in both bits and bytes or little endian in bits and bytes. 6094 If it is mixed, we must adjust. */ 6095 6096 /* If bytes are big endian and we had a paradoxical SUBREG, we must 6097 adjust OFFSET to compensate. */ 6098 if (BYTES_BIG_ENDIAN 6099 && ! spans_byte 6100 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) 6101 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); 6102 6103 /* If this is a constant position, we can move to the desired byte. */ 6104 if (pos_rtx == 0) 6105 { 6106 offset += pos / BITS_PER_UNIT; 6107 pos %= GET_MODE_BITSIZE (wanted_inner_mode); 6108 } 6109 6110 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN 6111 && ! spans_byte 6112 && is_mode != wanted_inner_mode) 6113 offset = (GET_MODE_SIZE (is_mode) 6114 - GET_MODE_SIZE (wanted_inner_mode) - offset); 6115 6116 if (offset != 0 || inner_mode != wanted_inner_mode) 6117 inner = adjust_address_nv (inner, wanted_inner_mode, offset); 6118 } 6119 6120 /* If INNER is not memory, we can always get it into the proper mode. If we 6121 are changing its mode, POS must be a constant and smaller than the size 6122 of the new mode. */ 6123 else if (GET_CODE (inner) != MEM) 6124 { 6125 if (GET_MODE (inner) != wanted_inner_mode 6126 && (pos_rtx != 0 6127 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) 6128 return 0; 6129 6130 inner = force_to_mode (inner, wanted_inner_mode, 6131 pos_rtx 6132 || len + orig_pos >= HOST_BITS_PER_WIDE_INT 6133 ? ~(unsigned HOST_WIDE_INT) 0 6134 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1) 6135 << orig_pos), 6136 NULL_RTX, 0); 6137 } 6138 6139 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we 6140 have to zero extend. Otherwise, we can just use a SUBREG. */ 6141 if (pos_rtx != 0 6142 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) 6143 { 6144 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx); 6145 6146 /* If we know that no extraneous bits are set, and that the high 6147 bit is not set, convert extraction to cheaper one - either 6148 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these 6149 cases. */ 6150 if (flag_expensive_optimizations 6151 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT 6152 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx)) 6153 & ~(((unsigned HOST_WIDE_INT) 6154 GET_MODE_MASK (GET_MODE (pos_rtx))) 6155 >> 1)) 6156 == 0))) 6157 { 6158 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx); 6159 6160 /* Prefer ZERO_EXTENSION, since it gives more information to 6161 backends. */ 6162 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET)) 6163 temp = temp1; 6164 } 6165 pos_rtx = temp; 6166 } 6167 else if (pos_rtx != 0 6168 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) 6169 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx); 6170 6171 /* Make POS_RTX unless we already have it and it is correct. If we don't 6172 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must 6173 be a CONST_INT. */ 6174 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) 6175 pos_rtx = orig_pos_rtx; 6176 6177 else if (pos_rtx == 0) 6178 pos_rtx = GEN_INT (pos); 6179 6180 /* Make the required operation. See if we can use existing rtx. */ 6181 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, 6182 extraction_mode, inner, GEN_INT (len), pos_rtx); 6183 if (! in_dest) 6184 new = gen_lowpart_for_combine (mode, new); 6185 6186 return new; 6187} 6188 6189/* See if X contains an ASHIFT of COUNT or more bits that can be commuted 6190 with any other operations in X. Return X without that shift if so. */ 6191 6192static rtx 6193extract_left_shift (x, count) 6194 rtx x; 6195 int count; 6196{ 6197 enum rtx_code code = GET_CODE (x); 6198 enum machine_mode mode = GET_MODE (x); 6199 rtx tem; 6200 6201 switch (code) 6202 { 6203 case ASHIFT: 6204 /* This is the shift itself. If it is wide enough, we will return 6205 either the value being shifted if the shift count is equal to 6206 COUNT or a shift for the difference. */ 6207 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6208 && INTVAL (XEXP (x, 1)) >= count) 6209 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), 6210 INTVAL (XEXP (x, 1)) - count); 6211 break; 6212 6213 case NEG: case NOT: 6214 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) 6215 return simplify_gen_unary (code, mode, tem, mode); 6216 6217 break; 6218 6219 case PLUS: case IOR: case XOR: case AND: 6220 /* If we can safely shift this constant and we find the inner shift, 6221 make a new operation. */ 6222 if (GET_CODE (XEXP (x,1)) == CONST_INT 6223 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0 6224 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) 6225 return gen_binary (code, mode, tem, 6226 GEN_INT (INTVAL (XEXP (x, 1)) >> count)); 6227 6228 break; 6229 6230 default: 6231 break; 6232 } 6233 6234 return 0; 6235} 6236 6237/* Look at the expression rooted at X. Look for expressions 6238 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. 6239 Form these expressions. 6240 6241 Return the new rtx, usually just X. 6242 6243 Also, for machines like the VAX that don't have logical shift insns, 6244 try to convert logical to arithmetic shift operations in cases where 6245 they are equivalent. This undoes the canonicalizations to logical 6246 shifts done elsewhere. 6247 6248 We try, as much as possible, to re-use rtl expressions to save memory. 6249 6250 IN_CODE says what kind of expression we are processing. Normally, it is 6251 SET. In a memory address (inside a MEM, PLUS or minus, the latter two 6252 being kludges), it is MEM. When processing the arguments of a comparison 6253 or a COMPARE against zero, it is COMPARE. */ 6254 6255static rtx 6256make_compound_operation (x, in_code) 6257 rtx x; 6258 enum rtx_code in_code; 6259{ 6260 enum rtx_code code = GET_CODE (x); 6261 enum machine_mode mode = GET_MODE (x); 6262 int mode_width = GET_MODE_BITSIZE (mode); 6263 rtx rhs, lhs; 6264 enum rtx_code next_code; 6265 int i; 6266 rtx new = 0; 6267 rtx tem; 6268 const char *fmt; 6269 6270 /* Select the code to be used in recursive calls. Once we are inside an 6271 address, we stay there. If we have a comparison, set to COMPARE, 6272 but once inside, go back to our default of SET. */ 6273 6274 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM 6275 : ((code == COMPARE || GET_RTX_CLASS (code) == '<') 6276 && XEXP (x, 1) == const0_rtx) ? COMPARE 6277 : in_code == COMPARE ? SET : in_code); 6278 6279 /* Process depending on the code of this operation. If NEW is set 6280 non-zero, it will be returned. */ 6281 6282 switch (code) 6283 { 6284 case ASHIFT: 6285 /* Convert shifts by constants into multiplications if inside 6286 an address. */ 6287 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT 6288 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 6289 && INTVAL (XEXP (x, 1)) >= 0) 6290 { 6291 new = make_compound_operation (XEXP (x, 0), next_code); 6292 new = gen_rtx_MULT (mode, new, 6293 GEN_INT ((HOST_WIDE_INT) 1 6294 << INTVAL (XEXP (x, 1)))); 6295 } 6296 break; 6297 6298 case AND: 6299 /* If the second operand is not a constant, we can't do anything 6300 with it. */ 6301 if (GET_CODE (XEXP (x, 1)) != CONST_INT) 6302 break; 6303 6304 /* If the constant is a power of two minus one and the first operand 6305 is a logical right shift, make an extraction. */ 6306 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6307 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6308 { 6309 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 6310 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1, 6311 0, in_code == COMPARE); 6312 } 6313 6314 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ 6315 else if (GET_CODE (XEXP (x, 0)) == SUBREG 6316 && subreg_lowpart_p (XEXP (x, 0)) 6317 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT 6318 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6319 { 6320 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), 6321 next_code); 6322 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0, 6323 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, 6324 0, in_code == COMPARE); 6325 } 6326 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ 6327 else if ((GET_CODE (XEXP (x, 0)) == XOR 6328 || GET_CODE (XEXP (x, 0)) == IOR) 6329 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT 6330 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT 6331 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6332 { 6333 /* Apply the distributive law, and then try to make extractions. */ 6334 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode, 6335 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), 6336 XEXP (x, 1)), 6337 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), 6338 XEXP (x, 1))); 6339 new = make_compound_operation (new, in_code); 6340 } 6341 6342 /* If we are have (and (rotate X C) M) and C is larger than the number 6343 of bits in M, this is an extraction. */ 6344 6345 else if (GET_CODE (XEXP (x, 0)) == ROTATE 6346 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6347 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 6348 && i <= INTVAL (XEXP (XEXP (x, 0), 1))) 6349 { 6350 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 6351 new = make_extraction (mode, new, 6352 (GET_MODE_BITSIZE (mode) 6353 - INTVAL (XEXP (XEXP (x, 0), 1))), 6354 NULL_RTX, i, 1, 0, in_code == COMPARE); 6355 } 6356 6357 /* On machines without logical shifts, if the operand of the AND is 6358 a logical shift and our mask turns off all the propagated sign 6359 bits, we can replace the logical shift with an arithmetic shift. */ 6360 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6361 && !have_insn_for (LSHIFTRT, mode) 6362 && have_insn_for (ASHIFTRT, mode) 6363 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6364 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 6365 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 6366 && mode_width <= HOST_BITS_PER_WIDE_INT) 6367 { 6368 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 6369 6370 mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); 6371 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) 6372 SUBST (XEXP (x, 0), 6373 gen_rtx_ASHIFTRT (mode, 6374 make_compound_operation 6375 (XEXP (XEXP (x, 0), 0), next_code), 6376 XEXP (XEXP (x, 0), 1))); 6377 } 6378 6379 /* If the constant is one less than a power of two, this might be 6380 representable by an extraction even if no shift is present. 6381 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless 6382 we are in a COMPARE. */ 6383 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6384 new = make_extraction (mode, 6385 make_compound_operation (XEXP (x, 0), 6386 next_code), 6387 0, NULL_RTX, i, 1, 0, in_code == COMPARE); 6388 6389 /* If we are in a comparison and this is an AND with a power of two, 6390 convert this into the appropriate bit extract. */ 6391 else if (in_code == COMPARE 6392 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) 6393 new = make_extraction (mode, 6394 make_compound_operation (XEXP (x, 0), 6395 next_code), 6396 i, NULL_RTX, 1, 1, 0, 1); 6397 6398 break; 6399 6400 case LSHIFTRT: 6401 /* If the sign bit is known to be zero, replace this with an 6402 arithmetic shift. */ 6403 if (have_insn_for (ASHIFTRT, mode) 6404 && ! have_insn_for (LSHIFTRT, mode) 6405 && mode_width <= HOST_BITS_PER_WIDE_INT 6406 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) 6407 { 6408 new = gen_rtx_ASHIFTRT (mode, 6409 make_compound_operation (XEXP (x, 0), 6410 next_code), 6411 XEXP (x, 1)); 6412 break; 6413 } 6414 6415 /* ... fall through ... */ 6416 6417 case ASHIFTRT: 6418 lhs = XEXP (x, 0); 6419 rhs = XEXP (x, 1); 6420 6421 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, 6422 this is a SIGN_EXTRACT. */ 6423 if (GET_CODE (rhs) == CONST_INT 6424 && GET_CODE (lhs) == ASHIFT 6425 && GET_CODE (XEXP (lhs, 1)) == CONST_INT 6426 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))) 6427 { 6428 new = make_compound_operation (XEXP (lhs, 0), next_code); 6429 new = make_extraction (mode, new, 6430 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), 6431 NULL_RTX, mode_width - INTVAL (rhs), 6432 code == LSHIFTRT, 0, in_code == COMPARE); 6433 break; 6434 } 6435 6436 /* See if we have operations between an ASHIFTRT and an ASHIFT. 6437 If so, try to merge the shifts into a SIGN_EXTEND. We could 6438 also do this for some cases of SIGN_EXTRACT, but it doesn't 6439 seem worth the effort; the case checked for occurs on Alpha. */ 6440 6441 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o' 6442 && ! (GET_CODE (lhs) == SUBREG 6443 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o')) 6444 && GET_CODE (rhs) == CONST_INT 6445 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT 6446 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0) 6447 new = make_extraction (mode, make_compound_operation (new, next_code), 6448 0, NULL_RTX, mode_width - INTVAL (rhs), 6449 code == LSHIFTRT, 0, in_code == COMPARE); 6450 6451 break; 6452 6453 case SUBREG: 6454 /* Call ourselves recursively on the inner expression. If we are 6455 narrowing the object and it has a different RTL code from 6456 what it originally did, do this SUBREG as a force_to_mode. */ 6457 6458 tem = make_compound_operation (SUBREG_REG (x), in_code); 6459 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x)) 6460 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem)) 6461 && subreg_lowpart_p (x)) 6462 { 6463 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0, 6464 NULL_RTX, 0); 6465 6466 /* If we have something other than a SUBREG, we might have 6467 done an expansion, so rerun ourselves. */ 6468 if (GET_CODE (newer) != SUBREG) 6469 newer = make_compound_operation (newer, in_code); 6470 6471 return newer; 6472 } 6473 6474 /* If this is a paradoxical subreg, and the new code is a sign or 6475 zero extension, omit the subreg and widen the extension. If it 6476 is a regular subreg, we can still get rid of the subreg by not 6477 widening so much, or in fact removing the extension entirely. */ 6478 if ((GET_CODE (tem) == SIGN_EXTEND 6479 || GET_CODE (tem) == ZERO_EXTEND) 6480 && subreg_lowpart_p (x)) 6481 { 6482 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem)) 6483 || (GET_MODE_SIZE (mode) > 6484 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0))))) 6485 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0)); 6486 else 6487 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0)); 6488 return tem; 6489 } 6490 break; 6491 6492 default: 6493 break; 6494 } 6495 6496 if (new) 6497 { 6498 x = gen_lowpart_for_combine (mode, new); 6499 code = GET_CODE (x); 6500 } 6501 6502 /* Now recursively process each operand of this operation. */ 6503 fmt = GET_RTX_FORMAT (code); 6504 for (i = 0; i < GET_RTX_LENGTH (code); i++) 6505 if (fmt[i] == 'e') 6506 { 6507 new = make_compound_operation (XEXP (x, i), next_code); 6508 SUBST (XEXP (x, i), new); 6509 } 6510 6511 return x; 6512} 6513 6514/* Given M see if it is a value that would select a field of bits 6515 within an item, but not the entire word. Return -1 if not. 6516 Otherwise, return the starting position of the field, where 0 is the 6517 low-order bit. 6518 6519 *PLEN is set to the length of the field. */ 6520 6521static int 6522get_pos_from_mask (m, plen) 6523 unsigned HOST_WIDE_INT m; 6524 unsigned HOST_WIDE_INT *plen; 6525{ 6526 /* Get the bit number of the first 1 bit from the right, -1 if none. */ 6527 int pos = exact_log2 (m & -m); 6528 int len; 6529 6530 if (pos < 0) 6531 return -1; 6532 6533 /* Now shift off the low-order zero bits and see if we have a power of 6534 two minus 1. */ 6535 len = exact_log2 ((m >> pos) + 1); 6536 6537 if (len <= 0) 6538 return -1; 6539 6540 *plen = len; 6541 return pos; 6542} 6543 6544/* See if X can be simplified knowing that we will only refer to it in 6545 MODE and will only refer to those bits that are nonzero in MASK. 6546 If other bits are being computed or if masking operations are done 6547 that select a superset of the bits in MASK, they can sometimes be 6548 ignored. 6549 6550 Return a possibly simplified expression, but always convert X to 6551 MODE. If X is a CONST_INT, AND the CONST_INT with MASK. 6552 6553 Also, if REG is non-zero and X is a register equal in value to REG, 6554 replace X with REG. 6555 6556 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK 6557 are all off in X. This is used when X will be complemented, by either 6558 NOT, NEG, or XOR. */ 6559 6560static rtx 6561force_to_mode (x, mode, mask, reg, just_select) 6562 rtx x; 6563 enum machine_mode mode; 6564 unsigned HOST_WIDE_INT mask; 6565 rtx reg; 6566 int just_select; 6567{ 6568 enum rtx_code code = GET_CODE (x); 6569 int next_select = just_select || code == XOR || code == NOT || code == NEG; 6570 enum machine_mode op_mode; 6571 unsigned HOST_WIDE_INT fuller_mask, nonzero; 6572 rtx op0, op1, temp; 6573 6574 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the 6575 code below will do the wrong thing since the mode of such an 6576 expression is VOIDmode. 6577 6578 Also do nothing if X is a CLOBBER; this can happen if X was 6579 the return value from a call to gen_lowpart_for_combine. */ 6580 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) 6581 return x; 6582 6583 /* We want to perform the operation is its present mode unless we know 6584 that the operation is valid in MODE, in which case we do the operation 6585 in MODE. */ 6586 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) 6587 && have_insn_for (code, mode)) 6588 ? mode : GET_MODE (x)); 6589 6590 /* It is not valid to do a right-shift in a narrower mode 6591 than the one it came in with. */ 6592 if ((code == LSHIFTRT || code == ASHIFTRT) 6593 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x))) 6594 op_mode = GET_MODE (x); 6595 6596 /* Truncate MASK to fit OP_MODE. */ 6597 if (op_mode) 6598 mask &= GET_MODE_MASK (op_mode); 6599 6600 /* When we have an arithmetic operation, or a shift whose count we 6601 do not know, we need to assume that all bit the up to the highest-order 6602 bit in MASK will be needed. This is how we form such a mask. */ 6603 if (op_mode) 6604 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT 6605 ? GET_MODE_MASK (op_mode) 6606 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) 6607 - 1)); 6608 else 6609 fuller_mask = ~(HOST_WIDE_INT) 0; 6610 6611 /* Determine what bits of X are guaranteed to be (non)zero. */ 6612 nonzero = nonzero_bits (x, mode); 6613 6614 /* If none of the bits in X are needed, return a zero. */ 6615 if (! just_select && (nonzero & mask) == 0) 6616 return const0_rtx; 6617 6618 /* If X is a CONST_INT, return a new one. Do this here since the 6619 test below will fail. */ 6620 if (GET_CODE (x) == CONST_INT) 6621 { 6622 HOST_WIDE_INT cval = INTVAL (x) & mask; 6623 int width = GET_MODE_BITSIZE (mode); 6624 6625 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative 6626 number, sign extend it. */ 6627 if (width > 0 && width < HOST_BITS_PER_WIDE_INT 6628 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6629 cval |= (HOST_WIDE_INT) -1 << width; 6630 6631 return GEN_INT (cval); 6632 } 6633 6634 /* If X is narrower than MODE and we want all the bits in X's mode, just 6635 get X in the proper mode. */ 6636 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) 6637 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0) 6638 return gen_lowpart_for_combine (mode, x); 6639 6640 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in 6641 MASK are already known to be zero in X, we need not do anything. */ 6642 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0) 6643 return x; 6644 6645 switch (code) 6646 { 6647 case CLOBBER: 6648 /* If X is a (clobber (const_int)), return it since we know we are 6649 generating something that won't match. */ 6650 return x; 6651 6652 case USE: 6653 /* X is a (use (mem ..)) that was made from a bit-field extraction that 6654 spanned the boundary of the MEM. If we are now masking so it is 6655 within that boundary, we don't need the USE any more. */ 6656 if (! BITS_BIG_ENDIAN 6657 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 6658 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 6659 break; 6660 6661 case SIGN_EXTEND: 6662 case ZERO_EXTEND: 6663 case ZERO_EXTRACT: 6664 case SIGN_EXTRACT: 6665 x = expand_compound_operation (x); 6666 if (GET_CODE (x) != code) 6667 return force_to_mode (x, mode, mask, reg, next_select); 6668 break; 6669 6670 case REG: 6671 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x) 6672 || rtx_equal_p (reg, get_last_value (x)))) 6673 x = reg; 6674 break; 6675 6676 case SUBREG: 6677 if (subreg_lowpart_p (x) 6678 /* We can ignore the effect of this SUBREG if it narrows the mode or 6679 if the constant masks to zero all the bits the mode doesn't 6680 have. */ 6681 && ((GET_MODE_SIZE (GET_MODE (x)) 6682 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 6683 || (0 == (mask 6684 & GET_MODE_MASK (GET_MODE (x)) 6685 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) 6686 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select); 6687 break; 6688 6689 case AND: 6690 /* If this is an AND with a constant, convert it into an AND 6691 whose constant is the AND of that constant with MASK. If it 6692 remains an AND of MASK, delete it since it is redundant. */ 6693 6694 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 6695 { 6696 x = simplify_and_const_int (x, op_mode, XEXP (x, 0), 6697 mask & INTVAL (XEXP (x, 1))); 6698 6699 /* If X is still an AND, see if it is an AND with a mask that 6700 is just some low-order bits. If so, and it is MASK, we don't 6701 need it. */ 6702 6703 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT 6704 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x))) 6705 == (HOST_WIDE_INT) mask)) 6706 x = XEXP (x, 0); 6707 6708 /* If it remains an AND, try making another AND with the bits 6709 in the mode mask that aren't in MASK turned on. If the 6710 constant in the AND is wide enough, this might make a 6711 cheaper constant. */ 6712 6713 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT 6714 && GET_MODE_MASK (GET_MODE (x)) != mask 6715 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) 6716 { 6717 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1)) 6718 | (GET_MODE_MASK (GET_MODE (x)) & ~mask)); 6719 int width = GET_MODE_BITSIZE (GET_MODE (x)); 6720 rtx y; 6721 6722 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative 6723 number, sign extend it. */ 6724 if (width > 0 && width < HOST_BITS_PER_WIDE_INT 6725 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6726 cval |= (HOST_WIDE_INT) -1 << width; 6727 6728 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval)); 6729 if (rtx_cost (y, SET) < rtx_cost (x, SET)) 6730 x = y; 6731 } 6732 6733 break; 6734 } 6735 6736 goto binop; 6737 6738 case PLUS: 6739 /* In (and (plus FOO C1) M), if M is a mask that just turns off 6740 low-order bits (as in an alignment operation) and FOO is already 6741 aligned to that boundary, mask C1 to that boundary as well. 6742 This may eliminate that PLUS and, later, the AND. */ 6743 6744 { 6745 unsigned int width = GET_MODE_BITSIZE (mode); 6746 unsigned HOST_WIDE_INT smask = mask; 6747 6748 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative 6749 number, sign extend it. */ 6750 6751 if (width < HOST_BITS_PER_WIDE_INT 6752 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6753 smask |= (HOST_WIDE_INT) -1 << width; 6754 6755 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6756 && exact_log2 (- smask) >= 0) 6757 { 6758#ifdef STACK_BIAS 6759 if (STACK_BIAS 6760 && (XEXP (x, 0) == stack_pointer_rtx 6761 || XEXP (x, 0) == frame_pointer_rtx)) 6762 { 6763 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; 6764 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode); 6765 6766 sp_mask &= ~(sp_alignment - 1); 6767 if ((sp_mask & ~smask) == 0 6768 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~smask) != 0) 6769 return force_to_mode (plus_constant (XEXP (x, 0), 6770 ((INTVAL (XEXP (x, 1)) - 6771 STACK_BIAS) & smask) 6772 + STACK_BIAS), 6773 mode, smask, reg, next_select); 6774 } 6775#endif 6776 if ((nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0 6777 && (INTVAL (XEXP (x, 1)) & ~smask) != 0) 6778 return force_to_mode (plus_constant (XEXP (x, 0), 6779 (INTVAL (XEXP (x, 1)) 6780 & smask)), 6781 mode, smask, reg, next_select); 6782 } 6783 } 6784 6785 /* ... fall through ... */ 6786 6787 case MULT: 6788 /* For PLUS, MINUS and MULT, we need any bits less significant than the 6789 most significant bit in MASK since carries from those bits will 6790 affect the bits we are interested in. */ 6791 mask = fuller_mask; 6792 goto binop; 6793 6794 case MINUS: 6795 /* If X is (minus C Y) where C's least set bit is larger than any bit 6796 in the mask, then we may replace with (neg Y). */ 6797 if (GET_CODE (XEXP (x, 0)) == CONST_INT 6798 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0)) 6799 & -INTVAL (XEXP (x, 0)))) 6800 > mask)) 6801 { 6802 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1), 6803 GET_MODE (x)); 6804 return force_to_mode (x, mode, mask, reg, next_select); 6805 } 6806 6807 /* Similarly, if C contains every bit in the mask, then we may 6808 replace with (not Y). */ 6809 if (GET_CODE (XEXP (x, 0)) == CONST_INT 6810 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask) 6811 == INTVAL (XEXP (x, 0)))) 6812 { 6813 x = simplify_gen_unary (NOT, GET_MODE (x), 6814 XEXP (x, 1), GET_MODE (x)); 6815 return force_to_mode (x, mode, mask, reg, next_select); 6816 } 6817 6818 mask = fuller_mask; 6819 goto binop; 6820 6821 case IOR: 6822 case XOR: 6823 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and 6824 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) 6825 operation which may be a bitfield extraction. Ensure that the 6826 constant we form is not wider than the mode of X. */ 6827 6828 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6829 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6830 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 6831 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 6832 && GET_CODE (XEXP (x, 1)) == CONST_INT 6833 && ((INTVAL (XEXP (XEXP (x, 0), 1)) 6834 + floor_log2 (INTVAL (XEXP (x, 1)))) 6835 < GET_MODE_BITSIZE (GET_MODE (x))) 6836 && (INTVAL (XEXP (x, 1)) 6837 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0) 6838 { 6839 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask) 6840 << INTVAL (XEXP (XEXP (x, 0), 1))); 6841 temp = gen_binary (GET_CODE (x), GET_MODE (x), 6842 XEXP (XEXP (x, 0), 0), temp); 6843 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, 6844 XEXP (XEXP (x, 0), 1)); 6845 return force_to_mode (x, mode, mask, reg, next_select); 6846 } 6847 6848 binop: 6849 /* For most binary operations, just propagate into the operation and 6850 change the mode if we have an operation of that mode. */ 6851 6852 op0 = gen_lowpart_for_combine (op_mode, 6853 force_to_mode (XEXP (x, 0), mode, mask, 6854 reg, next_select)); 6855 op1 = gen_lowpart_for_combine (op_mode, 6856 force_to_mode (XEXP (x, 1), mode, mask, 6857 reg, next_select)); 6858 6859 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside 6860 MASK since OP1 might have been sign-extended but we never want 6861 to turn on extra bits, since combine might have previously relied 6862 on them being off. */ 6863 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR) 6864 && (INTVAL (op1) & mask) != 0) 6865 op1 = GEN_INT (INTVAL (op1) & mask); 6866 6867 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 6868 x = gen_binary (code, op_mode, op0, op1); 6869 break; 6870 6871 case ASHIFT: 6872 /* For left shifts, do the same, but just for the first operand. 6873 However, we cannot do anything with shifts where we cannot 6874 guarantee that the counts are smaller than the size of the mode 6875 because such a count will have a different meaning in a 6876 wider mode. */ 6877 6878 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT 6879 && INTVAL (XEXP (x, 1)) >= 0 6880 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode)) 6881 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode 6882 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) 6883 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))) 6884 break; 6885 6886 /* If the shift count is a constant and we can do arithmetic in 6887 the mode of the shift, refine which bits we need. Otherwise, use the 6888 conservative form of the mask. */ 6889 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6890 && INTVAL (XEXP (x, 1)) >= 0 6891 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode) 6892 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) 6893 mask >>= INTVAL (XEXP (x, 1)); 6894 else 6895 mask = fuller_mask; 6896 6897 op0 = gen_lowpart_for_combine (op_mode, 6898 force_to_mode (XEXP (x, 0), op_mode, 6899 mask, reg, next_select)); 6900 6901 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 6902 x = gen_binary (code, op_mode, op0, XEXP (x, 1)); 6903 break; 6904 6905 case LSHIFTRT: 6906 /* Here we can only do something if the shift count is a constant, 6907 this shift constant is valid for the host, and we can do arithmetic 6908 in OP_MODE. */ 6909 6910 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6911 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 6912 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) 6913 { 6914 rtx inner = XEXP (x, 0); 6915 unsigned HOST_WIDE_INT inner_mask; 6916 6917 /* Select the mask of the bits we need for the shift operand. */ 6918 inner_mask = mask << INTVAL (XEXP (x, 1)); 6919 6920 /* We can only change the mode of the shift if we can do arithmetic 6921 in the mode of the shift and INNER_MASK is no wider than the 6922 width of OP_MODE. */ 6923 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT 6924 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0) 6925 op_mode = GET_MODE (x); 6926 6927 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select); 6928 6929 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) 6930 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); 6931 } 6932 6933 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the 6934 shift and AND produces only copies of the sign bit (C2 is one less 6935 than a power of two), we can do this with just a shift. */ 6936 6937 if (GET_CODE (x) == LSHIFTRT 6938 && GET_CODE (XEXP (x, 1)) == CONST_INT 6939 /* The shift puts one of the sign bit copies in the least significant 6940 bit. */ 6941 && ((INTVAL (XEXP (x, 1)) 6942 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) 6943 >= GET_MODE_BITSIZE (GET_MODE (x))) 6944 && exact_log2 (mask + 1) >= 0 6945 /* Number of bits left after the shift must be more than the mask 6946 needs. */ 6947 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1)) 6948 <= GET_MODE_BITSIZE (GET_MODE (x))) 6949 /* Must be more sign bit copies than the mask needs. */ 6950 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 6951 >= exact_log2 (mask + 1))) 6952 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), 6953 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x)) 6954 - exact_log2 (mask + 1))); 6955 6956 goto shiftrt; 6957 6958 case ASHIFTRT: 6959 /* If we are just looking for the sign bit, we don't need this shift at 6960 all, even if it has a variable count. */ 6961 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 6962 && (mask == ((unsigned HOST_WIDE_INT) 1 6963 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 6964 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 6965 6966 /* If this is a shift by a constant, get a mask that contains those bits 6967 that are not copies of the sign bit. We then have two cases: If 6968 MASK only includes those bits, this can be a logical shift, which may 6969 allow simplifications. If MASK is a single-bit field not within 6970 those bits, we are requesting a copy of the sign bit and hence can 6971 shift the sign bit to the appropriate location. */ 6972 6973 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0 6974 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 6975 { 6976 int i = -1; 6977 6978 /* If the considered data is wider than HOST_WIDE_INT, we can't 6979 represent a mask for all its bits in a single scalar. 6980 But we only care about the lower bits, so calculate these. */ 6981 6982 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT) 6983 { 6984 nonzero = ~(HOST_WIDE_INT) 0; 6985 6986 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 6987 is the number of bits a full-width mask would have set. 6988 We need only shift if these are fewer than nonzero can 6989 hold. If not, we must keep all bits set in nonzero. */ 6990 6991 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 6992 < HOST_BITS_PER_WIDE_INT) 6993 nonzero >>= INTVAL (XEXP (x, 1)) 6994 + HOST_BITS_PER_WIDE_INT 6995 - GET_MODE_BITSIZE (GET_MODE (x)) ; 6996 } 6997 else 6998 { 6999 nonzero = GET_MODE_MASK (GET_MODE (x)); 7000 nonzero >>= INTVAL (XEXP (x, 1)); 7001 } 7002 7003 if ((mask & ~nonzero) == 0 7004 || (i = exact_log2 (mask)) >= 0) 7005 { 7006 x = simplify_shift_const 7007 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0), 7008 i < 0 ? INTVAL (XEXP (x, 1)) 7009 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i); 7010 7011 if (GET_CODE (x) != ASHIFTRT) 7012 return force_to_mode (x, mode, mask, reg, next_select); 7013 } 7014 } 7015 7016 /* If MASK is 1, convert this to a LSHIFTRT. This can be done 7017 even if the shift count isn't a constant. */ 7018 if (mask == 1) 7019 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)); 7020 7021 shiftrt: 7022 7023 /* If this is a zero- or sign-extension operation that just affects bits 7024 we don't care about, remove it. Be sure the call above returned 7025 something that is still a shift. */ 7026 7027 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) 7028 && GET_CODE (XEXP (x, 1)) == CONST_INT 7029 && INTVAL (XEXP (x, 1)) >= 0 7030 && (INTVAL (XEXP (x, 1)) 7031 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1)) 7032 && GET_CODE (XEXP (x, 0)) == ASHIFT 7033 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 7034 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1))) 7035 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, 7036 reg, next_select); 7037 7038 break; 7039 7040 case ROTATE: 7041 case ROTATERT: 7042 /* If the shift count is constant and we can do computations 7043 in the mode of X, compute where the bits we care about are. 7044 Otherwise, we can't do anything. Don't change the mode of 7045 the shift or propagate MODE into the shift, though. */ 7046 if (GET_CODE (XEXP (x, 1)) == CONST_INT 7047 && INTVAL (XEXP (x, 1)) >= 0) 7048 { 7049 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, 7050 GET_MODE (x), GEN_INT (mask), 7051 XEXP (x, 1)); 7052 if (temp && GET_CODE(temp) == CONST_INT) 7053 SUBST (XEXP (x, 0), 7054 force_to_mode (XEXP (x, 0), GET_MODE (x), 7055 INTVAL (temp), reg, next_select)); 7056 } 7057 break; 7058 7059 case NEG: 7060 /* If we just want the low-order bit, the NEG isn't needed since it 7061 won't change the low-order bit. */ 7062 if (mask == 1) 7063 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select); 7064 7065 /* We need any bits less significant than the most significant bit in 7066 MASK since carries from those bits will affect the bits we are 7067 interested in. */ 7068 mask = fuller_mask; 7069 goto unop; 7070 7071 case NOT: 7072 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the 7073 same as the XOR case above. Ensure that the constant we form is not 7074 wider than the mode of X. */ 7075 7076 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 7077 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 7078 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 7079 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) 7080 < GET_MODE_BITSIZE (GET_MODE (x))) 7081 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) 7082 { 7083 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1))); 7084 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp); 7085 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1)); 7086 7087 return force_to_mode (x, mode, mask, reg, next_select); 7088 } 7089 7090 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must 7091 use the full mask inside the NOT. */ 7092 mask = fuller_mask; 7093 7094 unop: 7095 op0 = gen_lowpart_for_combine (op_mode, 7096 force_to_mode (XEXP (x, 0), mode, mask, 7097 reg, next_select)); 7098 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 7099 x = simplify_gen_unary (code, op_mode, op0, op_mode); 7100 break; 7101 7102 case NE: 7103 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included 7104 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, 7105 which is equal to STORE_FLAG_VALUE. */ 7106 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx 7107 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0 7108 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE) 7109 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 7110 7111 break; 7112 7113 case IF_THEN_ELSE: 7114 /* We have no way of knowing if the IF_THEN_ELSE can itself be 7115 written in a narrower mode. We play it safe and do not do so. */ 7116 7117 SUBST (XEXP (x, 1), 7118 gen_lowpart_for_combine (GET_MODE (x), 7119 force_to_mode (XEXP (x, 1), mode, 7120 mask, reg, next_select))); 7121 SUBST (XEXP (x, 2), 7122 gen_lowpart_for_combine (GET_MODE (x), 7123 force_to_mode (XEXP (x, 2), mode, 7124 mask, reg,next_select))); 7125 break; 7126 7127 default: 7128 break; 7129 } 7130 7131 /* Ensure we return a value of the proper mode. */ 7132 return gen_lowpart_for_combine (mode, x); 7133} 7134 7135/* Return nonzero if X is an expression that has one of two values depending on 7136 whether some other value is zero or nonzero. In that case, we return the 7137 value that is being tested, *PTRUE is set to the value if the rtx being 7138 returned has a nonzero value, and *PFALSE is set to the other alternative. 7139 7140 If we return zero, we set *PTRUE and *PFALSE to X. */ 7141 7142static rtx 7143if_then_else_cond (x, ptrue, pfalse) 7144 rtx x; 7145 rtx *ptrue, *pfalse; 7146{ 7147 enum machine_mode mode = GET_MODE (x); 7148 enum rtx_code code = GET_CODE (x); 7149 rtx cond0, cond1, true0, true1, false0, false1; 7150 unsigned HOST_WIDE_INT nz; 7151 7152 /* If we are comparing a value against zero, we are done. */ 7153 if ((code == NE || code == EQ) 7154 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0) 7155 { 7156 *ptrue = (code == NE) ? const_true_rtx : const0_rtx; 7157 *pfalse = (code == NE) ? const0_rtx : const_true_rtx; 7158 return XEXP (x, 0); 7159 } 7160 7161 /* If this is a unary operation whose operand has one of two values, apply 7162 our opcode to compute those values. */ 7163 else if (GET_RTX_CLASS (code) == '1' 7164 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) 7165 { 7166 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0))); 7167 *pfalse = simplify_gen_unary (code, mode, false0, 7168 GET_MODE (XEXP (x, 0))); 7169 return cond0; 7170 } 7171 7172 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would 7173 make can't possibly match and would suppress other optimizations. */ 7174 else if (code == COMPARE) 7175 ; 7176 7177 /* If this is a binary operation, see if either side has only one of two 7178 values. If either one does or if both do and they are conditional on 7179 the same value, compute the new true and false values. */ 7180 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2' 7181 || GET_RTX_CLASS (code) == '<') 7182 { 7183 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0); 7184 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1); 7185 7186 if ((cond0 != 0 || cond1 != 0) 7187 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1))) 7188 { 7189 /* If if_then_else_cond returned zero, then true/false are the 7190 same rtl. We must copy one of them to prevent invalid rtl 7191 sharing. */ 7192 if (cond0 == 0) 7193 true0 = copy_rtx (true0); 7194 else if (cond1 == 0) 7195 true1 = copy_rtx (true1); 7196 7197 *ptrue = gen_binary (code, mode, true0, true1); 7198 *pfalse = gen_binary (code, mode, false0, false1); 7199 return cond0 ? cond0 : cond1; 7200 } 7201 7202 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the 7203 operands is zero when the other is non-zero, and vice-versa, 7204 and STORE_FLAG_VALUE is 1 or -1. */ 7205 7206 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 7207 && (code == PLUS || code == IOR || code == XOR || code == MINUS 7208 || code == UMAX) 7209 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 7210 { 7211 rtx op0 = XEXP (XEXP (x, 0), 1); 7212 rtx op1 = XEXP (XEXP (x, 1), 1); 7213 7214 cond0 = XEXP (XEXP (x, 0), 0); 7215 cond1 = XEXP (XEXP (x, 1), 0); 7216 7217 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<' 7218 && GET_RTX_CLASS (GET_CODE (cond1)) == '<' 7219 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1) 7220 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 7221 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 7222 || ((swap_condition (GET_CODE (cond0)) 7223 == combine_reversed_comparison_code (cond1)) 7224 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 7225 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 7226 && ! side_effects_p (x)) 7227 { 7228 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx); 7229 *pfalse = gen_binary (MULT, mode, 7230 (code == MINUS 7231 ? simplify_gen_unary (NEG, mode, op1, 7232 mode) 7233 : op1), 7234 const_true_rtx); 7235 return cond0; 7236 } 7237 } 7238 7239 /* Similarly for MULT, AND and UMIN, except that for these the result 7240 is always zero. */ 7241 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 7242 && (code == MULT || code == AND || code == UMIN) 7243 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 7244 { 7245 cond0 = XEXP (XEXP (x, 0), 0); 7246 cond1 = XEXP (XEXP (x, 1), 0); 7247 7248 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<' 7249 && GET_RTX_CLASS (GET_CODE (cond1)) == '<' 7250 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1) 7251 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 7252 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 7253 || ((swap_condition (GET_CODE (cond0)) 7254 == combine_reversed_comparison_code (cond1)) 7255 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 7256 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 7257 && ! side_effects_p (x)) 7258 { 7259 *ptrue = *pfalse = const0_rtx; 7260 return cond0; 7261 } 7262 } 7263 } 7264 7265 else if (code == IF_THEN_ELSE) 7266 { 7267 /* If we have IF_THEN_ELSE already, extract the condition and 7268 canonicalize it if it is NE or EQ. */ 7269 cond0 = XEXP (x, 0); 7270 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); 7271 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) 7272 return XEXP (cond0, 0); 7273 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) 7274 { 7275 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); 7276 return XEXP (cond0, 0); 7277 } 7278 else 7279 return cond0; 7280 } 7281 7282 /* If X is a SUBREG, we can narrow both the true and false values 7283 if the inner expression, if there is a condition. */ 7284 else if (code == SUBREG 7285 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), 7286 &true0, &false0))) 7287 { 7288 *ptrue = simplify_gen_subreg (mode, true0, 7289 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 7290 *pfalse = simplify_gen_subreg (mode, false0, 7291 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 7292 7293 return cond0; 7294 } 7295 7296 /* If X is a constant, this isn't special and will cause confusions 7297 if we treat it as such. Likewise if it is equivalent to a constant. */ 7298 else if (CONSTANT_P (x) 7299 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) 7300 ; 7301 7302 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that 7303 will be least confusing to the rest of the compiler. */ 7304 else if (mode == BImode) 7305 { 7306 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx; 7307 return x; 7308 } 7309 7310 /* If X is known to be either 0 or -1, those are the true and 7311 false values when testing X. */ 7312 else if (x == constm1_rtx || x == const0_rtx 7313 || (mode != VOIDmode 7314 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode))) 7315 { 7316 *ptrue = constm1_rtx, *pfalse = const0_rtx; 7317 return x; 7318 } 7319 7320 /* Likewise for 0 or a single bit. */ 7321 else if (mode != VOIDmode 7322 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 7323 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0) 7324 { 7325 *ptrue = GEN_INT (nz), *pfalse = const0_rtx; 7326 return x; 7327 } 7328 7329 /* Otherwise fail; show no condition with true and false values the same. */ 7330 *ptrue = *pfalse = x; 7331 return 0; 7332} 7333 7334/* Return the value of expression X given the fact that condition COND 7335 is known to be true when applied to REG as its first operand and VAL 7336 as its second. X is known to not be shared and so can be modified in 7337 place. 7338 7339 We only handle the simplest cases, and specifically those cases that 7340 arise with IF_THEN_ELSE expressions. */ 7341 7342static rtx 7343known_cond (x, cond, reg, val) 7344 rtx x; 7345 enum rtx_code cond; 7346 rtx reg, val; 7347{ 7348 enum rtx_code code = GET_CODE (x); 7349 rtx temp; 7350 const char *fmt; 7351 int i, j; 7352 7353 if (side_effects_p (x)) 7354 return x; 7355 7356 /* If either operand of the condition is a floating point value, 7357 then we have to avoid collapsing an EQ comparison. */ 7358 if (cond == EQ 7359 && rtx_equal_p (x, reg) 7360 && ! FLOAT_MODE_P (GET_MODE (x)) 7361 && ! FLOAT_MODE_P (GET_MODE (val))) 7362 return val; 7363 7364 if (cond == UNEQ && rtx_equal_p (x, reg)) 7365 return val; 7366 7367 /* If X is (abs REG) and we know something about REG's relationship 7368 with zero, we may be able to simplify this. */ 7369 7370 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) 7371 switch (cond) 7372 { 7373 case GE: case GT: case EQ: 7374 return XEXP (x, 0); 7375 case LT: case LE: 7376 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)), 7377 XEXP (x, 0), 7378 GET_MODE (XEXP (x, 0))); 7379 default: 7380 break; 7381 } 7382 7383 /* The only other cases we handle are MIN, MAX, and comparisons if the 7384 operands are the same as REG and VAL. */ 7385 7386 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') 7387 { 7388 if (rtx_equal_p (XEXP (x, 0), val)) 7389 cond = swap_condition (cond), temp = val, val = reg, reg = temp; 7390 7391 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) 7392 { 7393 if (GET_RTX_CLASS (code) == '<') 7394 { 7395 if (comparison_dominates_p (cond, code)) 7396 return const_true_rtx; 7397 7398 code = combine_reversed_comparison_code (x); 7399 if (code != UNKNOWN 7400 && comparison_dominates_p (cond, code)) 7401 return const0_rtx; 7402 else 7403 return x; 7404 } 7405 else if (code == SMAX || code == SMIN 7406 || code == UMIN || code == UMAX) 7407 { 7408 int unsignedp = (code == UMIN || code == UMAX); 7409 7410 /* Do not reverse the condition when it is NE or EQ. 7411 This is because we cannot conclude anything about 7412 the value of 'SMAX (x, y)' when x is not equal to y, 7413 but we can when x equals y. */ 7414 if ((code == SMAX || code == UMAX) 7415 && ! (cond == EQ || cond == NE)) 7416 cond = reverse_condition (cond); 7417 7418 switch (cond) 7419 { 7420 case GE: case GT: 7421 return unsignedp ? x : XEXP (x, 1); 7422 case LE: case LT: 7423 return unsignedp ? x : XEXP (x, 0); 7424 case GEU: case GTU: 7425 return unsignedp ? XEXP (x, 1) : x; 7426 case LEU: case LTU: 7427 return unsignedp ? XEXP (x, 0) : x; 7428 default: 7429 break; 7430 } 7431 } 7432 } 7433 } 7434 7435 fmt = GET_RTX_FORMAT (code); 7436 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 7437 { 7438 if (fmt[i] == 'e') 7439 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); 7440 else if (fmt[i] == 'E') 7441 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 7442 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), 7443 cond, reg, val)); 7444 } 7445 7446 return x; 7447} 7448 7449/* See if X and Y are equal for the purposes of seeing if we can rewrite an 7450 assignment as a field assignment. */ 7451 7452static int 7453rtx_equal_for_field_assignment_p (x, y) 7454 rtx x; 7455 rtx y; 7456{ 7457 if (x == y || rtx_equal_p (x, y)) 7458 return 1; 7459 7460 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) 7461 return 0; 7462 7463 /* Check for a paradoxical SUBREG of a MEM compared with the MEM. 7464 Note that all SUBREGs of MEM are paradoxical; otherwise they 7465 would have been rewritten. */ 7466 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG 7467 && GET_CODE (SUBREG_REG (y)) == MEM 7468 && rtx_equal_p (SUBREG_REG (y), 7469 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x))) 7470 return 1; 7471 7472 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG 7473 && GET_CODE (SUBREG_REG (x)) == MEM 7474 && rtx_equal_p (SUBREG_REG (x), 7475 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y))) 7476 return 1; 7477 7478 /* We used to see if get_last_value of X and Y were the same but that's 7479 not correct. In one direction, we'll cause the assignment to have 7480 the wrong destination and in the case, we'll import a register into this 7481 insn that might have already have been dead. So fail if none of the 7482 above cases are true. */ 7483 return 0; 7484} 7485 7486/* See if X, a SET operation, can be rewritten as a bit-field assignment. 7487 Return that assignment if so. 7488 7489 We only handle the most common cases. */ 7490 7491static rtx 7492make_field_assignment (x) 7493 rtx x; 7494{ 7495 rtx dest = SET_DEST (x); 7496 rtx src = SET_SRC (x); 7497 rtx assign; 7498 rtx rhs, lhs; 7499 HOST_WIDE_INT c1; 7500 HOST_WIDE_INT pos; 7501 unsigned HOST_WIDE_INT len; 7502 rtx other; 7503 enum machine_mode mode; 7504 7505 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is 7506 a clear of a one-bit field. We will have changed it to 7507 (and (rotate (const_int -2) POS) DEST), so check for that. Also check 7508 for a SUBREG. */ 7509 7510 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE 7511 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT 7512 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 7513 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7514 { 7515 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 7516 1, 1, 1, 0); 7517 if (assign != 0) 7518 return gen_rtx_SET (VOIDmode, assign, const0_rtx); 7519 return x; 7520 } 7521 7522 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG 7523 && subreg_lowpart_p (XEXP (src, 0)) 7524 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) 7525 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) 7526 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE 7527 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 7528 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7529 { 7530 assign = make_extraction (VOIDmode, dest, 0, 7531 XEXP (SUBREG_REG (XEXP (src, 0)), 1), 7532 1, 1, 1, 0); 7533 if (assign != 0) 7534 return gen_rtx_SET (VOIDmode, assign, const0_rtx); 7535 return x; 7536 } 7537 7538 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a 7539 one-bit field. */ 7540 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT 7541 && XEXP (XEXP (src, 0), 0) == const1_rtx 7542 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7543 { 7544 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 7545 1, 1, 1, 0); 7546 if (assign != 0) 7547 return gen_rtx_SET (VOIDmode, assign, const1_rtx); 7548 return x; 7549 } 7550 7551 /* The other case we handle is assignments into a constant-position 7552 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents 7553 a mask that has all one bits except for a group of zero bits and 7554 OTHER is known to have zeros where C1 has ones, this is such an 7555 assignment. Compute the position and length from C1. Shift OTHER 7556 to the appropriate position, force it to the required mode, and 7557 make the extraction. Check for the AND in both operands. */ 7558 7559 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) 7560 return x; 7561 7562 rhs = expand_compound_operation (XEXP (src, 0)); 7563 lhs = expand_compound_operation (XEXP (src, 1)); 7564 7565 if (GET_CODE (rhs) == AND 7566 && GET_CODE (XEXP (rhs, 1)) == CONST_INT 7567 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) 7568 c1 = INTVAL (XEXP (rhs, 1)), other = lhs; 7569 else if (GET_CODE (lhs) == AND 7570 && GET_CODE (XEXP (lhs, 1)) == CONST_INT 7571 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) 7572 c1 = INTVAL (XEXP (lhs, 1)), other = rhs; 7573 else 7574 return x; 7575 7576 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len); 7577 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest)) 7578 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT 7579 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0) 7580 return x; 7581 7582 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); 7583 if (assign == 0) 7584 return x; 7585 7586 /* The mode to use for the source is the mode of the assignment, or of 7587 what is inside a possible STRICT_LOW_PART. */ 7588 mode = (GET_CODE (assign) == STRICT_LOW_PART 7589 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); 7590 7591 /* Shift OTHER right POS places and make it the source, restricting it 7592 to the proper length and mode. */ 7593 7594 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT, 7595 GET_MODE (src), other, pos), 7596 mode, 7597 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT 7598 ? ~(unsigned HOST_WIDE_INT) 0 7599 : ((unsigned HOST_WIDE_INT) 1 << len) - 1, 7600 dest, 0); 7601 7602 return gen_rtx_SET (VOIDmode, assign, src); 7603} 7604 7605/* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) 7606 if so. */ 7607 7608static rtx 7609apply_distributive_law (x) 7610 rtx x; 7611{ 7612 enum rtx_code code = GET_CODE (x); 7613 rtx lhs, rhs, other; 7614 rtx tem; 7615 enum rtx_code inner_code; 7616 7617 /* Distributivity is not true for floating point. 7618 It can change the value. So don't do it. 7619 -- rms and moshier@world.std.com. */ 7620 if (FLOAT_MODE_P (GET_MODE (x))) 7621 return x; 7622 7623 /* The outer operation can only be one of the following: */ 7624 if (code != IOR && code != AND && code != XOR 7625 && code != PLUS && code != MINUS) 7626 return x; 7627 7628 lhs = XEXP (x, 0), rhs = XEXP (x, 1); 7629 7630 /* If either operand is a primitive we can't do anything, so get out 7631 fast. */ 7632 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o' 7633 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o') 7634 return x; 7635 7636 lhs = expand_compound_operation (lhs); 7637 rhs = expand_compound_operation (rhs); 7638 inner_code = GET_CODE (lhs); 7639 if (inner_code != GET_CODE (rhs)) 7640 return x; 7641 7642 /* See if the inner and outer operations distribute. */ 7643 switch (inner_code) 7644 { 7645 case LSHIFTRT: 7646 case ASHIFTRT: 7647 case AND: 7648 case IOR: 7649 /* These all distribute except over PLUS. */ 7650 if (code == PLUS || code == MINUS) 7651 return x; 7652 break; 7653 7654 case MULT: 7655 if (code != PLUS && code != MINUS) 7656 return x; 7657 break; 7658 7659 case ASHIFT: 7660 /* This is also a multiply, so it distributes over everything. */ 7661 break; 7662 7663 case SUBREG: 7664 /* Non-paradoxical SUBREGs distributes over all operations, provided 7665 the inner modes and byte offsets are the same, this is an extraction 7666 of a low-order part, we don't convert an fp operation to int or 7667 vice versa, and we would not be converting a single-word 7668 operation into a multi-word operation. The latter test is not 7669 required, but it prevents generating unneeded multi-word operations. 7670 Some of the previous tests are redundant given the latter test, but 7671 are retained because they are required for correctness. 7672 7673 We produce the result slightly differently in this case. */ 7674 7675 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs)) 7676 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs) 7677 || ! subreg_lowpart_p (lhs) 7678 || (GET_MODE_CLASS (GET_MODE (lhs)) 7679 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) 7680 || (GET_MODE_SIZE (GET_MODE (lhs)) 7681 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) 7682 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD) 7683 return x; 7684 7685 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)), 7686 SUBREG_REG (lhs), SUBREG_REG (rhs)); 7687 return gen_lowpart_for_combine (GET_MODE (x), tem); 7688 7689 default: 7690 return x; 7691 } 7692 7693 /* Set LHS and RHS to the inner operands (A and B in the example 7694 above) and set OTHER to the common operand (C in the example). 7695 These is only one way to do this unless the inner operation is 7696 commutative. */ 7697 if (GET_RTX_CLASS (inner_code) == 'c' 7698 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) 7699 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); 7700 else if (GET_RTX_CLASS (inner_code) == 'c' 7701 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) 7702 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); 7703 else if (GET_RTX_CLASS (inner_code) == 'c' 7704 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) 7705 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); 7706 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) 7707 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); 7708 else 7709 return x; 7710 7711 /* Form the new inner operation, seeing if it simplifies first. */ 7712 tem = gen_binary (code, GET_MODE (x), lhs, rhs); 7713 7714 /* There is one exception to the general way of distributing: 7715 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */ 7716 if (code == XOR && inner_code == IOR) 7717 { 7718 inner_code = AND; 7719 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x)); 7720 } 7721 7722 /* We may be able to continuing distributing the result, so call 7723 ourselves recursively on the inner operation before forming the 7724 outer operation, which we return. */ 7725 return gen_binary (inner_code, GET_MODE (x), 7726 apply_distributive_law (tem), other); 7727} 7728 7729/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done 7730 in MODE. 7731 7732 Return an equivalent form, if different from X. Otherwise, return X. If 7733 X is zero, we are to always construct the equivalent form. */ 7734 7735static rtx 7736simplify_and_const_int (x, mode, varop, constop) 7737 rtx x; 7738 enum machine_mode mode; 7739 rtx varop; 7740 unsigned HOST_WIDE_INT constop; 7741{ 7742 unsigned HOST_WIDE_INT nonzero; 7743 int i; 7744 7745 /* Simplify VAROP knowing that we will be only looking at some of the 7746 bits in it. */ 7747 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0); 7748 7749 /* If VAROP is a CLOBBER, we will fail so return it; if it is a 7750 CONST_INT, we are done. */ 7751 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT) 7752 return varop; 7753 7754 /* See what bits may be nonzero in VAROP. Unlike the general case of 7755 a call to nonzero_bits, here we don't care about bits outside 7756 MODE. */ 7757 7758 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); 7759 7760 /* Turn off all bits in the constant that are known to already be zero. 7761 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS 7762 which is tested below. */ 7763 7764 constop &= nonzero; 7765 7766 /* If we don't have any bits left, return zero. */ 7767 if (constop == 0) 7768 return const0_rtx; 7769 7770 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is 7771 a power of two, we can replace this with a ASHIFT. */ 7772 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 7773 && (i = exact_log2 (constop)) >= 0) 7774 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); 7775 7776 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR 7777 or XOR, then try to apply the distributive law. This may eliminate 7778 operations if either branch can be simplified because of the AND. 7779 It may also make some cases more complex, but those cases probably 7780 won't match a pattern either with or without this. */ 7781 7782 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) 7783 return 7784 gen_lowpart_for_combine 7785 (mode, 7786 apply_distributive_law 7787 (gen_binary (GET_CODE (varop), GET_MODE (varop), 7788 simplify_and_const_int (NULL_RTX, GET_MODE (varop), 7789 XEXP (varop, 0), constop), 7790 simplify_and_const_int (NULL_RTX, GET_MODE (varop), 7791 XEXP (varop, 1), constop)))); 7792 7793 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute 7794 the AND and see if one of the operands simplifies to zero. If so, we 7795 may eliminate it. */ 7796 7797 if (GET_CODE (varop) == PLUS 7798 && exact_log2 (constop + 1) >= 0) 7799 { 7800 rtx o0, o1; 7801 7802 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop); 7803 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop); 7804 if (o0 == const0_rtx) 7805 return o1; 7806 if (o1 == const0_rtx) 7807 return o0; 7808 } 7809 7810 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG 7811 if we already had one (just check for the simplest cases). */ 7812 if (x && GET_CODE (XEXP (x, 0)) == SUBREG 7813 && GET_MODE (XEXP (x, 0)) == mode 7814 && SUBREG_REG (XEXP (x, 0)) == varop) 7815 varop = XEXP (x, 0); 7816 else 7817 varop = gen_lowpart_for_combine (mode, varop); 7818 7819 /* If we can't make the SUBREG, try to return what we were given. */ 7820 if (GET_CODE (varop) == CLOBBER) 7821 return x ? x : varop; 7822 7823 /* If we are only masking insignificant bits, return VAROP. */ 7824 if (constop == nonzero) 7825 x = varop; 7826 else 7827 { 7828 /* Otherwise, return an AND. */ 7829 constop = trunc_int_for_mode (constop, mode); 7830 /* See how much, if any, of X we can use. */ 7831 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode) 7832 x = gen_binary (AND, mode, varop, GEN_INT (constop)); 7833 7834 else 7835 { 7836 if (GET_CODE (XEXP (x, 1)) != CONST_INT 7837 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop) 7838 SUBST (XEXP (x, 1), GEN_INT (constop)); 7839 7840 SUBST (XEXP (x, 0), varop); 7841 } 7842 } 7843 7844 return x; 7845} 7846 7847/* We let num_sign_bit_copies recur into nonzero_bits as that is useful. 7848 We don't let nonzero_bits recur into num_sign_bit_copies, because that 7849 is less useful. We can't allow both, because that results in exponential 7850 run time recursion. There is a nullstone testcase that triggered 7851 this. This macro avoids accidental uses of num_sign_bit_copies. */ 7852#define num_sign_bit_copies() 7853 7854/* Given an expression, X, compute which bits in X can be non-zero. 7855 We don't care about bits outside of those defined in MODE. 7856 7857 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is 7858 a shift, AND, or zero_extract, we can do better. */ 7859 7860static unsigned HOST_WIDE_INT 7861nonzero_bits (x, mode) 7862 rtx x; 7863 enum machine_mode mode; 7864{ 7865 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode); 7866 unsigned HOST_WIDE_INT inner_nz; 7867 enum rtx_code code; 7868 unsigned int mode_width = GET_MODE_BITSIZE (mode); 7869 rtx tem; 7870 7871 /* For floating-point values, assume all bits are needed. */ 7872 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode)) 7873 return nonzero; 7874 7875 /* If X is wider than MODE, use its mode instead. */ 7876 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width) 7877 { 7878 mode = GET_MODE (x); 7879 nonzero = GET_MODE_MASK (mode); 7880 mode_width = GET_MODE_BITSIZE (mode); 7881 } 7882 7883 if (mode_width > HOST_BITS_PER_WIDE_INT) 7884 /* Our only callers in this case look for single bit values. So 7885 just return the mode mask. Those tests will then be false. */ 7886 return nonzero; 7887 7888#ifndef WORD_REGISTER_OPERATIONS 7889 /* If MODE is wider than X, but both are a single word for both the host 7890 and target machines, we can compute this from which bits of the 7891 object might be nonzero in its own mode, taking into account the fact 7892 that on many CISC machines, accessing an object in a wider mode 7893 causes the high-order bits to become undefined. So they are 7894 not known to be zero. */ 7895 7896 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode 7897 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD 7898 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 7899 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x))) 7900 { 7901 nonzero &= nonzero_bits (x, GET_MODE (x)); 7902 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)); 7903 return nonzero; 7904 } 7905#endif 7906 7907 code = GET_CODE (x); 7908 switch (code) 7909 { 7910 case REG: 7911#if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) 7912 /* If pointers extend unsigned and this is a pointer in Pmode, say that 7913 all the bits above ptr_mode are known to be zero. */ 7914 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode 7915 && REG_POINTER (x)) 7916 nonzero &= GET_MODE_MASK (ptr_mode); 7917#endif 7918 7919#ifdef STACK_BOUNDARY 7920 /* If this is the stack pointer, we may know something about its 7921 alignment. If PUSH_ROUNDING is defined, it is possible for the 7922 stack to be momentarily aligned only to that amount, so we pick 7923 the least alignment. */ 7924 7925 /* We can't check for arg_pointer_rtx here, because it is not 7926 guaranteed to have as much alignment as the stack pointer. 7927 In particular, in the Irix6 n64 ABI, the stack has 128 bit 7928 alignment but the argument pointer has only 64 bit alignment. */ 7929 7930 if ((x == frame_pointer_rtx 7931 || x == stack_pointer_rtx 7932 || x == hard_frame_pointer_rtx 7933 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER 7934 && REGNO (x) <= LAST_VIRTUAL_REGISTER)) 7935#ifdef STACK_BIAS 7936 && !STACK_BIAS 7937#endif 7938 ) 7939 { 7940 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; 7941 7942#ifdef PUSH_ROUNDING 7943 if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS) 7944 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment); 7945#endif 7946 7947 /* We must return here, otherwise we may get a worse result from 7948 one of the choices below. There is nothing useful below as 7949 far as the stack pointer is concerned. */ 7950 return nonzero &= ~(sp_alignment - 1); 7951 } 7952#endif 7953 7954 /* If X is a register whose nonzero bits value is current, use it. 7955 Otherwise, if X is a register whose value we can find, use that 7956 value. Otherwise, use the previously-computed global nonzero bits 7957 for this register. */ 7958 7959 if (reg_last_set_value[REGNO (x)] != 0 7960 && reg_last_set_mode[REGNO (x)] == mode 7961 && (reg_last_set_label[REGNO (x)] == label_tick 7962 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 7963 && REG_N_SETS (REGNO (x)) == 1 7964 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, 7965 REGNO (x)))) 7966 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) 7967 return reg_last_set_nonzero_bits[REGNO (x)]; 7968 7969 tem = get_last_value (x); 7970 7971 if (tem) 7972 { 7973#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 7974 /* If X is narrower than MODE and TEM is a non-negative 7975 constant that would appear negative in the mode of X, 7976 sign-extend it for use in reg_nonzero_bits because some 7977 machines (maybe most) will actually do the sign-extension 7978 and this is the conservative approach. 7979 7980 ??? For 2.5, try to tighten up the MD files in this regard 7981 instead of this kludge. */ 7982 7983 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width 7984 && GET_CODE (tem) == CONST_INT 7985 && INTVAL (tem) > 0 7986 && 0 != (INTVAL (tem) 7987 & ((HOST_WIDE_INT) 1 7988 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 7989 tem = GEN_INT (INTVAL (tem) 7990 | ((HOST_WIDE_INT) (-1) 7991 << GET_MODE_BITSIZE (GET_MODE (x)))); 7992#endif 7993 return nonzero_bits (tem, mode); 7994 } 7995 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)]) 7996 { 7997 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)]; 7998 7999 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width) 8000 /* We don't know anything about the upper bits. */ 8001 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x)); 8002 return nonzero & mask; 8003 } 8004 else 8005 return nonzero; 8006 8007 case CONST_INT: 8008#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 8009 /* If X is negative in MODE, sign-extend the value. */ 8010 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD 8011 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1)))) 8012 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width)); 8013#endif 8014 8015 return INTVAL (x); 8016 8017 case MEM: 8018#ifdef LOAD_EXTEND_OP 8019 /* In many, if not most, RISC machines, reading a byte from memory 8020 zeros the rest of the register. Noticing that fact saves a lot 8021 of extra zero-extends. */ 8022 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND) 8023 nonzero &= GET_MODE_MASK (GET_MODE (x)); 8024#endif 8025 break; 8026 8027 case EQ: case NE: 8028 case UNEQ: case LTGT: 8029 case GT: case GTU: case UNGT: 8030 case LT: case LTU: case UNLT: 8031 case GE: case GEU: case UNGE: 8032 case LE: case LEU: case UNLE: 8033 case UNORDERED: case ORDERED: 8034 8035 /* If this produces an integer result, we know which bits are set. 8036 Code here used to clear bits outside the mode of X, but that is 8037 now done above. */ 8038 8039 if (GET_MODE_CLASS (mode) == MODE_INT 8040 && mode_width <= HOST_BITS_PER_WIDE_INT) 8041 nonzero = STORE_FLAG_VALUE; 8042 break; 8043 8044 case NEG: 8045#if 0 8046 /* Disabled to avoid exponential mutual recursion between nonzero_bits 8047 and num_sign_bit_copies. */ 8048 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) 8049 == GET_MODE_BITSIZE (GET_MODE (x))) 8050 nonzero = 1; 8051#endif 8052 8053 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width) 8054 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x))); 8055 break; 8056 8057 case ABS: 8058#if 0 8059 /* Disabled to avoid exponential mutual recursion between nonzero_bits 8060 and num_sign_bit_copies. */ 8061 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) 8062 == GET_MODE_BITSIZE (GET_MODE (x))) 8063 nonzero = 1; 8064#endif 8065 break; 8066 8067 case TRUNCATE: 8068 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode)); 8069 break; 8070 8071 case ZERO_EXTEND: 8072 nonzero &= nonzero_bits (XEXP (x, 0), mode); 8073 if (GET_MODE (XEXP (x, 0)) != VOIDmode) 8074 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); 8075 break; 8076 8077 case SIGN_EXTEND: 8078 /* If the sign bit is known clear, this is the same as ZERO_EXTEND. 8079 Otherwise, show all the bits in the outer mode but not the inner 8080 may be non-zero. */ 8081 inner_nz = nonzero_bits (XEXP (x, 0), mode); 8082 if (GET_MODE (XEXP (x, 0)) != VOIDmode) 8083 { 8084 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); 8085 if (inner_nz 8086 & (((HOST_WIDE_INT) 1 8087 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))) 8088 inner_nz |= (GET_MODE_MASK (mode) 8089 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))); 8090 } 8091 8092 nonzero &= inner_nz; 8093 break; 8094 8095 case AND: 8096 nonzero &= (nonzero_bits (XEXP (x, 0), mode) 8097 & nonzero_bits (XEXP (x, 1), mode)); 8098 break; 8099 8100 case XOR: case IOR: 8101 case UMIN: case UMAX: case SMIN: case SMAX: 8102 nonzero &= (nonzero_bits (XEXP (x, 0), mode) 8103 | nonzero_bits (XEXP (x, 1), mode)); 8104 break; 8105 8106 case PLUS: case MINUS: 8107 case MULT: 8108 case DIV: case UDIV: 8109 case MOD: case UMOD: 8110 /* We can apply the rules of arithmetic to compute the number of 8111 high- and low-order zero bits of these operations. We start by 8112 computing the width (position of the highest-order non-zero bit) 8113 and the number of low-order zero bits for each value. */ 8114 { 8115 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode); 8116 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode); 8117 int width0 = floor_log2 (nz0) + 1; 8118 int width1 = floor_log2 (nz1) + 1; 8119 int low0 = floor_log2 (nz0 & -nz0); 8120 int low1 = floor_log2 (nz1 & -nz1); 8121 HOST_WIDE_INT op0_maybe_minusp 8122 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); 8123 HOST_WIDE_INT op1_maybe_minusp 8124 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); 8125 unsigned int result_width = mode_width; 8126 int result_low = 0; 8127 8128 switch (code) 8129 { 8130 case PLUS: 8131#ifdef STACK_BIAS 8132 if (STACK_BIAS 8133 && (XEXP (x, 0) == stack_pointer_rtx 8134 || XEXP (x, 0) == frame_pointer_rtx) 8135 && GET_CODE (XEXP (x, 1)) == CONST_INT) 8136 { 8137 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; 8138 8139 nz0 = (GET_MODE_MASK (mode) & ~(sp_alignment - 1)); 8140 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS; 8141 width0 = floor_log2 (nz0) + 1; 8142 width1 = floor_log2 (nz1) + 1; 8143 low0 = floor_log2 (nz0 & -nz0); 8144 low1 = floor_log2 (nz1 & -nz1); 8145 } 8146#endif 8147 result_width = MAX (width0, width1) + 1; 8148 result_low = MIN (low0, low1); 8149 break; 8150 case MINUS: 8151 result_low = MIN (low0, low1); 8152 break; 8153 case MULT: 8154 result_width = width0 + width1; 8155 result_low = low0 + low1; 8156 break; 8157 case DIV: 8158 if (width1 == 0) 8159 break; 8160 if (! op0_maybe_minusp && ! op1_maybe_minusp) 8161 result_width = width0; 8162 break; 8163 case UDIV: 8164 if (width1 == 0) 8165 break; 8166 result_width = width0; 8167 break; 8168 case MOD: 8169 if (width1 == 0) 8170 break; 8171 if (! op0_maybe_minusp && ! op1_maybe_minusp) 8172 result_width = MIN (width0, width1); 8173 result_low = MIN (low0, low1); 8174 break; 8175 case UMOD: 8176 if (width1 == 0) 8177 break; 8178 result_width = MIN (width0, width1); 8179 result_low = MIN (low0, low1); 8180 break; 8181 default: 8182 abort (); 8183 } 8184 8185 if (result_width < mode_width) 8186 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1; 8187 8188 if (result_low > 0) 8189 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1); 8190 8191#ifdef POINTERS_EXTEND_UNSIGNED 8192 /* If pointers extend unsigned and this is an addition or subtraction 8193 to a pointer in Pmode, all the bits above ptr_mode are known to be 8194 zero. */ 8195 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode 8196 && (code == PLUS || code == MINUS) 8197 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0))) 8198 nonzero &= GET_MODE_MASK (ptr_mode); 8199#endif 8200 } 8201 break; 8202 8203 case ZERO_EXTRACT: 8204 if (GET_CODE (XEXP (x, 1)) == CONST_INT 8205 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 8206 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1; 8207 break; 8208 8209 case SUBREG: 8210 /* If this is a SUBREG formed for a promoted variable that has 8211 been zero-extended, we know that at least the high-order bits 8212 are zero, though others might be too. */ 8213 8214 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x)) 8215 nonzero = (GET_MODE_MASK (GET_MODE (x)) 8216 & nonzero_bits (SUBREG_REG (x), GET_MODE (x))); 8217 8218 /* If the inner mode is a single word for both the host and target 8219 machines, we can compute this from which bits of the inner 8220 object might be nonzero. */ 8221 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD 8222 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) 8223 <= HOST_BITS_PER_WIDE_INT)) 8224 { 8225 nonzero &= nonzero_bits (SUBREG_REG (x), mode); 8226 8227#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP) 8228 /* If this is a typical RISC machine, we only have to worry 8229 about the way loads are extended. */ 8230 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND 8231 ? (((nonzero 8232 & (((unsigned HOST_WIDE_INT) 1 8233 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))) 8234 != 0)) 8235 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND) 8236#endif 8237 { 8238 /* On many CISC machines, accessing an object in a wider mode 8239 causes the high-order bits to become undefined. So they are 8240 not known to be zero. */ 8241 if (GET_MODE_SIZE (GET_MODE (x)) 8242 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 8243 nonzero |= (GET_MODE_MASK (GET_MODE (x)) 8244 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))); 8245 } 8246 } 8247 break; 8248 8249 case ASHIFTRT: 8250 case LSHIFTRT: 8251 case ASHIFT: 8252 case ROTATE: 8253 /* The nonzero bits are in two classes: any bits within MODE 8254 that aren't in GET_MODE (x) are always significant. The rest of the 8255 nonzero bits are those that are significant in the operand of 8256 the shift when shifted the appropriate number of bits. This 8257 shows that high-order bits are cleared by the right shift and 8258 low-order bits by left shifts. */ 8259 if (GET_CODE (XEXP (x, 1)) == CONST_INT 8260 && INTVAL (XEXP (x, 1)) >= 0 8261 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 8262 { 8263 enum machine_mode inner_mode = GET_MODE (x); 8264 unsigned int width = GET_MODE_BITSIZE (inner_mode); 8265 int count = INTVAL (XEXP (x, 1)); 8266 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode); 8267 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode); 8268 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask; 8269 unsigned HOST_WIDE_INT outer = 0; 8270 8271 if (mode_width > width) 8272 outer = (op_nonzero & nonzero & ~mode_mask); 8273 8274 if (code == LSHIFTRT) 8275 inner >>= count; 8276 else if (code == ASHIFTRT) 8277 { 8278 inner >>= count; 8279 8280 /* If the sign bit may have been nonzero before the shift, we 8281 need to mark all the places it could have been copied to 8282 by the shift as possibly nonzero. */ 8283 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count))) 8284 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count); 8285 } 8286 else if (code == ASHIFT) 8287 inner <<= count; 8288 else 8289 inner = ((inner << (count % width) 8290 | (inner >> (width - (count % width)))) & mode_mask); 8291 8292 nonzero &= (outer | inner); 8293 } 8294 break; 8295 8296 case FFS: 8297 /* This is at most the number of bits in the mode. */ 8298 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1; 8299 break; 8300 8301 case IF_THEN_ELSE: 8302 nonzero &= (nonzero_bits (XEXP (x, 1), mode) 8303 | nonzero_bits (XEXP (x, 2), mode)); 8304 break; 8305 8306 default: 8307 break; 8308 } 8309 8310 return nonzero; 8311} 8312 8313/* See the macro definition above. */ 8314#undef num_sign_bit_copies 8315 8316/* Return the number of bits at the high-order end of X that are known to 8317 be equal to the sign bit. X will be used in mode MODE; if MODE is 8318 VOIDmode, X will be used in its own mode. The returned value will always 8319 be between 1 and the number of bits in MODE. */ 8320 8321static unsigned int 8322num_sign_bit_copies (x, mode) 8323 rtx x; 8324 enum machine_mode mode; 8325{ 8326 enum rtx_code code = GET_CODE (x); 8327 unsigned int bitwidth; 8328 int num0, num1, result; 8329 unsigned HOST_WIDE_INT nonzero; 8330 rtx tem; 8331 8332 /* If we weren't given a mode, use the mode of X. If the mode is still 8333 VOIDmode, we don't know anything. Likewise if one of the modes is 8334 floating-point. */ 8335 8336 if (mode == VOIDmode) 8337 mode = GET_MODE (x); 8338 8339 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x))) 8340 return 1; 8341 8342 bitwidth = GET_MODE_BITSIZE (mode); 8343 8344 /* For a smaller object, just ignore the high bits. */ 8345 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x))) 8346 { 8347 num0 = num_sign_bit_copies (x, GET_MODE (x)); 8348 return MAX (1, 8349 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)); 8350 } 8351 8352 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x))) 8353 { 8354#ifndef WORD_REGISTER_OPERATIONS 8355 /* If this machine does not do all register operations on the entire 8356 register and MODE is wider than the mode of X, we can say nothing 8357 at all about the high-order bits. */ 8358 return 1; 8359#else 8360 /* Likewise on machines that do, if the mode of the object is smaller 8361 than a word and loads of that size don't sign extend, we can say 8362 nothing about the high order bits. */ 8363 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD 8364#ifdef LOAD_EXTEND_OP 8365 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND 8366#endif 8367 ) 8368 return 1; 8369#endif 8370 } 8371 8372 switch (code) 8373 { 8374 case REG: 8375 8376#if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) 8377 /* If pointers extend signed and this is a pointer in Pmode, say that 8378 all the bits above ptr_mode are known to be sign bit copies. */ 8379 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode 8380 && REG_POINTER (x)) 8381 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1; 8382#endif 8383 8384 if (reg_last_set_value[REGNO (x)] != 0 8385 && reg_last_set_mode[REGNO (x)] == mode 8386 && (reg_last_set_label[REGNO (x)] == label_tick 8387 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 8388 && REG_N_SETS (REGNO (x)) == 1 8389 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, 8390 REGNO (x)))) 8391 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) 8392 return reg_last_set_sign_bit_copies[REGNO (x)]; 8393 8394 tem = get_last_value (x); 8395 if (tem != 0) 8396 return num_sign_bit_copies (tem, mode); 8397 8398 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0 8399 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth) 8400 return reg_sign_bit_copies[REGNO (x)]; 8401 break; 8402 8403 case MEM: 8404#ifdef LOAD_EXTEND_OP 8405 /* Some RISC machines sign-extend all loads of smaller than a word. */ 8406 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND) 8407 return MAX (1, ((int) bitwidth 8408 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1)); 8409#endif 8410 break; 8411 8412 case CONST_INT: 8413 /* If the constant is negative, take its 1's complement and remask. 8414 Then see how many zero bits we have. */ 8415 nonzero = INTVAL (x) & GET_MODE_MASK (mode); 8416 if (bitwidth <= HOST_BITS_PER_WIDE_INT 8417 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8418 nonzero = (~nonzero) & GET_MODE_MASK (mode); 8419 8420 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); 8421 8422 case SUBREG: 8423 /* If this is a SUBREG for a promoted object that is sign-extended 8424 and we are looking at it in a wider mode, we know that at least the 8425 high-order bits are known to be sign bit copies. */ 8426 8427 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x)) 8428 { 8429 num0 = num_sign_bit_copies (SUBREG_REG (x), mode); 8430 return MAX ((int) bitwidth 8431 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1, 8432 num0); 8433 } 8434 8435 /* For a smaller object, just ignore the high bits. */ 8436 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))) 8437 { 8438 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode); 8439 return MAX (1, (num0 8440 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) 8441 - bitwidth))); 8442 } 8443 8444#ifdef WORD_REGISTER_OPERATIONS 8445#ifdef LOAD_EXTEND_OP 8446 /* For paradoxical SUBREGs on machines where all register operations 8447 affect the entire register, just look inside. Note that we are 8448 passing MODE to the recursive call, so the number of sign bit copies 8449 will remain relative to that mode, not the inner mode. */ 8450 8451 /* This works only if loads sign extend. Otherwise, if we get a 8452 reload for the inner part, it may be loaded from the stack, and 8453 then we lose all sign bit copies that existed before the store 8454 to the stack. */ 8455 8456 if ((GET_MODE_SIZE (GET_MODE (x)) 8457 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 8458 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND) 8459 return num_sign_bit_copies (SUBREG_REG (x), mode); 8460#endif 8461#endif 8462 break; 8463 8464 case SIGN_EXTRACT: 8465 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 8466 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1))); 8467 break; 8468 8469 case SIGN_EXTEND: 8470 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 8471 + num_sign_bit_copies (XEXP (x, 0), VOIDmode)); 8472 8473 case TRUNCATE: 8474 /* For a smaller object, just ignore the high bits. */ 8475 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode); 8476 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 8477 - bitwidth))); 8478 8479 case NOT: 8480 return num_sign_bit_copies (XEXP (x, 0), mode); 8481 8482 case ROTATE: case ROTATERT: 8483 /* If we are rotating left by a number of bits less than the number 8484 of sign bit copies, we can just subtract that amount from the 8485 number. */ 8486 if (GET_CODE (XEXP (x, 1)) == CONST_INT 8487 && INTVAL (XEXP (x, 1)) >= 0 8488 && INTVAL (XEXP (x, 1)) < (int) bitwidth) 8489 { 8490 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8491 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1)) 8492 : (int) bitwidth - INTVAL (XEXP (x, 1)))); 8493 } 8494 break; 8495 8496 case NEG: 8497 /* In general, this subtracts one sign bit copy. But if the value 8498 is known to be positive, the number of sign bit copies is the 8499 same as that of the input. Finally, if the input has just one bit 8500 that might be nonzero, all the bits are copies of the sign bit. */ 8501 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8502 if (bitwidth > HOST_BITS_PER_WIDE_INT) 8503 return num0 > 1 ? num0 - 1 : 1; 8504 8505 nonzero = nonzero_bits (XEXP (x, 0), mode); 8506 if (nonzero == 1) 8507 return bitwidth; 8508 8509 if (num0 > 1 8510 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero)) 8511 num0--; 8512 8513 return num0; 8514 8515 case IOR: case AND: case XOR: 8516 case SMIN: case SMAX: case UMIN: case UMAX: 8517 /* Logical operations will preserve the number of sign-bit copies. 8518 MIN and MAX operations always return one of the operands. */ 8519 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8520 num1 = num_sign_bit_copies (XEXP (x, 1), mode); 8521 return MIN (num0, num1); 8522 8523 case PLUS: case MINUS: 8524 /* For addition and subtraction, we can have a 1-bit carry. However, 8525 if we are subtracting 1 from a positive number, there will not 8526 be such a carry. Furthermore, if the positive number is known to 8527 be 0 or 1, we know the result is either -1 or 0. */ 8528 8529 if (code == PLUS && XEXP (x, 1) == constm1_rtx 8530 && bitwidth <= HOST_BITS_PER_WIDE_INT) 8531 { 8532 nonzero = nonzero_bits (XEXP (x, 0), mode); 8533 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0) 8534 return (nonzero == 1 || nonzero == 0 ? bitwidth 8535 : bitwidth - floor_log2 (nonzero) - 1); 8536 } 8537 8538 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8539 num1 = num_sign_bit_copies (XEXP (x, 1), mode); 8540 result = MAX (1, MIN (num0, num1) - 1); 8541 8542#ifdef POINTERS_EXTEND_UNSIGNED 8543 /* If pointers extend signed and this is an addition or subtraction 8544 to a pointer in Pmode, all the bits above ptr_mode are known to be 8545 sign bit copies. */ 8546 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode 8547 && (code == PLUS || code == MINUS) 8548 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0))) 8549 result = MAX ((int) (GET_MODE_BITSIZE (Pmode) 8550 - GET_MODE_BITSIZE (ptr_mode) + 1), 8551 result); 8552#endif 8553 return result; 8554 8555 case MULT: 8556 /* The number of bits of the product is the sum of the number of 8557 bits of both terms. However, unless one of the terms if known 8558 to be positive, we must allow for an additional bit since negating 8559 a negative number can remove one sign bit copy. */ 8560 8561 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8562 num1 = num_sign_bit_copies (XEXP (x, 1), mode); 8563 8564 result = bitwidth - (bitwidth - num0) - (bitwidth - num1); 8565 if (result > 0 8566 && (bitwidth > HOST_BITS_PER_WIDE_INT 8567 || (((nonzero_bits (XEXP (x, 0), mode) 8568 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8569 && ((nonzero_bits (XEXP (x, 1), mode) 8570 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)))) 8571 result--; 8572 8573 return MAX (1, result); 8574 8575 case UDIV: 8576 /* The result must be <= the first operand. If the first operand 8577 has the high bit set, we know nothing about the number of sign 8578 bit copies. */ 8579 if (bitwidth > HOST_BITS_PER_WIDE_INT) 8580 return 1; 8581 else if ((nonzero_bits (XEXP (x, 0), mode) 8582 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8583 return 1; 8584 else 8585 return num_sign_bit_copies (XEXP (x, 0), mode); 8586 8587 case UMOD: 8588 /* The result must be <= the second operand. */ 8589 return num_sign_bit_copies (XEXP (x, 1), mode); 8590 8591 case DIV: 8592 /* Similar to unsigned division, except that we have to worry about 8593 the case where the divisor is negative, in which case we have 8594 to add 1. */ 8595 result = num_sign_bit_copies (XEXP (x, 0), mode); 8596 if (result > 1 8597 && (bitwidth > HOST_BITS_PER_WIDE_INT 8598 || (nonzero_bits (XEXP (x, 1), mode) 8599 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) 8600 result--; 8601 8602 return result; 8603 8604 case MOD: 8605 result = num_sign_bit_copies (XEXP (x, 1), mode); 8606 if (result > 1 8607 && (bitwidth > HOST_BITS_PER_WIDE_INT 8608 || (nonzero_bits (XEXP (x, 1), mode) 8609 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) 8610 result--; 8611 8612 return result; 8613 8614 case ASHIFTRT: 8615 /* Shifts by a constant add to the number of bits equal to the 8616 sign bit. */ 8617 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8618 if (GET_CODE (XEXP (x, 1)) == CONST_INT 8619 && INTVAL (XEXP (x, 1)) > 0) 8620 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1))); 8621 8622 return num0; 8623 8624 case ASHIFT: 8625 /* Left shifts destroy copies. */ 8626 if (GET_CODE (XEXP (x, 1)) != CONST_INT 8627 || INTVAL (XEXP (x, 1)) < 0 8628 || INTVAL (XEXP (x, 1)) >= (int) bitwidth) 8629 return 1; 8630 8631 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8632 return MAX (1, num0 - INTVAL (XEXP (x, 1))); 8633 8634 case IF_THEN_ELSE: 8635 num0 = num_sign_bit_copies (XEXP (x, 1), mode); 8636 num1 = num_sign_bit_copies (XEXP (x, 2), mode); 8637 return MIN (num0, num1); 8638 8639 case EQ: case NE: case GE: case GT: case LE: case LT: 8640 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT: 8641 case GEU: case GTU: case LEU: case LTU: 8642 case UNORDERED: case ORDERED: 8643 /* If the constant is negative, take its 1's complement and remask. 8644 Then see how many zero bits we have. */ 8645 nonzero = STORE_FLAG_VALUE; 8646 if (bitwidth <= HOST_BITS_PER_WIDE_INT 8647 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8648 nonzero = (~nonzero) & GET_MODE_MASK (mode); 8649 8650 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); 8651 break; 8652 8653 default: 8654 break; 8655 } 8656 8657 /* If we haven't been able to figure it out by one of the above rules, 8658 see if some of the high-order bits are known to be zero. If so, 8659 count those bits and return one less than that amount. If we can't 8660 safely compute the mask for this mode, always return BITWIDTH. */ 8661 8662 if (bitwidth > HOST_BITS_PER_WIDE_INT) 8663 return 1; 8664 8665 nonzero = nonzero_bits (x, mode); 8666 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) 8667 ? 1 : bitwidth - floor_log2 (nonzero) - 1); 8668} 8669 8670/* Return the number of "extended" bits there are in X, when interpreted 8671 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For 8672 unsigned quantities, this is the number of high-order zero bits. 8673 For signed quantities, this is the number of copies of the sign bit 8674 minus 1. In both case, this function returns the number of "spare" 8675 bits. For example, if two quantities for which this function returns 8676 at least 1 are added, the addition is known not to overflow. 8677 8678 This function will always return 0 unless called during combine, which 8679 implies that it must be called from a define_split. */ 8680 8681unsigned int 8682extended_count (x, mode, unsignedp) 8683 rtx x; 8684 enum machine_mode mode; 8685 int unsignedp; 8686{ 8687 if (nonzero_sign_valid == 0) 8688 return 0; 8689 8690 return (unsignedp 8691 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 8692 ? (GET_MODE_BITSIZE (mode) - 1 8693 - floor_log2 (nonzero_bits (x, mode))) 8694 : 0) 8695 : num_sign_bit_copies (x, mode) - 1); 8696} 8697 8698/* This function is called from `simplify_shift_const' to merge two 8699 outer operations. Specifically, we have already found that we need 8700 to perform operation *POP0 with constant *PCONST0 at the outermost 8701 position. We would now like to also perform OP1 with constant CONST1 8702 (with *POP0 being done last). 8703 8704 Return 1 if we can do the operation and update *POP0 and *PCONST0 with 8705 the resulting operation. *PCOMP_P is set to 1 if we would need to 8706 complement the innermost operand, otherwise it is unchanged. 8707 8708 MODE is the mode in which the operation will be done. No bits outside 8709 the width of this mode matter. It is assumed that the width of this mode 8710 is smaller than or equal to HOST_BITS_PER_WIDE_INT. 8711 8712 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS, 8713 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper 8714 result is simply *PCONST0. 8715 8716 If the resulting operation cannot be expressed as one operation, we 8717 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ 8718 8719static int 8720merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p) 8721 enum rtx_code *pop0; 8722 HOST_WIDE_INT *pconst0; 8723 enum rtx_code op1; 8724 HOST_WIDE_INT const1; 8725 enum machine_mode mode; 8726 int *pcomp_p; 8727{ 8728 enum rtx_code op0 = *pop0; 8729 HOST_WIDE_INT const0 = *pconst0; 8730 8731 const0 &= GET_MODE_MASK (mode); 8732 const1 &= GET_MODE_MASK (mode); 8733 8734 /* If OP0 is an AND, clear unimportant bits in CONST1. */ 8735 if (op0 == AND) 8736 const1 &= const0; 8737 8738 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or 8739 if OP0 is SET. */ 8740 8741 if (op1 == NIL || op0 == SET) 8742 return 1; 8743 8744 else if (op0 == NIL) 8745 op0 = op1, const0 = const1; 8746 8747 else if (op0 == op1) 8748 { 8749 switch (op0) 8750 { 8751 case AND: 8752 const0 &= const1; 8753 break; 8754 case IOR: 8755 const0 |= const1; 8756 break; 8757 case XOR: 8758 const0 ^= const1; 8759 break; 8760 case PLUS: 8761 const0 += const1; 8762 break; 8763 case NEG: 8764 op0 = NIL; 8765 break; 8766 default: 8767 break; 8768 } 8769 } 8770 8771 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ 8772 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) 8773 return 0; 8774 8775 /* If the two constants aren't the same, we can't do anything. The 8776 remaining six cases can all be done. */ 8777 else if (const0 != const1) 8778 return 0; 8779 8780 else 8781 switch (op0) 8782 { 8783 case IOR: 8784 if (op1 == AND) 8785 /* (a & b) | b == b */ 8786 op0 = SET; 8787 else /* op1 == XOR */ 8788 /* (a ^ b) | b == a | b */ 8789 {;} 8790 break; 8791 8792 case XOR: 8793 if (op1 == AND) 8794 /* (a & b) ^ b == (~a) & b */ 8795 op0 = AND, *pcomp_p = 1; 8796 else /* op1 == IOR */ 8797 /* (a | b) ^ b == a & ~b */ 8798 op0 = AND, *pconst0 = ~const0; 8799 break; 8800 8801 case AND: 8802 if (op1 == IOR) 8803 /* (a | b) & b == b */ 8804 op0 = SET; 8805 else /* op1 == XOR */ 8806 /* (a ^ b) & b) == (~a) & b */ 8807 *pcomp_p = 1; 8808 break; 8809 default: 8810 break; 8811 } 8812 8813 /* Check for NO-OP cases. */ 8814 const0 &= GET_MODE_MASK (mode); 8815 if (const0 == 0 8816 && (op0 == IOR || op0 == XOR || op0 == PLUS)) 8817 op0 = NIL; 8818 else if (const0 == 0 && op0 == AND) 8819 op0 = SET; 8820 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) 8821 && op0 == AND) 8822 op0 = NIL; 8823 8824 /* ??? Slightly redundant with the above mask, but not entirely. 8825 Moving this above means we'd have to sign-extend the mode mask 8826 for the final test. */ 8827 const0 = trunc_int_for_mode (const0, mode); 8828 8829 *pop0 = op0; 8830 *pconst0 = const0; 8831 8832 return 1; 8833} 8834 8835/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. 8836 The result of the shift is RESULT_MODE. X, if non-zero, is an expression 8837 that we started with. 8838 8839 The shift is normally computed in the widest mode we find in VAROP, as 8840 long as it isn't a different number of words than RESULT_MODE. Exceptions 8841 are ASHIFTRT and ROTATE, which are always done in their original mode, */ 8842 8843static rtx 8844simplify_shift_const (x, code, result_mode, varop, orig_count) 8845 rtx x; 8846 enum rtx_code code; 8847 enum machine_mode result_mode; 8848 rtx varop; 8849 int orig_count; 8850{ 8851 enum rtx_code orig_code = code; 8852 unsigned int count; 8853 int signed_count; 8854 enum machine_mode mode = result_mode; 8855 enum machine_mode shift_mode, tmode; 8856 unsigned int mode_words 8857 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; 8858 /* We form (outer_op (code varop count) (outer_const)). */ 8859 enum rtx_code outer_op = NIL; 8860 HOST_WIDE_INT outer_const = 0; 8861 rtx const_rtx; 8862 int complement_p = 0; 8863 rtx new; 8864 8865 /* Make sure and truncate the "natural" shift on the way in. We don't 8866 want to do this inside the loop as it makes it more difficult to 8867 combine shifts. */ 8868#ifdef SHIFT_COUNT_TRUNCATED 8869 if (SHIFT_COUNT_TRUNCATED) 8870 orig_count &= GET_MODE_BITSIZE (mode) - 1; 8871#endif 8872 8873 /* If we were given an invalid count, don't do anything except exactly 8874 what was requested. */ 8875 8876 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode)) 8877 { 8878 if (x) 8879 return x; 8880 8881 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count)); 8882 } 8883 8884 count = orig_count; 8885 8886 /* Unless one of the branches of the `if' in this loop does a `continue', 8887 we will `break' the loop after the `if'. */ 8888 8889 while (count != 0) 8890 { 8891 /* If we have an operand of (clobber (const_int 0)), just return that 8892 value. */ 8893 if (GET_CODE (varop) == CLOBBER) 8894 return varop; 8895 8896 /* If we discovered we had to complement VAROP, leave. Making a NOT 8897 here would cause an infinite loop. */ 8898 if (complement_p) 8899 break; 8900 8901 /* Convert ROTATERT to ROTATE. */ 8902 if (code == ROTATERT) 8903 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count; 8904 8905 /* We need to determine what mode we will do the shift in. If the 8906 shift is a right shift or a ROTATE, we must always do it in the mode 8907 it was originally done in. Otherwise, we can do it in MODE, the 8908 widest mode encountered. */ 8909 shift_mode 8910 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE 8911 ? result_mode : mode); 8912 8913 /* Handle cases where the count is greater than the size of the mode 8914 minus 1. For ASHIFT, use the size minus one as the count (this can 8915 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, 8916 take the count modulo the size. For other shifts, the result is 8917 zero. 8918 8919 Since these shifts are being produced by the compiler by combining 8920 multiple operations, each of which are defined, we know what the 8921 result is supposed to be. */ 8922 8923 if (count > GET_MODE_BITSIZE (shift_mode) - 1) 8924 { 8925 if (code == ASHIFTRT) 8926 count = GET_MODE_BITSIZE (shift_mode) - 1; 8927 else if (code == ROTATE || code == ROTATERT) 8928 count %= GET_MODE_BITSIZE (shift_mode); 8929 else 8930 { 8931 /* We can't simply return zero because there may be an 8932 outer op. */ 8933 varop = const0_rtx; 8934 count = 0; 8935 break; 8936 } 8937 } 8938 8939 /* An arithmetic right shift of a quantity known to be -1 or 0 8940 is a no-op. */ 8941 if (code == ASHIFTRT 8942 && (num_sign_bit_copies (varop, shift_mode) 8943 == GET_MODE_BITSIZE (shift_mode))) 8944 { 8945 count = 0; 8946 break; 8947 } 8948 8949 /* If we are doing an arithmetic right shift and discarding all but 8950 the sign bit copies, this is equivalent to doing a shift by the 8951 bitsize minus one. Convert it into that shift because it will often 8952 allow other simplifications. */ 8953 8954 if (code == ASHIFTRT 8955 && (count + num_sign_bit_copies (varop, shift_mode) 8956 >= GET_MODE_BITSIZE (shift_mode))) 8957 count = GET_MODE_BITSIZE (shift_mode) - 1; 8958 8959 /* We simplify the tests below and elsewhere by converting 8960 ASHIFTRT to LSHIFTRT if we know the sign bit is clear. 8961 `make_compound_operation' will convert it to a ASHIFTRT for 8962 those machines (such as VAX) that don't have a LSHIFTRT. */ 8963 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT 8964 && code == ASHIFTRT 8965 && ((nonzero_bits (varop, shift_mode) 8966 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1))) 8967 == 0)) 8968 code = LSHIFTRT; 8969 8970 switch (GET_CODE (varop)) 8971 { 8972 case SIGN_EXTEND: 8973 case ZERO_EXTEND: 8974 case SIGN_EXTRACT: 8975 case ZERO_EXTRACT: 8976 new = expand_compound_operation (varop); 8977 if (new != varop) 8978 { 8979 varop = new; 8980 continue; 8981 } 8982 break; 8983 8984 case MEM: 8985 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH 8986 minus the width of a smaller mode, we can do this with a 8987 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ 8988 if ((code == ASHIFTRT || code == LSHIFTRT) 8989 && ! mode_dependent_address_p (XEXP (varop, 0)) 8990 && ! MEM_VOLATILE_P (varop) 8991 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 8992 MODE_INT, 1)) != BLKmode) 8993 { 8994 new = adjust_address_nv (varop, tmode, 8995 BYTES_BIG_ENDIAN ? 0 8996 : count / BITS_PER_UNIT); 8997 8998 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND 8999 : ZERO_EXTEND, mode, new); 9000 count = 0; 9001 continue; 9002 } 9003 break; 9004 9005 case USE: 9006 /* Similar to the case above, except that we can only do this if 9007 the resulting mode is the same as that of the underlying 9008 MEM and adjust the address depending on the *bits* endianness 9009 because of the way that bit-field extract insns are defined. */ 9010 if ((code == ASHIFTRT || code == LSHIFTRT) 9011 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 9012 MODE_INT, 1)) != BLKmode 9013 && tmode == GET_MODE (XEXP (varop, 0))) 9014 { 9015 if (BITS_BIG_ENDIAN) 9016 new = XEXP (varop, 0); 9017 else 9018 { 9019 new = copy_rtx (XEXP (varop, 0)); 9020 SUBST (XEXP (new, 0), 9021 plus_constant (XEXP (new, 0), 9022 count / BITS_PER_UNIT)); 9023 } 9024 9025 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND 9026 : ZERO_EXTEND, mode, new); 9027 count = 0; 9028 continue; 9029 } 9030 break; 9031 9032 case SUBREG: 9033 /* If VAROP is a SUBREG, strip it as long as the inner operand has 9034 the same number of words as what we've seen so far. Then store 9035 the widest mode in MODE. */ 9036 if (subreg_lowpart_p (varop) 9037 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 9038 > GET_MODE_SIZE (GET_MODE (varop))) 9039 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 9040 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 9041 == mode_words)) 9042 { 9043 varop = SUBREG_REG (varop); 9044 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) 9045 mode = GET_MODE (varop); 9046 continue; 9047 } 9048 break; 9049 9050 case MULT: 9051 /* Some machines use MULT instead of ASHIFT because MULT 9052 is cheaper. But it is still better on those machines to 9053 merge two shifts into one. */ 9054 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 9055 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) 9056 { 9057 varop 9058 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0), 9059 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1))))); 9060 continue; 9061 } 9062 break; 9063 9064 case UDIV: 9065 /* Similar, for when divides are cheaper. */ 9066 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 9067 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) 9068 { 9069 varop 9070 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0), 9071 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1))))); 9072 continue; 9073 } 9074 break; 9075 9076 case ASHIFTRT: 9077 /* If we are extracting just the sign bit of an arithmetic 9078 right shift, that shift is not needed. However, the sign 9079 bit of a wider mode may be different from what would be 9080 interpreted as the sign bit in a narrower mode, so, if 9081 the result is narrower, don't discard the shift. */ 9082 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 9083 && (GET_MODE_BITSIZE (result_mode) 9084 >= GET_MODE_BITSIZE (GET_MODE (varop)))) 9085 { 9086 varop = XEXP (varop, 0); 9087 continue; 9088 } 9089 9090 /* ... fall through ... */ 9091 9092 case LSHIFTRT: 9093 case ASHIFT: 9094 case ROTATE: 9095 /* Here we have two nested shifts. The result is usually the 9096 AND of a new shift with a mask. We compute the result below. */ 9097 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 9098 && INTVAL (XEXP (varop, 1)) >= 0 9099 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop)) 9100 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 9101 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 9102 { 9103 enum rtx_code first_code = GET_CODE (varop); 9104 unsigned int first_count = INTVAL (XEXP (varop, 1)); 9105 unsigned HOST_WIDE_INT mask; 9106 rtx mask_rtx; 9107 9108 /* We have one common special case. We can't do any merging if 9109 the inner code is an ASHIFTRT of a smaller mode. However, if 9110 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) 9111 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), 9112 we can convert it to 9113 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1). 9114 This simplifies certain SIGN_EXTEND operations. */ 9115 if (code == ASHIFT && first_code == ASHIFTRT 9116 && (GET_MODE_BITSIZE (result_mode) 9117 - GET_MODE_BITSIZE (GET_MODE (varop))) == count) 9118 { 9119 /* C3 has the low-order C1 bits zero. */ 9120 9121 mask = (GET_MODE_MASK (mode) 9122 & ~(((HOST_WIDE_INT) 1 << first_count) - 1)); 9123 9124 varop = simplify_and_const_int (NULL_RTX, result_mode, 9125 XEXP (varop, 0), mask); 9126 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, 9127 varop, count); 9128 count = first_count; 9129 code = ASHIFTRT; 9130 continue; 9131 } 9132 9133 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more 9134 than C1 high-order bits equal to the sign bit, we can convert 9135 this to either an ASHIFT or a ASHIFTRT depending on the 9136 two counts. 9137 9138 We cannot do this if VAROP's mode is not SHIFT_MODE. */ 9139 9140 if (code == ASHIFTRT && first_code == ASHIFT 9141 && GET_MODE (varop) == shift_mode 9142 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) 9143 > first_count)) 9144 { 9145 varop = XEXP (varop, 0); 9146 9147 signed_count = count - first_count; 9148 if (signed_count < 0) 9149 count = -signed_count, code = ASHIFT; 9150 else 9151 count = signed_count; 9152 9153 continue; 9154 } 9155 9156 /* There are some cases we can't do. If CODE is ASHIFTRT, 9157 we can only do this if FIRST_CODE is also ASHIFTRT. 9158 9159 We can't do the case when CODE is ROTATE and FIRST_CODE is 9160 ASHIFTRT. 9161 9162 If the mode of this shift is not the mode of the outer shift, 9163 we can't do this if either shift is a right shift or ROTATE. 9164 9165 Finally, we can't do any of these if the mode is too wide 9166 unless the codes are the same. 9167 9168 Handle the case where the shift codes are the same 9169 first. */ 9170 9171 if (code == first_code) 9172 { 9173 if (GET_MODE (varop) != result_mode 9174 && (code == ASHIFTRT || code == LSHIFTRT 9175 || code == ROTATE)) 9176 break; 9177 9178 count += first_count; 9179 varop = XEXP (varop, 0); 9180 continue; 9181 } 9182 9183 if (code == ASHIFTRT 9184 || (code == ROTATE && first_code == ASHIFTRT) 9185 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 9186 || (GET_MODE (varop) != result_mode 9187 && (first_code == ASHIFTRT || first_code == LSHIFTRT 9188 || first_code == ROTATE 9189 || code == ROTATE))) 9190 break; 9191 9192 /* To compute the mask to apply after the shift, shift the 9193 nonzero bits of the inner shift the same way the 9194 outer shift will. */ 9195 9196 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop))); 9197 9198 mask_rtx 9199 = simplify_binary_operation (code, result_mode, mask_rtx, 9200 GEN_INT (count)); 9201 9202 /* Give up if we can't compute an outer operation to use. */ 9203 if (mask_rtx == 0 9204 || GET_CODE (mask_rtx) != CONST_INT 9205 || ! merge_outer_ops (&outer_op, &outer_const, AND, 9206 INTVAL (mask_rtx), 9207 result_mode, &complement_p)) 9208 break; 9209 9210 /* If the shifts are in the same direction, we add the 9211 counts. Otherwise, we subtract them. */ 9212 signed_count = count; 9213 if ((code == ASHIFTRT || code == LSHIFTRT) 9214 == (first_code == ASHIFTRT || first_code == LSHIFTRT)) 9215 signed_count += first_count; 9216 else 9217 signed_count -= first_count; 9218 9219 /* If COUNT is positive, the new shift is usually CODE, 9220 except for the two exceptions below, in which case it is 9221 FIRST_CODE. If the count is negative, FIRST_CODE should 9222 always be used */ 9223 if (signed_count > 0 9224 && ((first_code == ROTATE && code == ASHIFT) 9225 || (first_code == ASHIFTRT && code == LSHIFTRT))) 9226 code = first_code, count = signed_count; 9227 else if (signed_count < 0) 9228 code = first_code, count = -signed_count; 9229 else 9230 count = signed_count; 9231 9232 varop = XEXP (varop, 0); 9233 continue; 9234 } 9235 9236 /* If we have (A << B << C) for any shift, we can convert this to 9237 (A << C << B). This wins if A is a constant. Only try this if 9238 B is not a constant. */ 9239 9240 else if (GET_CODE (varop) == code 9241 && GET_CODE (XEXP (varop, 1)) != CONST_INT 9242 && 0 != (new 9243 = simplify_binary_operation (code, mode, 9244 XEXP (varop, 0), 9245 GEN_INT (count)))) 9246 { 9247 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1)); 9248 count = 0; 9249 continue; 9250 } 9251 break; 9252 9253 case NOT: 9254 /* Make this fit the case below. */ 9255 varop = gen_rtx_XOR (mode, XEXP (varop, 0), 9256 GEN_INT (GET_MODE_MASK (mode))); 9257 continue; 9258 9259 case IOR: 9260 case AND: 9261 case XOR: 9262 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) 9263 with C the size of VAROP - 1 and the shift is logical if 9264 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 9265 we have an (le X 0) operation. If we have an arithmetic shift 9266 and STORE_FLAG_VALUE is 1 or we have a logical shift with 9267 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ 9268 9269 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS 9270 && XEXP (XEXP (varop, 0), 1) == constm1_rtx 9271 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 9272 && (code == LSHIFTRT || code == ASHIFTRT) 9273 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 9274 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 9275 { 9276 count = 0; 9277 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1), 9278 const0_rtx); 9279 9280 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 9281 varop = gen_rtx_NEG (GET_MODE (varop), varop); 9282 9283 continue; 9284 } 9285 9286 /* If we have (shift (logical)), move the logical to the outside 9287 to allow it to possibly combine with another logical and the 9288 shift to combine with another shift. This also canonicalizes to 9289 what a ZERO_EXTRACT looks like. Also, some machines have 9290 (and (shift)) insns. */ 9291 9292 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 9293 && (new = simplify_binary_operation (code, result_mode, 9294 XEXP (varop, 1), 9295 GEN_INT (count))) != 0 9296 && GET_CODE (new) == CONST_INT 9297 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), 9298 INTVAL (new), result_mode, &complement_p)) 9299 { 9300 varop = XEXP (varop, 0); 9301 continue; 9302 } 9303 9304 /* If we can't do that, try to simplify the shift in each arm of the 9305 logical expression, make a new logical expression, and apply 9306 the inverse distributive law. */ 9307 { 9308 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, 9309 XEXP (varop, 0), count); 9310 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, 9311 XEXP (varop, 1), count); 9312 9313 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs); 9314 varop = apply_distributive_law (varop); 9315 9316 count = 0; 9317 } 9318 break; 9319 9320 case EQ: 9321 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE 9322 says that the sign bit can be tested, FOO has mode MODE, C is 9323 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit 9324 that may be nonzero. */ 9325 if (code == LSHIFTRT 9326 && XEXP (varop, 1) == const0_rtx 9327 && GET_MODE (XEXP (varop, 0)) == result_mode 9328 && count == GET_MODE_BITSIZE (result_mode) - 1 9329 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 9330 && ((STORE_FLAG_VALUE 9331 & ((HOST_WIDE_INT) 1 9332 < (GET_MODE_BITSIZE (result_mode) - 1)))) 9333 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 9334 && merge_outer_ops (&outer_op, &outer_const, XOR, 9335 (HOST_WIDE_INT) 1, result_mode, 9336 &complement_p)) 9337 { 9338 varop = XEXP (varop, 0); 9339 count = 0; 9340 continue; 9341 } 9342 break; 9343 9344 case NEG: 9345 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less 9346 than the number of bits in the mode is equivalent to A. */ 9347 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 9348 && nonzero_bits (XEXP (varop, 0), result_mode) == 1) 9349 { 9350 varop = XEXP (varop, 0); 9351 count = 0; 9352 continue; 9353 } 9354 9355 /* NEG commutes with ASHIFT since it is multiplication. Move the 9356 NEG outside to allow shifts to combine. */ 9357 if (code == ASHIFT 9358 && merge_outer_ops (&outer_op, &outer_const, NEG, 9359 (HOST_WIDE_INT) 0, result_mode, 9360 &complement_p)) 9361 { 9362 varop = XEXP (varop, 0); 9363 continue; 9364 } 9365 break; 9366 9367 case PLUS: 9368 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C 9369 is one less than the number of bits in the mode is 9370 equivalent to (xor A 1). */ 9371 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 9372 && XEXP (varop, 1) == constm1_rtx 9373 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 9374 && merge_outer_ops (&outer_op, &outer_const, XOR, 9375 (HOST_WIDE_INT) 1, result_mode, 9376 &complement_p)) 9377 { 9378 count = 0; 9379 varop = XEXP (varop, 0); 9380 continue; 9381 } 9382 9383 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits 9384 that might be nonzero in BAR are those being shifted out and those 9385 bits are known zero in FOO, we can replace the PLUS with FOO. 9386 Similarly in the other operand order. This code occurs when 9387 we are computing the size of a variable-size array. */ 9388 9389 if ((code == ASHIFTRT || code == LSHIFTRT) 9390 && count < HOST_BITS_PER_WIDE_INT 9391 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 9392 && (nonzero_bits (XEXP (varop, 1), result_mode) 9393 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) 9394 { 9395 varop = XEXP (varop, 0); 9396 continue; 9397 } 9398 else if ((code == ASHIFTRT || code == LSHIFTRT) 9399 && count < HOST_BITS_PER_WIDE_INT 9400 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 9401 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 9402 >> count) 9403 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 9404 & nonzero_bits (XEXP (varop, 1), 9405 result_mode))) 9406 { 9407 varop = XEXP (varop, 1); 9408 continue; 9409 } 9410 9411 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ 9412 if (code == ASHIFT 9413 && GET_CODE (XEXP (varop, 1)) == CONST_INT 9414 && (new = simplify_binary_operation (ASHIFT, result_mode, 9415 XEXP (varop, 1), 9416 GEN_INT (count))) != 0 9417 && GET_CODE (new) == CONST_INT 9418 && merge_outer_ops (&outer_op, &outer_const, PLUS, 9419 INTVAL (new), result_mode, &complement_p)) 9420 { 9421 varop = XEXP (varop, 0); 9422 continue; 9423 } 9424 break; 9425 9426 case MINUS: 9427 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) 9428 with C the size of VAROP - 1 and the shift is logical if 9429 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 9430 we have a (gt X 0) operation. If the shift is arithmetic with 9431 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, 9432 we have a (neg (gt X 0)) operation. */ 9433 9434 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 9435 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT 9436 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 9437 && (code == LSHIFTRT || code == ASHIFTRT) 9438 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT 9439 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count 9440 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 9441 { 9442 count = 0; 9443 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1), 9444 const0_rtx); 9445 9446 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 9447 varop = gen_rtx_NEG (GET_MODE (varop), varop); 9448 9449 continue; 9450 } 9451 break; 9452 9453 case TRUNCATE: 9454 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) 9455 if the truncate does not affect the value. */ 9456 if (code == LSHIFTRT 9457 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT 9458 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT 9459 && (INTVAL (XEXP (XEXP (varop, 0), 1)) 9460 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0))) 9461 - GET_MODE_BITSIZE (GET_MODE (varop))))) 9462 { 9463 rtx varop_inner = XEXP (varop, 0); 9464 9465 varop_inner 9466 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner), 9467 XEXP (varop_inner, 0), 9468 GEN_INT 9469 (count + INTVAL (XEXP (varop_inner, 1)))); 9470 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner); 9471 count = 0; 9472 continue; 9473 } 9474 break; 9475 9476 default: 9477 break; 9478 } 9479 9480 break; 9481 } 9482 9483 /* We need to determine what mode to do the shift in. If the shift is 9484 a right shift or ROTATE, we must always do it in the mode it was 9485 originally done in. Otherwise, we can do it in MODE, the widest mode 9486 encountered. The code we care about is that of the shift that will 9487 actually be done, not the shift that was originally requested. */ 9488 shift_mode 9489 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE 9490 ? result_mode : mode); 9491 9492 /* We have now finished analyzing the shift. The result should be 9493 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If 9494 OUTER_OP is non-NIL, it is an operation that needs to be applied 9495 to the result of the shift. OUTER_CONST is the relevant constant, 9496 but we must turn off all bits turned off in the shift. 9497 9498 If we were passed a value for X, see if we can use any pieces of 9499 it. If not, make new rtx. */ 9500 9501 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2' 9502 && GET_CODE (XEXP (x, 1)) == CONST_INT 9503 && INTVAL (XEXP (x, 1)) == count) 9504 const_rtx = XEXP (x, 1); 9505 else 9506 const_rtx = GEN_INT (count); 9507 9508 if (x && GET_CODE (XEXP (x, 0)) == SUBREG 9509 && GET_MODE (XEXP (x, 0)) == shift_mode 9510 && SUBREG_REG (XEXP (x, 0)) == varop) 9511 varop = XEXP (x, 0); 9512 else if (GET_MODE (varop) != shift_mode) 9513 varop = gen_lowpart_for_combine (shift_mode, varop); 9514 9515 /* If we can't make the SUBREG, try to return what we were given. */ 9516 if (GET_CODE (varop) == CLOBBER) 9517 return x ? x : varop; 9518 9519 new = simplify_binary_operation (code, shift_mode, varop, const_rtx); 9520 if (new != 0) 9521 x = new; 9522 else 9523 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx); 9524 9525 /* If we have an outer operation and we just made a shift, it is 9526 possible that we could have simplified the shift were it not 9527 for the outer operation. So try to do the simplification 9528 recursively. */ 9529 9530 if (outer_op != NIL && GET_CODE (x) == code 9531 && GET_CODE (XEXP (x, 1)) == CONST_INT) 9532 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0), 9533 INTVAL (XEXP (x, 1))); 9534 9535 /* If we were doing a LSHIFTRT in a wider mode than it was originally, 9536 turn off all the bits that the shift would have turned off. */ 9537 if (orig_code == LSHIFTRT && result_mode != shift_mode) 9538 x = simplify_and_const_int (NULL_RTX, shift_mode, x, 9539 GET_MODE_MASK (result_mode) >> orig_count); 9540 9541 /* Do the remainder of the processing in RESULT_MODE. */ 9542 x = gen_lowpart_for_combine (result_mode, x); 9543 9544 /* If COMPLEMENT_P is set, we have to complement X before doing the outer 9545 operation. */ 9546 if (complement_p) 9547 x =simplify_gen_unary (NOT, result_mode, x, result_mode); 9548 9549 if (outer_op != NIL) 9550 { 9551 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT) 9552 outer_const = trunc_int_for_mode (outer_const, result_mode); 9553 9554 if (outer_op == AND) 9555 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); 9556 else if (outer_op == SET) 9557 /* This means that we have determined that the result is 9558 equivalent to a constant. This should be rare. */ 9559 x = GEN_INT (outer_const); 9560 else if (GET_RTX_CLASS (outer_op) == '1') 9561 x = simplify_gen_unary (outer_op, result_mode, x, result_mode); 9562 else 9563 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const)); 9564 } 9565 9566 return x; 9567} 9568 9569/* Like recog, but we receive the address of a pointer to a new pattern. 9570 We try to match the rtx that the pointer points to. 9571 If that fails, we may try to modify or replace the pattern, 9572 storing the replacement into the same pointer object. 9573 9574 Modifications include deletion or addition of CLOBBERs. 9575 9576 PNOTES is a pointer to a location where any REG_UNUSED notes added for 9577 the CLOBBERs are placed. 9578 9579 The value is the final insn code from the pattern ultimately matched, 9580 or -1. */ 9581 9582static int 9583recog_for_combine (pnewpat, insn, pnotes) 9584 rtx *pnewpat; 9585 rtx insn; 9586 rtx *pnotes; 9587{ 9588 rtx pat = *pnewpat; 9589 int insn_code_number; 9590 int num_clobbers_to_add = 0; 9591 int i; 9592 rtx notes = 0; 9593 rtx old_notes; 9594 9595 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER 9596 we use to indicate that something didn't match. If we find such a 9597 thing, force rejection. */ 9598 if (GET_CODE (pat) == PARALLEL) 9599 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) 9600 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER 9601 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) 9602 return -1; 9603 9604 /* Remove the old notes prior to trying to recognize the new pattern. */ 9605 old_notes = REG_NOTES (insn); 9606 REG_NOTES (insn) = 0; 9607 9608 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 9609 9610 /* If it isn't, there is the possibility that we previously had an insn 9611 that clobbered some register as a side effect, but the combined 9612 insn doesn't need to do that. So try once more without the clobbers 9613 unless this represents an ASM insn. */ 9614 9615 if (insn_code_number < 0 && ! check_asm_operands (pat) 9616 && GET_CODE (pat) == PARALLEL) 9617 { 9618 int pos; 9619 9620 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) 9621 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) 9622 { 9623 if (i != pos) 9624 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); 9625 pos++; 9626 } 9627 9628 SUBST_INT (XVECLEN (pat, 0), pos); 9629 9630 if (pos == 1) 9631 pat = XVECEXP (pat, 0, 0); 9632 9633 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 9634 } 9635 9636 /* Recognize all noop sets, these will be killed by followup pass. */ 9637 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat)) 9638 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0; 9639 9640 REG_NOTES (insn) = old_notes; 9641 9642 /* If we had any clobbers to add, make a new pattern than contains 9643 them. Then check to make sure that all of them are dead. */ 9644 if (num_clobbers_to_add) 9645 { 9646 rtx newpat = gen_rtx_PARALLEL (VOIDmode, 9647 rtvec_alloc (GET_CODE (pat) == PARALLEL 9648 ? (XVECLEN (pat, 0) 9649 + num_clobbers_to_add) 9650 : num_clobbers_to_add + 1)); 9651 9652 if (GET_CODE (pat) == PARALLEL) 9653 for (i = 0; i < XVECLEN (pat, 0); i++) 9654 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); 9655 else 9656 XVECEXP (newpat, 0, 0) = pat; 9657 9658 add_clobbers (newpat, insn_code_number); 9659 9660 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; 9661 i < XVECLEN (newpat, 0); i++) 9662 { 9663 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG 9664 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) 9665 return -1; 9666 notes = gen_rtx_EXPR_LIST (REG_UNUSED, 9667 XEXP (XVECEXP (newpat, 0, i), 0), notes); 9668 } 9669 pat = newpat; 9670 } 9671 9672 *pnewpat = pat; 9673 *pnotes = notes; 9674 9675 return insn_code_number; 9676} 9677 9678/* Like gen_lowpart but for use by combine. In combine it is not possible 9679 to create any new pseudoregs. However, it is safe to create 9680 invalid memory addresses, because combine will try to recognize 9681 them and all they will do is make the combine attempt fail. 9682 9683 If for some reason this cannot do its job, an rtx 9684 (clobber (const_int 0)) is returned. 9685 An insn containing that will not be recognized. */ 9686 9687#undef gen_lowpart 9688 9689static rtx 9690gen_lowpart_for_combine (mode, x) 9691 enum machine_mode mode; 9692 rtx x; 9693{ 9694 rtx result; 9695 9696 if (GET_MODE (x) == mode) 9697 return x; 9698 9699 /* We can only support MODE being wider than a word if X is a 9700 constant integer or has a mode the same size. */ 9701 9702 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 9703 && ! ((GET_MODE (x) == VOIDmode 9704 && (GET_CODE (x) == CONST_INT 9705 || GET_CODE (x) == CONST_DOUBLE)) 9706 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode))) 9707 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 9708 9709 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart 9710 won't know what to do. So we will strip off the SUBREG here and 9711 process normally. */ 9712 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM) 9713 { 9714 x = SUBREG_REG (x); 9715 if (GET_MODE (x) == mode) 9716 return x; 9717 } 9718 9719 result = gen_lowpart_common (mode, x); 9720#ifdef CLASS_CANNOT_CHANGE_MODE 9721 if (result != 0 9722 && GET_CODE (result) == SUBREG 9723 && GET_CODE (SUBREG_REG (result)) == REG 9724 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER 9725 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result), 9726 GET_MODE (SUBREG_REG (result)))) 9727 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1; 9728#endif 9729 9730 if (result) 9731 return result; 9732 9733 if (GET_CODE (x) == MEM) 9734 { 9735 int offset = 0; 9736 9737 /* Refuse to work on a volatile memory ref or one with a mode-dependent 9738 address. */ 9739 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0))) 9740 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 9741 9742 /* If we want to refer to something bigger than the original memref, 9743 generate a perverse subreg instead. That will force a reload 9744 of the original memref X. */ 9745 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)) 9746 return gen_rtx_SUBREG (mode, x, 0); 9747 9748 if (WORDS_BIG_ENDIAN) 9749 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) 9750 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); 9751 9752 if (BYTES_BIG_ENDIAN) 9753 { 9754 /* Adjust the address so that the address-after-the-data is 9755 unchanged. */ 9756 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) 9757 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); 9758 } 9759 9760 return adjust_address_nv (x, mode, offset); 9761 } 9762 9763 /* If X is a comparison operator, rewrite it in a new mode. This 9764 probably won't match, but may allow further simplifications. */ 9765 else if (GET_RTX_CLASS (GET_CODE (x)) == '<') 9766 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1)); 9767 9768 /* If we couldn't simplify X any other way, just enclose it in a 9769 SUBREG. Normally, this SUBREG won't match, but some patterns may 9770 include an explicit SUBREG or we may simplify it further in combine. */ 9771 else 9772 { 9773 int offset = 0; 9774 rtx res; 9775 9776 offset = subreg_lowpart_offset (mode, GET_MODE (x)); 9777 res = simplify_gen_subreg (mode, x, GET_MODE (x), offset); 9778 if (res) 9779 return res; 9780 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 9781 } 9782} 9783 9784/* These routines make binary and unary operations by first seeing if they 9785 fold; if not, a new expression is allocated. */ 9786 9787static rtx 9788gen_binary (code, mode, op0, op1) 9789 enum rtx_code code; 9790 enum machine_mode mode; 9791 rtx op0, op1; 9792{ 9793 rtx result; 9794 rtx tem; 9795 9796 if (GET_RTX_CLASS (code) == 'c' 9797 && swap_commutative_operands_p (op0, op1)) 9798 tem = op0, op0 = op1, op1 = tem; 9799 9800 if (GET_RTX_CLASS (code) == '<') 9801 { 9802 enum machine_mode op_mode = GET_MODE (op0); 9803 9804 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get 9805 just (REL_OP X Y). */ 9806 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx) 9807 { 9808 op1 = XEXP (op0, 1); 9809 op0 = XEXP (op0, 0); 9810 op_mode = GET_MODE (op0); 9811 } 9812 9813 if (op_mode == VOIDmode) 9814 op_mode = GET_MODE (op1); 9815 result = simplify_relational_operation (code, op_mode, op0, op1); 9816 } 9817 else 9818 result = simplify_binary_operation (code, mode, op0, op1); 9819 9820 if (result) 9821 return result; 9822 9823 /* Put complex operands first and constants second. */ 9824 if (GET_RTX_CLASS (code) == 'c' 9825 && swap_commutative_operands_p (op0, op1)) 9826 return gen_rtx_fmt_ee (code, mode, op1, op0); 9827 9828 /* If we are turning off bits already known off in OP0, we need not do 9829 an AND. */ 9830 else if (code == AND && GET_CODE (op1) == CONST_INT 9831 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 9832 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0) 9833 return op0; 9834 9835 return gen_rtx_fmt_ee (code, mode, op0, op1); 9836} 9837 9838/* Simplify a comparison between *POP0 and *POP1 where CODE is the 9839 comparison code that will be tested. 9840 9841 The result is a possibly different comparison code to use. *POP0 and 9842 *POP1 may be updated. 9843 9844 It is possible that we might detect that a comparison is either always 9845 true or always false. However, we do not perform general constant 9846 folding in combine, so this knowledge isn't useful. Such tautologies 9847 should have been detected earlier. Hence we ignore all such cases. */ 9848 9849static enum rtx_code 9850simplify_comparison (code, pop0, pop1) 9851 enum rtx_code code; 9852 rtx *pop0; 9853 rtx *pop1; 9854{ 9855 rtx op0 = *pop0; 9856 rtx op1 = *pop1; 9857 rtx tem, tem1; 9858 int i; 9859 enum machine_mode mode, tmode; 9860 9861 /* Try a few ways of applying the same transformation to both operands. */ 9862 while (1) 9863 { 9864#ifndef WORD_REGISTER_OPERATIONS 9865 /* The test below this one won't handle SIGN_EXTENDs on these machines, 9866 so check specially. */ 9867 if (code != GTU && code != GEU && code != LTU && code != LEU 9868 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT 9869 && GET_CODE (XEXP (op0, 0)) == ASHIFT 9870 && GET_CODE (XEXP (op1, 0)) == ASHIFT 9871 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG 9872 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG 9873 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) 9874 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) 9875 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9876 && GET_CODE (XEXP (op1, 1)) == CONST_INT 9877 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 9878 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT 9879 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1)) 9880 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1)) 9881 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1)) 9882 && (INTVAL (XEXP (op0, 1)) 9883 == (GET_MODE_BITSIZE (GET_MODE (op0)) 9884 - (GET_MODE_BITSIZE 9885 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) 9886 { 9887 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); 9888 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); 9889 } 9890#endif 9891 9892 /* If both operands are the same constant shift, see if we can ignore the 9893 shift. We can if the shift is a rotate or if the bits shifted out of 9894 this shift are known to be zero for both inputs and if the type of 9895 comparison is compatible with the shift. */ 9896 if (GET_CODE (op0) == GET_CODE (op1) 9897 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 9898 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) 9899 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) 9900 && (code != GT && code != LT && code != GE && code != LE)) 9901 || (GET_CODE (op0) == ASHIFTRT 9902 && (code != GTU && code != LTU 9903 && code != GEU && code != LEU))) 9904 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9905 && INTVAL (XEXP (op0, 1)) >= 0 9906 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 9907 && XEXP (op0, 1) == XEXP (op1, 1)) 9908 { 9909 enum machine_mode mode = GET_MODE (op0); 9910 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 9911 int shift_count = INTVAL (XEXP (op0, 1)); 9912 9913 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) 9914 mask &= (mask >> shift_count) << shift_count; 9915 else if (GET_CODE (op0) == ASHIFT) 9916 mask = (mask & (mask << shift_count)) >> shift_count; 9917 9918 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0 9919 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0) 9920 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); 9921 else 9922 break; 9923 } 9924 9925 /* If both operands are AND's of a paradoxical SUBREG by constant, the 9926 SUBREGs are of the same mode, and, in both cases, the AND would 9927 be redundant if the comparison was done in the narrower mode, 9928 do the comparison in the narrower mode (e.g., we are AND'ing with 1 9929 and the operand's possibly nonzero bits are 0xffffff01; in that case 9930 if we only care about QImode, we don't need the AND). This case 9931 occurs if the output mode of an scc insn is not SImode and 9932 STORE_FLAG_VALUE == 1 (e.g., the 386). 9933 9934 Similarly, check for a case where the AND's are ZERO_EXTEND 9935 operations from some narrower mode even though a SUBREG is not 9936 present. */ 9937 9938 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND 9939 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9940 && GET_CODE (XEXP (op1, 1)) == CONST_INT) 9941 { 9942 rtx inner_op0 = XEXP (op0, 0); 9943 rtx inner_op1 = XEXP (op1, 0); 9944 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); 9945 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); 9946 int changed = 0; 9947 9948 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG 9949 && (GET_MODE_SIZE (GET_MODE (inner_op0)) 9950 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0)))) 9951 && (GET_MODE (SUBREG_REG (inner_op0)) 9952 == GET_MODE (SUBREG_REG (inner_op1))) 9953 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0))) 9954 <= HOST_BITS_PER_WIDE_INT) 9955 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), 9956 GET_MODE (SUBREG_REG (inner_op0))))) 9957 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), 9958 GET_MODE (SUBREG_REG (inner_op1)))))) 9959 { 9960 op0 = SUBREG_REG (inner_op0); 9961 op1 = SUBREG_REG (inner_op1); 9962 9963 /* The resulting comparison is always unsigned since we masked 9964 off the original sign bit. */ 9965 code = unsigned_condition (code); 9966 9967 changed = 1; 9968 } 9969 9970 else if (c0 == c1) 9971 for (tmode = GET_CLASS_NARROWEST_MODE 9972 (GET_MODE_CLASS (GET_MODE (op0))); 9973 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) 9974 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) 9975 { 9976 op0 = gen_lowpart_for_combine (tmode, inner_op0); 9977 op1 = gen_lowpart_for_combine (tmode, inner_op1); 9978 code = unsigned_condition (code); 9979 changed = 1; 9980 break; 9981 } 9982 9983 if (! changed) 9984 break; 9985 } 9986 9987 /* If both operands are NOT, we can strip off the outer operation 9988 and adjust the comparison code for swapped operands; similarly for 9989 NEG, except that this must be an equality comparison. */ 9990 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) 9991 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG 9992 && (code == EQ || code == NE))) 9993 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); 9994 9995 else 9996 break; 9997 } 9998 9999 /* If the first operand is a constant, swap the operands and adjust the 10000 comparison code appropriately, but don't do this if the second operand 10001 is already a constant integer. */ 10002 if (swap_commutative_operands_p (op0, op1)) 10003 { 10004 tem = op0, op0 = op1, op1 = tem; 10005 code = swap_condition (code); 10006 } 10007 10008 /* We now enter a loop during which we will try to simplify the comparison. 10009 For the most part, we only are concerned with comparisons with zero, 10010 but some things may really be comparisons with zero but not start 10011 out looking that way. */ 10012 10013 while (GET_CODE (op1) == CONST_INT) 10014 { 10015 enum machine_mode mode = GET_MODE (op0); 10016 unsigned int mode_width = GET_MODE_BITSIZE (mode); 10017 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 10018 int equality_comparison_p; 10019 int sign_bit_comparison_p; 10020 int unsigned_comparison_p; 10021 HOST_WIDE_INT const_op; 10022 10023 /* We only want to handle integral modes. This catches VOIDmode, 10024 CCmode, and the floating-point modes. An exception is that we 10025 can handle VOIDmode if OP0 is a COMPARE or a comparison 10026 operation. */ 10027 10028 if (GET_MODE_CLASS (mode) != MODE_INT 10029 && ! (mode == VOIDmode 10030 && (GET_CODE (op0) == COMPARE 10031 || GET_RTX_CLASS (GET_CODE (op0)) == '<'))) 10032 break; 10033 10034 /* Get the constant we are comparing against and turn off all bits 10035 not on in our mode. */ 10036 const_op = trunc_int_for_mode (INTVAL (op1), mode); 10037 op1 = GEN_INT (const_op); 10038 10039 /* If we are comparing against a constant power of two and the value 10040 being compared can only have that single bit nonzero (e.g., it was 10041 `and'ed with that bit), we can replace this with a comparison 10042 with zero. */ 10043 if (const_op 10044 && (code == EQ || code == NE || code == GE || code == GEU 10045 || code == LT || code == LTU) 10046 && mode_width <= HOST_BITS_PER_WIDE_INT 10047 && exact_log2 (const_op) >= 0 10048 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op) 10049 { 10050 code = (code == EQ || code == GE || code == GEU ? NE : EQ); 10051 op1 = const0_rtx, const_op = 0; 10052 } 10053 10054 /* Similarly, if we are comparing a value known to be either -1 or 10055 0 with -1, change it to the opposite comparison against zero. */ 10056 10057 if (const_op == -1 10058 && (code == EQ || code == NE || code == GT || code == LE 10059 || code == GEU || code == LTU) 10060 && num_sign_bit_copies (op0, mode) == mode_width) 10061 { 10062 code = (code == EQ || code == LE || code == GEU ? NE : EQ); 10063 op1 = const0_rtx, const_op = 0; 10064 } 10065 10066 /* Do some canonicalizations based on the comparison code. We prefer 10067 comparisons against zero and then prefer equality comparisons. 10068 If we can reduce the size of a constant, we will do that too. */ 10069 10070 switch (code) 10071 { 10072 case LT: 10073 /* < C is equivalent to <= (C - 1) */ 10074 if (const_op > 0) 10075 { 10076 const_op -= 1; 10077 op1 = GEN_INT (const_op); 10078 code = LE; 10079 /* ... fall through to LE case below. */ 10080 } 10081 else 10082 break; 10083 10084 case LE: 10085 /* <= C is equivalent to < (C + 1); we do this for C < 0 */ 10086 if (const_op < 0) 10087 { 10088 const_op += 1; 10089 op1 = GEN_INT (const_op); 10090 code = LT; 10091 } 10092 10093 /* If we are doing a <= 0 comparison on a value known to have 10094 a zero sign bit, we can replace this with == 0. */ 10095 else if (const_op == 0 10096 && mode_width <= HOST_BITS_PER_WIDE_INT 10097 && (nonzero_bits (op0, mode) 10098 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) 10099 code = EQ; 10100 break; 10101 10102 case GE: 10103 /* >= C is equivalent to > (C - 1). */ 10104 if (const_op > 0) 10105 { 10106 const_op -= 1; 10107 op1 = GEN_INT (const_op); 10108 code = GT; 10109 /* ... fall through to GT below. */ 10110 } 10111 else 10112 break; 10113 10114 case GT: 10115 /* > C is equivalent to >= (C + 1); we do this for C < 0. */ 10116 if (const_op < 0) 10117 { 10118 const_op += 1; 10119 op1 = GEN_INT (const_op); 10120 code = GE; 10121 } 10122 10123 /* If we are doing a > 0 comparison on a value known to have 10124 a zero sign bit, we can replace this with != 0. */ 10125 else if (const_op == 0 10126 && mode_width <= HOST_BITS_PER_WIDE_INT 10127 && (nonzero_bits (op0, mode) 10128 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) 10129 code = NE; 10130 break; 10131 10132 case LTU: 10133 /* < C is equivalent to <= (C - 1). */ 10134 if (const_op > 0) 10135 { 10136 const_op -= 1; 10137 op1 = GEN_INT (const_op); 10138 code = LEU; 10139 /* ... fall through ... */ 10140 } 10141 10142 /* (unsigned) < 0x80000000 is equivalent to >= 0. */ 10143 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 10144 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) 10145 { 10146 const_op = 0, op1 = const0_rtx; 10147 code = GE; 10148 break; 10149 } 10150 else 10151 break; 10152 10153 case LEU: 10154 /* unsigned <= 0 is equivalent to == 0 */ 10155 if (const_op == 0) 10156 code = EQ; 10157 10158 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ 10159 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 10160 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) 10161 { 10162 const_op = 0, op1 = const0_rtx; 10163 code = GE; 10164 } 10165 break; 10166 10167 case GEU: 10168 /* >= C is equivalent to < (C - 1). */ 10169 if (const_op > 1) 10170 { 10171 const_op -= 1; 10172 op1 = GEN_INT (const_op); 10173 code = GTU; 10174 /* ... fall through ... */ 10175 } 10176 10177 /* (unsigned) >= 0x80000000 is equivalent to < 0. */ 10178 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 10179 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) 10180 { 10181 const_op = 0, op1 = const0_rtx; 10182 code = LT; 10183 break; 10184 } 10185 else 10186 break; 10187 10188 case GTU: 10189 /* unsigned > 0 is equivalent to != 0 */ 10190 if (const_op == 0) 10191 code = NE; 10192 10193 /* (unsigned) > 0x7fffffff is equivalent to < 0. */ 10194 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 10195 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) 10196 { 10197 const_op = 0, op1 = const0_rtx; 10198 code = LT; 10199 } 10200 break; 10201 10202 default: 10203 break; 10204 } 10205 10206 /* Compute some predicates to simplify code below. */ 10207 10208 equality_comparison_p = (code == EQ || code == NE); 10209 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); 10210 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU 10211 || code == GEU); 10212 10213 /* If this is a sign bit comparison and we can do arithmetic in 10214 MODE, say that we will only be needing the sign bit of OP0. */ 10215 if (sign_bit_comparison_p 10216 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 10217 op0 = force_to_mode (op0, mode, 10218 ((HOST_WIDE_INT) 1 10219 << (GET_MODE_BITSIZE (mode) - 1)), 10220 NULL_RTX, 0); 10221 10222 /* Now try cases based on the opcode of OP0. If none of the cases 10223 does a "continue", we exit this loop immediately after the 10224 switch. */ 10225 10226 switch (GET_CODE (op0)) 10227 { 10228 case ZERO_EXTRACT: 10229 /* If we are extracting a single bit from a variable position in 10230 a constant that has only a single bit set and are comparing it 10231 with zero, we can convert this into an equality comparison 10232 between the position and the location of the single bit. */ 10233 10234 if (GET_CODE (XEXP (op0, 0)) == CONST_INT 10235 && XEXP (op0, 1) == const1_rtx 10236 && equality_comparison_p && const_op == 0 10237 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0) 10238 { 10239 if (BITS_BIG_ENDIAN) 10240 { 10241 enum machine_mode new_mode 10242 = mode_for_extraction (EP_extzv, 1); 10243 if (new_mode == MAX_MACHINE_MODE) 10244 i = BITS_PER_WORD - 1 - i; 10245 else 10246 { 10247 mode = new_mode; 10248 i = (GET_MODE_BITSIZE (mode) - 1 - i); 10249 } 10250 } 10251 10252 op0 = XEXP (op0, 2); 10253 op1 = GEN_INT (i); 10254 const_op = i; 10255 10256 /* Result is nonzero iff shift count is equal to I. */ 10257 code = reverse_condition (code); 10258 continue; 10259 } 10260 10261 /* ... fall through ... */ 10262 10263 case SIGN_EXTRACT: 10264 tem = expand_compound_operation (op0); 10265 if (tem != op0) 10266 { 10267 op0 = tem; 10268 continue; 10269 } 10270 break; 10271 10272 case NOT: 10273 /* If testing for equality, we can take the NOT of the constant. */ 10274 if (equality_comparison_p 10275 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) 10276 { 10277 op0 = XEXP (op0, 0); 10278 op1 = tem; 10279 continue; 10280 } 10281 10282 /* If just looking at the sign bit, reverse the sense of the 10283 comparison. */ 10284 if (sign_bit_comparison_p) 10285 { 10286 op0 = XEXP (op0, 0); 10287 code = (code == GE ? LT : GE); 10288 continue; 10289 } 10290 break; 10291 10292 case NEG: 10293 /* If testing for equality, we can take the NEG of the constant. */ 10294 if (equality_comparison_p 10295 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) 10296 { 10297 op0 = XEXP (op0, 0); 10298 op1 = tem; 10299 continue; 10300 } 10301 10302 /* The remaining cases only apply to comparisons with zero. */ 10303 if (const_op != 0) 10304 break; 10305 10306 /* When X is ABS or is known positive, 10307 (neg X) is < 0 if and only if X != 0. */ 10308 10309 if (sign_bit_comparison_p 10310 && (GET_CODE (XEXP (op0, 0)) == ABS 10311 || (mode_width <= HOST_BITS_PER_WIDE_INT 10312 && (nonzero_bits (XEXP (op0, 0), mode) 10313 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0))) 10314 { 10315 op0 = XEXP (op0, 0); 10316 code = (code == LT ? NE : EQ); 10317 continue; 10318 } 10319 10320 /* If we have NEG of something whose two high-order bits are the 10321 same, we know that "(-a) < 0" is equivalent to "a > 0". */ 10322 if (num_sign_bit_copies (op0, mode) >= 2) 10323 { 10324 op0 = XEXP (op0, 0); 10325 code = swap_condition (code); 10326 continue; 10327 } 10328 break; 10329 10330 case ROTATE: 10331 /* If we are testing equality and our count is a constant, we 10332 can perform the inverse operation on our RHS. */ 10333 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT 10334 && (tem = simplify_binary_operation (ROTATERT, mode, 10335 op1, XEXP (op0, 1))) != 0) 10336 { 10337 op0 = XEXP (op0, 0); 10338 op1 = tem; 10339 continue; 10340 } 10341 10342 /* If we are doing a < 0 or >= 0 comparison, it means we are testing 10343 a particular bit. Convert it to an AND of a constant of that 10344 bit. This will be converted into a ZERO_EXTRACT. */ 10345 if (const_op == 0 && sign_bit_comparison_p 10346 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10347 && mode_width <= HOST_BITS_PER_WIDE_INT) 10348 { 10349 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10350 ((HOST_WIDE_INT) 1 10351 << (mode_width - 1 10352 - INTVAL (XEXP (op0, 1))))); 10353 code = (code == LT ? NE : EQ); 10354 continue; 10355 } 10356 10357 /* Fall through. */ 10358 10359 case ABS: 10360 /* ABS is ignorable inside an equality comparison with zero. */ 10361 if (const_op == 0 && equality_comparison_p) 10362 { 10363 op0 = XEXP (op0, 0); 10364 continue; 10365 } 10366 break; 10367 10368 case SIGN_EXTEND: 10369 /* Can simplify (compare (zero/sign_extend FOO) CONST) 10370 to (compare FOO CONST) if CONST fits in FOO's mode and we 10371 are either testing inequality or have an unsigned comparison 10372 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */ 10373 if (! unsigned_comparison_p 10374 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) 10375 <= HOST_BITS_PER_WIDE_INT) 10376 && ((unsigned HOST_WIDE_INT) const_op 10377 < (((unsigned HOST_WIDE_INT) 1 10378 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1))))) 10379 { 10380 op0 = XEXP (op0, 0); 10381 continue; 10382 } 10383 break; 10384 10385 case SUBREG: 10386 /* Check for the case where we are comparing A - C1 with C2, 10387 both constants are smaller than 1/2 the maximum positive 10388 value in MODE, and the comparison is equality or unsigned. 10389 In that case, if A is either zero-extended to MODE or has 10390 sufficient sign bits so that the high-order bit in MODE 10391 is a copy of the sign in the inner mode, we can prove that it is 10392 safe to do the operation in the wider mode. This simplifies 10393 many range checks. */ 10394 10395 if (mode_width <= HOST_BITS_PER_WIDE_INT 10396 && subreg_lowpart_p (op0) 10397 && GET_CODE (SUBREG_REG (op0)) == PLUS 10398 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT 10399 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0 10400 && (-INTVAL (XEXP (SUBREG_REG (op0), 1)) 10401 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2)) 10402 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2 10403 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0), 10404 GET_MODE (SUBREG_REG (op0))) 10405 & ~GET_MODE_MASK (mode)) 10406 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0), 10407 GET_MODE (SUBREG_REG (op0))) 10408 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) 10409 - GET_MODE_BITSIZE (mode))))) 10410 { 10411 op0 = SUBREG_REG (op0); 10412 continue; 10413 } 10414 10415 /* If the inner mode is narrower and we are extracting the low part, 10416 we can treat the SUBREG as if it were a ZERO_EXTEND. */ 10417 if (subreg_lowpart_p (op0) 10418 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width) 10419 /* Fall through */ ; 10420 else 10421 break; 10422 10423 /* ... fall through ... */ 10424 10425 case ZERO_EXTEND: 10426 if ((unsigned_comparison_p || equality_comparison_p) 10427 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) 10428 <= HOST_BITS_PER_WIDE_INT) 10429 && ((unsigned HOST_WIDE_INT) const_op 10430 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0))))) 10431 { 10432 op0 = XEXP (op0, 0); 10433 continue; 10434 } 10435 break; 10436 10437 case PLUS: 10438 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do 10439 this for equality comparisons due to pathological cases involving 10440 overflows. */ 10441 if (equality_comparison_p 10442 && 0 != (tem = simplify_binary_operation (MINUS, mode, 10443 op1, XEXP (op0, 1)))) 10444 { 10445 op0 = XEXP (op0, 0); 10446 op1 = tem; 10447 continue; 10448 } 10449 10450 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ 10451 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx 10452 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) 10453 { 10454 op0 = XEXP (XEXP (op0, 0), 0); 10455 code = (code == LT ? EQ : NE); 10456 continue; 10457 } 10458 break; 10459 10460 case MINUS: 10461 /* We used to optimize signed comparisons against zero, but that 10462 was incorrect. Unsigned comparisons against zero (GTU, LEU) 10463 arrive here as equality comparisons, or (GEU, LTU) are 10464 optimized away. No need to special-case them. */ 10465 10466 /* (eq (minus A B) C) -> (eq A (plus B C)) or 10467 (eq B (minus A C)), whichever simplifies. We can only do 10468 this for equality comparisons due to pathological cases involving 10469 overflows. */ 10470 if (equality_comparison_p 10471 && 0 != (tem = simplify_binary_operation (PLUS, mode, 10472 XEXP (op0, 1), op1))) 10473 { 10474 op0 = XEXP (op0, 0); 10475 op1 = tem; 10476 continue; 10477 } 10478 10479 if (equality_comparison_p 10480 && 0 != (tem = simplify_binary_operation (MINUS, mode, 10481 XEXP (op0, 0), op1))) 10482 { 10483 op0 = XEXP (op0, 1); 10484 op1 = tem; 10485 continue; 10486 } 10487 10488 /* The sign bit of (minus (ashiftrt X C) X), where C is the number 10489 of bits in X minus 1, is one iff X > 0. */ 10490 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT 10491 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10492 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1 10493 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 10494 { 10495 op0 = XEXP (op0, 1); 10496 code = (code == GE ? LE : GT); 10497 continue; 10498 } 10499 break; 10500 10501 case XOR: 10502 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification 10503 if C is zero or B is a constant. */ 10504 if (equality_comparison_p 10505 && 0 != (tem = simplify_binary_operation (XOR, mode, 10506 XEXP (op0, 1), op1))) 10507 { 10508 op0 = XEXP (op0, 0); 10509 op1 = tem; 10510 continue; 10511 } 10512 break; 10513 10514 case EQ: case NE: 10515 case UNEQ: case LTGT: 10516 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE: 10517 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE: 10518 case UNORDERED: case ORDERED: 10519 /* We can't do anything if OP0 is a condition code value, rather 10520 than an actual data value. */ 10521 if (const_op != 0 10522#ifdef HAVE_cc0 10523 || XEXP (op0, 0) == cc0_rtx 10524#endif 10525 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) 10526 break; 10527 10528 /* Get the two operands being compared. */ 10529 if (GET_CODE (XEXP (op0, 0)) == COMPARE) 10530 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); 10531 else 10532 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); 10533 10534 /* Check for the cases where we simply want the result of the 10535 earlier test or the opposite of that result. */ 10536 if (code == NE || code == EQ 10537 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 10538 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10539 && (STORE_FLAG_VALUE 10540 & (((HOST_WIDE_INT) 1 10541 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) 10542 && (code == LT || code == GE))) 10543 { 10544 enum rtx_code new_code; 10545 if (code == LT || code == NE) 10546 new_code = GET_CODE (op0); 10547 else 10548 new_code = combine_reversed_comparison_code (op0); 10549 10550 if (new_code != UNKNOWN) 10551 { 10552 code = new_code; 10553 op0 = tem; 10554 op1 = tem1; 10555 continue; 10556 } 10557 } 10558 break; 10559 10560 case IOR: 10561 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero 10562 iff X <= 0. */ 10563 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS 10564 && XEXP (XEXP (op0, 0), 1) == constm1_rtx 10565 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 10566 { 10567 op0 = XEXP (op0, 1); 10568 code = (code == GE ? GT : LE); 10569 continue; 10570 } 10571 break; 10572 10573 case AND: 10574 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This 10575 will be converted to a ZERO_EXTRACT later. */ 10576 if (const_op == 0 && equality_comparison_p 10577 && GET_CODE (XEXP (op0, 0)) == ASHIFT 10578 && XEXP (XEXP (op0, 0), 0) == const1_rtx) 10579 { 10580 op0 = simplify_and_const_int 10581 (op0, mode, gen_rtx_LSHIFTRT (mode, 10582 XEXP (op0, 1), 10583 XEXP (XEXP (op0, 0), 1)), 10584 (HOST_WIDE_INT) 1); 10585 continue; 10586 } 10587 10588 /* If we are comparing (and (lshiftrt X C1) C2) for equality with 10589 zero and X is a comparison and C1 and C2 describe only bits set 10590 in STORE_FLAG_VALUE, we can compare with X. */ 10591 if (const_op == 0 && equality_comparison_p 10592 && mode_width <= HOST_BITS_PER_WIDE_INT 10593 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10594 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT 10595 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10596 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 10597 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) 10598 { 10599 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 10600 << INTVAL (XEXP (XEXP (op0, 0), 1))); 10601 if ((~STORE_FLAG_VALUE & mask) == 0 10602 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<' 10603 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 10604 && GET_RTX_CLASS (GET_CODE (tem)) == '<'))) 10605 { 10606 op0 = XEXP (XEXP (op0, 0), 0); 10607 continue; 10608 } 10609 } 10610 10611 /* If we are doing an equality comparison of an AND of a bit equal 10612 to the sign bit, replace this with a LT or GE comparison of 10613 the underlying value. */ 10614 if (equality_comparison_p 10615 && const_op == 0 10616 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10617 && mode_width <= HOST_BITS_PER_WIDE_INT 10618 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 10619 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) 10620 { 10621 op0 = XEXP (op0, 0); 10622 code = (code == EQ ? GE : LT); 10623 continue; 10624 } 10625 10626 /* If this AND operation is really a ZERO_EXTEND from a narrower 10627 mode, the constant fits within that mode, and this is either an 10628 equality or unsigned comparison, try to do this comparison in 10629 the narrower mode. */ 10630 if ((equality_comparison_p || unsigned_comparison_p) 10631 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10632 && (i = exact_log2 ((INTVAL (XEXP (op0, 1)) 10633 & GET_MODE_MASK (mode)) 10634 + 1)) >= 0 10635 && const_op >> i == 0 10636 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode) 10637 { 10638 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0)); 10639 continue; 10640 } 10641 10642 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits 10643 in both M1 and M2 and the SUBREG is either paradoxical or 10644 represents the low part, permute the SUBREG and the AND and 10645 try again. */ 10646 if (GET_CODE (XEXP (op0, 0)) == SUBREG 10647 && (0 10648#ifdef WORD_REGISTER_OPERATIONS 10649 || ((mode_width 10650 > (GET_MODE_BITSIZE 10651 (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))) 10652 && mode_width <= BITS_PER_WORD) 10653#endif 10654 || ((mode_width 10655 <= (GET_MODE_BITSIZE 10656 (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))) 10657 && subreg_lowpart_p (XEXP (op0, 0)))) 10658#ifndef WORD_REGISTER_OPERATIONS 10659 /* It is unsafe to commute the AND into the SUBREG if the SUBREG 10660 is paradoxical and WORD_REGISTER_OPERATIONS is not defined. 10661 As originally written the upper bits have a defined value 10662 due to the AND operation. However, if we commute the AND 10663 inside the SUBREG then they no longer have defined values 10664 and the meaning of the code has been changed. */ 10665 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) 10666 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))) 10667#endif 10668 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10669 && mode_width <= HOST_BITS_PER_WIDE_INT 10670 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))) 10671 <= HOST_BITS_PER_WIDE_INT) 10672 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0 10673 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0)))) 10674 & INTVAL (XEXP (op0, 1))) 10675 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask 10676 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) 10677 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))) 10678 10679 { 10680 op0 10681 = gen_lowpart_for_combine 10682 (mode, 10683 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))), 10684 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1))); 10685 continue; 10686 } 10687 10688 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to 10689 (eq (and (lshiftrt X) 1) 0). */ 10690 if (const_op == 0 && equality_comparison_p 10691 && XEXP (op0, 1) == const1_rtx 10692 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT 10693 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT) 10694 { 10695 op0 = simplify_and_const_int 10696 (op0, mode, 10697 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0), 10698 XEXP (XEXP (op0, 0), 1)), 10699 (HOST_WIDE_INT) 1); 10700 code = (code == NE ? EQ : NE); 10701 continue; 10702 } 10703 break; 10704 10705 case ASHIFT: 10706 /* If we have (compare (ashift FOO N) (const_int C)) and 10707 the high order N bits of FOO (N+1 if an inequality comparison) 10708 are known to be zero, we can do this by comparing FOO with C 10709 shifted right N bits so long as the low-order N bits of C are 10710 zero. */ 10711 if (GET_CODE (XEXP (op0, 1)) == CONST_INT 10712 && INTVAL (XEXP (op0, 1)) >= 0 10713 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) 10714 < HOST_BITS_PER_WIDE_INT) 10715 && ((const_op 10716 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0) 10717 && mode_width <= HOST_BITS_PER_WIDE_INT 10718 && (nonzero_bits (XEXP (op0, 0), mode) 10719 & ~(mask >> (INTVAL (XEXP (op0, 1)) 10720 + ! equality_comparison_p))) == 0) 10721 { 10722 /* We must perform a logical shift, not an arithmetic one, 10723 as we want the top N bits of C to be zero. */ 10724 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode); 10725 10726 temp >>= INTVAL (XEXP (op0, 1)); 10727 op1 = GEN_INT (trunc_int_for_mode (temp, mode)); 10728 op0 = XEXP (op0, 0); 10729 continue; 10730 } 10731 10732 /* If we are doing a sign bit comparison, it means we are testing 10733 a particular bit. Convert it to the appropriate AND. */ 10734 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT 10735 && mode_width <= HOST_BITS_PER_WIDE_INT) 10736 { 10737 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10738 ((HOST_WIDE_INT) 1 10739 << (mode_width - 1 10740 - INTVAL (XEXP (op0, 1))))); 10741 code = (code == LT ? NE : EQ); 10742 continue; 10743 } 10744 10745 /* If this an equality comparison with zero and we are shifting 10746 the low bit to the sign bit, we can convert this to an AND of the 10747 low-order bit. */ 10748 if (const_op == 0 && equality_comparison_p 10749 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10750 && INTVAL (XEXP (op0, 1)) == mode_width - 1) 10751 { 10752 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10753 (HOST_WIDE_INT) 1); 10754 continue; 10755 } 10756 break; 10757 10758 case ASHIFTRT: 10759 /* If this is an equality comparison with zero, we can do this 10760 as a logical shift, which might be much simpler. */ 10761 if (equality_comparison_p && const_op == 0 10762 && GET_CODE (XEXP (op0, 1)) == CONST_INT) 10763 { 10764 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, 10765 XEXP (op0, 0), 10766 INTVAL (XEXP (op0, 1))); 10767 continue; 10768 } 10769 10770 /* If OP0 is a sign extension and CODE is not an unsigned comparison, 10771 do the comparison in a narrower mode. */ 10772 if (! unsigned_comparison_p 10773 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10774 && GET_CODE (XEXP (op0, 0)) == ASHIFT 10775 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 10776 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 10777 MODE_INT, 1)) != BLKmode 10778 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode) 10779 || ((unsigned HOST_WIDE_INT) -const_op 10780 <= GET_MODE_MASK (tmode)))) 10781 { 10782 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0)); 10783 continue; 10784 } 10785 10786 /* Likewise if OP0 is a PLUS of a sign extension with a 10787 constant, which is usually represented with the PLUS 10788 between the shifts. */ 10789 if (! unsigned_comparison_p 10790 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10791 && GET_CODE (XEXP (op0, 0)) == PLUS 10792 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10793 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT 10794 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1) 10795 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 10796 MODE_INT, 1)) != BLKmode 10797 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode) 10798 || ((unsigned HOST_WIDE_INT) -const_op 10799 <= GET_MODE_MASK (tmode)))) 10800 { 10801 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0); 10802 rtx add_const = XEXP (XEXP (op0, 0), 1); 10803 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const, 10804 XEXP (op0, 1)); 10805 10806 op0 = gen_binary (PLUS, tmode, 10807 gen_lowpart_for_combine (tmode, inner), 10808 new_const); 10809 continue; 10810 } 10811 10812 /* ... fall through ... */ 10813 case LSHIFTRT: 10814 /* If we have (compare (xshiftrt FOO N) (const_int C)) and 10815 the low order N bits of FOO are known to be zero, we can do this 10816 by comparing FOO with C shifted left N bits so long as no 10817 overflow occurs. */ 10818 if (GET_CODE (XEXP (op0, 1)) == CONST_INT 10819 && INTVAL (XEXP (op0, 1)) >= 0 10820 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 10821 && mode_width <= HOST_BITS_PER_WIDE_INT 10822 && (nonzero_bits (XEXP (op0, 0), mode) 10823 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 10824 && (const_op == 0 10825 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1)) 10826 < mode_width))) 10827 { 10828 const_op <<= INTVAL (XEXP (op0, 1)); 10829 op1 = GEN_INT (const_op); 10830 op0 = XEXP (op0, 0); 10831 continue; 10832 } 10833 10834 /* If we are using this shift to extract just the sign bit, we 10835 can replace this with an LT or GE comparison. */ 10836 if (const_op == 0 10837 && (equality_comparison_p || sign_bit_comparison_p) 10838 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10839 && INTVAL (XEXP (op0, 1)) == mode_width - 1) 10840 { 10841 op0 = XEXP (op0, 0); 10842 code = (code == NE || code == GT ? LT : GE); 10843 continue; 10844 } 10845 break; 10846 10847 default: 10848 break; 10849 } 10850 10851 break; 10852 } 10853 10854 /* Now make any compound operations involved in this comparison. Then, 10855 check for an outmost SUBREG on OP0 that is not doing anything or is 10856 paradoxical. The latter case can only occur when it is known that the 10857 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG. 10858 We can never remove a SUBREG for a non-equality comparison because the 10859 sign bit is in a different place in the underlying object. */ 10860 10861 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); 10862 op1 = make_compound_operation (op1, SET); 10863 10864 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 10865 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10866 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT 10867 && (code == NE || code == EQ) 10868 && ((GET_MODE_SIZE (GET_MODE (op0)) 10869 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))) 10870 { 10871 op0 = SUBREG_REG (op0); 10872 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1); 10873 } 10874 10875 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 10876 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10877 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT 10878 && (code == NE || code == EQ) 10879 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) 10880 <= HOST_BITS_PER_WIDE_INT) 10881 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0))) 10882 & ~GET_MODE_MASK (GET_MODE (op0))) == 0 10883 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), 10884 op1), 10885 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) 10886 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)) 10887 op0 = SUBREG_REG (op0), op1 = tem; 10888 10889 /* We now do the opposite procedure: Some machines don't have compare 10890 insns in all modes. If OP0's mode is an integer mode smaller than a 10891 word and we can't do a compare in that mode, see if there is a larger 10892 mode for which we can do the compare. There are a number of cases in 10893 which we can use the wider mode. */ 10894 10895 mode = GET_MODE (op0); 10896 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT 10897 && GET_MODE_SIZE (mode) < UNITS_PER_WORD 10898 && ! have_insn_for (COMPARE, mode)) 10899 for (tmode = GET_MODE_WIDER_MODE (mode); 10900 (tmode != VOIDmode 10901 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT); 10902 tmode = GET_MODE_WIDER_MODE (tmode)) 10903 if (have_insn_for (COMPARE, tmode)) 10904 { 10905 /* If the only nonzero bits in OP0 and OP1 are those in the 10906 narrower mode and this is an equality or unsigned comparison, 10907 we can use the wider mode. Similarly for sign-extended 10908 values, in which case it is true for all comparisons. */ 10909 if (((code == EQ || code == NE 10910 || code == GEU || code == GTU || code == LEU || code == LTU) 10911 && (nonzero_bits (op0, tmode) & ~GET_MODE_MASK (mode)) == 0 10912 && (nonzero_bits (op1, tmode) & ~GET_MODE_MASK (mode)) == 0) 10913 || ((num_sign_bit_copies (op0, tmode) 10914 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode)) 10915 && (num_sign_bit_copies (op1, tmode) 10916 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode)))) 10917 { 10918 /* If OP0 is an AND and we don't have an AND in MODE either, 10919 make a new AND in the proper mode. */ 10920 if (GET_CODE (op0) == AND 10921 && !have_insn_for (AND, mode)) 10922 op0 = gen_binary (AND, tmode, 10923 gen_lowpart_for_combine (tmode, 10924 XEXP (op0, 0)), 10925 gen_lowpart_for_combine (tmode, 10926 XEXP (op0, 1))); 10927 10928 op0 = gen_lowpart_for_combine (tmode, op0); 10929 op1 = gen_lowpart_for_combine (tmode, op1); 10930 break; 10931 } 10932 10933 /* If this is a test for negative, we can make an explicit 10934 test of the sign bit. */ 10935 10936 if (op1 == const0_rtx && (code == LT || code == GE) 10937 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 10938 { 10939 op0 = gen_binary (AND, tmode, 10940 gen_lowpart_for_combine (tmode, op0), 10941 GEN_INT ((HOST_WIDE_INT) 1 10942 << (GET_MODE_BITSIZE (mode) - 1))); 10943 code = (code == LT) ? NE : EQ; 10944 break; 10945 } 10946 } 10947 10948#ifdef CANONICALIZE_COMPARISON 10949 /* If this machine only supports a subset of valid comparisons, see if we 10950 can convert an unsupported one into a supported one. */ 10951 CANONICALIZE_COMPARISON (code, op0, op1); 10952#endif 10953 10954 *pop0 = op0; 10955 *pop1 = op1; 10956 10957 return code; 10958} 10959 10960/* Like jump.c' reversed_comparison_code, but use combine infrastructure for 10961 searching backward. */ 10962static enum rtx_code 10963combine_reversed_comparison_code (exp) 10964 rtx exp; 10965{ 10966 enum rtx_code code1 = reversed_comparison_code (exp, NULL); 10967 rtx x; 10968 10969 if (code1 != UNKNOWN 10970 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC) 10971 return code1; 10972 /* Otherwise try and find where the condition codes were last set and 10973 use that. */ 10974 x = get_last_value (XEXP (exp, 0)); 10975 if (!x || GET_CODE (x) != COMPARE) 10976 return UNKNOWN; 10977 return reversed_comparison_code_parts (GET_CODE (exp), 10978 XEXP (x, 0), XEXP (x, 1), NULL); 10979} 10980/* Return comparison with reversed code of EXP and operands OP0 and OP1. 10981 Return NULL_RTX in case we fail to do the reversal. */ 10982static rtx 10983reversed_comparison (exp, mode, op0, op1) 10984 rtx exp, op0, op1; 10985 enum machine_mode mode; 10986{ 10987 enum rtx_code reversed_code = combine_reversed_comparison_code (exp); 10988 if (reversed_code == UNKNOWN) 10989 return NULL_RTX; 10990 else 10991 return gen_binary (reversed_code, mode, op0, op1); 10992} 10993 10994/* Utility function for following routine. Called when X is part of a value 10995 being stored into reg_last_set_value. Sets reg_last_set_table_tick 10996 for each register mentioned. Similar to mention_regs in cse.c */ 10997 10998static void 10999update_table_tick (x) 11000 rtx x; 11001{ 11002 enum rtx_code code = GET_CODE (x); 11003 const char *fmt = GET_RTX_FORMAT (code); 11004 int i; 11005 11006 if (code == REG) 11007 { 11008 unsigned int regno = REGNO (x); 11009 unsigned int endregno 11010 = regno + (regno < FIRST_PSEUDO_REGISTER 11011 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 11012 unsigned int r; 11013 11014 for (r = regno; r < endregno; r++) 11015 reg_last_set_table_tick[r] = label_tick; 11016 11017 return; 11018 } 11019 11020 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 11021 /* Note that we can't have an "E" in values stored; see 11022 get_last_value_validate. */ 11023 if (fmt[i] == 'e') 11024 update_table_tick (XEXP (x, i)); 11025} 11026 11027/* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we 11028 are saying that the register is clobbered and we no longer know its 11029 value. If INSN is zero, don't update reg_last_set; this is only permitted 11030 with VALUE also zero and is used to invalidate the register. */ 11031 11032static void 11033record_value_for_reg (reg, insn, value) 11034 rtx reg; 11035 rtx insn; 11036 rtx value; 11037{ 11038 unsigned int regno = REGNO (reg); 11039 unsigned int endregno 11040 = regno + (regno < FIRST_PSEUDO_REGISTER 11041 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1); 11042 unsigned int i; 11043 11044 /* If VALUE contains REG and we have a previous value for REG, substitute 11045 the previous value. */ 11046 if (value && insn && reg_overlap_mentioned_p (reg, value)) 11047 { 11048 rtx tem; 11049 11050 /* Set things up so get_last_value is allowed to see anything set up to 11051 our insn. */ 11052 subst_low_cuid = INSN_CUID (insn); 11053 tem = get_last_value (reg); 11054 11055 /* If TEM is simply a binary operation with two CLOBBERs as operands, 11056 it isn't going to be useful and will take a lot of time to process, 11057 so just use the CLOBBER. */ 11058 11059 if (tem) 11060 { 11061 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2' 11062 || GET_RTX_CLASS (GET_CODE (tem)) == 'c') 11063 && GET_CODE (XEXP (tem, 0)) == CLOBBER 11064 && GET_CODE (XEXP (tem, 1)) == CLOBBER) 11065 tem = XEXP (tem, 0); 11066 11067 value = replace_rtx (copy_rtx (value), reg, tem); 11068 } 11069 } 11070 11071 /* For each register modified, show we don't know its value, that 11072 we don't know about its bitwise content, that its value has been 11073 updated, and that we don't know the location of the death of the 11074 register. */ 11075 for (i = regno; i < endregno; i++) 11076 { 11077 if (insn) 11078 reg_last_set[i] = insn; 11079 11080 reg_last_set_value[i] = 0; 11081 reg_last_set_mode[i] = 0; 11082 reg_last_set_nonzero_bits[i] = 0; 11083 reg_last_set_sign_bit_copies[i] = 0; 11084 reg_last_death[i] = 0; 11085 } 11086 11087 /* Mark registers that are being referenced in this value. */ 11088 if (value) 11089 update_table_tick (value); 11090 11091 /* Now update the status of each register being set. 11092 If someone is using this register in this block, set this register 11093 to invalid since we will get confused between the two lives in this 11094 basic block. This makes using this register always invalid. In cse, we 11095 scan the table to invalidate all entries using this register, but this 11096 is too much work for us. */ 11097 11098 for (i = regno; i < endregno; i++) 11099 { 11100 reg_last_set_label[i] = label_tick; 11101 if (value && reg_last_set_table_tick[i] == label_tick) 11102 reg_last_set_invalid[i] = 1; 11103 else 11104 reg_last_set_invalid[i] = 0; 11105 } 11106 11107 /* The value being assigned might refer to X (like in "x++;"). In that 11108 case, we must replace it with (clobber (const_int 0)) to prevent 11109 infinite loops. */ 11110 if (value && ! get_last_value_validate (&value, insn, 11111 reg_last_set_label[regno], 0)) 11112 { 11113 value = copy_rtx (value); 11114 if (! get_last_value_validate (&value, insn, 11115 reg_last_set_label[regno], 1)) 11116 value = 0; 11117 } 11118 11119 /* For the main register being modified, update the value, the mode, the 11120 nonzero bits, and the number of sign bit copies. */ 11121 11122 reg_last_set_value[regno] = value; 11123 11124 if (value) 11125 { 11126 subst_low_cuid = INSN_CUID (insn); 11127 reg_last_set_mode[regno] = GET_MODE (reg); 11128 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg)); 11129 reg_last_set_sign_bit_copies[regno] 11130 = num_sign_bit_copies (value, GET_MODE (reg)); 11131 } 11132} 11133 11134/* Called via note_stores from record_dead_and_set_regs to handle one 11135 SET or CLOBBER in an insn. DATA is the instruction in which the 11136 set is occurring. */ 11137 11138static void 11139record_dead_and_set_regs_1 (dest, setter, data) 11140 rtx dest, setter; 11141 void *data; 11142{ 11143 rtx record_dead_insn = (rtx) data; 11144 11145 if (GET_CODE (dest) == SUBREG) 11146 dest = SUBREG_REG (dest); 11147 11148 if (GET_CODE (dest) == REG) 11149 { 11150 /* If we are setting the whole register, we know its value. Otherwise 11151 show that we don't know the value. We can handle SUBREG in 11152 some cases. */ 11153 if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) 11154 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); 11155 else if (GET_CODE (setter) == SET 11156 && GET_CODE (SET_DEST (setter)) == SUBREG 11157 && SUBREG_REG (SET_DEST (setter)) == dest 11158 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD 11159 && subreg_lowpart_p (SET_DEST (setter))) 11160 record_value_for_reg (dest, record_dead_insn, 11161 gen_lowpart_for_combine (GET_MODE (dest), 11162 SET_SRC (setter))); 11163 else 11164 record_value_for_reg (dest, record_dead_insn, NULL_RTX); 11165 } 11166 else if (GET_CODE (dest) == MEM 11167 /* Ignore pushes, they clobber nothing. */ 11168 && ! push_operand (dest, GET_MODE (dest))) 11169 mem_last_set = INSN_CUID (record_dead_insn); 11170} 11171 11172/* Update the records of when each REG was most recently set or killed 11173 for the things done by INSN. This is the last thing done in processing 11174 INSN in the combiner loop. 11175 11176 We update reg_last_set, reg_last_set_value, reg_last_set_mode, 11177 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death, 11178 and also the similar information mem_last_set (which insn most recently 11179 modified memory) and last_call_cuid (which insn was the most recent 11180 subroutine call). */ 11181 11182static void 11183record_dead_and_set_regs (insn) 11184 rtx insn; 11185{ 11186 rtx link; 11187 unsigned int i; 11188 11189 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 11190 { 11191 if (REG_NOTE_KIND (link) == REG_DEAD 11192 && GET_CODE (XEXP (link, 0)) == REG) 11193 { 11194 unsigned int regno = REGNO (XEXP (link, 0)); 11195 unsigned int endregno 11196 = regno + (regno < FIRST_PSEUDO_REGISTER 11197 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0))) 11198 : 1); 11199 11200 for (i = regno; i < endregno; i++) 11201 reg_last_death[i] = insn; 11202 } 11203 else if (REG_NOTE_KIND (link) == REG_INC) 11204 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); 11205 } 11206 11207 if (GET_CODE (insn) == CALL_INSN) 11208 { 11209 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 11210 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i)) 11211 { 11212 reg_last_set_value[i] = 0; 11213 reg_last_set_mode[i] = 0; 11214 reg_last_set_nonzero_bits[i] = 0; 11215 reg_last_set_sign_bit_copies[i] = 0; 11216 reg_last_death[i] = 0; 11217 } 11218 11219 last_call_cuid = mem_last_set = INSN_CUID (insn); 11220 11221 /* Don't bother recording what this insn does. It might set the 11222 return value register, but we can't combine into a call 11223 pattern anyway, so there's no point trying (and it may cause 11224 a crash, if e.g. we wind up asking for last_set_value of a 11225 SUBREG of the return value register). */ 11226 return; 11227 } 11228 11229 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn); 11230} 11231 11232/* If a SUBREG has the promoted bit set, it is in fact a property of the 11233 register present in the SUBREG, so for each such SUBREG go back and 11234 adjust nonzero and sign bit information of the registers that are 11235 known to have some zero/sign bits set. 11236 11237 This is needed because when combine blows the SUBREGs away, the 11238 information on zero/sign bits is lost and further combines can be 11239 missed because of that. */ 11240 11241static void 11242record_promoted_value (insn, subreg) 11243 rtx insn; 11244 rtx subreg; 11245{ 11246 rtx links, set; 11247 unsigned int regno = REGNO (SUBREG_REG (subreg)); 11248 enum machine_mode mode = GET_MODE (subreg); 11249 11250 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) 11251 return; 11252 11253 for (links = LOG_LINKS (insn); links;) 11254 { 11255 insn = XEXP (links, 0); 11256 set = single_set (insn); 11257 11258 if (! set || GET_CODE (SET_DEST (set)) != REG 11259 || REGNO (SET_DEST (set)) != regno 11260 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg))) 11261 { 11262 links = XEXP (links, 1); 11263 continue; 11264 } 11265 11266 if (reg_last_set[regno] == insn) 11267 { 11268 if (SUBREG_PROMOTED_UNSIGNED_P (subreg)) 11269 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode); 11270 } 11271 11272 if (GET_CODE (SET_SRC (set)) == REG) 11273 { 11274 regno = REGNO (SET_SRC (set)); 11275 links = LOG_LINKS (insn); 11276 } 11277 else 11278 break; 11279 } 11280} 11281 11282/* Scan X for promoted SUBREGs. For each one found, 11283 note what it implies to the registers used in it. */ 11284 11285static void 11286check_promoted_subreg (insn, x) 11287 rtx insn; 11288 rtx x; 11289{ 11290 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x) 11291 && GET_CODE (SUBREG_REG (x)) == REG) 11292 record_promoted_value (insn, x); 11293 else 11294 { 11295 const char *format = GET_RTX_FORMAT (GET_CODE (x)); 11296 int i, j; 11297 11298 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) 11299 switch (format[i]) 11300 { 11301 case 'e': 11302 check_promoted_subreg (insn, XEXP (x, i)); 11303 break; 11304 case 'V': 11305 case 'E': 11306 if (XVEC (x, i) != 0) 11307 for (j = 0; j < XVECLEN (x, i); j++) 11308 check_promoted_subreg (insn, XVECEXP (x, i, j)); 11309 break; 11310 } 11311 } 11312} 11313 11314/* Utility routine for the following function. Verify that all the registers 11315 mentioned in *LOC are valid when *LOC was part of a value set when 11316 label_tick == TICK. Return 0 if some are not. 11317 11318 If REPLACE is non-zero, replace the invalid reference with 11319 (clobber (const_int 0)) and return 1. This replacement is useful because 11320 we often can get useful information about the form of a value (e.g., if 11321 it was produced by a shift that always produces -1 or 0) even though 11322 we don't know exactly what registers it was produced from. */ 11323 11324static int 11325get_last_value_validate (loc, insn, tick, replace) 11326 rtx *loc; 11327 rtx insn; 11328 int tick; 11329 int replace; 11330{ 11331 rtx x = *loc; 11332 const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); 11333 int len = GET_RTX_LENGTH (GET_CODE (x)); 11334 int i; 11335 11336 if (GET_CODE (x) == REG) 11337 { 11338 unsigned int regno = REGNO (x); 11339 unsigned int endregno 11340 = regno + (regno < FIRST_PSEUDO_REGISTER 11341 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 11342 unsigned int j; 11343 11344 for (j = regno; j < endregno; j++) 11345 if (reg_last_set_invalid[j] 11346 /* If this is a pseudo-register that was only set once and not 11347 live at the beginning of the function, it is always valid. */ 11348 || (! (regno >= FIRST_PSEUDO_REGISTER 11349 && REG_N_SETS (regno) == 1 11350 && (! REGNO_REG_SET_P 11351 (BASIC_BLOCK (0)->global_live_at_start, regno))) 11352 && reg_last_set_label[j] > tick)) 11353 { 11354 if (replace) 11355 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 11356 return replace; 11357 } 11358 11359 return 1; 11360 } 11361 /* If this is a memory reference, make sure that there were 11362 no stores after it that might have clobbered the value. We don't 11363 have alias info, so we assume any store invalidates it. */ 11364 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x) 11365 && INSN_CUID (insn) <= mem_last_set) 11366 { 11367 if (replace) 11368 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 11369 return replace; 11370 } 11371 11372 for (i = 0; i < len; i++) 11373 if ((fmt[i] == 'e' 11374 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0) 11375 /* Don't bother with these. They shouldn't occur anyway. */ 11376 || fmt[i] == 'E') 11377 return 0; 11378 11379 /* If we haven't found a reason for it to be invalid, it is valid. */ 11380 return 1; 11381} 11382 11383/* Get the last value assigned to X, if known. Some registers 11384 in the value may be replaced with (clobber (const_int 0)) if their value 11385 is known longer known reliably. */ 11386 11387static rtx 11388get_last_value (x) 11389 rtx x; 11390{ 11391 unsigned int regno; 11392 rtx value; 11393 11394 /* If this is a non-paradoxical SUBREG, get the value of its operand and 11395 then convert it to the desired mode. If this is a paradoxical SUBREG, 11396 we cannot predict what values the "extra" bits might have. */ 11397 if (GET_CODE (x) == SUBREG 11398 && subreg_lowpart_p (x) 11399 && (GET_MODE_SIZE (GET_MODE (x)) 11400 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 11401 && (value = get_last_value (SUBREG_REG (x))) != 0) 11402 return gen_lowpart_for_combine (GET_MODE (x), value); 11403 11404 if (GET_CODE (x) != REG) 11405 return 0; 11406 11407 regno = REGNO (x); 11408 value = reg_last_set_value[regno]; 11409 11410 /* If we don't have a value, or if it isn't for this basic block and 11411 it's either a hard register, set more than once, or it's a live 11412 at the beginning of the function, return 0. 11413 11414 Because if it's not live at the beginning of the function then the reg 11415 is always set before being used (is never used without being set). 11416 And, if it's set only once, and it's always set before use, then all 11417 uses must have the same last value, even if it's not from this basic 11418 block. */ 11419 11420 if (value == 0 11421 || (reg_last_set_label[regno] != label_tick 11422 && (regno < FIRST_PSEUDO_REGISTER 11423 || REG_N_SETS (regno) != 1 11424 || (REGNO_REG_SET_P 11425 (BASIC_BLOCK (0)->global_live_at_start, regno))))) 11426 return 0; 11427 11428 /* If the value was set in a later insn than the ones we are processing, 11429 we can't use it even if the register was only set once. */ 11430 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid) 11431 return 0; 11432 11433 /* If the value has all its registers valid, return it. */ 11434 if (get_last_value_validate (&value, reg_last_set[regno], 11435 reg_last_set_label[regno], 0)) 11436 return value; 11437 11438 /* Otherwise, make a copy and replace any invalid register with 11439 (clobber (const_int 0)). If that fails for some reason, return 0. */ 11440 11441 value = copy_rtx (value); 11442 if (get_last_value_validate (&value, reg_last_set[regno], 11443 reg_last_set_label[regno], 1)) 11444 return value; 11445 11446 return 0; 11447} 11448 11449/* Return nonzero if expression X refers to a REG or to memory 11450 that is set in an instruction more recent than FROM_CUID. */ 11451 11452static int 11453use_crosses_set_p (x, from_cuid) 11454 rtx x; 11455 int from_cuid; 11456{ 11457 const char *fmt; 11458 int i; 11459 enum rtx_code code = GET_CODE (x); 11460 11461 if (code == REG) 11462 { 11463 unsigned int regno = REGNO (x); 11464 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER 11465 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 11466 11467#ifdef PUSH_ROUNDING 11468 /* Don't allow uses of the stack pointer to be moved, 11469 because we don't know whether the move crosses a push insn. */ 11470 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS) 11471 return 1; 11472#endif 11473 for (; regno < endreg; regno++) 11474 if (reg_last_set[regno] 11475 && INSN_CUID (reg_last_set[regno]) > from_cuid) 11476 return 1; 11477 return 0; 11478 } 11479 11480 if (code == MEM && mem_last_set > from_cuid) 11481 return 1; 11482 11483 fmt = GET_RTX_FORMAT (code); 11484 11485 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 11486 { 11487 if (fmt[i] == 'E') 11488 { 11489 int j; 11490 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 11491 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid)) 11492 return 1; 11493 } 11494 else if (fmt[i] == 'e' 11495 && use_crosses_set_p (XEXP (x, i), from_cuid)) 11496 return 1; 11497 } 11498 return 0; 11499} 11500 11501/* Define three variables used for communication between the following 11502 routines. */ 11503 11504static unsigned int reg_dead_regno, reg_dead_endregno; 11505static int reg_dead_flag; 11506 11507/* Function called via note_stores from reg_dead_at_p. 11508 11509 If DEST is within [reg_dead_regno, reg_dead_endregno), set 11510 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ 11511 11512static void 11513reg_dead_at_p_1 (dest, x, data) 11514 rtx dest; 11515 rtx x; 11516 void *data ATTRIBUTE_UNUSED; 11517{ 11518 unsigned int regno, endregno; 11519 11520 if (GET_CODE (dest) != REG) 11521 return; 11522 11523 regno = REGNO (dest); 11524 endregno = regno + (regno < FIRST_PSEUDO_REGISTER 11525 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1); 11526 11527 if (reg_dead_endregno > regno && reg_dead_regno < endregno) 11528 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; 11529} 11530 11531/* Return non-zero if REG is known to be dead at INSN. 11532 11533 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER 11534 referencing REG, it is dead. If we hit a SET referencing REG, it is 11535 live. Otherwise, see if it is live or dead at the start of the basic 11536 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS 11537 must be assumed to be always live. */ 11538 11539static int 11540reg_dead_at_p (reg, insn) 11541 rtx reg; 11542 rtx insn; 11543{ 11544 int block; 11545 unsigned int i; 11546 11547 /* Set variables for reg_dead_at_p_1. */ 11548 reg_dead_regno = REGNO (reg); 11549 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER 11550 ? HARD_REGNO_NREGS (reg_dead_regno, 11551 GET_MODE (reg)) 11552 : 1); 11553 11554 reg_dead_flag = 0; 11555 11556 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */ 11557 if (reg_dead_regno < FIRST_PSEUDO_REGISTER) 11558 { 11559 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 11560 if (TEST_HARD_REG_BIT (newpat_used_regs, i)) 11561 return 0; 11562 } 11563 11564 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or 11565 beginning of function. */ 11566 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER; 11567 insn = prev_nonnote_insn (insn)) 11568 { 11569 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL); 11570 if (reg_dead_flag) 11571 return reg_dead_flag == 1 ? 1 : 0; 11572 11573 if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) 11574 return 1; 11575 } 11576 11577 /* Get the basic block number that we were in. */ 11578 if (insn == 0) 11579 block = 0; 11580 else 11581 { 11582 for (block = 0; block < n_basic_blocks; block++) 11583 if (insn == BLOCK_HEAD (block)) 11584 break; 11585 11586 if (block == n_basic_blocks) 11587 return 0; 11588 } 11589 11590 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 11591 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i)) 11592 return 0; 11593 11594 return 1; 11595} 11596 11597/* Note hard registers in X that are used. This code is similar to 11598 that in flow.c, but much simpler since we don't care about pseudos. */ 11599 11600static void 11601mark_used_regs_combine (x) 11602 rtx x; 11603{ 11604 RTX_CODE code = GET_CODE (x); 11605 unsigned int regno; 11606 int i; 11607 11608 switch (code) 11609 { 11610 case LABEL_REF: 11611 case SYMBOL_REF: 11612 case CONST_INT: 11613 case CONST: 11614 case CONST_DOUBLE: 11615 case PC: 11616 case ADDR_VEC: 11617 case ADDR_DIFF_VEC: 11618 case ASM_INPUT: 11619#ifdef HAVE_cc0 11620 /* CC0 must die in the insn after it is set, so we don't need to take 11621 special note of it here. */ 11622 case CC0: 11623#endif 11624 return; 11625 11626 case CLOBBER: 11627 /* If we are clobbering a MEM, mark any hard registers inside the 11628 address as used. */ 11629 if (GET_CODE (XEXP (x, 0)) == MEM) 11630 mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); 11631 return; 11632 11633 case REG: 11634 regno = REGNO (x); 11635 /* A hard reg in a wide mode may really be multiple registers. 11636 If so, mark all of them just like the first. */ 11637 if (regno < FIRST_PSEUDO_REGISTER) 11638 { 11639 unsigned int endregno, r; 11640 11641 /* None of this applies to the stack, frame or arg pointers */ 11642 if (regno == STACK_POINTER_REGNUM 11643#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM 11644 || regno == HARD_FRAME_POINTER_REGNUM 11645#endif 11646#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 11647 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) 11648#endif 11649 || regno == FRAME_POINTER_REGNUM) 11650 return; 11651 11652 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11653 for (r = regno; r < endregno; r++) 11654 SET_HARD_REG_BIT (newpat_used_regs, r); 11655 } 11656 return; 11657 11658 case SET: 11659 { 11660 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in 11661 the address. */ 11662 rtx testreg = SET_DEST (x); 11663 11664 while (GET_CODE (testreg) == SUBREG 11665 || GET_CODE (testreg) == ZERO_EXTRACT 11666 || GET_CODE (testreg) == SIGN_EXTRACT 11667 || GET_CODE (testreg) == STRICT_LOW_PART) 11668 testreg = XEXP (testreg, 0); 11669 11670 if (GET_CODE (testreg) == MEM) 11671 mark_used_regs_combine (XEXP (testreg, 0)); 11672 11673 mark_used_regs_combine (SET_SRC (x)); 11674 } 11675 return; 11676 11677 default: 11678 break; 11679 } 11680 11681 /* Recursively scan the operands of this expression. */ 11682 11683 { 11684 const char *fmt = GET_RTX_FORMAT (code); 11685 11686 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 11687 { 11688 if (fmt[i] == 'e') 11689 mark_used_regs_combine (XEXP (x, i)); 11690 else if (fmt[i] == 'E') 11691 { 11692 int j; 11693 11694 for (j = 0; j < XVECLEN (x, i); j++) 11695 mark_used_regs_combine (XVECEXP (x, i, j)); 11696 } 11697 } 11698 } 11699} 11700 11701/* Remove register number REGNO from the dead registers list of INSN. 11702 11703 Return the note used to record the death, if there was one. */ 11704 11705rtx 11706remove_death (regno, insn) 11707 unsigned int regno; 11708 rtx insn; 11709{ 11710 rtx note = find_regno_note (insn, REG_DEAD, regno); 11711 11712 if (note) 11713 { 11714 REG_N_DEATHS (regno)--; 11715 remove_note (insn, note); 11716 } 11717 11718 return note; 11719} 11720 11721/* For each register (hardware or pseudo) used within expression X, if its 11722 death is in an instruction with cuid between FROM_CUID (inclusive) and 11723 TO_INSN (exclusive), put a REG_DEAD note for that register in the 11724 list headed by PNOTES. 11725 11726 That said, don't move registers killed by maybe_kill_insn. 11727 11728 This is done when X is being merged by combination into TO_INSN. These 11729 notes will then be distributed as needed. */ 11730 11731static void 11732move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes) 11733 rtx x; 11734 rtx maybe_kill_insn; 11735 int from_cuid; 11736 rtx to_insn; 11737 rtx *pnotes; 11738{ 11739 const char *fmt; 11740 int len, i; 11741 enum rtx_code code = GET_CODE (x); 11742 11743 if (code == REG) 11744 { 11745 unsigned int regno = REGNO (x); 11746 rtx where_dead = reg_last_death[regno]; 11747 rtx before_dead, after_dead; 11748 11749 /* Don't move the register if it gets killed in between from and to */ 11750 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) 11751 && ! reg_referenced_p (x, maybe_kill_insn)) 11752 return; 11753 11754 /* WHERE_DEAD could be a USE insn made by combine, so first we 11755 make sure that we have insns with valid INSN_CUID values. */ 11756 before_dead = where_dead; 11757 while (before_dead && INSN_UID (before_dead) > max_uid_cuid) 11758 before_dead = PREV_INSN (before_dead); 11759 11760 after_dead = where_dead; 11761 while (after_dead && INSN_UID (after_dead) > max_uid_cuid) 11762 after_dead = NEXT_INSN (after_dead); 11763 11764 if (before_dead && after_dead 11765 && INSN_CUID (before_dead) >= from_cuid 11766 && (INSN_CUID (after_dead) < INSN_CUID (to_insn) 11767 || (where_dead != after_dead 11768 && INSN_CUID (after_dead) == INSN_CUID (to_insn)))) 11769 { 11770 rtx note = remove_death (regno, where_dead); 11771 11772 /* It is possible for the call above to return 0. This can occur 11773 when reg_last_death points to I2 or I1 that we combined with. 11774 In that case make a new note. 11775 11776 We must also check for the case where X is a hard register 11777 and NOTE is a death note for a range of hard registers 11778 including X. In that case, we must put REG_DEAD notes for 11779 the remaining registers in place of NOTE. */ 11780 11781 if (note != 0 && regno < FIRST_PSEUDO_REGISTER 11782 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 11783 > GET_MODE_SIZE (GET_MODE (x)))) 11784 { 11785 unsigned int deadregno = REGNO (XEXP (note, 0)); 11786 unsigned int deadend 11787 = (deadregno + HARD_REGNO_NREGS (deadregno, 11788 GET_MODE (XEXP (note, 0)))); 11789 unsigned int ourend 11790 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11791 unsigned int i; 11792 11793 for (i = deadregno; i < deadend; i++) 11794 if (i < regno || i >= ourend) 11795 REG_NOTES (where_dead) 11796 = gen_rtx_EXPR_LIST (REG_DEAD, 11797 gen_rtx_REG (reg_raw_mode[i], i), 11798 REG_NOTES (where_dead)); 11799 } 11800 11801 /* If we didn't find any note, or if we found a REG_DEAD note that 11802 covers only part of the given reg, and we have a multi-reg hard 11803 register, then to be safe we must check for REG_DEAD notes 11804 for each register other than the first. They could have 11805 their own REG_DEAD notes lying around. */ 11806 else if ((note == 0 11807 || (note != 0 11808 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 11809 < GET_MODE_SIZE (GET_MODE (x))))) 11810 && regno < FIRST_PSEUDO_REGISTER 11811 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1) 11812 { 11813 unsigned int ourend 11814 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11815 unsigned int i, offset; 11816 rtx oldnotes = 0; 11817 11818 if (note) 11819 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))); 11820 else 11821 offset = 1; 11822 11823 for (i = regno + offset; i < ourend; i++) 11824 move_deaths (gen_rtx_REG (reg_raw_mode[i], i), 11825 maybe_kill_insn, from_cuid, to_insn, &oldnotes); 11826 } 11827 11828 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) 11829 { 11830 XEXP (note, 1) = *pnotes; 11831 *pnotes = note; 11832 } 11833 else 11834 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes); 11835 11836 REG_N_DEATHS (regno)++; 11837 } 11838 11839 return; 11840 } 11841 11842 else if (GET_CODE (x) == SET) 11843 { 11844 rtx dest = SET_DEST (x); 11845 11846 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes); 11847 11848 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG 11849 that accesses one word of a multi-word item, some 11850 piece of everything register in the expression is used by 11851 this insn, so remove any old death. */ 11852 /* ??? So why do we test for equality of the sizes? */ 11853 11854 if (GET_CODE (dest) == ZERO_EXTRACT 11855 || GET_CODE (dest) == STRICT_LOW_PART 11856 || (GET_CODE (dest) == SUBREG 11857 && (((GET_MODE_SIZE (GET_MODE (dest)) 11858 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 11859 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) 11860 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) 11861 { 11862 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes); 11863 return; 11864 } 11865 11866 /* If this is some other SUBREG, we know it replaces the entire 11867 value, so use that as the destination. */ 11868 if (GET_CODE (dest) == SUBREG) 11869 dest = SUBREG_REG (dest); 11870 11871 /* If this is a MEM, adjust deaths of anything used in the address. 11872 For a REG (the only other possibility), the entire value is 11873 being replaced so the old value is not used in this insn. */ 11874 11875 if (GET_CODE (dest) == MEM) 11876 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid, 11877 to_insn, pnotes); 11878 return; 11879 } 11880 11881 else if (GET_CODE (x) == CLOBBER) 11882 return; 11883 11884 len = GET_RTX_LENGTH (code); 11885 fmt = GET_RTX_FORMAT (code); 11886 11887 for (i = 0; i < len; i++) 11888 { 11889 if (fmt[i] == 'E') 11890 { 11891 int j; 11892 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 11893 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid, 11894 to_insn, pnotes); 11895 } 11896 else if (fmt[i] == 'e') 11897 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes); 11898 } 11899} 11900 11901/* Return 1 if X is the target of a bit-field assignment in BODY, the 11902 pattern of an insn. X must be a REG. */ 11903 11904static int 11905reg_bitfield_target_p (x, body) 11906 rtx x; 11907 rtx body; 11908{ 11909 int i; 11910 11911 if (GET_CODE (body) == SET) 11912 { 11913 rtx dest = SET_DEST (body); 11914 rtx target; 11915 unsigned int regno, tregno, endregno, endtregno; 11916 11917 if (GET_CODE (dest) == ZERO_EXTRACT) 11918 target = XEXP (dest, 0); 11919 else if (GET_CODE (dest) == STRICT_LOW_PART) 11920 target = SUBREG_REG (XEXP (dest, 0)); 11921 else 11922 return 0; 11923 11924 if (GET_CODE (target) == SUBREG) 11925 target = SUBREG_REG (target); 11926 11927 if (GET_CODE (target) != REG) 11928 return 0; 11929 11930 tregno = REGNO (target), regno = REGNO (x); 11931 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) 11932 return target == x; 11933 11934 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target)); 11935 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11936 11937 return endregno > tregno && regno < endtregno; 11938 } 11939 11940 else if (GET_CODE (body) == PARALLEL) 11941 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 11942 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) 11943 return 1; 11944 11945 return 0; 11946} 11947 11948/* Given a chain of REG_NOTES originally from FROM_INSN, try to place them 11949 as appropriate. I3 and I2 are the insns resulting from the combination 11950 insns including FROM (I2 may be zero). 11951 11952 ELIM_I2 and ELIM_I1 are either zero or registers that we know will 11953 not need REG_DEAD notes because they are being substituted for. This 11954 saves searching in the most common cases. 11955 11956 Each note in the list is either ignored or placed on some insns, depending 11957 on the type of note. */ 11958 11959static void 11960distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1) 11961 rtx notes; 11962 rtx from_insn; 11963 rtx i3, i2; 11964 rtx elim_i2, elim_i1; 11965{ 11966 rtx note, next_note; 11967 rtx tem; 11968 11969 for (note = notes; note; note = next_note) 11970 { 11971 rtx place = 0, place2 = 0; 11972 11973 /* If this NOTE references a pseudo register, ensure it references 11974 the latest copy of that register. */ 11975 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG 11976 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER) 11977 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))]; 11978 11979 next_note = XEXP (note, 1); 11980 switch (REG_NOTE_KIND (note)) 11981 { 11982 case REG_BR_PROB: 11983 case REG_BR_PRED: 11984 case REG_EXEC_COUNT: 11985 /* Doesn't matter much where we put this, as long as it's somewhere. 11986 It is preferable to keep these notes on branches, which is most 11987 likely to be i3. */ 11988 place = i3; 11989 break; 11990 11991 case REG_VTABLE_REF: 11992 /* ??? Should remain with *a particular* memory load. Given the 11993 nature of vtable data, the last insn seems relatively safe. */ 11994 place = i3; 11995 break; 11996 11997 case REG_NON_LOCAL_GOTO: 11998 if (GET_CODE (i3) == JUMP_INSN) 11999 place = i3; 12000 else if (i2 && GET_CODE (i2) == JUMP_INSN) 12001 place = i2; 12002 else 12003 abort (); 12004 break; 12005 12006 case REG_EH_REGION: 12007 /* These notes must remain with the call or trapping instruction. */ 12008 if (GET_CODE (i3) == CALL_INSN) 12009 place = i3; 12010 else if (i2 && GET_CODE (i2) == CALL_INSN) 12011 place = i2; 12012 else if (flag_non_call_exceptions) 12013 { 12014 if (may_trap_p (i3)) 12015 place = i3; 12016 else if (i2 && may_trap_p (i2)) 12017 place = i2; 12018 /* ??? Otherwise assume we've combined things such that we 12019 can now prove that the instructions can't trap. Drop the 12020 note in this case. */ 12021 } 12022 else 12023 abort (); 12024 break; 12025 12026 case REG_NORETURN: 12027 case REG_SETJMP: 12028 /* These notes must remain with the call. It should not be 12029 possible for both I2 and I3 to be a call. */ 12030 if (GET_CODE (i3) == CALL_INSN) 12031 place = i3; 12032 else if (i2 && GET_CODE (i2) == CALL_INSN) 12033 place = i2; 12034 else 12035 abort (); 12036 break; 12037 12038 case REG_UNUSED: 12039 /* Any clobbers for i3 may still exist, and so we must process 12040 REG_UNUSED notes from that insn. 12041 12042 Any clobbers from i2 or i1 can only exist if they were added by 12043 recog_for_combine. In that case, recog_for_combine created the 12044 necessary REG_UNUSED notes. Trying to keep any original 12045 REG_UNUSED notes from these insns can cause incorrect output 12046 if it is for the same register as the original i3 dest. 12047 In that case, we will notice that the register is set in i3, 12048 and then add a REG_UNUSED note for the destination of i3, which 12049 is wrong. However, it is possible to have REG_UNUSED notes from 12050 i2 or i1 for register which were both used and clobbered, so 12051 we keep notes from i2 or i1 if they will turn into REG_DEAD 12052 notes. */ 12053 12054 /* If this register is set or clobbered in I3, put the note there 12055 unless there is one already. */ 12056 if (reg_set_p (XEXP (note, 0), PATTERN (i3))) 12057 { 12058 if (from_insn != i3) 12059 break; 12060 12061 if (! (GET_CODE (XEXP (note, 0)) == REG 12062 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) 12063 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) 12064 place = i3; 12065 } 12066 /* Otherwise, if this register is used by I3, then this register 12067 now dies here, so we must put a REG_DEAD note here unless there 12068 is one already. */ 12069 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) 12070 && ! (GET_CODE (XEXP (note, 0)) == REG 12071 ? find_regno_note (i3, REG_DEAD, 12072 REGNO (XEXP (note, 0))) 12073 : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) 12074 { 12075 PUT_REG_NOTE_KIND (note, REG_DEAD); 12076 place = i3; 12077 } 12078 break; 12079 12080 case REG_EQUAL: 12081 case REG_EQUIV: 12082 case REG_NOALIAS: 12083 /* These notes say something about results of an insn. We can 12084 only support them if they used to be on I3 in which case they 12085 remain on I3. Otherwise they are ignored. 12086 12087 If the note refers to an expression that is not a constant, we 12088 must also ignore the note since we cannot tell whether the 12089 equivalence is still true. It might be possible to do 12090 slightly better than this (we only have a problem if I2DEST 12091 or I1DEST is present in the expression), but it doesn't 12092 seem worth the trouble. */ 12093 12094 if (from_insn == i3 12095 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) 12096 place = i3; 12097 break; 12098 12099 case REG_INC: 12100 case REG_NO_CONFLICT: 12101 /* These notes say something about how a register is used. They must 12102 be present on any use of the register in I2 or I3. */ 12103 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) 12104 place = i3; 12105 12106 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) 12107 { 12108 if (place) 12109 place2 = i2; 12110 else 12111 place = i2; 12112 } 12113 break; 12114 12115 case REG_LABEL: 12116 /* This can show up in several ways -- either directly in the 12117 pattern, or hidden off in the constant pool with (or without?) 12118 a REG_EQUAL note. */ 12119 /* ??? Ignore the without-reg_equal-note problem for now. */ 12120 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) 12121 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX)) 12122 && GET_CODE (XEXP (tem, 0)) == LABEL_REF 12123 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))) 12124 place = i3; 12125 12126 if (i2 12127 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) 12128 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX)) 12129 && GET_CODE (XEXP (tem, 0)) == LABEL_REF 12130 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))) 12131 { 12132 if (place) 12133 place2 = i2; 12134 else 12135 place = i2; 12136 } 12137 12138 /* Don't attach REG_LABEL note to a JUMP_INSN which has 12139 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */ 12140 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place)) 12141 { 12142 if (JUMP_LABEL (place) != XEXP (note, 0)) 12143 abort (); 12144 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL) 12145 LABEL_NUSES (JUMP_LABEL (place))--; 12146 place = 0; 12147 } 12148 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2)) 12149 { 12150 if (JUMP_LABEL (place2) != XEXP (note, 0)) 12151 abort (); 12152 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL) 12153 LABEL_NUSES (JUMP_LABEL (place2))--; 12154 place2 = 0; 12155 } 12156 break; 12157 12158 case REG_NONNEG: 12159 case REG_WAS_0: 12160 /* These notes say something about the value of a register prior 12161 to the execution of an insn. It is too much trouble to see 12162 if the note is still correct in all situations. It is better 12163 to simply delete it. */ 12164 break; 12165 12166 case REG_RETVAL: 12167 /* If the insn previously containing this note still exists, 12168 put it back where it was. Otherwise move it to the previous 12169 insn. Adjust the corresponding REG_LIBCALL note. */ 12170 if (GET_CODE (from_insn) != NOTE) 12171 place = from_insn; 12172 else 12173 { 12174 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX); 12175 place = prev_real_insn (from_insn); 12176 if (tem && place) 12177 XEXP (tem, 0) = place; 12178 /* If we're deleting the last remaining instruction of a 12179 libcall sequence, don't add the notes. */ 12180 else if (XEXP (note, 0) == from_insn) 12181 tem = place = 0; 12182 } 12183 break; 12184 12185 case REG_LIBCALL: 12186 /* This is handled similarly to REG_RETVAL. */ 12187 if (GET_CODE (from_insn) != NOTE) 12188 place = from_insn; 12189 else 12190 { 12191 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX); 12192 place = next_real_insn (from_insn); 12193 if (tem && place) 12194 XEXP (tem, 0) = place; 12195 /* If we're deleting the last remaining instruction of a 12196 libcall sequence, don't add the notes. */ 12197 else if (XEXP (note, 0) == from_insn) 12198 tem = place = 0; 12199 } 12200 break; 12201 12202 case REG_DEAD: 12203 /* If the register is used as an input in I3, it dies there. 12204 Similarly for I2, if it is non-zero and adjacent to I3. 12205 12206 If the register is not used as an input in either I3 or I2 12207 and it is not one of the registers we were supposed to eliminate, 12208 there are two possibilities. We might have a non-adjacent I2 12209 or we might have somehow eliminated an additional register 12210 from a computation. For example, we might have had A & B where 12211 we discover that B will always be zero. In this case we will 12212 eliminate the reference to A. 12213 12214 In both cases, we must search to see if we can find a previous 12215 use of A and put the death note there. */ 12216 12217 if (from_insn 12218 && GET_CODE (from_insn) == CALL_INSN 12219 && find_reg_fusage (from_insn, USE, XEXP (note, 0))) 12220 place = from_insn; 12221 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) 12222 place = i3; 12223 else if (i2 != 0 && next_nonnote_insn (i2) == i3 12224 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 12225 place = i2; 12226 12227 if (rtx_equal_p (XEXP (note, 0), elim_i2) 12228 || rtx_equal_p (XEXP (note, 0), elim_i1)) 12229 break; 12230 12231 if (place == 0) 12232 { 12233 basic_block bb = BASIC_BLOCK (this_basic_block); 12234 12235 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem)) 12236 { 12237 if (! INSN_P (tem)) 12238 { 12239 if (tem == bb->head) 12240 break; 12241 continue; 12242 } 12243 12244 /* If the register is being set at TEM, see if that is all 12245 TEM is doing. If so, delete TEM. Otherwise, make this 12246 into a REG_UNUSED note instead. */ 12247 if (reg_set_p (XEXP (note, 0), PATTERN (tem))) 12248 { 12249 rtx set = single_set (tem); 12250 rtx inner_dest = 0; 12251#ifdef HAVE_cc0 12252 rtx cc0_setter = NULL_RTX; 12253#endif 12254 12255 if (set != 0) 12256 for (inner_dest = SET_DEST (set); 12257 (GET_CODE (inner_dest) == STRICT_LOW_PART 12258 || GET_CODE (inner_dest) == SUBREG 12259 || GET_CODE (inner_dest) == ZERO_EXTRACT); 12260 inner_dest = XEXP (inner_dest, 0)) 12261 ; 12262 12263 /* Verify that it was the set, and not a clobber that 12264 modified the register. 12265 12266 CC0 targets must be careful to maintain setter/user 12267 pairs. If we cannot delete the setter due to side 12268 effects, mark the user with an UNUSED note instead 12269 of deleting it. */ 12270 12271 if (set != 0 && ! side_effects_p (SET_SRC (set)) 12272 && rtx_equal_p (XEXP (note, 0), inner_dest) 12273#ifdef HAVE_cc0 12274 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) 12275 || ((cc0_setter = prev_cc0_setter (tem)) != NULL 12276 && sets_cc0_p (PATTERN (cc0_setter)) > 0)) 12277#endif 12278 ) 12279 { 12280 /* Move the notes and links of TEM elsewhere. 12281 This might delete other dead insns recursively. 12282 First set the pattern to something that won't use 12283 any register. */ 12284 12285 PATTERN (tem) = pc_rtx; 12286 12287 distribute_notes (REG_NOTES (tem), tem, tem, 12288 NULL_RTX, NULL_RTX, NULL_RTX); 12289 distribute_links (LOG_LINKS (tem)); 12290 12291 PUT_CODE (tem, NOTE); 12292 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED; 12293 NOTE_SOURCE_FILE (tem) = 0; 12294 12295#ifdef HAVE_cc0 12296 /* Delete the setter too. */ 12297 if (cc0_setter) 12298 { 12299 PATTERN (cc0_setter) = pc_rtx; 12300 12301 distribute_notes (REG_NOTES (cc0_setter), 12302 cc0_setter, cc0_setter, 12303 NULL_RTX, NULL_RTX, NULL_RTX); 12304 distribute_links (LOG_LINKS (cc0_setter)); 12305 12306 PUT_CODE (cc0_setter, NOTE); 12307 NOTE_LINE_NUMBER (cc0_setter) 12308 = NOTE_INSN_DELETED; 12309 NOTE_SOURCE_FILE (cc0_setter) = 0; 12310 } 12311#endif 12312 } 12313 /* If the register is both set and used here, put the 12314 REG_DEAD note here, but place a REG_UNUSED note 12315 here too unless there already is one. */ 12316 else if (reg_referenced_p (XEXP (note, 0), 12317 PATTERN (tem))) 12318 { 12319 place = tem; 12320 12321 if (! find_regno_note (tem, REG_UNUSED, 12322 REGNO (XEXP (note, 0)))) 12323 REG_NOTES (tem) 12324 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0), 12325 REG_NOTES (tem)); 12326 } 12327 else 12328 { 12329 PUT_REG_NOTE_KIND (note, REG_UNUSED); 12330 12331 /* If there isn't already a REG_UNUSED note, put one 12332 here. */ 12333 if (! find_regno_note (tem, REG_UNUSED, 12334 REGNO (XEXP (note, 0)))) 12335 place = tem; 12336 break; 12337 } 12338 } 12339 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)) 12340 || (GET_CODE (tem) == CALL_INSN 12341 && find_reg_fusage (tem, USE, XEXP (note, 0)))) 12342 { 12343 place = tem; 12344 12345 /* If we are doing a 3->2 combination, and we have a 12346 register which formerly died in i3 and was not used 12347 by i2, which now no longer dies in i3 and is used in 12348 i2 but does not die in i2, and place is between i2 12349 and i3, then we may need to move a link from place to 12350 i2. */ 12351 if (i2 && INSN_UID (place) <= max_uid_cuid 12352 && INSN_CUID (place) > INSN_CUID (i2) 12353 && from_insn 12354 && INSN_CUID (from_insn) > INSN_CUID (i2) 12355 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 12356 { 12357 rtx links = LOG_LINKS (place); 12358 LOG_LINKS (place) = 0; 12359 distribute_links (links); 12360 } 12361 break; 12362 } 12363 12364 if (tem == bb->head) 12365 break; 12366 } 12367 12368 /* We haven't found an insn for the death note and it 12369 is still a REG_DEAD note, but we have hit the beginning 12370 of the block. If the existing life info says the reg 12371 was dead, there's nothing left to do. Otherwise, we'll 12372 need to do a global life update after combine. */ 12373 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 12374 && REGNO_REG_SET_P (bb->global_live_at_start, 12375 REGNO (XEXP (note, 0)))) 12376 { 12377 SET_BIT (refresh_blocks, this_basic_block); 12378 need_refresh = 1; 12379 } 12380 } 12381 12382 /* If the register is set or already dead at PLACE, we needn't do 12383 anything with this note if it is still a REG_DEAD note. 12384 We can here if it is set at all, not if is it totally replace, 12385 which is what `dead_or_set_p' checks, so also check for it being 12386 set partially. */ 12387 12388 if (place && REG_NOTE_KIND (note) == REG_DEAD) 12389 { 12390 unsigned int regno = REGNO (XEXP (note, 0)); 12391 12392 /* Similarly, if the instruction on which we want to place 12393 the note is a noop, we'll need do a global live update 12394 after we remove them in delete_noop_moves. */ 12395 if (noop_move_p (place)) 12396 { 12397 SET_BIT (refresh_blocks, this_basic_block); 12398 need_refresh = 1; 12399 } 12400 12401 if (dead_or_set_p (place, XEXP (note, 0)) 12402 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) 12403 { 12404 /* Unless the register previously died in PLACE, clear 12405 reg_last_death. [I no longer understand why this is 12406 being done.] */ 12407 if (reg_last_death[regno] != place) 12408 reg_last_death[regno] = 0; 12409 place = 0; 12410 } 12411 else 12412 reg_last_death[regno] = place; 12413 12414 /* If this is a death note for a hard reg that is occupying 12415 multiple registers, ensure that we are still using all 12416 parts of the object. If we find a piece of the object 12417 that is unused, we must arrange for an appropriate REG_DEAD 12418 note to be added for it. However, we can't just emit a USE 12419 and tag the note to it, since the register might actually 12420 be dead; so we recourse, and the recursive call then finds 12421 the previous insn that used this register. */ 12422 12423 if (place && regno < FIRST_PSEUDO_REGISTER 12424 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1) 12425 { 12426 unsigned int endregno 12427 = regno + HARD_REGNO_NREGS (regno, 12428 GET_MODE (XEXP (note, 0))); 12429 int all_used = 1; 12430 unsigned int i; 12431 12432 for (i = regno; i < endregno; i++) 12433 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0) 12434 && ! find_regno_fusage (place, USE, i)) 12435 || dead_or_set_regno_p (place, i)) 12436 all_used = 0; 12437 12438 if (! all_used) 12439 { 12440 /* Put only REG_DEAD notes for pieces that are 12441 not already dead or set. */ 12442 12443 for (i = regno; i < endregno; 12444 i += HARD_REGNO_NREGS (i, reg_raw_mode[i])) 12445 { 12446 rtx piece = gen_rtx_REG (reg_raw_mode[i], i); 12447 basic_block bb = BASIC_BLOCK (this_basic_block); 12448 12449 if (! dead_or_set_p (place, piece) 12450 && ! reg_bitfield_target_p (piece, 12451 PATTERN (place))) 12452 { 12453 rtx new_note 12454 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX); 12455 12456 distribute_notes (new_note, place, place, 12457 NULL_RTX, NULL_RTX, NULL_RTX); 12458 } 12459 else if (! refers_to_regno_p (i, i + 1, 12460 PATTERN (place), 0) 12461 && ! find_regno_fusage (place, USE, i)) 12462 for (tem = PREV_INSN (place); ; 12463 tem = PREV_INSN (tem)) 12464 { 12465 if (! INSN_P (tem)) 12466 { 12467 if (tem == bb->head) 12468 { 12469 SET_BIT (refresh_blocks, 12470 this_basic_block); 12471 need_refresh = 1; 12472 break; 12473 } 12474 continue; 12475 } 12476 if (dead_or_set_p (tem, piece) 12477 || reg_bitfield_target_p (piece, 12478 PATTERN (tem))) 12479 { 12480 REG_NOTES (tem) 12481 = gen_rtx_EXPR_LIST (REG_UNUSED, piece, 12482 REG_NOTES (tem)); 12483 break; 12484 } 12485 } 12486 12487 } 12488 12489 place = 0; 12490 } 12491 } 12492 } 12493 break; 12494 12495 default: 12496 /* Any other notes should not be present at this point in the 12497 compilation. */ 12498 abort (); 12499 } 12500 12501 if (place) 12502 { 12503 XEXP (note, 1) = REG_NOTES (place); 12504 REG_NOTES (place) = note; 12505 } 12506 else if ((REG_NOTE_KIND (note) == REG_DEAD 12507 || REG_NOTE_KIND (note) == REG_UNUSED) 12508 && GET_CODE (XEXP (note, 0)) == REG) 12509 REG_N_DEATHS (REGNO (XEXP (note, 0)))--; 12510 12511 if (place2) 12512 { 12513 if ((REG_NOTE_KIND (note) == REG_DEAD 12514 || REG_NOTE_KIND (note) == REG_UNUSED) 12515 && GET_CODE (XEXP (note, 0)) == REG) 12516 REG_N_DEATHS (REGNO (XEXP (note, 0)))++; 12517 12518 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note), 12519 REG_NOTE_KIND (note), 12520 XEXP (note, 0), 12521 REG_NOTES (place2)); 12522 } 12523 } 12524} 12525 12526/* Similarly to above, distribute the LOG_LINKS that used to be present on 12527 I3, I2, and I1 to new locations. This is also called in one case to 12528 add a link pointing at I3 when I3's destination is changed. */ 12529 12530static void 12531distribute_links (links) 12532 rtx links; 12533{ 12534 rtx link, next_link; 12535 12536 for (link = links; link; link = next_link) 12537 { 12538 rtx place = 0; 12539 rtx insn; 12540 rtx set, reg; 12541 12542 next_link = XEXP (link, 1); 12543 12544 /* If the insn that this link points to is a NOTE or isn't a single 12545 set, ignore it. In the latter case, it isn't clear what we 12546 can do other than ignore the link, since we can't tell which 12547 register it was for. Such links wouldn't be used by combine 12548 anyway. 12549 12550 It is not possible for the destination of the target of the link to 12551 have been changed by combine. The only potential of this is if we 12552 replace I3, I2, and I1 by I3 and I2. But in that case the 12553 destination of I2 also remains unchanged. */ 12554 12555 if (GET_CODE (XEXP (link, 0)) == NOTE 12556 || (set = single_set (XEXP (link, 0))) == 0) 12557 continue; 12558 12559 reg = SET_DEST (set); 12560 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT 12561 || GET_CODE (reg) == SIGN_EXTRACT 12562 || GET_CODE (reg) == STRICT_LOW_PART) 12563 reg = XEXP (reg, 0); 12564 12565 /* A LOG_LINK is defined as being placed on the first insn that uses 12566 a register and points to the insn that sets the register. Start 12567 searching at the next insn after the target of the link and stop 12568 when we reach a set of the register or the end of the basic block. 12569 12570 Note that this correctly handles the link that used to point from 12571 I3 to I2. Also note that not much searching is typically done here 12572 since most links don't point very far away. */ 12573 12574 for (insn = NEXT_INSN (XEXP (link, 0)); 12575 (insn && (this_basic_block == n_basic_blocks - 1 12576 || BLOCK_HEAD (this_basic_block + 1) != insn)); 12577 insn = NEXT_INSN (insn)) 12578 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn))) 12579 { 12580 if (reg_referenced_p (reg, PATTERN (insn))) 12581 place = insn; 12582 break; 12583 } 12584 else if (GET_CODE (insn) == CALL_INSN 12585 && find_reg_fusage (insn, USE, reg)) 12586 { 12587 place = insn; 12588 break; 12589 } 12590 12591 /* If we found a place to put the link, place it there unless there 12592 is already a link to the same insn as LINK at that point. */ 12593 12594 if (place) 12595 { 12596 rtx link2; 12597 12598 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1)) 12599 if (XEXP (link2, 0) == XEXP (link, 0)) 12600 break; 12601 12602 if (link2 == 0) 12603 { 12604 XEXP (link, 1) = LOG_LINKS (place); 12605 LOG_LINKS (place) = link; 12606 12607 /* Set added_links_insn to the earliest insn we added a 12608 link to. */ 12609 if (added_links_insn == 0 12610 || INSN_CUID (added_links_insn) > INSN_CUID (place)) 12611 added_links_insn = place; 12612 } 12613 } 12614 } 12615} 12616 12617/* Compute INSN_CUID for INSN, which is an insn made by combine. */ 12618 12619static int 12620insn_cuid (insn) 12621 rtx insn; 12622{ 12623 while (insn != 0 && INSN_UID (insn) > max_uid_cuid 12624 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE) 12625 insn = NEXT_INSN (insn); 12626 12627 if (INSN_UID (insn) > max_uid_cuid) 12628 abort (); 12629 12630 return INSN_CUID (insn); 12631} 12632 12633void 12634dump_combine_stats (file) 12635 FILE *file; 12636{ 12637 fnotice 12638 (file, 12639 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", 12640 combine_attempts, combine_merges, combine_extras, combine_successes); 12641} 12642 12643void 12644dump_combine_total_stats (file) 12645 FILE *file; 12646{ 12647 fnotice 12648 (file, 12649 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", 12650 total_attempts, total_merges, total_extras, total_successes); 12651} 12652