combine.c revision 52284
1/* Optimize by combining instructions for GNU compiler. 2 Copyright (C) 1987, 88, 92-98, 1999 Free Software Foundation, Inc. 3 4This file is part of GNU CC. 5 6GNU CC is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 2, or (at your option) 9any later version. 10 11GNU CC is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with GNU CC; see the file COPYING. If not, write to 18the Free Software Foundation, 59 Temple Place - Suite 330, 19Boston, MA 02111-1307, USA. */ 20 21 22/* This module is essentially the "combiner" phase of the U. of Arizona 23 Portable Optimizer, but redone to work on our list-structured 24 representation for RTL instead of their string representation. 25 26 The LOG_LINKS of each insn identify the most recent assignment 27 to each REG used in the insn. It is a list of previous insns, 28 each of which contains a SET for a REG that is used in this insn 29 and not used or set in between. LOG_LINKs never cross basic blocks. 30 They were set up by the preceding pass (lifetime analysis). 31 32 We try to combine each pair of insns joined by a logical link. 33 We also try to combine triples of insns A, B and C when 34 C has a link back to B and B has a link back to A. 35 36 LOG_LINKS does not have links for use of the CC0. They don't 37 need to, because the insn that sets the CC0 is always immediately 38 before the insn that tests it. So we always regard a branch 39 insn as having a logical link to the preceding insn. The same is true 40 for an insn explicitly using CC0. 41 42 We check (with use_crosses_set_p) to avoid combining in such a way 43 as to move a computation to a place where its value would be different. 44 45 Combination is done by mathematically substituting the previous 46 insn(s) values for the regs they set into the expressions in 47 the later insns that refer to these regs. If the result is a valid insn 48 for our target machine, according to the machine description, 49 we install it, delete the earlier insns, and update the data flow 50 information (LOG_LINKS and REG_NOTES) for what we did. 51 52 There are a few exceptions where the dataflow information created by 53 flow.c aren't completely updated: 54 55 - reg_live_length is not updated 56 - reg_n_refs is not adjusted in the rare case when a register is 57 no longer required in a computation 58 - there are extremely rare cases (see distribute_regnotes) when a 59 REG_DEAD note is lost 60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be 61 removed because there is no way to know which register it was 62 linking 63 64 To simplify substitution, we combine only when the earlier insn(s) 65 consist of only a single assignment. To simplify updating afterward, 66 we never combine when a subroutine call appears in the middle. 67 68 Since we do not represent assignments to CC0 explicitly except when that 69 is all an insn does, there is no LOG_LINKS entry in an insn that uses 70 the condition code for the insn that set the condition code. 71 Fortunately, these two insns must be consecutive. 72 Therefore, every JUMP_INSN is taken to have an implicit logical link 73 to the preceding insn. This is not quite right, since non-jumps can 74 also use the condition code; but in practice such insns would not 75 combine anyway. */ 76 77#include "config.h" 78#include "system.h" 79#include "rtl.h" /* stdio.h must precede rtl.h for FFS. */ 80#include "flags.h" 81#include "regs.h" 82#include "hard-reg-set.h" 83#include "basic-block.h" 84#include "insn-config.h" 85/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ 86#include "expr.h" 87#include "insn-flags.h" 88#include "insn-codes.h" 89#include "insn-attr.h" 90#include "recog.h" 91#include "real.h" 92#include "toplev.h" 93 94/* It is not safe to use ordinary gen_lowpart in combine. 95 Use gen_lowpart_for_combine instead. See comments there. */ 96#define gen_lowpart dont_use_gen_lowpart_you_dummy 97 98/* Number of attempts to combine instructions in this function. */ 99 100static int combine_attempts; 101 102/* Number of attempts that got as far as substitution in this function. */ 103 104static int combine_merges; 105 106/* Number of instructions combined with added SETs in this function. */ 107 108static int combine_extras; 109 110/* Number of instructions combined in this function. */ 111 112static int combine_successes; 113 114/* Totals over entire compilation. */ 115 116static int total_attempts, total_merges, total_extras, total_successes; 117 118/* Define a default value for REVERSIBLE_CC_MODE. 119 We can never assume that a condition code mode is safe to reverse unless 120 the md tells us so. */ 121#ifndef REVERSIBLE_CC_MODE 122#define REVERSIBLE_CC_MODE(MODE) 0 123#endif 124 125/* Vector mapping INSN_UIDs to cuids. 126 The cuids are like uids but increase monotonically always. 127 Combine always uses cuids so that it can compare them. 128 But actually renumbering the uids, which we used to do, 129 proves to be a bad idea because it makes it hard to compare 130 the dumps produced by earlier passes with those from later passes. */ 131 132static int *uid_cuid; 133static int max_uid_cuid; 134 135/* Get the cuid of an insn. */ 136 137#define INSN_CUID(INSN) \ 138(INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)]) 139 140/* Maximum register number, which is the size of the tables below. */ 141 142static int combine_max_regno; 143 144/* Record last point of death of (hard or pseudo) register n. */ 145 146static rtx *reg_last_death; 147 148/* Record last point of modification of (hard or pseudo) register n. */ 149 150static rtx *reg_last_set; 151 152/* Record the cuid of the last insn that invalidated memory 153 (anything that writes memory, and subroutine calls, but not pushes). */ 154 155static int mem_last_set; 156 157/* Record the cuid of the last CALL_INSN 158 so we can tell whether a potential combination crosses any calls. */ 159 160static int last_call_cuid; 161 162/* When `subst' is called, this is the insn that is being modified 163 (by combining in a previous insn). The PATTERN of this insn 164 is still the old pattern partially modified and it should not be 165 looked at, but this may be used to examine the successors of the insn 166 to judge whether a simplification is valid. */ 167 168static rtx subst_insn; 169 170/* This is an insn that belongs before subst_insn, but is not currently 171 on the insn chain. */ 172 173static rtx subst_prev_insn; 174 175/* This is the lowest CUID that `subst' is currently dealing with. 176 get_last_value will not return a value if the register was set at or 177 after this CUID. If not for this mechanism, we could get confused if 178 I2 or I1 in try_combine were an insn that used the old value of a register 179 to obtain a new value. In that case, we might erroneously get the 180 new value of the register when we wanted the old one. */ 181 182static int subst_low_cuid; 183 184/* This contains any hard registers that are used in newpat; reg_dead_at_p 185 must consider all these registers to be always live. */ 186 187static HARD_REG_SET newpat_used_regs; 188 189/* This is an insn to which a LOG_LINKS entry has been added. If this 190 insn is the earlier than I2 or I3, combine should rescan starting at 191 that location. */ 192 193static rtx added_links_insn; 194 195/* Basic block number of the block in which we are performing combines. */ 196static int this_basic_block; 197 198/* The next group of arrays allows the recording of the last value assigned 199 to (hard or pseudo) register n. We use this information to see if a 200 operation being processed is redundant given a prior operation performed 201 on the register. For example, an `and' with a constant is redundant if 202 all the zero bits are already known to be turned off. 203 204 We use an approach similar to that used by cse, but change it in the 205 following ways: 206 207 (1) We do not want to reinitialize at each label. 208 (2) It is useful, but not critical, to know the actual value assigned 209 to a register. Often just its form is helpful. 210 211 Therefore, we maintain the following arrays: 212 213 reg_last_set_value the last value assigned 214 reg_last_set_label records the value of label_tick when the 215 register was assigned 216 reg_last_set_table_tick records the value of label_tick when a 217 value using the register is assigned 218 reg_last_set_invalid set to non-zero when it is not valid 219 to use the value of this register in some 220 register's value 221 222 To understand the usage of these tables, it is important to understand 223 the distinction between the value in reg_last_set_value being valid 224 and the register being validly contained in some other expression in the 225 table. 226 227 Entry I in reg_last_set_value is valid if it is non-zero, and either 228 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick. 229 230 Register I may validly appear in any expression returned for the value 231 of another register if reg_n_sets[i] is 1. It may also appear in the 232 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or 233 reg_last_set_invalid[j] is zero. 234 235 If an expression is found in the table containing a register which may 236 not validly appear in an expression, the register is replaced by 237 something that won't match, (clobber (const_int 0)). 238 239 reg_last_set_invalid[i] is set non-zero when register I is being assigned 240 to and reg_last_set_table_tick[i] == label_tick. */ 241 242/* Record last value assigned to (hard or pseudo) register n. */ 243 244static rtx *reg_last_set_value; 245 246/* Record the value of label_tick when the value for register n is placed in 247 reg_last_set_value[n]. */ 248 249static int *reg_last_set_label; 250 251/* Record the value of label_tick when an expression involving register n 252 is placed in reg_last_set_value. */ 253 254static int *reg_last_set_table_tick; 255 256/* Set non-zero if references to register n in expressions should not be 257 used. */ 258 259static char *reg_last_set_invalid; 260 261/* Incremented for each label. */ 262 263static int label_tick; 264 265/* Some registers that are set more than once and used in more than one 266 basic block are nevertheless always set in similar ways. For example, 267 a QImode register may be loaded from memory in two places on a machine 268 where byte loads zero extend. 269 270 We record in the following array what we know about the nonzero 271 bits of a register, specifically which bits are known to be zero. 272 273 If an entry is zero, it means that we don't know anything special. */ 274 275static unsigned HOST_WIDE_INT *reg_nonzero_bits; 276 277/* Mode used to compute significance in reg_nonzero_bits. It is the largest 278 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ 279 280static enum machine_mode nonzero_bits_mode; 281 282/* Nonzero if we know that a register has some leading bits that are always 283 equal to the sign bit. */ 284 285static char *reg_sign_bit_copies; 286 287/* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used. 288 It is zero while computing them and after combine has completed. This 289 former test prevents propagating values based on previously set values, 290 which can be incorrect if a variable is modified in a loop. */ 291 292static int nonzero_sign_valid; 293 294/* These arrays are maintained in parallel with reg_last_set_value 295 and are used to store the mode in which the register was last set, 296 the bits that were known to be zero when it was last set, and the 297 number of sign bits copies it was known to have when it was last set. */ 298 299static enum machine_mode *reg_last_set_mode; 300static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits; 301static char *reg_last_set_sign_bit_copies; 302 303/* Record one modification to rtl structure 304 to be undone by storing old_contents into *where. 305 is_int is 1 if the contents are an int. */ 306 307struct undo 308{ 309 struct undo *next; 310 int is_int; 311 union {rtx r; int i;} old_contents; 312 union {rtx *r; int *i;} where; 313}; 314 315/* Record a bunch of changes to be undone, up to MAX_UNDO of them. 316 num_undo says how many are currently recorded. 317 318 storage is nonzero if we must undo the allocation of new storage. 319 The value of storage is what to pass to obfree. 320 321 other_insn is nonzero if we have modified some other insn in the process 322 of working on subst_insn. It must be verified too. 323 324 previous_undos is the value of undobuf.undos when we started processing 325 this substitution. This will prevent gen_rtx_combine from re-used a piece 326 from the previous expression. Doing so can produce circular rtl 327 structures. */ 328 329struct undobuf 330{ 331 char *storage; 332 struct undo *undos; 333 struct undo *frees; 334 struct undo *previous_undos; 335 rtx other_insn; 336}; 337 338static struct undobuf undobuf; 339 340/* Substitute NEWVAL, an rtx expression, into INTO, a place in some 341 insn. The substitution can be undone by undo_all. If INTO is already 342 set to NEWVAL, do not record this change. Because computing NEWVAL might 343 also call SUBST, we have to compute it before we put anything into 344 the undo table. */ 345 346#define SUBST(INTO, NEWVAL) \ 347 do { rtx _new = (NEWVAL); \ 348 struct undo *_buf; \ 349 \ 350 if (undobuf.frees) \ 351 _buf = undobuf.frees, undobuf.frees = _buf->next; \ 352 else \ 353 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \ 354 \ 355 _buf->is_int = 0; \ 356 _buf->where.r = &INTO; \ 357 _buf->old_contents.r = INTO; \ 358 INTO = _new; \ 359 if (_buf->old_contents.r == INTO) \ 360 _buf->next = undobuf.frees, undobuf.frees = _buf; \ 361 else \ 362 _buf->next = undobuf.undos, undobuf.undos = _buf; \ 363 } while (0) 364 365/* Similar to SUBST, but NEWVAL is an int expression. Note that substitution 366 for the value of a HOST_WIDE_INT value (including CONST_INT) is 367 not safe. */ 368 369#define SUBST_INT(INTO, NEWVAL) \ 370 do { struct undo *_buf; \ 371 \ 372 if (undobuf.frees) \ 373 _buf = undobuf.frees, undobuf.frees = _buf->next; \ 374 else \ 375 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \ 376 \ 377 _buf->is_int = 1; \ 378 _buf->where.i = (int *) &INTO; \ 379 _buf->old_contents.i = INTO; \ 380 INTO = NEWVAL; \ 381 if (_buf->old_contents.i == INTO) \ 382 _buf->next = undobuf.frees, undobuf.frees = _buf; \ 383 else \ 384 _buf->next = undobuf.undos, undobuf.undos = _buf; \ 385 } while (0) 386 387/* Number of times the pseudo being substituted for 388 was found and replaced. */ 389 390static int n_occurrences; 391 392static void init_reg_last_arrays PROTO((void)); 393static void setup_incoming_promotions PROTO((void)); 394static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx)); 395static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *)); 396static int sets_function_arg_p PROTO((rtx)); 397static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *)); 398static rtx try_combine PROTO((rtx, rtx, rtx)); 399static void undo_all PROTO((void)); 400static rtx *find_split_point PROTO((rtx *, rtx)); 401static rtx subst PROTO((rtx, rtx, rtx, int, int)); 402static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int)); 403static rtx simplify_if_then_else PROTO((rtx)); 404static rtx simplify_set PROTO((rtx)); 405static rtx simplify_logical PROTO((rtx, int)); 406static rtx expand_compound_operation PROTO((rtx)); 407static rtx expand_field_assignment PROTO((rtx)); 408static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int, 409 int, int, int)); 410static rtx extract_left_shift PROTO((rtx, int)); 411static rtx make_compound_operation PROTO((rtx, enum rtx_code)); 412static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *)); 413static rtx force_to_mode PROTO((rtx, enum machine_mode, 414 unsigned HOST_WIDE_INT, rtx, int)); 415static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *)); 416static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx)); 417static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx)); 418static rtx make_field_assignment PROTO((rtx)); 419static rtx apply_distributive_law PROTO((rtx)); 420static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx, 421 unsigned HOST_WIDE_INT)); 422static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode)); 423static int num_sign_bit_copies PROTO((rtx, enum machine_mode)); 424static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *, 425 enum rtx_code, HOST_WIDE_INT, 426 enum machine_mode, int *)); 427static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode, 428 rtx, int)); 429static int recog_for_combine PROTO((rtx *, rtx, rtx *)); 430static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx)); 431static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode, 432 ...)); 433static rtx gen_binary PROTO((enum rtx_code, enum machine_mode, 434 rtx, rtx)); 435static rtx gen_unary PROTO((enum rtx_code, enum machine_mode, 436 enum machine_mode, rtx)); 437static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *)); 438static int reversible_comparison_p PROTO((rtx)); 439static void update_table_tick PROTO((rtx)); 440static void record_value_for_reg PROTO((rtx, rtx, rtx)); 441static void record_dead_and_set_regs_1 PROTO((rtx, rtx)); 442static void record_dead_and_set_regs PROTO((rtx)); 443static int get_last_value_validate PROTO((rtx *, rtx, int, int)); 444static rtx get_last_value PROTO((rtx)); 445static int use_crosses_set_p PROTO((rtx, int)); 446static void reg_dead_at_p_1 PROTO((rtx, rtx)); 447static int reg_dead_at_p PROTO((rtx, rtx)); 448static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *)); 449static int reg_bitfield_target_p PROTO((rtx, rtx)); 450static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx)); 451static void distribute_links PROTO((rtx)); 452static void mark_used_regs_combine PROTO((rtx)); 453static int insn_cuid PROTO((rtx)); 454 455/* Main entry point for combiner. F is the first insn of the function. 456 NREGS is the first unused pseudo-reg number. */ 457 458void 459combine_instructions (f, nregs) 460 rtx f; 461 int nregs; 462{ 463 register rtx insn, next; 464#ifdef HAVE_cc0 465 register rtx prev; 466#endif 467 register int i; 468 register rtx links, nextlinks; 469 470 combine_attempts = 0; 471 combine_merges = 0; 472 combine_extras = 0; 473 combine_successes = 0; 474 undobuf.undos = undobuf.previous_undos = 0; 475 476 combine_max_regno = nregs; 477 478 reg_nonzero_bits 479 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT)); 480 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char)); 481 482 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT)); 483 bzero (reg_sign_bit_copies, nregs * sizeof (char)); 484 485 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx)); 486 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx)); 487 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx)); 488 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int)); 489 reg_last_set_label = (int *) alloca (nregs * sizeof (int)); 490 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char)); 491 reg_last_set_mode 492 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode)); 493 reg_last_set_nonzero_bits 494 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT)); 495 reg_last_set_sign_bit_copies 496 = (char *) alloca (nregs * sizeof (char)); 497 498 init_reg_last_arrays (); 499 500 init_recog_no_volatile (); 501 502 /* Compute maximum uid value so uid_cuid can be allocated. */ 503 504 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) 505 if (INSN_UID (insn) > i) 506 i = INSN_UID (insn); 507 508 uid_cuid = (int *) alloca ((i + 1) * sizeof (int)); 509 max_uid_cuid = i; 510 511 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); 512 513 /* Don't use reg_nonzero_bits when computing it. This can cause problems 514 when, for example, we have j <<= 1 in a loop. */ 515 516 nonzero_sign_valid = 0; 517 518 /* Compute the mapping from uids to cuids. 519 Cuids are numbers assigned to insns, like uids, 520 except that cuids increase monotonically through the code. 521 522 Scan all SETs and see if we can deduce anything about what 523 bits are known to be zero for some registers and how many copies 524 of the sign bit are known to exist for those registers. 525 526 Also set any known values so that we can use it while searching 527 for what bits are known to be set. */ 528 529 label_tick = 1; 530 531 /* We need to initialize it here, because record_dead_and_set_regs may call 532 get_last_value. */ 533 subst_prev_insn = NULL_RTX; 534 535 setup_incoming_promotions (); 536 537 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) 538 { 539 uid_cuid[INSN_UID (insn)] = ++i; 540 subst_low_cuid = i; 541 subst_insn = insn; 542 543 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 544 { 545 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies); 546 record_dead_and_set_regs (insn); 547 548#ifdef AUTO_INC_DEC 549 for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) 550 if (REG_NOTE_KIND (links) == REG_INC) 551 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX); 552#endif 553 } 554 555 if (GET_CODE (insn) == CODE_LABEL) 556 label_tick++; 557 } 558 559 nonzero_sign_valid = 1; 560 561 /* Now scan all the insns in forward order. */ 562 563 this_basic_block = -1; 564 label_tick = 1; 565 last_call_cuid = 0; 566 mem_last_set = 0; 567 init_reg_last_arrays (); 568 setup_incoming_promotions (); 569 570 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn)) 571 { 572 next = 0; 573 574 /* If INSN starts a new basic block, update our basic block number. */ 575 if (this_basic_block + 1 < n_basic_blocks 576 && BLOCK_HEAD (this_basic_block + 1) == insn) 577 this_basic_block++; 578 579 if (GET_CODE (insn) == CODE_LABEL) 580 label_tick++; 581 582 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 583 { 584 /* Try this insn with each insn it links back to. */ 585 586 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 587 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0) 588 goto retry; 589 590 /* Try each sequence of three linked insns ending with this one. */ 591 592 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 593 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks; 594 nextlinks = XEXP (nextlinks, 1)) 595 if ((next = try_combine (insn, XEXP (links, 0), 596 XEXP (nextlinks, 0))) != 0) 597 goto retry; 598 599#ifdef HAVE_cc0 600 /* Try to combine a jump insn that uses CC0 601 with a preceding insn that sets CC0, and maybe with its 602 logical predecessor as well. 603 This is how we make decrement-and-branch insns. 604 We need this special code because data flow connections 605 via CC0 do not get entered in LOG_LINKS. */ 606 607 if (GET_CODE (insn) == JUMP_INSN 608 && (prev = prev_nonnote_insn (insn)) != 0 609 && GET_CODE (prev) == INSN 610 && sets_cc0_p (PATTERN (prev))) 611 { 612 if ((next = try_combine (insn, prev, NULL_RTX)) != 0) 613 goto retry; 614 615 for (nextlinks = LOG_LINKS (prev); nextlinks; 616 nextlinks = XEXP (nextlinks, 1)) 617 if ((next = try_combine (insn, prev, 618 XEXP (nextlinks, 0))) != 0) 619 goto retry; 620 } 621 622 /* Do the same for an insn that explicitly references CC0. */ 623 if (GET_CODE (insn) == INSN 624 && (prev = prev_nonnote_insn (insn)) != 0 625 && GET_CODE (prev) == INSN 626 && sets_cc0_p (PATTERN (prev)) 627 && GET_CODE (PATTERN (insn)) == SET 628 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) 629 { 630 if ((next = try_combine (insn, prev, NULL_RTX)) != 0) 631 goto retry; 632 633 for (nextlinks = LOG_LINKS (prev); nextlinks; 634 nextlinks = XEXP (nextlinks, 1)) 635 if ((next = try_combine (insn, prev, 636 XEXP (nextlinks, 0))) != 0) 637 goto retry; 638 } 639 640 /* Finally, see if any of the insns that this insn links to 641 explicitly references CC0. If so, try this insn, that insn, 642 and its predecessor if it sets CC0. */ 643 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 644 if (GET_CODE (XEXP (links, 0)) == INSN 645 && GET_CODE (PATTERN (XEXP (links, 0))) == SET 646 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0)))) 647 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0 648 && GET_CODE (prev) == INSN 649 && sets_cc0_p (PATTERN (prev)) 650 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0) 651 goto retry; 652#endif 653 654 /* Try combining an insn with two different insns whose results it 655 uses. */ 656 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 657 for (nextlinks = XEXP (links, 1); nextlinks; 658 nextlinks = XEXP (nextlinks, 1)) 659 if ((next = try_combine (insn, XEXP (links, 0), 660 XEXP (nextlinks, 0))) != 0) 661 goto retry; 662 663 if (GET_CODE (insn) != NOTE) 664 record_dead_and_set_regs (insn); 665 666 retry: 667 ; 668 } 669 } 670 671 total_attempts += combine_attempts; 672 total_merges += combine_merges; 673 total_extras += combine_extras; 674 total_successes += combine_successes; 675 676 nonzero_sign_valid = 0; 677 678 /* Make recognizer allow volatile MEMs again. */ 679 init_recog (); 680} 681 682/* Wipe the reg_last_xxx arrays in preparation for another pass. */ 683 684static void 685init_reg_last_arrays () 686{ 687 int nregs = combine_max_regno; 688 689 bzero ((char *) reg_last_death, nregs * sizeof (rtx)); 690 bzero ((char *) reg_last_set, nregs * sizeof (rtx)); 691 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx)); 692 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int)); 693 bzero ((char *) reg_last_set_label, nregs * sizeof (int)); 694 bzero (reg_last_set_invalid, nregs * sizeof (char)); 695 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode)); 696 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT)); 697 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char)); 698} 699 700/* Set up any promoted values for incoming argument registers. */ 701 702static void 703setup_incoming_promotions () 704{ 705#ifdef PROMOTE_FUNCTION_ARGS 706 int regno; 707 rtx reg; 708 enum machine_mode mode; 709 int unsignedp; 710 rtx first = get_insns (); 711 712 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 713 if (FUNCTION_ARG_REGNO_P (regno) 714 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0) 715 { 716 record_value_for_reg 717 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND 718 : SIGN_EXTEND), 719 GET_MODE (reg), 720 gen_rtx_CLOBBER (mode, const0_rtx))); 721 } 722#endif 723} 724 725/* Called via note_stores. If X is a pseudo that is narrower than 726 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. 727 728 If we are setting only a portion of X and we can't figure out what 729 portion, assume all bits will be used since we don't know what will 730 be happening. 731 732 Similarly, set how many bits of X are known to be copies of the sign bit 733 at all locations in the function. This is the smallest number implied 734 by any set of X. */ 735 736static void 737set_nonzero_bits_and_sign_copies (x, set) 738 rtx x; 739 rtx set; 740{ 741 int num; 742 743 if (GET_CODE (x) == REG 744 && REGNO (x) >= FIRST_PSEUDO_REGISTER 745 /* If this register is undefined at the start of the file, we can't 746 say what its contents were. */ 747 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x)) 748 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) 749 { 750 if (set == 0 || GET_CODE (set) == CLOBBER) 751 { 752 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); 753 reg_sign_bit_copies[REGNO (x)] = 1; 754 return; 755 } 756 757 /* If this is a complex assignment, see if we can convert it into a 758 simple assignment. */ 759 set = expand_field_assignment (set); 760 761 /* If this is a simple assignment, or we have a paradoxical SUBREG, 762 set what we know about X. */ 763 764 if (SET_DEST (set) == x 765 || (GET_CODE (SET_DEST (set)) == SUBREG 766 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set))) 767 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set))))) 768 && SUBREG_REG (SET_DEST (set)) == x)) 769 { 770 rtx src = SET_SRC (set); 771 772#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 773 /* If X is narrower than a word and SRC is a non-negative 774 constant that would appear negative in the mode of X, 775 sign-extend it for use in reg_nonzero_bits because some 776 machines (maybe most) will actually do the sign-extension 777 and this is the conservative approach. 778 779 ??? For 2.5, try to tighten up the MD files in this regard 780 instead of this kludge. */ 781 782 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD 783 && GET_CODE (src) == CONST_INT 784 && INTVAL (src) > 0 785 && 0 != (INTVAL (src) 786 & ((HOST_WIDE_INT) 1 787 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 788 src = GEN_INT (INTVAL (src) 789 | ((HOST_WIDE_INT) (-1) 790 << GET_MODE_BITSIZE (GET_MODE (x)))); 791#endif 792 793 reg_nonzero_bits[REGNO (x)] 794 |= nonzero_bits (src, nonzero_bits_mode); 795 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); 796 if (reg_sign_bit_copies[REGNO (x)] == 0 797 || reg_sign_bit_copies[REGNO (x)] > num) 798 reg_sign_bit_copies[REGNO (x)] = num; 799 } 800 else 801 { 802 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); 803 reg_sign_bit_copies[REGNO (x)] = 1; 804 } 805 } 806} 807 808/* See if INSN can be combined into I3. PRED and SUCC are optionally 809 insns that were previously combined into I3 or that will be combined 810 into the merger of INSN and I3. 811 812 Return 0 if the combination is not allowed for any reason. 813 814 If the combination is allowed, *PDEST will be set to the single 815 destination of INSN and *PSRC to the single source, and this function 816 will return 1. */ 817 818static int 819can_combine_p (insn, i3, pred, succ, pdest, psrc) 820 rtx insn; 821 rtx i3; 822 rtx pred ATTRIBUTE_UNUSED; 823 rtx succ; 824 rtx *pdest, *psrc; 825{ 826 int i; 827 rtx set = 0, src, dest; 828 rtx p; 829#ifdef AUTO_INC_DEC 830 rtx link; 831#endif 832 int all_adjacent = (succ ? (next_active_insn (insn) == succ 833 && next_active_insn (succ) == i3) 834 : next_active_insn (insn) == i3); 835 836 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. 837 or a PARALLEL consisting of such a SET and CLOBBERs. 838 839 If INSN has CLOBBER parallel parts, ignore them for our processing. 840 By definition, these happen during the execution of the insn. When it 841 is merged with another insn, all bets are off. If they are, in fact, 842 needed and aren't also supplied in I3, they may be added by 843 recog_for_combine. Otherwise, it won't match. 844 845 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED 846 note. 847 848 Get the source and destination of INSN. If more than one, can't 849 combine. */ 850 851 if (GET_CODE (PATTERN (insn)) == SET) 852 set = PATTERN (insn); 853 else if (GET_CODE (PATTERN (insn)) == PARALLEL 854 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) 855 { 856 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) 857 { 858 rtx elt = XVECEXP (PATTERN (insn), 0, i); 859 860 switch (GET_CODE (elt)) 861 { 862 /* This is important to combine floating point insns 863 for the SH4 port. */ 864 case USE: 865 /* Combining an isolated USE doesn't make sense. 866 We depend here on combinable_i3_pat to reject them. */ 867 /* The code below this loop only verifies that the inputs of 868 the SET in INSN do not change. We call reg_set_between_p 869 to verify that the REG in the USE does not change betweeen 870 I3 and INSN. 871 If the USE in INSN was for a pseudo register, the matching 872 insn pattern will likely match any register; combining this 873 with any other USE would only be safe if we knew that the 874 used registers have identical values, or if there was 875 something to tell them apart, e.g. different modes. For 876 now, we forgo such compilcated tests and simply disallow 877 combining of USES of pseudo registers with any other USE. */ 878 if (GET_CODE (XEXP (elt, 0)) == REG 879 && GET_CODE (PATTERN (i3)) == PARALLEL) 880 { 881 rtx i3pat = PATTERN (i3); 882 int i = XVECLEN (i3pat, 0) - 1; 883 int regno = REGNO (XEXP (elt, 0)); 884 do 885 { 886 rtx i3elt = XVECEXP (i3pat, 0, i); 887 if (GET_CODE (i3elt) == USE 888 && GET_CODE (XEXP (i3elt, 0)) == REG 889 && (REGNO (XEXP (i3elt, 0)) == regno 890 ? reg_set_between_p (XEXP (elt, 0), 891 PREV_INSN (insn), i3) 892 : regno >= FIRST_PSEUDO_REGISTER)) 893 return 0; 894 } 895 while (--i >= 0); 896 } 897 break; 898 899 /* We can ignore CLOBBERs. */ 900 case CLOBBER: 901 break; 902 903 case SET: 904 /* Ignore SETs whose result isn't used but not those that 905 have side-effects. */ 906 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) 907 && ! side_effects_p (elt)) 908 break; 909 910 /* If we have already found a SET, this is a second one and 911 so we cannot combine with this insn. */ 912 if (set) 913 return 0; 914 915 set = elt; 916 break; 917 918 default: 919 /* Anything else means we can't combine. */ 920 return 0; 921 } 922 } 923 924 if (set == 0 925 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, 926 so don't do anything with it. */ 927 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) 928 return 0; 929 } 930 else 931 return 0; 932 933 if (set == 0) 934 return 0; 935 936 set = expand_field_assignment (set); 937 src = SET_SRC (set), dest = SET_DEST (set); 938 939 /* Don't eliminate a store in the stack pointer. */ 940 if (dest == stack_pointer_rtx 941 /* If we couldn't eliminate a field assignment, we can't combine. */ 942 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART 943 /* Don't combine with an insn that sets a register to itself if it has 944 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */ 945 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) 946 /* Can't merge a function call. */ 947 || GET_CODE (src) == CALL 948 /* Don't eliminate a function call argument. */ 949 || (GET_CODE (i3) == CALL_INSN 950 && (find_reg_fusage (i3, USE, dest) 951 || (GET_CODE (dest) == REG 952 && REGNO (dest) < FIRST_PSEUDO_REGISTER 953 && global_regs[REGNO (dest)]))) 954 /* Don't substitute into an incremented register. */ 955 || FIND_REG_INC_NOTE (i3, dest) 956 || (succ && FIND_REG_INC_NOTE (succ, dest)) 957#if 0 958 /* Don't combine the end of a libcall into anything. */ 959 /* ??? This gives worse code, and appears to be unnecessary, since no 960 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does 961 use REG_RETVAL notes for noconflict blocks, but other code here 962 makes sure that those insns don't disappear. */ 963 || find_reg_note (insn, REG_RETVAL, NULL_RTX) 964#endif 965 /* Make sure that DEST is not used after SUCC but before I3. */ 966 || (succ && ! all_adjacent 967 && reg_used_between_p (dest, succ, i3)) 968 /* Make sure that the value that is to be substituted for the register 969 does not use any registers whose values alter in between. However, 970 If the insns are adjacent, a use can't cross a set even though we 971 think it might (this can happen for a sequence of insns each setting 972 the same destination; reg_last_set of that register might point to 973 a NOTE). If INSN has a REG_EQUIV note, the register is always 974 equivalent to the memory so the substitution is valid even if there 975 are intervening stores. Also, don't move a volatile asm or 976 UNSPEC_VOLATILE across any other insns. */ 977 || (! all_adjacent 978 && (((GET_CODE (src) != MEM 979 || ! find_reg_note (insn, REG_EQUIV, src)) 980 && use_crosses_set_p (src, INSN_CUID (insn))) 981 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) 982 || GET_CODE (src) == UNSPEC_VOLATILE)) 983 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get 984 better register allocation by not doing the combine. */ 985 || find_reg_note (i3, REG_NO_CONFLICT, dest) 986 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest)) 987 /* Don't combine across a CALL_INSN, because that would possibly 988 change whether the life span of some REGs crosses calls or not, 989 and it is a pain to update that information. 990 Exception: if source is a constant, moving it later can't hurt. 991 Accept that special case, because it helps -fforce-addr a lot. */ 992 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src))) 993 return 0; 994 995 /* DEST must either be a REG or CC0. */ 996 if (GET_CODE (dest) == REG) 997 { 998 /* If register alignment is being enforced for multi-word items in all 999 cases except for parameters, it is possible to have a register copy 1000 insn referencing a hard register that is not allowed to contain the 1001 mode being copied and which would not be valid as an operand of most 1002 insns. Eliminate this problem by not combining with such an insn. 1003 1004 Also, on some machines we don't want to extend the life of a hard 1005 register. 1006 1007 This is the same test done in can_combine except that we don't test 1008 if SRC is a CALL operation to permit a hard register with 1009 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent 1010 into account. */ 1011 1012 if (GET_CODE (src) == REG 1013 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER 1014 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) 1015 /* Don't extend the life of a hard register unless it is 1016 user variable (if we have few registers) or it can't 1017 fit into the desired register (meaning something special 1018 is going on). 1019 Also avoid substituting a return register into I3, because 1020 reload can't handle a conflict with constraints of other 1021 inputs. */ 1022 || (REGNO (src) < FIRST_PSEUDO_REGISTER 1023 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)) 1024 || (SMALL_REGISTER_CLASSES 1025 && ((! all_adjacent && ! REG_USERVAR_P (src)) 1026 || (FUNCTION_VALUE_REGNO_P (REGNO (src)) 1027 && ! REG_USERVAR_P (src)))))))) 1028 return 0; 1029 } 1030 else if (GET_CODE (dest) != CC0) 1031 return 0; 1032 1033 /* Don't substitute for a register intended as a clobberable operand. 1034 Similarly, don't substitute an expression containing a register that 1035 will be clobbered in I3. */ 1036 if (GET_CODE (PATTERN (i3)) == PARALLEL) 1037 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) 1038 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER 1039 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), 1040 src) 1041 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest))) 1042 return 0; 1043 1044 /* If INSN contains anything volatile, or is an `asm' (whether volatile 1045 or not), reject, unless nothing volatile comes between it and I3 */ 1046 1047 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) 1048 { 1049 /* Make sure succ doesn't contain a volatile reference. */ 1050 if (succ != 0 && volatile_refs_p (PATTERN (succ))) 1051 return 0; 1052 1053 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 1054 if (GET_RTX_CLASS (GET_CODE (p)) == 'i' 1055 && p != succ && volatile_refs_p (PATTERN (p))) 1056 return 0; 1057 } 1058 1059 /* If INSN is an asm, and DEST is a hard register, reject, since it has 1060 to be an explicit register variable, and was chosen for a reason. */ 1061 1062 if (GET_CODE (src) == ASM_OPERANDS 1063 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER) 1064 return 0; 1065 1066 /* If there are any volatile insns between INSN and I3, reject, because 1067 they might affect machine state. */ 1068 1069 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 1070 if (GET_RTX_CLASS (GET_CODE (p)) == 'i' 1071 && p != succ && volatile_insn_p (PATTERN (p))) 1072 return 0; 1073 1074 /* If INSN or I2 contains an autoincrement or autodecrement, 1075 make sure that register is not used between there and I3, 1076 and not already used in I3 either. 1077 Also insist that I3 not be a jump; if it were one 1078 and the incremented register were spilled, we would lose. */ 1079 1080#ifdef AUTO_INC_DEC 1081 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1082 if (REG_NOTE_KIND (link) == REG_INC 1083 && (GET_CODE (i3) == JUMP_INSN 1084 || reg_used_between_p (XEXP (link, 0), insn, i3) 1085 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) 1086 return 0; 1087#endif 1088 1089#ifdef HAVE_cc0 1090 /* Don't combine an insn that follows a CC0-setting insn. 1091 An insn that uses CC0 must not be separated from the one that sets it. 1092 We do, however, allow I2 to follow a CC0-setting insn if that insn 1093 is passed as I1; in that case it will be deleted also. 1094 We also allow combining in this case if all the insns are adjacent 1095 because that would leave the two CC0 insns adjacent as well. 1096 It would be more logical to test whether CC0 occurs inside I1 or I2, 1097 but that would be much slower, and this ought to be equivalent. */ 1098 1099 p = prev_nonnote_insn (insn); 1100 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p)) 1101 && ! all_adjacent) 1102 return 0; 1103#endif 1104 1105 /* If we get here, we have passed all the tests and the combination is 1106 to be allowed. */ 1107 1108 *pdest = dest; 1109 *psrc = src; 1110 1111 return 1; 1112} 1113 1114/* Check if PAT is an insn - or a part of it - used to set up an 1115 argument for a function in a hard register. */ 1116 1117static int 1118sets_function_arg_p (pat) 1119 rtx pat; 1120{ 1121 int i; 1122 rtx inner_dest; 1123 1124 switch (GET_CODE (pat)) 1125 { 1126 case INSN: 1127 return sets_function_arg_p (PATTERN (pat)); 1128 1129 case PARALLEL: 1130 for (i = XVECLEN (pat, 0); --i >= 0;) 1131 if (sets_function_arg_p (XVECEXP (pat, 0, i))) 1132 return 1; 1133 1134 break; 1135 1136 case SET: 1137 inner_dest = SET_DEST (pat); 1138 while (GET_CODE (inner_dest) == STRICT_LOW_PART 1139 || GET_CODE (inner_dest) == SUBREG 1140 || GET_CODE (inner_dest) == ZERO_EXTRACT) 1141 inner_dest = XEXP (inner_dest, 0); 1142 1143 return (GET_CODE (inner_dest) == REG 1144 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 1145 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest))); 1146 1147 default: 1148 break; 1149 } 1150 1151 return 0; 1152} 1153 1154/* LOC is the location within I3 that contains its pattern or the component 1155 of a PARALLEL of the pattern. We validate that it is valid for combining. 1156 1157 One problem is if I3 modifies its output, as opposed to replacing it 1158 entirely, we can't allow the output to contain I2DEST or I1DEST as doing 1159 so would produce an insn that is not equivalent to the original insns. 1160 1161 Consider: 1162 1163 (set (reg:DI 101) (reg:DI 100)) 1164 (set (subreg:SI (reg:DI 101) 0) <foo>) 1165 1166 This is NOT equivalent to: 1167 1168 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) 1169 (set (reg:DI 101) (reg:DI 100))]) 1170 1171 Not only does this modify 100 (in which case it might still be valid 1172 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. 1173 1174 We can also run into a problem if I2 sets a register that I1 1175 uses and I1 gets directly substituted into I3 (not via I2). In that 1176 case, we would be getting the wrong value of I2DEST into I3, so we 1177 must reject the combination. This case occurs when I2 and I1 both 1178 feed into I3, rather than when I1 feeds into I2, which feeds into I3. 1179 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source 1180 of a SET must prevent combination from occurring. 1181 1182 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine 1183 if the destination of a SET is a hard register that isn't a user 1184 variable. 1185 1186 Before doing the above check, we first try to expand a field assignment 1187 into a set of logical operations. 1188 1189 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which 1190 we place a register that is both set and used within I3. If more than one 1191 such register is detected, we fail. 1192 1193 Return 1 if the combination is valid, zero otherwise. */ 1194 1195static int 1196combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed) 1197 rtx i3; 1198 rtx *loc; 1199 rtx i2dest; 1200 rtx i1dest; 1201 int i1_not_in_src; 1202 rtx *pi3dest_killed; 1203{ 1204 rtx x = *loc; 1205 1206 if (GET_CODE (x) == SET) 1207 { 1208 rtx set = expand_field_assignment (x); 1209 rtx dest = SET_DEST (set); 1210 rtx src = SET_SRC (set); 1211 rtx inner_dest = dest; 1212 1213#if 0 1214 rtx inner_src = src; 1215#endif 1216 1217 SUBST (*loc, set); 1218 1219 while (GET_CODE (inner_dest) == STRICT_LOW_PART 1220 || GET_CODE (inner_dest) == SUBREG 1221 || GET_CODE (inner_dest) == ZERO_EXTRACT) 1222 inner_dest = XEXP (inner_dest, 0); 1223 1224 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS 1225 was added. */ 1226#if 0 1227 while (GET_CODE (inner_src) == STRICT_LOW_PART 1228 || GET_CODE (inner_src) == SUBREG 1229 || GET_CODE (inner_src) == ZERO_EXTRACT) 1230 inner_src = XEXP (inner_src, 0); 1231 1232 /* If it is better that two different modes keep two different pseudos, 1233 avoid combining them. This avoids producing the following pattern 1234 on a 386: 1235 (set (subreg:SI (reg/v:QI 21) 0) 1236 (lshiftrt:SI (reg/v:SI 20) 1237 (const_int 24))) 1238 If that were made, reload could not handle the pair of 1239 reg 20/21, since it would try to get any GENERAL_REGS 1240 but some of them don't handle QImode. */ 1241 1242 if (rtx_equal_p (inner_src, i2dest) 1243 && GET_CODE (inner_dest) == REG 1244 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest))) 1245 return 0; 1246#endif 1247 1248 /* Check for the case where I3 modifies its output, as 1249 discussed above. */ 1250 if ((inner_dest != dest 1251 && (reg_overlap_mentioned_p (i2dest, inner_dest) 1252 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) 1253 1254 /* This is the same test done in can_combine_p except that we 1255 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a 1256 CALL operation. Moreover, we can't test all_adjacent; we don't 1257 have to, since this instruction will stay in place, thus we are 1258 not considering increasing the lifetime of INNER_DEST. 1259 1260 Also, if this insn sets a function argument, combining it with 1261 something that might need a spill could clobber a previous 1262 function argument; the all_adjacent test in can_combine_p also 1263 checks this; here, we do a more specific test for this case. */ 1264 1265 || (GET_CODE (inner_dest) == REG 1266 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 1267 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), 1268 GET_MODE (inner_dest)) 1269 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL 1270 && ! REG_USERVAR_P (inner_dest) 1271 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest)) 1272 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest)) 1273 && i3 != 0 1274 && sets_function_arg_p (prev_nonnote_insn (i3))))))) 1275 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) 1276 return 0; 1277 1278 /* If DEST is used in I3, it is being killed in this insn, 1279 so record that for later. 1280 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the 1281 STACK_POINTER_REGNUM, since these are always considered to be 1282 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ 1283 if (pi3dest_killed && GET_CODE (dest) == REG 1284 && reg_referenced_p (dest, PATTERN (i3)) 1285 && REGNO (dest) != FRAME_POINTER_REGNUM 1286#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 1287 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM 1288#endif 1289#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM 1290 && (REGNO (dest) != ARG_POINTER_REGNUM 1291 || ! fixed_regs [REGNO (dest)]) 1292#endif 1293 && REGNO (dest) != STACK_POINTER_REGNUM) 1294 { 1295 if (*pi3dest_killed) 1296 return 0; 1297 1298 *pi3dest_killed = dest; 1299 } 1300 } 1301 1302 else if (GET_CODE (x) == PARALLEL) 1303 { 1304 int i; 1305 1306 for (i = 0; i < XVECLEN (x, 0); i++) 1307 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, 1308 i1_not_in_src, pi3dest_killed)) 1309 return 0; 1310 } 1311 1312 return 1; 1313} 1314 1315/* Try to combine the insns I1 and I2 into I3. 1316 Here I1 and I2 appear earlier than I3. 1317 I1 can be zero; then we combine just I2 into I3. 1318 1319 It we are combining three insns and the resulting insn is not recognized, 1320 try splitting it into two insns. If that happens, I2 and I3 are retained 1321 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2 1322 are pseudo-deleted. 1323 1324 Return 0 if the combination does not work. Then nothing is changed. 1325 If we did the combination, return the insn at which combine should 1326 resume scanning. */ 1327 1328static rtx 1329try_combine (i3, i2, i1) 1330 register rtx i3, i2, i1; 1331{ 1332 /* New patterns for I3 and I3, respectively. */ 1333 rtx newpat, newi2pat = 0; 1334 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */ 1335 int added_sets_1, added_sets_2; 1336 /* Total number of SETs to put into I3. */ 1337 int total_sets; 1338 /* Nonzero is I2's body now appears in I3. */ 1339 int i2_is_used; 1340 /* INSN_CODEs for new I3, new I2, and user of condition code. */ 1341 int insn_code_number, i2_code_number, other_code_number; 1342 /* Contains I3 if the destination of I3 is used in its source, which means 1343 that the old life of I3 is being killed. If that usage is placed into 1344 I2 and not in I3, a REG_DEAD note must be made. */ 1345 rtx i3dest_killed = 0; 1346 /* SET_DEST and SET_SRC of I2 and I1. */ 1347 rtx i2dest, i2src, i1dest = 0, i1src = 0; 1348 /* PATTERN (I2), or a copy of it in certain cases. */ 1349 rtx i2pat; 1350 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ 1351 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; 1352 int i1_feeds_i3 = 0; 1353 /* Notes that must be added to REG_NOTES in I3 and I2. */ 1354 rtx new_i3_notes, new_i2_notes; 1355 /* Notes that we substituted I3 into I2 instead of the normal case. */ 1356 int i3_subst_into_i2 = 0; 1357 /* Notes that I1, I2 or I3 is a MULT operation. */ 1358 int have_mult = 0; 1359 1360 int maxreg; 1361 rtx temp; 1362 register rtx link; 1363 int i; 1364 1365 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything. 1366 This can occur when flow deletes an insn that it has merged into an 1367 auto-increment address. We also can't do anything if I3 has a 1368 REG_LIBCALL note since we don't want to disrupt the contiguity of a 1369 libcall. */ 1370 1371 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i' 1372 || GET_RTX_CLASS (GET_CODE (i2)) != 'i' 1373 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i') 1374#if 0 1375 /* ??? This gives worse code, and appears to be unnecessary, since no 1376 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */ 1377 || find_reg_note (i3, REG_LIBCALL, NULL_RTX) 1378#endif 1379) 1380 return 0; 1381 1382 combine_attempts++; 1383 1384 undobuf.undos = undobuf.previous_undos = 0; 1385 undobuf.other_insn = 0; 1386 1387 /* Save the current high-water-mark so we can free storage if we didn't 1388 accept this combination. */ 1389 undobuf.storage = (char *) oballoc (0); 1390 1391 /* Reset the hard register usage information. */ 1392 CLEAR_HARD_REG_SET (newpat_used_regs); 1393 1394 /* If I1 and I2 both feed I3, they can be in any order. To simplify the 1395 code below, set I1 to be the earlier of the two insns. */ 1396 if (i1 && INSN_CUID (i1) > INSN_CUID (i2)) 1397 temp = i1, i1 = i2, i2 = temp; 1398 1399 added_links_insn = 0; 1400 1401 /* First check for one important special-case that the code below will 1402 not handle. Namely, the case where I1 is zero, I2 has multiple sets, 1403 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, 1404 we may be able to replace that destination with the destination of I3. 1405 This occurs in the common code where we compute both a quotient and 1406 remainder into a structure, in which case we want to do the computation 1407 directly into the structure to avoid register-register copies. 1408 1409 We make very conservative checks below and only try to handle the 1410 most common cases of this. For example, we only handle the case 1411 where I2 and I3 are adjacent to avoid making difficult register 1412 usage tests. */ 1413 1414 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET 1415 && GET_CODE (SET_SRC (PATTERN (i3))) == REG 1416 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER 1417 && (! SMALL_REGISTER_CLASSES 1418 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG 1419 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER 1420 || REG_USERVAR_P (SET_DEST (PATTERN (i3))))) 1421 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) 1422 && GET_CODE (PATTERN (i2)) == PARALLEL 1423 && ! side_effects_p (SET_DEST (PATTERN (i3))) 1424 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code 1425 below would need to check what is inside (and reg_overlap_mentioned_p 1426 doesn't support those codes anyway). Don't allow those destinations; 1427 the resulting insn isn't likely to be recognized anyway. */ 1428 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT 1429 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART 1430 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), 1431 SET_DEST (PATTERN (i3))) 1432 && next_real_insn (i2) == i3) 1433 { 1434 rtx p2 = PATTERN (i2); 1435 1436 /* Make sure that the destination of I3, 1437 which we are going to substitute into one output of I2, 1438 is not used within another output of I2. We must avoid making this: 1439 (parallel [(set (mem (reg 69)) ...) 1440 (set (reg 69) ...)]) 1441 which is not well-defined as to order of actions. 1442 (Besides, reload can't handle output reloads for this.) 1443 1444 The problem can also happen if the dest of I3 is a memory ref, 1445 if another dest in I2 is an indirect memory ref. */ 1446 for (i = 0; i < XVECLEN (p2, 0); i++) 1447 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET 1448 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) 1449 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), 1450 SET_DEST (XVECEXP (p2, 0, i)))) 1451 break; 1452 1453 if (i == XVECLEN (p2, 0)) 1454 for (i = 0; i < XVECLEN (p2, 0); i++) 1455 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) 1456 { 1457 combine_merges++; 1458 1459 subst_insn = i3; 1460 subst_low_cuid = INSN_CUID (i2); 1461 1462 added_sets_2 = added_sets_1 = 0; 1463 i2dest = SET_SRC (PATTERN (i3)); 1464 1465 /* Replace the dest in I2 with our dest and make the resulting 1466 insn the new pattern for I3. Then skip to where we 1467 validate the pattern. Everything was set up above. */ 1468 SUBST (SET_DEST (XVECEXP (p2, 0, i)), 1469 SET_DEST (PATTERN (i3))); 1470 1471 newpat = p2; 1472 i3_subst_into_i2 = 1; 1473 goto validate_replacement; 1474 } 1475 } 1476 1477#ifndef HAVE_cc0 1478 /* If we have no I1 and I2 looks like: 1479 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) 1480 (set Y OP)]) 1481 make up a dummy I1 that is 1482 (set Y OP) 1483 and change I2 to be 1484 (set (reg:CC X) (compare:CC Y (const_int 0))) 1485 1486 (We can ignore any trailing CLOBBERs.) 1487 1488 This undoes a previous combination and allows us to match a branch-and- 1489 decrement insn. */ 1490 1491 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL 1492 && XVECLEN (PATTERN (i2), 0) >= 2 1493 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET 1494 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) 1495 == MODE_CC) 1496 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE 1497 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx 1498 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET 1499 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG 1500 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), 1501 SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) 1502 { 1503 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) 1504 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) 1505 break; 1506 1507 if (i == 1) 1508 { 1509 /* We make I1 with the same INSN_UID as I2. This gives it 1510 the same INSN_CUID for value tracking. Our fake I1 will 1511 never appear in the insn stream so giving it the same INSN_UID 1512 as I2 will not cause a problem. */ 1513 1514 subst_prev_insn = i1 1515 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2, 1516 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, 1517 NULL_RTX); 1518 1519 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); 1520 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), 1521 SET_DEST (PATTERN (i1))); 1522 } 1523 } 1524#endif 1525 1526 /* Verify that I2 and I1 are valid for combining. */ 1527 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src) 1528 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src))) 1529 { 1530 undo_all (); 1531 return 0; 1532 } 1533 1534 /* Record whether I2DEST is used in I2SRC and similarly for the other 1535 cases. Knowing this will help in register status updating below. */ 1536 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); 1537 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); 1538 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); 1539 1540 /* See if I1 directly feeds into I3. It does if I1DEST is not used 1541 in I2SRC. */ 1542 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); 1543 1544 /* Ensure that I3's pattern can be the destination of combines. */ 1545 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, 1546 i1 && i2dest_in_i1src && i1_feeds_i3, 1547 &i3dest_killed)) 1548 { 1549 undo_all (); 1550 return 0; 1551 } 1552 1553 /* See if any of the insns is a MULT operation. Unless one is, we will 1554 reject a combination that is, since it must be slower. Be conservative 1555 here. */ 1556 if (GET_CODE (i2src) == MULT 1557 || (i1 != 0 && GET_CODE (i1src) == MULT) 1558 || (GET_CODE (PATTERN (i3)) == SET 1559 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) 1560 have_mult = 1; 1561 1562 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. 1563 We used to do this EXCEPT in one case: I3 has a post-inc in an 1564 output operand. However, that exception can give rise to insns like 1565 mov r3,(r3)+ 1566 which is a famous insn on the PDP-11 where the value of r3 used as the 1567 source was model-dependent. Avoid this sort of thing. */ 1568 1569#if 0 1570 if (!(GET_CODE (PATTERN (i3)) == SET 1571 && GET_CODE (SET_SRC (PATTERN (i3))) == REG 1572 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM 1573 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC 1574 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) 1575 /* It's not the exception. */ 1576#endif 1577#ifdef AUTO_INC_DEC 1578 for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) 1579 if (REG_NOTE_KIND (link) == REG_INC 1580 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) 1581 || (i1 != 0 1582 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) 1583 { 1584 undo_all (); 1585 return 0; 1586 } 1587#endif 1588 1589 /* See if the SETs in I1 or I2 need to be kept around in the merged 1590 instruction: whenever the value set there is still needed past I3. 1591 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3. 1592 1593 For the SET in I1, we have two cases: If I1 and I2 independently 1594 feed into I3, the set in I1 needs to be kept around if I1DEST dies 1595 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set 1596 in I1 needs to be kept around unless I1DEST dies or is set in either 1597 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions 1598 I1DEST. If so, we know I1 feeds into I2. */ 1599 1600 added_sets_2 = ! dead_or_set_p (i3, i2dest); 1601 1602 added_sets_1 1603 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) 1604 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); 1605 1606 /* If the set in I2 needs to be kept around, we must make a copy of 1607 PATTERN (I2), so that when we substitute I1SRC for I1DEST in 1608 PATTERN (I2), we are only substituting for the original I1DEST, not into 1609 an already-substituted copy. This also prevents making self-referential 1610 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to 1611 I2DEST. */ 1612 1613 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL 1614 ? gen_rtx_SET (VOIDmode, i2dest, i2src) 1615 : PATTERN (i2)); 1616 1617 if (added_sets_2) 1618 i2pat = copy_rtx (i2pat); 1619 1620 combine_merges++; 1621 1622 /* Substitute in the latest insn for the regs set by the earlier ones. */ 1623 1624 maxreg = max_reg_num (); 1625 1626 subst_insn = i3; 1627 1628 /* It is possible that the source of I2 or I1 may be performing an 1629 unneeded operation, such as a ZERO_EXTEND of something that is known 1630 to have the high part zero. Handle that case by letting subst look at 1631 the innermost one of them. 1632 1633 Another way to do this would be to have a function that tries to 1634 simplify a single insn instead of merging two or more insns. We don't 1635 do this because of the potential of infinite loops and because 1636 of the potential extra memory required. However, doing it the way 1637 we are is a bit of a kludge and doesn't catch all cases. 1638 1639 But only do this if -fexpensive-optimizations since it slows things down 1640 and doesn't usually win. */ 1641 1642 if (flag_expensive_optimizations) 1643 { 1644 /* Pass pc_rtx so no substitutions are done, just simplifications. 1645 The cases that we are interested in here do not involve the few 1646 cases were is_replaced is checked. */ 1647 if (i1) 1648 { 1649 subst_low_cuid = INSN_CUID (i1); 1650 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); 1651 } 1652 else 1653 { 1654 subst_low_cuid = INSN_CUID (i2); 1655 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); 1656 } 1657 1658 undobuf.previous_undos = undobuf.undos; 1659 } 1660 1661#ifndef HAVE_cc0 1662 /* Many machines that don't use CC0 have insns that can both perform an 1663 arithmetic operation and set the condition code. These operations will 1664 be represented as a PARALLEL with the first element of the vector 1665 being a COMPARE of an arithmetic operation with the constant zero. 1666 The second element of the vector will set some pseudo to the result 1667 of the same arithmetic operation. If we simplify the COMPARE, we won't 1668 match such a pattern and so will generate an extra insn. Here we test 1669 for this case, where both the comparison and the operation result are 1670 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with 1671 I2SRC. Later we will make the PARALLEL that contains I2. */ 1672 1673 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET 1674 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE 1675 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx 1676 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) 1677 { 1678#ifdef EXTRA_CC_MODES 1679 rtx *cc_use; 1680 enum machine_mode compare_mode; 1681#endif 1682 1683 newpat = PATTERN (i3); 1684 SUBST (XEXP (SET_SRC (newpat), 0), i2src); 1685 1686 i2_is_used = 1; 1687 1688#ifdef EXTRA_CC_MODES 1689 /* See if a COMPARE with the operand we substituted in should be done 1690 with the mode that is currently being used. If not, do the same 1691 processing we do in `subst' for a SET; namely, if the destination 1692 is used only once, try to replace it with a register of the proper 1693 mode and also replace the COMPARE. */ 1694 if (undobuf.other_insn == 0 1695 && (cc_use = find_single_use (SET_DEST (newpat), i3, 1696 &undobuf.other_insn)) 1697 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), 1698 i2src, const0_rtx)) 1699 != GET_MODE (SET_DEST (newpat)))) 1700 { 1701 int regno = REGNO (SET_DEST (newpat)); 1702 rtx new_dest = gen_rtx_REG (compare_mode, regno); 1703 1704 if (regno < FIRST_PSEUDO_REGISTER 1705 || (REG_N_SETS (regno) == 1 && ! added_sets_2 1706 && ! REG_USERVAR_P (SET_DEST (newpat)))) 1707 { 1708 if (regno >= FIRST_PSEUDO_REGISTER) 1709 SUBST (regno_reg_rtx[regno], new_dest); 1710 1711 SUBST (SET_DEST (newpat), new_dest); 1712 SUBST (XEXP (*cc_use, 0), new_dest); 1713 SUBST (SET_SRC (newpat), 1714 gen_rtx_combine (COMPARE, compare_mode, 1715 i2src, const0_rtx)); 1716 } 1717 else 1718 undobuf.other_insn = 0; 1719 } 1720#endif 1721 } 1722 else 1723#endif 1724 { 1725 n_occurrences = 0; /* `subst' counts here */ 1726 1727 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we 1728 need to make a unique copy of I2SRC each time we substitute it 1729 to avoid self-referential rtl. */ 1730 1731 subst_low_cuid = INSN_CUID (i2); 1732 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 1733 ! i1_feeds_i3 && i1dest_in_i1src); 1734 undobuf.previous_undos = undobuf.undos; 1735 1736 /* Record whether i2's body now appears within i3's body. */ 1737 i2_is_used = n_occurrences; 1738 } 1739 1740 /* If we already got a failure, don't try to do more. Otherwise, 1741 try to substitute in I1 if we have it. */ 1742 1743 if (i1 && GET_CODE (newpat) != CLOBBER) 1744 { 1745 /* Before we can do this substitution, we must redo the test done 1746 above (see detailed comments there) that ensures that I1DEST 1747 isn't mentioned in any SETs in NEWPAT that are field assignments. */ 1748 1749 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 1750 0, NULL_PTR)) 1751 { 1752 undo_all (); 1753 return 0; 1754 } 1755 1756 n_occurrences = 0; 1757 subst_low_cuid = INSN_CUID (i1); 1758 newpat = subst (newpat, i1dest, i1src, 0, 0); 1759 undobuf.previous_undos = undobuf.undos; 1760 } 1761 1762 /* Fail if an autoincrement side-effect has been duplicated. Be careful 1763 to count all the ways that I2SRC and I1SRC can be used. */ 1764 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 1765 && i2_is_used + added_sets_2 > 1) 1766 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 1767 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) 1768 > 1)) 1769 /* Fail if we tried to make a new register (we used to abort, but there's 1770 really no reason to). */ 1771 || max_reg_num () != maxreg 1772 /* Fail if we couldn't do something and have a CLOBBER. */ 1773 || GET_CODE (newpat) == CLOBBER 1774 /* Fail if this new pattern is a MULT and we didn't have one before 1775 at the outer level. */ 1776 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT 1777 && ! have_mult)) 1778 { 1779 undo_all (); 1780 return 0; 1781 } 1782 1783 /* If the actions of the earlier insns must be kept 1784 in addition to substituting them into the latest one, 1785 we must make a new PARALLEL for the latest insn 1786 to hold additional the SETs. */ 1787 1788 if (added_sets_1 || added_sets_2) 1789 { 1790 combine_extras++; 1791 1792 if (GET_CODE (newpat) == PARALLEL) 1793 { 1794 rtvec old = XVEC (newpat, 0); 1795 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2; 1796 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 1797 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem, 1798 sizeof (old->elem[0]) * old->num_elem); 1799 } 1800 else 1801 { 1802 rtx old = newpat; 1803 total_sets = 1 + added_sets_1 + added_sets_2; 1804 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 1805 XVECEXP (newpat, 0, 0) = old; 1806 } 1807 1808 if (added_sets_1) 1809 XVECEXP (newpat, 0, --total_sets) 1810 = (GET_CODE (PATTERN (i1)) == PARALLEL 1811 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1)); 1812 1813 if (added_sets_2) 1814 { 1815 /* If there is no I1, use I2's body as is. We used to also not do 1816 the subst call below if I2 was substituted into I3, 1817 but that could lose a simplification. */ 1818 if (i1 == 0) 1819 XVECEXP (newpat, 0, --total_sets) = i2pat; 1820 else 1821 /* See comment where i2pat is assigned. */ 1822 XVECEXP (newpat, 0, --total_sets) 1823 = subst (i2pat, i1dest, i1src, 0, 0); 1824 } 1825 } 1826 1827 /* We come here when we are replacing a destination in I2 with the 1828 destination of I3. */ 1829 validate_replacement: 1830 1831 /* Note which hard regs this insn has as inputs. */ 1832 mark_used_regs_combine (newpat); 1833 1834 /* Is the result of combination a valid instruction? */ 1835 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 1836 1837 /* If the result isn't valid, see if it is a PARALLEL of two SETs where 1838 the second SET's destination is a register that is unused. In that case, 1839 we just need the first SET. This can occur when simplifying a divmod 1840 insn. We *must* test for this case here because the code below that 1841 splits two independent SETs doesn't handle this case correctly when it 1842 updates the register status. Also check the case where the first 1843 SET's destination is unused. That would not cause incorrect code, but 1844 does cause an unneeded insn to remain. */ 1845 1846 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL 1847 && XVECLEN (newpat, 0) == 2 1848 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 1849 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 1850 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG 1851 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1))) 1852 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1))) 1853 && asm_noperands (newpat) < 0) 1854 { 1855 newpat = XVECEXP (newpat, 0, 0); 1856 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 1857 } 1858 1859 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL 1860 && XVECLEN (newpat, 0) == 2 1861 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 1862 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 1863 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG 1864 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0))) 1865 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0))) 1866 && asm_noperands (newpat) < 0) 1867 { 1868 newpat = XVECEXP (newpat, 0, 1); 1869 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 1870 } 1871 1872 /* If we were combining three insns and the result is a simple SET 1873 with no ASM_OPERANDS that wasn't recognized, try to split it into two 1874 insns. There are two ways to do this. It can be split using a 1875 machine-specific method (like when you have an addition of a large 1876 constant) or by combine in the function find_split_point. */ 1877 1878 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET 1879 && asm_noperands (newpat) < 0) 1880 { 1881 rtx m_split, *split; 1882 rtx ni2dest = i2dest; 1883 1884 /* See if the MD file can split NEWPAT. If it can't, see if letting it 1885 use I2DEST as a scratch register will help. In the latter case, 1886 convert I2DEST to the mode of the source of NEWPAT if we can. */ 1887 1888 m_split = split_insns (newpat, i3); 1889 1890 /* We can only use I2DEST as a scratch reg if it doesn't overlap any 1891 inputs of NEWPAT. */ 1892 1893 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be 1894 possible to try that as a scratch reg. This would require adding 1895 more code to make it work though. */ 1896 1897 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat)) 1898 { 1899 /* If I2DEST is a hard register or the only use of a pseudo, 1900 we can change its mode. */ 1901 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest) 1902 && GET_MODE (SET_DEST (newpat)) != VOIDmode 1903 && GET_CODE (i2dest) == REG 1904 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER 1905 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2 1906 && ! REG_USERVAR_P (i2dest)))) 1907 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)), 1908 REGNO (i2dest)); 1909 1910 m_split = split_insns 1911 (gen_rtx_PARALLEL (VOIDmode, 1912 gen_rtvec (2, newpat, 1913 gen_rtx_CLOBBER (VOIDmode, 1914 ni2dest))), 1915 i3); 1916 } 1917 1918 if (m_split && GET_CODE (m_split) == SEQUENCE 1919 && XVECLEN (m_split, 0) == 2 1920 && (next_real_insn (i2) == i3 1921 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)), 1922 INSN_CUID (i2)))) 1923 { 1924 rtx i2set, i3set; 1925 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1)); 1926 newi2pat = PATTERN (XVECEXP (m_split, 0, 0)); 1927 1928 i3set = single_set (XVECEXP (m_split, 0, 1)); 1929 i2set = single_set (XVECEXP (m_split, 0, 0)); 1930 1931 /* In case we changed the mode of I2DEST, replace it in the 1932 pseudo-register table here. We can't do it above in case this 1933 code doesn't get executed and we do a split the other way. */ 1934 1935 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 1936 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest); 1937 1938 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 1939 1940 /* If I2 or I3 has multiple SETs, we won't know how to track 1941 register status, so don't use these insns. If I2's destination 1942 is used between I2 and I3, we also can't use these insns. */ 1943 1944 if (i2_code_number >= 0 && i2set && i3set 1945 && (next_real_insn (i2) == i3 1946 || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) 1947 insn_code_number = recog_for_combine (&newi3pat, i3, 1948 &new_i3_notes); 1949 if (insn_code_number >= 0) 1950 newpat = newi3pat; 1951 1952 /* It is possible that both insns now set the destination of I3. 1953 If so, we must show an extra use of it. */ 1954 1955 if (insn_code_number >= 0) 1956 { 1957 rtx new_i3_dest = SET_DEST (i3set); 1958 rtx new_i2_dest = SET_DEST (i2set); 1959 1960 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT 1961 || GET_CODE (new_i3_dest) == STRICT_LOW_PART 1962 || GET_CODE (new_i3_dest) == SUBREG) 1963 new_i3_dest = XEXP (new_i3_dest, 0); 1964 1965 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT 1966 || GET_CODE (new_i2_dest) == STRICT_LOW_PART 1967 || GET_CODE (new_i2_dest) == SUBREG) 1968 new_i2_dest = XEXP (new_i2_dest, 0); 1969 1970 if (GET_CODE (new_i3_dest) == REG 1971 && GET_CODE (new_i2_dest) == REG 1972 && REGNO (new_i3_dest) == REGNO (new_i2_dest)) 1973 REG_N_SETS (REGNO (new_i2_dest))++; 1974 } 1975 } 1976 1977 /* If we can split it and use I2DEST, go ahead and see if that 1978 helps things be recognized. Verify that none of the registers 1979 are set between I2 and I3. */ 1980 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0 1981#ifdef HAVE_cc0 1982 && GET_CODE (i2dest) == REG 1983#endif 1984 /* We need I2DEST in the proper mode. If it is a hard register 1985 or the only use of a pseudo, we can change its mode. */ 1986 && (GET_MODE (*split) == GET_MODE (i2dest) 1987 || GET_MODE (*split) == VOIDmode 1988 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER 1989 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2 1990 && ! REG_USERVAR_P (i2dest))) 1991 && (next_real_insn (i2) == i3 1992 || ! use_crosses_set_p (*split, INSN_CUID (i2))) 1993 /* We can't overwrite I2DEST if its value is still used by 1994 NEWPAT. */ 1995 && ! reg_referenced_p (i2dest, newpat)) 1996 { 1997 rtx newdest = i2dest; 1998 enum rtx_code split_code = GET_CODE (*split); 1999 enum machine_mode split_mode = GET_MODE (*split); 2000 2001 /* Get NEWDEST as a register in the proper mode. We have already 2002 validated that we can do this. */ 2003 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) 2004 { 2005 newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); 2006 2007 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 2008 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest); 2009 } 2010 2011 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to 2012 an ASHIFT. This can occur if it was inside a PLUS and hence 2013 appeared to be a memory address. This is a kludge. */ 2014 if (split_code == MULT 2015 && GET_CODE (XEXP (*split, 1)) == CONST_INT 2016 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0) 2017 { 2018 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode, 2019 XEXP (*split, 0), GEN_INT (i))); 2020 /* Update split_code because we may not have a multiply 2021 anymore. */ 2022 split_code = GET_CODE (*split); 2023 } 2024 2025#ifdef INSN_SCHEDULING 2026 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should 2027 be written as a ZERO_EXTEND. */ 2028 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM) 2029 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode, 2030 XEXP (*split, 0))); 2031#endif 2032 2033 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split); 2034 SUBST (*split, newdest); 2035 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2036 2037 /* If the split point was a MULT and we didn't have one before, 2038 don't use one now. */ 2039 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) 2040 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2041 } 2042 } 2043 2044 /* Check for a case where we loaded from memory in a narrow mode and 2045 then sign extended it, but we need both registers. In that case, 2046 we have a PARALLEL with both loads from the same memory location. 2047 We can split this into a load from memory followed by a register-register 2048 copy. This saves at least one insn, more if register allocation can 2049 eliminate the copy. 2050 2051 We cannot do this if the destination of the second assignment is 2052 a register that we have already assumed is zero-extended. Similarly 2053 for a SUBREG of such a register. */ 2054 2055 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 2056 && GET_CODE (newpat) == PARALLEL 2057 && XVECLEN (newpat, 0) == 2 2058 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2059 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND 2060 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2061 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2062 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) 2063 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2064 INSN_CUID (i2)) 2065 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 2066 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 2067 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)), 2068 (GET_CODE (temp) == REG 2069 && reg_nonzero_bits[REGNO (temp)] != 0 2070 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD 2071 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT 2072 && (reg_nonzero_bits[REGNO (temp)] 2073 != GET_MODE_MASK (word_mode)))) 2074 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG 2075 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), 2076 (GET_CODE (temp) == REG 2077 && reg_nonzero_bits[REGNO (temp)] != 0 2078 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD 2079 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT 2080 && (reg_nonzero_bits[REGNO (temp)] 2081 != GET_MODE_MASK (word_mode))))) 2082 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), 2083 SET_SRC (XVECEXP (newpat, 0, 1))) 2084 && ! find_reg_note (i3, REG_UNUSED, 2085 SET_DEST (XVECEXP (newpat, 0, 0)))) 2086 { 2087 rtx ni2dest; 2088 2089 newi2pat = XVECEXP (newpat, 0, 0); 2090 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); 2091 newpat = XVECEXP (newpat, 0, 1); 2092 SUBST (SET_SRC (newpat), 2093 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest)); 2094 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2095 2096 if (i2_code_number >= 0) 2097 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2098 2099 if (insn_code_number >= 0) 2100 { 2101 rtx insn; 2102 rtx link; 2103 2104 /* If we will be able to accept this, we have made a change to the 2105 destination of I3. This can invalidate a LOG_LINKS pointing 2106 to I3. No other part of combine.c makes such a transformation. 2107 2108 The new I3 will have a destination that was previously the 2109 destination of I1 or I2 and which was used in i2 or I3. Call 2110 distribute_links to make a LOG_LINK from the next use of 2111 that destination. */ 2112 2113 PATTERN (i3) = newpat; 2114 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX)); 2115 2116 /* I3 now uses what used to be its destination and which is 2117 now I2's destination. That means we need a LOG_LINK from 2118 I3 to I2. But we used to have one, so we still will. 2119 2120 However, some later insn might be using I2's dest and have 2121 a LOG_LINK pointing at I3. We must remove this link. 2122 The simplest way to remove the link is to point it at I1, 2123 which we know will be a NOTE. */ 2124 2125 for (insn = NEXT_INSN (i3); 2126 insn && (this_basic_block == n_basic_blocks - 1 2127 || insn != BLOCK_HEAD (this_basic_block + 1)); 2128 insn = NEXT_INSN (insn)) 2129 { 2130 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' 2131 && reg_referenced_p (ni2dest, PATTERN (insn))) 2132 { 2133 for (link = LOG_LINKS (insn); link; 2134 link = XEXP (link, 1)) 2135 if (XEXP (link, 0) == i3) 2136 XEXP (link, 0) = i1; 2137 2138 break; 2139 } 2140 } 2141 } 2142 } 2143 2144 /* Similarly, check for a case where we have a PARALLEL of two independent 2145 SETs but we started with three insns. In this case, we can do the sets 2146 as two separate insns. This case occurs when some SET allows two 2147 other insns to combine, but the destination of that SET is still live. */ 2148 2149 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 2150 && GET_CODE (newpat) == PARALLEL 2151 && XVECLEN (newpat, 0) == 2 2152 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2153 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT 2154 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART 2155 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2156 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 2157 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 2158 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2159 INSN_CUID (i2)) 2160 /* Don't pass sets with (USE (MEM ...)) dests to the following. */ 2161 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE 2162 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE 2163 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), 2164 XVECEXP (newpat, 0, 0)) 2165 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), 2166 XVECEXP (newpat, 0, 1))) 2167 { 2168 /* Normally, it doesn't matter which of the two is done first, 2169 but it does if one references cc0. In that case, it has to 2170 be first. */ 2171#ifdef HAVE_cc0 2172 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))) 2173 { 2174 newi2pat = XVECEXP (newpat, 0, 0); 2175 newpat = XVECEXP (newpat, 0, 1); 2176 } 2177 else 2178#endif 2179 { 2180 newi2pat = XVECEXP (newpat, 0, 1); 2181 newpat = XVECEXP (newpat, 0, 0); 2182 } 2183 2184 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2185 2186 if (i2_code_number >= 0) 2187 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2188 } 2189 2190 /* If it still isn't recognized, fail and change things back the way they 2191 were. */ 2192 if ((insn_code_number < 0 2193 /* Is the result a reasonable ASM_OPERANDS? */ 2194 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) 2195 { 2196 undo_all (); 2197 return 0; 2198 } 2199 2200 /* If we had to change another insn, make sure it is valid also. */ 2201 if (undobuf.other_insn) 2202 { 2203 rtx other_pat = PATTERN (undobuf.other_insn); 2204 rtx new_other_notes; 2205 rtx note, next; 2206 2207 CLEAR_HARD_REG_SET (newpat_used_regs); 2208 2209 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, 2210 &new_other_notes); 2211 2212 if (other_code_number < 0 && ! check_asm_operands (other_pat)) 2213 { 2214 undo_all (); 2215 return 0; 2216 } 2217 2218 PATTERN (undobuf.other_insn) = other_pat; 2219 2220 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they 2221 are still valid. Then add any non-duplicate notes added by 2222 recog_for_combine. */ 2223 for (note = REG_NOTES (undobuf.other_insn); note; note = next) 2224 { 2225 next = XEXP (note, 1); 2226 2227 if (REG_NOTE_KIND (note) == REG_UNUSED 2228 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) 2229 { 2230 if (GET_CODE (XEXP (note, 0)) == REG) 2231 REG_N_DEATHS (REGNO (XEXP (note, 0)))--; 2232 2233 remove_note (undobuf.other_insn, note); 2234 } 2235 } 2236 2237 for (note = new_other_notes; note; note = XEXP (note, 1)) 2238 if (GET_CODE (XEXP (note, 0)) == REG) 2239 REG_N_DEATHS (REGNO (XEXP (note, 0)))++; 2240 2241 distribute_notes (new_other_notes, undobuf.other_insn, 2242 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX); 2243 } 2244 2245 /* We now know that we can do this combination. Merge the insns and 2246 update the status of registers and LOG_LINKS. */ 2247 2248 { 2249 rtx i3notes, i2notes, i1notes = 0; 2250 rtx i3links, i2links, i1links = 0; 2251 rtx midnotes = 0; 2252 register int regno; 2253 /* Compute which registers we expect to eliminate. newi2pat may be setting 2254 either i3dest or i2dest, so we must check it. Also, i1dest may be the 2255 same as i3dest, in which case newi2pat may be setting i1dest. */ 2256 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat)) 2257 || i2dest_in_i2src || i2dest_in_i1src 2258 ? 0 : i2dest); 2259 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src 2260 || (newi2pat && reg_set_p (i1dest, newi2pat)) 2261 ? 0 : i1dest); 2262 2263 /* Get the old REG_NOTES and LOG_LINKS from all our insns and 2264 clear them. */ 2265 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); 2266 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); 2267 if (i1) 2268 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); 2269 2270 /* Ensure that we do not have something that should not be shared but 2271 occurs multiple times in the new insns. Check this by first 2272 resetting all the `used' flags and then copying anything is shared. */ 2273 2274 reset_used_flags (i3notes); 2275 reset_used_flags (i2notes); 2276 reset_used_flags (i1notes); 2277 reset_used_flags (newpat); 2278 reset_used_flags (newi2pat); 2279 if (undobuf.other_insn) 2280 reset_used_flags (PATTERN (undobuf.other_insn)); 2281 2282 i3notes = copy_rtx_if_shared (i3notes); 2283 i2notes = copy_rtx_if_shared (i2notes); 2284 i1notes = copy_rtx_if_shared (i1notes); 2285 newpat = copy_rtx_if_shared (newpat); 2286 newi2pat = copy_rtx_if_shared (newi2pat); 2287 if (undobuf.other_insn) 2288 reset_used_flags (PATTERN (undobuf.other_insn)); 2289 2290 INSN_CODE (i3) = insn_code_number; 2291 PATTERN (i3) = newpat; 2292 if (undobuf.other_insn) 2293 INSN_CODE (undobuf.other_insn) = other_code_number; 2294 2295 /* We had one special case above where I2 had more than one set and 2296 we replaced a destination of one of those sets with the destination 2297 of I3. In that case, we have to update LOG_LINKS of insns later 2298 in this basic block. Note that this (expensive) case is rare. 2299 2300 Also, in this case, we must pretend that all REG_NOTEs for I2 2301 actually came from I3, so that REG_UNUSED notes from I2 will be 2302 properly handled. */ 2303 2304 if (i3_subst_into_i2) 2305 { 2306 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) 2307 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG 2308 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest 2309 && ! find_reg_note (i2, REG_UNUSED, 2310 SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) 2311 for (temp = NEXT_INSN (i2); 2312 temp && (this_basic_block == n_basic_blocks - 1 2313 || BLOCK_HEAD (this_basic_block) != temp); 2314 temp = NEXT_INSN (temp)) 2315 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i') 2316 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1)) 2317 if (XEXP (link, 0) == i2) 2318 XEXP (link, 0) = i3; 2319 2320 if (i3notes) 2321 { 2322 rtx link = i3notes; 2323 while (XEXP (link, 1)) 2324 link = XEXP (link, 1); 2325 XEXP (link, 1) = i2notes; 2326 } 2327 else 2328 i3notes = i2notes; 2329 i2notes = 0; 2330 } 2331 2332 LOG_LINKS (i3) = 0; 2333 REG_NOTES (i3) = 0; 2334 LOG_LINKS (i2) = 0; 2335 REG_NOTES (i2) = 0; 2336 2337 if (newi2pat) 2338 { 2339 INSN_CODE (i2) = i2_code_number; 2340 PATTERN (i2) = newi2pat; 2341 } 2342 else 2343 { 2344 PUT_CODE (i2, NOTE); 2345 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; 2346 NOTE_SOURCE_FILE (i2) = 0; 2347 } 2348 2349 if (i1) 2350 { 2351 LOG_LINKS (i1) = 0; 2352 REG_NOTES (i1) = 0; 2353 PUT_CODE (i1, NOTE); 2354 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED; 2355 NOTE_SOURCE_FILE (i1) = 0; 2356 } 2357 2358 /* Get death notes for everything that is now used in either I3 or 2359 I2 and used to die in a previous insn. If we built two new 2360 patterns, move from I1 to I2 then I2 to I3 so that we get the 2361 proper movement on registers that I2 modifies. */ 2362 2363 if (newi2pat) 2364 { 2365 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes); 2366 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes); 2367 } 2368 else 2369 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2), 2370 i3, &midnotes); 2371 2372 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ 2373 if (i3notes) 2374 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX, 2375 elim_i2, elim_i1); 2376 if (i2notes) 2377 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX, 2378 elim_i2, elim_i1); 2379 if (i1notes) 2380 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX, 2381 elim_i2, elim_i1); 2382 if (midnotes) 2383 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2384 elim_i2, elim_i1); 2385 2386 /* Distribute any notes added to I2 or I3 by recog_for_combine. We 2387 know these are REG_UNUSED and want them to go to the desired insn, 2388 so we always pass it as i3. We have not counted the notes in 2389 reg_n_deaths yet, so we need to do so now. */ 2390 2391 if (newi2pat && new_i2_notes) 2392 { 2393 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1)) 2394 if (GET_CODE (XEXP (temp, 0)) == REG) 2395 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; 2396 2397 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2398 } 2399 2400 if (new_i3_notes) 2401 { 2402 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1)) 2403 if (GET_CODE (XEXP (temp, 0)) == REG) 2404 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; 2405 2406 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX); 2407 } 2408 2409 /* If I3DEST was used in I3SRC, it really died in I3. We may need to 2410 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets 2411 I3DEST, the death must be somewhere before I2, not I3. If we passed I3 2412 in that case, it might delete I2. Similarly for I2 and I1. 2413 Show an additional death due to the REG_DEAD note we make here. If 2414 we discard it in distribute_notes, we will decrement it again. */ 2415 2416 if (i3dest_killed) 2417 { 2418 if (GET_CODE (i3dest_killed) == REG) 2419 REG_N_DEATHS (REGNO (i3dest_killed))++; 2420 2421 if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) 2422 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, 2423 NULL_RTX), 2424 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1); 2425 else 2426 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, 2427 NULL_RTX), 2428 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2429 elim_i2, elim_i1); 2430 } 2431 2432 if (i2dest_in_i2src) 2433 { 2434 if (GET_CODE (i2dest) == REG) 2435 REG_N_DEATHS (REGNO (i2dest))++; 2436 2437 if (newi2pat && reg_set_p (i2dest, newi2pat)) 2438 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), 2439 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2440 else 2441 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), 2442 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2443 NULL_RTX, NULL_RTX); 2444 } 2445 2446 if (i1dest_in_i1src) 2447 { 2448 if (GET_CODE (i1dest) == REG) 2449 REG_N_DEATHS (REGNO (i1dest))++; 2450 2451 if (newi2pat && reg_set_p (i1dest, newi2pat)) 2452 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), 2453 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2454 else 2455 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), 2456 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2457 NULL_RTX, NULL_RTX); 2458 } 2459 2460 distribute_links (i3links); 2461 distribute_links (i2links); 2462 distribute_links (i1links); 2463 2464 if (GET_CODE (i2dest) == REG) 2465 { 2466 rtx link; 2467 rtx i2_insn = 0, i2_val = 0, set; 2468 2469 /* The insn that used to set this register doesn't exist, and 2470 this life of the register may not exist either. See if one of 2471 I3's links points to an insn that sets I2DEST. If it does, 2472 that is now the last known value for I2DEST. If we don't update 2473 this and I2 set the register to a value that depended on its old 2474 contents, we will get confused. If this insn is used, thing 2475 will be set correctly in combine_instructions. */ 2476 2477 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) 2478 if ((set = single_set (XEXP (link, 0))) != 0 2479 && rtx_equal_p (i2dest, SET_DEST (set))) 2480 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set); 2481 2482 record_value_for_reg (i2dest, i2_insn, i2_val); 2483 2484 /* If the reg formerly set in I2 died only once and that was in I3, 2485 zero its use count so it won't make `reload' do any work. */ 2486 if (! added_sets_2 2487 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) 2488 && ! i2dest_in_i2src) 2489 { 2490 regno = REGNO (i2dest); 2491 REG_N_SETS (regno)--; 2492 if (REG_N_SETS (regno) == 0 2493 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, 2494 regno)) 2495 REG_N_REFS (regno) = 0; 2496 } 2497 } 2498 2499 if (i1 && GET_CODE (i1dest) == REG) 2500 { 2501 rtx link; 2502 rtx i1_insn = 0, i1_val = 0, set; 2503 2504 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) 2505 if ((set = single_set (XEXP (link, 0))) != 0 2506 && rtx_equal_p (i1dest, SET_DEST (set))) 2507 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set); 2508 2509 record_value_for_reg (i1dest, i1_insn, i1_val); 2510 2511 regno = REGNO (i1dest); 2512 if (! added_sets_1 && ! i1dest_in_i1src) 2513 { 2514 REG_N_SETS (regno)--; 2515 if (REG_N_SETS (regno) == 0 2516 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, 2517 regno)) 2518 REG_N_REFS (regno) = 0; 2519 } 2520 } 2521 2522 /* Update reg_nonzero_bits et al for any changes that may have been made 2523 to this insn. */ 2524 2525 note_stores (newpat, set_nonzero_bits_and_sign_copies); 2526 if (newi2pat) 2527 note_stores (newi2pat, set_nonzero_bits_and_sign_copies); 2528 2529 /* If I3 is now an unconditional jump, ensure that it has a 2530 BARRIER following it since it may have initially been a 2531 conditional jump. It may also be the last nonnote insn. */ 2532 2533 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3)) 2534 && ((temp = next_nonnote_insn (i3)) == NULL_RTX 2535 || GET_CODE (temp) != BARRIER)) 2536 emit_barrier_after (i3); 2537 } 2538 2539 combine_successes++; 2540 2541 /* Clear this here, so that subsequent get_last_value calls are not 2542 affected. */ 2543 subst_prev_insn = NULL_RTX; 2544 2545 if (added_links_insn 2546 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2)) 2547 && INSN_CUID (added_links_insn) < INSN_CUID (i3)) 2548 return added_links_insn; 2549 else 2550 return newi2pat ? i2 : i3; 2551} 2552 2553/* Undo all the modifications recorded in undobuf. */ 2554 2555static void 2556undo_all () 2557{ 2558 struct undo *undo, *next; 2559 2560 for (undo = undobuf.undos; undo; undo = next) 2561 { 2562 next = undo->next; 2563 if (undo->is_int) 2564 *undo->where.i = undo->old_contents.i; 2565 else 2566 *undo->where.r = undo->old_contents.r; 2567 2568 undo->next = undobuf.frees; 2569 undobuf.frees = undo; 2570 } 2571 2572 obfree (undobuf.storage); 2573 undobuf.undos = undobuf.previous_undos = 0; 2574 2575 /* Clear this here, so that subsequent get_last_value calls are not 2576 affected. */ 2577 subst_prev_insn = NULL_RTX; 2578} 2579 2580/* Find the innermost point within the rtx at LOC, possibly LOC itself, 2581 where we have an arithmetic expression and return that point. LOC will 2582 be inside INSN. 2583 2584 try_combine will call this function to see if an insn can be split into 2585 two insns. */ 2586 2587static rtx * 2588find_split_point (loc, insn) 2589 rtx *loc; 2590 rtx insn; 2591{ 2592 rtx x = *loc; 2593 enum rtx_code code = GET_CODE (x); 2594 rtx *split; 2595 int len = 0, pos, unsignedp; 2596 rtx inner; 2597 2598 /* First special-case some codes. */ 2599 switch (code) 2600 { 2601 case SUBREG: 2602#ifdef INSN_SCHEDULING 2603 /* If we are making a paradoxical SUBREG invalid, it becomes a split 2604 point. */ 2605 if (GET_CODE (SUBREG_REG (x)) == MEM) 2606 return loc; 2607#endif 2608 return find_split_point (&SUBREG_REG (x), insn); 2609 2610 case MEM: 2611#ifdef HAVE_lo_sum 2612 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it 2613 using LO_SUM and HIGH. */ 2614 if (GET_CODE (XEXP (x, 0)) == CONST 2615 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) 2616 { 2617 SUBST (XEXP (x, 0), 2618 gen_rtx_combine (LO_SUM, Pmode, 2619 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)), 2620 XEXP (x, 0))); 2621 return &XEXP (XEXP (x, 0), 0); 2622 } 2623#endif 2624 2625 /* If we have a PLUS whose second operand is a constant and the 2626 address is not valid, perhaps will can split it up using 2627 the machine-specific way to split large constants. We use 2628 the first pseudo-reg (one of the virtual regs) as a placeholder; 2629 it will not remain in the result. */ 2630 if (GET_CODE (XEXP (x, 0)) == PLUS 2631 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 2632 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) 2633 { 2634 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; 2635 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)), 2636 subst_insn); 2637 2638 /* This should have produced two insns, each of which sets our 2639 placeholder. If the source of the second is a valid address, 2640 we can make put both sources together and make a split point 2641 in the middle. */ 2642 2643 if (seq && XVECLEN (seq, 0) == 2 2644 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN 2645 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET 2646 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg 2647 && ! reg_mentioned_p (reg, 2648 SET_SRC (PATTERN (XVECEXP (seq, 0, 0)))) 2649 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN 2650 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET 2651 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg 2652 && memory_address_p (GET_MODE (x), 2653 SET_SRC (PATTERN (XVECEXP (seq, 0, 1))))) 2654 { 2655 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0))); 2656 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1))); 2657 2658 /* Replace the placeholder in SRC2 with SRC1. If we can 2659 find where in SRC2 it was placed, that can become our 2660 split point and we can replace this address with SRC2. 2661 Just try two obvious places. */ 2662 2663 src2 = replace_rtx (src2, reg, src1); 2664 split = 0; 2665 if (XEXP (src2, 0) == src1) 2666 split = &XEXP (src2, 0); 2667 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' 2668 && XEXP (XEXP (src2, 0), 0) == src1) 2669 split = &XEXP (XEXP (src2, 0), 0); 2670 2671 if (split) 2672 { 2673 SUBST (XEXP (x, 0), src2); 2674 return split; 2675 } 2676 } 2677 2678 /* If that didn't work, perhaps the first operand is complex and 2679 needs to be computed separately, so make a split point there. 2680 This will occur on machines that just support REG + CONST 2681 and have a constant moved through some previous computation. */ 2682 2683 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o' 2684 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG 2685 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0)))) 2686 == 'o'))) 2687 return &XEXP (XEXP (x, 0), 0); 2688 } 2689 break; 2690 2691 case SET: 2692#ifdef HAVE_cc0 2693 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a 2694 ZERO_EXTRACT, the most likely reason why this doesn't match is that 2695 we need to put the operand into a register. So split at that 2696 point. */ 2697 2698 if (SET_DEST (x) == cc0_rtx 2699 && GET_CODE (SET_SRC (x)) != COMPARE 2700 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT 2701 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o' 2702 && ! (GET_CODE (SET_SRC (x)) == SUBREG 2703 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o')) 2704 return &SET_SRC (x); 2705#endif 2706 2707 /* See if we can split SET_SRC as it stands. */ 2708 split = find_split_point (&SET_SRC (x), insn); 2709 if (split && split != &SET_SRC (x)) 2710 return split; 2711 2712 /* See if we can split SET_DEST as it stands. */ 2713 split = find_split_point (&SET_DEST (x), insn); 2714 if (split && split != &SET_DEST (x)) 2715 return split; 2716 2717 /* See if this is a bitfield assignment with everything constant. If 2718 so, this is an IOR of an AND, so split it into that. */ 2719 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 2720 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))) 2721 <= HOST_BITS_PER_WIDE_INT) 2722 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT 2723 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT 2724 && GET_CODE (SET_SRC (x)) == CONST_INT 2725 && ((INTVAL (XEXP (SET_DEST (x), 1)) 2726 + INTVAL (XEXP (SET_DEST (x), 2))) 2727 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))) 2728 && ! side_effects_p (XEXP (SET_DEST (x), 0))) 2729 { 2730 int pos = INTVAL (XEXP (SET_DEST (x), 2)); 2731 int len = INTVAL (XEXP (SET_DEST (x), 1)); 2732 int src = INTVAL (SET_SRC (x)); 2733 rtx dest = XEXP (SET_DEST (x), 0); 2734 enum machine_mode mode = GET_MODE (dest); 2735 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1; 2736 2737 if (BITS_BIG_ENDIAN) 2738 pos = GET_MODE_BITSIZE (mode) - len - pos; 2739 2740 if ((unsigned HOST_WIDE_INT) src == mask) 2741 SUBST (SET_SRC (x), 2742 gen_binary (IOR, mode, dest, GEN_INT (src << pos))); 2743 else 2744 SUBST (SET_SRC (x), 2745 gen_binary (IOR, mode, 2746 gen_binary (AND, mode, dest, 2747 GEN_INT (~ (mask << pos) 2748 & GET_MODE_MASK (mode))), 2749 GEN_INT (src << pos))); 2750 2751 SUBST (SET_DEST (x), dest); 2752 2753 split = find_split_point (&SET_SRC (x), insn); 2754 if (split && split != &SET_SRC (x)) 2755 return split; 2756 } 2757 2758 /* Otherwise, see if this is an operation that we can split into two. 2759 If so, try to split that. */ 2760 code = GET_CODE (SET_SRC (x)); 2761 2762 switch (code) 2763 { 2764 case AND: 2765 /* If we are AND'ing with a large constant that is only a single 2766 bit and the result is only being used in a context where we 2767 need to know if it is zero or non-zero, replace it with a bit 2768 extraction. This will avoid the large constant, which might 2769 have taken more than one insn to make. If the constant were 2770 not a valid argument to the AND but took only one insn to make, 2771 this is no worse, but if it took more than one insn, it will 2772 be better. */ 2773 2774 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2775 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 2776 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7 2777 && GET_CODE (SET_DEST (x)) == REG 2778 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0 2779 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) 2780 && XEXP (*split, 0) == SET_DEST (x) 2781 && XEXP (*split, 1) == const0_rtx) 2782 { 2783 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), 2784 XEXP (SET_SRC (x), 0), 2785 pos, NULL_RTX, 1, 1, 0, 0); 2786 if (extraction != 0) 2787 { 2788 SUBST (SET_SRC (x), extraction); 2789 return find_split_point (loc, insn); 2790 } 2791 } 2792 break; 2793 2794 case NE: 2795 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X 2796 is known to be on, this can be converted into a NEG of a shift. */ 2797 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx 2798 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) 2799 && 1 <= (pos = exact_log2 2800 (nonzero_bits (XEXP (SET_SRC (x), 0), 2801 GET_MODE (XEXP (SET_SRC (x), 0)))))) 2802 { 2803 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); 2804 2805 SUBST (SET_SRC (x), 2806 gen_rtx_combine (NEG, mode, 2807 gen_rtx_combine (LSHIFTRT, mode, 2808 XEXP (SET_SRC (x), 0), 2809 GEN_INT (pos)))); 2810 2811 split = find_split_point (&SET_SRC (x), insn); 2812 if (split && split != &SET_SRC (x)) 2813 return split; 2814 } 2815 break; 2816 2817 case SIGN_EXTEND: 2818 inner = XEXP (SET_SRC (x), 0); 2819 2820 /* We can't optimize if either mode is a partial integer 2821 mode as we don't know how many bits are significant 2822 in those modes. */ 2823 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT 2824 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) 2825 break; 2826 2827 pos = 0; 2828 len = GET_MODE_BITSIZE (GET_MODE (inner)); 2829 unsignedp = 0; 2830 break; 2831 2832 case SIGN_EXTRACT: 2833 case ZERO_EXTRACT: 2834 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2835 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT) 2836 { 2837 inner = XEXP (SET_SRC (x), 0); 2838 len = INTVAL (XEXP (SET_SRC (x), 1)); 2839 pos = INTVAL (XEXP (SET_SRC (x), 2)); 2840 2841 if (BITS_BIG_ENDIAN) 2842 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos; 2843 unsignedp = (code == ZERO_EXTRACT); 2844 } 2845 break; 2846 2847 default: 2848 break; 2849 } 2850 2851 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner))) 2852 { 2853 enum machine_mode mode = GET_MODE (SET_SRC (x)); 2854 2855 /* For unsigned, we have a choice of a shift followed by an 2856 AND or two shifts. Use two shifts for field sizes where the 2857 constant might be too large. We assume here that we can 2858 always at least get 8-bit constants in an AND insn, which is 2859 true for every current RISC. */ 2860 2861 if (unsignedp && len <= 8) 2862 { 2863 SUBST (SET_SRC (x), 2864 gen_rtx_combine 2865 (AND, mode, 2866 gen_rtx_combine (LSHIFTRT, mode, 2867 gen_lowpart_for_combine (mode, inner), 2868 GEN_INT (pos)), 2869 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1))); 2870 2871 split = find_split_point (&SET_SRC (x), insn); 2872 if (split && split != &SET_SRC (x)) 2873 return split; 2874 } 2875 else 2876 { 2877 SUBST (SET_SRC (x), 2878 gen_rtx_combine 2879 (unsignedp ? LSHIFTRT : ASHIFTRT, mode, 2880 gen_rtx_combine (ASHIFT, mode, 2881 gen_lowpart_for_combine (mode, inner), 2882 GEN_INT (GET_MODE_BITSIZE (mode) 2883 - len - pos)), 2884 GEN_INT (GET_MODE_BITSIZE (mode) - len))); 2885 2886 split = find_split_point (&SET_SRC (x), insn); 2887 if (split && split != &SET_SRC (x)) 2888 return split; 2889 } 2890 } 2891 2892 /* See if this is a simple operation with a constant as the second 2893 operand. It might be that this constant is out of range and hence 2894 could be used as a split point. */ 2895 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' 2896 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' 2897 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<') 2898 && CONSTANT_P (XEXP (SET_SRC (x), 1)) 2899 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o' 2900 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG 2901 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0)))) 2902 == 'o')))) 2903 return &XEXP (SET_SRC (x), 1); 2904 2905 /* Finally, see if this is a simple operation with its first operand 2906 not in a register. The operation might require this operand in a 2907 register, so return it as a split point. We can always do this 2908 because if the first operand were another operation, we would have 2909 already found it as a split point. */ 2910 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' 2911 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' 2912 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<' 2913 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1') 2914 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) 2915 return &XEXP (SET_SRC (x), 0); 2916 2917 return 0; 2918 2919 case AND: 2920 case IOR: 2921 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, 2922 it is better to write this as (not (ior A B)) so we can split it. 2923 Similarly for IOR. */ 2924 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) 2925 { 2926 SUBST (*loc, 2927 gen_rtx_combine (NOT, GET_MODE (x), 2928 gen_rtx_combine (code == IOR ? AND : IOR, 2929 GET_MODE (x), 2930 XEXP (XEXP (x, 0), 0), 2931 XEXP (XEXP (x, 1), 0)))); 2932 return find_split_point (loc, insn); 2933 } 2934 2935 /* Many RISC machines have a large set of logical insns. If the 2936 second operand is a NOT, put it first so we will try to split the 2937 other operand first. */ 2938 if (GET_CODE (XEXP (x, 1)) == NOT) 2939 { 2940 rtx tem = XEXP (x, 0); 2941 SUBST (XEXP (x, 0), XEXP (x, 1)); 2942 SUBST (XEXP (x, 1), tem); 2943 } 2944 break; 2945 2946 default: 2947 break; 2948 } 2949 2950 /* Otherwise, select our actions depending on our rtx class. */ 2951 switch (GET_RTX_CLASS (code)) 2952 { 2953 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ 2954 case '3': 2955 split = find_split_point (&XEXP (x, 2), insn); 2956 if (split) 2957 return split; 2958 /* ... fall through ... */ 2959 case '2': 2960 case 'c': 2961 case '<': 2962 split = find_split_point (&XEXP (x, 1), insn); 2963 if (split) 2964 return split; 2965 /* ... fall through ... */ 2966 case '1': 2967 /* Some machines have (and (shift ...) ...) insns. If X is not 2968 an AND, but XEXP (X, 0) is, use it as our split point. */ 2969 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) 2970 return &XEXP (x, 0); 2971 2972 split = find_split_point (&XEXP (x, 0), insn); 2973 if (split) 2974 return split; 2975 return loc; 2976 } 2977 2978 /* Otherwise, we don't have a split point. */ 2979 return 0; 2980} 2981 2982/* Throughout X, replace FROM with TO, and return the result. 2983 The result is TO if X is FROM; 2984 otherwise the result is X, but its contents may have been modified. 2985 If they were modified, a record was made in undobuf so that 2986 undo_all will (among other things) return X to its original state. 2987 2988 If the number of changes necessary is too much to record to undo, 2989 the excess changes are not made, so the result is invalid. 2990 The changes already made can still be undone. 2991 undobuf.num_undo is incremented for such changes, so by testing that 2992 the caller can tell whether the result is valid. 2993 2994 `n_occurrences' is incremented each time FROM is replaced. 2995 2996 IN_DEST is non-zero if we are processing the SET_DEST of a SET. 2997 2998 UNIQUE_COPY is non-zero if each substitution must be unique. We do this 2999 by copying if `n_occurrences' is non-zero. */ 3000 3001static rtx 3002subst (x, from, to, in_dest, unique_copy) 3003 register rtx x, from, to; 3004 int in_dest; 3005 int unique_copy; 3006{ 3007 register enum rtx_code code = GET_CODE (x); 3008 enum machine_mode op0_mode = VOIDmode; 3009 register char *fmt; 3010 register int len, i; 3011 rtx new; 3012 3013/* Two expressions are equal if they are identical copies of a shared 3014 RTX or if they are both registers with the same register number 3015 and mode. */ 3016 3017#define COMBINE_RTX_EQUAL_P(X,Y) \ 3018 ((X) == (Y) \ 3019 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \ 3020 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) 3021 3022 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) 3023 { 3024 n_occurrences++; 3025 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); 3026 } 3027 3028 /* If X and FROM are the same register but different modes, they will 3029 not have been seen as equal above. However, flow.c will make a 3030 LOG_LINKS entry for that case. If we do nothing, we will try to 3031 rerecognize our original insn and, when it succeeds, we will 3032 delete the feeding insn, which is incorrect. 3033 3034 So force this insn not to match in this (rare) case. */ 3035 if (! in_dest && code == REG && GET_CODE (from) == REG 3036 && REGNO (x) == REGNO (from)) 3037 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 3038 3039 /* If this is an object, we are done unless it is a MEM or LO_SUM, both 3040 of which may contain things that can be combined. */ 3041 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o') 3042 return x; 3043 3044 /* It is possible to have a subexpression appear twice in the insn. 3045 Suppose that FROM is a register that appears within TO. 3046 Then, after that subexpression has been scanned once by `subst', 3047 the second time it is scanned, TO may be found. If we were 3048 to scan TO here, we would find FROM within it and create a 3049 self-referent rtl structure which is completely wrong. */ 3050 if (COMBINE_RTX_EQUAL_P (x, to)) 3051 return to; 3052 3053 /* Parallel asm_operands need special attention because all of the 3054 inputs are shared across the arms. Furthermore, unsharing the 3055 rtl results in recognition failures. Failure to handle this case 3056 specially can result in circular rtl. 3057 3058 Solve this by doing a normal pass across the first entry of the 3059 parallel, and only processing the SET_DESTs of the subsequent 3060 entries. Ug. */ 3061 3062 if (code == PARALLEL 3063 && GET_CODE (XVECEXP (x, 0, 0)) == SET 3064 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) 3065 { 3066 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy); 3067 3068 /* If this substitution failed, this whole thing fails. */ 3069 if (GET_CODE (new) == CLOBBER 3070 && XEXP (new, 0) == const0_rtx) 3071 return new; 3072 3073 SUBST (XVECEXP (x, 0, 0), new); 3074 3075 for (i = XVECLEN (x, 0) - 1; i >= 1; i--) 3076 { 3077 rtx dest = SET_DEST (XVECEXP (x, 0, i)); 3078 3079 if (GET_CODE (dest) != REG 3080 && GET_CODE (dest) != CC0 3081 && GET_CODE (dest) != PC) 3082 { 3083 new = subst (dest, from, to, 0, unique_copy); 3084 3085 /* If this substitution failed, this whole thing fails. */ 3086 if (GET_CODE (new) == CLOBBER 3087 && XEXP (new, 0) == const0_rtx) 3088 return new; 3089 3090 SUBST (SET_DEST (XVECEXP (x, 0, i)), new); 3091 } 3092 } 3093 } 3094 else 3095 { 3096 len = GET_RTX_LENGTH (code); 3097 fmt = GET_RTX_FORMAT (code); 3098 3099 /* We don't need to process a SET_DEST that is a register, CC0, 3100 or PC, so set up to skip this common case. All other cases 3101 where we want to suppress replacing something inside a 3102 SET_SRC are handled via the IN_DEST operand. */ 3103 if (code == SET 3104 && (GET_CODE (SET_DEST (x)) == REG 3105 || GET_CODE (SET_DEST (x)) == CC0 3106 || GET_CODE (SET_DEST (x)) == PC)) 3107 fmt = "ie"; 3108 3109 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a 3110 constant. */ 3111 if (fmt[0] == 'e') 3112 op0_mode = GET_MODE (XEXP (x, 0)); 3113 3114 for (i = 0; i < len; i++) 3115 { 3116 if (fmt[i] == 'E') 3117 { 3118 register int j; 3119 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3120 { 3121 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) 3122 { 3123 new = (unique_copy && n_occurrences 3124 ? copy_rtx (to) : to); 3125 n_occurrences++; 3126 } 3127 else 3128 { 3129 new = subst (XVECEXP (x, i, j), from, to, 0, 3130 unique_copy); 3131 3132 /* If this substitution failed, this whole thing 3133 fails. */ 3134 if (GET_CODE (new) == CLOBBER 3135 && XEXP (new, 0) == const0_rtx) 3136 return new; 3137 } 3138 3139 SUBST (XVECEXP (x, i, j), new); 3140 } 3141 } 3142 else if (fmt[i] == 'e') 3143 { 3144 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) 3145 { 3146 /* In general, don't install a subreg involving two 3147 modes not tieable. It can worsen register 3148 allocation, and can even make invalid reload 3149 insns, since the reg inside may need to be copied 3150 from in the outside mode, and that may be invalid 3151 if it is an fp reg copied in integer mode. 3152 3153 We allow two exceptions to this: It is valid if 3154 it is inside another SUBREG and the mode of that 3155 SUBREG and the mode of the inside of TO is 3156 tieable and it is valid if X is a SET that copies 3157 FROM to CC0. */ 3158 3159 if (GET_CODE (to) == SUBREG 3160 && ! MODES_TIEABLE_P (GET_MODE (to), 3161 GET_MODE (SUBREG_REG (to))) 3162 && ! (code == SUBREG 3163 && MODES_TIEABLE_P (GET_MODE (x), 3164 GET_MODE (SUBREG_REG (to)))) 3165#ifdef HAVE_cc0 3166 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx) 3167#endif 3168 ) 3169 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 3170 3171 new = (unique_copy && n_occurrences ? copy_rtx (to) : to); 3172 n_occurrences++; 3173 } 3174 else 3175 /* If we are in a SET_DEST, suppress most cases unless we 3176 have gone inside a MEM, in which case we want to 3177 simplify the address. We assume here that things that 3178 are actually part of the destination have their inner 3179 parts in the first expression. This is true for SUBREG, 3180 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only 3181 things aside from REG and MEM that should appear in a 3182 SET_DEST. */ 3183 new = subst (XEXP (x, i), from, to, 3184 (((in_dest 3185 && (code == SUBREG || code == STRICT_LOW_PART 3186 || code == ZERO_EXTRACT)) 3187 || code == SET) 3188 && i == 0), unique_copy); 3189 3190 /* If we found that we will have to reject this combination, 3191 indicate that by returning the CLOBBER ourselves, rather than 3192 an expression containing it. This will speed things up as 3193 well as prevent accidents where two CLOBBERs are considered 3194 to be equal, thus producing an incorrect simplification. */ 3195 3196 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) 3197 return new; 3198 3199 SUBST (XEXP (x, i), new); 3200 } 3201 } 3202 } 3203 3204 /* Try to simplify X. If the simplification changed the code, it is likely 3205 that further simplification will help, so loop, but limit the number 3206 of repetitions that will be performed. */ 3207 3208 for (i = 0; i < 4; i++) 3209 { 3210 /* If X is sufficiently simple, don't bother trying to do anything 3211 with it. */ 3212 if (code != CONST_INT && code != REG && code != CLOBBER) 3213 x = simplify_rtx (x, op0_mode, i == 3, in_dest); 3214 3215 if (GET_CODE (x) == code) 3216 break; 3217 3218 code = GET_CODE (x); 3219 3220 /* We no longer know the original mode of operand 0 since we 3221 have changed the form of X) */ 3222 op0_mode = VOIDmode; 3223 } 3224 3225 return x; 3226} 3227 3228/* Simplify X, a piece of RTL. We just operate on the expression at the 3229 outer level; call `subst' to simplify recursively. Return the new 3230 expression. 3231 3232 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this 3233 will be the iteration even if an expression with a code different from 3234 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */ 3235 3236static rtx 3237simplify_rtx (x, op0_mode, last, in_dest) 3238 rtx x; 3239 enum machine_mode op0_mode; 3240 int last; 3241 int in_dest; 3242{ 3243 enum rtx_code code = GET_CODE (x); 3244 enum machine_mode mode = GET_MODE (x); 3245 rtx temp; 3246 int i; 3247 3248 /* If this is a commutative operation, put a constant last and a complex 3249 expression first. We don't need to do this for comparisons here. */ 3250 if (GET_RTX_CLASS (code) == 'c' 3251 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT) 3252 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o' 3253 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o') 3254 || (GET_CODE (XEXP (x, 0)) == SUBREG 3255 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o' 3256 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'))) 3257 { 3258 temp = XEXP (x, 0); 3259 SUBST (XEXP (x, 0), XEXP (x, 1)); 3260 SUBST (XEXP (x, 1), temp); 3261 } 3262 3263 /* If this is a PLUS, MINUS, or MULT, and the first operand is the 3264 sign extension of a PLUS with a constant, reverse the order of the sign 3265 extension and the addition. Note that this not the same as the original 3266 code, but overflow is undefined for signed values. Also note that the 3267 PLUS will have been partially moved "inside" the sign-extension, so that 3268 the first operand of X will really look like: 3269 (ashiftrt (plus (ashift A C4) C5) C4). 3270 We convert this to 3271 (plus (ashiftrt (ashift A C4) C2) C4) 3272 and replace the first operand of X with that expression. Later parts 3273 of this function may simplify the expression further. 3274 3275 For example, if we start with (mult (sign_extend (plus A C1)) C2), 3276 we swap the SIGN_EXTEND and PLUS. Later code will apply the 3277 distributive law to produce (plus (mult (sign_extend X) C1) C3). 3278 3279 We do this to simplify address expressions. */ 3280 3281 if ((code == PLUS || code == MINUS || code == MULT) 3282 && GET_CODE (XEXP (x, 0)) == ASHIFTRT 3283 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS 3284 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT 3285 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT 3286 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3287 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1) 3288 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT 3289 && (temp = simplify_binary_operation (ASHIFTRT, mode, 3290 XEXP (XEXP (XEXP (x, 0), 0), 1), 3291 XEXP (XEXP (x, 0), 1))) != 0) 3292 { 3293 rtx new 3294 = simplify_shift_const (NULL_RTX, ASHIFT, mode, 3295 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0), 3296 INTVAL (XEXP (XEXP (x, 0), 1))); 3297 3298 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new, 3299 INTVAL (XEXP (XEXP (x, 0), 1))); 3300 3301 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp)); 3302 } 3303 3304 /* If this is a simple operation applied to an IF_THEN_ELSE, try 3305 applying it to the arms of the IF_THEN_ELSE. This often simplifies 3306 things. Check for cases where both arms are testing the same 3307 condition. 3308 3309 Don't do anything if all operands are very simple. */ 3310 3311 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c' 3312 || GET_RTX_CLASS (code) == '<') 3313 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' 3314 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 3315 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) 3316 == 'o'))) 3317 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o' 3318 && ! (GET_CODE (XEXP (x, 1)) == SUBREG 3319 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1)))) 3320 == 'o'))))) 3321 || (GET_RTX_CLASS (code) == '1' 3322 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' 3323 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 3324 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) 3325 == 'o')))))) 3326 { 3327 rtx cond, true, false; 3328 3329 cond = if_then_else_cond (x, &true, &false); 3330 if (cond != 0 3331 /* If everything is a comparison, what we have is highly unlikely 3332 to be simpler, so don't use it. */ 3333 && ! (GET_RTX_CLASS (code) == '<' 3334 && (GET_RTX_CLASS (GET_CODE (true)) == '<' 3335 || GET_RTX_CLASS (GET_CODE (false)) == '<'))) 3336 { 3337 rtx cop1 = const0_rtx; 3338 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); 3339 3340 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<') 3341 return x; 3342 3343 /* Simplify the alternative arms; this may collapse the true and 3344 false arms to store-flag values. */ 3345 true = subst (true, pc_rtx, pc_rtx, 0, 0); 3346 false = subst (false, pc_rtx, pc_rtx, 0, 0); 3347 3348 /* Restarting if we generate a store-flag expression will cause 3349 us to loop. Just drop through in this case. */ 3350 3351 /* If the result values are STORE_FLAG_VALUE and zero, we can 3352 just make the comparison operation. */ 3353 if (true == const_true_rtx && false == const0_rtx) 3354 x = gen_binary (cond_code, mode, cond, cop1); 3355 else if (true == const0_rtx && false == const_true_rtx) 3356 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1); 3357 3358 /* Likewise, we can make the negate of a comparison operation 3359 if the result values are - STORE_FLAG_VALUE and zero. */ 3360 else if (GET_CODE (true) == CONST_INT 3361 && INTVAL (true) == - STORE_FLAG_VALUE 3362 && false == const0_rtx) 3363 x = gen_unary (NEG, mode, mode, 3364 gen_binary (cond_code, mode, cond, cop1)); 3365 else if (GET_CODE (false) == CONST_INT 3366 && INTVAL (false) == - STORE_FLAG_VALUE 3367 && true == const0_rtx) 3368 x = gen_unary (NEG, mode, mode, 3369 gen_binary (reverse_condition (cond_code), 3370 mode, cond, cop1)); 3371 else 3372 return gen_rtx_IF_THEN_ELSE (mode, 3373 gen_binary (cond_code, VOIDmode, 3374 cond, cop1), 3375 true, false); 3376 3377 code = GET_CODE (x); 3378 op0_mode = VOIDmode; 3379 } 3380 } 3381 3382 /* Try to fold this expression in case we have constants that weren't 3383 present before. */ 3384 temp = 0; 3385 switch (GET_RTX_CLASS (code)) 3386 { 3387 case '1': 3388 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); 3389 break; 3390 case '<': 3391 temp = simplify_relational_operation (code, op0_mode, 3392 XEXP (x, 0), XEXP (x, 1)); 3393#ifdef FLOAT_STORE_FLAG_VALUE 3394 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 3395 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x)) 3396 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x))); 3397#endif 3398 break; 3399 case 'c': 3400 case '2': 3401 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); 3402 break; 3403 case 'b': 3404 case '3': 3405 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), 3406 XEXP (x, 1), XEXP (x, 2)); 3407 break; 3408 } 3409 3410 if (temp) 3411 x = temp, code = GET_CODE (temp); 3412 3413 /* First see if we can apply the inverse distributive law. */ 3414 if (code == PLUS || code == MINUS 3415 || code == AND || code == IOR || code == XOR) 3416 { 3417 x = apply_distributive_law (x); 3418 code = GET_CODE (x); 3419 } 3420 3421 /* If CODE is an associative operation not otherwise handled, see if we 3422 can associate some operands. This can win if they are constants or 3423 if they are logically related (i.e. (a & b) & a. */ 3424 if ((code == PLUS || code == MINUS 3425 || code == MULT || code == AND || code == IOR || code == XOR 3426 || code == DIV || code == UDIV 3427 || code == SMAX || code == SMIN || code == UMAX || code == UMIN) 3428 && INTEGRAL_MODE_P (mode)) 3429 { 3430 if (GET_CODE (XEXP (x, 0)) == code) 3431 { 3432 rtx other = XEXP (XEXP (x, 0), 0); 3433 rtx inner_op0 = XEXP (XEXP (x, 0), 1); 3434 rtx inner_op1 = XEXP (x, 1); 3435 rtx inner; 3436 3437 /* Make sure we pass the constant operand if any as the second 3438 one if this is a commutative operation. */ 3439 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c') 3440 { 3441 rtx tem = inner_op0; 3442 inner_op0 = inner_op1; 3443 inner_op1 = tem; 3444 } 3445 inner = simplify_binary_operation (code == MINUS ? PLUS 3446 : code == DIV ? MULT 3447 : code == UDIV ? MULT 3448 : code, 3449 mode, inner_op0, inner_op1); 3450 3451 /* For commutative operations, try the other pair if that one 3452 didn't simplify. */ 3453 if (inner == 0 && GET_RTX_CLASS (code) == 'c') 3454 { 3455 other = XEXP (XEXP (x, 0), 1); 3456 inner = simplify_binary_operation (code, mode, 3457 XEXP (XEXP (x, 0), 0), 3458 XEXP (x, 1)); 3459 } 3460 3461 if (inner) 3462 return gen_binary (code, mode, other, inner); 3463 } 3464 } 3465 3466 /* A little bit of algebraic simplification here. */ 3467 switch (code) 3468 { 3469 case MEM: 3470 /* Ensure that our address has any ASHIFTs converted to MULT in case 3471 address-recognizing predicates are called later. */ 3472 temp = make_compound_operation (XEXP (x, 0), MEM); 3473 SUBST (XEXP (x, 0), temp); 3474 break; 3475 3476 case SUBREG: 3477 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG 3478 is paradoxical. If we can't do that safely, then it becomes 3479 something nonsensical so that this combination won't take place. */ 3480 3481 if (GET_CODE (SUBREG_REG (x)) == MEM 3482 && (GET_MODE_SIZE (mode) 3483 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) 3484 { 3485 rtx inner = SUBREG_REG (x); 3486 int endian_offset = 0; 3487 /* Don't change the mode of the MEM 3488 if that would change the meaning of the address. */ 3489 if (MEM_VOLATILE_P (SUBREG_REG (x)) 3490 || mode_dependent_address_p (XEXP (inner, 0))) 3491 return gen_rtx_CLOBBER (mode, const0_rtx); 3492 3493 if (BYTES_BIG_ENDIAN) 3494 { 3495 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD) 3496 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode); 3497 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD) 3498 endian_offset -= (UNITS_PER_WORD 3499 - GET_MODE_SIZE (GET_MODE (inner))); 3500 } 3501 /* Note if the plus_constant doesn't make a valid address 3502 then this combination won't be accepted. */ 3503 x = gen_rtx_MEM (mode, 3504 plus_constant (XEXP (inner, 0), 3505 (SUBREG_WORD (x) * UNITS_PER_WORD 3506 + endian_offset))); 3507 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner); 3508 MEM_COPY_ATTRIBUTES (x, inner); 3509 return x; 3510 } 3511 3512 /* If we are in a SET_DEST, these other cases can't apply. */ 3513 if (in_dest) 3514 return x; 3515 3516 /* Changing mode twice with SUBREG => just change it once, 3517 or not at all if changing back to starting mode. */ 3518 if (GET_CODE (SUBREG_REG (x)) == SUBREG) 3519 { 3520 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x))) 3521 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0) 3522 return SUBREG_REG (SUBREG_REG (x)); 3523 3524 SUBST_INT (SUBREG_WORD (x), 3525 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x))); 3526 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x))); 3527 } 3528 3529 /* SUBREG of a hard register => just change the register number 3530 and/or mode. If the hard register is not valid in that mode, 3531 suppress this combination. If the hard register is the stack, 3532 frame, or argument pointer, leave this as a SUBREG. */ 3533 3534 if (GET_CODE (SUBREG_REG (x)) == REG 3535 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER 3536 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM 3537#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 3538 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM 3539#endif 3540#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 3541 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM 3542#endif 3543 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM) 3544 { 3545 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x), 3546 mode)) 3547 return gen_rtx_REG (mode, 3548 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)); 3549 else 3550 return gen_rtx_CLOBBER (mode, const0_rtx); 3551 } 3552 3553 /* For a constant, try to pick up the part we want. Handle a full 3554 word and low-order part. Only do this if we are narrowing 3555 the constant; if it is being widened, we have no idea what 3556 the extra bits will have been set to. */ 3557 3558 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode 3559 && GET_MODE_SIZE (mode) == UNITS_PER_WORD 3560 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD 3561 && GET_MODE_CLASS (mode) == MODE_INT) 3562 { 3563 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 3564 0, op0_mode); 3565 if (temp) 3566 return temp; 3567 } 3568 3569 /* If we want a subreg of a constant, at offset 0, 3570 take the low bits. On a little-endian machine, that's 3571 always valid. On a big-endian machine, it's valid 3572 only if the constant's mode fits in one word. Note that we 3573 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */ 3574 if (CONSTANT_P (SUBREG_REG (x)) 3575 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD 3576 || ! WORDS_BIG_ENDIAN) 3577 ? SUBREG_WORD (x) == 0 3578 : (SUBREG_WORD (x) 3579 == ((GET_MODE_SIZE (op0_mode) 3580 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) 3581 / UNITS_PER_WORD))) 3582 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode) 3583 && (! WORDS_BIG_ENDIAN 3584 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD)) 3585 return gen_lowpart_for_combine (mode, SUBREG_REG (x)); 3586 3587 /* A paradoxical SUBREG of a VOIDmode constant is the same constant, 3588 since we are saying that the high bits don't matter. */ 3589 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode 3590 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode)) 3591 return SUBREG_REG (x); 3592 3593 /* Note that we cannot do any narrowing for non-constants since 3594 we might have been counting on using the fact that some bits were 3595 zero. We now do this in the SET. */ 3596 3597 break; 3598 3599 case NOT: 3600 /* (not (plus X -1)) can become (neg X). */ 3601 if (GET_CODE (XEXP (x, 0)) == PLUS 3602 && XEXP (XEXP (x, 0), 1) == constm1_rtx) 3603 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0)); 3604 3605 /* Similarly, (not (neg X)) is (plus X -1). */ 3606 if (GET_CODE (XEXP (x, 0)) == NEG) 3607 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), 3608 constm1_rtx); 3609 3610 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */ 3611 if (GET_CODE (XEXP (x, 0)) == XOR 3612 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3613 && (temp = simplify_unary_operation (NOT, mode, 3614 XEXP (XEXP (x, 0), 1), 3615 mode)) != 0) 3616 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp); 3617 3618 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands 3619 other than 1, but that is not valid. We could do a similar 3620 simplification for (not (lshiftrt C X)) where C is just the sign bit, 3621 but this doesn't seem common enough to bother with. */ 3622 if (GET_CODE (XEXP (x, 0)) == ASHIFT 3623 && XEXP (XEXP (x, 0), 0) == const1_rtx) 3624 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx), 3625 XEXP (XEXP (x, 0), 1)); 3626 3627 if (GET_CODE (XEXP (x, 0)) == SUBREG 3628 && subreg_lowpart_p (XEXP (x, 0)) 3629 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) 3630 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0))))) 3631 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT 3632 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx) 3633 { 3634 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0))); 3635 3636 x = gen_rtx_ROTATE (inner_mode, 3637 gen_unary (NOT, inner_mode, inner_mode, 3638 const1_rtx), 3639 XEXP (SUBREG_REG (XEXP (x, 0)), 1)); 3640 return gen_lowpart_for_combine (mode, x); 3641 } 3642 3643 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by 3644 reversing the comparison code if valid. */ 3645 if (STORE_FLAG_VALUE == -1 3646 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 3647 && reversible_comparison_p (XEXP (x, 0))) 3648 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))), 3649 mode, XEXP (XEXP (x, 0), 0), 3650 XEXP (XEXP (x, 0), 1)); 3651 3652 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1 3653 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can 3654 perform the above simplification. */ 3655 3656 if (STORE_FLAG_VALUE == -1 3657 && XEXP (x, 1) == const1_rtx 3658 && GET_CODE (XEXP (x, 0)) == ASHIFTRT 3659 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3660 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1) 3661 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx); 3662 3663 /* Apply De Morgan's laws to reduce number of patterns for machines 3664 with negating logical insns (and-not, nand, etc.). If result has 3665 only one NOT, put it first, since that is how the patterns are 3666 coded. */ 3667 3668 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND) 3669 { 3670 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1); 3671 3672 if (GET_CODE (in1) == NOT) 3673 in1 = XEXP (in1, 0); 3674 else 3675 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1); 3676 3677 if (GET_CODE (in2) == NOT) 3678 in2 = XEXP (in2, 0); 3679 else if (GET_CODE (in2) == CONST_INT 3680 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 3681 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2)); 3682 else 3683 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2); 3684 3685 if (GET_CODE (in2) == NOT) 3686 { 3687 rtx tem = in2; 3688 in2 = in1; in1 = tem; 3689 } 3690 3691 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR, 3692 mode, in1, in2); 3693 } 3694 break; 3695 3696 case NEG: 3697 /* (neg (plus X 1)) can become (not X). */ 3698 if (GET_CODE (XEXP (x, 0)) == PLUS 3699 && XEXP (XEXP (x, 0), 1) == const1_rtx) 3700 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0)); 3701 3702 /* Similarly, (neg (not X)) is (plus X 1). */ 3703 if (GET_CODE (XEXP (x, 0)) == NOT) 3704 return plus_constant (XEXP (XEXP (x, 0), 0), 1); 3705 3706 /* (neg (minus X Y)) can become (minus Y X). */ 3707 if (GET_CODE (XEXP (x, 0)) == MINUS 3708 && (! FLOAT_MODE_P (mode) 3709 /* x-y != -(y-x) with IEEE floating point. */ 3710 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT 3711 || flag_fast_math)) 3712 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1), 3713 XEXP (XEXP (x, 0), 0)); 3714 3715 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */ 3716 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx 3717 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1) 3718 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx); 3719 3720 /* NEG commutes with ASHIFT since it is multiplication. Only do this 3721 if we can then eliminate the NEG (e.g., 3722 if the operand is a constant). */ 3723 3724 if (GET_CODE (XEXP (x, 0)) == ASHIFT) 3725 { 3726 temp = simplify_unary_operation (NEG, mode, 3727 XEXP (XEXP (x, 0), 0), mode); 3728 if (temp) 3729 { 3730 SUBST (XEXP (XEXP (x, 0), 0), temp); 3731 return XEXP (x, 0); 3732 } 3733 } 3734 3735 temp = expand_compound_operation (XEXP (x, 0)); 3736 3737 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be 3738 replaced by (lshiftrt X C). This will convert 3739 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ 3740 3741 if (GET_CODE (temp) == ASHIFTRT 3742 && GET_CODE (XEXP (temp, 1)) == CONST_INT 3743 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1) 3744 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0), 3745 INTVAL (XEXP (temp, 1))); 3746 3747 /* If X has only a single bit that might be nonzero, say, bit I, convert 3748 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of 3749 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to 3750 (sign_extract X 1 Y). But only do this if TEMP isn't a register 3751 or a SUBREG of one since we'd be making the expression more 3752 complex if it was just a register. */ 3753 3754 if (GET_CODE (temp) != REG 3755 && ! (GET_CODE (temp) == SUBREG 3756 && GET_CODE (SUBREG_REG (temp)) == REG) 3757 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) 3758 { 3759 rtx temp1 = simplify_shift_const 3760 (NULL_RTX, ASHIFTRT, mode, 3761 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, 3762 GET_MODE_BITSIZE (mode) - 1 - i), 3763 GET_MODE_BITSIZE (mode) - 1 - i); 3764 3765 /* If all we did was surround TEMP with the two shifts, we 3766 haven't improved anything, so don't use it. Otherwise, 3767 we are better off with TEMP1. */ 3768 if (GET_CODE (temp1) != ASHIFTRT 3769 || GET_CODE (XEXP (temp1, 0)) != ASHIFT 3770 || XEXP (XEXP (temp1, 0), 0) != temp) 3771 return temp1; 3772 } 3773 break; 3774 3775 case TRUNCATE: 3776 /* We can't handle truncation to a partial integer mode here 3777 because we don't know the real bitsize of the partial 3778 integer mode. */ 3779 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) 3780 break; 3781 3782 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 3783 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 3784 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))) 3785 SUBST (XEXP (x, 0), 3786 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), 3787 GET_MODE_MASK (mode), NULL_RTX, 0)); 3788 3789 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */ 3790 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND 3791 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) 3792 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) 3793 return XEXP (XEXP (x, 0), 0); 3794 3795 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is 3796 (OP:SI foo:SI) if OP is NEG or ABS. */ 3797 if ((GET_CODE (XEXP (x, 0)) == ABS 3798 || GET_CODE (XEXP (x, 0)) == NEG) 3799 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND 3800 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND) 3801 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) 3802 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode, 3803 XEXP (XEXP (XEXP (x, 0), 0), 0)); 3804 3805 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is 3806 (truncate:SI x). */ 3807 if (GET_CODE (XEXP (x, 0)) == SUBREG 3808 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE 3809 && subreg_lowpart_p (XEXP (x, 0))) 3810 return SUBREG_REG (XEXP (x, 0)); 3811 3812 /* If we know that the value is already truncated, we can 3813 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION is 3814 nonzero for the corresponding modes. */ 3815 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 3816 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) 3817 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 3818 >= GET_MODE_BITSIZE (mode) + 1) 3819 return gen_lowpart_for_combine (mode, XEXP (x, 0)); 3820 3821 /* A truncate of a comparison can be replaced with a subreg if 3822 STORE_FLAG_VALUE permits. This is like the previous test, 3823 but it works even if the comparison is done in a mode larger 3824 than HOST_BITS_PER_WIDE_INT. */ 3825 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 3826 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 3827 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0) 3828 return gen_lowpart_for_combine (mode, XEXP (x, 0)); 3829 3830 /* Similarly, a truncate of a register whose value is a 3831 comparison can be replaced with a subreg if STORE_FLAG_VALUE 3832 permits. */ 3833 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 3834 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0 3835 && (temp = get_last_value (XEXP (x, 0))) 3836 && GET_RTX_CLASS (GET_CODE (temp)) == '<') 3837 return gen_lowpart_for_combine (mode, XEXP (x, 0)); 3838 3839 break; 3840 3841 case FLOAT_TRUNCATE: 3842 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */ 3843 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND 3844 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) 3845 return XEXP (XEXP (x, 0), 0); 3846 3847 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is 3848 (OP:SF foo:SF) if OP is NEG or ABS. */ 3849 if ((GET_CODE (XEXP (x, 0)) == ABS 3850 || GET_CODE (XEXP (x, 0)) == NEG) 3851 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND 3852 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) 3853 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode, 3854 XEXP (XEXP (XEXP (x, 0), 0), 0)); 3855 3856 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0)) 3857 is (float_truncate:SF x). */ 3858 if (GET_CODE (XEXP (x, 0)) == SUBREG 3859 && subreg_lowpart_p (XEXP (x, 0)) 3860 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE) 3861 return SUBREG_REG (XEXP (x, 0)); 3862 break; 3863 3864#ifdef HAVE_cc0 3865 case COMPARE: 3866 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't 3867 using cc0, in which case we want to leave it as a COMPARE 3868 so we can distinguish it from a register-register-copy. */ 3869 if (XEXP (x, 1) == const0_rtx) 3870 return XEXP (x, 0); 3871 3872 /* In IEEE floating point, x-0 is not the same as x. */ 3873 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT 3874 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))) 3875 || flag_fast_math) 3876 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0)))) 3877 return XEXP (x, 0); 3878 break; 3879#endif 3880 3881 case CONST: 3882 /* (const (const X)) can become (const X). Do it this way rather than 3883 returning the inner CONST since CONST can be shared with a 3884 REG_EQUAL note. */ 3885 if (GET_CODE (XEXP (x, 0)) == CONST) 3886 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 3887 break; 3888 3889#ifdef HAVE_lo_sum 3890 case LO_SUM: 3891 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we 3892 can add in an offset. find_split_point will split this address up 3893 again if it doesn't match. */ 3894 if (GET_CODE (XEXP (x, 0)) == HIGH 3895 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) 3896 return XEXP (x, 1); 3897 break; 3898#endif 3899 3900 case PLUS: 3901 /* If we have (plus (plus (A const) B)), associate it so that CONST is 3902 outermost. That's because that's the way indexed addresses are 3903 supposed to appear. This code used to check many more cases, but 3904 they are now checked elsewhere. */ 3905 if (GET_CODE (XEXP (x, 0)) == PLUS 3906 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1))) 3907 return gen_binary (PLUS, mode, 3908 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), 3909 XEXP (x, 1)), 3910 XEXP (XEXP (x, 0), 1)); 3911 3912 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) 3913 when c is (const_int (pow2 + 1) / 2) is a sign extension of a 3914 bit-field and can be replaced by either a sign_extend or a 3915 sign_extract. The `and' may be a zero_extend. */ 3916 if (GET_CODE (XEXP (x, 0)) == XOR 3917 && GET_CODE (XEXP (x, 1)) == CONST_INT 3918 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3919 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1)) 3920 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 3921 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 3922 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND 3923 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT 3924 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) 3925 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1)) 3926 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND 3927 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) 3928 == i + 1)))) 3929 return simplify_shift_const 3930 (NULL_RTX, ASHIFTRT, mode, 3931 simplify_shift_const (NULL_RTX, ASHIFT, mode, 3932 XEXP (XEXP (XEXP (x, 0), 0), 0), 3933 GET_MODE_BITSIZE (mode) - (i + 1)), 3934 GET_MODE_BITSIZE (mode) - (i + 1)); 3935 3936 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if 3937 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE 3938 is 1. This produces better code than the alternative immediately 3939 below. */ 3940 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 3941 && reversible_comparison_p (XEXP (x, 0)) 3942 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx) 3943 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))) 3944 return 3945 gen_unary (NEG, mode, mode, 3946 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))), 3947 mode, XEXP (XEXP (x, 0), 0), 3948 XEXP (XEXP (x, 0), 1))); 3949 3950 /* If only the low-order bit of X is possibly nonzero, (plus x -1) 3951 can become (ashiftrt (ashift (xor x 1) C) C) where C is 3952 the bitsize of the mode - 1. This allows simplification of 3953 "a = (b & 8) == 0;" */ 3954 if (XEXP (x, 1) == constm1_rtx 3955 && GET_CODE (XEXP (x, 0)) != REG 3956 && ! (GET_CODE (XEXP (x,0)) == SUBREG 3957 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG) 3958 && nonzero_bits (XEXP (x, 0), mode) == 1) 3959 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, 3960 simplify_shift_const (NULL_RTX, ASHIFT, mode, 3961 gen_rtx_combine (XOR, mode, 3962 XEXP (x, 0), const1_rtx), 3963 GET_MODE_BITSIZE (mode) - 1), 3964 GET_MODE_BITSIZE (mode) - 1); 3965 3966 /* If we are adding two things that have no bits in common, convert 3967 the addition into an IOR. This will often be further simplified, 3968 for example in cases like ((a & 1) + (a & 2)), which can 3969 become a & 3. */ 3970 3971 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 3972 && (nonzero_bits (XEXP (x, 0), mode) 3973 & nonzero_bits (XEXP (x, 1), mode)) == 0) 3974 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); 3975 break; 3976 3977 case MINUS: 3978 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done 3979 by reversing the comparison code if valid. */ 3980 if (STORE_FLAG_VALUE == 1 3981 && XEXP (x, 0) == const1_rtx 3982 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<' 3983 && reversible_comparison_p (XEXP (x, 1))) 3984 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))), 3985 mode, XEXP (XEXP (x, 1), 0), 3986 XEXP (XEXP (x, 1), 1)); 3987 3988 /* (minus <foo> (and <foo> (const_int -pow2))) becomes 3989 (and <foo> (const_int pow2-1)) */ 3990 if (GET_CODE (XEXP (x, 1)) == AND 3991 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 3992 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0 3993 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) 3994 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), 3995 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1); 3996 3997 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for 3998 integers. */ 3999 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode)) 4000 return gen_binary (MINUS, mode, 4001 gen_binary (MINUS, mode, XEXP (x, 0), 4002 XEXP (XEXP (x, 1), 0)), 4003 XEXP (XEXP (x, 1), 1)); 4004 break; 4005 4006 case MULT: 4007 /* If we have (mult (plus A B) C), apply the distributive law and then 4008 the inverse distributive law to see if things simplify. This 4009 occurs mostly in addresses, often when unrolling loops. */ 4010 4011 if (GET_CODE (XEXP (x, 0)) == PLUS) 4012 { 4013 x = apply_distributive_law 4014 (gen_binary (PLUS, mode, 4015 gen_binary (MULT, mode, 4016 XEXP (XEXP (x, 0), 0), XEXP (x, 1)), 4017 gen_binary (MULT, mode, 4018 XEXP (XEXP (x, 0), 1), XEXP (x, 1)))); 4019 4020 if (GET_CODE (x) != MULT) 4021 return x; 4022 } 4023 break; 4024 4025 case UDIV: 4026 /* If this is a divide by a power of two, treat it as a shift if 4027 its first operand is a shift. */ 4028 if (GET_CODE (XEXP (x, 1)) == CONST_INT 4029 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 4030 && (GET_CODE (XEXP (x, 0)) == ASHIFT 4031 || GET_CODE (XEXP (x, 0)) == LSHIFTRT 4032 || GET_CODE (XEXP (x, 0)) == ASHIFTRT 4033 || GET_CODE (XEXP (x, 0)) == ROTATE 4034 || GET_CODE (XEXP (x, 0)) == ROTATERT)) 4035 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); 4036 break; 4037 4038 case EQ: case NE: 4039 case GT: case GTU: case GE: case GEU: 4040 case LT: case LTU: case LE: case LEU: 4041 /* If the first operand is a condition code, we can't do anything 4042 with it. */ 4043 if (GET_CODE (XEXP (x, 0)) == COMPARE 4044 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC 4045#ifdef HAVE_cc0 4046 && XEXP (x, 0) != cc0_rtx 4047#endif 4048 )) 4049 { 4050 rtx op0 = XEXP (x, 0); 4051 rtx op1 = XEXP (x, 1); 4052 enum rtx_code new_code; 4053 4054 if (GET_CODE (op0) == COMPARE) 4055 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); 4056 4057 /* Simplify our comparison, if possible. */ 4058 new_code = simplify_comparison (code, &op0, &op1); 4059 4060 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X 4061 if only the low-order bit is possibly nonzero in X (such as when 4062 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to 4063 (xor X 1) or (minus 1 X); we use the former. Finally, if X is 4064 known to be either 0 or -1, NE becomes a NEG and EQ becomes 4065 (plus X 1). 4066 4067 Remove any ZERO_EXTRACT we made when thinking this was a 4068 comparison. It may now be simpler to use, e.g., an AND. If a 4069 ZERO_EXTRACT is indeed appropriate, it will be placed back by 4070 the call to make_compound_operation in the SET case. */ 4071 4072 if (STORE_FLAG_VALUE == 1 4073 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4074 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1) 4075 return gen_lowpart_for_combine (mode, 4076 expand_compound_operation (op0)); 4077 4078 else if (STORE_FLAG_VALUE == 1 4079 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4080 && op1 == const0_rtx 4081 && (num_sign_bit_copies (op0, mode) 4082 == GET_MODE_BITSIZE (mode))) 4083 { 4084 op0 = expand_compound_operation (op0); 4085 return gen_unary (NEG, mode, mode, 4086 gen_lowpart_for_combine (mode, op0)); 4087 } 4088 4089 else if (STORE_FLAG_VALUE == 1 4090 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4091 && op1 == const0_rtx 4092 && nonzero_bits (op0, mode) == 1) 4093 { 4094 op0 = expand_compound_operation (op0); 4095 return gen_binary (XOR, mode, 4096 gen_lowpart_for_combine (mode, op0), 4097 const1_rtx); 4098 } 4099 4100 else if (STORE_FLAG_VALUE == 1 4101 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4102 && op1 == const0_rtx 4103 && (num_sign_bit_copies (op0, mode) 4104 == GET_MODE_BITSIZE (mode))) 4105 { 4106 op0 = expand_compound_operation (op0); 4107 return plus_constant (gen_lowpart_for_combine (mode, op0), 1); 4108 } 4109 4110 /* If STORE_FLAG_VALUE is -1, we have cases similar to 4111 those above. */ 4112 if (STORE_FLAG_VALUE == -1 4113 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4114 && op1 == const0_rtx 4115 && (num_sign_bit_copies (op0, mode) 4116 == GET_MODE_BITSIZE (mode))) 4117 return gen_lowpart_for_combine (mode, 4118 expand_compound_operation (op0)); 4119 4120 else if (STORE_FLAG_VALUE == -1 4121 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4122 && op1 == const0_rtx 4123 && nonzero_bits (op0, mode) == 1) 4124 { 4125 op0 = expand_compound_operation (op0); 4126 return gen_unary (NEG, mode, mode, 4127 gen_lowpart_for_combine (mode, op0)); 4128 } 4129 4130 else if (STORE_FLAG_VALUE == -1 4131 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4132 && op1 == const0_rtx 4133 && (num_sign_bit_copies (op0, mode) 4134 == GET_MODE_BITSIZE (mode))) 4135 { 4136 op0 = expand_compound_operation (op0); 4137 return gen_unary (NOT, mode, mode, 4138 gen_lowpart_for_combine (mode, op0)); 4139 } 4140 4141 /* If X is 0/1, (eq X 0) is X-1. */ 4142 else if (STORE_FLAG_VALUE == -1 4143 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4144 && op1 == const0_rtx 4145 && nonzero_bits (op0, mode) == 1) 4146 { 4147 op0 = expand_compound_operation (op0); 4148 return plus_constant (gen_lowpart_for_combine (mode, op0), -1); 4149 } 4150 4151 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just 4152 one bit that might be nonzero, we can convert (ne x 0) to 4153 (ashift x c) where C puts the bit in the sign bit. Remove any 4154 AND with STORE_FLAG_VALUE when we are done, since we are only 4155 going to test the sign bit. */ 4156 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4157 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4158 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) 4159 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1)) 4160 && op1 == const0_rtx 4161 && mode == GET_MODE (op0) 4162 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) 4163 { 4164 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, 4165 expand_compound_operation (op0), 4166 GET_MODE_BITSIZE (mode) - 1 - i); 4167 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) 4168 return XEXP (x, 0); 4169 else 4170 return x; 4171 } 4172 4173 /* If the code changed, return a whole new comparison. */ 4174 if (new_code != code) 4175 return gen_rtx_combine (new_code, mode, op0, op1); 4176 4177 /* Otherwise, keep this operation, but maybe change its operands. 4178 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ 4179 SUBST (XEXP (x, 0), op0); 4180 SUBST (XEXP (x, 1), op1); 4181 } 4182 break; 4183 4184 case IF_THEN_ELSE: 4185 return simplify_if_then_else (x); 4186 4187 case ZERO_EXTRACT: 4188 case SIGN_EXTRACT: 4189 case ZERO_EXTEND: 4190 case SIGN_EXTEND: 4191 /* If we are processing SET_DEST, we are done. */ 4192 if (in_dest) 4193 return x; 4194 4195 return expand_compound_operation (x); 4196 4197 case SET: 4198 return simplify_set (x); 4199 4200 case AND: 4201 case IOR: 4202 case XOR: 4203 return simplify_logical (x, last); 4204 4205 case ABS: 4206 /* (abs (neg <foo>)) -> (abs <foo>) */ 4207 if (GET_CODE (XEXP (x, 0)) == NEG) 4208 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4209 4210 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS), 4211 do nothing. */ 4212 if (GET_MODE (XEXP (x, 0)) == VOIDmode) 4213 break; 4214 4215 /* If operand is something known to be positive, ignore the ABS. */ 4216 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS 4217 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 4218 <= HOST_BITS_PER_WIDE_INT) 4219 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 4220 & ((HOST_WIDE_INT) 1 4221 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))) 4222 == 0))) 4223 return XEXP (x, 0); 4224 4225 4226 /* If operand is known to be only -1 or 0, convert ABS to NEG. */ 4227 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode)) 4228 return gen_rtx_combine (NEG, mode, XEXP (x, 0)); 4229 4230 break; 4231 4232 case FFS: 4233 /* (ffs (*_extend <X>)) = (ffs <X>) */ 4234 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND 4235 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) 4236 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4237 break; 4238 4239 case FLOAT: 4240 /* (float (sign_extend <X>)) = (float <X>). */ 4241 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) 4242 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4243 break; 4244 4245 case ASHIFT: 4246 case LSHIFTRT: 4247 case ASHIFTRT: 4248 case ROTATE: 4249 case ROTATERT: 4250 /* If this is a shift by a constant amount, simplify it. */ 4251 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 4252 return simplify_shift_const (x, code, mode, XEXP (x, 0), 4253 INTVAL (XEXP (x, 1))); 4254 4255#ifdef SHIFT_COUNT_TRUNCATED 4256 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG) 4257 SUBST (XEXP (x, 1), 4258 force_to_mode (XEXP (x, 1), GET_MODE (x), 4259 ((HOST_WIDE_INT) 1 4260 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) 4261 - 1, 4262 NULL_RTX, 0)); 4263#endif 4264 4265 break; 4266 4267 default: 4268 break; 4269 } 4270 4271 return x; 4272} 4273 4274/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ 4275 4276static rtx 4277simplify_if_then_else (x) 4278 rtx x; 4279{ 4280 enum machine_mode mode = GET_MODE (x); 4281 rtx cond = XEXP (x, 0); 4282 rtx true = XEXP (x, 1); 4283 rtx false = XEXP (x, 2); 4284 enum rtx_code true_code = GET_CODE (cond); 4285 int comparison_p = GET_RTX_CLASS (true_code) == '<'; 4286 rtx temp; 4287 int i; 4288 4289 /* Simplify storing of the truth value. */ 4290 if (comparison_p && true == const_true_rtx && false == const0_rtx) 4291 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1)); 4292 4293 /* Also when the truth value has to be reversed. */ 4294 if (comparison_p && reversible_comparison_p (cond) 4295 && true == const0_rtx && false == const_true_rtx) 4296 return gen_binary (reverse_condition (true_code), 4297 mode, XEXP (cond, 0), XEXP (cond, 1)); 4298 4299 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used 4300 in it is being compared against certain values. Get the true and false 4301 comparisons and see if that says anything about the value of each arm. */ 4302 4303 if (comparison_p && reversible_comparison_p (cond) 4304 && GET_CODE (XEXP (cond, 0)) == REG) 4305 { 4306 HOST_WIDE_INT nzb; 4307 rtx from = XEXP (cond, 0); 4308 enum rtx_code false_code = reverse_condition (true_code); 4309 rtx true_val = XEXP (cond, 1); 4310 rtx false_val = true_val; 4311 int swapped = 0; 4312 4313 /* If FALSE_CODE is EQ, swap the codes and arms. */ 4314 4315 if (false_code == EQ) 4316 { 4317 swapped = 1, true_code = EQ, false_code = NE; 4318 temp = true, true = false, false = temp; 4319 } 4320 4321 /* If we are comparing against zero and the expression being tested has 4322 only a single bit that might be nonzero, that is its value when it is 4323 not equal to zero. Similarly if it is known to be -1 or 0. */ 4324 4325 if (true_code == EQ && true_val == const0_rtx 4326 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) 4327 false_code = EQ, false_val = GEN_INT (nzb); 4328 else if (true_code == EQ && true_val == const0_rtx 4329 && (num_sign_bit_copies (from, GET_MODE (from)) 4330 == GET_MODE_BITSIZE (GET_MODE (from)))) 4331 false_code = EQ, false_val = constm1_rtx; 4332 4333 /* Now simplify an arm if we know the value of the register in the 4334 branch and it is used in the arm. Be careful due to the potential 4335 of locally-shared RTL. */ 4336 4337 if (reg_mentioned_p (from, true)) 4338 true = subst (known_cond (copy_rtx (true), true_code, from, true_val), 4339 pc_rtx, pc_rtx, 0, 0); 4340 if (reg_mentioned_p (from, false)) 4341 false = subst (known_cond (copy_rtx (false), false_code, 4342 from, false_val), 4343 pc_rtx, pc_rtx, 0, 0); 4344 4345 SUBST (XEXP (x, 1), swapped ? false : true); 4346 SUBST (XEXP (x, 2), swapped ? true : false); 4347 4348 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond); 4349 } 4350 4351 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be 4352 reversed, do so to avoid needing two sets of patterns for 4353 subtract-and-branch insns. Similarly if we have a constant in the true 4354 arm, the false arm is the same as the first operand of the comparison, or 4355 the false arm is more complicated than the true arm. */ 4356 4357 if (comparison_p && reversible_comparison_p (cond) 4358 && (true == pc_rtx 4359 || (CONSTANT_P (true) 4360 && GET_CODE (false) != CONST_INT && false != pc_rtx) 4361 || true == const0_rtx 4362 || (GET_RTX_CLASS (GET_CODE (true)) == 'o' 4363 && GET_RTX_CLASS (GET_CODE (false)) != 'o') 4364 || (GET_CODE (true) == SUBREG 4365 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o' 4366 && GET_RTX_CLASS (GET_CODE (false)) != 'o') 4367 || reg_mentioned_p (true, false) 4368 || rtx_equal_p (false, XEXP (cond, 0)))) 4369 { 4370 true_code = reverse_condition (true_code); 4371 SUBST (XEXP (x, 0), 4372 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0), 4373 XEXP (cond, 1))); 4374 4375 SUBST (XEXP (x, 1), false); 4376 SUBST (XEXP (x, 2), true); 4377 4378 temp = true, true = false, false = temp, cond = XEXP (x, 0); 4379 4380 /* It is possible that the conditional has been simplified out. */ 4381 true_code = GET_CODE (cond); 4382 comparison_p = GET_RTX_CLASS (true_code) == '<'; 4383 } 4384 4385 /* If the two arms are identical, we don't need the comparison. */ 4386 4387 if (rtx_equal_p (true, false) && ! side_effects_p (cond)) 4388 return true; 4389 4390 /* Convert a == b ? b : a to "a". */ 4391 if (true_code == EQ && ! side_effects_p (cond) 4392 && rtx_equal_p (XEXP (cond, 0), false) 4393 && rtx_equal_p (XEXP (cond, 1), true)) 4394 return false; 4395 else if (true_code == NE && ! side_effects_p (cond) 4396 && rtx_equal_p (XEXP (cond, 0), true) 4397 && rtx_equal_p (XEXP (cond, 1), false)) 4398 return true; 4399 4400 /* Look for cases where we have (abs x) or (neg (abs X)). */ 4401 4402 if (GET_MODE_CLASS (mode) == MODE_INT 4403 && GET_CODE (false) == NEG 4404 && rtx_equal_p (true, XEXP (false, 0)) 4405 && comparison_p 4406 && rtx_equal_p (true, XEXP (cond, 0)) 4407 && ! side_effects_p (true)) 4408 switch (true_code) 4409 { 4410 case GT: 4411 case GE: 4412 return gen_unary (ABS, mode, mode, true); 4413 case LT: 4414 case LE: 4415 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true)); 4416 default: 4417 break; 4418 } 4419 4420 /* Look for MIN or MAX. */ 4421 4422 if ((! FLOAT_MODE_P (mode) || flag_fast_math) 4423 && comparison_p 4424 && rtx_equal_p (XEXP (cond, 0), true) 4425 && rtx_equal_p (XEXP (cond, 1), false) 4426 && ! side_effects_p (cond)) 4427 switch (true_code) 4428 { 4429 case GE: 4430 case GT: 4431 return gen_binary (SMAX, mode, true, false); 4432 case LE: 4433 case LT: 4434 return gen_binary (SMIN, mode, true, false); 4435 case GEU: 4436 case GTU: 4437 return gen_binary (UMAX, mode, true, false); 4438 case LEU: 4439 case LTU: 4440 return gen_binary (UMIN, mode, true, false); 4441 default: 4442 break; 4443 } 4444 4445 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its 4446 second operand is zero, this can be done as (OP Z (mult COND C2)) where 4447 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or 4448 SIGN_EXTEND as long as Z is already extended (so we don't destroy it). 4449 We can do this kind of thing in some cases when STORE_FLAG_VALUE is 4450 neither 1 or -1, but it isn't worth checking for. */ 4451 4452 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 4453 && comparison_p && mode != VOIDmode && ! side_effects_p (x)) 4454 { 4455 rtx t = make_compound_operation (true, SET); 4456 rtx f = make_compound_operation (false, SET); 4457 rtx cond_op0 = XEXP (cond, 0); 4458 rtx cond_op1 = XEXP (cond, 1); 4459 enum rtx_code op, extend_op = NIL; 4460 enum machine_mode m = mode; 4461 rtx z = 0, c1; 4462 4463 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS 4464 || GET_CODE (t) == IOR || GET_CODE (t) == XOR 4465 || GET_CODE (t) == ASHIFT 4466 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) 4467 && rtx_equal_p (XEXP (t, 0), f)) 4468 c1 = XEXP (t, 1), op = GET_CODE (t), z = f; 4469 4470 /* If an identity-zero op is commutative, check whether there 4471 would be a match if we swapped the operands. */ 4472 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR 4473 || GET_CODE (t) == XOR) 4474 && rtx_equal_p (XEXP (t, 1), f)) 4475 c1 = XEXP (t, 0), op = GET_CODE (t), z = f; 4476 else if (GET_CODE (t) == SIGN_EXTEND 4477 && (GET_CODE (XEXP (t, 0)) == PLUS 4478 || GET_CODE (XEXP (t, 0)) == MINUS 4479 || GET_CODE (XEXP (t, 0)) == IOR 4480 || GET_CODE (XEXP (t, 0)) == XOR 4481 || GET_CODE (XEXP (t, 0)) == ASHIFT 4482 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 4483 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 4484 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 4485 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 4486 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 4487 && (num_sign_bit_copies (f, GET_MODE (f)) 4488 > (GET_MODE_BITSIZE (mode) 4489 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0)))))) 4490 { 4491 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 4492 extend_op = SIGN_EXTEND; 4493 m = GET_MODE (XEXP (t, 0)); 4494 } 4495 else if (GET_CODE (t) == SIGN_EXTEND 4496 && (GET_CODE (XEXP (t, 0)) == PLUS 4497 || GET_CODE (XEXP (t, 0)) == IOR 4498 || GET_CODE (XEXP (t, 0)) == XOR) 4499 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 4500 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 4501 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 4502 && (num_sign_bit_copies (f, GET_MODE (f)) 4503 > (GET_MODE_BITSIZE (mode) 4504 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1)))))) 4505 { 4506 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 4507 extend_op = SIGN_EXTEND; 4508 m = GET_MODE (XEXP (t, 0)); 4509 } 4510 else if (GET_CODE (t) == ZERO_EXTEND 4511 && (GET_CODE (XEXP (t, 0)) == PLUS 4512 || GET_CODE (XEXP (t, 0)) == MINUS 4513 || GET_CODE (XEXP (t, 0)) == IOR 4514 || GET_CODE (XEXP (t, 0)) == XOR 4515 || GET_CODE (XEXP (t, 0)) == ASHIFT 4516 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 4517 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 4518 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 4519 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4520 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 4521 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 4522 && ((nonzero_bits (f, GET_MODE (f)) 4523 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) 4524 == 0)) 4525 { 4526 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 4527 extend_op = ZERO_EXTEND; 4528 m = GET_MODE (XEXP (t, 0)); 4529 } 4530 else if (GET_CODE (t) == ZERO_EXTEND 4531 && (GET_CODE (XEXP (t, 0)) == PLUS 4532 || GET_CODE (XEXP (t, 0)) == IOR 4533 || GET_CODE (XEXP (t, 0)) == XOR) 4534 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 4535 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4536 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 4537 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 4538 && ((nonzero_bits (f, GET_MODE (f)) 4539 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) 4540 == 0)) 4541 { 4542 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 4543 extend_op = ZERO_EXTEND; 4544 m = GET_MODE (XEXP (t, 0)); 4545 } 4546 4547 if (z) 4548 { 4549 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1), 4550 pc_rtx, pc_rtx, 0, 0); 4551 temp = gen_binary (MULT, m, temp, 4552 gen_binary (MULT, m, c1, const_true_rtx)); 4553 temp = subst (temp, pc_rtx, pc_rtx, 0, 0); 4554 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp); 4555 4556 if (extend_op != NIL) 4557 temp = gen_unary (extend_op, mode, m, temp); 4558 4559 return temp; 4560 } 4561 } 4562 4563 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or 4564 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the 4565 negation of a single bit, we can convert this operation to a shift. We 4566 can actually do this more generally, but it doesn't seem worth it. */ 4567 4568 if (true_code == NE && XEXP (cond, 1) == const0_rtx 4569 && false == const0_rtx && GET_CODE (true) == CONST_INT 4570 && ((1 == nonzero_bits (XEXP (cond, 0), mode) 4571 && (i = exact_log2 (INTVAL (true))) >= 0) 4572 || ((num_sign_bit_copies (XEXP (cond, 0), mode) 4573 == GET_MODE_BITSIZE (mode)) 4574 && (i = exact_log2 (- INTVAL (true))) >= 0))) 4575 return 4576 simplify_shift_const (NULL_RTX, ASHIFT, mode, 4577 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i); 4578 4579 return x; 4580} 4581 4582/* Simplify X, a SET expression. Return the new expression. */ 4583 4584static rtx 4585simplify_set (x) 4586 rtx x; 4587{ 4588 rtx src = SET_SRC (x); 4589 rtx dest = SET_DEST (x); 4590 enum machine_mode mode 4591 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); 4592 rtx other_insn; 4593 rtx *cc_use; 4594 4595 /* (set (pc) (return)) gets written as (return). */ 4596 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN) 4597 return src; 4598 4599 /* Now that we know for sure which bits of SRC we are using, see if we can 4600 simplify the expression for the object knowing that we only need the 4601 low-order bits. */ 4602 4603 if (GET_MODE_CLASS (mode) == MODE_INT) 4604 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0); 4605 4606 /* If we are setting CC0 or if the source is a COMPARE, look for the use of 4607 the comparison result and try to simplify it unless we already have used 4608 undobuf.other_insn. */ 4609 if ((GET_CODE (src) == COMPARE 4610#ifdef HAVE_cc0 4611 || dest == cc0_rtx 4612#endif 4613 ) 4614 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 4615 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) 4616 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<' 4617 && rtx_equal_p (XEXP (*cc_use, 0), dest)) 4618 { 4619 enum rtx_code old_code = GET_CODE (*cc_use); 4620 enum rtx_code new_code; 4621 rtx op0, op1; 4622 int other_changed = 0; 4623 enum machine_mode compare_mode = GET_MODE (dest); 4624 4625 if (GET_CODE (src) == COMPARE) 4626 op0 = XEXP (src, 0), op1 = XEXP (src, 1); 4627 else 4628 op0 = src, op1 = const0_rtx; 4629 4630 /* Simplify our comparison, if possible. */ 4631 new_code = simplify_comparison (old_code, &op0, &op1); 4632 4633#ifdef EXTRA_CC_MODES 4634 /* If this machine has CC modes other than CCmode, check to see if we 4635 need to use a different CC mode here. */ 4636 compare_mode = SELECT_CC_MODE (new_code, op0, op1); 4637#endif /* EXTRA_CC_MODES */ 4638 4639#if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES) 4640 /* If the mode changed, we have to change SET_DEST, the mode in the 4641 compare, and the mode in the place SET_DEST is used. If SET_DEST is 4642 a hard register, just build new versions with the proper mode. If it 4643 is a pseudo, we lose unless it is only time we set the pseudo, in 4644 which case we can safely change its mode. */ 4645 if (compare_mode != GET_MODE (dest)) 4646 { 4647 int regno = REGNO (dest); 4648 rtx new_dest = gen_rtx_REG (compare_mode, regno); 4649 4650 if (regno < FIRST_PSEUDO_REGISTER 4651 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest))) 4652 { 4653 if (regno >= FIRST_PSEUDO_REGISTER) 4654 SUBST (regno_reg_rtx[regno], new_dest); 4655 4656 SUBST (SET_DEST (x), new_dest); 4657 SUBST (XEXP (*cc_use, 0), new_dest); 4658 other_changed = 1; 4659 4660 dest = new_dest; 4661 } 4662 } 4663#endif 4664 4665 /* If the code changed, we have to build a new comparison in 4666 undobuf.other_insn. */ 4667 if (new_code != old_code) 4668 { 4669 unsigned HOST_WIDE_INT mask; 4670 4671 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use), 4672 dest, const0_rtx)); 4673 4674 /* If the only change we made was to change an EQ into an NE or 4675 vice versa, OP0 has only one bit that might be nonzero, and OP1 4676 is zero, check if changing the user of the condition code will 4677 produce a valid insn. If it won't, we can keep the original code 4678 in that insn by surrounding our operation with an XOR. */ 4679 4680 if (((old_code == NE && new_code == EQ) 4681 || (old_code == EQ && new_code == NE)) 4682 && ! other_changed && op1 == const0_rtx 4683 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 4684 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0) 4685 { 4686 rtx pat = PATTERN (other_insn), note = 0; 4687 4688 if ((recog_for_combine (&pat, other_insn, ¬e) < 0 4689 && ! check_asm_operands (pat))) 4690 { 4691 PUT_CODE (*cc_use, old_code); 4692 other_insn = 0; 4693 4694 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask)); 4695 } 4696 } 4697 4698 other_changed = 1; 4699 } 4700 4701 if (other_changed) 4702 undobuf.other_insn = other_insn; 4703 4704#ifdef HAVE_cc0 4705 /* If we are now comparing against zero, change our source if 4706 needed. If we do not use cc0, we always have a COMPARE. */ 4707 if (op1 == const0_rtx && dest == cc0_rtx) 4708 { 4709 SUBST (SET_SRC (x), op0); 4710 src = op0; 4711 } 4712 else 4713#endif 4714 4715 /* Otherwise, if we didn't previously have a COMPARE in the 4716 correct mode, we need one. */ 4717 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode) 4718 { 4719 SUBST (SET_SRC (x), 4720 gen_rtx_combine (COMPARE, compare_mode, op0, op1)); 4721 src = SET_SRC (x); 4722 } 4723 else 4724 { 4725 /* Otherwise, update the COMPARE if needed. */ 4726 SUBST (XEXP (src, 0), op0); 4727 SUBST (XEXP (src, 1), op1); 4728 } 4729 } 4730 else 4731 { 4732 /* Get SET_SRC in a form where we have placed back any 4733 compound expressions. Then do the checks below. */ 4734 src = make_compound_operation (src, SET); 4735 SUBST (SET_SRC (x), src); 4736 } 4737 4738 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, 4739 and X being a REG or (subreg (reg)), we may be able to convert this to 4740 (set (subreg:m2 x) (op)). 4741 4742 We can always do this if M1 is narrower than M2 because that means that 4743 we only care about the low bits of the result. 4744 4745 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot 4746 perform a narrower operation than requested since the high-order bits will 4747 be undefined. On machine where it is defined, this transformation is safe 4748 as long as M1 and M2 have the same number of words. */ 4749 4750 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 4751 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o' 4752 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) 4753 / UNITS_PER_WORD) 4754 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) 4755 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) 4756#ifndef WORD_REGISTER_OPERATIONS 4757 && (GET_MODE_SIZE (GET_MODE (src)) 4758 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) 4759#endif 4760#ifdef CLASS_CANNOT_CHANGE_SIZE 4761 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER 4762 && (TEST_HARD_REG_BIT 4763 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], 4764 REGNO (dest))) 4765 && (GET_MODE_SIZE (GET_MODE (src)) 4766 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))) 4767#endif 4768 && (GET_CODE (dest) == REG 4769 || (GET_CODE (dest) == SUBREG 4770 && GET_CODE (SUBREG_REG (dest)) == REG))) 4771 { 4772 SUBST (SET_DEST (x), 4773 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)), 4774 dest)); 4775 SUBST (SET_SRC (x), SUBREG_REG (src)); 4776 4777 src = SET_SRC (x), dest = SET_DEST (x); 4778 } 4779 4780#ifdef LOAD_EXTEND_OP 4781 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this 4782 would require a paradoxical subreg. Replace the subreg with a 4783 zero_extend to avoid the reload that would otherwise be required. */ 4784 4785 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 4786 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL 4787 && SUBREG_WORD (src) == 0 4788 && (GET_MODE_SIZE (GET_MODE (src)) 4789 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) 4790 && GET_CODE (SUBREG_REG (src)) == MEM) 4791 { 4792 SUBST (SET_SRC (x), 4793 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))), 4794 GET_MODE (src), XEXP (src, 0))); 4795 4796 src = SET_SRC (x); 4797 } 4798#endif 4799 4800 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we 4801 are comparing an item known to be 0 or -1 against 0, use a logical 4802 operation instead. Check for one of the arms being an IOR of the other 4803 arm with some value. We compute three terms to be IOR'ed together. In 4804 practice, at most two will be nonzero. Then we do the IOR's. */ 4805 4806 if (GET_CODE (dest) != PC 4807 && GET_CODE (src) == IF_THEN_ELSE 4808 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT 4809 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) 4810 && XEXP (XEXP (src, 0), 1) == const0_rtx 4811 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) 4812#ifdef HAVE_conditional_move 4813 && ! can_conditionally_move_p (GET_MODE (src)) 4814#endif 4815 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), 4816 GET_MODE (XEXP (XEXP (src, 0), 0))) 4817 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0)))) 4818 && ! side_effects_p (src)) 4819 { 4820 rtx true = (GET_CODE (XEXP (src, 0)) == NE 4821 ? XEXP (src, 1) : XEXP (src, 2)); 4822 rtx false = (GET_CODE (XEXP (src, 0)) == NE 4823 ? XEXP (src, 2) : XEXP (src, 1)); 4824 rtx term1 = const0_rtx, term2, term3; 4825 4826 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false)) 4827 term1 = false, true = XEXP (true, 1), false = const0_rtx; 4828 else if (GET_CODE (true) == IOR 4829 && rtx_equal_p (XEXP (true, 1), false)) 4830 term1 = false, true = XEXP (true, 0), false = const0_rtx; 4831 else if (GET_CODE (false) == IOR 4832 && rtx_equal_p (XEXP (false, 0), true)) 4833 term1 = true, false = XEXP (false, 1), true = const0_rtx; 4834 else if (GET_CODE (false) == IOR 4835 && rtx_equal_p (XEXP (false, 1), true)) 4836 term1 = true, false = XEXP (false, 0), true = const0_rtx; 4837 4838 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true); 4839 term3 = gen_binary (AND, GET_MODE (src), 4840 gen_unary (NOT, GET_MODE (src), GET_MODE (src), 4841 XEXP (XEXP (src, 0), 0)), 4842 false); 4843 4844 SUBST (SET_SRC (x), 4845 gen_binary (IOR, GET_MODE (src), 4846 gen_binary (IOR, GET_MODE (src), term1, term2), 4847 term3)); 4848 4849 src = SET_SRC (x); 4850 } 4851 4852 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this 4853 whole thing fail. */ 4854 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) 4855 return src; 4856 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) 4857 return dest; 4858 else 4859 /* Convert this into a field assignment operation, if possible. */ 4860 return make_field_assignment (x); 4861} 4862 4863/* Simplify, X, and AND, IOR, or XOR operation, and return the simplified 4864 result. LAST is nonzero if this is the last retry. */ 4865 4866static rtx 4867simplify_logical (x, last) 4868 rtx x; 4869 int last; 4870{ 4871 enum machine_mode mode = GET_MODE (x); 4872 rtx op0 = XEXP (x, 0); 4873 rtx op1 = XEXP (x, 1); 4874 4875 switch (GET_CODE (x)) 4876 { 4877 case AND: 4878 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single 4879 insn (and may simplify more). */ 4880 if (GET_CODE (op0) == XOR 4881 && rtx_equal_p (XEXP (op0, 0), op1) 4882 && ! side_effects_p (op1)) 4883 x = gen_binary (AND, mode, 4884 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1); 4885 4886 if (GET_CODE (op0) == XOR 4887 && rtx_equal_p (XEXP (op0, 1), op1) 4888 && ! side_effects_p (op1)) 4889 x = gen_binary (AND, mode, 4890 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1); 4891 4892 /* Similarly for (~ (A ^ B)) & A. */ 4893 if (GET_CODE (op0) == NOT 4894 && GET_CODE (XEXP (op0, 0)) == XOR 4895 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1) 4896 && ! side_effects_p (op1)) 4897 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1); 4898 4899 if (GET_CODE (op0) == NOT 4900 && GET_CODE (XEXP (op0, 0)) == XOR 4901 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1) 4902 && ! side_effects_p (op1)) 4903 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1); 4904 4905 if (GET_CODE (op1) == CONST_INT) 4906 { 4907 x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); 4908 4909 /* If we have (ior (and (X C1) C2)) and the next restart would be 4910 the last, simplify this by making C1 as small as possible 4911 and then exit. */ 4912 if (last 4913 && GET_CODE (x) == IOR && GET_CODE (op0) == AND 4914 && GET_CODE (XEXP (op0, 1)) == CONST_INT 4915 && GET_CODE (op1) == CONST_INT) 4916 return gen_binary (IOR, mode, 4917 gen_binary (AND, mode, XEXP (op0, 0), 4918 GEN_INT (INTVAL (XEXP (op0, 1)) 4919 & ~ INTVAL (op1))), op1); 4920 4921 if (GET_CODE (x) != AND) 4922 return x; 4923 4924 if (GET_RTX_CLASS (GET_CODE (x)) == 'c' 4925 || GET_RTX_CLASS (GET_CODE (x)) == '2') 4926 op0 = XEXP (x, 0), op1 = XEXP (x, 1); 4927 } 4928 4929 /* Convert (A | B) & A to A. */ 4930 if (GET_CODE (op0) == IOR 4931 && (rtx_equal_p (XEXP (op0, 0), op1) 4932 || rtx_equal_p (XEXP (op0, 1), op1)) 4933 && ! side_effects_p (XEXP (op0, 0)) 4934 && ! side_effects_p (XEXP (op0, 1))) 4935 return op1; 4936 4937 /* In the following group of tests (and those in case IOR below), 4938 we start with some combination of logical operations and apply 4939 the distributive law followed by the inverse distributive law. 4940 Most of the time, this results in no change. However, if some of 4941 the operands are the same or inverses of each other, simplifications 4942 will result. 4943 4944 For example, (and (ior A B) (not B)) can occur as the result of 4945 expanding a bit field assignment. When we apply the distributive 4946 law to this, we get (ior (and (A (not B))) (and (B (not B)))), 4947 which then simplifies to (and (A (not B))). 4948 4949 If we have (and (ior A B) C), apply the distributive law and then 4950 the inverse distributive law to see if things simplify. */ 4951 4952 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) 4953 { 4954 x = apply_distributive_law 4955 (gen_binary (GET_CODE (op0), mode, 4956 gen_binary (AND, mode, XEXP (op0, 0), op1), 4957 gen_binary (AND, mode, XEXP (op0, 1), op1))); 4958 if (GET_CODE (x) != AND) 4959 return x; 4960 } 4961 4962 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) 4963 return apply_distributive_law 4964 (gen_binary (GET_CODE (op1), mode, 4965 gen_binary (AND, mode, XEXP (op1, 0), op0), 4966 gen_binary (AND, mode, XEXP (op1, 1), op0))); 4967 4968 /* Similarly, taking advantage of the fact that 4969 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */ 4970 4971 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR) 4972 return apply_distributive_law 4973 (gen_binary (XOR, mode, 4974 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)), 4975 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1)))); 4976 4977 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR) 4978 return apply_distributive_law 4979 (gen_binary (XOR, mode, 4980 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)), 4981 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1)))); 4982 break; 4983 4984 case IOR: 4985 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ 4986 if (GET_CODE (op1) == CONST_INT 4987 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4988 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0) 4989 return op1; 4990 4991 /* Convert (A & B) | A to A. */ 4992 if (GET_CODE (op0) == AND 4993 && (rtx_equal_p (XEXP (op0, 0), op1) 4994 || rtx_equal_p (XEXP (op0, 1), op1)) 4995 && ! side_effects_p (XEXP (op0, 0)) 4996 && ! side_effects_p (XEXP (op0, 1))) 4997 return op1; 4998 4999 /* If we have (ior (and A B) C), apply the distributive law and then 5000 the inverse distributive law to see if things simplify. */ 5001 5002 if (GET_CODE (op0) == AND) 5003 { 5004 x = apply_distributive_law 5005 (gen_binary (AND, mode, 5006 gen_binary (IOR, mode, XEXP (op0, 0), op1), 5007 gen_binary (IOR, mode, XEXP (op0, 1), op1))); 5008 5009 if (GET_CODE (x) != IOR) 5010 return x; 5011 } 5012 5013 if (GET_CODE (op1) == AND) 5014 { 5015 x = apply_distributive_law 5016 (gen_binary (AND, mode, 5017 gen_binary (IOR, mode, XEXP (op1, 0), op0), 5018 gen_binary (IOR, mode, XEXP (op1, 1), op0))); 5019 5020 if (GET_CODE (x) != IOR) 5021 return x; 5022 } 5023 5024 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the 5025 mode size to (rotate A CX). */ 5026 5027 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT) 5028 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT)) 5029 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0)) 5030 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5031 && GET_CODE (XEXP (op1, 1)) == CONST_INT 5032 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1)) 5033 == GET_MODE_BITSIZE (mode))) 5034 return gen_rtx_ROTATE (mode, XEXP (op0, 0), 5035 (GET_CODE (op0) == ASHIFT 5036 ? XEXP (op0, 1) : XEXP (op1, 1))); 5037 5038 /* If OP0 is (ashiftrt (plus ...) C), it might actually be 5039 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS 5040 does not affect any of the bits in OP1, it can really be done 5041 as a PLUS and we can associate. We do this by seeing if OP1 5042 can be safely shifted left C bits. */ 5043 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT 5044 && GET_CODE (XEXP (op0, 0)) == PLUS 5045 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 5046 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5047 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT) 5048 { 5049 int count = INTVAL (XEXP (op0, 1)); 5050 HOST_WIDE_INT mask = INTVAL (op1) << count; 5051 5052 if (mask >> count == INTVAL (op1) 5053 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0) 5054 { 5055 SUBST (XEXP (XEXP (op0, 0), 1), 5056 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask)); 5057 return op0; 5058 } 5059 } 5060 break; 5061 5062 case XOR: 5063 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y). 5064 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for 5065 (NOT y). */ 5066 { 5067 int num_negated = 0; 5068 5069 if (GET_CODE (op0) == NOT) 5070 num_negated++, op0 = XEXP (op0, 0); 5071 if (GET_CODE (op1) == NOT) 5072 num_negated++, op1 = XEXP (op1, 0); 5073 5074 if (num_negated == 2) 5075 { 5076 SUBST (XEXP (x, 0), op0); 5077 SUBST (XEXP (x, 1), op1); 5078 } 5079 else if (num_negated == 1) 5080 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1)); 5081 } 5082 5083 /* Convert (xor (and A B) B) to (and (not A) B). The latter may 5084 correspond to a machine insn or result in further simplifications 5085 if B is a constant. */ 5086 5087 if (GET_CODE (op0) == AND 5088 && rtx_equal_p (XEXP (op0, 1), op1) 5089 && ! side_effects_p (op1)) 5090 return gen_binary (AND, mode, 5091 gen_unary (NOT, mode, mode, XEXP (op0, 0)), 5092 op1); 5093 5094 else if (GET_CODE (op0) == AND 5095 && rtx_equal_p (XEXP (op0, 0), op1) 5096 && ! side_effects_p (op1)) 5097 return gen_binary (AND, mode, 5098 gen_unary (NOT, mode, mode, XEXP (op0, 1)), 5099 op1); 5100 5101 /* (xor (comparison foo bar) (const_int 1)) can become the reversed 5102 comparison if STORE_FLAG_VALUE is 1. */ 5103 if (STORE_FLAG_VALUE == 1 5104 && op1 == const1_rtx 5105 && GET_RTX_CLASS (GET_CODE (op0)) == '<' 5106 && reversible_comparison_p (op0)) 5107 return gen_rtx_combine (reverse_condition (GET_CODE (op0)), 5108 mode, XEXP (op0, 0), XEXP (op0, 1)); 5109 5110 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1 5111 is (lt foo (const_int 0)), so we can perform the above 5112 simplification if STORE_FLAG_VALUE is 1. */ 5113 5114 if (STORE_FLAG_VALUE == 1 5115 && op1 == const1_rtx 5116 && GET_CODE (op0) == LSHIFTRT 5117 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5118 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1) 5119 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx); 5120 5121 /* (xor (comparison foo bar) (const_int sign-bit)) 5122 when STORE_FLAG_VALUE is the sign bit. */ 5123 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5124 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) 5125 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) 5126 && op1 == const_true_rtx 5127 && GET_RTX_CLASS (GET_CODE (op0)) == '<' 5128 && reversible_comparison_p (op0)) 5129 return gen_rtx_combine (reverse_condition (GET_CODE (op0)), 5130 mode, XEXP (op0, 0), XEXP (op0, 1)); 5131 break; 5132 5133 default: 5134 abort (); 5135 } 5136 5137 return x; 5138} 5139 5140/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound 5141 operations" because they can be replaced with two more basic operations. 5142 ZERO_EXTEND is also considered "compound" because it can be replaced with 5143 an AND operation, which is simpler, though only one operation. 5144 5145 The function expand_compound_operation is called with an rtx expression 5146 and will convert it to the appropriate shifts and AND operations, 5147 simplifying at each stage. 5148 5149 The function make_compound_operation is called to convert an expression 5150 consisting of shifts and ANDs into the equivalent compound expression. 5151 It is the inverse of this function, loosely speaking. */ 5152 5153static rtx 5154expand_compound_operation (x) 5155 rtx x; 5156{ 5157 int pos = 0, len; 5158 int unsignedp = 0; 5159 int modewidth; 5160 rtx tem; 5161 5162 switch (GET_CODE (x)) 5163 { 5164 case ZERO_EXTEND: 5165 unsignedp = 1; 5166 case SIGN_EXTEND: 5167 /* We can't necessarily use a const_int for a multiword mode; 5168 it depends on implicitly extending the value. 5169 Since we don't know the right way to extend it, 5170 we can't tell whether the implicit way is right. 5171 5172 Even for a mode that is no wider than a const_int, 5173 we can't win, because we need to sign extend one of its bits through 5174 the rest of it, and we don't know which bit. */ 5175 if (GET_CODE (XEXP (x, 0)) == CONST_INT) 5176 return x; 5177 5178 /* Return if (subreg:MODE FROM 0) is not a safe replacement for 5179 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM 5180 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be 5181 reloaded. If not for that, MEM's would very rarely be safe. 5182 5183 Reject MODEs bigger than a word, because we might not be able 5184 to reference a two-register group starting with an arbitrary register 5185 (and currently gen_lowpart might crash for a SUBREG). */ 5186 5187 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) 5188 return x; 5189 5190 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))); 5191 /* If the inner object has VOIDmode (the only way this can happen 5192 is if it is a ASM_OPERANDS), we can't do anything since we don't 5193 know how much masking to do. */ 5194 if (len == 0) 5195 return x; 5196 5197 break; 5198 5199 case ZERO_EXTRACT: 5200 unsignedp = 1; 5201 case SIGN_EXTRACT: 5202 /* If the operand is a CLOBBER, just return it. */ 5203 if (GET_CODE (XEXP (x, 0)) == CLOBBER) 5204 return XEXP (x, 0); 5205 5206 if (GET_CODE (XEXP (x, 1)) != CONST_INT 5207 || GET_CODE (XEXP (x, 2)) != CONST_INT 5208 || GET_MODE (XEXP (x, 0)) == VOIDmode) 5209 return x; 5210 5211 len = INTVAL (XEXP (x, 1)); 5212 pos = INTVAL (XEXP (x, 2)); 5213 5214 /* If this goes outside the object being extracted, replace the object 5215 with a (use (mem ...)) construct that only combine understands 5216 and is used only for this purpose. */ 5217 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) 5218 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0))); 5219 5220 if (BITS_BIG_ENDIAN) 5221 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos; 5222 5223 break; 5224 5225 default: 5226 return x; 5227 } 5228 5229 /* We can optimize some special cases of ZERO_EXTEND. */ 5230 if (GET_CODE (x) == ZERO_EXTEND) 5231 { 5232 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we 5233 know that the last value didn't have any inappropriate bits 5234 set. */ 5235 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 5236 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 5237 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5238 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x)) 5239 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5240 return XEXP (XEXP (x, 0), 0); 5241 5242 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 5243 if (GET_CODE (XEXP (x, 0)) == SUBREG 5244 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 5245 && subreg_lowpart_p (XEXP (x, 0)) 5246 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5247 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x)) 5248 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5249 return SUBREG_REG (XEXP (x, 0)); 5250 5251 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo 5252 is a comparison and STORE_FLAG_VALUE permits. This is like 5253 the first case, but it works even when GET_MODE (x) is larger 5254 than HOST_WIDE_INT. */ 5255 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 5256 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 5257 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<' 5258 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 5259 <= HOST_BITS_PER_WIDE_INT) 5260 && ((HOST_WIDE_INT) STORE_FLAG_VALUE 5261 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5262 return XEXP (XEXP (x, 0), 0); 5263 5264 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 5265 if (GET_CODE (XEXP (x, 0)) == SUBREG 5266 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 5267 && subreg_lowpart_p (XEXP (x, 0)) 5268 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<' 5269 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 5270 <= HOST_BITS_PER_WIDE_INT) 5271 && ((HOST_WIDE_INT) STORE_FLAG_VALUE 5272 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5273 return SUBREG_REG (XEXP (x, 0)); 5274 5275 /* If sign extension is cheaper than zero extension, then use it 5276 if we know that no extraneous bits are set, and that the high 5277 bit is not set. */ 5278 if (flag_expensive_optimizations 5279 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5280 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x)) 5281 & ~ (((unsigned HOST_WIDE_INT) 5282 GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) 5283 >> 1)) 5284 == 0)) 5285 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 5286 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 5287 <= HOST_BITS_PER_WIDE_INT) 5288 && (((HOST_WIDE_INT) STORE_FLAG_VALUE 5289 & ~ (((unsigned HOST_WIDE_INT) 5290 GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) 5291 >> 1)) 5292 == 0)))) 5293 { 5294 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0)); 5295 5296 if (rtx_cost (temp, SET) < rtx_cost (x, SET)) 5297 return expand_compound_operation (temp); 5298 } 5299 } 5300 5301 /* If we reach here, we want to return a pair of shifts. The inner 5302 shift is a left shift of BITSIZE - POS - LEN bits. The outer 5303 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or 5304 logical depending on the value of UNSIGNEDP. 5305 5306 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be 5307 converted into an AND of a shift. 5308 5309 We must check for the case where the left shift would have a negative 5310 count. This can happen in a case like (x >> 31) & 255 on machines 5311 that can't shift by a constant. On those machines, we would first 5312 combine the shift with the AND to produce a variable-position 5313 extraction. Then the constant of 31 would be substituted in to produce 5314 a such a position. */ 5315 5316 modewidth = GET_MODE_BITSIZE (GET_MODE (x)); 5317 if (modewidth >= pos - len) 5318 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, 5319 GET_MODE (x), 5320 simplify_shift_const (NULL_RTX, ASHIFT, 5321 GET_MODE (x), 5322 XEXP (x, 0), 5323 modewidth - pos - len), 5324 modewidth - len); 5325 5326 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) 5327 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), 5328 simplify_shift_const (NULL_RTX, LSHIFTRT, 5329 GET_MODE (x), 5330 XEXP (x, 0), pos), 5331 ((HOST_WIDE_INT) 1 << len) - 1); 5332 else 5333 /* Any other cases we can't handle. */ 5334 return x; 5335 5336 5337 /* If we couldn't do this for some reason, return the original 5338 expression. */ 5339 if (GET_CODE (tem) == CLOBBER) 5340 return x; 5341 5342 return tem; 5343} 5344 5345/* X is a SET which contains an assignment of one object into 5346 a part of another (such as a bit-field assignment, STRICT_LOW_PART, 5347 or certain SUBREGS). If possible, convert it into a series of 5348 logical operations. 5349 5350 We half-heartedly support variable positions, but do not at all 5351 support variable lengths. */ 5352 5353static rtx 5354expand_field_assignment (x) 5355 rtx x; 5356{ 5357 rtx inner; 5358 rtx pos; /* Always counts from low bit. */ 5359 int len; 5360 rtx mask; 5361 enum machine_mode compute_mode; 5362 5363 /* Loop until we find something we can't simplify. */ 5364 while (1) 5365 { 5366 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART 5367 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) 5368 { 5369 inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); 5370 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))); 5371 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0))); 5372 } 5373 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 5374 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT) 5375 { 5376 inner = XEXP (SET_DEST (x), 0); 5377 len = INTVAL (XEXP (SET_DEST (x), 1)); 5378 pos = XEXP (SET_DEST (x), 2); 5379 5380 /* If the position is constant and spans the width of INNER, 5381 surround INNER with a USE to indicate this. */ 5382 if (GET_CODE (pos) == CONST_INT 5383 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner))) 5384 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner); 5385 5386 if (BITS_BIG_ENDIAN) 5387 { 5388 if (GET_CODE (pos) == CONST_INT) 5389 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len 5390 - INTVAL (pos)); 5391 else if (GET_CODE (pos) == MINUS 5392 && GET_CODE (XEXP (pos, 1)) == CONST_INT 5393 && (INTVAL (XEXP (pos, 1)) 5394 == GET_MODE_BITSIZE (GET_MODE (inner)) - len)) 5395 /* If position is ADJUST - X, new position is X. */ 5396 pos = XEXP (pos, 0); 5397 else 5398 pos = gen_binary (MINUS, GET_MODE (pos), 5399 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) 5400 - len), 5401 pos); 5402 } 5403 } 5404 5405 /* A SUBREG between two modes that occupy the same numbers of words 5406 can be done by moving the SUBREG to the source. */ 5407 else if (GET_CODE (SET_DEST (x)) == SUBREG 5408 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) 5409 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 5410 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) 5411 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) 5412 { 5413 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)), 5414 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))), 5415 SET_SRC (x))); 5416 continue; 5417 } 5418 else 5419 break; 5420 5421 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 5422 inner = SUBREG_REG (inner); 5423 5424 compute_mode = GET_MODE (inner); 5425 5426 /* Don't attempt bitwise arithmetic on non-integral modes. */ 5427 if (! INTEGRAL_MODE_P (compute_mode)) 5428 { 5429 enum machine_mode imode; 5430 5431 /* Something is probably seriously wrong if this matches. */ 5432 if (! FLOAT_MODE_P (compute_mode)) 5433 break; 5434 5435 /* Try to find an integral mode to pun with. */ 5436 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0); 5437 if (imode == BLKmode) 5438 break; 5439 5440 compute_mode = imode; 5441 inner = gen_lowpart_for_combine (imode, inner); 5442 } 5443 5444 /* Compute a mask of LEN bits, if we can do this on the host machine. */ 5445 if (len < HOST_BITS_PER_WIDE_INT) 5446 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1); 5447 else 5448 break; 5449 5450 /* Now compute the equivalent expression. Make a copy of INNER 5451 for the SET_DEST in case it is a MEM into which we will substitute; 5452 we don't want shared RTL in that case. */ 5453 x = gen_rtx_SET (VOIDmode, copy_rtx (inner), 5454 gen_binary (IOR, compute_mode, 5455 gen_binary (AND, compute_mode, 5456 gen_unary (NOT, compute_mode, 5457 compute_mode, 5458 gen_binary (ASHIFT, 5459 compute_mode, 5460 mask, pos)), 5461 inner), 5462 gen_binary (ASHIFT, compute_mode, 5463 gen_binary (AND, compute_mode, 5464 gen_lowpart_for_combine 5465 (compute_mode, 5466 SET_SRC (x)), 5467 mask), 5468 pos))); 5469 } 5470 5471 return x; 5472} 5473 5474/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, 5475 it is an RTX that represents a variable starting position; otherwise, 5476 POS is the (constant) starting bit position (counted from the LSB). 5477 5478 INNER may be a USE. This will occur when we started with a bitfield 5479 that went outside the boundary of the object in memory, which is 5480 allowed on most machines. To isolate this case, we produce a USE 5481 whose mode is wide enough and surround the MEM with it. The only 5482 code that understands the USE is this routine. If it is not removed, 5483 it will cause the resulting insn not to match. 5484 5485 UNSIGNEDP is non-zero for an unsigned reference and zero for a 5486 signed reference. 5487 5488 IN_DEST is non-zero if this is a reference in the destination of a 5489 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero, 5490 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will 5491 be used. 5492 5493 IN_COMPARE is non-zero if we are in a COMPARE. This means that a 5494 ZERO_EXTRACT should be built even for bits starting at bit 0. 5495 5496 MODE is the desired mode of the result (if IN_DEST == 0). 5497 5498 The result is an RTX for the extraction or NULL_RTX if the target 5499 can't handle it. */ 5500 5501static rtx 5502make_extraction (mode, inner, pos, pos_rtx, len, 5503 unsignedp, in_dest, in_compare) 5504 enum machine_mode mode; 5505 rtx inner; 5506 int pos; 5507 rtx pos_rtx; 5508 int len; 5509 int unsignedp; 5510 int in_dest, in_compare; 5511{ 5512 /* This mode describes the size of the storage area 5513 to fetch the overall value from. Within that, we 5514 ignore the POS lowest bits, etc. */ 5515 enum machine_mode is_mode = GET_MODE (inner); 5516 enum machine_mode inner_mode; 5517 enum machine_mode wanted_inner_mode = byte_mode; 5518 enum machine_mode wanted_inner_reg_mode = word_mode; 5519 enum machine_mode pos_mode = word_mode; 5520 enum machine_mode extraction_mode = word_mode; 5521 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); 5522 int spans_byte = 0; 5523 rtx new = 0; 5524 rtx orig_pos_rtx = pos_rtx; 5525 int orig_pos; 5526 5527 /* Get some information about INNER and get the innermost object. */ 5528 if (GET_CODE (inner) == USE) 5529 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */ 5530 /* We don't need to adjust the position because we set up the USE 5531 to pretend that it was a full-word object. */ 5532 spans_byte = 1, inner = XEXP (inner, 0); 5533 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 5534 { 5535 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), 5536 consider just the QI as the memory to extract from. 5537 The subreg adds or removes high bits; its mode is 5538 irrelevant to the meaning of this extraction, 5539 since POS and LEN count from the lsb. */ 5540 if (GET_CODE (SUBREG_REG (inner)) == MEM) 5541 is_mode = GET_MODE (SUBREG_REG (inner)); 5542 inner = SUBREG_REG (inner); 5543 } 5544 5545 inner_mode = GET_MODE (inner); 5546 5547 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT) 5548 pos = INTVAL (pos_rtx), pos_rtx = 0; 5549 5550 /* See if this can be done without an extraction. We never can if the 5551 width of the field is not the same as that of some integer mode. For 5552 registers, we can only avoid the extraction if the position is at the 5553 low-order bit and this is either not in the destination or we have the 5554 appropriate STRICT_LOW_PART operation available. 5555 5556 For MEM, we can avoid an extract if the field starts on an appropriate 5557 boundary and we can change the mode of the memory reference. However, 5558 we cannot directly access the MEM if we have a USE and the underlying 5559 MEM is not TMODE. This combination means that MEM was being used in a 5560 context where bits outside its mode were being referenced; that is only 5561 valid in bit-field insns. */ 5562 5563 if (tmode != BLKmode 5564 && ! (spans_byte && inner_mode != tmode) 5565 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 5566 && GET_CODE (inner) != MEM 5567 && (! in_dest 5568 || (GET_CODE (inner) == REG 5569 && (movstrict_optab->handlers[(int) tmode].insn_code 5570 != CODE_FOR_nothing)))) 5571 || (GET_CODE (inner) == MEM && pos_rtx == 0 5572 && (pos 5573 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) 5574 : BITS_PER_UNIT)) == 0 5575 /* We can't do this if we are widening INNER_MODE (it 5576 may not be aligned, for one thing). */ 5577 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode) 5578 && (inner_mode == tmode 5579 || (! mode_dependent_address_p (XEXP (inner, 0)) 5580 && ! MEM_VOLATILE_P (inner)))))) 5581 { 5582 /* If INNER is a MEM, make a new MEM that encompasses just the desired 5583 field. If the original and current mode are the same, we need not 5584 adjust the offset. Otherwise, we do if bytes big endian. 5585 5586 If INNER is not a MEM, get a piece consisting of just the field 5587 of interest (in this case POS % BITS_PER_WORD must be 0). */ 5588 5589 if (GET_CODE (inner) == MEM) 5590 { 5591 int offset; 5592 /* POS counts from lsb, but make OFFSET count in memory order. */ 5593 if (BYTES_BIG_ENDIAN) 5594 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT; 5595 else 5596 offset = pos / BITS_PER_UNIT; 5597 5598 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset)); 5599 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner); 5600 MEM_COPY_ATTRIBUTES (new, inner); 5601 } 5602 else if (GET_CODE (inner) == REG) 5603 { 5604 /* We can't call gen_lowpart_for_combine here since we always want 5605 a SUBREG and it would sometimes return a new hard register. */ 5606 if (tmode != inner_mode) 5607 new = gen_rtx_SUBREG (tmode, inner, 5608 (WORDS_BIG_ENDIAN 5609 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD 5610 ? (((GET_MODE_SIZE (inner_mode) 5611 - GET_MODE_SIZE (tmode)) 5612 / UNITS_PER_WORD) 5613 - pos / BITS_PER_WORD) 5614 : pos / BITS_PER_WORD)); 5615 else 5616 new = inner; 5617 } 5618 else 5619 new = force_to_mode (inner, tmode, 5620 len >= HOST_BITS_PER_WIDE_INT 5621 ? GET_MODE_MASK (tmode) 5622 : ((HOST_WIDE_INT) 1 << len) - 1, 5623 NULL_RTX, 0); 5624 5625 /* If this extraction is going into the destination of a SET, 5626 make a STRICT_LOW_PART unless we made a MEM. */ 5627 5628 if (in_dest) 5629 return (GET_CODE (new) == MEM ? new 5630 : (GET_CODE (new) != SUBREG 5631 ? gen_rtx_CLOBBER (tmode, const0_rtx) 5632 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new))); 5633 5634 /* Otherwise, sign- or zero-extend unless we already are in the 5635 proper mode. */ 5636 5637 return (mode == tmode ? new 5638 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 5639 mode, new)); 5640 } 5641 5642 /* Unless this is a COMPARE or we have a funny memory reference, 5643 don't do anything with zero-extending field extracts starting at 5644 the low-order bit since they are simple AND operations. */ 5645 if (pos_rtx == 0 && pos == 0 && ! in_dest 5646 && ! in_compare && ! spans_byte && unsignedp) 5647 return 0; 5648 5649 /* Unless we are allowed to span bytes, reject this if we would be 5650 spanning bytes or if the position is not a constant and the length 5651 is not 1. In all other cases, we would only be going outside 5652 out object in cases when an original shift would have been 5653 undefined. */ 5654 if (! spans_byte 5655 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode)) 5656 || (pos_rtx != 0 && len != 1))) 5657 return 0; 5658 5659 /* Get the mode to use should INNER not be a MEM, the mode for the position, 5660 and the mode for the result. */ 5661#ifdef HAVE_insv 5662 if (in_dest) 5663 { 5664 wanted_inner_reg_mode 5665 = (insn_operand_mode[(int) CODE_FOR_insv][0] == VOIDmode 5666 ? word_mode 5667 : insn_operand_mode[(int) CODE_FOR_insv][0]); 5668 pos_mode = (insn_operand_mode[(int) CODE_FOR_insv][2] == VOIDmode 5669 ? word_mode : insn_operand_mode[(int) CODE_FOR_insv][2]); 5670 extraction_mode = (insn_operand_mode[(int) CODE_FOR_insv][3] == VOIDmode 5671 ? word_mode 5672 : insn_operand_mode[(int) CODE_FOR_insv][3]); 5673 } 5674#endif 5675 5676#ifdef HAVE_extzv 5677 if (! in_dest && unsignedp) 5678 { 5679 wanted_inner_reg_mode 5680 = (insn_operand_mode[(int) CODE_FOR_extzv][1] == VOIDmode 5681 ? word_mode 5682 : insn_operand_mode[(int) CODE_FOR_extzv][1]); 5683 pos_mode = (insn_operand_mode[(int) CODE_FOR_extzv][3] == VOIDmode 5684 ? word_mode : insn_operand_mode[(int) CODE_FOR_extzv][3]); 5685 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extzv][0] == VOIDmode 5686 ? word_mode 5687 : insn_operand_mode[(int) CODE_FOR_extzv][0]); 5688 } 5689#endif 5690 5691#ifdef HAVE_extv 5692 if (! in_dest && ! unsignedp) 5693 { 5694 wanted_inner_reg_mode 5695 = (insn_operand_mode[(int) CODE_FOR_extv][1] == VOIDmode 5696 ? word_mode 5697 : insn_operand_mode[(int) CODE_FOR_extv][1]); 5698 pos_mode = (insn_operand_mode[(int) CODE_FOR_extv][3] == VOIDmode 5699 ? word_mode : insn_operand_mode[(int) CODE_FOR_extv][3]); 5700 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extv][0] == VOIDmode 5701 ? word_mode 5702 : insn_operand_mode[(int) CODE_FOR_extv][0]); 5703 } 5704#endif 5705 5706 /* Never narrow an object, since that might not be safe. */ 5707 5708 if (mode != VOIDmode 5709 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) 5710 extraction_mode = mode; 5711 5712 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode 5713 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) 5714 pos_mode = GET_MODE (pos_rtx); 5715 5716 /* If this is not from memory, the desired mode is wanted_inner_reg_mode; 5717 if we have to change the mode of memory and cannot, the desired mode is 5718 EXTRACTION_MODE. */ 5719 if (GET_CODE (inner) != MEM) 5720 wanted_inner_mode = wanted_inner_reg_mode; 5721 else if (inner_mode != wanted_inner_mode 5722 && (mode_dependent_address_p (XEXP (inner, 0)) 5723 || MEM_VOLATILE_P (inner))) 5724 wanted_inner_mode = extraction_mode; 5725 5726 orig_pos = pos; 5727 5728 if (BITS_BIG_ENDIAN) 5729 { 5730 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to 5731 BITS_BIG_ENDIAN style. If position is constant, compute new 5732 position. Otherwise, build subtraction. 5733 Note that POS is relative to the mode of the original argument. 5734 If it's a MEM we need to recompute POS relative to that. 5735 However, if we're extracting from (or inserting into) a register, 5736 we want to recompute POS relative to wanted_inner_mode. */ 5737 int width = (GET_CODE (inner) == MEM 5738 ? GET_MODE_BITSIZE (is_mode) 5739 : GET_MODE_BITSIZE (wanted_inner_mode)); 5740 5741 if (pos_rtx == 0) 5742 pos = width - len - pos; 5743 else 5744 pos_rtx 5745 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx), 5746 GEN_INT (width - len), pos_rtx); 5747 /* POS may be less than 0 now, but we check for that below. 5748 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */ 5749 } 5750 5751 /* If INNER has a wider mode, make it smaller. If this is a constant 5752 extract, try to adjust the byte to point to the byte containing 5753 the value. */ 5754 if (wanted_inner_mode != VOIDmode 5755 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode) 5756 && ((GET_CODE (inner) == MEM 5757 && (inner_mode == wanted_inner_mode 5758 || (! mode_dependent_address_p (XEXP (inner, 0)) 5759 && ! MEM_VOLATILE_P (inner)))))) 5760 { 5761 int offset = 0; 5762 5763 /* The computations below will be correct if the machine is big 5764 endian in both bits and bytes or little endian in bits and bytes. 5765 If it is mixed, we must adjust. */ 5766 5767 /* If bytes are big endian and we had a paradoxical SUBREG, we must 5768 adjust OFFSET to compensate. */ 5769 if (BYTES_BIG_ENDIAN 5770 && ! spans_byte 5771 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) 5772 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); 5773 5774 /* If this is a constant position, we can move to the desired byte. */ 5775 if (pos_rtx == 0) 5776 { 5777 offset += pos / BITS_PER_UNIT; 5778 pos %= GET_MODE_BITSIZE (wanted_inner_mode); 5779 } 5780 5781 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN 5782 && ! spans_byte 5783 && is_mode != wanted_inner_mode) 5784 offset = (GET_MODE_SIZE (is_mode) 5785 - GET_MODE_SIZE (wanted_inner_mode) - offset); 5786 5787 if (offset != 0 || inner_mode != wanted_inner_mode) 5788 { 5789 rtx newmem = gen_rtx_MEM (wanted_inner_mode, 5790 plus_constant (XEXP (inner, 0), offset)); 5791 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner); 5792 MEM_COPY_ATTRIBUTES (newmem, inner); 5793 inner = newmem; 5794 } 5795 } 5796 5797 /* If INNER is not memory, we can always get it into the proper mode. If we 5798 are changing its mode, POS must be a constant and smaller than the size 5799 of the new mode. */ 5800 else if (GET_CODE (inner) != MEM) 5801 { 5802 if (GET_MODE (inner) != wanted_inner_mode 5803 && (pos_rtx != 0 5804 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) 5805 return 0; 5806 5807 inner = force_to_mode (inner, wanted_inner_mode, 5808 pos_rtx 5809 || len + orig_pos >= HOST_BITS_PER_WIDE_INT 5810 ? GET_MODE_MASK (wanted_inner_mode) 5811 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos, 5812 NULL_RTX, 0); 5813 } 5814 5815 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we 5816 have to zero extend. Otherwise, we can just use a SUBREG. */ 5817 if (pos_rtx != 0 5818 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) 5819 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx); 5820 else if (pos_rtx != 0 5821 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) 5822 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx); 5823 5824 /* Make POS_RTX unless we already have it and it is correct. If we don't 5825 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must 5826 be a CONST_INT. */ 5827 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) 5828 pos_rtx = orig_pos_rtx; 5829 5830 else if (pos_rtx == 0) 5831 pos_rtx = GEN_INT (pos); 5832 5833 /* Make the required operation. See if we can use existing rtx. */ 5834 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, 5835 extraction_mode, inner, GEN_INT (len), pos_rtx); 5836 if (! in_dest) 5837 new = gen_lowpart_for_combine (mode, new); 5838 5839 return new; 5840} 5841 5842/* See if X contains an ASHIFT of COUNT or more bits that can be commuted 5843 with any other operations in X. Return X without that shift if so. */ 5844 5845static rtx 5846extract_left_shift (x, count) 5847 rtx x; 5848 int count; 5849{ 5850 enum rtx_code code = GET_CODE (x); 5851 enum machine_mode mode = GET_MODE (x); 5852 rtx tem; 5853 5854 switch (code) 5855 { 5856 case ASHIFT: 5857 /* This is the shift itself. If it is wide enough, we will return 5858 either the value being shifted if the shift count is equal to 5859 COUNT or a shift for the difference. */ 5860 if (GET_CODE (XEXP (x, 1)) == CONST_INT 5861 && INTVAL (XEXP (x, 1)) >= count) 5862 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), 5863 INTVAL (XEXP (x, 1)) - count); 5864 break; 5865 5866 case NEG: case NOT: 5867 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) 5868 return gen_unary (code, mode, mode, tem); 5869 5870 break; 5871 5872 case PLUS: case IOR: case XOR: case AND: 5873 /* If we can safely shift this constant and we find the inner shift, 5874 make a new operation. */ 5875 if (GET_CODE (XEXP (x,1)) == CONST_INT 5876 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0 5877 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) 5878 return gen_binary (code, mode, tem, 5879 GEN_INT (INTVAL (XEXP (x, 1)) >> count)); 5880 5881 break; 5882 5883 default: 5884 break; 5885 } 5886 5887 return 0; 5888} 5889 5890/* Look at the expression rooted at X. Look for expressions 5891 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. 5892 Form these expressions. 5893 5894 Return the new rtx, usually just X. 5895 5896 Also, for machines like the Vax that don't have logical shift insns, 5897 try to convert logical to arithmetic shift operations in cases where 5898 they are equivalent. This undoes the canonicalizations to logical 5899 shifts done elsewhere. 5900 5901 We try, as much as possible, to re-use rtl expressions to save memory. 5902 5903 IN_CODE says what kind of expression we are processing. Normally, it is 5904 SET. In a memory address (inside a MEM, PLUS or minus, the latter two 5905 being kludges), it is MEM. When processing the arguments of a comparison 5906 or a COMPARE against zero, it is COMPARE. */ 5907 5908static rtx 5909make_compound_operation (x, in_code) 5910 rtx x; 5911 enum rtx_code in_code; 5912{ 5913 enum rtx_code code = GET_CODE (x); 5914 enum machine_mode mode = GET_MODE (x); 5915 int mode_width = GET_MODE_BITSIZE (mode); 5916 rtx rhs, lhs; 5917 enum rtx_code next_code; 5918 int i; 5919 rtx new = 0; 5920 rtx tem; 5921 char *fmt; 5922 5923 /* Select the code to be used in recursive calls. Once we are inside an 5924 address, we stay there. If we have a comparison, set to COMPARE, 5925 but once inside, go back to our default of SET. */ 5926 5927 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM 5928 : ((code == COMPARE || GET_RTX_CLASS (code) == '<') 5929 && XEXP (x, 1) == const0_rtx) ? COMPARE 5930 : in_code == COMPARE ? SET : in_code); 5931 5932 /* Process depending on the code of this operation. If NEW is set 5933 non-zero, it will be returned. */ 5934 5935 switch (code) 5936 { 5937 case ASHIFT: 5938 /* Convert shifts by constants into multiplications if inside 5939 an address. */ 5940 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT 5941 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 5942 && INTVAL (XEXP (x, 1)) >= 0) 5943 { 5944 new = make_compound_operation (XEXP (x, 0), next_code); 5945 new = gen_rtx_combine (MULT, mode, new, 5946 GEN_INT ((HOST_WIDE_INT) 1 5947 << INTVAL (XEXP (x, 1)))); 5948 } 5949 break; 5950 5951 case AND: 5952 /* If the second operand is not a constant, we can't do anything 5953 with it. */ 5954 if (GET_CODE (XEXP (x, 1)) != CONST_INT) 5955 break; 5956 5957 /* If the constant is a power of two minus one and the first operand 5958 is a logical right shift, make an extraction. */ 5959 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 5960 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 5961 { 5962 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 5963 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1, 5964 0, in_code == COMPARE); 5965 } 5966 5967 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ 5968 else if (GET_CODE (XEXP (x, 0)) == SUBREG 5969 && subreg_lowpart_p (XEXP (x, 0)) 5970 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT 5971 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 5972 { 5973 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), 5974 next_code); 5975 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0, 5976 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, 5977 0, in_code == COMPARE); 5978 } 5979 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ 5980 else if ((GET_CODE (XEXP (x, 0)) == XOR 5981 || GET_CODE (XEXP (x, 0)) == IOR) 5982 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT 5983 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT 5984 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 5985 { 5986 /* Apply the distributive law, and then try to make extractions. */ 5987 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode, 5988 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), 5989 XEXP (x, 1)), 5990 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), 5991 XEXP (x, 1))); 5992 new = make_compound_operation (new, in_code); 5993 } 5994 5995 /* If we are have (and (rotate X C) M) and C is larger than the number 5996 of bits in M, this is an extraction. */ 5997 5998 else if (GET_CODE (XEXP (x, 0)) == ROTATE 5999 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6000 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 6001 && i <= INTVAL (XEXP (XEXP (x, 0), 1))) 6002 { 6003 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 6004 new = make_extraction (mode, new, 6005 (GET_MODE_BITSIZE (mode) 6006 - INTVAL (XEXP (XEXP (x, 0), 1))), 6007 NULL_RTX, i, 1, 0, in_code == COMPARE); 6008 } 6009 6010 /* On machines without logical shifts, if the operand of the AND is 6011 a logical shift and our mask turns off all the propagated sign 6012 bits, we can replace the logical shift with an arithmetic shift. */ 6013 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing 6014 && (lshr_optab->handlers[(int) mode].insn_code 6015 == CODE_FOR_nothing) 6016 && GET_CODE (XEXP (x, 0)) == LSHIFTRT 6017 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6018 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 6019 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 6020 && mode_width <= HOST_BITS_PER_WIDE_INT) 6021 { 6022 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 6023 6024 mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); 6025 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) 6026 SUBST (XEXP (x, 0), 6027 gen_rtx_combine (ASHIFTRT, mode, 6028 make_compound_operation (XEXP (XEXP (x, 0), 0), 6029 next_code), 6030 XEXP (XEXP (x, 0), 1))); 6031 } 6032 6033 /* If the constant is one less than a power of two, this might be 6034 representable by an extraction even if no shift is present. 6035 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless 6036 we are in a COMPARE. */ 6037 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6038 new = make_extraction (mode, 6039 make_compound_operation (XEXP (x, 0), 6040 next_code), 6041 0, NULL_RTX, i, 1, 0, in_code == COMPARE); 6042 6043 /* If we are in a comparison and this is an AND with a power of two, 6044 convert this into the appropriate bit extract. */ 6045 else if (in_code == COMPARE 6046 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) 6047 new = make_extraction (mode, 6048 make_compound_operation (XEXP (x, 0), 6049 next_code), 6050 i, NULL_RTX, 1, 1, 0, 1); 6051 6052 break; 6053 6054 case LSHIFTRT: 6055 /* If the sign bit is known to be zero, replace this with an 6056 arithmetic shift. */ 6057 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing 6058 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing 6059 && mode_width <= HOST_BITS_PER_WIDE_INT 6060 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) 6061 { 6062 new = gen_rtx_combine (ASHIFTRT, mode, 6063 make_compound_operation (XEXP (x, 0), 6064 next_code), 6065 XEXP (x, 1)); 6066 break; 6067 } 6068 6069 /* ... fall through ... */ 6070 6071 case ASHIFTRT: 6072 lhs = XEXP (x, 0); 6073 rhs = XEXP (x, 1); 6074 6075 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, 6076 this is a SIGN_EXTRACT. */ 6077 if (GET_CODE (rhs) == CONST_INT 6078 && GET_CODE (lhs) == ASHIFT 6079 && GET_CODE (XEXP (lhs, 1)) == CONST_INT 6080 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))) 6081 { 6082 new = make_compound_operation (XEXP (lhs, 0), next_code); 6083 new = make_extraction (mode, new, 6084 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), 6085 NULL_RTX, mode_width - INTVAL (rhs), 6086 code == LSHIFTRT, 0, in_code == COMPARE); 6087 } 6088 6089 /* See if we have operations between an ASHIFTRT and an ASHIFT. 6090 If so, try to merge the shifts into a SIGN_EXTEND. We could 6091 also do this for some cases of SIGN_EXTRACT, but it doesn't 6092 seem worth the effort; the case checked for occurs on Alpha. */ 6093 6094 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o' 6095 && ! (GET_CODE (lhs) == SUBREG 6096 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o')) 6097 && GET_CODE (rhs) == CONST_INT 6098 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT 6099 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0) 6100 new = make_extraction (mode, make_compound_operation (new, next_code), 6101 0, NULL_RTX, mode_width - INTVAL (rhs), 6102 code == LSHIFTRT, 0, in_code == COMPARE); 6103 6104 break; 6105 6106 case SUBREG: 6107 /* Call ourselves recursively on the inner expression. If we are 6108 narrowing the object and it has a different RTL code from 6109 what it originally did, do this SUBREG as a force_to_mode. */ 6110 6111 tem = make_compound_operation (SUBREG_REG (x), in_code); 6112 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x)) 6113 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem)) 6114 && subreg_lowpart_p (x)) 6115 { 6116 rtx newer = force_to_mode (tem, mode, 6117 GET_MODE_MASK (mode), NULL_RTX, 0); 6118 6119 /* If we have something other than a SUBREG, we might have 6120 done an expansion, so rerun outselves. */ 6121 if (GET_CODE (newer) != SUBREG) 6122 newer = make_compound_operation (newer, in_code); 6123 6124 return newer; 6125 } 6126 6127 /* If this is a paradoxical subreg, and the new code is a sign or 6128 zero extension, omit the subreg and widen the extension. If it 6129 is a regular subreg, we can still get rid of the subreg by not 6130 widening so much, or in fact removing the extension entirely. */ 6131 if ((GET_CODE (tem) == SIGN_EXTEND 6132 || GET_CODE (tem) == ZERO_EXTEND) 6133 && subreg_lowpart_p (x)) 6134 { 6135 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem)) 6136 || (GET_MODE_SIZE (mode) > 6137 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0))))) 6138 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0)); 6139 else 6140 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0)); 6141 return tem; 6142 } 6143 break; 6144 6145 default: 6146 break; 6147 } 6148 6149 if (new) 6150 { 6151 x = gen_lowpart_for_combine (mode, new); 6152 code = GET_CODE (x); 6153 } 6154 6155 /* Now recursively process each operand of this operation. */ 6156 fmt = GET_RTX_FORMAT (code); 6157 for (i = 0; i < GET_RTX_LENGTH (code); i++) 6158 if (fmt[i] == 'e') 6159 { 6160 new = make_compound_operation (XEXP (x, i), next_code); 6161 SUBST (XEXP (x, i), new); 6162 } 6163 6164 return x; 6165} 6166 6167/* Given M see if it is a value that would select a field of bits 6168 within an item, but not the entire word. Return -1 if not. 6169 Otherwise, return the starting position of the field, where 0 is the 6170 low-order bit. 6171 6172 *PLEN is set to the length of the field. */ 6173 6174static int 6175get_pos_from_mask (m, plen) 6176 unsigned HOST_WIDE_INT m; 6177 int *plen; 6178{ 6179 /* Get the bit number of the first 1 bit from the right, -1 if none. */ 6180 int pos = exact_log2 (m & - m); 6181 6182 if (pos < 0) 6183 return -1; 6184 6185 /* Now shift off the low-order zero bits and see if we have a power of 6186 two minus 1. */ 6187 *plen = exact_log2 ((m >> pos) + 1); 6188 6189 if (*plen <= 0) 6190 return -1; 6191 6192 return pos; 6193} 6194 6195/* See if X can be simplified knowing that we will only refer to it in 6196 MODE and will only refer to those bits that are nonzero in MASK. 6197 If other bits are being computed or if masking operations are done 6198 that select a superset of the bits in MASK, they can sometimes be 6199 ignored. 6200 6201 Return a possibly simplified expression, but always convert X to 6202 MODE. If X is a CONST_INT, AND the CONST_INT with MASK. 6203 6204 Also, if REG is non-zero and X is a register equal in value to REG, 6205 replace X with REG. 6206 6207 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK 6208 are all off in X. This is used when X will be complemented, by either 6209 NOT, NEG, or XOR. */ 6210 6211static rtx 6212force_to_mode (x, mode, mask, reg, just_select) 6213 rtx x; 6214 enum machine_mode mode; 6215 unsigned HOST_WIDE_INT mask; 6216 rtx reg; 6217 int just_select; 6218{ 6219 enum rtx_code code = GET_CODE (x); 6220 int next_select = just_select || code == XOR || code == NOT || code == NEG; 6221 enum machine_mode op_mode; 6222 unsigned HOST_WIDE_INT fuller_mask, nonzero; 6223 rtx op0, op1, temp; 6224 6225 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the 6226 code below will do the wrong thing since the mode of such an 6227 expression is VOIDmode. 6228 6229 Also do nothing if X is a CLOBBER; this can happen if X was 6230 the return value from a call to gen_lowpart_for_combine. */ 6231 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) 6232 return x; 6233 6234 /* We want to perform the operation is its present mode unless we know 6235 that the operation is valid in MODE, in which case we do the operation 6236 in MODE. */ 6237 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) 6238 && code_to_optab[(int) code] != 0 6239 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code 6240 != CODE_FOR_nothing)) 6241 ? mode : GET_MODE (x)); 6242 6243 /* It is not valid to do a right-shift in a narrower mode 6244 than the one it came in with. */ 6245 if ((code == LSHIFTRT || code == ASHIFTRT) 6246 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x))) 6247 op_mode = GET_MODE (x); 6248 6249 /* Truncate MASK to fit OP_MODE. */ 6250 if (op_mode) 6251 mask &= GET_MODE_MASK (op_mode); 6252 6253 /* When we have an arithmetic operation, or a shift whose count we 6254 do not know, we need to assume that all bit the up to the highest-order 6255 bit in MASK will be needed. This is how we form such a mask. */ 6256 if (op_mode) 6257 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT 6258 ? GET_MODE_MASK (op_mode) 6259 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1); 6260 else 6261 fuller_mask = ~ (HOST_WIDE_INT) 0; 6262 6263 /* Determine what bits of X are guaranteed to be (non)zero. */ 6264 nonzero = nonzero_bits (x, mode); 6265 6266 /* If none of the bits in X are needed, return a zero. */ 6267 if (! just_select && (nonzero & mask) == 0) 6268 return const0_rtx; 6269 6270 /* If X is a CONST_INT, return a new one. Do this here since the 6271 test below will fail. */ 6272 if (GET_CODE (x) == CONST_INT) 6273 { 6274 HOST_WIDE_INT cval = INTVAL (x) & mask; 6275 int width = GET_MODE_BITSIZE (mode); 6276 6277 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative 6278 number, sign extend it. */ 6279 if (width > 0 && width < HOST_BITS_PER_WIDE_INT 6280 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6281 cval |= (HOST_WIDE_INT) -1 << width; 6282 6283 return GEN_INT (cval); 6284 } 6285 6286 /* If X is narrower than MODE and we want all the bits in X's mode, just 6287 get X in the proper mode. */ 6288 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) 6289 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0) 6290 return gen_lowpart_for_combine (mode, x); 6291 6292 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in 6293 MASK are already known to be zero in X, we need not do anything. */ 6294 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0) 6295 return x; 6296 6297 switch (code) 6298 { 6299 case CLOBBER: 6300 /* If X is a (clobber (const_int)), return it since we know we are 6301 generating something that won't match. */ 6302 return x; 6303 6304 case USE: 6305 /* X is a (use (mem ..)) that was made from a bit-field extraction that 6306 spanned the boundary of the MEM. If we are now masking so it is 6307 within that boundary, we don't need the USE any more. */ 6308 if (! BITS_BIG_ENDIAN 6309 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 6310 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 6311 break; 6312 6313 case SIGN_EXTEND: 6314 case ZERO_EXTEND: 6315 case ZERO_EXTRACT: 6316 case SIGN_EXTRACT: 6317 x = expand_compound_operation (x); 6318 if (GET_CODE (x) != code) 6319 return force_to_mode (x, mode, mask, reg, next_select); 6320 break; 6321 6322 case REG: 6323 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x) 6324 || rtx_equal_p (reg, get_last_value (x)))) 6325 x = reg; 6326 break; 6327 6328 case SUBREG: 6329 if (subreg_lowpart_p (x) 6330 /* We can ignore the effect of this SUBREG if it narrows the mode or 6331 if the constant masks to zero all the bits the mode doesn't 6332 have. */ 6333 && ((GET_MODE_SIZE (GET_MODE (x)) 6334 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 6335 || (0 == (mask 6336 & GET_MODE_MASK (GET_MODE (x)) 6337 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) 6338 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select); 6339 break; 6340 6341 case AND: 6342 /* If this is an AND with a constant, convert it into an AND 6343 whose constant is the AND of that constant with MASK. If it 6344 remains an AND of MASK, delete it since it is redundant. */ 6345 6346 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 6347 { 6348 x = simplify_and_const_int (x, op_mode, XEXP (x, 0), 6349 mask & INTVAL (XEXP (x, 1))); 6350 6351 /* If X is still an AND, see if it is an AND with a mask that 6352 is just some low-order bits. If so, and it is MASK, we don't 6353 need it. */ 6354 6355 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT 6356 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask) 6357 x = XEXP (x, 0); 6358 6359 /* If it remains an AND, try making another AND with the bits 6360 in the mode mask that aren't in MASK turned on. If the 6361 constant in the AND is wide enough, this might make a 6362 cheaper constant. */ 6363 6364 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT 6365 && GET_MODE_MASK (GET_MODE (x)) != mask 6366 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) 6367 { 6368 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1)) 6369 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask)); 6370 int width = GET_MODE_BITSIZE (GET_MODE (x)); 6371 rtx y; 6372 6373 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative 6374 number, sign extend it. */ 6375 if (width > 0 && width < HOST_BITS_PER_WIDE_INT 6376 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6377 cval |= (HOST_WIDE_INT) -1 << width; 6378 6379 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval)); 6380 if (rtx_cost (y, SET) < rtx_cost (x, SET)) 6381 x = y; 6382 } 6383 6384 break; 6385 } 6386 6387 goto binop; 6388 6389 case PLUS: 6390 /* In (and (plus FOO C1) M), if M is a mask that just turns off 6391 low-order bits (as in an alignment operation) and FOO is already 6392 aligned to that boundary, mask C1 to that boundary as well. 6393 This may eliminate that PLUS and, later, the AND. */ 6394 6395 { 6396 int width = GET_MODE_BITSIZE (mode); 6397 unsigned HOST_WIDE_INT smask = mask; 6398 6399 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative 6400 number, sign extend it. */ 6401 6402 if (width < HOST_BITS_PER_WIDE_INT 6403 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6404 smask |= (HOST_WIDE_INT) -1 << width; 6405 6406 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6407 && exact_log2 (- smask) >= 0) 6408 { 6409#ifdef STACK_BIAS 6410 if (STACK_BIAS 6411 && (XEXP (x, 0) == stack_pointer_rtx 6412 || XEXP (x, 0) == frame_pointer_rtx)) 6413 { 6414 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; 6415 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode); 6416 6417 sp_mask &= ~ (sp_alignment - 1); 6418 if ((sp_mask & ~ smask) == 0 6419 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0) 6420 return force_to_mode (plus_constant (XEXP (x, 0), 6421 ((INTVAL (XEXP (x, 1)) - 6422 STACK_BIAS) & smask) 6423 + STACK_BIAS), 6424 mode, smask, reg, next_select); 6425 } 6426#endif 6427 if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0 6428 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0) 6429 return force_to_mode (plus_constant (XEXP (x, 0), 6430 (INTVAL (XEXP (x, 1)) 6431 & smask)), 6432 mode, smask, reg, next_select); 6433 } 6434 } 6435 6436 /* ... fall through ... */ 6437 6438 case MINUS: 6439 case MULT: 6440 /* For PLUS, MINUS and MULT, we need any bits less significant than the 6441 most significant bit in MASK since carries from those bits will 6442 affect the bits we are interested in. */ 6443 mask = fuller_mask; 6444 goto binop; 6445 6446 case IOR: 6447 case XOR: 6448 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and 6449 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) 6450 operation which may be a bitfield extraction. Ensure that the 6451 constant we form is not wider than the mode of X. */ 6452 6453 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6454 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6455 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 6456 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 6457 && GET_CODE (XEXP (x, 1)) == CONST_INT 6458 && ((INTVAL (XEXP (XEXP (x, 0), 1)) 6459 + floor_log2 (INTVAL (XEXP (x, 1)))) 6460 < GET_MODE_BITSIZE (GET_MODE (x))) 6461 && (INTVAL (XEXP (x, 1)) 6462 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0) 6463 { 6464 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask) 6465 << INTVAL (XEXP (XEXP (x, 0), 1))); 6466 temp = gen_binary (GET_CODE (x), GET_MODE (x), 6467 XEXP (XEXP (x, 0), 0), temp); 6468 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, 6469 XEXP (XEXP (x, 0), 1)); 6470 return force_to_mode (x, mode, mask, reg, next_select); 6471 } 6472 6473 binop: 6474 /* For most binary operations, just propagate into the operation and 6475 change the mode if we have an operation of that mode. */ 6476 6477 op0 = gen_lowpart_for_combine (op_mode, 6478 force_to_mode (XEXP (x, 0), mode, mask, 6479 reg, next_select)); 6480 op1 = gen_lowpart_for_combine (op_mode, 6481 force_to_mode (XEXP (x, 1), mode, mask, 6482 reg, next_select)); 6483 6484 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside 6485 MASK since OP1 might have been sign-extended but we never want 6486 to turn on extra bits, since combine might have previously relied 6487 on them being off. */ 6488 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR) 6489 && (INTVAL (op1) & mask) != 0) 6490 op1 = GEN_INT (INTVAL (op1) & mask); 6491 6492 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 6493 x = gen_binary (code, op_mode, op0, op1); 6494 break; 6495 6496 case ASHIFT: 6497 /* For left shifts, do the same, but just for the first operand. 6498 However, we cannot do anything with shifts where we cannot 6499 guarantee that the counts are smaller than the size of the mode 6500 because such a count will have a different meaning in a 6501 wider mode. */ 6502 6503 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT 6504 && INTVAL (XEXP (x, 1)) >= 0 6505 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode)) 6506 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode 6507 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) 6508 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))) 6509 break; 6510 6511 /* If the shift count is a constant and we can do arithmetic in 6512 the mode of the shift, refine which bits we need. Otherwise, use the 6513 conservative form of the mask. */ 6514 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6515 && INTVAL (XEXP (x, 1)) >= 0 6516 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode) 6517 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) 6518 mask >>= INTVAL (XEXP (x, 1)); 6519 else 6520 mask = fuller_mask; 6521 6522 op0 = gen_lowpart_for_combine (op_mode, 6523 force_to_mode (XEXP (x, 0), op_mode, 6524 mask, reg, next_select)); 6525 6526 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 6527 x = gen_binary (code, op_mode, op0, XEXP (x, 1)); 6528 break; 6529 6530 case LSHIFTRT: 6531 /* Here we can only do something if the shift count is a constant, 6532 this shift constant is valid for the host, and we can do arithmetic 6533 in OP_MODE. */ 6534 6535 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6536 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 6537 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) 6538 { 6539 rtx inner = XEXP (x, 0); 6540 6541 /* Select the mask of the bits we need for the shift operand. */ 6542 mask <<= INTVAL (XEXP (x, 1)); 6543 6544 /* We can only change the mode of the shift if we can do arithmetic 6545 in the mode of the shift and MASK is no wider than the width of 6546 OP_MODE. */ 6547 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT 6548 || (mask & ~ GET_MODE_MASK (op_mode)) != 0) 6549 op_mode = GET_MODE (x); 6550 6551 inner = force_to_mode (inner, op_mode, mask, reg, next_select); 6552 6553 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) 6554 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); 6555 } 6556 6557 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the 6558 shift and AND produces only copies of the sign bit (C2 is one less 6559 than a power of two), we can do this with just a shift. */ 6560 6561 if (GET_CODE (x) == LSHIFTRT 6562 && GET_CODE (XEXP (x, 1)) == CONST_INT 6563 && ((INTVAL (XEXP (x, 1)) 6564 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) 6565 >= GET_MODE_BITSIZE (GET_MODE (x))) 6566 && exact_log2 (mask + 1) >= 0 6567 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 6568 >= exact_log2 (mask + 1))) 6569 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), 6570 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x)) 6571 - exact_log2 (mask + 1))); 6572 break; 6573 6574 case ASHIFTRT: 6575 /* If we are just looking for the sign bit, we don't need this shift at 6576 all, even if it has a variable count. */ 6577 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 6578 && (mask == ((unsigned HOST_WIDE_INT) 1 6579 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 6580 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 6581 6582 /* If this is a shift by a constant, get a mask that contains those bits 6583 that are not copies of the sign bit. We then have two cases: If 6584 MASK only includes those bits, this can be a logical shift, which may 6585 allow simplifications. If MASK is a single-bit field not within 6586 those bits, we are requesting a copy of the sign bit and hence can 6587 shift the sign bit to the appropriate location. */ 6588 6589 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0 6590 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 6591 { 6592 int i = -1; 6593 6594 /* If the considered data is wider then HOST_WIDE_INT, we can't 6595 represent a mask for all its bits in a single scalar. 6596 But we only care about the lower bits, so calculate these. */ 6597 6598 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT) 6599 { 6600 nonzero = ~ (HOST_WIDE_INT) 0; 6601 6602 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 6603 is the number of bits a full-width mask would have set. 6604 We need only shift if these are fewer than nonzero can 6605 hold. If not, we must keep all bits set in nonzero. */ 6606 6607 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 6608 < HOST_BITS_PER_WIDE_INT) 6609 nonzero >>= INTVAL (XEXP (x, 1)) 6610 + HOST_BITS_PER_WIDE_INT 6611 - GET_MODE_BITSIZE (GET_MODE (x)) ; 6612 } 6613 else 6614 { 6615 nonzero = GET_MODE_MASK (GET_MODE (x)); 6616 nonzero >>= INTVAL (XEXP (x, 1)); 6617 } 6618 6619 if ((mask & ~ nonzero) == 0 6620 || (i = exact_log2 (mask)) >= 0) 6621 { 6622 x = simplify_shift_const 6623 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0), 6624 i < 0 ? INTVAL (XEXP (x, 1)) 6625 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i); 6626 6627 if (GET_CODE (x) != ASHIFTRT) 6628 return force_to_mode (x, mode, mask, reg, next_select); 6629 } 6630 } 6631 6632 /* If MASK is 1, convert this to a LSHIFTRT. This can be done 6633 even if the shift count isn't a constant. */ 6634 if (mask == 1) 6635 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)); 6636 6637 /* If this is a sign-extension operation that just affects bits 6638 we don't care about, remove it. Be sure the call above returned 6639 something that is still a shift. */ 6640 6641 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) 6642 && GET_CODE (XEXP (x, 1)) == CONST_INT 6643 && INTVAL (XEXP (x, 1)) >= 0 6644 && (INTVAL (XEXP (x, 1)) 6645 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1)) 6646 && GET_CODE (XEXP (x, 0)) == ASHIFT 6647 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6648 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1))) 6649 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, 6650 reg, next_select); 6651 6652 break; 6653 6654 case ROTATE: 6655 case ROTATERT: 6656 /* If the shift count is constant and we can do computations 6657 in the mode of X, compute where the bits we care about are. 6658 Otherwise, we can't do anything. Don't change the mode of 6659 the shift or propagate MODE into the shift, though. */ 6660 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6661 && INTVAL (XEXP (x, 1)) >= 0) 6662 { 6663 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, 6664 GET_MODE (x), GEN_INT (mask), 6665 XEXP (x, 1)); 6666 if (temp && GET_CODE(temp) == CONST_INT) 6667 SUBST (XEXP (x, 0), 6668 force_to_mode (XEXP (x, 0), GET_MODE (x), 6669 INTVAL (temp), reg, next_select)); 6670 } 6671 break; 6672 6673 case NEG: 6674 /* If we just want the low-order bit, the NEG isn't needed since it 6675 won't change the low-order bit. */ 6676 if (mask == 1) 6677 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select); 6678 6679 /* We need any bits less significant than the most significant bit in 6680 MASK since carries from those bits will affect the bits we are 6681 interested in. */ 6682 mask = fuller_mask; 6683 goto unop; 6684 6685 case NOT: 6686 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the 6687 same as the XOR case above. Ensure that the constant we form is not 6688 wider than the mode of X. */ 6689 6690 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6691 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6692 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 6693 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) 6694 < GET_MODE_BITSIZE (GET_MODE (x))) 6695 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) 6696 { 6697 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1))); 6698 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp); 6699 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1)); 6700 6701 return force_to_mode (x, mode, mask, reg, next_select); 6702 } 6703 6704 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must 6705 use the full mask inside the NOT. */ 6706 mask = fuller_mask; 6707 6708 unop: 6709 op0 = gen_lowpart_for_combine (op_mode, 6710 force_to_mode (XEXP (x, 0), mode, mask, 6711 reg, next_select)); 6712 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 6713 x = gen_unary (code, op_mode, op_mode, op0); 6714 break; 6715 6716 case NE: 6717 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included 6718 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, 6719 which is equal to STORE_FLAG_VALUE. */ 6720 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx 6721 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0 6722 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE) 6723 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 6724 6725 break; 6726 6727 case IF_THEN_ELSE: 6728 /* We have no way of knowing if the IF_THEN_ELSE can itself be 6729 written in a narrower mode. We play it safe and do not do so. */ 6730 6731 SUBST (XEXP (x, 1), 6732 gen_lowpart_for_combine (GET_MODE (x), 6733 force_to_mode (XEXP (x, 1), mode, 6734 mask, reg, next_select))); 6735 SUBST (XEXP (x, 2), 6736 gen_lowpart_for_combine (GET_MODE (x), 6737 force_to_mode (XEXP (x, 2), mode, 6738 mask, reg,next_select))); 6739 break; 6740 6741 default: 6742 break; 6743 } 6744 6745 /* Ensure we return a value of the proper mode. */ 6746 return gen_lowpart_for_combine (mode, x); 6747} 6748 6749/* Return nonzero if X is an expression that has one of two values depending on 6750 whether some other value is zero or nonzero. In that case, we return the 6751 value that is being tested, *PTRUE is set to the value if the rtx being 6752 returned has a nonzero value, and *PFALSE is set to the other alternative. 6753 6754 If we return zero, we set *PTRUE and *PFALSE to X. */ 6755 6756static rtx 6757if_then_else_cond (x, ptrue, pfalse) 6758 rtx x; 6759 rtx *ptrue, *pfalse; 6760{ 6761 enum machine_mode mode = GET_MODE (x); 6762 enum rtx_code code = GET_CODE (x); 6763 int size = GET_MODE_BITSIZE (mode); 6764 rtx cond0, cond1, true0, true1, false0, false1; 6765 unsigned HOST_WIDE_INT nz; 6766 6767 /* If this is a unary operation whose operand has one of two values, apply 6768 our opcode to compute those values. */ 6769 if (GET_RTX_CLASS (code) == '1' 6770 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) 6771 { 6772 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0); 6773 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0); 6774 return cond0; 6775 } 6776 6777 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would 6778 make can't possibly match and would suppress other optimizations. */ 6779 else if (code == COMPARE) 6780 ; 6781 6782 /* If this is a binary operation, see if either side has only one of two 6783 values. If either one does or if both do and they are conditional on 6784 the same value, compute the new true and false values. */ 6785 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2' 6786 || GET_RTX_CLASS (code) == '<') 6787 { 6788 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0); 6789 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1); 6790 6791 if ((cond0 != 0 || cond1 != 0) 6792 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1))) 6793 { 6794 /* If if_then_else_cond returned zero, then true/false are the 6795 same rtl. We must copy one of them to prevent invalid rtl 6796 sharing. */ 6797 if (cond0 == 0) 6798 true0 = copy_rtx (true0); 6799 else if (cond1 == 0) 6800 true1 = copy_rtx (true1); 6801 6802 *ptrue = gen_binary (code, mode, true0, true1); 6803 *pfalse = gen_binary (code, mode, false0, false1); 6804 return cond0 ? cond0 : cond1; 6805 } 6806 6807 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the 6808 operands is zero when the other is non-zero, and vice-versa, 6809 and STORE_FLAG_VALUE is 1 or -1. */ 6810 6811 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 6812 && (code == PLUS || code == IOR || code == XOR || code == MINUS 6813 || code == UMAX) 6814 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 6815 { 6816 rtx op0 = XEXP (XEXP (x, 0), 1); 6817 rtx op1 = XEXP (XEXP (x, 1), 1); 6818 6819 cond0 = XEXP (XEXP (x, 0), 0); 6820 cond1 = XEXP (XEXP (x, 1), 0); 6821 6822 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<' 6823 && GET_RTX_CLASS (GET_CODE (cond1)) == '<' 6824 && reversible_comparison_p (cond1) 6825 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1)) 6826 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 6827 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 6828 || ((swap_condition (GET_CODE (cond0)) 6829 == reverse_condition (GET_CODE (cond1))) 6830 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 6831 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 6832 && ! side_effects_p (x)) 6833 { 6834 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx); 6835 *pfalse = gen_binary (MULT, mode, 6836 (code == MINUS 6837 ? gen_unary (NEG, mode, mode, op1) : op1), 6838 const_true_rtx); 6839 return cond0; 6840 } 6841 } 6842 6843 /* Similarly for MULT, AND and UMIN, execpt that for these the result 6844 is always zero. */ 6845 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 6846 && (code == MULT || code == AND || code == UMIN) 6847 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 6848 { 6849 cond0 = XEXP (XEXP (x, 0), 0); 6850 cond1 = XEXP (XEXP (x, 1), 0); 6851 6852 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<' 6853 && GET_RTX_CLASS (GET_CODE (cond1)) == '<' 6854 && reversible_comparison_p (cond1) 6855 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1)) 6856 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 6857 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 6858 || ((swap_condition (GET_CODE (cond0)) 6859 == reverse_condition (GET_CODE (cond1))) 6860 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 6861 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 6862 && ! side_effects_p (x)) 6863 { 6864 *ptrue = *pfalse = const0_rtx; 6865 return cond0; 6866 } 6867 } 6868 } 6869 6870 else if (code == IF_THEN_ELSE) 6871 { 6872 /* If we have IF_THEN_ELSE already, extract the condition and 6873 canonicalize it if it is NE or EQ. */ 6874 cond0 = XEXP (x, 0); 6875 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); 6876 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) 6877 return XEXP (cond0, 0); 6878 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) 6879 { 6880 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); 6881 return XEXP (cond0, 0); 6882 } 6883 else 6884 return cond0; 6885 } 6886 6887 /* If X is a normal SUBREG with both inner and outer modes integral, 6888 we can narrow both the true and false values of the inner expression, 6889 if there is a condition. */ 6890 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT 6891 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT 6892 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) 6893 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), 6894 &true0, &false0))) 6895 { 6896 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0); 6897 *pfalse 6898 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0); 6899 6900 return cond0; 6901 } 6902 6903 /* If X is a constant, this isn't special and will cause confusions 6904 if we treat it as such. Likewise if it is equivalent to a constant. */ 6905 else if (CONSTANT_P (x) 6906 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) 6907 ; 6908 6909 /* If X is known to be either 0 or -1, those are the true and 6910 false values when testing X. */ 6911 else if (num_sign_bit_copies (x, mode) == size) 6912 { 6913 *ptrue = constm1_rtx, *pfalse = const0_rtx; 6914 return x; 6915 } 6916 6917 /* Likewise for 0 or a single bit. */ 6918 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0) 6919 { 6920 *ptrue = GEN_INT (nz), *pfalse = const0_rtx; 6921 return x; 6922 } 6923 6924 /* Otherwise fail; show no condition with true and false values the same. */ 6925 *ptrue = *pfalse = x; 6926 return 0; 6927} 6928 6929/* Return the value of expression X given the fact that condition COND 6930 is known to be true when applied to REG as its first operand and VAL 6931 as its second. X is known to not be shared and so can be modified in 6932 place. 6933 6934 We only handle the simplest cases, and specifically those cases that 6935 arise with IF_THEN_ELSE expressions. */ 6936 6937static rtx 6938known_cond (x, cond, reg, val) 6939 rtx x; 6940 enum rtx_code cond; 6941 rtx reg, val; 6942{ 6943 enum rtx_code code = GET_CODE (x); 6944 rtx temp; 6945 char *fmt; 6946 int i, j; 6947 6948 if (side_effects_p (x)) 6949 return x; 6950 6951 if (cond == EQ && rtx_equal_p (x, reg)) 6952 return val; 6953 6954 /* If X is (abs REG) and we know something about REG's relationship 6955 with zero, we may be able to simplify this. */ 6956 6957 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) 6958 switch (cond) 6959 { 6960 case GE: case GT: case EQ: 6961 return XEXP (x, 0); 6962 case LT: case LE: 6963 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)), 6964 XEXP (x, 0)); 6965 default: 6966 break; 6967 } 6968 6969 /* The only other cases we handle are MIN, MAX, and comparisons if the 6970 operands are the same as REG and VAL. */ 6971 6972 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') 6973 { 6974 if (rtx_equal_p (XEXP (x, 0), val)) 6975 cond = swap_condition (cond), temp = val, val = reg, reg = temp; 6976 6977 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) 6978 { 6979 if (GET_RTX_CLASS (code) == '<') 6980 return (comparison_dominates_p (cond, code) ? const_true_rtx 6981 : (comparison_dominates_p (cond, 6982 reverse_condition (code)) 6983 ? const0_rtx : x)); 6984 6985 else if (code == SMAX || code == SMIN 6986 || code == UMIN || code == UMAX) 6987 { 6988 int unsignedp = (code == UMIN || code == UMAX); 6989 6990 if (code == SMAX || code == UMAX) 6991 cond = reverse_condition (cond); 6992 6993 switch (cond) 6994 { 6995 case GE: case GT: 6996 return unsignedp ? x : XEXP (x, 1); 6997 case LE: case LT: 6998 return unsignedp ? x : XEXP (x, 0); 6999 case GEU: case GTU: 7000 return unsignedp ? XEXP (x, 1) : x; 7001 case LEU: case LTU: 7002 return unsignedp ? XEXP (x, 0) : x; 7003 default: 7004 break; 7005 } 7006 } 7007 } 7008 } 7009 7010 fmt = GET_RTX_FORMAT (code); 7011 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 7012 { 7013 if (fmt[i] == 'e') 7014 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); 7015 else if (fmt[i] == 'E') 7016 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 7017 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), 7018 cond, reg, val)); 7019 } 7020 7021 return x; 7022} 7023 7024/* See if X and Y are equal for the purposes of seeing if we can rewrite an 7025 assignment as a field assignment. */ 7026 7027static int 7028rtx_equal_for_field_assignment_p (x, y) 7029 rtx x; 7030 rtx y; 7031{ 7032 if (x == y || rtx_equal_p (x, y)) 7033 return 1; 7034 7035 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) 7036 return 0; 7037 7038 /* Check for a paradoxical SUBREG of a MEM compared with the MEM. 7039 Note that all SUBREGs of MEM are paradoxical; otherwise they 7040 would have been rewritten. */ 7041 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG 7042 && GET_CODE (SUBREG_REG (y)) == MEM 7043 && rtx_equal_p (SUBREG_REG (y), 7044 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x))) 7045 return 1; 7046 7047 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG 7048 && GET_CODE (SUBREG_REG (x)) == MEM 7049 && rtx_equal_p (SUBREG_REG (x), 7050 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y))) 7051 return 1; 7052 7053 /* We used to see if get_last_value of X and Y were the same but that's 7054 not correct. In one direction, we'll cause the assignment to have 7055 the wrong destination and in the case, we'll import a register into this 7056 insn that might have already have been dead. So fail if none of the 7057 above cases are true. */ 7058 return 0; 7059} 7060 7061/* See if X, a SET operation, can be rewritten as a bit-field assignment. 7062 Return that assignment if so. 7063 7064 We only handle the most common cases. */ 7065 7066static rtx 7067make_field_assignment (x) 7068 rtx x; 7069{ 7070 rtx dest = SET_DEST (x); 7071 rtx src = SET_SRC (x); 7072 rtx assign; 7073 rtx rhs, lhs; 7074 HOST_WIDE_INT c1; 7075 int pos, len; 7076 rtx other; 7077 enum machine_mode mode; 7078 7079 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is 7080 a clear of a one-bit field. We will have changed it to 7081 (and (rotate (const_int -2) POS) DEST), so check for that. Also check 7082 for a SUBREG. */ 7083 7084 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE 7085 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT 7086 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 7087 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7088 { 7089 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 7090 1, 1, 1, 0); 7091 if (assign != 0) 7092 return gen_rtx_SET (VOIDmode, assign, const0_rtx); 7093 return x; 7094 } 7095 7096 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG 7097 && subreg_lowpart_p (XEXP (src, 0)) 7098 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) 7099 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) 7100 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE 7101 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 7102 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7103 { 7104 assign = make_extraction (VOIDmode, dest, 0, 7105 XEXP (SUBREG_REG (XEXP (src, 0)), 1), 7106 1, 1, 1, 0); 7107 if (assign != 0) 7108 return gen_rtx_SET (VOIDmode, assign, const0_rtx); 7109 return x; 7110 } 7111 7112 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a 7113 one-bit field. */ 7114 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT 7115 && XEXP (XEXP (src, 0), 0) == const1_rtx 7116 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7117 { 7118 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 7119 1, 1, 1, 0); 7120 if (assign != 0) 7121 return gen_rtx_SET (VOIDmode, assign, const1_rtx); 7122 return x; 7123 } 7124 7125 /* The other case we handle is assignments into a constant-position 7126 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents 7127 a mask that has all one bits except for a group of zero bits and 7128 OTHER is known to have zeros where C1 has ones, this is such an 7129 assignment. Compute the position and length from C1. Shift OTHER 7130 to the appropriate position, force it to the required mode, and 7131 make the extraction. Check for the AND in both operands. */ 7132 7133 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) 7134 return x; 7135 7136 rhs = expand_compound_operation (XEXP (src, 0)); 7137 lhs = expand_compound_operation (XEXP (src, 1)); 7138 7139 if (GET_CODE (rhs) == AND 7140 && GET_CODE (XEXP (rhs, 1)) == CONST_INT 7141 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) 7142 c1 = INTVAL (XEXP (rhs, 1)), other = lhs; 7143 else if (GET_CODE (lhs) == AND 7144 && GET_CODE (XEXP (lhs, 1)) == CONST_INT 7145 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) 7146 c1 = INTVAL (XEXP (lhs, 1)), other = rhs; 7147 else 7148 return x; 7149 7150 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len); 7151 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest)) 7152 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT 7153 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0) 7154 return x; 7155 7156 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); 7157 if (assign == 0) 7158 return x; 7159 7160 /* The mode to use for the source is the mode of the assignment, or of 7161 what is inside a possible STRICT_LOW_PART. */ 7162 mode = (GET_CODE (assign) == STRICT_LOW_PART 7163 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); 7164 7165 /* Shift OTHER right POS places and make it the source, restricting it 7166 to the proper length and mode. */ 7167 7168 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT, 7169 GET_MODE (src), other, pos), 7170 mode, 7171 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT 7172 ? GET_MODE_MASK (mode) 7173 : ((HOST_WIDE_INT) 1 << len) - 1, 7174 dest, 0); 7175 7176 return gen_rtx_combine (SET, VOIDmode, assign, src); 7177} 7178 7179/* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) 7180 if so. */ 7181 7182static rtx 7183apply_distributive_law (x) 7184 rtx x; 7185{ 7186 enum rtx_code code = GET_CODE (x); 7187 rtx lhs, rhs, other; 7188 rtx tem; 7189 enum rtx_code inner_code; 7190 7191 /* Distributivity is not true for floating point. 7192 It can change the value. So don't do it. 7193 -- rms and moshier@world.std.com. */ 7194 if (FLOAT_MODE_P (GET_MODE (x))) 7195 return x; 7196 7197 /* The outer operation can only be one of the following: */ 7198 if (code != IOR && code != AND && code != XOR 7199 && code != PLUS && code != MINUS) 7200 return x; 7201 7202 lhs = XEXP (x, 0), rhs = XEXP (x, 1); 7203 7204 /* If either operand is a primitive we can't do anything, so get out 7205 fast. */ 7206 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o' 7207 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o') 7208 return x; 7209 7210 lhs = expand_compound_operation (lhs); 7211 rhs = expand_compound_operation (rhs); 7212 inner_code = GET_CODE (lhs); 7213 if (inner_code != GET_CODE (rhs)) 7214 return x; 7215 7216 /* See if the inner and outer operations distribute. */ 7217 switch (inner_code) 7218 { 7219 case LSHIFTRT: 7220 case ASHIFTRT: 7221 case AND: 7222 case IOR: 7223 /* These all distribute except over PLUS. */ 7224 if (code == PLUS || code == MINUS) 7225 return x; 7226 break; 7227 7228 case MULT: 7229 if (code != PLUS && code != MINUS) 7230 return x; 7231 break; 7232 7233 case ASHIFT: 7234 /* This is also a multiply, so it distributes over everything. */ 7235 break; 7236 7237 case SUBREG: 7238 /* Non-paradoxical SUBREGs distributes over all operations, provided 7239 the inner modes and word numbers are the same, this is an extraction 7240 of a low-order part, we don't convert an fp operation to int or 7241 vice versa, and we would not be converting a single-word 7242 operation into a multi-word operation. The latter test is not 7243 required, but it prevents generating unneeded multi-word operations. 7244 Some of the previous tests are redundant given the latter test, but 7245 are retained because they are required for correctness. 7246 7247 We produce the result slightly differently in this case. */ 7248 7249 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs)) 7250 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs) 7251 || ! subreg_lowpart_p (lhs) 7252 || (GET_MODE_CLASS (GET_MODE (lhs)) 7253 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) 7254 || (GET_MODE_SIZE (GET_MODE (lhs)) 7255 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) 7256 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD) 7257 return x; 7258 7259 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)), 7260 SUBREG_REG (lhs), SUBREG_REG (rhs)); 7261 return gen_lowpart_for_combine (GET_MODE (x), tem); 7262 7263 default: 7264 return x; 7265 } 7266 7267 /* Set LHS and RHS to the inner operands (A and B in the example 7268 above) and set OTHER to the common operand (C in the example). 7269 These is only one way to do this unless the inner operation is 7270 commutative. */ 7271 if (GET_RTX_CLASS (inner_code) == 'c' 7272 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) 7273 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); 7274 else if (GET_RTX_CLASS (inner_code) == 'c' 7275 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) 7276 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); 7277 else if (GET_RTX_CLASS (inner_code) == 'c' 7278 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) 7279 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); 7280 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) 7281 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); 7282 else 7283 return x; 7284 7285 /* Form the new inner operation, seeing if it simplifies first. */ 7286 tem = gen_binary (code, GET_MODE (x), lhs, rhs); 7287 7288 /* There is one exception to the general way of distributing: 7289 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */ 7290 if (code == XOR && inner_code == IOR) 7291 { 7292 inner_code = AND; 7293 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other); 7294 } 7295 7296 /* We may be able to continuing distributing the result, so call 7297 ourselves recursively on the inner operation before forming the 7298 outer operation, which we return. */ 7299 return gen_binary (inner_code, GET_MODE (x), 7300 apply_distributive_law (tem), other); 7301} 7302 7303/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done 7304 in MODE. 7305 7306 Return an equivalent form, if different from X. Otherwise, return X. If 7307 X is zero, we are to always construct the equivalent form. */ 7308 7309static rtx 7310simplify_and_const_int (x, mode, varop, constop) 7311 rtx x; 7312 enum machine_mode mode; 7313 rtx varop; 7314 unsigned HOST_WIDE_INT constop; 7315{ 7316 unsigned HOST_WIDE_INT nonzero; 7317 int width = GET_MODE_BITSIZE (mode); 7318 int i; 7319 7320 /* Simplify VAROP knowing that we will be only looking at some of the 7321 bits in it. */ 7322 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0); 7323 7324 /* If VAROP is a CLOBBER, we will fail so return it; if it is a 7325 CONST_INT, we are done. */ 7326 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT) 7327 return varop; 7328 7329 /* See what bits may be nonzero in VAROP. Unlike the general case of 7330 a call to nonzero_bits, here we don't care about bits outside 7331 MODE. */ 7332 7333 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); 7334 7335 /* If this would be an entire word for the target, but is not for 7336 the host, then sign-extend on the host so that the number will look 7337 the same way on the host that it would on the target. 7338 7339 For example, when building a 64 bit alpha hosted 32 bit sparc 7340 targeted compiler, then we want the 32 bit unsigned value -1 to be 7341 represented as a 64 bit value -1, and not as 0x00000000ffffffff. 7342 The later confuses the sparc backend. */ 7343 7344 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width 7345 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1)))) 7346 nonzero |= ((HOST_WIDE_INT) (-1) << width); 7347 7348 /* Turn off all bits in the constant that are known to already be zero. 7349 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS 7350 which is tested below. */ 7351 7352 constop &= nonzero; 7353 7354 /* If we don't have any bits left, return zero. */ 7355 if (constop == 0) 7356 return const0_rtx; 7357 7358 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is 7359 a power of two, we can replace this with a ASHIFT. */ 7360 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 7361 && (i = exact_log2 (constop)) >= 0) 7362 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); 7363 7364 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR 7365 or XOR, then try to apply the distributive law. This may eliminate 7366 operations if either branch can be simplified because of the AND. 7367 It may also make some cases more complex, but those cases probably 7368 won't match a pattern either with or without this. */ 7369 7370 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) 7371 return 7372 gen_lowpart_for_combine 7373 (mode, 7374 apply_distributive_law 7375 (gen_binary (GET_CODE (varop), GET_MODE (varop), 7376 simplify_and_const_int (NULL_RTX, GET_MODE (varop), 7377 XEXP (varop, 0), constop), 7378 simplify_and_const_int (NULL_RTX, GET_MODE (varop), 7379 XEXP (varop, 1), constop)))); 7380 7381 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG 7382 if we already had one (just check for the simplest cases). */ 7383 if (x && GET_CODE (XEXP (x, 0)) == SUBREG 7384 && GET_MODE (XEXP (x, 0)) == mode 7385 && SUBREG_REG (XEXP (x, 0)) == varop) 7386 varop = XEXP (x, 0); 7387 else 7388 varop = gen_lowpart_for_combine (mode, varop); 7389 7390 /* If we can't make the SUBREG, try to return what we were given. */ 7391 if (GET_CODE (varop) == CLOBBER) 7392 return x ? x : varop; 7393 7394 /* If we are only masking insignificant bits, return VAROP. */ 7395 if (constop == nonzero) 7396 x = varop; 7397 7398 /* Otherwise, return an AND. See how much, if any, of X we can use. */ 7399 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode) 7400 x = gen_binary (AND, mode, varop, GEN_INT (constop)); 7401 7402 else 7403 { 7404 if (GET_CODE (XEXP (x, 1)) != CONST_INT 7405 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop) 7406 SUBST (XEXP (x, 1), GEN_INT (constop)); 7407 7408 SUBST (XEXP (x, 0), varop); 7409 } 7410 7411 return x; 7412} 7413 7414/* We let num_sign_bit_copies recur into nonzero_bits as that is useful. 7415 We don't let nonzero_bits recur into num_sign_bit_copies, because that 7416 is less useful. We can't allow both, because that results in exponential 7417 run time recursion. There is a nullstone testcase that triggered 7418 this. This macro avoids accidental uses of num_sign_bit_copies. */ 7419#define num_sign_bit_copies() 7420 7421/* Given an expression, X, compute which bits in X can be non-zero. 7422 We don't care about bits outside of those defined in MODE. 7423 7424 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is 7425 a shift, AND, or zero_extract, we can do better. */ 7426 7427static unsigned HOST_WIDE_INT 7428nonzero_bits (x, mode) 7429 rtx x; 7430 enum machine_mode mode; 7431{ 7432 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode); 7433 unsigned HOST_WIDE_INT inner_nz; 7434 enum rtx_code code; 7435 int mode_width = GET_MODE_BITSIZE (mode); 7436 rtx tem; 7437 7438 /* For floating-point values, assume all bits are needed. */ 7439 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode)) 7440 return nonzero; 7441 7442 /* If X is wider than MODE, use its mode instead. */ 7443 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width) 7444 { 7445 mode = GET_MODE (x); 7446 nonzero = GET_MODE_MASK (mode); 7447 mode_width = GET_MODE_BITSIZE (mode); 7448 } 7449 7450 if (mode_width > HOST_BITS_PER_WIDE_INT) 7451 /* Our only callers in this case look for single bit values. So 7452 just return the mode mask. Those tests will then be false. */ 7453 return nonzero; 7454 7455#ifndef WORD_REGISTER_OPERATIONS 7456 /* If MODE is wider than X, but both are a single word for both the host 7457 and target machines, we can compute this from which bits of the 7458 object might be nonzero in its own mode, taking into account the fact 7459 that on many CISC machines, accessing an object in a wider mode 7460 causes the high-order bits to become undefined. So they are 7461 not known to be zero. */ 7462 7463 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode 7464 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD 7465 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 7466 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x))) 7467 { 7468 nonzero &= nonzero_bits (x, GET_MODE (x)); 7469 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)); 7470 return nonzero; 7471 } 7472#endif 7473 7474 code = GET_CODE (x); 7475 switch (code) 7476 { 7477 case REG: 7478#ifdef POINTERS_EXTEND_UNSIGNED 7479 /* If pointers extend unsigned and this is a pointer in Pmode, say that 7480 all the bits above ptr_mode are known to be zero. */ 7481 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode 7482 && REGNO_POINTER_FLAG (REGNO (x))) 7483 nonzero &= GET_MODE_MASK (ptr_mode); 7484#endif 7485 7486#ifdef STACK_BOUNDARY 7487 /* If this is the stack pointer, we may know something about its 7488 alignment. If PUSH_ROUNDING is defined, it is possible for the 7489 stack to be momentarily aligned only to that amount, so we pick 7490 the least alignment. */ 7491 7492 /* We can't check for arg_pointer_rtx here, because it is not 7493 guaranteed to have as much alignment as the stack pointer. 7494 In particular, in the Irix6 n64 ABI, the stack has 128 bit 7495 alignment but the argument pointer has only 64 bit alignment. */ 7496 7497 if ((x == frame_pointer_rtx 7498 || x == stack_pointer_rtx 7499 || x == hard_frame_pointer_rtx 7500 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER 7501 && REGNO (x) <= LAST_VIRTUAL_REGISTER)) 7502#ifdef STACK_BIAS 7503 && !STACK_BIAS 7504#endif 7505 ) 7506 { 7507 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; 7508 7509#ifdef PUSH_ROUNDING 7510 if (REGNO (x) == STACK_POINTER_REGNUM) 7511 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment); 7512#endif 7513 7514 /* We must return here, otherwise we may get a worse result from 7515 one of the choices below. There is nothing useful below as 7516 far as the stack pointer is concerned. */ 7517 return nonzero &= ~ (sp_alignment - 1); 7518 } 7519#endif 7520 7521 /* If X is a register whose nonzero bits value is current, use it. 7522 Otherwise, if X is a register whose value we can find, use that 7523 value. Otherwise, use the previously-computed global nonzero bits 7524 for this register. */ 7525 7526 if (reg_last_set_value[REGNO (x)] != 0 7527 && reg_last_set_mode[REGNO (x)] == mode 7528 && (REG_N_SETS (REGNO (x)) == 1 7529 || reg_last_set_label[REGNO (x)] == label_tick) 7530 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) 7531 return reg_last_set_nonzero_bits[REGNO (x)]; 7532 7533 tem = get_last_value (x); 7534 7535 if (tem) 7536 { 7537#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 7538 /* If X is narrower than MODE and TEM is a non-negative 7539 constant that would appear negative in the mode of X, 7540 sign-extend it for use in reg_nonzero_bits because some 7541 machines (maybe most) will actually do the sign-extension 7542 and this is the conservative approach. 7543 7544 ??? For 2.5, try to tighten up the MD files in this regard 7545 instead of this kludge. */ 7546 7547 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width 7548 && GET_CODE (tem) == CONST_INT 7549 && INTVAL (tem) > 0 7550 && 0 != (INTVAL (tem) 7551 & ((HOST_WIDE_INT) 1 7552 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 7553 tem = GEN_INT (INTVAL (tem) 7554 | ((HOST_WIDE_INT) (-1) 7555 << GET_MODE_BITSIZE (GET_MODE (x)))); 7556#endif 7557 return nonzero_bits (tem, mode); 7558 } 7559 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)]) 7560 return reg_nonzero_bits[REGNO (x)] & nonzero; 7561 else 7562 return nonzero; 7563 7564 case CONST_INT: 7565#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 7566 /* If X is negative in MODE, sign-extend the value. */ 7567 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD 7568 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1)))) 7569 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width)); 7570#endif 7571 7572 return INTVAL (x); 7573 7574 case MEM: 7575#ifdef LOAD_EXTEND_OP 7576 /* In many, if not most, RISC machines, reading a byte from memory 7577 zeros the rest of the register. Noticing that fact saves a lot 7578 of extra zero-extends. */ 7579 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND) 7580 nonzero &= GET_MODE_MASK (GET_MODE (x)); 7581#endif 7582 break; 7583 7584 case EQ: case NE: 7585 case GT: case GTU: 7586 case LT: case LTU: 7587 case GE: case GEU: 7588 case LE: case LEU: 7589 7590 /* If this produces an integer result, we know which bits are set. 7591 Code here used to clear bits outside the mode of X, but that is 7592 now done above. */ 7593 7594 if (GET_MODE_CLASS (mode) == MODE_INT 7595 && mode_width <= HOST_BITS_PER_WIDE_INT) 7596 nonzero = STORE_FLAG_VALUE; 7597 break; 7598 7599 case NEG: 7600#if 0 7601 /* Disabled to avoid exponential mutual recursion between nonzero_bits 7602 and num_sign_bit_copies. */ 7603 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) 7604 == GET_MODE_BITSIZE (GET_MODE (x))) 7605 nonzero = 1; 7606#endif 7607 7608 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width) 7609 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x))); 7610 break; 7611 7612 case ABS: 7613#if 0 7614 /* Disabled to avoid exponential mutual recursion between nonzero_bits 7615 and num_sign_bit_copies. */ 7616 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) 7617 == GET_MODE_BITSIZE (GET_MODE (x))) 7618 nonzero = 1; 7619#endif 7620 break; 7621 7622 case TRUNCATE: 7623 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode)); 7624 break; 7625 7626 case ZERO_EXTEND: 7627 nonzero &= nonzero_bits (XEXP (x, 0), mode); 7628 if (GET_MODE (XEXP (x, 0)) != VOIDmode) 7629 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); 7630 break; 7631 7632 case SIGN_EXTEND: 7633 /* If the sign bit is known clear, this is the same as ZERO_EXTEND. 7634 Otherwise, show all the bits in the outer mode but not the inner 7635 may be non-zero. */ 7636 inner_nz = nonzero_bits (XEXP (x, 0), mode); 7637 if (GET_MODE (XEXP (x, 0)) != VOIDmode) 7638 { 7639 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); 7640 if (inner_nz 7641 & (((HOST_WIDE_INT) 1 7642 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))) 7643 inner_nz |= (GET_MODE_MASK (mode) 7644 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))); 7645 } 7646 7647 nonzero &= inner_nz; 7648 break; 7649 7650 case AND: 7651 nonzero &= (nonzero_bits (XEXP (x, 0), mode) 7652 & nonzero_bits (XEXP (x, 1), mode)); 7653 break; 7654 7655 case XOR: case IOR: 7656 case UMIN: case UMAX: case SMIN: case SMAX: 7657 nonzero &= (nonzero_bits (XEXP (x, 0), mode) 7658 | nonzero_bits (XEXP (x, 1), mode)); 7659 break; 7660 7661 case PLUS: case MINUS: 7662 case MULT: 7663 case DIV: case UDIV: 7664 case MOD: case UMOD: 7665 /* We can apply the rules of arithmetic to compute the number of 7666 high- and low-order zero bits of these operations. We start by 7667 computing the width (position of the highest-order non-zero bit) 7668 and the number of low-order zero bits for each value. */ 7669 { 7670 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode); 7671 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode); 7672 int width0 = floor_log2 (nz0) + 1; 7673 int width1 = floor_log2 (nz1) + 1; 7674 int low0 = floor_log2 (nz0 & -nz0); 7675 int low1 = floor_log2 (nz1 & -nz1); 7676 HOST_WIDE_INT op0_maybe_minusp 7677 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); 7678 HOST_WIDE_INT op1_maybe_minusp 7679 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); 7680 int result_width = mode_width; 7681 int result_low = 0; 7682 7683 switch (code) 7684 { 7685 case PLUS: 7686#ifdef STACK_BIAS 7687 if (STACK_BIAS 7688 && (XEXP (x, 0) == stack_pointer_rtx 7689 || XEXP (x, 0) == frame_pointer_rtx) 7690 && GET_CODE (XEXP (x, 1)) == CONST_INT) 7691 { 7692 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; 7693 7694 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1)); 7695 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS; 7696 width0 = floor_log2 (nz0) + 1; 7697 width1 = floor_log2 (nz1) + 1; 7698 low0 = floor_log2 (nz0 & -nz0); 7699 low1 = floor_log2 (nz1 & -nz1); 7700 } 7701#endif 7702 result_width = MAX (width0, width1) + 1; 7703 result_low = MIN (low0, low1); 7704 break; 7705 case MINUS: 7706 result_low = MIN (low0, low1); 7707 break; 7708 case MULT: 7709 result_width = width0 + width1; 7710 result_low = low0 + low1; 7711 break; 7712 case DIV: 7713 if (! op0_maybe_minusp && ! op1_maybe_minusp) 7714 result_width = width0; 7715 break; 7716 case UDIV: 7717 result_width = width0; 7718 break; 7719 case MOD: 7720 if (! op0_maybe_minusp && ! op1_maybe_minusp) 7721 result_width = MIN (width0, width1); 7722 result_low = MIN (low0, low1); 7723 break; 7724 case UMOD: 7725 result_width = MIN (width0, width1); 7726 result_low = MIN (low0, low1); 7727 break; 7728 default: 7729 abort (); 7730 } 7731 7732 if (result_width < mode_width) 7733 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1; 7734 7735 if (result_low > 0) 7736 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1); 7737 } 7738 break; 7739 7740 case ZERO_EXTRACT: 7741 if (GET_CODE (XEXP (x, 1)) == CONST_INT 7742 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 7743 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1; 7744 break; 7745 7746 case SUBREG: 7747 /* If this is a SUBREG formed for a promoted variable that has 7748 been zero-extended, we know that at least the high-order bits 7749 are zero, though others might be too. */ 7750 7751 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x)) 7752 nonzero = (GET_MODE_MASK (GET_MODE (x)) 7753 & nonzero_bits (SUBREG_REG (x), GET_MODE (x))); 7754 7755 /* If the inner mode is a single word for both the host and target 7756 machines, we can compute this from which bits of the inner 7757 object might be nonzero. */ 7758 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD 7759 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) 7760 <= HOST_BITS_PER_WIDE_INT)) 7761 { 7762 nonzero &= nonzero_bits (SUBREG_REG (x), mode); 7763 7764#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP) 7765 /* If this is a typical RISC machine, we only have to worry 7766 about the way loads are extended. */ 7767 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND 7768 ? (nonzero 7769 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))) 7770 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND) 7771#endif 7772 { 7773 /* On many CISC machines, accessing an object in a wider mode 7774 causes the high-order bits to become undefined. So they are 7775 not known to be zero. */ 7776 if (GET_MODE_SIZE (GET_MODE (x)) 7777 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 7778 nonzero |= (GET_MODE_MASK (GET_MODE (x)) 7779 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))); 7780 } 7781 } 7782 break; 7783 7784 case ASHIFTRT: 7785 case LSHIFTRT: 7786 case ASHIFT: 7787 case ROTATE: 7788 /* The nonzero bits are in two classes: any bits within MODE 7789 that aren't in GET_MODE (x) are always significant. The rest of the 7790 nonzero bits are those that are significant in the operand of 7791 the shift when shifted the appropriate number of bits. This 7792 shows that high-order bits are cleared by the right shift and 7793 low-order bits by left shifts. */ 7794 if (GET_CODE (XEXP (x, 1)) == CONST_INT 7795 && INTVAL (XEXP (x, 1)) >= 0 7796 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 7797 { 7798 enum machine_mode inner_mode = GET_MODE (x); 7799 int width = GET_MODE_BITSIZE (inner_mode); 7800 int count = INTVAL (XEXP (x, 1)); 7801 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode); 7802 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode); 7803 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask; 7804 unsigned HOST_WIDE_INT outer = 0; 7805 7806 if (mode_width > width) 7807 outer = (op_nonzero & nonzero & ~ mode_mask); 7808 7809 if (code == LSHIFTRT) 7810 inner >>= count; 7811 else if (code == ASHIFTRT) 7812 { 7813 inner >>= count; 7814 7815 /* If the sign bit may have been nonzero before the shift, we 7816 need to mark all the places it could have been copied to 7817 by the shift as possibly nonzero. */ 7818 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count))) 7819 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count); 7820 } 7821 else if (code == ASHIFT) 7822 inner <<= count; 7823 else 7824 inner = ((inner << (count % width) 7825 | (inner >> (width - (count % width)))) & mode_mask); 7826 7827 nonzero &= (outer | inner); 7828 } 7829 break; 7830 7831 case FFS: 7832 /* This is at most the number of bits in the mode. */ 7833 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1; 7834 break; 7835 7836 case IF_THEN_ELSE: 7837 nonzero &= (nonzero_bits (XEXP (x, 1), mode) 7838 | nonzero_bits (XEXP (x, 2), mode)); 7839 break; 7840 7841 default: 7842 break; 7843 } 7844 7845 return nonzero; 7846} 7847 7848/* See the macro definition above. */ 7849#undef num_sign_bit_copies 7850 7851/* Return the number of bits at the high-order end of X that are known to 7852 be equal to the sign bit. X will be used in mode MODE; if MODE is 7853 VOIDmode, X will be used in its own mode. The returned value will always 7854 be between 1 and the number of bits in MODE. */ 7855 7856static int 7857num_sign_bit_copies (x, mode) 7858 rtx x; 7859 enum machine_mode mode; 7860{ 7861 enum rtx_code code = GET_CODE (x); 7862 int bitwidth; 7863 int num0, num1, result; 7864 unsigned HOST_WIDE_INT nonzero; 7865 rtx tem; 7866 7867 /* If we weren't given a mode, use the mode of X. If the mode is still 7868 VOIDmode, we don't know anything. Likewise if one of the modes is 7869 floating-point. */ 7870 7871 if (mode == VOIDmode) 7872 mode = GET_MODE (x); 7873 7874 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x))) 7875 return 1; 7876 7877 bitwidth = GET_MODE_BITSIZE (mode); 7878 7879 /* For a smaller object, just ignore the high bits. */ 7880 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x))) 7881 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x)) 7882 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth))); 7883 7884 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x))) 7885 { 7886#ifndef WORD_REGISTER_OPERATIONS 7887 /* If this machine does not do all register operations on the entire 7888 register and MODE is wider than the mode of X, we can say nothing 7889 at all about the high-order bits. */ 7890 return 1; 7891#else 7892 /* Likewise on machines that do, if the mode of the object is smaller 7893 than a word and loads of that size don't sign extend, we can say 7894 nothing about the high order bits. */ 7895 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD 7896#ifdef LOAD_EXTEND_OP 7897 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND 7898#endif 7899 ) 7900 return 1; 7901#endif 7902 } 7903 7904 switch (code) 7905 { 7906 case REG: 7907 7908#ifdef POINTERS_EXTEND_UNSIGNED 7909 /* If pointers extend signed and this is a pointer in Pmode, say that 7910 all the bits above ptr_mode are known to be sign bit copies. */ 7911 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode 7912 && REGNO_POINTER_FLAG (REGNO (x))) 7913 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1; 7914#endif 7915 7916 if (reg_last_set_value[REGNO (x)] != 0 7917 && reg_last_set_mode[REGNO (x)] == mode 7918 && (REG_N_SETS (REGNO (x)) == 1 7919 || reg_last_set_label[REGNO (x)] == label_tick) 7920 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) 7921 return reg_last_set_sign_bit_copies[REGNO (x)]; 7922 7923 tem = get_last_value (x); 7924 if (tem != 0) 7925 return num_sign_bit_copies (tem, mode); 7926 7927 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0) 7928 return reg_sign_bit_copies[REGNO (x)]; 7929 break; 7930 7931 case MEM: 7932#ifdef LOAD_EXTEND_OP 7933 /* Some RISC machines sign-extend all loads of smaller than a word. */ 7934 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND) 7935 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1); 7936#endif 7937 break; 7938 7939 case CONST_INT: 7940 /* If the constant is negative, take its 1's complement and remask. 7941 Then see how many zero bits we have. */ 7942 nonzero = INTVAL (x) & GET_MODE_MASK (mode); 7943 if (bitwidth <= HOST_BITS_PER_WIDE_INT 7944 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 7945 nonzero = (~ nonzero) & GET_MODE_MASK (mode); 7946 7947 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); 7948 7949 case SUBREG: 7950 /* If this is a SUBREG for a promoted object that is sign-extended 7951 and we are looking at it in a wider mode, we know that at least the 7952 high-order bits are known to be sign bit copies. */ 7953 7954 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x)) 7955 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1, 7956 num_sign_bit_copies (SUBREG_REG (x), mode)); 7957 7958 /* For a smaller object, just ignore the high bits. */ 7959 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))) 7960 { 7961 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode); 7962 return MAX (1, (num0 7963 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) 7964 - bitwidth))); 7965 } 7966 7967#ifdef WORD_REGISTER_OPERATIONS 7968#ifdef LOAD_EXTEND_OP 7969 /* For paradoxical SUBREGs on machines where all register operations 7970 affect the entire register, just look inside. Note that we are 7971 passing MODE to the recursive call, so the number of sign bit copies 7972 will remain relative to that mode, not the inner mode. */ 7973 7974 /* This works only if loads sign extend. Otherwise, if we get a 7975 reload for the inner part, it may be loaded from the stack, and 7976 then we lose all sign bit copies that existed before the store 7977 to the stack. */ 7978 7979 if ((GET_MODE_SIZE (GET_MODE (x)) 7980 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 7981 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND) 7982 return num_sign_bit_copies (SUBREG_REG (x), mode); 7983#endif 7984#endif 7985 break; 7986 7987 case SIGN_EXTRACT: 7988 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 7989 return MAX (1, bitwidth - INTVAL (XEXP (x, 1))); 7990 break; 7991 7992 case SIGN_EXTEND: 7993 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 7994 + num_sign_bit_copies (XEXP (x, 0), VOIDmode)); 7995 7996 case TRUNCATE: 7997 /* For a smaller object, just ignore the high bits. */ 7998 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode); 7999 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 8000 - bitwidth))); 8001 8002 case NOT: 8003 return num_sign_bit_copies (XEXP (x, 0), mode); 8004 8005 case ROTATE: case ROTATERT: 8006 /* If we are rotating left by a number of bits less than the number 8007 of sign bit copies, we can just subtract that amount from the 8008 number. */ 8009 if (GET_CODE (XEXP (x, 1)) == CONST_INT 8010 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth) 8011 { 8012 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8013 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1)) 8014 : bitwidth - INTVAL (XEXP (x, 1)))); 8015 } 8016 break; 8017 8018 case NEG: 8019 /* In general, this subtracts one sign bit copy. But if the value 8020 is known to be positive, the number of sign bit copies is the 8021 same as that of the input. Finally, if the input has just one bit 8022 that might be nonzero, all the bits are copies of the sign bit. */ 8023 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8024 if (bitwidth > HOST_BITS_PER_WIDE_INT) 8025 return num0 > 1 ? num0 - 1 : 1; 8026 8027 nonzero = nonzero_bits (XEXP (x, 0), mode); 8028 if (nonzero == 1) 8029 return bitwidth; 8030 8031 if (num0 > 1 8032 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero)) 8033 num0--; 8034 8035 return num0; 8036 8037 case IOR: case AND: case XOR: 8038 case SMIN: case SMAX: case UMIN: case UMAX: 8039 /* Logical operations will preserve the number of sign-bit copies. 8040 MIN and MAX operations always return one of the operands. */ 8041 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8042 num1 = num_sign_bit_copies (XEXP (x, 1), mode); 8043 return MIN (num0, num1); 8044 8045 case PLUS: case MINUS: 8046 /* For addition and subtraction, we can have a 1-bit carry. However, 8047 if we are subtracting 1 from a positive number, there will not 8048 be such a carry. Furthermore, if the positive number is known to 8049 be 0 or 1, we know the result is either -1 or 0. */ 8050 8051 if (code == PLUS && XEXP (x, 1) == constm1_rtx 8052 && bitwidth <= HOST_BITS_PER_WIDE_INT) 8053 { 8054 nonzero = nonzero_bits (XEXP (x, 0), mode); 8055 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0) 8056 return (nonzero == 1 || nonzero == 0 ? bitwidth 8057 : bitwidth - floor_log2 (nonzero) - 1); 8058 } 8059 8060 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8061 num1 = num_sign_bit_copies (XEXP (x, 1), mode); 8062 return MAX (1, MIN (num0, num1) - 1); 8063 8064 case MULT: 8065 /* The number of bits of the product is the sum of the number of 8066 bits of both terms. However, unless one of the terms if known 8067 to be positive, we must allow for an additional bit since negating 8068 a negative number can remove one sign bit copy. */ 8069 8070 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8071 num1 = num_sign_bit_copies (XEXP (x, 1), mode); 8072 8073 result = bitwidth - (bitwidth - num0) - (bitwidth - num1); 8074 if (result > 0 8075 && (bitwidth > HOST_BITS_PER_WIDE_INT 8076 || (((nonzero_bits (XEXP (x, 0), mode) 8077 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8078 && ((nonzero_bits (XEXP (x, 1), mode) 8079 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)))) 8080 result--; 8081 8082 return MAX (1, result); 8083 8084 case UDIV: 8085 /* The result must be <= the first operand. If the first operand 8086 has the high bit set, we know nothing about the number of sign 8087 bit copies. */ 8088 if (bitwidth > HOST_BITS_PER_WIDE_INT) 8089 return 1; 8090 else if ((nonzero_bits (XEXP (x, 0), mode) 8091 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8092 return 1; 8093 else 8094 return num_sign_bit_copies (XEXP (x, 0), mode); 8095 8096 case UMOD: 8097 /* The result must be <= the scond operand. */ 8098 return num_sign_bit_copies (XEXP (x, 1), mode); 8099 8100 case DIV: 8101 /* Similar to unsigned division, except that we have to worry about 8102 the case where the divisor is negative, in which case we have 8103 to add 1. */ 8104 result = num_sign_bit_copies (XEXP (x, 0), mode); 8105 if (result > 1 8106 && (bitwidth > HOST_BITS_PER_WIDE_INT 8107 || (nonzero_bits (XEXP (x, 1), mode) 8108 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) 8109 result--; 8110 8111 return result; 8112 8113 case MOD: 8114 result = num_sign_bit_copies (XEXP (x, 1), mode); 8115 if (result > 1 8116 && (bitwidth > HOST_BITS_PER_WIDE_INT 8117 || (nonzero_bits (XEXP (x, 1), mode) 8118 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) 8119 result--; 8120 8121 return result; 8122 8123 case ASHIFTRT: 8124 /* Shifts by a constant add to the number of bits equal to the 8125 sign bit. */ 8126 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8127 if (GET_CODE (XEXP (x, 1)) == CONST_INT 8128 && INTVAL (XEXP (x, 1)) > 0) 8129 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1))); 8130 8131 return num0; 8132 8133 case ASHIFT: 8134 /* Left shifts destroy copies. */ 8135 if (GET_CODE (XEXP (x, 1)) != CONST_INT 8136 || INTVAL (XEXP (x, 1)) < 0 8137 || INTVAL (XEXP (x, 1)) >= bitwidth) 8138 return 1; 8139 8140 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8141 return MAX (1, num0 - INTVAL (XEXP (x, 1))); 8142 8143 case IF_THEN_ELSE: 8144 num0 = num_sign_bit_copies (XEXP (x, 1), mode); 8145 num1 = num_sign_bit_copies (XEXP (x, 2), mode); 8146 return MIN (num0, num1); 8147 8148 case EQ: case NE: case GE: case GT: case LE: case LT: 8149 case GEU: case GTU: case LEU: case LTU: 8150 if (STORE_FLAG_VALUE == -1) 8151 return bitwidth; 8152 break; 8153 8154 default: 8155 break; 8156 } 8157 8158 /* If we haven't been able to figure it out by one of the above rules, 8159 see if some of the high-order bits are known to be zero. If so, 8160 count those bits and return one less than that amount. If we can't 8161 safely compute the mask for this mode, always return BITWIDTH. */ 8162 8163 if (bitwidth > HOST_BITS_PER_WIDE_INT) 8164 return 1; 8165 8166 nonzero = nonzero_bits (x, mode); 8167 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) 8168 ? 1 : bitwidth - floor_log2 (nonzero) - 1); 8169} 8170 8171/* Return the number of "extended" bits there are in X, when interpreted 8172 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For 8173 unsigned quantities, this is the number of high-order zero bits. 8174 For signed quantities, this is the number of copies of the sign bit 8175 minus 1. In both case, this function returns the number of "spare" 8176 bits. For example, if two quantities for which this function returns 8177 at least 1 are added, the addition is known not to overflow. 8178 8179 This function will always return 0 unless called during combine, which 8180 implies that it must be called from a define_split. */ 8181 8182int 8183extended_count (x, mode, unsignedp) 8184 rtx x; 8185 enum machine_mode mode; 8186 int unsignedp; 8187{ 8188 if (nonzero_sign_valid == 0) 8189 return 0; 8190 8191 return (unsignedp 8192 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 8193 && (GET_MODE_BITSIZE (mode) - 1 8194 - floor_log2 (nonzero_bits (x, mode)))) 8195 : num_sign_bit_copies (x, mode) - 1); 8196} 8197 8198/* This function is called from `simplify_shift_const' to merge two 8199 outer operations. Specifically, we have already found that we need 8200 to perform operation *POP0 with constant *PCONST0 at the outermost 8201 position. We would now like to also perform OP1 with constant CONST1 8202 (with *POP0 being done last). 8203 8204 Return 1 if we can do the operation and update *POP0 and *PCONST0 with 8205 the resulting operation. *PCOMP_P is set to 1 if we would need to 8206 complement the innermost operand, otherwise it is unchanged. 8207 8208 MODE is the mode in which the operation will be done. No bits outside 8209 the width of this mode matter. It is assumed that the width of this mode 8210 is smaller than or equal to HOST_BITS_PER_WIDE_INT. 8211 8212 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS, 8213 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper 8214 result is simply *PCONST0. 8215 8216 If the resulting operation cannot be expressed as one operation, we 8217 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ 8218 8219static int 8220merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p) 8221 enum rtx_code *pop0; 8222 HOST_WIDE_INT *pconst0; 8223 enum rtx_code op1; 8224 HOST_WIDE_INT const1; 8225 enum machine_mode mode; 8226 int *pcomp_p; 8227{ 8228 enum rtx_code op0 = *pop0; 8229 HOST_WIDE_INT const0 = *pconst0; 8230 int width = GET_MODE_BITSIZE (mode); 8231 8232 const0 &= GET_MODE_MASK (mode); 8233 const1 &= GET_MODE_MASK (mode); 8234 8235 /* If OP0 is an AND, clear unimportant bits in CONST1. */ 8236 if (op0 == AND) 8237 const1 &= const0; 8238 8239 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or 8240 if OP0 is SET. */ 8241 8242 if (op1 == NIL || op0 == SET) 8243 return 1; 8244 8245 else if (op0 == NIL) 8246 op0 = op1, const0 = const1; 8247 8248 else if (op0 == op1) 8249 { 8250 switch (op0) 8251 { 8252 case AND: 8253 const0 &= const1; 8254 break; 8255 case IOR: 8256 const0 |= const1; 8257 break; 8258 case XOR: 8259 const0 ^= const1; 8260 break; 8261 case PLUS: 8262 const0 += const1; 8263 break; 8264 case NEG: 8265 op0 = NIL; 8266 break; 8267 default: 8268 break; 8269 } 8270 } 8271 8272 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ 8273 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) 8274 return 0; 8275 8276 /* If the two constants aren't the same, we can't do anything. The 8277 remaining six cases can all be done. */ 8278 else if (const0 != const1) 8279 return 0; 8280 8281 else 8282 switch (op0) 8283 { 8284 case IOR: 8285 if (op1 == AND) 8286 /* (a & b) | b == b */ 8287 op0 = SET; 8288 else /* op1 == XOR */ 8289 /* (a ^ b) | b == a | b */ 8290 {;} 8291 break; 8292 8293 case XOR: 8294 if (op1 == AND) 8295 /* (a & b) ^ b == (~a) & b */ 8296 op0 = AND, *pcomp_p = 1; 8297 else /* op1 == IOR */ 8298 /* (a | b) ^ b == a & ~b */ 8299 op0 = AND, *pconst0 = ~ const0; 8300 break; 8301 8302 case AND: 8303 if (op1 == IOR) 8304 /* (a | b) & b == b */ 8305 op0 = SET; 8306 else /* op1 == XOR */ 8307 /* (a ^ b) & b) == (~a) & b */ 8308 *pcomp_p = 1; 8309 break; 8310 default: 8311 break; 8312 } 8313 8314 /* Check for NO-OP cases. */ 8315 const0 &= GET_MODE_MASK (mode); 8316 if (const0 == 0 8317 && (op0 == IOR || op0 == XOR || op0 == PLUS)) 8318 op0 = NIL; 8319 else if (const0 == 0 && op0 == AND) 8320 op0 = SET; 8321 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) 8322 && op0 == AND) 8323 op0 = NIL; 8324 8325 /* If this would be an entire word for the target, but is not for 8326 the host, then sign-extend on the host so that the number will look 8327 the same way on the host that it would on the target. 8328 8329 For example, when building a 64 bit alpha hosted 32 bit sparc 8330 targeted compiler, then we want the 32 bit unsigned value -1 to be 8331 represented as a 64 bit value -1, and not as 0x00000000ffffffff. 8332 The later confuses the sparc backend. */ 8333 8334 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width 8335 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1)))) 8336 const0 |= ((HOST_WIDE_INT) (-1) << width); 8337 8338 *pop0 = op0; 8339 *pconst0 = const0; 8340 8341 return 1; 8342} 8343 8344/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. 8345 The result of the shift is RESULT_MODE. X, if non-zero, is an expression 8346 that we started with. 8347 8348 The shift is normally computed in the widest mode we find in VAROP, as 8349 long as it isn't a different number of words than RESULT_MODE. Exceptions 8350 are ASHIFTRT and ROTATE, which are always done in their original mode, */ 8351 8352static rtx 8353simplify_shift_const (x, code, result_mode, varop, count) 8354 rtx x; 8355 enum rtx_code code; 8356 enum machine_mode result_mode; 8357 rtx varop; 8358 int count; 8359{ 8360 enum rtx_code orig_code = code; 8361 int orig_count = count; 8362 enum machine_mode mode = result_mode; 8363 enum machine_mode shift_mode, tmode; 8364 int mode_words 8365 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; 8366 /* We form (outer_op (code varop count) (outer_const)). */ 8367 enum rtx_code outer_op = NIL; 8368 HOST_WIDE_INT outer_const = 0; 8369 rtx const_rtx; 8370 int complement_p = 0; 8371 rtx new; 8372 8373 /* If we were given an invalid count, don't do anything except exactly 8374 what was requested. */ 8375 8376 if (count < 0 || count > GET_MODE_BITSIZE (mode)) 8377 { 8378 if (x) 8379 return x; 8380 8381 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count)); 8382 } 8383 8384 /* Unless one of the branches of the `if' in this loop does a `continue', 8385 we will `break' the loop after the `if'. */ 8386 8387 while (count != 0) 8388 { 8389 /* If we have an operand of (clobber (const_int 0)), just return that 8390 value. */ 8391 if (GET_CODE (varop) == CLOBBER) 8392 return varop; 8393 8394 /* If we discovered we had to complement VAROP, leave. Making a NOT 8395 here would cause an infinite loop. */ 8396 if (complement_p) 8397 break; 8398 8399 /* Convert ROTATERT to ROTATE. */ 8400 if (code == ROTATERT) 8401 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count; 8402 8403 /* We need to determine what mode we will do the shift in. If the 8404 shift is a right shift or a ROTATE, we must always do it in the mode 8405 it was originally done in. Otherwise, we can do it in MODE, the 8406 widest mode encountered. */ 8407 shift_mode 8408 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE 8409 ? result_mode : mode); 8410 8411 /* Handle cases where the count is greater than the size of the mode 8412 minus 1. For ASHIFT, use the size minus one as the count (this can 8413 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, 8414 take the count modulo the size. For other shifts, the result is 8415 zero. 8416 8417 Since these shifts are being produced by the compiler by combining 8418 multiple operations, each of which are defined, we know what the 8419 result is supposed to be. */ 8420 8421 if (count > GET_MODE_BITSIZE (shift_mode) - 1) 8422 { 8423 if (code == ASHIFTRT) 8424 count = GET_MODE_BITSIZE (shift_mode) - 1; 8425 else if (code == ROTATE || code == ROTATERT) 8426 count %= GET_MODE_BITSIZE (shift_mode); 8427 else 8428 { 8429 /* We can't simply return zero because there may be an 8430 outer op. */ 8431 varop = const0_rtx; 8432 count = 0; 8433 break; 8434 } 8435 } 8436 8437 /* Negative counts are invalid and should not have been made (a 8438 programmer-specified negative count should have been handled 8439 above). */ 8440 else if (count < 0) 8441 abort (); 8442 8443 /* An arithmetic right shift of a quantity known to be -1 or 0 8444 is a no-op. */ 8445 if (code == ASHIFTRT 8446 && (num_sign_bit_copies (varop, shift_mode) 8447 == GET_MODE_BITSIZE (shift_mode))) 8448 { 8449 count = 0; 8450 break; 8451 } 8452 8453 /* If we are doing an arithmetic right shift and discarding all but 8454 the sign bit copies, this is equivalent to doing a shift by the 8455 bitsize minus one. Convert it into that shift because it will often 8456 allow other simplifications. */ 8457 8458 if (code == ASHIFTRT 8459 && (count + num_sign_bit_copies (varop, shift_mode) 8460 >= GET_MODE_BITSIZE (shift_mode))) 8461 count = GET_MODE_BITSIZE (shift_mode) - 1; 8462 8463 /* We simplify the tests below and elsewhere by converting 8464 ASHIFTRT to LSHIFTRT if we know the sign bit is clear. 8465 `make_compound_operation' will convert it to a ASHIFTRT for 8466 those machines (such as Vax) that don't have a LSHIFTRT. */ 8467 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT 8468 && code == ASHIFTRT 8469 && ((nonzero_bits (varop, shift_mode) 8470 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1))) 8471 == 0)) 8472 code = LSHIFTRT; 8473 8474 switch (GET_CODE (varop)) 8475 { 8476 case SIGN_EXTEND: 8477 case ZERO_EXTEND: 8478 case SIGN_EXTRACT: 8479 case ZERO_EXTRACT: 8480 new = expand_compound_operation (varop); 8481 if (new != varop) 8482 { 8483 varop = new; 8484 continue; 8485 } 8486 break; 8487 8488 case MEM: 8489 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH 8490 minus the width of a smaller mode, we can do this with a 8491 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ 8492 if ((code == ASHIFTRT || code == LSHIFTRT) 8493 && ! mode_dependent_address_p (XEXP (varop, 0)) 8494 && ! MEM_VOLATILE_P (varop) 8495 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 8496 MODE_INT, 1)) != BLKmode) 8497 { 8498 if (BYTES_BIG_ENDIAN) 8499 new = gen_rtx_MEM (tmode, XEXP (varop, 0)); 8500 else 8501 new = gen_rtx_MEM (tmode, 8502 plus_constant (XEXP (varop, 0), 8503 count / BITS_PER_UNIT)); 8504 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop); 8505 MEM_COPY_ATTRIBUTES (new, varop); 8506 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND 8507 : ZERO_EXTEND, mode, new); 8508 count = 0; 8509 continue; 8510 } 8511 break; 8512 8513 case USE: 8514 /* Similar to the case above, except that we can only do this if 8515 the resulting mode is the same as that of the underlying 8516 MEM and adjust the address depending on the *bits* endianness 8517 because of the way that bit-field extract insns are defined. */ 8518 if ((code == ASHIFTRT || code == LSHIFTRT) 8519 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 8520 MODE_INT, 1)) != BLKmode 8521 && tmode == GET_MODE (XEXP (varop, 0))) 8522 { 8523 if (BITS_BIG_ENDIAN) 8524 new = XEXP (varop, 0); 8525 else 8526 { 8527 new = copy_rtx (XEXP (varop, 0)); 8528 SUBST (XEXP (new, 0), 8529 plus_constant (XEXP (new, 0), 8530 count / BITS_PER_UNIT)); 8531 } 8532 8533 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND 8534 : ZERO_EXTEND, mode, new); 8535 count = 0; 8536 continue; 8537 } 8538 break; 8539 8540 case SUBREG: 8541 /* If VAROP is a SUBREG, strip it as long as the inner operand has 8542 the same number of words as what we've seen so far. Then store 8543 the widest mode in MODE. */ 8544 if (subreg_lowpart_p (varop) 8545 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 8546 > GET_MODE_SIZE (GET_MODE (varop))) 8547 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 8548 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 8549 == mode_words)) 8550 { 8551 varop = SUBREG_REG (varop); 8552 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) 8553 mode = GET_MODE (varop); 8554 continue; 8555 } 8556 break; 8557 8558 case MULT: 8559 /* Some machines use MULT instead of ASHIFT because MULT 8560 is cheaper. But it is still better on those machines to 8561 merge two shifts into one. */ 8562 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8563 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) 8564 { 8565 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0), 8566 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));; 8567 continue; 8568 } 8569 break; 8570 8571 case UDIV: 8572 /* Similar, for when divides are cheaper. */ 8573 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8574 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) 8575 { 8576 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0), 8577 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1))))); 8578 continue; 8579 } 8580 break; 8581 8582 case ASHIFTRT: 8583 /* If we are extracting just the sign bit of an arithmetic right 8584 shift, that shift is not needed. */ 8585 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1) 8586 { 8587 varop = XEXP (varop, 0); 8588 continue; 8589 } 8590 8591 /* ... fall through ... */ 8592 8593 case LSHIFTRT: 8594 case ASHIFT: 8595 case ROTATE: 8596 /* Here we have two nested shifts. The result is usually the 8597 AND of a new shift with a mask. We compute the result below. */ 8598 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8599 && INTVAL (XEXP (varop, 1)) >= 0 8600 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop)) 8601 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 8602 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 8603 { 8604 enum rtx_code first_code = GET_CODE (varop); 8605 int first_count = INTVAL (XEXP (varop, 1)); 8606 unsigned HOST_WIDE_INT mask; 8607 rtx mask_rtx; 8608 8609 /* We have one common special case. We can't do any merging if 8610 the inner code is an ASHIFTRT of a smaller mode. However, if 8611 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) 8612 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), 8613 we can convert it to 8614 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1). 8615 This simplifies certain SIGN_EXTEND operations. */ 8616 if (code == ASHIFT && first_code == ASHIFTRT 8617 && (GET_MODE_BITSIZE (result_mode) 8618 - GET_MODE_BITSIZE (GET_MODE (varop))) == count) 8619 { 8620 /* C3 has the low-order C1 bits zero. */ 8621 8622 mask = (GET_MODE_MASK (mode) 8623 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1)); 8624 8625 varop = simplify_and_const_int (NULL_RTX, result_mode, 8626 XEXP (varop, 0), mask); 8627 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, 8628 varop, count); 8629 count = first_count; 8630 code = ASHIFTRT; 8631 continue; 8632 } 8633 8634 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more 8635 than C1 high-order bits equal to the sign bit, we can convert 8636 this to either an ASHIFT or a ASHIFTRT depending on the 8637 two counts. 8638 8639 We cannot do this if VAROP's mode is not SHIFT_MODE. */ 8640 8641 if (code == ASHIFTRT && first_code == ASHIFT 8642 && GET_MODE (varop) == shift_mode 8643 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) 8644 > first_count)) 8645 { 8646 count -= first_count; 8647 if (count < 0) 8648 count = - count, code = ASHIFT; 8649 varop = XEXP (varop, 0); 8650 continue; 8651 } 8652 8653 /* There are some cases we can't do. If CODE is ASHIFTRT, 8654 we can only do this if FIRST_CODE is also ASHIFTRT. 8655 8656 We can't do the case when CODE is ROTATE and FIRST_CODE is 8657 ASHIFTRT. 8658 8659 If the mode of this shift is not the mode of the outer shift, 8660 we can't do this if either shift is a right shift or ROTATE. 8661 8662 Finally, we can't do any of these if the mode is too wide 8663 unless the codes are the same. 8664 8665 Handle the case where the shift codes are the same 8666 first. */ 8667 8668 if (code == first_code) 8669 { 8670 if (GET_MODE (varop) != result_mode 8671 && (code == ASHIFTRT || code == LSHIFTRT 8672 || code == ROTATE)) 8673 break; 8674 8675 count += first_count; 8676 varop = XEXP (varop, 0); 8677 continue; 8678 } 8679 8680 if (code == ASHIFTRT 8681 || (code == ROTATE && first_code == ASHIFTRT) 8682 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 8683 || (GET_MODE (varop) != result_mode 8684 && (first_code == ASHIFTRT || first_code == LSHIFTRT 8685 || first_code == ROTATE 8686 || code == ROTATE))) 8687 break; 8688 8689 /* To compute the mask to apply after the shift, shift the 8690 nonzero bits of the inner shift the same way the 8691 outer shift will. */ 8692 8693 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop))); 8694 8695 mask_rtx 8696 = simplify_binary_operation (code, result_mode, mask_rtx, 8697 GEN_INT (count)); 8698 8699 /* Give up if we can't compute an outer operation to use. */ 8700 if (mask_rtx == 0 8701 || GET_CODE (mask_rtx) != CONST_INT 8702 || ! merge_outer_ops (&outer_op, &outer_const, AND, 8703 INTVAL (mask_rtx), 8704 result_mode, &complement_p)) 8705 break; 8706 8707 /* If the shifts are in the same direction, we add the 8708 counts. Otherwise, we subtract them. */ 8709 if ((code == ASHIFTRT || code == LSHIFTRT) 8710 == (first_code == ASHIFTRT || first_code == LSHIFTRT)) 8711 count += first_count; 8712 else 8713 count -= first_count; 8714 8715 /* If COUNT is positive, the new shift is usually CODE, 8716 except for the two exceptions below, in which case it is 8717 FIRST_CODE. If the count is negative, FIRST_CODE should 8718 always be used */ 8719 if (count > 0 8720 && ((first_code == ROTATE && code == ASHIFT) 8721 || (first_code == ASHIFTRT && code == LSHIFTRT))) 8722 code = first_code; 8723 else if (count < 0) 8724 code = first_code, count = - count; 8725 8726 varop = XEXP (varop, 0); 8727 continue; 8728 } 8729 8730 /* If we have (A << B << C) for any shift, we can convert this to 8731 (A << C << B). This wins if A is a constant. Only try this if 8732 B is not a constant. */ 8733 8734 else if (GET_CODE (varop) == code 8735 && GET_CODE (XEXP (varop, 1)) != CONST_INT 8736 && 0 != (new 8737 = simplify_binary_operation (code, mode, 8738 XEXP (varop, 0), 8739 GEN_INT (count)))) 8740 { 8741 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1)); 8742 count = 0; 8743 continue; 8744 } 8745 break; 8746 8747 case NOT: 8748 /* Make this fit the case below. */ 8749 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0), 8750 GEN_INT (GET_MODE_MASK (mode))); 8751 continue; 8752 8753 case IOR: 8754 case AND: 8755 case XOR: 8756 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) 8757 with C the size of VAROP - 1 and the shift is logical if 8758 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 8759 we have an (le X 0) operation. If we have an arithmetic shift 8760 and STORE_FLAG_VALUE is 1 or we have a logical shift with 8761 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ 8762 8763 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS 8764 && XEXP (XEXP (varop, 0), 1) == constm1_rtx 8765 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 8766 && (code == LSHIFTRT || code == ASHIFTRT) 8767 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 8768 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 8769 { 8770 count = 0; 8771 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1), 8772 const0_rtx); 8773 8774 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 8775 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop); 8776 8777 continue; 8778 } 8779 8780 /* If we have (shift (logical)), move the logical to the outside 8781 to allow it to possibly combine with another logical and the 8782 shift to combine with another shift. This also canonicalizes to 8783 what a ZERO_EXTRACT looks like. Also, some machines have 8784 (and (shift)) insns. */ 8785 8786 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8787 && (new = simplify_binary_operation (code, result_mode, 8788 XEXP (varop, 1), 8789 GEN_INT (count))) != 0 8790 && GET_CODE(new) == CONST_INT 8791 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), 8792 INTVAL (new), result_mode, &complement_p)) 8793 { 8794 varop = XEXP (varop, 0); 8795 continue; 8796 } 8797 8798 /* If we can't do that, try to simplify the shift in each arm of the 8799 logical expression, make a new logical expression, and apply 8800 the inverse distributive law. */ 8801 { 8802 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, 8803 XEXP (varop, 0), count); 8804 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, 8805 XEXP (varop, 1), count); 8806 8807 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs); 8808 varop = apply_distributive_law (varop); 8809 8810 count = 0; 8811 } 8812 break; 8813 8814 case EQ: 8815 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE 8816 says that the sign bit can be tested, FOO has mode MODE, C is 8817 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit 8818 that may be nonzero. */ 8819 if (code == LSHIFTRT 8820 && XEXP (varop, 1) == const0_rtx 8821 && GET_MODE (XEXP (varop, 0)) == result_mode 8822 && count == GET_MODE_BITSIZE (result_mode) - 1 8823 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 8824 && ((STORE_FLAG_VALUE 8825 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1)))) 8826 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 8827 && merge_outer_ops (&outer_op, &outer_const, XOR, 8828 (HOST_WIDE_INT) 1, result_mode, 8829 &complement_p)) 8830 { 8831 varop = XEXP (varop, 0); 8832 count = 0; 8833 continue; 8834 } 8835 break; 8836 8837 case NEG: 8838 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less 8839 than the number of bits in the mode is equivalent to A. */ 8840 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 8841 && nonzero_bits (XEXP (varop, 0), result_mode) == 1) 8842 { 8843 varop = XEXP (varop, 0); 8844 count = 0; 8845 continue; 8846 } 8847 8848 /* NEG commutes with ASHIFT since it is multiplication. Move the 8849 NEG outside to allow shifts to combine. */ 8850 if (code == ASHIFT 8851 && merge_outer_ops (&outer_op, &outer_const, NEG, 8852 (HOST_WIDE_INT) 0, result_mode, 8853 &complement_p)) 8854 { 8855 varop = XEXP (varop, 0); 8856 continue; 8857 } 8858 break; 8859 8860 case PLUS: 8861 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C 8862 is one less than the number of bits in the mode is 8863 equivalent to (xor A 1). */ 8864 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 8865 && XEXP (varop, 1) == constm1_rtx 8866 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 8867 && merge_outer_ops (&outer_op, &outer_const, XOR, 8868 (HOST_WIDE_INT) 1, result_mode, 8869 &complement_p)) 8870 { 8871 count = 0; 8872 varop = XEXP (varop, 0); 8873 continue; 8874 } 8875 8876 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits 8877 that might be nonzero in BAR are those being shifted out and those 8878 bits are known zero in FOO, we can replace the PLUS with FOO. 8879 Similarly in the other operand order. This code occurs when 8880 we are computing the size of a variable-size array. */ 8881 8882 if ((code == ASHIFTRT || code == LSHIFTRT) 8883 && count < HOST_BITS_PER_WIDE_INT 8884 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 8885 && (nonzero_bits (XEXP (varop, 1), result_mode) 8886 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) 8887 { 8888 varop = XEXP (varop, 0); 8889 continue; 8890 } 8891 else if ((code == ASHIFTRT || code == LSHIFTRT) 8892 && count < HOST_BITS_PER_WIDE_INT 8893 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 8894 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 8895 >> count) 8896 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 8897 & nonzero_bits (XEXP (varop, 1), 8898 result_mode))) 8899 { 8900 varop = XEXP (varop, 1); 8901 continue; 8902 } 8903 8904 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ 8905 if (code == ASHIFT 8906 && GET_CODE (XEXP (varop, 1)) == CONST_INT 8907 && (new = simplify_binary_operation (ASHIFT, result_mode, 8908 XEXP (varop, 1), 8909 GEN_INT (count))) != 0 8910 && GET_CODE(new) == CONST_INT 8911 && merge_outer_ops (&outer_op, &outer_const, PLUS, 8912 INTVAL (new), result_mode, &complement_p)) 8913 { 8914 varop = XEXP (varop, 0); 8915 continue; 8916 } 8917 break; 8918 8919 case MINUS: 8920 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) 8921 with C the size of VAROP - 1 and the shift is logical if 8922 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 8923 we have a (gt X 0) operation. If the shift is arithmetic with 8924 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, 8925 we have a (neg (gt X 0)) operation. */ 8926 8927 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 8928 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT 8929 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 8930 && (code == LSHIFTRT || code == ASHIFTRT) 8931 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT 8932 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count 8933 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 8934 { 8935 count = 0; 8936 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1), 8937 const0_rtx); 8938 8939 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 8940 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop); 8941 8942 continue; 8943 } 8944 break; 8945 8946 case TRUNCATE: 8947 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) 8948 if the truncate does not affect the value. */ 8949 if (code == LSHIFTRT 8950 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT 8951 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT 8952 && (INTVAL (XEXP (XEXP (varop, 0), 1)) 8953 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0))) 8954 - GET_MODE_BITSIZE (GET_MODE (varop))))) 8955 { 8956 rtx varop_inner = XEXP (varop, 0); 8957 8958 varop_inner = gen_rtx_combine (LSHIFTRT, 8959 GET_MODE (varop_inner), 8960 XEXP (varop_inner, 0), 8961 GEN_INT (count + INTVAL (XEXP (varop_inner, 1)))); 8962 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop), 8963 varop_inner); 8964 count = 0; 8965 continue; 8966 } 8967 break; 8968 8969 default: 8970 break; 8971 } 8972 8973 break; 8974 } 8975 8976 /* We need to determine what mode to do the shift in. If the shift is 8977 a right shift or ROTATE, we must always do it in the mode it was 8978 originally done in. Otherwise, we can do it in MODE, the widest mode 8979 encountered. The code we care about is that of the shift that will 8980 actually be done, not the shift that was originally requested. */ 8981 shift_mode 8982 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE 8983 ? result_mode : mode); 8984 8985 /* We have now finished analyzing the shift. The result should be 8986 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If 8987 OUTER_OP is non-NIL, it is an operation that needs to be applied 8988 to the result of the shift. OUTER_CONST is the relevant constant, 8989 but we must turn off all bits turned off in the shift. 8990 8991 If we were passed a value for X, see if we can use any pieces of 8992 it. If not, make new rtx. */ 8993 8994 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2' 8995 && GET_CODE (XEXP (x, 1)) == CONST_INT 8996 && INTVAL (XEXP (x, 1)) == count) 8997 const_rtx = XEXP (x, 1); 8998 else 8999 const_rtx = GEN_INT (count); 9000 9001 if (x && GET_CODE (XEXP (x, 0)) == SUBREG 9002 && GET_MODE (XEXP (x, 0)) == shift_mode 9003 && SUBREG_REG (XEXP (x, 0)) == varop) 9004 varop = XEXP (x, 0); 9005 else if (GET_MODE (varop) != shift_mode) 9006 varop = gen_lowpart_for_combine (shift_mode, varop); 9007 9008 /* If we can't make the SUBREG, try to return what we were given. */ 9009 if (GET_CODE (varop) == CLOBBER) 9010 return x ? x : varop; 9011 9012 new = simplify_binary_operation (code, shift_mode, varop, const_rtx); 9013 if (new != 0) 9014 x = new; 9015 else 9016 { 9017 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode) 9018 x = gen_rtx_combine (code, shift_mode, varop, const_rtx); 9019 9020 SUBST (XEXP (x, 0), varop); 9021 SUBST (XEXP (x, 1), const_rtx); 9022 } 9023 9024 /* If we have an outer operation and we just made a shift, it is 9025 possible that we could have simplified the shift were it not 9026 for the outer operation. So try to do the simplification 9027 recursively. */ 9028 9029 if (outer_op != NIL && GET_CODE (x) == code 9030 && GET_CODE (XEXP (x, 1)) == CONST_INT) 9031 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0), 9032 INTVAL (XEXP (x, 1))); 9033 9034 /* If we were doing a LSHIFTRT in a wider mode than it was originally, 9035 turn off all the bits that the shift would have turned off. */ 9036 if (orig_code == LSHIFTRT && result_mode != shift_mode) 9037 x = simplify_and_const_int (NULL_RTX, shift_mode, x, 9038 GET_MODE_MASK (result_mode) >> orig_count); 9039 9040 /* Do the remainder of the processing in RESULT_MODE. */ 9041 x = gen_lowpart_for_combine (result_mode, x); 9042 9043 /* If COMPLEMENT_P is set, we have to complement X before doing the outer 9044 operation. */ 9045 if (complement_p) 9046 x = gen_unary (NOT, result_mode, result_mode, x); 9047 9048 if (outer_op != NIL) 9049 { 9050 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT) 9051 { 9052 int width = GET_MODE_BITSIZE (result_mode); 9053 9054 outer_const &= GET_MODE_MASK (result_mode); 9055 9056 /* If this would be an entire word for the target, but is not for 9057 the host, then sign-extend on the host so that the number will 9058 look the same way on the host that it would on the target. 9059 9060 For example, when building a 64 bit alpha hosted 32 bit sparc 9061 targeted compiler, then we want the 32 bit unsigned value -1 to be 9062 represented as a 64 bit value -1, and not as 0x00000000ffffffff. 9063 The later confuses the sparc backend. */ 9064 9065 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width 9066 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1)))) 9067 outer_const |= ((HOST_WIDE_INT) (-1) << width); 9068 } 9069 9070 if (outer_op == AND) 9071 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); 9072 else if (outer_op == SET) 9073 /* This means that we have determined that the result is 9074 equivalent to a constant. This should be rare. */ 9075 x = GEN_INT (outer_const); 9076 else if (GET_RTX_CLASS (outer_op) == '1') 9077 x = gen_unary (outer_op, result_mode, result_mode, x); 9078 else 9079 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const)); 9080 } 9081 9082 return x; 9083} 9084 9085/* Like recog, but we receive the address of a pointer to a new pattern. 9086 We try to match the rtx that the pointer points to. 9087 If that fails, we may try to modify or replace the pattern, 9088 storing the replacement into the same pointer object. 9089 9090 Modifications include deletion or addition of CLOBBERs. 9091 9092 PNOTES is a pointer to a location where any REG_UNUSED notes added for 9093 the CLOBBERs are placed. 9094 9095 The value is the final insn code from the pattern ultimately matched, 9096 or -1. */ 9097 9098static int 9099recog_for_combine (pnewpat, insn, pnotes) 9100 rtx *pnewpat; 9101 rtx insn; 9102 rtx *pnotes; 9103{ 9104 register rtx pat = *pnewpat; 9105 int insn_code_number; 9106 int num_clobbers_to_add = 0; 9107 int i; 9108 rtx notes = 0; 9109 9110 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER 9111 we use to indicate that something didn't match. If we find such a 9112 thing, force rejection. */ 9113 if (GET_CODE (pat) == PARALLEL) 9114 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) 9115 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER 9116 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) 9117 return -1; 9118 9119 /* Is the result of combination a valid instruction? */ 9120 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 9121 9122 /* If it isn't, there is the possibility that we previously had an insn 9123 that clobbered some register as a side effect, but the combined 9124 insn doesn't need to do that. So try once more without the clobbers 9125 unless this represents an ASM insn. */ 9126 9127 if (insn_code_number < 0 && ! check_asm_operands (pat) 9128 && GET_CODE (pat) == PARALLEL) 9129 { 9130 int pos; 9131 9132 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) 9133 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) 9134 { 9135 if (i != pos) 9136 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); 9137 pos++; 9138 } 9139 9140 SUBST_INT (XVECLEN (pat, 0), pos); 9141 9142 if (pos == 1) 9143 pat = XVECEXP (pat, 0, 0); 9144 9145 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 9146 } 9147 9148 /* If we had any clobbers to add, make a new pattern than contains 9149 them. Then check to make sure that all of them are dead. */ 9150 if (num_clobbers_to_add) 9151 { 9152 rtx newpat = gen_rtx_PARALLEL (VOIDmode, 9153 gen_rtvec (GET_CODE (pat) == PARALLEL 9154 ? XVECLEN (pat, 0) + num_clobbers_to_add 9155 : num_clobbers_to_add + 1)); 9156 9157 if (GET_CODE (pat) == PARALLEL) 9158 for (i = 0; i < XVECLEN (pat, 0); i++) 9159 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); 9160 else 9161 XVECEXP (newpat, 0, 0) = pat; 9162 9163 add_clobbers (newpat, insn_code_number); 9164 9165 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; 9166 i < XVECLEN (newpat, 0); i++) 9167 { 9168 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG 9169 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) 9170 return -1; 9171 notes = gen_rtx_EXPR_LIST (REG_UNUSED, 9172 XEXP (XVECEXP (newpat, 0, i), 0), notes); 9173 } 9174 pat = newpat; 9175 } 9176 9177 *pnewpat = pat; 9178 *pnotes = notes; 9179 9180 return insn_code_number; 9181} 9182 9183/* Like gen_lowpart but for use by combine. In combine it is not possible 9184 to create any new pseudoregs. However, it is safe to create 9185 invalid memory addresses, because combine will try to recognize 9186 them and all they will do is make the combine attempt fail. 9187 9188 If for some reason this cannot do its job, an rtx 9189 (clobber (const_int 0)) is returned. 9190 An insn containing that will not be recognized. */ 9191 9192#undef gen_lowpart 9193 9194static rtx 9195gen_lowpart_for_combine (mode, x) 9196 enum machine_mode mode; 9197 register rtx x; 9198{ 9199 rtx result; 9200 9201 if (GET_MODE (x) == mode) 9202 return x; 9203 9204 /* We can only support MODE being wider than a word if X is a 9205 constant integer or has a mode the same size. */ 9206 9207 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 9208 && ! ((GET_MODE (x) == VOIDmode 9209 && (GET_CODE (x) == CONST_INT 9210 || GET_CODE (x) == CONST_DOUBLE)) 9211 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode))) 9212 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 9213 9214 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart 9215 won't know what to do. So we will strip off the SUBREG here and 9216 process normally. */ 9217 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM) 9218 { 9219 x = SUBREG_REG (x); 9220 if (GET_MODE (x) == mode) 9221 return x; 9222 } 9223 9224 result = gen_lowpart_common (mode, x); 9225 if (result != 0 9226 && GET_CODE (result) == SUBREG 9227 && GET_CODE (SUBREG_REG (result)) == REG 9228 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER 9229 && (GET_MODE_SIZE (GET_MODE (result)) 9230 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result))))) 9231 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1; 9232 9233 if (result) 9234 return result; 9235 9236 if (GET_CODE (x) == MEM) 9237 { 9238 register int offset = 0; 9239 rtx new; 9240 9241 /* Refuse to work on a volatile memory ref or one with a mode-dependent 9242 address. */ 9243 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0))) 9244 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 9245 9246 /* If we want to refer to something bigger than the original memref, 9247 generate a perverse subreg instead. That will force a reload 9248 of the original memref X. */ 9249 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)) 9250 return gen_rtx_SUBREG (mode, x, 0); 9251 9252 if (WORDS_BIG_ENDIAN) 9253 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) 9254 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); 9255 if (BYTES_BIG_ENDIAN) 9256 { 9257 /* Adjust the address so that the address-after-the-data is 9258 unchanged. */ 9259 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) 9260 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); 9261 } 9262 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset)); 9263 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x); 9264 MEM_COPY_ATTRIBUTES (new, x); 9265 return new; 9266 } 9267 9268 /* If X is a comparison operator, rewrite it in a new mode. This 9269 probably won't match, but may allow further simplifications. */ 9270 else if (GET_RTX_CLASS (GET_CODE (x)) == '<') 9271 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1)); 9272 9273 /* If we couldn't simplify X any other way, just enclose it in a 9274 SUBREG. Normally, this SUBREG won't match, but some patterns may 9275 include an explicit SUBREG or we may simplify it further in combine. */ 9276 else 9277 { 9278 int word = 0; 9279 9280 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) 9281 word = ((GET_MODE_SIZE (GET_MODE (x)) 9282 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) 9283 / UNITS_PER_WORD); 9284 return gen_rtx_SUBREG (mode, x, word); 9285 } 9286} 9287 9288/* Make an rtx expression. This is a subset of gen_rtx and only supports 9289 expressions of 1, 2, or 3 operands, each of which are rtx expressions. 9290 9291 If the identical expression was previously in the insn (in the undobuf), 9292 it will be returned. Only if it is not found will a new expression 9293 be made. */ 9294 9295/*VARARGS2*/ 9296static rtx 9297gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...)) 9298{ 9299#ifndef ANSI_PROTOTYPES 9300 enum rtx_code code; 9301 enum machine_mode mode; 9302#endif 9303 va_list p; 9304 int n_args; 9305 rtx args[3]; 9306 int j; 9307 char *fmt; 9308 rtx rt; 9309 struct undo *undo; 9310 9311 VA_START (p, mode); 9312 9313#ifndef ANSI_PROTOTYPES 9314 code = va_arg (p, enum rtx_code); 9315 mode = va_arg (p, enum machine_mode); 9316#endif 9317 9318 n_args = GET_RTX_LENGTH (code); 9319 fmt = GET_RTX_FORMAT (code); 9320 9321 if (n_args == 0 || n_args > 3) 9322 abort (); 9323 9324 /* Get each arg and verify that it is supposed to be an expression. */ 9325 for (j = 0; j < n_args; j++) 9326 { 9327 if (*fmt++ != 'e') 9328 abort (); 9329 9330 args[j] = va_arg (p, rtx); 9331 } 9332 9333 /* See if this is in undobuf. Be sure we don't use objects that came 9334 from another insn; this could produce circular rtl structures. */ 9335 9336 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next) 9337 if (!undo->is_int 9338 && GET_CODE (undo->old_contents.r) == code 9339 && GET_MODE (undo->old_contents.r) == mode) 9340 { 9341 for (j = 0; j < n_args; j++) 9342 if (XEXP (undo->old_contents.r, j) != args[j]) 9343 break; 9344 9345 if (j == n_args) 9346 return undo->old_contents.r; 9347 } 9348 9349 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args. 9350 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */ 9351 rt = rtx_alloc (code); 9352 PUT_MODE (rt, mode); 9353 XEXP (rt, 0) = args[0]; 9354 if (n_args > 1) 9355 { 9356 XEXP (rt, 1) = args[1]; 9357 if (n_args > 2) 9358 XEXP (rt, 2) = args[2]; 9359 } 9360 return rt; 9361} 9362 9363/* These routines make binary and unary operations by first seeing if they 9364 fold; if not, a new expression is allocated. */ 9365 9366static rtx 9367gen_binary (code, mode, op0, op1) 9368 enum rtx_code code; 9369 enum machine_mode mode; 9370 rtx op0, op1; 9371{ 9372 rtx result; 9373 rtx tem; 9374 9375 if (GET_RTX_CLASS (code) == 'c' 9376 && (GET_CODE (op0) == CONST_INT 9377 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT))) 9378 tem = op0, op0 = op1, op1 = tem; 9379 9380 if (GET_RTX_CLASS (code) == '<') 9381 { 9382 enum machine_mode op_mode = GET_MODE (op0); 9383 9384 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get 9385 just (REL_OP X Y). */ 9386 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx) 9387 { 9388 op1 = XEXP (op0, 1); 9389 op0 = XEXP (op0, 0); 9390 op_mode = GET_MODE (op0); 9391 } 9392 9393 if (op_mode == VOIDmode) 9394 op_mode = GET_MODE (op1); 9395 result = simplify_relational_operation (code, op_mode, op0, op1); 9396 } 9397 else 9398 result = simplify_binary_operation (code, mode, op0, op1); 9399 9400 if (result) 9401 return result; 9402 9403 /* Put complex operands first and constants second. */ 9404 if (GET_RTX_CLASS (code) == 'c' 9405 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT) 9406 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o' 9407 && GET_RTX_CLASS (GET_CODE (op1)) != 'o') 9408 || (GET_CODE (op0) == SUBREG 9409 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o' 9410 && GET_RTX_CLASS (GET_CODE (op1)) != 'o'))) 9411 return gen_rtx_combine (code, mode, op1, op0); 9412 9413 /* If we are turning off bits already known off in OP0, we need not do 9414 an AND. */ 9415 else if (code == AND && GET_CODE (op1) == CONST_INT 9416 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 9417 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0) 9418 return op0; 9419 9420 return gen_rtx_combine (code, mode, op0, op1); 9421} 9422 9423static rtx 9424gen_unary (code, mode, op0_mode, op0) 9425 enum rtx_code code; 9426 enum machine_mode mode, op0_mode; 9427 rtx op0; 9428{ 9429 rtx result = simplify_unary_operation (code, mode, op0, op0_mode); 9430 9431 if (result) 9432 return result; 9433 9434 return gen_rtx_combine (code, mode, op0); 9435} 9436 9437/* Simplify a comparison between *POP0 and *POP1 where CODE is the 9438 comparison code that will be tested. 9439 9440 The result is a possibly different comparison code to use. *POP0 and 9441 *POP1 may be updated. 9442 9443 It is possible that we might detect that a comparison is either always 9444 true or always false. However, we do not perform general constant 9445 folding in combine, so this knowledge isn't useful. Such tautologies 9446 should have been detected earlier. Hence we ignore all such cases. */ 9447 9448static enum rtx_code 9449simplify_comparison (code, pop0, pop1) 9450 enum rtx_code code; 9451 rtx *pop0; 9452 rtx *pop1; 9453{ 9454 rtx op0 = *pop0; 9455 rtx op1 = *pop1; 9456 rtx tem, tem1; 9457 int i; 9458 enum machine_mode mode, tmode; 9459 9460 /* Try a few ways of applying the same transformation to both operands. */ 9461 while (1) 9462 { 9463#ifndef WORD_REGISTER_OPERATIONS 9464 /* The test below this one won't handle SIGN_EXTENDs on these machines, 9465 so check specially. */ 9466 if (code != GTU && code != GEU && code != LTU && code != LEU 9467 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT 9468 && GET_CODE (XEXP (op0, 0)) == ASHIFT 9469 && GET_CODE (XEXP (op1, 0)) == ASHIFT 9470 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG 9471 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG 9472 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) 9473 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) 9474 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9475 && GET_CODE (XEXP (op1, 1)) == CONST_INT 9476 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 9477 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT 9478 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1)) 9479 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1)) 9480 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1)) 9481 && (INTVAL (XEXP (op0, 1)) 9482 == (GET_MODE_BITSIZE (GET_MODE (op0)) 9483 - (GET_MODE_BITSIZE 9484 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) 9485 { 9486 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); 9487 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); 9488 } 9489#endif 9490 9491 /* If both operands are the same constant shift, see if we can ignore the 9492 shift. We can if the shift is a rotate or if the bits shifted out of 9493 this shift are known to be zero for both inputs and if the type of 9494 comparison is compatible with the shift. */ 9495 if (GET_CODE (op0) == GET_CODE (op1) 9496 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 9497 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) 9498 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) 9499 && (code != GT && code != LT && code != GE && code != LE)) 9500 || (GET_CODE (op0) == ASHIFTRT 9501 && (code != GTU && code != LTU 9502 && code != GEU && code != GEU))) 9503 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9504 && INTVAL (XEXP (op0, 1)) >= 0 9505 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 9506 && XEXP (op0, 1) == XEXP (op1, 1)) 9507 { 9508 enum machine_mode mode = GET_MODE (op0); 9509 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 9510 int shift_count = INTVAL (XEXP (op0, 1)); 9511 9512 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) 9513 mask &= (mask >> shift_count) << shift_count; 9514 else if (GET_CODE (op0) == ASHIFT) 9515 mask = (mask & (mask << shift_count)) >> shift_count; 9516 9517 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0 9518 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0) 9519 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); 9520 else 9521 break; 9522 } 9523 9524 /* If both operands are AND's of a paradoxical SUBREG by constant, the 9525 SUBREGs are of the same mode, and, in both cases, the AND would 9526 be redundant if the comparison was done in the narrower mode, 9527 do the comparison in the narrower mode (e.g., we are AND'ing with 1 9528 and the operand's possibly nonzero bits are 0xffffff01; in that case 9529 if we only care about QImode, we don't need the AND). This case 9530 occurs if the output mode of an scc insn is not SImode and 9531 STORE_FLAG_VALUE == 1 (e.g., the 386). 9532 9533 Similarly, check for a case where the AND's are ZERO_EXTEND 9534 operations from some narrower mode even though a SUBREG is not 9535 present. */ 9536 9537 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND 9538 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9539 && GET_CODE (XEXP (op1, 1)) == CONST_INT) 9540 { 9541 rtx inner_op0 = XEXP (op0, 0); 9542 rtx inner_op1 = XEXP (op1, 0); 9543 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); 9544 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); 9545 int changed = 0; 9546 9547 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG 9548 && (GET_MODE_SIZE (GET_MODE (inner_op0)) 9549 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0)))) 9550 && (GET_MODE (SUBREG_REG (inner_op0)) 9551 == GET_MODE (SUBREG_REG (inner_op1))) 9552 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0))) 9553 <= HOST_BITS_PER_WIDE_INT) 9554 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), 9555 GET_MODE (SUBREG_REG (inner_op0))))) 9556 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), 9557 GET_MODE (SUBREG_REG (inner_op1)))))) 9558 { 9559 op0 = SUBREG_REG (inner_op0); 9560 op1 = SUBREG_REG (inner_op1); 9561 9562 /* The resulting comparison is always unsigned since we masked 9563 off the original sign bit. */ 9564 code = unsigned_condition (code); 9565 9566 changed = 1; 9567 } 9568 9569 else if (c0 == c1) 9570 for (tmode = GET_CLASS_NARROWEST_MODE 9571 (GET_MODE_CLASS (GET_MODE (op0))); 9572 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) 9573 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) 9574 { 9575 op0 = gen_lowpart_for_combine (tmode, inner_op0); 9576 op1 = gen_lowpart_for_combine (tmode, inner_op1); 9577 code = unsigned_condition (code); 9578 changed = 1; 9579 break; 9580 } 9581 9582 if (! changed) 9583 break; 9584 } 9585 9586 /* If both operands are NOT, we can strip off the outer operation 9587 and adjust the comparison code for swapped operands; similarly for 9588 NEG, except that this must be an equality comparison. */ 9589 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) 9590 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG 9591 && (code == EQ || code == NE))) 9592 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); 9593 9594 else 9595 break; 9596 } 9597 9598 /* If the first operand is a constant, swap the operands and adjust the 9599 comparison code appropriately, but don't do this if the second operand 9600 is already a constant integer. */ 9601 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT) 9602 { 9603 tem = op0, op0 = op1, op1 = tem; 9604 code = swap_condition (code); 9605 } 9606 9607 /* We now enter a loop during which we will try to simplify the comparison. 9608 For the most part, we only are concerned with comparisons with zero, 9609 but some things may really be comparisons with zero but not start 9610 out looking that way. */ 9611 9612 while (GET_CODE (op1) == CONST_INT) 9613 { 9614 enum machine_mode mode = GET_MODE (op0); 9615 int mode_width = GET_MODE_BITSIZE (mode); 9616 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 9617 int equality_comparison_p; 9618 int sign_bit_comparison_p; 9619 int unsigned_comparison_p; 9620 HOST_WIDE_INT const_op; 9621 9622 /* We only want to handle integral modes. This catches VOIDmode, 9623 CCmode, and the floating-point modes. An exception is that we 9624 can handle VOIDmode if OP0 is a COMPARE or a comparison 9625 operation. */ 9626 9627 if (GET_MODE_CLASS (mode) != MODE_INT 9628 && ! (mode == VOIDmode 9629 && (GET_CODE (op0) == COMPARE 9630 || GET_RTX_CLASS (GET_CODE (op0)) == '<'))) 9631 break; 9632 9633 /* Get the constant we are comparing against and turn off all bits 9634 not on in our mode. */ 9635 const_op = INTVAL (op1); 9636 if (mode_width <= HOST_BITS_PER_WIDE_INT) 9637 const_op &= mask; 9638 9639 /* If we are comparing against a constant power of two and the value 9640 being compared can only have that single bit nonzero (e.g., it was 9641 `and'ed with that bit), we can replace this with a comparison 9642 with zero. */ 9643 if (const_op 9644 && (code == EQ || code == NE || code == GE || code == GEU 9645 || code == LT || code == LTU) 9646 && mode_width <= HOST_BITS_PER_WIDE_INT 9647 && exact_log2 (const_op) >= 0 9648 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op) 9649 { 9650 code = (code == EQ || code == GE || code == GEU ? NE : EQ); 9651 op1 = const0_rtx, const_op = 0; 9652 } 9653 9654 /* Similarly, if we are comparing a value known to be either -1 or 9655 0 with -1, change it to the opposite comparison against zero. */ 9656 9657 if (const_op == -1 9658 && (code == EQ || code == NE || code == GT || code == LE 9659 || code == GEU || code == LTU) 9660 && num_sign_bit_copies (op0, mode) == mode_width) 9661 { 9662 code = (code == EQ || code == LE || code == GEU ? NE : EQ); 9663 op1 = const0_rtx, const_op = 0; 9664 } 9665 9666 /* Do some canonicalizations based on the comparison code. We prefer 9667 comparisons against zero and then prefer equality comparisons. 9668 If we can reduce the size of a constant, we will do that too. */ 9669 9670 switch (code) 9671 { 9672 case LT: 9673 /* < C is equivalent to <= (C - 1) */ 9674 if (const_op > 0) 9675 { 9676 const_op -= 1; 9677 op1 = GEN_INT (const_op); 9678 code = LE; 9679 /* ... fall through to LE case below. */ 9680 } 9681 else 9682 break; 9683 9684 case LE: 9685 /* <= C is equivalent to < (C + 1); we do this for C < 0 */ 9686 if (const_op < 0) 9687 { 9688 const_op += 1; 9689 op1 = GEN_INT (const_op); 9690 code = LT; 9691 } 9692 9693 /* If we are doing a <= 0 comparison on a value known to have 9694 a zero sign bit, we can replace this with == 0. */ 9695 else if (const_op == 0 9696 && mode_width <= HOST_BITS_PER_WIDE_INT 9697 && (nonzero_bits (op0, mode) 9698 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) 9699 code = EQ; 9700 break; 9701 9702 case GE: 9703 /* >= C is equivalent to > (C - 1). */ 9704 if (const_op > 0) 9705 { 9706 const_op -= 1; 9707 op1 = GEN_INT (const_op); 9708 code = GT; 9709 /* ... fall through to GT below. */ 9710 } 9711 else 9712 break; 9713 9714 case GT: 9715 /* > C is equivalent to >= (C + 1); we do this for C < 0*/ 9716 if (const_op < 0) 9717 { 9718 const_op += 1; 9719 op1 = GEN_INT (const_op); 9720 code = GE; 9721 } 9722 9723 /* If we are doing a > 0 comparison on a value known to have 9724 a zero sign bit, we can replace this with != 0. */ 9725 else if (const_op == 0 9726 && mode_width <= HOST_BITS_PER_WIDE_INT 9727 && (nonzero_bits (op0, mode) 9728 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) 9729 code = NE; 9730 break; 9731 9732 case LTU: 9733 /* < C is equivalent to <= (C - 1). */ 9734 if (const_op > 0) 9735 { 9736 const_op -= 1; 9737 op1 = GEN_INT (const_op); 9738 code = LEU; 9739 /* ... fall through ... */ 9740 } 9741 9742 /* (unsigned) < 0x80000000 is equivalent to >= 0. */ 9743 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 9744 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) 9745 { 9746 const_op = 0, op1 = const0_rtx; 9747 code = GE; 9748 break; 9749 } 9750 else 9751 break; 9752 9753 case LEU: 9754 /* unsigned <= 0 is equivalent to == 0 */ 9755 if (const_op == 0) 9756 code = EQ; 9757 9758 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ 9759 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 9760 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) 9761 { 9762 const_op = 0, op1 = const0_rtx; 9763 code = GE; 9764 } 9765 break; 9766 9767 case GEU: 9768 /* >= C is equivalent to < (C - 1). */ 9769 if (const_op > 1) 9770 { 9771 const_op -= 1; 9772 op1 = GEN_INT (const_op); 9773 code = GTU; 9774 /* ... fall through ... */ 9775 } 9776 9777 /* (unsigned) >= 0x80000000 is equivalent to < 0. */ 9778 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 9779 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) 9780 { 9781 const_op = 0, op1 = const0_rtx; 9782 code = LT; 9783 break; 9784 } 9785 else 9786 break; 9787 9788 case GTU: 9789 /* unsigned > 0 is equivalent to != 0 */ 9790 if (const_op == 0) 9791 code = NE; 9792 9793 /* (unsigned) > 0x7fffffff is equivalent to < 0. */ 9794 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 9795 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) 9796 { 9797 const_op = 0, op1 = const0_rtx; 9798 code = LT; 9799 } 9800 break; 9801 9802 default: 9803 break; 9804 } 9805 9806 /* Compute some predicates to simplify code below. */ 9807 9808 equality_comparison_p = (code == EQ || code == NE); 9809 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); 9810 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU 9811 || code == LEU); 9812 9813 /* If this is a sign bit comparison and we can do arithmetic in 9814 MODE, say that we will only be needing the sign bit of OP0. */ 9815 if (sign_bit_comparison_p 9816 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 9817 op0 = force_to_mode (op0, mode, 9818 ((HOST_WIDE_INT) 1 9819 << (GET_MODE_BITSIZE (mode) - 1)), 9820 NULL_RTX, 0); 9821 9822 /* Now try cases based on the opcode of OP0. If none of the cases 9823 does a "continue", we exit this loop immediately after the 9824 switch. */ 9825 9826 switch (GET_CODE (op0)) 9827 { 9828 case ZERO_EXTRACT: 9829 /* If we are extracting a single bit from a variable position in 9830 a constant that has only a single bit set and are comparing it 9831 with zero, we can convert this into an equality comparison 9832 between the position and the location of the single bit. */ 9833 9834 if (GET_CODE (XEXP (op0, 0)) == CONST_INT 9835 && XEXP (op0, 1) == const1_rtx 9836 && equality_comparison_p && const_op == 0 9837 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0) 9838 { 9839 if (BITS_BIG_ENDIAN) 9840 { 9841#ifdef HAVE_extzv 9842 mode = insn_operand_mode[(int) CODE_FOR_extzv][1]; 9843 if (mode == VOIDmode) 9844 mode = word_mode; 9845 i = (GET_MODE_BITSIZE (mode) - 1 - i); 9846#else 9847 i = BITS_PER_WORD - 1 - i; 9848#endif 9849 } 9850 9851 op0 = XEXP (op0, 2); 9852 op1 = GEN_INT (i); 9853 const_op = i; 9854 9855 /* Result is nonzero iff shift count is equal to I. */ 9856 code = reverse_condition (code); 9857 continue; 9858 } 9859 9860 /* ... fall through ... */ 9861 9862 case SIGN_EXTRACT: 9863 tem = expand_compound_operation (op0); 9864 if (tem != op0) 9865 { 9866 op0 = tem; 9867 continue; 9868 } 9869 break; 9870 9871 case NOT: 9872 /* If testing for equality, we can take the NOT of the constant. */ 9873 if (equality_comparison_p 9874 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) 9875 { 9876 op0 = XEXP (op0, 0); 9877 op1 = tem; 9878 continue; 9879 } 9880 9881 /* If just looking at the sign bit, reverse the sense of the 9882 comparison. */ 9883 if (sign_bit_comparison_p) 9884 { 9885 op0 = XEXP (op0, 0); 9886 code = (code == GE ? LT : GE); 9887 continue; 9888 } 9889 break; 9890 9891 case NEG: 9892 /* If testing for equality, we can take the NEG of the constant. */ 9893 if (equality_comparison_p 9894 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) 9895 { 9896 op0 = XEXP (op0, 0); 9897 op1 = tem; 9898 continue; 9899 } 9900 9901 /* The remaining cases only apply to comparisons with zero. */ 9902 if (const_op != 0) 9903 break; 9904 9905 /* When X is ABS or is known positive, 9906 (neg X) is < 0 if and only if X != 0. */ 9907 9908 if (sign_bit_comparison_p 9909 && (GET_CODE (XEXP (op0, 0)) == ABS 9910 || (mode_width <= HOST_BITS_PER_WIDE_INT 9911 && (nonzero_bits (XEXP (op0, 0), mode) 9912 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0))) 9913 { 9914 op0 = XEXP (op0, 0); 9915 code = (code == LT ? NE : EQ); 9916 continue; 9917 } 9918 9919 /* If we have NEG of something whose two high-order bits are the 9920 same, we know that "(-a) < 0" is equivalent to "a > 0". */ 9921 if (num_sign_bit_copies (op0, mode) >= 2) 9922 { 9923 op0 = XEXP (op0, 0); 9924 code = swap_condition (code); 9925 continue; 9926 } 9927 break; 9928 9929 case ROTATE: 9930 /* If we are testing equality and our count is a constant, we 9931 can perform the inverse operation on our RHS. */ 9932 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT 9933 && (tem = simplify_binary_operation (ROTATERT, mode, 9934 op1, XEXP (op0, 1))) != 0) 9935 { 9936 op0 = XEXP (op0, 0); 9937 op1 = tem; 9938 continue; 9939 } 9940 9941 /* If we are doing a < 0 or >= 0 comparison, it means we are testing 9942 a particular bit. Convert it to an AND of a constant of that 9943 bit. This will be converted into a ZERO_EXTRACT. */ 9944 if (const_op == 0 && sign_bit_comparison_p 9945 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9946 && mode_width <= HOST_BITS_PER_WIDE_INT) 9947 { 9948 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 9949 ((HOST_WIDE_INT) 1 9950 << (mode_width - 1 9951 - INTVAL (XEXP (op0, 1))))); 9952 code = (code == LT ? NE : EQ); 9953 continue; 9954 } 9955 9956 /* ... fall through ... */ 9957 9958 case ABS: 9959 /* ABS is ignorable inside an equality comparison with zero. */ 9960 if (const_op == 0 && equality_comparison_p) 9961 { 9962 op0 = XEXP (op0, 0); 9963 continue; 9964 } 9965 break; 9966 9967 9968 case SIGN_EXTEND: 9969 /* Can simplify (compare (zero/sign_extend FOO) CONST) 9970 to (compare FOO CONST) if CONST fits in FOO's mode and we 9971 are either testing inequality or have an unsigned comparison 9972 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */ 9973 if (! unsigned_comparison_p 9974 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) 9975 <= HOST_BITS_PER_WIDE_INT) 9976 && ((unsigned HOST_WIDE_INT) const_op 9977 < (((unsigned HOST_WIDE_INT) 1 9978 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1))))) 9979 { 9980 op0 = XEXP (op0, 0); 9981 continue; 9982 } 9983 break; 9984 9985 case SUBREG: 9986 /* Check for the case where we are comparing A - C1 with C2, 9987 both constants are smaller than 1/2 the maximum positive 9988 value in MODE, and the comparison is equality or unsigned. 9989 In that case, if A is either zero-extended to MODE or has 9990 sufficient sign bits so that the high-order bit in MODE 9991 is a copy of the sign in the inner mode, we can prove that it is 9992 safe to do the operation in the wider mode. This simplifies 9993 many range checks. */ 9994 9995 if (mode_width <= HOST_BITS_PER_WIDE_INT 9996 && subreg_lowpart_p (op0) 9997 && GET_CODE (SUBREG_REG (op0)) == PLUS 9998 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT 9999 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0 10000 && (- INTVAL (XEXP (SUBREG_REG (op0), 1)) 10001 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2)) 10002 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2 10003 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0), 10004 GET_MODE (SUBREG_REG (op0))) 10005 & ~ GET_MODE_MASK (mode)) 10006 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0), 10007 GET_MODE (SUBREG_REG (op0))) 10008 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) 10009 - GET_MODE_BITSIZE (mode))))) 10010 { 10011 op0 = SUBREG_REG (op0); 10012 continue; 10013 } 10014 10015 /* If the inner mode is narrower and we are extracting the low part, 10016 we can treat the SUBREG as if it were a ZERO_EXTEND. */ 10017 if (subreg_lowpart_p (op0) 10018 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width) 10019 /* Fall through */ ; 10020 else 10021 break; 10022 10023 /* ... fall through ... */ 10024 10025 case ZERO_EXTEND: 10026 if ((unsigned_comparison_p || equality_comparison_p) 10027 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) 10028 <= HOST_BITS_PER_WIDE_INT) 10029 && ((unsigned HOST_WIDE_INT) const_op 10030 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0))))) 10031 { 10032 op0 = XEXP (op0, 0); 10033 continue; 10034 } 10035 break; 10036 10037 case PLUS: 10038 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do 10039 this for equality comparisons due to pathological cases involving 10040 overflows. */ 10041 if (equality_comparison_p 10042 && 0 != (tem = simplify_binary_operation (MINUS, mode, 10043 op1, XEXP (op0, 1)))) 10044 { 10045 op0 = XEXP (op0, 0); 10046 op1 = tem; 10047 continue; 10048 } 10049 10050 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ 10051 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx 10052 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) 10053 { 10054 op0 = XEXP (XEXP (op0, 0), 0); 10055 code = (code == LT ? EQ : NE); 10056 continue; 10057 } 10058 break; 10059 10060 case MINUS: 10061 /* (eq (minus A B) C) -> (eq A (plus B C)) or 10062 (eq B (minus A C)), whichever simplifies. We can only do 10063 this for equality comparisons due to pathological cases involving 10064 overflows. */ 10065 if (equality_comparison_p 10066 && 0 != (tem = simplify_binary_operation (PLUS, mode, 10067 XEXP (op0, 1), op1))) 10068 { 10069 op0 = XEXP (op0, 0); 10070 op1 = tem; 10071 continue; 10072 } 10073 10074 if (equality_comparison_p 10075 && 0 != (tem = simplify_binary_operation (MINUS, mode, 10076 XEXP (op0, 0), op1))) 10077 { 10078 op0 = XEXP (op0, 1); 10079 op1 = tem; 10080 continue; 10081 } 10082 10083 /* The sign bit of (minus (ashiftrt X C) X), where C is the number 10084 of bits in X minus 1, is one iff X > 0. */ 10085 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT 10086 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10087 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1 10088 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 10089 { 10090 op0 = XEXP (op0, 1); 10091 code = (code == GE ? LE : GT); 10092 continue; 10093 } 10094 break; 10095 10096 case XOR: 10097 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification 10098 if C is zero or B is a constant. */ 10099 if (equality_comparison_p 10100 && 0 != (tem = simplify_binary_operation (XOR, mode, 10101 XEXP (op0, 1), op1))) 10102 { 10103 op0 = XEXP (op0, 0); 10104 op1 = tem; 10105 continue; 10106 } 10107 break; 10108 10109 case EQ: case NE: 10110 case LT: case LTU: case LE: case LEU: 10111 case GT: case GTU: case GE: case GEU: 10112 /* We can't do anything if OP0 is a condition code value, rather 10113 than an actual data value. */ 10114 if (const_op != 0 10115#ifdef HAVE_cc0 10116 || XEXP (op0, 0) == cc0_rtx 10117#endif 10118 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) 10119 break; 10120 10121 /* Get the two operands being compared. */ 10122 if (GET_CODE (XEXP (op0, 0)) == COMPARE) 10123 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); 10124 else 10125 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); 10126 10127 /* Check for the cases where we simply want the result of the 10128 earlier test or the opposite of that result. */ 10129 if (code == NE 10130 || (code == EQ && reversible_comparison_p (op0)) 10131 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 10132 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10133 && (STORE_FLAG_VALUE 10134 & (((HOST_WIDE_INT) 1 10135 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) 10136 && (code == LT 10137 || (code == GE && reversible_comparison_p (op0))))) 10138 { 10139 code = (code == LT || code == NE 10140 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0))); 10141 op0 = tem, op1 = tem1; 10142 continue; 10143 } 10144 break; 10145 10146 case IOR: 10147 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero 10148 iff X <= 0. */ 10149 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS 10150 && XEXP (XEXP (op0, 0), 1) == constm1_rtx 10151 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 10152 { 10153 op0 = XEXP (op0, 1); 10154 code = (code == GE ? GT : LE); 10155 continue; 10156 } 10157 break; 10158 10159 case AND: 10160 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This 10161 will be converted to a ZERO_EXTRACT later. */ 10162 if (const_op == 0 && equality_comparison_p 10163 && GET_CODE (XEXP (op0, 0)) == ASHIFT 10164 && XEXP (XEXP (op0, 0), 0) == const1_rtx) 10165 { 10166 op0 = simplify_and_const_int 10167 (op0, mode, gen_rtx_combine (LSHIFTRT, mode, 10168 XEXP (op0, 1), 10169 XEXP (XEXP (op0, 0), 1)), 10170 (HOST_WIDE_INT) 1); 10171 continue; 10172 } 10173 10174 /* If we are comparing (and (lshiftrt X C1) C2) for equality with 10175 zero and X is a comparison and C1 and C2 describe only bits set 10176 in STORE_FLAG_VALUE, we can compare with X. */ 10177 if (const_op == 0 && equality_comparison_p 10178 && mode_width <= HOST_BITS_PER_WIDE_INT 10179 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10180 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT 10181 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10182 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 10183 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) 10184 { 10185 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 10186 << INTVAL (XEXP (XEXP (op0, 0), 1))); 10187 if ((~ STORE_FLAG_VALUE & mask) == 0 10188 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<' 10189 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 10190 && GET_RTX_CLASS (GET_CODE (tem)) == '<'))) 10191 { 10192 op0 = XEXP (XEXP (op0, 0), 0); 10193 continue; 10194 } 10195 } 10196 10197 /* If we are doing an equality comparison of an AND of a bit equal 10198 to the sign bit, replace this with a LT or GE comparison of 10199 the underlying value. */ 10200 if (equality_comparison_p 10201 && const_op == 0 10202 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10203 && mode_width <= HOST_BITS_PER_WIDE_INT 10204 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 10205 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) 10206 { 10207 op0 = XEXP (op0, 0); 10208 code = (code == EQ ? GE : LT); 10209 continue; 10210 } 10211 10212 /* If this AND operation is really a ZERO_EXTEND from a narrower 10213 mode, the constant fits within that mode, and this is either an 10214 equality or unsigned comparison, try to do this comparison in 10215 the narrower mode. */ 10216 if ((equality_comparison_p || unsigned_comparison_p) 10217 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10218 && (i = exact_log2 ((INTVAL (XEXP (op0, 1)) 10219 & GET_MODE_MASK (mode)) 10220 + 1)) >= 0 10221 && const_op >> i == 0 10222 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode) 10223 { 10224 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0)); 10225 continue; 10226 } 10227 10228 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits 10229 in both M1 and M2 and the SUBREG is either paradoxical or 10230 represents the low part, permute the SUBREG and the AND and 10231 try again. */ 10232 if (GET_CODE (XEXP (op0, 0)) == SUBREG 10233 && ((mode_width 10234 >= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))) 10235#ifdef WORD_REGISTER_OPERATIONS 10236 || subreg_lowpart_p (XEXP (op0, 0)) 10237#endif 10238 ) 10239#ifndef WORD_REGISTER_OPERATIONS 10240 /* It is unsafe to commute the AND into the SUBREG if the SUBREG 10241 is paradoxical and WORD_REGISTER_OPERATIONS is not defined. 10242 As originally written the upper bits have a defined value 10243 due to the AND operation. However, if we commute the AND 10244 inside the SUBREG then they no longer have defined values 10245 and the meaning of the code has been changed. */ 10246 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) 10247 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))) 10248#endif 10249 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10250 && mode_width <= HOST_BITS_PER_WIDE_INT 10251 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))) 10252 <= HOST_BITS_PER_WIDE_INT) 10253 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0 10254 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0)))) 10255 & INTVAL (XEXP (op0, 1))) 10256 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask 10257 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) 10258 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))) 10259 10260 { 10261 op0 10262 = gen_lowpart_for_combine 10263 (mode, 10264 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))), 10265 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1))); 10266 continue; 10267 } 10268 10269 break; 10270 10271 case ASHIFT: 10272 /* If we have (compare (ashift FOO N) (const_int C)) and 10273 the high order N bits of FOO (N+1 if an inequality comparison) 10274 are known to be zero, we can do this by comparing FOO with C 10275 shifted right N bits so long as the low-order N bits of C are 10276 zero. */ 10277 if (GET_CODE (XEXP (op0, 1)) == CONST_INT 10278 && INTVAL (XEXP (op0, 1)) >= 0 10279 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) 10280 < HOST_BITS_PER_WIDE_INT) 10281 && ((const_op 10282 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0) 10283 && mode_width <= HOST_BITS_PER_WIDE_INT 10284 && (nonzero_bits (XEXP (op0, 0), mode) 10285 & ~ (mask >> (INTVAL (XEXP (op0, 1)) 10286 + ! equality_comparison_p))) == 0) 10287 { 10288 const_op >>= INTVAL (XEXP (op0, 1)); 10289 op1 = GEN_INT (const_op); 10290 op0 = XEXP (op0, 0); 10291 continue; 10292 } 10293 10294 /* If we are doing a sign bit comparison, it means we are testing 10295 a particular bit. Convert it to the appropriate AND. */ 10296 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT 10297 && mode_width <= HOST_BITS_PER_WIDE_INT) 10298 { 10299 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10300 ((HOST_WIDE_INT) 1 10301 << (mode_width - 1 10302 - INTVAL (XEXP (op0, 1))))); 10303 code = (code == LT ? NE : EQ); 10304 continue; 10305 } 10306 10307 /* If this an equality comparison with zero and we are shifting 10308 the low bit to the sign bit, we can convert this to an AND of the 10309 low-order bit. */ 10310 if (const_op == 0 && equality_comparison_p 10311 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10312 && INTVAL (XEXP (op0, 1)) == mode_width - 1) 10313 { 10314 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10315 (HOST_WIDE_INT) 1); 10316 continue; 10317 } 10318 break; 10319 10320 case ASHIFTRT: 10321 /* If this is an equality comparison with zero, we can do this 10322 as a logical shift, which might be much simpler. */ 10323 if (equality_comparison_p && const_op == 0 10324 && GET_CODE (XEXP (op0, 1)) == CONST_INT) 10325 { 10326 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, 10327 XEXP (op0, 0), 10328 INTVAL (XEXP (op0, 1))); 10329 continue; 10330 } 10331 10332 /* If OP0 is a sign extension and CODE is not an unsigned comparison, 10333 do the comparison in a narrower mode. */ 10334 if (! unsigned_comparison_p 10335 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10336 && GET_CODE (XEXP (op0, 0)) == ASHIFT 10337 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 10338 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 10339 MODE_INT, 1)) != BLKmode 10340 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode) 10341 || ((unsigned HOST_WIDE_INT) - const_op 10342 <= GET_MODE_MASK (tmode)))) 10343 { 10344 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0)); 10345 continue; 10346 } 10347 10348 /* ... fall through ... */ 10349 case LSHIFTRT: 10350 /* If we have (compare (xshiftrt FOO N) (const_int C)) and 10351 the low order N bits of FOO are known to be zero, we can do this 10352 by comparing FOO with C shifted left N bits so long as no 10353 overflow occurs. */ 10354 if (GET_CODE (XEXP (op0, 1)) == CONST_INT 10355 && INTVAL (XEXP (op0, 1)) >= 0 10356 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 10357 && mode_width <= HOST_BITS_PER_WIDE_INT 10358 && (nonzero_bits (XEXP (op0, 0), mode) 10359 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 10360 && (const_op == 0 10361 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1)) 10362 < mode_width))) 10363 { 10364 const_op <<= INTVAL (XEXP (op0, 1)); 10365 op1 = GEN_INT (const_op); 10366 op0 = XEXP (op0, 0); 10367 continue; 10368 } 10369 10370 /* If we are using this shift to extract just the sign bit, we 10371 can replace this with an LT or GE comparison. */ 10372 if (const_op == 0 10373 && (equality_comparison_p || sign_bit_comparison_p) 10374 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10375 && INTVAL (XEXP (op0, 1)) == mode_width - 1) 10376 { 10377 op0 = XEXP (op0, 0); 10378 code = (code == NE || code == GT ? LT : GE); 10379 continue; 10380 } 10381 break; 10382 10383 default: 10384 break; 10385 } 10386 10387 break; 10388 } 10389 10390 /* Now make any compound operations involved in this comparison. Then, 10391 check for an outmost SUBREG on OP0 that is not doing anything or is 10392 paradoxical. The latter case can only occur when it is known that the 10393 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG. 10394 We can never remove a SUBREG for a non-equality comparison because the 10395 sign bit is in a different place in the underlying object. */ 10396 10397 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); 10398 op1 = make_compound_operation (op1, SET); 10399 10400 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 10401 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10402 && (code == NE || code == EQ) 10403 && ((GET_MODE_SIZE (GET_MODE (op0)) 10404 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))) 10405 { 10406 op0 = SUBREG_REG (op0); 10407 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1); 10408 } 10409 10410 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 10411 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10412 && (code == NE || code == EQ) 10413 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) 10414 <= HOST_BITS_PER_WIDE_INT) 10415 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0))) 10416 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0 10417 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), 10418 op1), 10419 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) 10420 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0)) 10421 op0 = SUBREG_REG (op0), op1 = tem; 10422 10423 /* We now do the opposite procedure: Some machines don't have compare 10424 insns in all modes. If OP0's mode is an integer mode smaller than a 10425 word and we can't do a compare in that mode, see if there is a larger 10426 mode for which we can do the compare. There are a number of cases in 10427 which we can use the wider mode. */ 10428 10429 mode = GET_MODE (op0); 10430 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT 10431 && GET_MODE_SIZE (mode) < UNITS_PER_WORD 10432 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) 10433 for (tmode = GET_MODE_WIDER_MODE (mode); 10434 (tmode != VOIDmode 10435 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT); 10436 tmode = GET_MODE_WIDER_MODE (tmode)) 10437 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing) 10438 { 10439 /* If the only nonzero bits in OP0 and OP1 are those in the 10440 narrower mode and this is an equality or unsigned comparison, 10441 we can use the wider mode. Similarly for sign-extended 10442 values, in which case it is true for all comparisons. */ 10443 if (((code == EQ || code == NE 10444 || code == GEU || code == GTU || code == LEU || code == LTU) 10445 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0 10446 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0) 10447 || ((num_sign_bit_copies (op0, tmode) 10448 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode)) 10449 && (num_sign_bit_copies (op1, tmode) 10450 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode)))) 10451 { 10452 op0 = gen_lowpart_for_combine (tmode, op0); 10453 op1 = gen_lowpart_for_combine (tmode, op1); 10454 break; 10455 } 10456 10457 /* If this is a test for negative, we can make an explicit 10458 test of the sign bit. */ 10459 10460 if (op1 == const0_rtx && (code == LT || code == GE) 10461 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 10462 { 10463 op0 = gen_binary (AND, tmode, 10464 gen_lowpart_for_combine (tmode, op0), 10465 GEN_INT ((HOST_WIDE_INT) 1 10466 << (GET_MODE_BITSIZE (mode) - 1))); 10467 code = (code == LT) ? NE : EQ; 10468 break; 10469 } 10470 } 10471 10472#ifdef CANONICALIZE_COMPARISON 10473 /* If this machine only supports a subset of valid comparisons, see if we 10474 can convert an unsupported one into a supported one. */ 10475 CANONICALIZE_COMPARISON (code, op0, op1); 10476#endif 10477 10478 *pop0 = op0; 10479 *pop1 = op1; 10480 10481 return code; 10482} 10483 10484/* Return 1 if we know that X, a comparison operation, is not operating 10485 on a floating-point value or is EQ or NE, meaning that we can safely 10486 reverse it. */ 10487 10488static int 10489reversible_comparison_p (x) 10490 rtx x; 10491{ 10492 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT 10493 || flag_fast_math 10494 || GET_CODE (x) == NE || GET_CODE (x) == EQ) 10495 return 1; 10496 10497 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0)))) 10498 { 10499 case MODE_INT: 10500 case MODE_PARTIAL_INT: 10501 case MODE_COMPLEX_INT: 10502 return 1; 10503 10504 case MODE_CC: 10505 /* If the mode of the condition codes tells us that this is safe, 10506 we need look no further. */ 10507 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0)))) 10508 return 1; 10509 10510 /* Otherwise try and find where the condition codes were last set and 10511 use that. */ 10512 x = get_last_value (XEXP (x, 0)); 10513 return (x && GET_CODE (x) == COMPARE 10514 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))); 10515 10516 default: 10517 return 0; 10518 } 10519} 10520 10521/* Utility function for following routine. Called when X is part of a value 10522 being stored into reg_last_set_value. Sets reg_last_set_table_tick 10523 for each register mentioned. Similar to mention_regs in cse.c */ 10524 10525static void 10526update_table_tick (x) 10527 rtx x; 10528{ 10529 register enum rtx_code code = GET_CODE (x); 10530 register char *fmt = GET_RTX_FORMAT (code); 10531 register int i; 10532 10533 if (code == REG) 10534 { 10535 int regno = REGNO (x); 10536 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER 10537 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 10538 10539 for (i = regno; i < endregno; i++) 10540 reg_last_set_table_tick[i] = label_tick; 10541 10542 return; 10543 } 10544 10545 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 10546 /* Note that we can't have an "E" in values stored; see 10547 get_last_value_validate. */ 10548 if (fmt[i] == 'e') 10549 update_table_tick (XEXP (x, i)); 10550} 10551 10552/* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we 10553 are saying that the register is clobbered and we no longer know its 10554 value. If INSN is zero, don't update reg_last_set; this is only permitted 10555 with VALUE also zero and is used to invalidate the register. */ 10556 10557static void 10558record_value_for_reg (reg, insn, value) 10559 rtx reg; 10560 rtx insn; 10561 rtx value; 10562{ 10563 int regno = REGNO (reg); 10564 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER 10565 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1); 10566 int i; 10567 10568 /* If VALUE contains REG and we have a previous value for REG, substitute 10569 the previous value. */ 10570 if (value && insn && reg_overlap_mentioned_p (reg, value)) 10571 { 10572 rtx tem; 10573 10574 /* Set things up so get_last_value is allowed to see anything set up to 10575 our insn. */ 10576 subst_low_cuid = INSN_CUID (insn); 10577 tem = get_last_value (reg); 10578 10579 if (tem) 10580 value = replace_rtx (copy_rtx (value), reg, tem); 10581 } 10582 10583 /* For each register modified, show we don't know its value, that 10584 we don't know about its bitwise content, that its value has been 10585 updated, and that we don't know the location of the death of the 10586 register. */ 10587 for (i = regno; i < endregno; i ++) 10588 { 10589 if (insn) 10590 reg_last_set[i] = insn; 10591 reg_last_set_value[i] = 0; 10592 reg_last_set_mode[i] = 0; 10593 reg_last_set_nonzero_bits[i] = 0; 10594 reg_last_set_sign_bit_copies[i] = 0; 10595 reg_last_death[i] = 0; 10596 } 10597 10598 /* Mark registers that are being referenced in this value. */ 10599 if (value) 10600 update_table_tick (value); 10601 10602 /* Now update the status of each register being set. 10603 If someone is using this register in this block, set this register 10604 to invalid since we will get confused between the two lives in this 10605 basic block. This makes using this register always invalid. In cse, we 10606 scan the table to invalidate all entries using this register, but this 10607 is too much work for us. */ 10608 10609 for (i = regno; i < endregno; i++) 10610 { 10611 reg_last_set_label[i] = label_tick; 10612 if (value && reg_last_set_table_tick[i] == label_tick) 10613 reg_last_set_invalid[i] = 1; 10614 else 10615 reg_last_set_invalid[i] = 0; 10616 } 10617 10618 /* The value being assigned might refer to X (like in "x++;"). In that 10619 case, we must replace it with (clobber (const_int 0)) to prevent 10620 infinite loops. */ 10621 if (value && ! get_last_value_validate (&value, insn, 10622 reg_last_set_label[regno], 0)) 10623 { 10624 value = copy_rtx (value); 10625 if (! get_last_value_validate (&value, insn, 10626 reg_last_set_label[regno], 1)) 10627 value = 0; 10628 } 10629 10630 /* For the main register being modified, update the value, the mode, the 10631 nonzero bits, and the number of sign bit copies. */ 10632 10633 reg_last_set_value[regno] = value; 10634 10635 if (value) 10636 { 10637 subst_low_cuid = INSN_CUID (insn); 10638 reg_last_set_mode[regno] = GET_MODE (reg); 10639 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg)); 10640 reg_last_set_sign_bit_copies[regno] 10641 = num_sign_bit_copies (value, GET_MODE (reg)); 10642 } 10643} 10644 10645/* Used for communication between the following two routines. */ 10646static rtx record_dead_insn; 10647 10648/* Called via note_stores from record_dead_and_set_regs to handle one 10649 SET or CLOBBER in an insn. */ 10650 10651static void 10652record_dead_and_set_regs_1 (dest, setter) 10653 rtx dest, setter; 10654{ 10655 if (GET_CODE (dest) == SUBREG) 10656 dest = SUBREG_REG (dest); 10657 10658 if (GET_CODE (dest) == REG) 10659 { 10660 /* If we are setting the whole register, we know its value. Otherwise 10661 show that we don't know the value. We can handle SUBREG in 10662 some cases. */ 10663 if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) 10664 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); 10665 else if (GET_CODE (setter) == SET 10666 && GET_CODE (SET_DEST (setter)) == SUBREG 10667 && SUBREG_REG (SET_DEST (setter)) == dest 10668 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD 10669 && subreg_lowpart_p (SET_DEST (setter))) 10670 record_value_for_reg (dest, record_dead_insn, 10671 gen_lowpart_for_combine (GET_MODE (dest), 10672 SET_SRC (setter))); 10673 else 10674 record_value_for_reg (dest, record_dead_insn, NULL_RTX); 10675 } 10676 else if (GET_CODE (dest) == MEM 10677 /* Ignore pushes, they clobber nothing. */ 10678 && ! push_operand (dest, GET_MODE (dest))) 10679 mem_last_set = INSN_CUID (record_dead_insn); 10680} 10681 10682/* Update the records of when each REG was most recently set or killed 10683 for the things done by INSN. This is the last thing done in processing 10684 INSN in the combiner loop. 10685 10686 We update reg_last_set, reg_last_set_value, reg_last_set_mode, 10687 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death, 10688 and also the similar information mem_last_set (which insn most recently 10689 modified memory) and last_call_cuid (which insn was the most recent 10690 subroutine call). */ 10691 10692static void 10693record_dead_and_set_regs (insn) 10694 rtx insn; 10695{ 10696 register rtx link; 10697 int i; 10698 10699 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 10700 { 10701 if (REG_NOTE_KIND (link) == REG_DEAD 10702 && GET_CODE (XEXP (link, 0)) == REG) 10703 { 10704 int regno = REGNO (XEXP (link, 0)); 10705 int endregno 10706 = regno + (regno < FIRST_PSEUDO_REGISTER 10707 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0))) 10708 : 1); 10709 10710 for (i = regno; i < endregno; i++) 10711 reg_last_death[i] = insn; 10712 } 10713 else if (REG_NOTE_KIND (link) == REG_INC) 10714 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); 10715 } 10716 10717 if (GET_CODE (insn) == CALL_INSN) 10718 { 10719 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 10720 if (call_used_regs[i]) 10721 { 10722 reg_last_set_value[i] = 0; 10723 reg_last_set_mode[i] = 0; 10724 reg_last_set_nonzero_bits[i] = 0; 10725 reg_last_set_sign_bit_copies[i] = 0; 10726 reg_last_death[i] = 0; 10727 } 10728 10729 last_call_cuid = mem_last_set = INSN_CUID (insn); 10730 } 10731 10732 record_dead_insn = insn; 10733 note_stores (PATTERN (insn), record_dead_and_set_regs_1); 10734} 10735 10736/* Utility routine for the following function. Verify that all the registers 10737 mentioned in *LOC are valid when *LOC was part of a value set when 10738 label_tick == TICK. Return 0 if some are not. 10739 10740 If REPLACE is non-zero, replace the invalid reference with 10741 (clobber (const_int 0)) and return 1. This replacement is useful because 10742 we often can get useful information about the form of a value (e.g., if 10743 it was produced by a shift that always produces -1 or 0) even though 10744 we don't know exactly what registers it was produced from. */ 10745 10746static int 10747get_last_value_validate (loc, insn, tick, replace) 10748 rtx *loc; 10749 rtx insn; 10750 int tick; 10751 int replace; 10752{ 10753 rtx x = *loc; 10754 char *fmt = GET_RTX_FORMAT (GET_CODE (x)); 10755 int len = GET_RTX_LENGTH (GET_CODE (x)); 10756 int i; 10757 10758 if (GET_CODE (x) == REG) 10759 { 10760 int regno = REGNO (x); 10761 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER 10762 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 10763 int j; 10764 10765 for (j = regno; j < endregno; j++) 10766 if (reg_last_set_invalid[j] 10767 /* If this is a pseudo-register that was only set once, it is 10768 always valid. */ 10769 || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1) 10770 && reg_last_set_label[j] > tick)) 10771 { 10772 if (replace) 10773 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 10774 return replace; 10775 } 10776 10777 return 1; 10778 } 10779 /* If this is a memory reference, make sure that there were 10780 no stores after it that might have clobbered the value. We don't 10781 have alias info, so we assume any store invalidates it. */ 10782 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x) 10783 && INSN_CUID (insn) <= mem_last_set) 10784 { 10785 if (replace) 10786 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 10787 return replace; 10788 } 10789 10790 for (i = 0; i < len; i++) 10791 if ((fmt[i] == 'e' 10792 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0) 10793 /* Don't bother with these. They shouldn't occur anyway. */ 10794 || fmt[i] == 'E') 10795 return 0; 10796 10797 /* If we haven't found a reason for it to be invalid, it is valid. */ 10798 return 1; 10799} 10800 10801/* Get the last value assigned to X, if known. Some registers 10802 in the value may be replaced with (clobber (const_int 0)) if their value 10803 is known longer known reliably. */ 10804 10805static rtx 10806get_last_value (x) 10807 rtx x; 10808{ 10809 int regno; 10810 rtx value; 10811 10812 /* If this is a non-paradoxical SUBREG, get the value of its operand and 10813 then convert it to the desired mode. If this is a paradoxical SUBREG, 10814 we cannot predict what values the "extra" bits might have. */ 10815 if (GET_CODE (x) == SUBREG 10816 && subreg_lowpart_p (x) 10817 && (GET_MODE_SIZE (GET_MODE (x)) 10818 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 10819 && (value = get_last_value (SUBREG_REG (x))) != 0) 10820 return gen_lowpart_for_combine (GET_MODE (x), value); 10821 10822 if (GET_CODE (x) != REG) 10823 return 0; 10824 10825 regno = REGNO (x); 10826 value = reg_last_set_value[regno]; 10827 10828 /* If we don't have a value or if it isn't for this basic block, 10829 return 0. */ 10830 10831 if (value == 0 10832 || (REG_N_SETS (regno) != 1 10833 && reg_last_set_label[regno] != label_tick)) 10834 return 0; 10835 10836 /* If the value was set in a later insn than the ones we are processing, 10837 we can't use it even if the register was only set once, but make a quick 10838 check to see if the previous insn set it to something. This is commonly 10839 the case when the same pseudo is used by repeated insns. 10840 10841 This does not work if there exists an instruction which is temporarily 10842 not on the insn chain. */ 10843 10844 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid) 10845 { 10846 rtx insn, set; 10847 10848 /* We can not do anything useful in this case, because there is 10849 an instruction which is not on the insn chain. */ 10850 if (subst_prev_insn) 10851 return 0; 10852 10853 /* Skip over USE insns. They are not useful here, and they may have 10854 been made by combine, in which case they do not have a INSN_CUID 10855 value. We can't use prev_real_insn, because that would incorrectly 10856 take us backwards across labels. Skip over BARRIERs also, since 10857 they could have been made by combine. If we see one, we must be 10858 optimizing dead code, so it doesn't matter what we do. */ 10859 for (insn = prev_nonnote_insn (subst_insn); 10860 insn && ((GET_CODE (insn) == INSN 10861 && GET_CODE (PATTERN (insn)) == USE) 10862 || GET_CODE (insn) == BARRIER 10863 || INSN_CUID (insn) >= subst_low_cuid); 10864 insn = prev_nonnote_insn (insn)) 10865 ; 10866 10867 if (insn 10868 && (set = single_set (insn)) != 0 10869 && rtx_equal_p (SET_DEST (set), x)) 10870 { 10871 value = SET_SRC (set); 10872 10873 /* Make sure that VALUE doesn't reference X. Replace any 10874 explicit references with a CLOBBER. If there are any remaining 10875 references (rare), don't use the value. */ 10876 10877 if (reg_mentioned_p (x, value)) 10878 value = replace_rtx (copy_rtx (value), x, 10879 gen_rtx_CLOBBER (GET_MODE (x), const0_rtx)); 10880 10881 if (reg_overlap_mentioned_p (x, value)) 10882 return 0; 10883 } 10884 else 10885 return 0; 10886 } 10887 10888 /* If the value has all its registers valid, return it. */ 10889 if (get_last_value_validate (&value, reg_last_set[regno], 10890 reg_last_set_label[regno], 0)) 10891 return value; 10892 10893 /* Otherwise, make a copy and replace any invalid register with 10894 (clobber (const_int 0)). If that fails for some reason, return 0. */ 10895 10896 value = copy_rtx (value); 10897 if (get_last_value_validate (&value, reg_last_set[regno], 10898 reg_last_set_label[regno], 1)) 10899 return value; 10900 10901 return 0; 10902} 10903 10904/* Return nonzero if expression X refers to a REG or to memory 10905 that is set in an instruction more recent than FROM_CUID. */ 10906 10907static int 10908use_crosses_set_p (x, from_cuid) 10909 register rtx x; 10910 int from_cuid; 10911{ 10912 register char *fmt; 10913 register int i; 10914 register enum rtx_code code = GET_CODE (x); 10915 10916 if (code == REG) 10917 { 10918 register int regno = REGNO (x); 10919 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER 10920 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 10921 10922#ifdef PUSH_ROUNDING 10923 /* Don't allow uses of the stack pointer to be moved, 10924 because we don't know whether the move crosses a push insn. */ 10925 if (regno == STACK_POINTER_REGNUM) 10926 return 1; 10927#endif 10928 for (;regno < endreg; regno++) 10929 if (reg_last_set[regno] 10930 && INSN_CUID (reg_last_set[regno]) > from_cuid) 10931 return 1; 10932 return 0; 10933 } 10934 10935 if (code == MEM && mem_last_set > from_cuid) 10936 return 1; 10937 10938 fmt = GET_RTX_FORMAT (code); 10939 10940 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 10941 { 10942 if (fmt[i] == 'E') 10943 { 10944 register int j; 10945 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 10946 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid)) 10947 return 1; 10948 } 10949 else if (fmt[i] == 'e' 10950 && use_crosses_set_p (XEXP (x, i), from_cuid)) 10951 return 1; 10952 } 10953 return 0; 10954} 10955 10956/* Define three variables used for communication between the following 10957 routines. */ 10958 10959static int reg_dead_regno, reg_dead_endregno; 10960static int reg_dead_flag; 10961 10962/* Function called via note_stores from reg_dead_at_p. 10963 10964 If DEST is within [reg_dead_regno, reg_dead_endregno), set 10965 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ 10966 10967static void 10968reg_dead_at_p_1 (dest, x) 10969 rtx dest; 10970 rtx x; 10971{ 10972 int regno, endregno; 10973 10974 if (GET_CODE (dest) != REG) 10975 return; 10976 10977 regno = REGNO (dest); 10978 endregno = regno + (regno < FIRST_PSEUDO_REGISTER 10979 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1); 10980 10981 if (reg_dead_endregno > regno && reg_dead_regno < endregno) 10982 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; 10983} 10984 10985/* Return non-zero if REG is known to be dead at INSN. 10986 10987 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER 10988 referencing REG, it is dead. If we hit a SET referencing REG, it is 10989 live. Otherwise, see if it is live or dead at the start of the basic 10990 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS 10991 must be assumed to be always live. */ 10992 10993static int 10994reg_dead_at_p (reg, insn) 10995 rtx reg; 10996 rtx insn; 10997{ 10998 int block, i; 10999 11000 /* Set variables for reg_dead_at_p_1. */ 11001 reg_dead_regno = REGNO (reg); 11002 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER 11003 ? HARD_REGNO_NREGS (reg_dead_regno, 11004 GET_MODE (reg)) 11005 : 1); 11006 11007 reg_dead_flag = 0; 11008 11009 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */ 11010 if (reg_dead_regno < FIRST_PSEUDO_REGISTER) 11011 { 11012 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 11013 if (TEST_HARD_REG_BIT (newpat_used_regs, i)) 11014 return 0; 11015 } 11016 11017 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or 11018 beginning of function. */ 11019 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER; 11020 insn = prev_nonnote_insn (insn)) 11021 { 11022 note_stores (PATTERN (insn), reg_dead_at_p_1); 11023 if (reg_dead_flag) 11024 return reg_dead_flag == 1 ? 1 : 0; 11025 11026 if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) 11027 return 1; 11028 } 11029 11030 /* Get the basic block number that we were in. */ 11031 if (insn == 0) 11032 block = 0; 11033 else 11034 { 11035 for (block = 0; block < n_basic_blocks; block++) 11036 if (insn == BLOCK_HEAD (block)) 11037 break; 11038 11039 if (block == n_basic_blocks) 11040 return 0; 11041 } 11042 11043 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 11044 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i)) 11045 return 0; 11046 11047 return 1; 11048} 11049 11050/* Note hard registers in X that are used. This code is similar to 11051 that in flow.c, but much simpler since we don't care about pseudos. */ 11052 11053static void 11054mark_used_regs_combine (x) 11055 rtx x; 11056{ 11057 register RTX_CODE code = GET_CODE (x); 11058 register int regno; 11059 int i; 11060 11061 switch (code) 11062 { 11063 case LABEL_REF: 11064 case SYMBOL_REF: 11065 case CONST_INT: 11066 case CONST: 11067 case CONST_DOUBLE: 11068 case PC: 11069 case ADDR_VEC: 11070 case ADDR_DIFF_VEC: 11071 case ASM_INPUT: 11072#ifdef HAVE_cc0 11073 /* CC0 must die in the insn after it is set, so we don't need to take 11074 special note of it here. */ 11075 case CC0: 11076#endif 11077 return; 11078 11079 case CLOBBER: 11080 /* If we are clobbering a MEM, mark any hard registers inside the 11081 address as used. */ 11082 if (GET_CODE (XEXP (x, 0)) == MEM) 11083 mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); 11084 return; 11085 11086 case REG: 11087 regno = REGNO (x); 11088 /* A hard reg in a wide mode may really be multiple registers. 11089 If so, mark all of them just like the first. */ 11090 if (regno < FIRST_PSEUDO_REGISTER) 11091 { 11092 /* None of this applies to the stack, frame or arg pointers */ 11093 if (regno == STACK_POINTER_REGNUM 11094#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM 11095 || regno == HARD_FRAME_POINTER_REGNUM 11096#endif 11097#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 11098 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) 11099#endif 11100 || regno == FRAME_POINTER_REGNUM) 11101 return; 11102 11103 i = HARD_REGNO_NREGS (regno, GET_MODE (x)); 11104 while (i-- > 0) 11105 SET_HARD_REG_BIT (newpat_used_regs, regno + i); 11106 } 11107 return; 11108 11109 case SET: 11110 { 11111 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in 11112 the address. */ 11113 register rtx testreg = SET_DEST (x); 11114 11115 while (GET_CODE (testreg) == SUBREG 11116 || GET_CODE (testreg) == ZERO_EXTRACT 11117 || GET_CODE (testreg) == SIGN_EXTRACT 11118 || GET_CODE (testreg) == STRICT_LOW_PART) 11119 testreg = XEXP (testreg, 0); 11120 11121 if (GET_CODE (testreg) == MEM) 11122 mark_used_regs_combine (XEXP (testreg, 0)); 11123 11124 mark_used_regs_combine (SET_SRC (x)); 11125 } 11126 return; 11127 11128 default: 11129 break; 11130 } 11131 11132 /* Recursively scan the operands of this expression. */ 11133 11134 { 11135 register char *fmt = GET_RTX_FORMAT (code); 11136 11137 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 11138 { 11139 if (fmt[i] == 'e') 11140 mark_used_regs_combine (XEXP (x, i)); 11141 else if (fmt[i] == 'E') 11142 { 11143 register int j; 11144 11145 for (j = 0; j < XVECLEN (x, i); j++) 11146 mark_used_regs_combine (XVECEXP (x, i, j)); 11147 } 11148 } 11149 } 11150} 11151 11152 11153/* Remove register number REGNO from the dead registers list of INSN. 11154 11155 Return the note used to record the death, if there was one. */ 11156 11157rtx 11158remove_death (regno, insn) 11159 int regno; 11160 rtx insn; 11161{ 11162 register rtx note = find_regno_note (insn, REG_DEAD, regno); 11163 11164 if (note) 11165 { 11166 REG_N_DEATHS (regno)--; 11167 remove_note (insn, note); 11168 } 11169 11170 return note; 11171} 11172 11173/* For each register (hardware or pseudo) used within expression X, if its 11174 death is in an instruction with cuid between FROM_CUID (inclusive) and 11175 TO_INSN (exclusive), put a REG_DEAD note for that register in the 11176 list headed by PNOTES. 11177 11178 That said, don't move registers killed by maybe_kill_insn. 11179 11180 This is done when X is being merged by combination into TO_INSN. These 11181 notes will then be distributed as needed. */ 11182 11183static void 11184move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes) 11185 rtx x; 11186 rtx maybe_kill_insn; 11187 int from_cuid; 11188 rtx to_insn; 11189 rtx *pnotes; 11190{ 11191 register char *fmt; 11192 register int len, i; 11193 register enum rtx_code code = GET_CODE (x); 11194 11195 if (code == REG) 11196 { 11197 register int regno = REGNO (x); 11198 register rtx where_dead = reg_last_death[regno]; 11199 register rtx before_dead, after_dead; 11200 11201 /* Don't move the register if it gets killed in between from and to */ 11202 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) 11203 && !reg_referenced_p (x, maybe_kill_insn)) 11204 return; 11205 11206 /* WHERE_DEAD could be a USE insn made by combine, so first we 11207 make sure that we have insns with valid INSN_CUID values. */ 11208 before_dead = where_dead; 11209 while (before_dead && INSN_UID (before_dead) > max_uid_cuid) 11210 before_dead = PREV_INSN (before_dead); 11211 after_dead = where_dead; 11212 while (after_dead && INSN_UID (after_dead) > max_uid_cuid) 11213 after_dead = NEXT_INSN (after_dead); 11214 11215 if (before_dead && after_dead 11216 && INSN_CUID (before_dead) >= from_cuid 11217 && (INSN_CUID (after_dead) < INSN_CUID (to_insn) 11218 || (where_dead != after_dead 11219 && INSN_CUID (after_dead) == INSN_CUID (to_insn)))) 11220 { 11221 rtx note = remove_death (regno, where_dead); 11222 11223 /* It is possible for the call above to return 0. This can occur 11224 when reg_last_death points to I2 or I1 that we combined with. 11225 In that case make a new note. 11226 11227 We must also check for the case where X is a hard register 11228 and NOTE is a death note for a range of hard registers 11229 including X. In that case, we must put REG_DEAD notes for 11230 the remaining registers in place of NOTE. */ 11231 11232 if (note != 0 && regno < FIRST_PSEUDO_REGISTER 11233 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 11234 > GET_MODE_SIZE (GET_MODE (x)))) 11235 { 11236 int deadregno = REGNO (XEXP (note, 0)); 11237 int deadend 11238 = (deadregno + HARD_REGNO_NREGS (deadregno, 11239 GET_MODE (XEXP (note, 0)))); 11240 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11241 int i; 11242 11243 for (i = deadregno; i < deadend; i++) 11244 if (i < regno || i >= ourend) 11245 REG_NOTES (where_dead) 11246 = gen_rtx_EXPR_LIST (REG_DEAD, 11247 gen_rtx_REG (reg_raw_mode[i], i), 11248 REG_NOTES (where_dead)); 11249 } 11250 /* If we didn't find any note, or if we found a REG_DEAD note that 11251 covers only part of the given reg, and we have a multi-reg hard 11252 register, then to be safe we must check for REG_DEAD notes 11253 for each register other than the first. They could have 11254 their own REG_DEAD notes lying around. */ 11255 else if ((note == 0 11256 || (note != 0 11257 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 11258 < GET_MODE_SIZE (GET_MODE (x))))) 11259 && regno < FIRST_PSEUDO_REGISTER 11260 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1) 11261 { 11262 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11263 int i, offset; 11264 rtx oldnotes = 0; 11265 11266 if (note) 11267 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))); 11268 else 11269 offset = 1; 11270 11271 for (i = regno + offset; i < ourend; i++) 11272 move_deaths (gen_rtx_REG (reg_raw_mode[i], i), 11273 maybe_kill_insn, from_cuid, to_insn, &oldnotes); 11274 } 11275 11276 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) 11277 { 11278 XEXP (note, 1) = *pnotes; 11279 *pnotes = note; 11280 } 11281 else 11282 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes); 11283 11284 REG_N_DEATHS (regno)++; 11285 } 11286 11287 return; 11288 } 11289 11290 else if (GET_CODE (x) == SET) 11291 { 11292 rtx dest = SET_DEST (x); 11293 11294 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes); 11295 11296 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG 11297 that accesses one word of a multi-word item, some 11298 piece of everything register in the expression is used by 11299 this insn, so remove any old death. */ 11300 11301 if (GET_CODE (dest) == ZERO_EXTRACT 11302 || GET_CODE (dest) == STRICT_LOW_PART 11303 || (GET_CODE (dest) == SUBREG 11304 && (((GET_MODE_SIZE (GET_MODE (dest)) 11305 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 11306 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) 11307 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) 11308 { 11309 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes); 11310 return; 11311 } 11312 11313 /* If this is some other SUBREG, we know it replaces the entire 11314 value, so use that as the destination. */ 11315 if (GET_CODE (dest) == SUBREG) 11316 dest = SUBREG_REG (dest); 11317 11318 /* If this is a MEM, adjust deaths of anything used in the address. 11319 For a REG (the only other possibility), the entire value is 11320 being replaced so the old value is not used in this insn. */ 11321 11322 if (GET_CODE (dest) == MEM) 11323 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid, 11324 to_insn, pnotes); 11325 return; 11326 } 11327 11328 else if (GET_CODE (x) == CLOBBER) 11329 return; 11330 11331 len = GET_RTX_LENGTH (code); 11332 fmt = GET_RTX_FORMAT (code); 11333 11334 for (i = 0; i < len; i++) 11335 { 11336 if (fmt[i] == 'E') 11337 { 11338 register int j; 11339 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 11340 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid, 11341 to_insn, pnotes); 11342 } 11343 else if (fmt[i] == 'e') 11344 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes); 11345 } 11346} 11347 11348/* Return 1 if X is the target of a bit-field assignment in BODY, the 11349 pattern of an insn. X must be a REG. */ 11350 11351static int 11352reg_bitfield_target_p (x, body) 11353 rtx x; 11354 rtx body; 11355{ 11356 int i; 11357 11358 if (GET_CODE (body) == SET) 11359 { 11360 rtx dest = SET_DEST (body); 11361 rtx target; 11362 int regno, tregno, endregno, endtregno; 11363 11364 if (GET_CODE (dest) == ZERO_EXTRACT) 11365 target = XEXP (dest, 0); 11366 else if (GET_CODE (dest) == STRICT_LOW_PART) 11367 target = SUBREG_REG (XEXP (dest, 0)); 11368 else 11369 return 0; 11370 11371 if (GET_CODE (target) == SUBREG) 11372 target = SUBREG_REG (target); 11373 11374 if (GET_CODE (target) != REG) 11375 return 0; 11376 11377 tregno = REGNO (target), regno = REGNO (x); 11378 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) 11379 return target == x; 11380 11381 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target)); 11382 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11383 11384 return endregno > tregno && regno < endtregno; 11385 } 11386 11387 else if (GET_CODE (body) == PARALLEL) 11388 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 11389 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) 11390 return 1; 11391 11392 return 0; 11393} 11394 11395/* Given a chain of REG_NOTES originally from FROM_INSN, try to place them 11396 as appropriate. I3 and I2 are the insns resulting from the combination 11397 insns including FROM (I2 may be zero). 11398 11399 ELIM_I2 and ELIM_I1 are either zero or registers that we know will 11400 not need REG_DEAD notes because they are being substituted for. This 11401 saves searching in the most common cases. 11402 11403 Each note in the list is either ignored or placed on some insns, depending 11404 on the type of note. */ 11405 11406static void 11407distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1) 11408 rtx notes; 11409 rtx from_insn; 11410 rtx i3, i2; 11411 rtx elim_i2, elim_i1; 11412{ 11413 rtx note, next_note; 11414 rtx tem; 11415 11416 for (note = notes; note; note = next_note) 11417 { 11418 rtx place = 0, place2 = 0; 11419 11420 /* If this NOTE references a pseudo register, ensure it references 11421 the latest copy of that register. */ 11422 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG 11423 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER) 11424 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))]; 11425 11426 next_note = XEXP (note, 1); 11427 switch (REG_NOTE_KIND (note)) 11428 { 11429 case REG_BR_PROB: 11430 case REG_EXEC_COUNT: 11431 /* Doesn't matter much where we put this, as long as it's somewhere. 11432 It is preferable to keep these notes on branches, which is most 11433 likely to be i3. */ 11434 place = i3; 11435 break; 11436 11437 case REG_EH_REGION: 11438 /* This note must remain with the call. It should not be possible 11439 for both I2 and I3 to be a call. */ 11440 if (GET_CODE (i3) == CALL_INSN) 11441 place = i3; 11442 else if (i2 && GET_CODE (i2) == CALL_INSN) 11443 place = i2; 11444 else 11445 abort (); 11446 break; 11447 11448 case REG_UNUSED: 11449 /* Any clobbers for i3 may still exist, and so we must process 11450 REG_UNUSED notes from that insn. 11451 11452 Any clobbers from i2 or i1 can only exist if they were added by 11453 recog_for_combine. In that case, recog_for_combine created the 11454 necessary REG_UNUSED notes. Trying to keep any original 11455 REG_UNUSED notes from these insns can cause incorrect output 11456 if it is for the same register as the original i3 dest. 11457 In that case, we will notice that the register is set in i3, 11458 and then add a REG_UNUSED note for the destination of i3, which 11459 is wrong. However, it is possible to have REG_UNUSED notes from 11460 i2 or i1 for register which were both used and clobbered, so 11461 we keep notes from i2 or i1 if they will turn into REG_DEAD 11462 notes. */ 11463 11464 /* If this register is set or clobbered in I3, put the note there 11465 unless there is one already. */ 11466 if (reg_set_p (XEXP (note, 0), PATTERN (i3))) 11467 { 11468 if (from_insn != i3) 11469 break; 11470 11471 if (! (GET_CODE (XEXP (note, 0)) == REG 11472 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) 11473 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) 11474 place = i3; 11475 } 11476 /* Otherwise, if this register is used by I3, then this register 11477 now dies here, so we must put a REG_DEAD note here unless there 11478 is one already. */ 11479 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) 11480 && ! (GET_CODE (XEXP (note, 0)) == REG 11481 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0))) 11482 : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) 11483 { 11484 PUT_REG_NOTE_KIND (note, REG_DEAD); 11485 place = i3; 11486 } 11487 break; 11488 11489 case REG_EQUAL: 11490 case REG_EQUIV: 11491 case REG_NONNEG: 11492 case REG_NOALIAS: 11493 /* These notes say something about results of an insn. We can 11494 only support them if they used to be on I3 in which case they 11495 remain on I3. Otherwise they are ignored. 11496 11497 If the note refers to an expression that is not a constant, we 11498 must also ignore the note since we cannot tell whether the 11499 equivalence is still true. It might be possible to do 11500 slightly better than this (we only have a problem if I2DEST 11501 or I1DEST is present in the expression), but it doesn't 11502 seem worth the trouble. */ 11503 11504 if (from_insn == i3 11505 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) 11506 place = i3; 11507 break; 11508 11509 case REG_INC: 11510 case REG_NO_CONFLICT: 11511 /* These notes say something about how a register is used. They must 11512 be present on any use of the register in I2 or I3. */ 11513 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) 11514 place = i3; 11515 11516 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) 11517 { 11518 if (place) 11519 place2 = i2; 11520 else 11521 place = i2; 11522 } 11523 break; 11524 11525 case REG_LABEL: 11526 /* This can show up in several ways -- either directly in the 11527 pattern, or hidden off in the constant pool with (or without?) 11528 a REG_EQUAL note. */ 11529 /* ??? Ignore the without-reg_equal-note problem for now. */ 11530 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) 11531 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX)) 11532 && GET_CODE (XEXP (tem, 0)) == LABEL_REF 11533 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))) 11534 place = i3; 11535 11536 if (i2 11537 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) 11538 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX)) 11539 && GET_CODE (XEXP (tem, 0)) == LABEL_REF 11540 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))) 11541 { 11542 if (place) 11543 place2 = i2; 11544 else 11545 place = i2; 11546 } 11547 break; 11548 11549 case REG_WAS_0: 11550 /* It is too much trouble to try to see if this note is still 11551 correct in all situations. It is better to simply delete it. */ 11552 break; 11553 11554 case REG_RETVAL: 11555 /* If the insn previously containing this note still exists, 11556 put it back where it was. Otherwise move it to the previous 11557 insn. Adjust the corresponding REG_LIBCALL note. */ 11558 if (GET_CODE (from_insn) != NOTE) 11559 place = from_insn; 11560 else 11561 { 11562 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX); 11563 place = prev_real_insn (from_insn); 11564 if (tem && place) 11565 XEXP (tem, 0) = place; 11566 } 11567 break; 11568 11569 case REG_LIBCALL: 11570 /* This is handled similarly to REG_RETVAL. */ 11571 if (GET_CODE (from_insn) != NOTE) 11572 place = from_insn; 11573 else 11574 { 11575 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX); 11576 place = next_real_insn (from_insn); 11577 if (tem && place) 11578 XEXP (tem, 0) = place; 11579 } 11580 break; 11581 11582 case REG_DEAD: 11583 /* If the register is used as an input in I3, it dies there. 11584 Similarly for I2, if it is non-zero and adjacent to I3. 11585 11586 If the register is not used as an input in either I3 or I2 11587 and it is not one of the registers we were supposed to eliminate, 11588 there are two possibilities. We might have a non-adjacent I2 11589 or we might have somehow eliminated an additional register 11590 from a computation. For example, we might have had A & B where 11591 we discover that B will always be zero. In this case we will 11592 eliminate the reference to A. 11593 11594 In both cases, we must search to see if we can find a previous 11595 use of A and put the death note there. */ 11596 11597 if (from_insn 11598 && GET_CODE (from_insn) == CALL_INSN 11599 && find_reg_fusage (from_insn, USE, XEXP (note, 0))) 11600 place = from_insn; 11601 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) 11602 place = i3; 11603 else if (i2 != 0 && next_nonnote_insn (i2) == i3 11604 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 11605 place = i2; 11606 11607 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1) 11608 break; 11609 11610 /* If the register is used in both I2 and I3 and it dies in I3, 11611 we might have added another reference to it. If reg_n_refs 11612 was 2, bump it to 3. This has to be correct since the 11613 register must have been set somewhere. The reason this is 11614 done is because local-alloc.c treats 2 references as a 11615 special case. */ 11616 11617 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG 11618 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2 11619 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 11620 REG_N_REFS (REGNO (XEXP (note, 0))) = 3; 11621 11622 if (place == 0) 11623 { 11624 for (tem = prev_nonnote_insn (i3); 11625 place == 0 && tem 11626 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN); 11627 tem = prev_nonnote_insn (tem)) 11628 { 11629 /* If the register is being set at TEM, see if that is all 11630 TEM is doing. If so, delete TEM. Otherwise, make this 11631 into a REG_UNUSED note instead. */ 11632 if (reg_set_p (XEXP (note, 0), PATTERN (tem))) 11633 { 11634 rtx set = single_set (tem); 11635 rtx inner_dest = 0; 11636#ifdef HAVE_cc0 11637 rtx cc0_setter = NULL_RTX; 11638#endif 11639 11640 if (set != 0) 11641 for (inner_dest = SET_DEST (set); 11642 GET_CODE (inner_dest) == STRICT_LOW_PART 11643 || GET_CODE (inner_dest) == SUBREG 11644 || GET_CODE (inner_dest) == ZERO_EXTRACT; 11645 inner_dest = XEXP (inner_dest, 0)) 11646 ; 11647 11648 /* Verify that it was the set, and not a clobber that 11649 modified the register. 11650 11651 CC0 targets must be careful to maintain setter/user 11652 pairs. If we cannot delete the setter due to side 11653 effects, mark the user with an UNUSED note instead 11654 of deleting it. */ 11655 11656 if (set != 0 && ! side_effects_p (SET_SRC (set)) 11657 && rtx_equal_p (XEXP (note, 0), inner_dest) 11658#ifdef HAVE_cc0 11659 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) 11660 || ((cc0_setter = prev_cc0_setter (tem)) != NULL 11661 && sets_cc0_p (PATTERN (cc0_setter)) > 0)) 11662#endif 11663 ) 11664 { 11665 /* Move the notes and links of TEM elsewhere. 11666 This might delete other dead insns recursively. 11667 First set the pattern to something that won't use 11668 any register. */ 11669 11670 PATTERN (tem) = pc_rtx; 11671 11672 distribute_notes (REG_NOTES (tem), tem, tem, 11673 NULL_RTX, NULL_RTX, NULL_RTX); 11674 distribute_links (LOG_LINKS (tem)); 11675 11676 PUT_CODE (tem, NOTE); 11677 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED; 11678 NOTE_SOURCE_FILE (tem) = 0; 11679 11680#ifdef HAVE_cc0 11681 /* Delete the setter too. */ 11682 if (cc0_setter) 11683 { 11684 PATTERN (cc0_setter) = pc_rtx; 11685 11686 distribute_notes (REG_NOTES (cc0_setter), 11687 cc0_setter, cc0_setter, 11688 NULL_RTX, NULL_RTX, NULL_RTX); 11689 distribute_links (LOG_LINKS (cc0_setter)); 11690 11691 PUT_CODE (cc0_setter, NOTE); 11692 NOTE_LINE_NUMBER (cc0_setter) = NOTE_INSN_DELETED; 11693 NOTE_SOURCE_FILE (cc0_setter) = 0; 11694 } 11695#endif 11696 } 11697 /* If the register is both set and used here, put the 11698 REG_DEAD note here, but place a REG_UNUSED note 11699 here too unless there already is one. */ 11700 else if (reg_referenced_p (XEXP (note, 0), 11701 PATTERN (tem))) 11702 { 11703 place = tem; 11704 11705 if (! find_regno_note (tem, REG_UNUSED, 11706 REGNO (XEXP (note, 0)))) 11707 REG_NOTES (tem) 11708 = gen_rtx_EXPR_LIST (REG_UNUSED, 11709 XEXP (note, 0), 11710 REG_NOTES (tem)); 11711 } 11712 else 11713 { 11714 PUT_REG_NOTE_KIND (note, REG_UNUSED); 11715 11716 /* If there isn't already a REG_UNUSED note, put one 11717 here. */ 11718 if (! find_regno_note (tem, REG_UNUSED, 11719 REGNO (XEXP (note, 0)))) 11720 place = tem; 11721 break; 11722 } 11723 } 11724 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)) 11725 || (GET_CODE (tem) == CALL_INSN 11726 && find_reg_fusage (tem, USE, XEXP (note, 0)))) 11727 { 11728 place = tem; 11729 11730 /* If we are doing a 3->2 combination, and we have a 11731 register which formerly died in i3 and was not used 11732 by i2, which now no longer dies in i3 and is used in 11733 i2 but does not die in i2, and place is between i2 11734 and i3, then we may need to move a link from place to 11735 i2. */ 11736 if (i2 && INSN_UID (place) <= max_uid_cuid 11737 && INSN_CUID (place) > INSN_CUID (i2) 11738 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2) 11739 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 11740 { 11741 rtx links = LOG_LINKS (place); 11742 LOG_LINKS (place) = 0; 11743 distribute_links (links); 11744 } 11745 break; 11746 } 11747 } 11748 11749 /* If we haven't found an insn for the death note and it 11750 is still a REG_DEAD note, but we have hit a CODE_LABEL, 11751 insert a USE insn for the register at that label and 11752 put the death node there. This prevents problems with 11753 call-state tracking in caller-save.c. */ 11754 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0) 11755 { 11756 place 11757 = emit_insn_after (gen_rtx_USE (VOIDmode, XEXP (note, 0)), 11758 tem); 11759 11760 /* If this insn was emitted between blocks, then update 11761 BLOCK_HEAD of the current block to include it. */ 11762 if (BLOCK_END (this_basic_block - 1) == tem) 11763 BLOCK_HEAD (this_basic_block) = place; 11764 } 11765 } 11766 11767 /* If the register is set or already dead at PLACE, we needn't do 11768 anything with this note if it is still a REG_DEAD note. 11769 We can here if it is set at all, not if is it totally replace, 11770 which is what `dead_or_set_p' checks, so also check for it being 11771 set partially. */ 11772 11773 11774 if (place && REG_NOTE_KIND (note) == REG_DEAD) 11775 { 11776 int regno = REGNO (XEXP (note, 0)); 11777 11778 if (dead_or_set_p (place, XEXP (note, 0)) 11779 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) 11780 { 11781 /* Unless the register previously died in PLACE, clear 11782 reg_last_death. [I no longer understand why this is 11783 being done.] */ 11784 if (reg_last_death[regno] != place) 11785 reg_last_death[regno] = 0; 11786 place = 0; 11787 } 11788 else 11789 reg_last_death[regno] = place; 11790 11791 /* If this is a death note for a hard reg that is occupying 11792 multiple registers, ensure that we are still using all 11793 parts of the object. If we find a piece of the object 11794 that is unused, we must add a USE for that piece before 11795 PLACE and put the appropriate REG_DEAD note on it. 11796 11797 An alternative would be to put a REG_UNUSED for the pieces 11798 on the insn that set the register, but that can't be done if 11799 it is not in the same block. It is simpler, though less 11800 efficient, to add the USE insns. */ 11801 11802 if (place && regno < FIRST_PSEUDO_REGISTER 11803 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1) 11804 { 11805 int endregno 11806 = regno + HARD_REGNO_NREGS (regno, 11807 GET_MODE (XEXP (note, 0))); 11808 int all_used = 1; 11809 int i; 11810 11811 for (i = regno; i < endregno; i++) 11812 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0) 11813 && ! find_regno_fusage (place, USE, i)) 11814 { 11815 rtx piece = gen_rtx_REG (reg_raw_mode[i], i); 11816 rtx p; 11817 11818 /* See if we already placed a USE note for this 11819 register in front of PLACE. */ 11820 for (p = place; 11821 GET_CODE (PREV_INSN (p)) == INSN 11822 && GET_CODE (PATTERN (PREV_INSN (p))) == USE; 11823 p = PREV_INSN (p)) 11824 if (rtx_equal_p (piece, 11825 XEXP (PATTERN (PREV_INSN (p)), 0))) 11826 { 11827 p = 0; 11828 break; 11829 } 11830 11831 if (p) 11832 { 11833 rtx use_insn 11834 = emit_insn_before (gen_rtx_USE (VOIDmode, 11835 piece), 11836 p); 11837 REG_NOTES (use_insn) 11838 = gen_rtx_EXPR_LIST (REG_DEAD, piece, 11839 REG_NOTES (use_insn)); 11840 } 11841 11842 all_used = 0; 11843 } 11844 11845 /* Check for the case where the register dying partially 11846 overlaps the register set by this insn. */ 11847 if (all_used) 11848 for (i = regno; i < endregno; i++) 11849 if (dead_or_set_regno_p (place, i)) 11850 { 11851 all_used = 0; 11852 break; 11853 } 11854 11855 if (! all_used) 11856 { 11857 /* Put only REG_DEAD notes for pieces that are 11858 still used and that are not already dead or set. */ 11859 11860 for (i = regno; i < endregno; i++) 11861 { 11862 rtx piece = gen_rtx_REG (reg_raw_mode[i], i); 11863 11864 if ((reg_referenced_p (piece, PATTERN (place)) 11865 || (GET_CODE (place) == CALL_INSN 11866 && find_reg_fusage (place, USE, piece))) 11867 && ! dead_or_set_p (place, piece) 11868 && ! reg_bitfield_target_p (piece, 11869 PATTERN (place))) 11870 REG_NOTES (place) 11871 = gen_rtx_EXPR_LIST (REG_DEAD, 11872 piece, REG_NOTES (place)); 11873 } 11874 11875 place = 0; 11876 } 11877 } 11878 } 11879 break; 11880 11881 default: 11882 /* Any other notes should not be present at this point in the 11883 compilation. */ 11884 abort (); 11885 } 11886 11887 if (place) 11888 { 11889 XEXP (note, 1) = REG_NOTES (place); 11890 REG_NOTES (place) = note; 11891 } 11892 else if ((REG_NOTE_KIND (note) == REG_DEAD 11893 || REG_NOTE_KIND (note) == REG_UNUSED) 11894 && GET_CODE (XEXP (note, 0)) == REG) 11895 REG_N_DEATHS (REGNO (XEXP (note, 0)))--; 11896 11897 if (place2) 11898 { 11899 if ((REG_NOTE_KIND (note) == REG_DEAD 11900 || REG_NOTE_KIND (note) == REG_UNUSED) 11901 && GET_CODE (XEXP (note, 0)) == REG) 11902 REG_N_DEATHS (REGNO (XEXP (note, 0)))++; 11903 11904 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note), 11905 REG_NOTE_KIND (note), 11906 XEXP (note, 0), 11907 REG_NOTES (place2)); 11908 } 11909 } 11910} 11911 11912/* Similarly to above, distribute the LOG_LINKS that used to be present on 11913 I3, I2, and I1 to new locations. This is also called in one case to 11914 add a link pointing at I3 when I3's destination is changed. */ 11915 11916static void 11917distribute_links (links) 11918 rtx links; 11919{ 11920 rtx link, next_link; 11921 11922 for (link = links; link; link = next_link) 11923 { 11924 rtx place = 0; 11925 rtx insn; 11926 rtx set, reg; 11927 11928 next_link = XEXP (link, 1); 11929 11930 /* If the insn that this link points to is a NOTE or isn't a single 11931 set, ignore it. In the latter case, it isn't clear what we 11932 can do other than ignore the link, since we can't tell which 11933 register it was for. Such links wouldn't be used by combine 11934 anyway. 11935 11936 It is not possible for the destination of the target of the link to 11937 have been changed by combine. The only potential of this is if we 11938 replace I3, I2, and I1 by I3 and I2. But in that case the 11939 destination of I2 also remains unchanged. */ 11940 11941 if (GET_CODE (XEXP (link, 0)) == NOTE 11942 || (set = single_set (XEXP (link, 0))) == 0) 11943 continue; 11944 11945 reg = SET_DEST (set); 11946 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT 11947 || GET_CODE (reg) == SIGN_EXTRACT 11948 || GET_CODE (reg) == STRICT_LOW_PART) 11949 reg = XEXP (reg, 0); 11950 11951 /* A LOG_LINK is defined as being placed on the first insn that uses 11952 a register and points to the insn that sets the register. Start 11953 searching at the next insn after the target of the link and stop 11954 when we reach a set of the register or the end of the basic block. 11955 11956 Note that this correctly handles the link that used to point from 11957 I3 to I2. Also note that not much searching is typically done here 11958 since most links don't point very far away. */ 11959 11960 for (insn = NEXT_INSN (XEXP (link, 0)); 11961 (insn && (this_basic_block == n_basic_blocks - 1 11962 || BLOCK_HEAD (this_basic_block + 1) != insn)); 11963 insn = NEXT_INSN (insn)) 11964 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' 11965 && reg_overlap_mentioned_p (reg, PATTERN (insn))) 11966 { 11967 if (reg_referenced_p (reg, PATTERN (insn))) 11968 place = insn; 11969 break; 11970 } 11971 else if (GET_CODE (insn) == CALL_INSN 11972 && find_reg_fusage (insn, USE, reg)) 11973 { 11974 place = insn; 11975 break; 11976 } 11977 11978 /* If we found a place to put the link, place it there unless there 11979 is already a link to the same insn as LINK at that point. */ 11980 11981 if (place) 11982 { 11983 rtx link2; 11984 11985 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1)) 11986 if (XEXP (link2, 0) == XEXP (link, 0)) 11987 break; 11988 11989 if (link2 == 0) 11990 { 11991 XEXP (link, 1) = LOG_LINKS (place); 11992 LOG_LINKS (place) = link; 11993 11994 /* Set added_links_insn to the earliest insn we added a 11995 link to. */ 11996 if (added_links_insn == 0 11997 || INSN_CUID (added_links_insn) > INSN_CUID (place)) 11998 added_links_insn = place; 11999 } 12000 } 12001 } 12002} 12003 12004/* Compute INSN_CUID for INSN, which is an insn made by combine. */ 12005 12006static int 12007insn_cuid (insn) 12008 rtx insn; 12009{ 12010 while (insn != 0 && INSN_UID (insn) > max_uid_cuid 12011 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE) 12012 insn = NEXT_INSN (insn); 12013 12014 if (INSN_UID (insn) > max_uid_cuid) 12015 abort (); 12016 12017 return INSN_CUID (insn); 12018} 12019 12020void 12021dump_combine_stats (file) 12022 FILE *file; 12023{ 12024 fnotice 12025 (file, 12026 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", 12027 combine_attempts, combine_merges, combine_extras, combine_successes); 12028} 12029 12030void 12031dump_combine_total_stats (file) 12032 FILE *file; 12033{ 12034 fnotice 12035 (file, 12036 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", 12037 total_attempts, total_merges, total_extras, total_successes); 12038} 12039