1@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, 2@c 2002, 2003, 2004 3@c Free Software Foundation, Inc. 4@c This is part of the GAS manual. 5@c For copying conditions, see the file as.texinfo. 6@ifset GENERIC 7@page 8@node MIPS-Dependent 9@chapter MIPS Dependent Features 10@end ifset 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter MIPS Dependent Features 14@end ifclear 15 16@cindex MIPS processor 17@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several 18different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, 19and MIPS64. For information about the @sc{mips} instruction set, see 20@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). 21For an overview of @sc{mips} assembly conventions, see ``Appendix D: 22Assembly Language Programming'' in the same work. 23 24@menu 25* MIPS Opts:: Assembler options 26* MIPS Object:: ECOFF object code 27* MIPS Stabs:: Directives for debugging information 28* MIPS ISA:: Directives to override the ISA level 29* MIPS symbol sizes:: Directives to override the size of symbols 30* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 31* MIPS insn:: Directive to mark data as an instruction 32* MIPS option stack:: Directives to save and restore options 33* MIPS ASE instruction generation overrides:: Directives to control 34 generation of MIPS ASE instructions 35@end menu 36 37@node MIPS Opts 38@section Assembler options 39 40The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these 41special options: 42 43@table @code 44@cindex @code{-G} option (MIPS) 45@item -G @var{num} 46This option sets the largest size of an object that can be referenced 47implicitly with the @code{gp} register. It is only accepted for targets 48that use @sc{ecoff} format. The default value is 8. 49 50@cindex @code{-EB} option (MIPS) 51@cindex @code{-EL} option (MIPS) 52@cindex MIPS big-endian output 53@cindex MIPS little-endian output 54@cindex big-endian output, MIPS 55@cindex little-endian output, MIPS 56@item -EB 57@itemx -EL 58Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or 59little-endian output at run time (unlike the other @sc{gnu} development 60tools, which must be configured for one or the other). Use @samp{-EB} 61to select big-endian output, and @samp{-EL} for little-endian. 62 63@item -KPIC 64@cindex PIC selection, MIPS 65@cindex @option{-KPIC} option, MIPS 66Generate SVR4-style PIC. This option tells the assembler to generate 67SVR4-style position-independent macro expansions. It also tells the 68assembler to mark the output file as PIC. 69 70@item -mvxworks-pic 71@cindex @option{-mvxworks-pic} option, MIPS 72Generate VxWorks PIC. This option tells the assembler to generate 73VxWorks-style position-independent macro expansions. 74 75@cindex MIPS architecture options 76@item -mips1 77@itemx -mips2 78@itemx -mips3 79@itemx -mips4 80@itemx -mips5 81@itemx -mips32 82@itemx -mips32r2 83@itemx -mips64 84@itemx -mips64r2 85Generate code for a particular MIPS Instruction Set Architecture level. 86@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, 87@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the 88@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and 89@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, 90@samp{-mips64}, and @samp{-mips64r2} 91correspond to generic 92@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, 93and @sc{MIPS64 Release 2} 94ISA processors, respectively. You can also switch 95instruction sets during the assembly; see @ref{MIPS ISA, Directives to 96override the ISA level}. 97 98@item -mgp32 99@itemx -mfp32 100Some macros have different expansions for 32-bit and 64-bit registers. 101The register sizes are normally inferred from the ISA and ABI, but these 102flags force a certain group of registers to be treated as 32 bits wide at 103all times. @samp{-mgp32} controls the size of general-purpose registers 104and @samp{-mfp32} controls the size of floating-point registers. 105 106The @code{.set gp=32} and @code{.set fp=32} directives allow the size 107of registers to be changed for parts of an object. The default value is 108restored by @code{.set gp=default} and @code{.set fp=default}. 109 110On some MIPS variants there is a 32-bit mode flag; when this flag is 111set, 64-bit instructions generate a trap. Also, some 32-bit OSes only 112save the 32-bit registers on a context switch, so it is essential never 113to use the 64-bit registers. 114 115@item -mgp64 116@itemx -mfp64 117Assume that 64-bit registers are available. This is provided in the 118interests of symmetry with @samp{-mgp32} and @samp{-mfp32}. 119 120The @code{.set gp=64} and @code{.set fp=64} directives allow the size 121of registers to be changed for parts of an object. The default value is 122restored by @code{.set gp=default} and @code{.set fp=default}. 123 124@item -mips16 125@itemx -no-mips16 126Generate code for the MIPS 16 processor. This is equivalent to putting 127@code{.set mips16} at the start of the assembly file. @samp{-no-mips16} 128turns off this option. 129 130@item -msmartmips 131@itemx -mno-smartmips 132Enables the SmartMIPS extensions to the MIPS32 instruction set, which 133provides a number of new instructions which target smartcard and 134cryptographic applications. This is equivalent to putting 135@code{.set smartmips} at the start of the assembly file. 136@samp{-mno-smartmips} turns off this option. 137 138@item -mips3d 139@itemx -no-mips3d 140Generate code for the MIPS-3D Application Specific Extension. 141This tells the assembler to accept MIPS-3D instructions. 142@samp{-no-mips3d} turns off this option. 143 144@item -mdmx 145@itemx -no-mdmx 146Generate code for the MDMX Application Specific Extension. 147This tells the assembler to accept MDMX instructions. 148@samp{-no-mdmx} turns off this option. 149 150@item -mdsp 151@itemx -mno-dsp 152Generate code for the DSP Release 1 Application Specific Extension. 153This tells the assembler to accept DSP Release 1 instructions. 154@samp{-mno-dsp} turns off this option. 155 156@item -mdspr2 157@itemx -mno-dspr2 158Generate code for the DSP Release 2 Application Specific Extension. 159This option implies -mdsp. 160This tells the assembler to accept DSP Release 2 instructions. 161@samp{-mno-dspr2} turns off this option. 162 163@item -mmt 164@itemx -mno-mt 165Generate code for the MT Application Specific Extension. 166This tells the assembler to accept MT instructions. 167@samp{-mno-mt} turns off this option. 168 169@item -mfix7000 170@itemx -mno-fix7000 171Cause nops to be inserted if the read of the destination register 172of an mfhi or mflo instruction occurs in the following two instructions. 173 174@item -mfix-vr4120 175@itemx -no-mfix-vr4120 176Insert nops to work around certain VR4120 errata. This option is 177intended to be used on GCC-generated code: it is not designed to catch 178all problems in hand-written assembler code. 179 180@item -mfix-vr4130 181@itemx -no-mfix-vr4130 182Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. 183 184@item -m4010 185@itemx -no-m4010 186Generate code for the LSI @sc{r4010} chip. This tells the assembler to 187accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, 188etc.), and to not schedule @samp{nop} instructions around accesses to 189the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this 190option. 191 192@item -m4650 193@itemx -no-m4650 194Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept 195the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} 196instructions around accesses to the @samp{HI} and @samp{LO} registers. 197@samp{-no-m4650} turns off this option. 198 199@itemx -m3900 200@itemx -no-m3900 201@itemx -m4100 202@itemx -no-m4100 203For each option @samp{-m@var{nnnn}}, generate code for the MIPS 204@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions 205specific to that chip, and to schedule for that chip's hazards. 206 207@item -march=@var{cpu} 208Generate code for a particular MIPS cpu. It is exactly equivalent to 209@samp{-m@var{cpu}}, except that there are more value of @var{cpu} 210understood. Valid @var{cpu} value are: 211 212@quotation 2132000, 2143000, 2153900, 2164000, 2174010, 2184100, 2194111, 220vr4120, 221vr4130, 222vr4181, 2234300, 2244400, 2254600, 2264650, 2275000, 228rm5200, 229rm5230, 230rm5231, 231rm5261, 232rm5721, 233vr5400, 234vr5500, 2356000, 236rm7000, 2378000, 238rm9000, 23910000, 24012000, 2414kc, 2424km, 2434kp, 2444ksc, 2454kec, 2464kem, 2474kep, 2484ksd, 249m4k, 250m4kp, 25124kc, 25224kf, 25324kx, 25424kec, 25524kef, 25624kex, 25734kc, 25834kf, 25934kx, 26074kc, 26174kf, 26274kx, 2635kc, 2645kf, 26520kc, 26625kf, 267sb1, 268sb1a 269@end quotation 270 271@item -mtune=@var{cpu} 272Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are 273identical to @samp{-march=@var{cpu}}. 274 275@item -mabi=@var{abi} 276Record which ABI the source code uses. The recognized arguments 277are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. 278 279@item -msym32 280@itemx -mno-sym32 281@cindex -msym32 282@cindex -mno-sym32 283Equivalent to adding @code{.set sym32} or @code{.set nosym32} to 284the beginning of the assembler input. @xref{MIPS symbol sizes}. 285 286@cindex @code{-nocpp} ignored (MIPS) 287@item -nocpp 288This option is ignored. It is accepted for command-line compatibility with 289other assemblers, which use it to turn off C style preprocessing. With 290@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the 291@sc{gnu} assembler itself never runs the C preprocessor. 292 293@item --construct-floats 294@itemx --no-construct-floats 295@cindex --construct-floats 296@cindex --no-construct-floats 297The @code{--no-construct-floats} option disables the construction of 298double width floating point constants by loading the two halves of the 299value into the two single width floating point registers that make up 300the double width register. This feature is useful if the processor 301support the FR bit in its status register, and this bit is known (by 302the programmer) to be set. This bit prevents the aliasing of the double 303width register by the single width registers. 304 305By default @code{--construct-floats} is selected, allowing construction 306of these floating point constants. 307 308@item --trap 309@itemx --no-break 310@c FIXME! (1) reflect these options (next item too) in option summaries; 311@c (2) stop teasing, say _which_ instructions expanded _how_. 312@code{@value{AS}} automatically macro expands certain division and 313multiplication instructions to check for overflow and division by zero. This 314option causes @code{@value{AS}} to generate code to take a trap exception 315rather than a break exception when an error is detected. The trap instructions 316are only supported at Instruction Set Architecture level 2 and higher. 317 318@item --break 319@itemx --no-trap 320Generate code to take a break exception rather than a trap exception when an 321error is detected. This is the default. 322 323@item -mpdr 324@itemx -mno-pdr 325Control generation of @code{.pdr} sections. Off by default on IRIX, on 326elsewhere. 327 328@item -mshared 329@itemx -mno-shared 330When generating code using the Unix calling conventions (selected by 331@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code 332which can go into a shared library. The @samp{-mno-shared} option 333tells gas to generate code which uses the calling convention, but can 334not go into a shared library. The resulting code is slightly more 335efficient. This option only affects the handling of the 336@samp{.cpload} and @samp{.cpsetup} pseudo-ops. 337@end table 338 339@node MIPS Object 340@section MIPS ECOFF object code 341 342@cindex ECOFF sections 343@cindex MIPS ECOFF sections 344Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections 345besides the usual @code{.text}, @code{.data} and @code{.bss}. The 346additional sections are @code{.rdata}, used for read-only data, 347@code{.sdata}, used for small data, and @code{.sbss}, used for small 348common objects. 349 350@cindex small objects, MIPS ECOFF 351@cindex @code{gp} register, MIPS 352When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) 353register to form the address of a ``small object''. Any object in the 354@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. 355For external objects, or for objects in the @code{.bss} section, you can use 356the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via 357@code{$gp}; the default value is 8, meaning that a reference to any object 358eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to 359@code{@value{AS}} prevents it from using the @code{$gp} register on the basis 360of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} 361or @code{sbss} in any case). The size of an object in the @code{.bss} section 362is set by the @code{.comm} or @code{.lcomm} directive that defines it. The 363size of an external object may be set with the @code{.extern} directive. For 364example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes 365in length, whie leaving @code{sym} otherwise undefined. 366 367Using small @sc{ecoff} objects requires linker support, and assumes that the 368@code{$gp} register is correctly initialized (normally done automatically by 369the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the 370@code{$gp} register. 371 372@node MIPS Stabs 373@section Directives for debugging information 374 375@cindex MIPS debugging directives 376@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for 377generating debugging information which are not support by traditional @sc{mips} 378assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, 379@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, 380@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information 381generated by the three @code{.stab} directives can only be read by @sc{gdb}, 382not by traditional @sc{mips} debuggers (this enhancement is required to fully 383support C++ debugging). These directives are primarily used by compilers, not 384assembly language programmers! 385 386@node MIPS symbol sizes 387@section Directives to override the size of symbols 388 389@cindex @code{.set sym32} 390@cindex @code{.set nosym32} 391The n64 ABI allows symbols to have any 64-bit value. Although this 392provides a great deal of flexibility, it means that some macros have 393much longer expansions than their 32-bit counterparts. For example, 394the non-PIC expansion of @samp{dla $4,sym} is usually: 395 396@smallexample 397lui $4,%highest(sym) 398lui $1,%hi(sym) 399daddiu $4,$4,%higher(sym) 400daddiu $1,$1,%lo(sym) 401dsll32 $4,$4,0 402daddu $4,$4,$1 403@end smallexample 404 405whereas the 32-bit expansion is simply: 406 407@smallexample 408lui $4,%hi(sym) 409daddiu $4,$4,%lo(sym) 410@end smallexample 411 412n64 code is sometimes constructed in such a way that all symbolic 413constants are known to have 32-bit values, and in such cases, it's 414preferable to use the 32-bit expansion instead of the 64-bit 415expansion. 416 417You can use the @code{.set sym32} directive to tell the assembler 418that, from this point on, all expressions of the form 419@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} 420have 32-bit values. For example: 421 422@smallexample 423.set sym32 424dla $4,sym 425lw $4,sym+16 426sw $4,sym+0x8000($4) 427@end smallexample 428 429will cause the assembler to treat @samp{sym}, @code{sym+16} and 430@code{sym+0x8000} as 32-bit values. The handling of non-symbolic 431addresses is not affected. 432 433The directive @code{.set nosym32} ends a @code{.set sym32} block and 434reverts to the normal behavior. It is also possible to change the 435symbol size using the command-line options @option{-msym32} and 436@option{-mno-sym32}. 437 438These options and directives are always accepted, but at present, 439they have no effect for anything other than n64. 440 441@node MIPS ISA 442@section Directives to override the ISA level 443 444@cindex MIPS ISA override 445@kindex @code{.set mips@var{n}} 446@sc{gnu} @code{@value{AS}} supports an additional directive to change 447the @sc{mips} Instruction Set Architecture level on the fly: @code{.set 448mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 449or 64r2. 450The values other than 0 make the assembler accept instructions 451for the corresponding @sc{isa} level, from that point on in the 452assembly. @code{.set mips@var{n}} affects not only which instructions 453are permitted, but also how certain macros are expanded. @code{.set 454mips0} restores the @sc{isa} level to its original level: either the 455level you selected with command line options, or the default for your 456configuration. You can use this feature to permit specific @sc{mips3} 457instructions while assembling in 32 bit mode. Use this directive with 458care! 459 460@cindex MIPS CPU override 461@kindex @code{.set arch=@var{cpu}} 462The @code{.set arch=@var{cpu}} directive provides even finer control. 463It changes the effective CPU target and allows the assembler to use 464instructions specific to a particular CPU. All CPUs supported by the 465@samp{-march} command line option are also selectable by this directive. 466The original value is restored by @code{.set arch=default}. 467 468The directive @code{.set mips16} puts the assembler into MIPS 16 mode, 469in which it will assemble instructions for the MIPS 16 processor. Use 470@code{.set nomips16} to return to normal 32 bit mode. 471 472Traditional @sc{mips} assemblers do not support this directive. 473 474@node MIPS autoextend 475@section Directives for extending MIPS 16 bit instructions 476 477@kindex @code{.set autoextend} 478@kindex @code{.set noautoextend} 479By default, MIPS 16 instructions are automatically extended to 32 bits 480when necessary. The directive @code{.set noautoextend} will turn this 481off. When @code{.set noautoextend} is in effect, any 32 bit instruction 482must be explicitly extended with the @code{.e} modifier (e.g., 483@code{li.e $4,1000}). The directive @code{.set autoextend} may be used 484to once again automatically extend instructions when necessary. 485 486This directive is only meaningful when in MIPS 16 mode. Traditional 487@sc{mips} assemblers do not support this directive. 488 489@node MIPS insn 490@section Directive to mark data as an instruction 491 492@kindex @code{.insn} 493The @code{.insn} directive tells @code{@value{AS}} that the following 494data is actually instructions. This makes a difference in MIPS 16 mode: 495when loading the address of a label which precedes instructions, 496@code{@value{AS}} automatically adds 1 to the value, so that jumping to 497the loaded address will do the right thing. 498 499@node MIPS option stack 500@section Directives to save and restore options 501 502@cindex MIPS option stack 503@kindex @code{.set push} 504@kindex @code{.set pop} 505The directives @code{.set push} and @code{.set pop} may be used to save 506and restore the current settings for all the options which are 507controlled by @code{.set}. The @code{.set push} directive saves the 508current settings on a stack. The @code{.set pop} directive pops the 509stack and restores the settings. 510 511These directives can be useful inside an macro which must change an 512option such as the ISA level or instruction reordering but does not want 513to change the state of the code which invoked the macro. 514 515Traditional @sc{mips} assemblers do not support these directives. 516 517@node MIPS ASE instruction generation overrides 518@section Directives to control generation of MIPS ASE instructions 519 520@cindex MIPS MIPS-3D instruction generation override 521@kindex @code{.set mips3d} 522@kindex @code{.set nomips3d} 523The directive @code{.set mips3d} makes the assembler accept instructions 524from the MIPS-3D Application Specific Extension from that point on 525in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D 526instructions from being accepted. 527 528@cindex SmartMIPS instruction generation override 529@kindex @code{.set smartmips} 530@kindex @code{.set nosmartmips} 531The directive @code{.set smartmips} makes the assembler accept 532instructions from the SmartMIPS Application Specific Extension to the 533MIPS32 @sc{isa} from that point on in the assembly. The 534@code{.set nosmartmips} directive prevents SmartMIPS instructions from 535being accepted. 536 537@cindex MIPS MDMX instruction generation override 538@kindex @code{.set mdmx} 539@kindex @code{.set nomdmx} 540The directive @code{.set mdmx} makes the assembler accept instructions 541from the MDMX Application Specific Extension from that point on 542in the assembly. The @code{.set nomdmx} directive prevents MDMX 543instructions from being accepted. 544 545@cindex MIPS DSP Release 1 instruction generation override 546@kindex @code{.set dsp} 547@kindex @code{.set nodsp} 548The directive @code{.set dsp} makes the assembler accept instructions 549from the DSP Release 1 Application Specific Extension from that point 550on in the assembly. The @code{.set nodsp} directive prevents DSP 551Release 1 instructions from being accepted. 552 553@cindex MIPS DSP Release 2 instruction generation override 554@kindex @code{.set dspr2} 555@kindex @code{.set nodspr2} 556The directive @code{.set dspr2} makes the assembler accept instructions 557from the DSP Release 2 Application Specific Extension from that point 558on in the assembly. This dirctive implies @code{.set dsp}. The 559@code{.set nodspr2} directive prevents DSP Release 2 instructions from 560being accepted. 561 562@cindex MIPS MT instruction generation override 563@kindex @code{.set mt} 564@kindex @code{.set nomt} 565The directive @code{.set mt} makes the assembler accept instructions 566from the MT Application Specific Extension from that point on 567in the assembly. The @code{.set nomt} directive prevents MT 568instructions from being accepted. 569 570Traditional @sc{mips} assemblers do not support these directives. 571