1/* 2 * Copyright (C) 2005, 2007 Internet Systems Consortium, Inc. ("ISC") 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL ISC BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE 13 * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17/* $Id: atomic.h,v 1.3 2007/06/19 23:47:18 tbox Exp $ */ 18 19#ifndef ISC_ATOMIC_H 20#define ISC_ATOMIC_H 1 21 22#include <isc/platform.h> 23#include <isc/types.h> 24 25#ifdef ISC_PLATFORM_USEGCCASM 26/* 27 * This routine atomically increments the value stored in 'p' by 'val', and 28 * returns the previous value. 29 */ 30static inline isc_int32_t 31isc_atomic_xadd(isc_int32_t *p, int val) { 32 isc_int32_t orig; 33 34 /* add is a cheat, since MIPS has no mov instruction */ 35 __asm__ volatile ( 36 "1:" 37 "ll $3, %1\n" 38 "add %0, $0, $3\n" 39 "add $3, $3, %2\n" 40 "sc $3, %1\n" 41 "beq $3, 0, 1b" 42 : "=&r"(orig) 43 : "m"(*p), "r"(val) 44 : "memory", "$3" 45 ); 46 47 return (orig); 48} 49 50/* 51 * This routine atomically stores the value 'val' in 'p'. 52 */ 53static inline void 54isc_atomic_store(isc_int32_t *p, isc_int32_t val) { 55 __asm__ volatile ( 56 "1:" 57 "ll $3, %0\n" 58 "add $3, $0, %1\n" 59 "sc $3, %0\n" 60 "beq $3, 0, 1b" 61 : 62 : "m"(*p), "r"(val) 63 : "memory", "$3" 64 ); 65} 66 67/* 68 * This routine atomically replaces the value in 'p' with 'val', if the 69 * original value is equal to 'cmpval'. The original value is returned in any 70 * case. 71 */ 72static inline isc_int32_t 73isc_atomic_cmpxchg(isc_int32_t *p, int cmpval, int val) { 74 isc_int32_t orig; 75 76 __asm__ volatile( 77 "1:" 78 "ll $3, %1\n" 79 "add %0, $0, $3\n" 80 "bne $3, %2, 2f\n" 81 "add $3, $0, %3\n" 82 "sc $3, %1\n" 83 "beq $3, 0, 1b\n" 84 "2:" 85 : "=&r"(orig) 86 : "m"(*p), "r"(cmpval), "r"(val) 87 : "memory", "$3" 88 ); 89 90 return (orig); 91} 92 93#else /* !ISC_PLATFORM_USEGCCASM */ 94 95#error "unsupported compiler. disable atomic ops by --disable-atomic" 96 97#endif 98#endif /* ISC_ATOMIC_H */ 99