1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31#ifndef _PCI_EMUL_H_ 32#define _PCI_EMUL_H_ 33 34#include <sys/types.h> 35#include <sys/queue.h> 36#include <sys/kernel.h> 37#include <sys/_pthreadtypes.h> 38 39#include <dev/pci/pcireg.h> 40 41#include <assert.h> 42 43#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 44 45struct vmctx; 46struct pci_devinst; 47struct memory_region; 48struct vm_snapshot_meta; 49 50struct pci_devemu { 51 char *pe_emu; /* Name of device emulation */ 52 53 /* instance creation */ 54 int (*pe_init)(struct vmctx *, struct pci_devinst *, 55 char *opts); 56 57 /* ACPI DSDT enumeration */ 58 void (*pe_write_dsdt)(struct pci_devinst *); 59 60 /* config space read/write callbacks */ 61 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu, 62 struct pci_devinst *pi, int offset, 63 int bytes, uint32_t val); 64 int (*pe_cfgread)(struct vmctx *ctx, int vcpu, 65 struct pci_devinst *pi, int offset, 66 int bytes, uint32_t *retval); 67 68 /* BAR read/write callbacks */ 69 void (*pe_barwrite)(struct vmctx *ctx, int vcpu, 70 struct pci_devinst *pi, int baridx, 71 uint64_t offset, int size, uint64_t value); 72 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, 73 struct pci_devinst *pi, int baridx, 74 uint64_t offset, int size); 75 76 void (*pe_baraddr)(struct vmctx *ctx, struct pci_devinst *pi, 77 int baridx, int enabled, uint64_t address); 78 79 /* Save/restore device state */ 80 int (*pe_snapshot)(struct vm_snapshot_meta *meta); 81 int (*pe_pause)(struct vmctx *ctx, struct pci_devinst *pi); 82 int (*pe_resume)(struct vmctx *ctx, struct pci_devinst *pi); 83}; 84#define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); 85 86enum pcibar_type { 87 PCIBAR_NONE, 88 PCIBAR_IO, 89 PCIBAR_MEM32, 90 PCIBAR_MEM64, 91 PCIBAR_MEMHI64 92}; 93 94struct pcibar { 95 enum pcibar_type type; /* io or memory */ 96 uint64_t size; 97 uint64_t addr; 98}; 99 100#define PI_NAMESZ 40 101 102struct msix_table_entry { 103 uint64_t addr; 104 uint32_t msg_data; 105 uint32_t vector_control; 106} __packed; 107 108/* 109 * In case the structure is modified to hold extra information, use a define 110 * for the size that should be emulated. 111 */ 112#define MSIX_TABLE_ENTRY_SIZE 16 113#define MAX_MSIX_TABLE_ENTRIES 2048 114#define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8) 115 116enum lintr_stat { 117 IDLE, 118 ASSERTED, 119 PENDING 120}; 121 122struct pci_devinst { 123 struct pci_devemu *pi_d; 124 struct vmctx *pi_vmctx; 125 uint8_t pi_bus, pi_slot, pi_func; 126 char pi_name[PI_NAMESZ]; 127 int pi_bar_getsize; 128 int pi_prevcap; 129 int pi_capend; 130 131 struct { 132 int8_t pin; 133 enum lintr_stat state; 134 int pirq_pin; 135 int ioapic_irq; 136 pthread_mutex_t lock; 137 } pi_lintr; 138 139 struct { 140 int enabled; 141 uint64_t addr; 142 uint64_t msg_data; 143 int maxmsgnum; 144 } pi_msi; 145 146 struct { 147 int enabled; 148 int table_bar; 149 int pba_bar; 150 uint32_t table_offset; 151 int table_count; 152 uint32_t pba_offset; 153 int pba_size; 154 int function_mask; 155 struct msix_table_entry *table; /* allocated at runtime */ 156 void *pba_page; 157 int pba_page_offset; 158 } pi_msix; 159 160 void *pi_arg; /* devemu-private data */ 161 162 u_char pi_cfgdata[PCI_REGMAX + 1]; 163 struct pcibar pi_bar[PCI_BARMAX + 1]; 164}; 165 166struct msicap { 167 uint8_t capid; 168 uint8_t nextptr; 169 uint16_t msgctrl; 170 uint32_t addrlo; 171 uint32_t addrhi; 172 uint16_t msgdata; 173} __packed; 174static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed"); 175 176struct msixcap { 177 uint8_t capid; 178 uint8_t nextptr; 179 uint16_t msgctrl; 180 uint32_t table_info; /* bar index and offset within it */ 181 uint32_t pba_info; /* bar index and offset within it */ 182} __packed; 183static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed"); 184 185struct pciecap { 186 uint8_t capid; 187 uint8_t nextptr; 188 uint16_t pcie_capabilities; 189 190 uint32_t dev_capabilities; /* all devices */ 191 uint16_t dev_control; 192 uint16_t dev_status; 193 194 uint32_t link_capabilities; /* devices with links */ 195 uint16_t link_control; 196 uint16_t link_status; 197 198 uint32_t slot_capabilities; /* ports with slots */ 199 uint16_t slot_control; 200 uint16_t slot_status; 201 202 uint16_t root_control; /* root ports */ 203 uint16_t root_capabilities; 204 uint32_t root_status; 205 206 uint32_t dev_capabilities2; /* all devices */ 207 uint16_t dev_control2; 208 uint16_t dev_status2; 209 210 uint32_t link_capabilities2; /* devices with links */ 211 uint16_t link_control2; 212 uint16_t link_status2; 213 214 uint32_t slot_capabilities2; /* ports with slots */ 215 uint16_t slot_control2; 216 uint16_t slot_status2; 217} __packed; 218static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed"); 219 220typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin, 221 int ioapic_irq, void *arg); 222 223int init_pci(struct vmctx *ctx); 224void pci_callback(void); 225int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 226 enum pcibar_type type, uint64_t size); 227int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 228int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 229void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, 230 uint32_t val, uint8_t capoff, int capid); 231void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old); 232void pci_generate_msi(struct pci_devinst *pi, int msgnum); 233void pci_generate_msix(struct pci_devinst *pi, int msgnum); 234void pci_lintr_assert(struct pci_devinst *pi); 235void pci_lintr_deassert(struct pci_devinst *pi); 236void pci_lintr_request(struct pci_devinst *pi); 237int pci_msi_enabled(struct pci_devinst *pi); 238int pci_msix_enabled(struct pci_devinst *pi); 239int pci_msix_table_bar(struct pci_devinst *pi); 240int pci_msix_pba_bar(struct pci_devinst *pi); 241int pci_msi_maxmsgnum(struct pci_devinst *pi); 242int pci_parse_slot(char *opt); 243void pci_print_supported_devices(); 244void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 245int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 246int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 247 uint64_t value); 248uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 249int pci_count_lintr(int bus); 250void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg); 251void pci_write_dsdt(void); 252uint64_t pci_ecfg_base(void); 253int pci_bus_configured(int bus); 254#ifdef BHYVE_SNAPSHOT 255int pci_snapshot(struct vm_snapshot_meta *meta); 256int pci_pause(struct vmctx *ctx, const char *dev_name); 257int pci_resume(struct vmctx *ctx, const char *dev_name); 258#endif 259 260static __inline void 261pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 262{ 263 assert(offset <= PCI_REGMAX); 264 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 265} 266 267static __inline void 268pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 269{ 270 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 271 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 272} 273 274static __inline void 275pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 276{ 277 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 278 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 279} 280 281static __inline uint8_t 282pci_get_cfgdata8(struct pci_devinst *pi, int offset) 283{ 284 assert(offset <= PCI_REGMAX); 285 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 286} 287 288static __inline uint16_t 289pci_get_cfgdata16(struct pci_devinst *pi, int offset) 290{ 291 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 292 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 293} 294 295static __inline uint32_t 296pci_get_cfgdata32(struct pci_devinst *pi, int offset) 297{ 298 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 299 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 300} 301 302#endif /* _PCI_EMUL_H_ */ 303