1/****************************************************************************** 2 * include/public/trace.h 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to 6 * deal in the Software without restriction, including without limitation the 7 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 8 * sell copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 * 22 * Mark Williamson, (C) 2004 Intel Research Cambridge 23 * Copyright (C) 2005 Bin Ren 24 */ 25 26#ifndef __XEN_PUBLIC_TRACE_H__ 27#define __XEN_PUBLIC_TRACE_H__ 28 29#define TRACE_EXTRA_MAX 7 30#define TRACE_EXTRA_SHIFT 28 31 32/* Trace classes */ 33#define TRC_CLS_SHIFT 16 34#define TRC_GEN 0x0001f000 /* General trace */ 35#define TRC_SCHED 0x0002f000 /* Xen Scheduler trace */ 36#define TRC_DOM0OP 0x0004f000 /* Xen DOM0 operation trace */ 37#define TRC_HVM 0x0008f000 /* Xen HVM trace */ 38#define TRC_MEM 0x0010f000 /* Xen memory trace */ 39#define TRC_PV 0x0020f000 /* Xen PV traces */ 40#define TRC_SHADOW 0x0040f000 /* Xen shadow tracing */ 41#define TRC_HW 0x0080f000 /* Xen hardware-related traces */ 42#define TRC_GUEST 0x0800f000 /* Guest-generated traces */ 43#define TRC_ALL 0x0ffff000 44#define TRC_HD_TO_EVENT(x) ((x)&0x0fffffff) 45#define TRC_HD_CYCLE_FLAG (1UL<<31) 46#define TRC_HD_INCLUDES_CYCLE_COUNT(x) ( !!( (x) & TRC_HD_CYCLE_FLAG ) ) 47#define TRC_HD_EXTRA(x) (((x)>>TRACE_EXTRA_SHIFT)&TRACE_EXTRA_MAX) 48 49/* Trace subclasses */ 50#define TRC_SUBCLS_SHIFT 12 51 52/* trace subclasses for SVM */ 53#define TRC_HVM_ENTRYEXIT 0x00081000 /* VMENTRY and #VMEXIT */ 54#define TRC_HVM_HANDLER 0x00082000 /* various HVM handlers */ 55#define TRC_HVM_EMUL 0x00084000 /* emulated devices */ 56 57#define TRC_SCHED_MIN 0x00021000 /* Just runstate changes */ 58#define TRC_SCHED_CLASS 0x00022000 /* Scheduler-specific */ 59#define TRC_SCHED_VERBOSE 0x00028000 /* More inclusive scheduling */ 60 61/* 62 * The highest 3 bits of the last 12 bits of TRC_SCHED_CLASS above are 63 * reserved for encoding what scheduler produced the information. The 64 * actual event is encoded in the last 9 bits. 65 * 66 * This means we have 8 scheduling IDs available (which means at most 8 67 * schedulers generating events) and, in each scheduler, up to 512 68 * different events. 69 */ 70#define TRC_SCHED_ID_BITS 3 71#define TRC_SCHED_ID_SHIFT (TRC_SUBCLS_SHIFT - TRC_SCHED_ID_BITS) 72#define TRC_SCHED_ID_MASK (((1UL<<TRC_SCHED_ID_BITS) - 1) << TRC_SCHED_ID_SHIFT) 73#define TRC_SCHED_EVT_MASK (~(TRC_SCHED_ID_MASK)) 74 75/* Per-scheduler IDs, to identify scheduler specific events */ 76#define TRC_SCHED_CSCHED 0 77#define TRC_SCHED_CSCHED2 1 78/* #define XEN_SCHEDULER_SEDF 2 (Removed) */ 79#define TRC_SCHED_ARINC653 3 80#define TRC_SCHED_RTDS 4 81#define TRC_SCHED_SNULL 5 82 83/* Per-scheduler tracing */ 84#define TRC_SCHED_CLASS_EVT(_c, _e) \ 85 ( ( TRC_SCHED_CLASS | \ 86 ((TRC_SCHED_##_c << TRC_SCHED_ID_SHIFT) & TRC_SCHED_ID_MASK) ) + \ 87 (_e & TRC_SCHED_EVT_MASK) ) 88 89/* Trace classes for DOM0 operations */ 90#define TRC_DOM0_DOMOPS 0x00041000 /* Domains manipulations */ 91 92/* Trace classes for Hardware */ 93#define TRC_HW_PM 0x00801000 /* Power management traces */ 94#define TRC_HW_IRQ 0x00802000 /* Traces relating to the handling of IRQs */ 95 96/* Trace events per class */ 97#define TRC_LOST_RECORDS (TRC_GEN + 1) 98#define TRC_TRACE_WRAP_BUFFER (TRC_GEN + 2) 99#define TRC_TRACE_CPU_CHANGE (TRC_GEN + 3) 100 101#define TRC_SCHED_RUNSTATE_CHANGE (TRC_SCHED_MIN + 1) 102#define TRC_SCHED_CONTINUE_RUNNING (TRC_SCHED_MIN + 2) 103#define TRC_SCHED_DOM_ADD (TRC_SCHED_VERBOSE + 1) 104#define TRC_SCHED_DOM_REM (TRC_SCHED_VERBOSE + 2) 105#define TRC_SCHED_SLEEP (TRC_SCHED_VERBOSE + 3) 106#define TRC_SCHED_WAKE (TRC_SCHED_VERBOSE + 4) 107#define TRC_SCHED_YIELD (TRC_SCHED_VERBOSE + 5) 108#define TRC_SCHED_BLOCK (TRC_SCHED_VERBOSE + 6) 109#define TRC_SCHED_SHUTDOWN (TRC_SCHED_VERBOSE + 7) 110#define TRC_SCHED_CTL (TRC_SCHED_VERBOSE + 8) 111#define TRC_SCHED_ADJDOM (TRC_SCHED_VERBOSE + 9) 112#define TRC_SCHED_SWITCH (TRC_SCHED_VERBOSE + 10) 113#define TRC_SCHED_S_TIMER_FN (TRC_SCHED_VERBOSE + 11) 114#define TRC_SCHED_T_TIMER_FN (TRC_SCHED_VERBOSE + 12) 115#define TRC_SCHED_DOM_TIMER_FN (TRC_SCHED_VERBOSE + 13) 116#define TRC_SCHED_SWITCH_INFPREV (TRC_SCHED_VERBOSE + 14) 117#define TRC_SCHED_SWITCH_INFNEXT (TRC_SCHED_VERBOSE + 15) 118#define TRC_SCHED_SHUTDOWN_CODE (TRC_SCHED_VERBOSE + 16) 119#define TRC_SCHED_SWITCH_INFCONT (TRC_SCHED_VERBOSE + 17) 120 121#define TRC_DOM0_DOM_ADD (TRC_DOM0_DOMOPS + 1) 122#define TRC_DOM0_DOM_REM (TRC_DOM0_DOMOPS + 2) 123 124#define TRC_MEM_PAGE_GRANT_MAP (TRC_MEM + 1) 125#define TRC_MEM_PAGE_GRANT_UNMAP (TRC_MEM + 2) 126#define TRC_MEM_PAGE_GRANT_TRANSFER (TRC_MEM + 3) 127#define TRC_MEM_SET_P2M_ENTRY (TRC_MEM + 4) 128#define TRC_MEM_DECREASE_RESERVATION (TRC_MEM + 5) 129#define TRC_MEM_POD_POPULATE (TRC_MEM + 16) 130#define TRC_MEM_POD_ZERO_RECLAIM (TRC_MEM + 17) 131#define TRC_MEM_POD_SUPERPAGE_SPLINTER (TRC_MEM + 18) 132 133#define TRC_PV_ENTRY 0x00201000 /* Hypervisor entry points for PV guests. */ 134#define TRC_PV_SUBCALL 0x00202000 /* Sub-call in a multicall hypercall */ 135 136#define TRC_PV_HYPERCALL (TRC_PV_ENTRY + 1) 137#define TRC_PV_TRAP (TRC_PV_ENTRY + 3) 138#define TRC_PV_PAGE_FAULT (TRC_PV_ENTRY + 4) 139#define TRC_PV_FORCED_INVALID_OP (TRC_PV_ENTRY + 5) 140#define TRC_PV_EMULATE_PRIVOP (TRC_PV_ENTRY + 6) 141#define TRC_PV_EMULATE_4GB (TRC_PV_ENTRY + 7) 142#define TRC_PV_MATH_STATE_RESTORE (TRC_PV_ENTRY + 8) 143#define TRC_PV_PAGING_FIXUP (TRC_PV_ENTRY + 9) 144#define TRC_PV_GDT_LDT_MAPPING_FAULT (TRC_PV_ENTRY + 10) 145#define TRC_PV_PTWR_EMULATION (TRC_PV_ENTRY + 11) 146#define TRC_PV_PTWR_EMULATION_PAE (TRC_PV_ENTRY + 12) 147#define TRC_PV_HYPERCALL_V2 (TRC_PV_ENTRY + 13) 148#define TRC_PV_HYPERCALL_SUBCALL (TRC_PV_SUBCALL + 14) 149 150/* 151 * TRC_PV_HYPERCALL_V2 format 152 * 153 * Only some of the hypercall argument are recorded. Bit fields A0 to 154 * A5 in the first extra word are set if the argument is present and 155 * the arguments themselves are packed sequentially in the following 156 * words. 157 * 158 * The TRC_64_FLAG bit is not set for these events (even if there are 159 * 64-bit arguments in the record). 160 * 161 * Word 162 * 0 bit 31 30|29 28|27 26|25 24|23 22|21 20|19 ... 0 163 * A5 |A4 |A3 |A2 |A1 |A0 |Hypercall op 164 * 1 First 32 bit (or low word of first 64 bit) arg in record 165 * 2 Second 32 bit (or high word of first 64 bit) arg in record 166 * ... 167 * 168 * A0-A5 bitfield values: 169 * 170 * 00b Argument not present 171 * 01b 32-bit argument present 172 * 10b 64-bit argument present 173 * 11b Reserved 174 */ 175#define TRC_PV_HYPERCALL_V2_ARG_32(i) (0x1 << (20 + 2*(i))) 176#define TRC_PV_HYPERCALL_V2_ARG_64(i) (0x2 << (20 + 2*(i))) 177#define TRC_PV_HYPERCALL_V2_ARG_MASK (0xfff00000) 178 179#define TRC_SHADOW_NOT_SHADOW (TRC_SHADOW + 1) 180#define TRC_SHADOW_FAST_PROPAGATE (TRC_SHADOW + 2) 181#define TRC_SHADOW_FAST_MMIO (TRC_SHADOW + 3) 182#define TRC_SHADOW_FALSE_FAST_PATH (TRC_SHADOW + 4) 183#define TRC_SHADOW_MMIO (TRC_SHADOW + 5) 184#define TRC_SHADOW_FIXUP (TRC_SHADOW + 6) 185#define TRC_SHADOW_DOMF_DYING (TRC_SHADOW + 7) 186#define TRC_SHADOW_EMULATE (TRC_SHADOW + 8) 187#define TRC_SHADOW_EMULATE_UNSHADOW_USER (TRC_SHADOW + 9) 188#define TRC_SHADOW_EMULATE_UNSHADOW_EVTINJ (TRC_SHADOW + 10) 189#define TRC_SHADOW_EMULATE_UNSHADOW_UNHANDLED (TRC_SHADOW + 11) 190#define TRC_SHADOW_WRMAP_BF (TRC_SHADOW + 12) 191#define TRC_SHADOW_PREALLOC_UNPIN (TRC_SHADOW + 13) 192#define TRC_SHADOW_RESYNC_FULL (TRC_SHADOW + 14) 193#define TRC_SHADOW_RESYNC_ONLY (TRC_SHADOW + 15) 194 195/* trace events per subclass */ 196#define TRC_HVM_NESTEDFLAG (0x400) 197#define TRC_HVM_VMENTRY (TRC_HVM_ENTRYEXIT + 0x01) 198#define TRC_HVM_VMEXIT (TRC_HVM_ENTRYEXIT + 0x02) 199#define TRC_HVM_VMEXIT64 (TRC_HVM_ENTRYEXIT + TRC_64_FLAG + 0x02) 200#define TRC_HVM_PF_XEN (TRC_HVM_HANDLER + 0x01) 201#define TRC_HVM_PF_XEN64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x01) 202#define TRC_HVM_PF_INJECT (TRC_HVM_HANDLER + 0x02) 203#define TRC_HVM_PF_INJECT64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x02) 204#define TRC_HVM_INJ_EXC (TRC_HVM_HANDLER + 0x03) 205#define TRC_HVM_INJ_VIRQ (TRC_HVM_HANDLER + 0x04) 206#define TRC_HVM_REINJ_VIRQ (TRC_HVM_HANDLER + 0x05) 207#define TRC_HVM_IO_READ (TRC_HVM_HANDLER + 0x06) 208#define TRC_HVM_IO_WRITE (TRC_HVM_HANDLER + 0x07) 209#define TRC_HVM_CR_READ (TRC_HVM_HANDLER + 0x08) 210#define TRC_HVM_CR_READ64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x08) 211#define TRC_HVM_CR_WRITE (TRC_HVM_HANDLER + 0x09) 212#define TRC_HVM_CR_WRITE64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x09) 213#define TRC_HVM_DR_READ (TRC_HVM_HANDLER + 0x0A) 214#define TRC_HVM_DR_WRITE (TRC_HVM_HANDLER + 0x0B) 215#define TRC_HVM_MSR_READ (TRC_HVM_HANDLER + 0x0C) 216#define TRC_HVM_MSR_WRITE (TRC_HVM_HANDLER + 0x0D) 217#define TRC_HVM_CPUID (TRC_HVM_HANDLER + 0x0E) 218#define TRC_HVM_INTR (TRC_HVM_HANDLER + 0x0F) 219#define TRC_HVM_NMI (TRC_HVM_HANDLER + 0x10) 220#define TRC_HVM_SMI (TRC_HVM_HANDLER + 0x11) 221#define TRC_HVM_VMMCALL (TRC_HVM_HANDLER + 0x12) 222#define TRC_HVM_HLT (TRC_HVM_HANDLER + 0x13) 223#define TRC_HVM_INVLPG (TRC_HVM_HANDLER + 0x14) 224#define TRC_HVM_INVLPG64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x14) 225#define TRC_HVM_MCE (TRC_HVM_HANDLER + 0x15) 226#define TRC_HVM_IOPORT_READ (TRC_HVM_HANDLER + 0x16) 227#define TRC_HVM_IOMEM_READ (TRC_HVM_HANDLER + 0x17) 228#define TRC_HVM_CLTS (TRC_HVM_HANDLER + 0x18) 229#define TRC_HVM_LMSW (TRC_HVM_HANDLER + 0x19) 230#define TRC_HVM_LMSW64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x19) 231#define TRC_HVM_RDTSC (TRC_HVM_HANDLER + 0x1a) 232#define TRC_HVM_INTR_WINDOW (TRC_HVM_HANDLER + 0x20) 233#define TRC_HVM_NPF (TRC_HVM_HANDLER + 0x21) 234#define TRC_HVM_REALMODE_EMULATE (TRC_HVM_HANDLER + 0x22) 235#define TRC_HVM_TRAP (TRC_HVM_HANDLER + 0x23) 236#define TRC_HVM_TRAP_DEBUG (TRC_HVM_HANDLER + 0x24) 237#define TRC_HVM_VLAPIC (TRC_HVM_HANDLER + 0x25) 238#define TRC_HVM_XCR_READ64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x26) 239#define TRC_HVM_XCR_WRITE64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x27) 240 241#define TRC_HVM_IOPORT_WRITE (TRC_HVM_HANDLER + 0x216) 242#define TRC_HVM_IOMEM_WRITE (TRC_HVM_HANDLER + 0x217) 243 244/* Trace events for emulated devices */ 245#define TRC_HVM_EMUL_HPET_START_TIMER (TRC_HVM_EMUL + 0x1) 246#define TRC_HVM_EMUL_PIT_START_TIMER (TRC_HVM_EMUL + 0x2) 247#define TRC_HVM_EMUL_RTC_START_TIMER (TRC_HVM_EMUL + 0x3) 248#define TRC_HVM_EMUL_LAPIC_START_TIMER (TRC_HVM_EMUL + 0x4) 249#define TRC_HVM_EMUL_HPET_STOP_TIMER (TRC_HVM_EMUL + 0x5) 250#define TRC_HVM_EMUL_PIT_STOP_TIMER (TRC_HVM_EMUL + 0x6) 251#define TRC_HVM_EMUL_RTC_STOP_TIMER (TRC_HVM_EMUL + 0x7) 252#define TRC_HVM_EMUL_LAPIC_STOP_TIMER (TRC_HVM_EMUL + 0x8) 253#define TRC_HVM_EMUL_PIT_TIMER_CB (TRC_HVM_EMUL + 0x9) 254#define TRC_HVM_EMUL_LAPIC_TIMER_CB (TRC_HVM_EMUL + 0xA) 255#define TRC_HVM_EMUL_PIC_INT_OUTPUT (TRC_HVM_EMUL + 0xB) 256#define TRC_HVM_EMUL_PIC_KICK (TRC_HVM_EMUL + 0xC) 257#define TRC_HVM_EMUL_PIC_INTACK (TRC_HVM_EMUL + 0xD) 258#define TRC_HVM_EMUL_PIC_POSEDGE (TRC_HVM_EMUL + 0xE) 259#define TRC_HVM_EMUL_PIC_NEGEDGE (TRC_HVM_EMUL + 0xF) 260#define TRC_HVM_EMUL_PIC_PEND_IRQ_CALL (TRC_HVM_EMUL + 0x10) 261#define TRC_HVM_EMUL_LAPIC_PIC_INTR (TRC_HVM_EMUL + 0x11) 262 263/* trace events for per class */ 264#define TRC_PM_FREQ_CHANGE (TRC_HW_PM + 0x01) 265#define TRC_PM_IDLE_ENTRY (TRC_HW_PM + 0x02) 266#define TRC_PM_IDLE_EXIT (TRC_HW_PM + 0x03) 267 268/* Trace events for IRQs */ 269#define TRC_HW_IRQ_MOVE_CLEANUP_DELAY (TRC_HW_IRQ + 0x1) 270#define TRC_HW_IRQ_MOVE_CLEANUP (TRC_HW_IRQ + 0x2) 271#define TRC_HW_IRQ_BIND_VECTOR (TRC_HW_IRQ + 0x3) 272#define TRC_HW_IRQ_CLEAR_VECTOR (TRC_HW_IRQ + 0x4) 273#define TRC_HW_IRQ_MOVE_FINISH (TRC_HW_IRQ + 0x5) 274#define TRC_HW_IRQ_ASSIGN_VECTOR (TRC_HW_IRQ + 0x6) 275#define TRC_HW_IRQ_UNMAPPED_VECTOR (TRC_HW_IRQ + 0x7) 276#define TRC_HW_IRQ_HANDLED (TRC_HW_IRQ + 0x8) 277 278/* 279 * Event Flags 280 * 281 * Some events (e.g, TRC_PV_TRAP and TRC_HVM_IOMEM_READ) have multiple 282 * record formats. These event flags distinguish between the 283 * different formats. 284 */ 285#define TRC_64_FLAG 0x100 /* Addresses are 64 bits (instead of 32 bits) */ 286 287/* This structure represents a single trace buffer record. */ 288struct t_rec { 289 uint32_t event:28; 290 uint32_t extra_u32:3; /* # entries in trailing extra_u32[] array */ 291 uint32_t cycles_included:1; /* u.cycles or u.no_cycles? */ 292 union { 293 struct { 294 uint32_t cycles_lo, cycles_hi; /* cycle counter timestamp */ 295 uint32_t extra_u32[7]; /* event data items */ 296 } cycles; 297 struct { 298 uint32_t extra_u32[7]; /* event data items */ 299 } nocycles; 300 } u; 301}; 302 303/* 304 * This structure contains the metadata for a single trace buffer. The head 305 * field, indexes into an array of struct t_rec's. 306 */ 307struct t_buf { 308 /* Assume the data buffer size is X. X is generally not a power of 2. 309 * CONS and PROD are incremented modulo (2*X): 310 * 0 <= cons < 2*X 311 * 0 <= prod < 2*X 312 * This is done because addition modulo X breaks at 2^32 when X is not a 313 * power of 2: 314 * (((2^32 - 1) % X) + 1) % X != (2^32) % X 315 */ 316 uint32_t cons; /* Offset of next item to be consumed by control tools. */ 317 uint32_t prod; /* Offset of next item to be produced by Xen. */ 318 /* Records follow immediately after the meta-data header. */ 319}; 320 321/* Structure used to pass MFNs to the trace buffers back to trace consumers. 322 * Offset is an offset into the mapped structure where the mfn list will be held. 323 * MFNs will be at ((unsigned long *)(t_info))+(t_info->cpu_offset[cpu]). 324 */ 325struct t_info { 326 uint16_t tbuf_size; /* Size in pages of each trace buffer */ 327 uint16_t mfn_offset[]; /* Offset within t_info structure of the page list per cpu */ 328 /* MFN lists immediately after the header */ 329}; 330 331#endif /* __XEN_PUBLIC_TRACE_H__ */ 332 333/* 334 * Local variables: 335 * mode: C 336 * c-file-style: "BSD" 337 * c-basic-offset: 4 338 * tab-width: 4 339 * indent-tabs-mode: nil 340 * End: 341 */ 342