1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD$"); 34 35#include "opt_acpi.h" 36#if defined(__amd64__) 37#define DEV_APIC 38#else 39#include "opt_apic.h" 40#endif 41#include "opt_ddb.h" 42 43#include <sys/param.h> 44#include <sys/bus.h> 45#include <sys/kernel.h> 46#include <sys/lock.h> 47#include <sys/malloc.h> 48#include <sys/memdesc.h> 49#include <sys/module.h> 50#include <sys/mutex.h> 51#include <sys/rman.h> 52#include <sys/rwlock.h> 53#include <sys/smp.h> 54#include <sys/taskqueue.h> 55#include <sys/tree.h> 56#include <sys/vmem.h> 57#include <vm/vm.h> 58#include <vm/vm_extern.h> 59#include <vm/vm_kern.h> 60#include <vm/vm_object.h> 61#include <vm/vm_page.h> 62#include <vm/vm_pager.h> 63#include <vm/vm_map.h> 64#include <contrib/dev/acpica/include/acpi.h> 65#include <contrib/dev/acpica/include/accommon.h> 66#include <dev/acpica/acpivar.h> 67#include <dev/pci/pcireg.h> 68#include <dev/pci/pcivar.h> 69#include <machine/bus.h> 70#include <machine/pci_cfgreg.h> 71#include <x86/include/busdma_impl.h> 72#include <dev/iommu/busdma_iommu.h> 73#include <x86/iommu/intel_reg.h> 74#include <x86/iommu/intel_dmar.h> 75 76#ifdef DEV_APIC 77#include "pcib_if.h" 78#include <machine/intr_machdep.h> 79#include <x86/apicreg.h> 80#include <x86/apicvar.h> 81#endif 82 83#define DMAR_FAULT_IRQ_RID 0 84#define DMAR_QI_IRQ_RID 1 85#define DMAR_REG_RID 2 86 87static devclass_t dmar_devclass; 88static device_t *dmar_devs; 89static int dmar_devcnt; 90 91typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *); 92 93static void 94dmar_iterate_tbl(dmar_iter_t iter, void *arg) 95{ 96 ACPI_TABLE_DMAR *dmartbl; 97 ACPI_DMAR_HEADER *dmarh; 98 char *ptr, *ptrend; 99 ACPI_STATUS status; 100 101 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 102 if (ACPI_FAILURE(status)) 103 return; 104 ptr = (char *)dmartbl + sizeof(*dmartbl); 105 ptrend = (char *)dmartbl + dmartbl->Header.Length; 106 for (;;) { 107 if (ptr >= ptrend) 108 break; 109 dmarh = (ACPI_DMAR_HEADER *)ptr; 110 if (dmarh->Length <= 0) { 111 printf("dmar_identify: corrupted DMAR table, l %d\n", 112 dmarh->Length); 113 break; 114 } 115 ptr += dmarh->Length; 116 if (!iter(dmarh, arg)) 117 break; 118 } 119 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 120} 121 122struct find_iter_args { 123 int i; 124 ACPI_DMAR_HARDWARE_UNIT *res; 125}; 126 127static int 128dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 129{ 130 struct find_iter_args *fia; 131 132 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) 133 return (1); 134 135 fia = arg; 136 if (fia->i == 0) { 137 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; 138 return (0); 139 } 140 fia->i--; 141 return (1); 142} 143 144static ACPI_DMAR_HARDWARE_UNIT * 145dmar_find_by_index(int idx) 146{ 147 struct find_iter_args fia; 148 149 fia.i = idx; 150 fia.res = NULL; 151 dmar_iterate_tbl(dmar_find_iter, &fia); 152 return (fia.res); 153} 154 155static int 156dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 157{ 158 159 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) 160 dmar_devcnt++; 161 return (1); 162} 163 164static int dmar_enable = 0; 165static void 166dmar_identify(driver_t *driver, device_t parent) 167{ 168 ACPI_TABLE_DMAR *dmartbl; 169 ACPI_DMAR_HARDWARE_UNIT *dmarh; 170 ACPI_STATUS status; 171 int i, error; 172 173 if (acpi_disabled("dmar")) 174 return; 175 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable); 176 if (!dmar_enable) 177 return; 178 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 179 if (ACPI_FAILURE(status)) 180 return; 181 haw = dmartbl->Width + 1; 182 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR) 183 dmar_high = BUS_SPACE_MAXADDR; 184 else 185 dmar_high = 1ULL << (haw + 1); 186 if (bootverbose) { 187 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, 188 (unsigned)dmartbl->Flags, 189 "\020\001INTR_REMAP\002X2APIC_OPT_OUT"); 190 } 191 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 192 193 dmar_iterate_tbl(dmar_count_iter, NULL); 194 if (dmar_devcnt == 0) 195 return; 196 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF, 197 M_WAITOK | M_ZERO); 198 for (i = 0; i < dmar_devcnt; i++) { 199 dmarh = dmar_find_by_index(i); 200 if (dmarh == NULL) { 201 printf("dmar_identify: cannot find HWUNIT %d\n", i); 202 continue; 203 } 204 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i); 205 if (dmar_devs[i] == NULL) { 206 printf("dmar_identify: cannot create instance %d\n", i); 207 continue; 208 } 209 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY, 210 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); 211 if (error != 0) { 212 printf( 213 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n", 214 i, (uintmax_t)dmarh->Address, error); 215 device_delete_child(parent, dmar_devs[i]); 216 dmar_devs[i] = NULL; 217 } 218 } 219} 220 221static int 222dmar_probe(device_t dev) 223{ 224 225 if (acpi_get_handle(dev) != NULL) 226 return (ENXIO); 227 device_set_desc(dev, "DMA remap"); 228 return (BUS_PROBE_NOWILDCARD); 229} 230 231static void 232dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx) 233{ 234 struct dmar_msi_data *dmd; 235 236 dmd = &unit->intrs[idx]; 237 if (dmd->irq == -1) 238 return; 239 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 240 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 241 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 242 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)), 243 dev, dmd->irq); 244 dmd->irq = -1; 245} 246 247static void 248dmar_release_resources(device_t dev, struct dmar_unit *unit) 249{ 250 int i; 251 252 iommu_fini_busdma(&unit->iommu); 253 dmar_fini_irt(unit); 254 dmar_fini_qi(unit); 255 dmar_fini_fault_log(unit); 256 for (i = 0; i < DMAR_INTR_TOTAL; i++) 257 dmar_release_intr(dev, unit, i); 258 if (unit->regs != NULL) { 259 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 260 unit->regs); 261 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 262 unit->regs); 263 unit->regs = NULL; 264 } 265 if (unit->domids != NULL) { 266 delete_unrhdr(unit->domids); 267 unit->domids = NULL; 268 } 269 if (unit->ctx_obj != NULL) { 270 vm_object_deallocate(unit->ctx_obj); 271 unit->ctx_obj = NULL; 272 } 273} 274 275static int 276dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx) 277{ 278 device_t pcib; 279 struct dmar_msi_data *dmd; 280 uint64_t msi_addr; 281 uint32_t msi_data; 282 int error; 283 284 dmd = &unit->intrs[idx]; 285 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */ 286 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq); 287 if (error != 0) { 288 device_printf(dev, "cannot allocate %s interrupt, %d\n", 289 dmd->name, error); 290 goto err1; 291 } 292 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid, 293 dmd->irq, 1); 294 if (error != 0) { 295 device_printf(dev, "cannot set %s interrupt resource, %d\n", 296 dmd->name, error); 297 goto err2; 298 } 299 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 300 &dmd->irq_rid, RF_ACTIVE); 301 if (dmd->irq_res == NULL) { 302 device_printf(dev, 303 "cannot allocate resource for %s interrupt\n", dmd->name); 304 error = ENXIO; 305 goto err3; 306 } 307 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC, 308 dmd->handler, NULL, unit, &dmd->intr_handle); 309 if (error != 0) { 310 device_printf(dev, "cannot setup %s interrupt, %d\n", 311 dmd->name, error); 312 goto err4; 313 } 314 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name); 315 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data); 316 if (error != 0) { 317 device_printf(dev, "cannot map %s interrupt, %d\n", 318 dmd->name, error); 319 goto err5; 320 } 321 dmar_write4(unit, dmd->msi_data_reg, msi_data); 322 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 323 /* Only for xAPIC mode */ 324 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 325 return (0); 326 327err5: 328 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 329err4: 330 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 331err3: 332 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 333err2: 334 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq); 335 dmd->irq = -1; 336err1: 337 return (error); 338} 339 340#ifdef DEV_APIC 341static int 342dmar_remap_intr(device_t dev, device_t child, u_int irq) 343{ 344 struct dmar_unit *unit; 345 struct dmar_msi_data *dmd; 346 uint64_t msi_addr; 347 uint32_t msi_data; 348 int i, error; 349 350 unit = device_get_softc(dev); 351 for (i = 0; i < DMAR_INTR_TOTAL; i++) { 352 dmd = &unit->intrs[i]; 353 if (irq == dmd->irq) { 354 error = PCIB_MAP_MSI(device_get_parent( 355 device_get_parent(dev)), 356 dev, irq, &msi_addr, &msi_data); 357 if (error != 0) 358 return (error); 359 DMAR_LOCK(unit); 360 (dmd->disable_intr)(unit); 361 dmar_write4(unit, dmd->msi_data_reg, msi_data); 362 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 363 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 364 (dmd->enable_intr)(unit); 365 DMAR_UNLOCK(unit); 366 return (0); 367 } 368 } 369 return (ENOENT); 370} 371#endif 372 373static void 374dmar_print_caps(device_t dev, struct dmar_unit *unit, 375 ACPI_DMAR_HARDWARE_UNIT *dmaru) 376{ 377 uint32_t caphi, ecaphi; 378 379 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n", 380 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), 381 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, 382 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); 383 caphi = unit->hw_cap >> 32; 384 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, 385 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); 386 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); 387 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", 388 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), 389 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), 390 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); 391 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) 392 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); 393 printf("\n"); 394 ecaphi = unit->hw_ecap >> 32; 395 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, 396 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" 397 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); 398 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); 399 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), 400 DMAR_ECAP_IRO(unit->hw_ecap)); 401} 402 403static int 404dmar_attach(device_t dev) 405{ 406 struct dmar_unit *unit; 407 ACPI_DMAR_HARDWARE_UNIT *dmaru; 408 uint64_t timeout; 409 int i, error; 410 411 unit = device_get_softc(dev); 412 unit->dev = dev; 413 unit->iommu.unit = device_get_unit(dev); 414 unit->iommu.dev = dev; 415 dmaru = dmar_find_by_index(unit->iommu.unit); 416 if (dmaru == NULL) 417 return (EINVAL); 418 unit->segment = dmaru->Segment; 419 unit->base = dmaru->Address; 420 unit->reg_rid = DMAR_REG_RID; 421 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 422 &unit->reg_rid, RF_ACTIVE); 423 if (unit->regs == NULL) { 424 device_printf(dev, "cannot allocate register window\n"); 425 return (ENOMEM); 426 } 427 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); 428 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); 429 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); 430 if (bootverbose) 431 dmar_print_caps(dev, unit, dmaru); 432 dmar_quirks_post_ident(unit); 433 434 timeout = dmar_get_timeout(); 435 TUNABLE_UINT64_FETCH("hw.dmar.timeout", &timeout); 436 dmar_update_timeout(timeout); 437 438 for (i = 0; i < DMAR_INTR_TOTAL; i++) 439 unit->intrs[i].irq = -1; 440 441 unit->intrs[DMAR_INTR_FAULT].name = "fault"; 442 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID; 443 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr; 444 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG; 445 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG; 446 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG; 447 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr; 448 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr; 449 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT); 450 if (error != 0) { 451 dmar_release_resources(dev, unit); 452 return (error); 453 } 454 if (DMAR_HAS_QI(unit)) { 455 unit->intrs[DMAR_INTR_QI].name = "qi"; 456 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID; 457 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr; 458 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG; 459 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG; 460 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG; 461 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr; 462 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr; 463 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI); 464 if (error != 0) { 465 dmar_release_resources(dev, unit); 466 return (error); 467 } 468 } 469 470 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF); 471 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), 472 &unit->iommu.lock); 473 LIST_INIT(&unit->domains); 474 475 /* 476 * 9.2 "Context Entry": 477 * When Caching Mode (CM) field is reported as Set, the 478 * domain-id value of zero is architecturally reserved. 479 * Software must not use domain-id value of zero 480 * when CM is Set. 481 */ 482 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 483 alloc_unr_specific(unit->domids, 0); 484 485 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + 486 DMAR_CTX_CNT), 0, 0, NULL); 487 488 /* 489 * Allocate and load the root entry table pointer. Enable the 490 * address translation after the required invalidations are 491 * done. 492 */ 493 dmar_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO); 494 DMAR_LOCK(unit); 495 error = dmar_load_root_entry_ptr(unit); 496 if (error != 0) { 497 DMAR_UNLOCK(unit); 498 dmar_release_resources(dev, unit); 499 return (error); 500 } 501 error = dmar_inv_ctx_glob(unit); 502 if (error != 0) { 503 DMAR_UNLOCK(unit); 504 dmar_release_resources(dev, unit); 505 return (error); 506 } 507 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { 508 error = dmar_inv_iotlb_glob(unit); 509 if (error != 0) { 510 DMAR_UNLOCK(unit); 511 dmar_release_resources(dev, unit); 512 return (error); 513 } 514 } 515 516 DMAR_UNLOCK(unit); 517 error = dmar_init_fault_log(unit); 518 if (error != 0) { 519 dmar_release_resources(dev, unit); 520 return (error); 521 } 522 error = dmar_init_qi(unit); 523 if (error != 0) { 524 dmar_release_resources(dev, unit); 525 return (error); 526 } 527 error = dmar_init_irt(unit); 528 if (error != 0) { 529 dmar_release_resources(dev, unit); 530 return (error); 531 } 532 error = iommu_init_busdma(&unit->iommu); 533 if (error != 0) { 534 dmar_release_resources(dev, unit); 535 return (error); 536 } 537 538#ifdef NOTYET 539 DMAR_LOCK(unit); 540 error = dmar_enable_translation(unit); 541 if (error != 0) { 542 DMAR_UNLOCK(unit); 543 dmar_release_resources(dev, unit); 544 return (error); 545 } 546 DMAR_UNLOCK(unit); 547#endif 548 549 return (0); 550} 551 552static int 553dmar_detach(device_t dev) 554{ 555 556 return (EBUSY); 557} 558 559static int 560dmar_suspend(device_t dev) 561{ 562 563 return (0); 564} 565 566static int 567dmar_resume(device_t dev) 568{ 569 570 /* XXXKIB */ 571 return (0); 572} 573 574static device_method_t dmar_methods[] = { 575 DEVMETHOD(device_identify, dmar_identify), 576 DEVMETHOD(device_probe, dmar_probe), 577 DEVMETHOD(device_attach, dmar_attach), 578 DEVMETHOD(device_detach, dmar_detach), 579 DEVMETHOD(device_suspend, dmar_suspend), 580 DEVMETHOD(device_resume, dmar_resume), 581#ifdef DEV_APIC 582 DEVMETHOD(bus_remap_intr, dmar_remap_intr), 583#endif 584 DEVMETHOD_END 585}; 586 587static driver_t dmar_driver = { 588 "dmar", 589 dmar_methods, 590 sizeof(struct dmar_unit), 591}; 592 593DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0); 594MODULE_DEPEND(dmar, acpi, 1, 1, 1); 595 596static void 597dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path) 598{ 599 int i; 600 601 printf("[%d, ", busno); 602 for (i = 0; i < depth; i++) { 603 if (i != 0) 604 printf(", "); 605 printf("(%d, %d)", path[i].Device, path[i].Function); 606 } 607 printf("]"); 608} 609 610int 611dmar_dev_depth(device_t child) 612{ 613 devclass_t pci_class; 614 device_t bus, pcib; 615 int depth; 616 617 pci_class = devclass_find("pci"); 618 for (depth = 1; ; depth++) { 619 bus = device_get_parent(child); 620 pcib = device_get_parent(bus); 621 if (device_get_devclass(device_get_parent(pcib)) != 622 pci_class) 623 return (depth); 624 child = pcib; 625 } 626} 627 628void 629dmar_dev_path(device_t child, int *busno, void *path1, int depth) 630{ 631 devclass_t pci_class; 632 device_t bus, pcib; 633 ACPI_DMAR_PCI_PATH *path; 634 635 pci_class = devclass_find("pci"); 636 path = path1; 637 for (depth--; depth != -1; depth--) { 638 path[depth].Device = pci_get_slot(child); 639 path[depth].Function = pci_get_function(child); 640 bus = device_get_parent(child); 641 pcib = device_get_parent(bus); 642 if (device_get_devclass(device_get_parent(pcib)) != 643 pci_class) { 644 /* reached a host bridge */ 645 *busno = pcib_get_bus(bus); 646 return; 647 } 648 child = pcib; 649 } 650 panic("wrong depth"); 651} 652 653static int 654dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1, 655 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2, 656 enum AcpiDmarScopeType scope_type) 657{ 658 int i, depth; 659 660 if (busno1 != busno2) 661 return (0); 662 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2) 663 return (0); 664 depth = depth1; 665 if (depth2 < depth) 666 depth = depth2; 667 for (i = 0; i < depth; i++) { 668 if (path1[i].Device != path2[i].Device || 669 path1[i].Function != path2[i].Function) 670 return (0); 671 } 672 return (1); 673} 674 675static int 676dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno, 677 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 678{ 679 ACPI_DMAR_PCI_PATH *path; 680 int path_len; 681 682 if (devscope->Length < sizeof(*devscope)) { 683 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 684 devscope->Length); 685 return (-1); 686 } 687 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 688 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 689 return (0); 690 path_len = devscope->Length - sizeof(*devscope); 691 if (path_len % 2 != 0) { 692 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 693 devscope->Length); 694 return (-1); 695 } 696 path_len /= 2; 697 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1); 698 if (path_len == 0) { 699 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 700 devscope->Length); 701 return (-1); 702 } 703 704 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, 705 dev_path, dev_path_len, devscope->EntryType)); 706} 707 708static bool 709dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno, 710 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner) 711{ 712 ACPI_DMAR_HARDWARE_UNIT *dmarh; 713 ACPI_DMAR_DEVICE_SCOPE *devscope; 714 char *ptr, *ptrend; 715 int match; 716 717 dmarh = dmar_find_by_index(unit->iommu.unit); 718 if (dmarh == NULL) 719 return (false); 720 if (dmarh->Segment != dev_domain) 721 return (false); 722 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { 723 if (banner != NULL) 724 *banner = "INCLUDE_ALL"; 725 return (true); 726 } 727 ptr = (char *)dmarh + sizeof(*dmarh); 728 ptrend = (char *)dmarh + dmarh->Header.Length; 729 while (ptr < ptrend) { 730 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 731 ptr += devscope->Length; 732 match = dmar_match_devscope(devscope, dev_busno, dev_path, 733 dev_path_len); 734 if (match == -1) 735 return (false); 736 if (match == 1) { 737 if (banner != NULL) 738 *banner = "specific match"; 739 return (true); 740 } 741 } 742 return (false); 743} 744 745static struct dmar_unit * 746dmar_find_by_scope(int dev_domain, int dev_busno, 747 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 748{ 749 struct dmar_unit *unit; 750 int i; 751 752 for (i = 0; i < dmar_devcnt; i++) { 753 if (dmar_devs[i] == NULL) 754 continue; 755 unit = device_get_softc(dmar_devs[i]); 756 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path, 757 dev_path_len, NULL)) 758 return (unit); 759 } 760 return (NULL); 761} 762 763struct dmar_unit * 764dmar_find(device_t dev, bool verbose) 765{ 766 device_t dmar_dev; 767 struct dmar_unit *unit; 768 const char *banner; 769 int i, dev_domain, dev_busno, dev_path_len; 770 771 /* 772 * This function can only handle PCI(e) devices. 773 */ 774 if (device_get_devclass(device_get_parent(dev)) != 775 devclass_find("pci")) 776 return (NULL); 777 778 dmar_dev = NULL; 779 dev_domain = pci_get_domain(dev); 780 dev_path_len = dmar_dev_depth(dev); 781 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 782 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 783 banner = ""; 784 785 for (i = 0; i < dmar_devcnt; i++) { 786 if (dmar_devs[i] == NULL) 787 continue; 788 unit = device_get_softc(dmar_devs[i]); 789 if (dmar_match_by_path(unit, dev_domain, dev_busno, 790 dev_path, dev_path_len, &banner)) 791 break; 792 } 793 if (i == dmar_devcnt) 794 return (NULL); 795 796 if (verbose) { 797 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s", 798 dev_domain, pci_get_bus(dev), pci_get_slot(dev), 799 pci_get_function(dev), unit->iommu.unit, banner); 800 printf(" scope path "); 801 dmar_print_path(dev_busno, dev_path_len, dev_path); 802 printf("\n"); 803 } 804 return (unit); 805} 806 807static struct dmar_unit * 808dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid) 809{ 810 device_t dmar_dev; 811 struct dmar_unit *unit; 812 ACPI_DMAR_HARDWARE_UNIT *dmarh; 813 ACPI_DMAR_DEVICE_SCOPE *devscope; 814 ACPI_DMAR_PCI_PATH *path; 815 char *ptr, *ptrend; 816#ifdef DEV_APIC 817 int error; 818#endif 819 int i; 820 821 for (i = 0; i < dmar_devcnt; i++) { 822 dmar_dev = dmar_devs[i]; 823 if (dmar_dev == NULL) 824 continue; 825 unit = (struct dmar_unit *)device_get_softc(dmar_dev); 826 dmarh = dmar_find_by_index(i); 827 if (dmarh == NULL) 828 continue; 829 ptr = (char *)dmarh + sizeof(*dmarh); 830 ptrend = (char *)dmarh + dmarh->Header.Length; 831 for (;;) { 832 if (ptr >= ptrend) 833 break; 834 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 835 ptr += devscope->Length; 836 if (devscope->EntryType != entry_type) 837 continue; 838 if (devscope->EnumerationId != id) 839 continue; 840#ifdef DEV_APIC 841 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { 842 error = ioapic_get_rid(id, rid); 843 /* 844 * If our IOAPIC has PCI bindings then 845 * use the PCI device rid. 846 */ 847 if (error == 0) 848 return (unit); 849 } 850#endif 851 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) 852 == 2) { 853 if (rid != NULL) { 854 path = (ACPI_DMAR_PCI_PATH *) 855 (devscope + 1); 856 *rid = PCI_RID(devscope->Bus, 857 path->Device, path->Function); 858 } 859 return (unit); 860 } 861 printf( 862 "dmar_find_nonpci: id %d type %d path length != 2\n", 863 id, entry_type); 864 break; 865 } 866 } 867 return (NULL); 868} 869 870struct dmar_unit * 871dmar_find_hpet(device_t dev, uint16_t *rid) 872{ 873 874 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET, 875 rid)); 876} 877 878struct dmar_unit * 879dmar_find_ioapic(u_int apic_id, uint16_t *rid) 880{ 881 882 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid)); 883} 884 885struct rmrr_iter_args { 886 struct dmar_domain *domain; 887 int dev_domain; 888 int dev_busno; 889 const ACPI_DMAR_PCI_PATH *dev_path; 890 int dev_path_len; 891 struct iommu_map_entries_tailq *rmrr_entries; 892}; 893 894static int 895dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 896{ 897 struct rmrr_iter_args *ria; 898 ACPI_DMAR_RESERVED_MEMORY *resmem; 899 ACPI_DMAR_DEVICE_SCOPE *devscope; 900 struct iommu_map_entry *entry; 901 char *ptr, *ptrend; 902 int match; 903 904 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 905 return (1); 906 907 ria = arg; 908 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 909 if (resmem->Segment != ria->dev_domain) 910 return (1); 911 912 ptr = (char *)resmem + sizeof(*resmem); 913 ptrend = (char *)resmem + resmem->Header.Length; 914 for (;;) { 915 if (ptr >= ptrend) 916 break; 917 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 918 ptr += devscope->Length; 919 match = dmar_match_devscope(devscope, ria->dev_busno, 920 ria->dev_path, ria->dev_path_len); 921 if (match == 1) { 922 entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain), 923 IOMMU_PGF_WAITOK); 924 entry->start = resmem->BaseAddress; 925 /* The RMRR entry end address is inclusive. */ 926 entry->end = resmem->EndAddress; 927 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, 928 unroll_link); 929 } 930 } 931 932 return (1); 933} 934 935void 936dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno, 937 const void *dev_path, int dev_path_len, 938 struct iommu_map_entries_tailq *rmrr_entries) 939{ 940 struct rmrr_iter_args ria; 941 942 ria.domain = domain; 943 ria.dev_domain = dev_domain; 944 ria.dev_busno = dev_busno; 945 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path; 946 ria.dev_path_len = dev_path_len; 947 ria.rmrr_entries = rmrr_entries; 948 dmar_iterate_tbl(dmar_rmrr_iter, &ria); 949} 950 951struct inst_rmrr_iter_args { 952 struct dmar_unit *dmar; 953}; 954 955static device_t 956dmar_path_dev(int segment, int path_len, int busno, 957 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid) 958{ 959 device_t dev; 960 int i; 961 962 dev = NULL; 963 for (i = 0; i < path_len; i++) { 964 dev = pci_find_dbsf(segment, busno, path->Device, 965 path->Function); 966 if (i != path_len - 1) { 967 busno = pci_cfgregread(busno, path->Device, 968 path->Function, PCIR_SECBUS_1, 1); 969 path++; 970 } 971 } 972 *rid = PCI_RID(busno, path->Device, path->Function); 973 return (dev); 974} 975 976static int 977dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 978{ 979 const ACPI_DMAR_RESERVED_MEMORY *resmem; 980 const ACPI_DMAR_DEVICE_SCOPE *devscope; 981 struct inst_rmrr_iter_args *iria; 982 const char *ptr, *ptrend; 983 device_t dev; 984 struct dmar_unit *unit; 985 int dev_path_len; 986 uint16_t rid; 987 988 iria = arg; 989 990 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 991 return (1); 992 993 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 994 if (resmem->Segment != iria->dmar->segment) 995 return (1); 996 997 ptr = (const char *)resmem + sizeof(*resmem); 998 ptrend = (const char *)resmem + resmem->Header.Length; 999 for (;;) { 1000 if (ptr >= ptrend) 1001 break; 1002 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr; 1003 ptr += devscope->Length; 1004 /* XXXKIB bridge */ 1005 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) 1006 continue; 1007 rid = 0; 1008 dev_path_len = (devscope->Length - 1009 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2; 1010 dev = dmar_path_dev(resmem->Segment, dev_path_len, 1011 devscope->Bus, 1012 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid); 1013 if (dev == NULL) { 1014 if (bootverbose) { 1015 printf("dmar%d no dev found for RMRR " 1016 "[%#jx, %#jx] rid %#x scope path ", 1017 iria->dmar->iommu.unit, 1018 (uintmax_t)resmem->BaseAddress, 1019 (uintmax_t)resmem->EndAddress, 1020 rid); 1021 dmar_print_path(devscope->Bus, dev_path_len, 1022 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 1023 printf("\n"); 1024 } 1025 unit = dmar_find_by_scope(resmem->Segment, 1026 devscope->Bus, 1027 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1028 dev_path_len); 1029 if (iria->dmar != unit) 1030 continue; 1031 dmar_get_ctx_for_devpath(iria->dmar, rid, 1032 resmem->Segment, devscope->Bus, 1033 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1034 dev_path_len, false, true); 1035 } else { 1036 unit = dmar_find(dev, false); 1037 if (iria->dmar != unit) 1038 continue; 1039 iommu_instantiate_ctx(&(iria)->dmar->iommu, 1040 dev, true); 1041 } 1042 } 1043 1044 return (1); 1045 1046} 1047 1048/* 1049 * Pre-create all contexts for the DMAR which have RMRR entries. 1050 */ 1051int 1052dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit) 1053{ 1054 struct dmar_unit *dmar; 1055 struct inst_rmrr_iter_args iria; 1056 int error; 1057 1058 dmar = IOMMU2DMAR(unit); 1059 1060 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) 1061 return (0); 1062 1063 error = 0; 1064 iria.dmar = dmar; 1065 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria); 1066 DMAR_LOCK(dmar); 1067 if (!LIST_EMPTY(&dmar->domains)) { 1068 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, 1069 ("dmar%d: RMRR not handled but translation is already enabled", 1070 dmar->iommu.unit)); 1071 error = dmar_enable_translation(dmar); 1072 if (bootverbose) { 1073 if (error == 0) { 1074 printf("dmar%d: enabled translation\n", 1075 dmar->iommu.unit); 1076 } else { 1077 printf("dmar%d: enabling translation failed, " 1078 "error %d\n", dmar->iommu.unit, error); 1079 } 1080 } 1081 } 1082 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR); 1083 return (error); 1084} 1085 1086#ifdef DDB 1087#include <ddb/ddb.h> 1088#include <ddb/db_lex.h> 1089 1090static void 1091dmar_print_domain_entry(const struct iommu_map_entry *entry) 1092{ 1093 struct iommu_map_entry *l, *r; 1094 1095 db_printf( 1096 " start %jx end %jx first %jx last %jx free_down %jx flags %x ", 1097 entry->start, entry->end, entry->first, entry->last, 1098 entry->free_down, entry->flags); 1099 db_printf("left "); 1100 l = RB_LEFT(entry, rb_entry); 1101 if (l == NULL) 1102 db_printf("NULL "); 1103 else 1104 db_printf("%jx ", l->start); 1105 db_printf("right "); 1106 r = RB_RIGHT(entry, rb_entry); 1107 if (r == NULL) 1108 db_printf("NULL"); 1109 else 1110 db_printf("%jx", r->start); 1111 db_printf("\n"); 1112} 1113 1114static void 1115dmar_print_ctx(struct dmar_ctx *ctx) 1116{ 1117 1118 db_printf( 1119 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n", 1120 ctx, pci_get_bus(ctx->context.tag->owner), 1121 pci_get_slot(ctx->context.tag->owner), 1122 pci_get_function(ctx->context.tag->owner), ctx->refs, 1123 ctx->context.flags, ctx->context.loads, ctx->context.unloads); 1124} 1125 1126static void 1127dmar_print_domain(struct dmar_domain *domain, bool show_mappings) 1128{ 1129 struct iommu_domain *iodom; 1130 struct iommu_map_entry *entry; 1131 struct dmar_ctx *ctx; 1132 1133 iodom = DOM2IODOM(domain); 1134 1135 db_printf( 1136 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n" 1137 " ctx_cnt %d flags %x pgobj %p map_ents %u\n", 1138 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl, 1139 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt, 1140 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt); 1141 if (!LIST_EMPTY(&domain->contexts)) { 1142 db_printf(" Contexts:\n"); 1143 LIST_FOREACH(ctx, &domain->contexts, link) 1144 dmar_print_ctx(ctx); 1145 } 1146 if (!show_mappings) 1147 return; 1148 db_printf(" mapped:\n"); 1149 RB_FOREACH(entry, iommu_gas_entries_tree, &iodom->rb_root) { 1150 dmar_print_domain_entry(entry); 1151 if (db_pager_quit) 1152 break; 1153 } 1154 if (db_pager_quit) 1155 return; 1156 db_printf(" unloading:\n"); 1157 TAILQ_FOREACH(entry, &domain->iodom.unload_entries, dmamap_link) { 1158 dmar_print_domain_entry(entry); 1159 if (db_pager_quit) 1160 break; 1161 } 1162} 1163 1164DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL) 1165{ 1166 struct dmar_unit *unit; 1167 struct dmar_domain *domain; 1168 struct dmar_ctx *ctx; 1169 bool show_mappings, valid; 1170 int pci_domain, bus, device, function, i, t; 1171 db_expr_t radix; 1172 1173 valid = false; 1174 radix = db_radix; 1175 db_radix = 10; 1176 t = db_read_token(); 1177 if (t == tSLASH) { 1178 t = db_read_token(); 1179 if (t != tIDENT) { 1180 db_printf("Bad modifier\n"); 1181 db_radix = radix; 1182 db_skip_to_eol(); 1183 return; 1184 } 1185 show_mappings = strchr(db_tok_string, 'm') != NULL; 1186 t = db_read_token(); 1187 } else { 1188 show_mappings = false; 1189 } 1190 if (t == tNUMBER) { 1191 pci_domain = db_tok_number; 1192 t = db_read_token(); 1193 if (t == tNUMBER) { 1194 bus = db_tok_number; 1195 t = db_read_token(); 1196 if (t == tNUMBER) { 1197 device = db_tok_number; 1198 t = db_read_token(); 1199 if (t == tNUMBER) { 1200 function = db_tok_number; 1201 valid = true; 1202 } 1203 } 1204 } 1205 } 1206 db_radix = radix; 1207 db_skip_to_eol(); 1208 if (!valid) { 1209 db_printf("usage: show dmar_domain [/m] " 1210 "<domain> <bus> <device> <func>\n"); 1211 return; 1212 } 1213 for (i = 0; i < dmar_devcnt; i++) { 1214 unit = device_get_softc(dmar_devs[i]); 1215 LIST_FOREACH(domain, &unit->domains, link) { 1216 LIST_FOREACH(ctx, &domain->contexts, link) { 1217 if (pci_domain == unit->segment && 1218 bus == pci_get_bus(ctx->context.tag->owner) && 1219 device == 1220 pci_get_slot(ctx->context.tag->owner) && 1221 function == 1222 pci_get_function(ctx->context.tag->owner)) { 1223 dmar_print_domain(domain, 1224 show_mappings); 1225 goto out; 1226 } 1227 } 1228 } 1229 } 1230out:; 1231} 1232 1233static void 1234dmar_print_one(int idx, bool show_domains, bool show_mappings) 1235{ 1236 struct dmar_unit *unit; 1237 struct dmar_domain *domain; 1238 int i, frir; 1239 1240 unit = device_get_softc(dmar_devs[idx]); 1241 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit, 1242 unit, dmar_read8(unit, DMAR_RTADDR_REG), 1243 dmar_read4(unit, DMAR_VER_REG)); 1244 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n", 1245 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), 1246 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), 1247 dmar_read4(unit, DMAR_GSTS_REG), 1248 dmar_read4(unit, DMAR_FSTS_REG), 1249 dmar_read4(unit, DMAR_FECTL_REG)); 1250 if (unit->ir_enabled) { 1251 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n", 1252 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); 1253 } 1254 db_printf("fed 0x%x fea 0x%x feua 0x%x\n", 1255 dmar_read4(unit, DMAR_FEDATA_REG), 1256 dmar_read4(unit, DMAR_FEADDR_REG), 1257 dmar_read4(unit, DMAR_FEUADDR_REG)); 1258 db_printf("primary fault log:\n"); 1259 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { 1260 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; 1261 db_printf(" %d at 0x%x: %jx %jx\n", i, frir, 1262 (uintmax_t)dmar_read8(unit, frir), 1263 (uintmax_t)dmar_read8(unit, frir + 8)); 1264 } 1265 if (DMAR_HAS_QI(unit)) { 1266 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n", 1267 dmar_read4(unit, DMAR_IEDATA_REG), 1268 dmar_read4(unit, DMAR_IEADDR_REG), 1269 dmar_read4(unit, DMAR_IEUADDR_REG)); 1270 if (unit->qi_enabled) { 1271 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " 1272 "size 0x%jx\n" 1273 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" 1274 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n", 1275 (uintmax_t)unit->inv_queue, 1276 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), 1277 (uintmax_t)unit->inv_queue_size, 1278 dmar_read4(unit, DMAR_IQH_REG), 1279 dmar_read4(unit, DMAR_IQT_REG), 1280 unit->inv_queue_avail, 1281 dmar_read4(unit, DMAR_ICS_REG), 1282 dmar_read4(unit, DMAR_IECTL_REG), 1283 unit->inv_waitd_seq_hw, 1284 &unit->inv_waitd_seq_hw, 1285 (uintmax_t)unit->inv_waitd_seq_hw_phys, 1286 unit->inv_waitd_seq, 1287 unit->inv_waitd_gen); 1288 } else { 1289 db_printf("qi is disabled\n"); 1290 } 1291 } 1292 if (show_domains) { 1293 db_printf("domains:\n"); 1294 LIST_FOREACH(domain, &unit->domains, link) { 1295 dmar_print_domain(domain, show_mappings); 1296 if (db_pager_quit) 1297 break; 1298 } 1299 } 1300} 1301 1302DB_SHOW_COMMAND(dmar, db_dmar_print) 1303{ 1304 bool show_domains, show_mappings; 1305 1306 show_domains = strchr(modif, 'd') != NULL; 1307 show_mappings = strchr(modif, 'm') != NULL; 1308 if (!have_addr) { 1309 db_printf("usage: show dmar [/d] [/m] index\n"); 1310 return; 1311 } 1312 dmar_print_one((int)addr, show_domains, show_mappings); 1313} 1314 1315DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars) 1316{ 1317 int i; 1318 bool show_domains, show_mappings; 1319 1320 show_domains = strchr(modif, 'd') != NULL; 1321 show_mappings = strchr(modif, 'm') != NULL; 1322 1323 for (i = 0; i < dmar_devcnt; i++) { 1324 dmar_print_one(i, show_domains, show_mappings); 1325 if (db_pager_quit) 1326 break; 1327 } 1328} 1329#endif 1330 1331struct iommu_unit * 1332iommu_find(device_t dev, bool verbose) 1333{ 1334 struct dmar_unit *dmar; 1335 1336 dmar = dmar_find(dev, verbose); 1337 1338 return (&dmar->iommu); 1339} 1340