1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright 2006-2007 by Juniper Networks. 5 * Copyright 2008 Semihalf. 6 * Copyright 2010 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Semihalf 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 36 */ 37 38#include <sys/cdefs.h> 39__FBSDID("$FreeBSD$"); 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/ktr.h> 44#include <sys/sockio.h> 45#include <sys/mbuf.h> 46#include <sys/malloc.h> 47#include <sys/kernel.h> 48#include <sys/module.h> 49#include <sys/socket.h> 50#include <sys/queue.h> 51#include <sys/bus.h> 52#include <sys/lock.h> 53#include <sys/mutex.h> 54#include <sys/queue.h> 55#include <sys/rman.h> 56#include <sys/endian.h> 57#include <sys/vmem.h> 58 59#include <vm/vm.h> 60#include <vm/pmap.h> 61 62#include <dev/ofw/ofw_pci.h> 63#include <dev/ofw/ofw_bus.h> 64#include <dev/ofw/ofw_bus_subr.h> 65#include <dev/ofw/ofwpci.h> 66#include <dev/pci/pcivar.h> 67#include <dev/pci/pcireg.h> 68#include <dev/pci/pcib_private.h> 69 70#include "ofw_bus_if.h" 71#include "pcib_if.h" 72#include "pic_if.h" 73 74#include <machine/resource.h> 75#include <machine/bus.h> 76#include <machine/intr_machdep.h> 77 78#include <powerpc/mpc85xx/mpc85xx.h> 79 80#define REG_CFG_ADDR 0x0000 81#define CONFIG_ACCESS_ENABLE 0x80000000 82 83#define REG_CFG_DATA 0x0004 84#define REG_INT_ACK 0x0008 85 86#define REG_PEX_IP_BLK_REV1 0x0bf8 87#define IP_MJ_M 0x0000ff00 88#define IP_MJ_S 8 89#define IP_MN_M 0x000000ff 90#define IP_MN_S 0 91 92#define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 93#define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 94#define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 95#define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 96 97#define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 98#define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 99#define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 100#define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 101#define PIWAR_EN 0x80000000 102#define PIWAR_PF 0x40000000 103#define PIWAR_TRGT_M 0x00f00000 104#define PIWAR_TRGT_S 20 105#define PIWAR_TRGT_CCSR 0xe 106#define PIWAR_TRGT_LOCAL 0xf 107 108#define REG_PEX_MES_DR 0x0020 109#define REG_PEX_MES_IER 0x0028 110#define REG_PEX_ERR_DR 0x0e00 111#define REG_PEX_ERR_EN 0x0e08 112 113#define REG_PEX_ERR_DR 0x0e00 114#define REG_PEX_ERR_DR_ME 0x80000000 115#define REG_PEX_ERR_DR_PCT 0x800000 116#define REG_PEX_ERR_DR_PAT 0x400000 117#define REG_PEX_ERR_DR_PCAC 0x200000 118#define REG_PEX_ERR_DR_PNM 0x100000 119#define REG_PEX_ERR_DR_CDNSC 0x80000 120#define REG_PEX_ERR_DR_CRSNC 0x40000 121#define REG_PEX_ERR_DR_ICCA 0x20000 122#define REG_PEX_ERR_DR_IACA 0x10000 123#define REG_PEX_ERR_DR_CRST 0x8000 124#define REG_PEX_ERR_DR_MIS 0x4000 125#define REG_PEX_ERR_DR_IOIS 0x2000 126#define REG_PEX_ERR_DR_CIS 0x1000 127#define REG_PEX_ERR_DR_CIEP 0x800 128#define REG_PEX_ERR_DR_IOIEP 0x400 129#define REG_PEX_ERR_DR_OAC 0x200 130#define REG_PEX_ERR_DR_IOIA 0x100 131#define REG_PEX_ERR_DR_IMBA 0x80 132#define REG_PEX_ERR_DR_IIOBA 0x40 133#define REG_PEX_ERR_DR_LDDE 0x20 134#define REG_PEX_ERR_EN 0x0e08 135 136#define PCIR_LTSSM 0x404 137#define LTSSM_STAT_L0 0x16 138 139#define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 140 141#define FSL_NUM_MSIS 256 /* 8 registers of 32 bits (8 hardware IRQs) */ 142 143struct fsl_pcib_softc { 144 struct ofw_pci_softc pci_sc; 145 device_t sc_dev; 146 struct mtx sc_cfg_mtx; 147 int sc_ip_maj; 148 int sc_ip_min; 149 150 int sc_iomem_target; 151 bus_addr_t sc_iomem_start, sc_iomem_end; 152 int sc_ioport_target; 153 bus_addr_t sc_ioport_start, sc_ioport_end; 154 155 struct resource *sc_res; 156 bus_space_handle_t sc_bsh; 157 bus_space_tag_t sc_bst; 158 int sc_rid; 159 160 struct resource *sc_irq_res; 161 void *sc_ih; 162 163 int sc_busnr; 164 int sc_pcie; 165 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 166}; 167 168struct fsl_pcib_err_dr { 169 const char *msg; 170 uint32_t err_dr_mask; 171}; 172 173struct fsl_msi_map { 174 SLIST_ENTRY(fsl_msi_map) slist; 175 uint32_t irq_base; 176 bus_addr_t target; 177}; 178 179SLIST_HEAD(msi_head, fsl_msi_map) fsl_msis = SLIST_HEAD_INITIALIZER(msi_head); 180 181static const struct fsl_pcib_err_dr pci_err[] = { 182 {"ME", REG_PEX_ERR_DR_ME}, 183 {"PCT", REG_PEX_ERR_DR_PCT}, 184 {"PAT", REG_PEX_ERR_DR_PAT}, 185 {"PCAC", REG_PEX_ERR_DR_PCAC}, 186 {"PNM", REG_PEX_ERR_DR_PNM}, 187 {"CDNSC", REG_PEX_ERR_DR_CDNSC}, 188 {"CRSNC", REG_PEX_ERR_DR_CRSNC}, 189 {"ICCA", REG_PEX_ERR_DR_ICCA}, 190 {"IACA", REG_PEX_ERR_DR_IACA}, 191 {"CRST", REG_PEX_ERR_DR_CRST}, 192 {"MIS", REG_PEX_ERR_DR_MIS}, 193 {"IOIS", REG_PEX_ERR_DR_IOIS}, 194 {"CIS", REG_PEX_ERR_DR_CIS}, 195 {"CIEP", REG_PEX_ERR_DR_CIEP}, 196 {"IOIEP", REG_PEX_ERR_DR_IOIEP}, 197 {"OAC", REG_PEX_ERR_DR_OAC}, 198 {"IOIA", REG_PEX_ERR_DR_IOIA}, 199 {"IMBA", REG_PEX_ERR_DR_IMBA}, 200 {"IIOBA", REG_PEX_ERR_DR_IIOBA}, 201 {"LDDE", REG_PEX_ERR_DR_LDDE} 202}; 203 204/* Local forward declerations. */ 205static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 206 u_int, int); 207static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 208 u_int, uint32_t, int); 209static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 210static void fsl_pcib_err_init(device_t); 211static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t, 212 uint64_t, uint64_t); 213static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t, 214 uint64_t, uint64_t); 215 216/* Forward declerations. */ 217static int fsl_pcib_attach(device_t); 218static int fsl_pcib_detach(device_t); 219static int fsl_pcib_probe(device_t); 220 221static int fsl_pcib_maxslots(device_t); 222static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 223static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 224 uint32_t, int); 225static int fsl_pcib_alloc_msi(device_t dev, device_t child, 226 int count, int maxcount, int *irqs); 227static int fsl_pcib_release_msi(device_t dev, device_t child, 228 int count, int *irqs); 229static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq); 230static int fsl_pcib_release_msix(device_t dev, device_t child, int irq); 231static int fsl_pcib_map_msi(device_t dev, device_t child, 232 int irq, uint64_t *addr, uint32_t *data); 233 234static vmem_t *msi_vmem; /* Global MSI vmem, holds all MSI ranges. */ 235 236/* 237 * Bus interface definitions. 238 */ 239static device_method_t fsl_pcib_methods[] = { 240 /* Device interface */ 241 DEVMETHOD(device_probe, fsl_pcib_probe), 242 DEVMETHOD(device_attach, fsl_pcib_attach), 243 DEVMETHOD(device_detach, fsl_pcib_detach), 244 245 /* pcib interface */ 246 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 247 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 248 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 249 DEVMETHOD(pcib_alloc_msi, fsl_pcib_alloc_msi), 250 DEVMETHOD(pcib_release_msi, fsl_pcib_release_msi), 251 DEVMETHOD(pcib_alloc_msix, fsl_pcib_alloc_msix), 252 DEVMETHOD(pcib_release_msix, fsl_pcib_release_msix), 253 DEVMETHOD(pcib_map_msi, fsl_pcib_map_msi), 254 255 DEVMETHOD_END 256}; 257 258static devclass_t fsl_pcib_devclass; 259 260DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods, 261 sizeof(struct fsl_pcib_softc), ofw_pci_driver); 262EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0, 263 BUS_PASS_BUS); 264 265static void 266fsl_pcib_err_intr(void *v) 267{ 268 struct fsl_pcib_softc *sc; 269 device_t dev; 270 uint32_t err_reg, clear_reg; 271 uint8_t i; 272 273 dev = (device_t)v; 274 sc = device_get_softc(dev); 275 276 clear_reg = 0; 277 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR); 278 279 /* Check which one error occurred */ 280 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) { 281 if (err_reg & pci_err[i].err_dr_mask) { 282 device_printf(dev, "PCI %d: report %s error\n", 283 device_get_unit(dev), pci_err[i].msg); 284 clear_reg |= pci_err[i].err_dr_mask; 285 } 286 } 287 288 /* Clear pending errors */ 289 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg); 290} 291 292static int 293fsl_pcib_probe(device_t dev) 294{ 295 296 if (ofw_bus_get_type(dev) == NULL || 297 strcmp(ofw_bus_get_type(dev), "pci") != 0) 298 return (ENXIO); 299 300 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") || 301 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") || 302 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") || 303 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") || 304 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") || 305 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie"))) 306 return (ENXIO); 307 308 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 309 return (BUS_PROBE_DEFAULT); 310} 311 312static int 313fsl_pcib_attach(device_t dev) 314{ 315 struct fsl_pcib_softc *sc; 316 phandle_t node; 317 uint32_t cfgreg, brctl, ipreg; 318 int error, rid; 319 uint8_t ltssm, capptr; 320 321 sc = device_get_softc(dev); 322 sc->sc_dev = dev; 323 324 sc->sc_rid = 0; 325 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 326 RF_ACTIVE); 327 if (sc->sc_res == NULL) { 328 device_printf(dev, "could not map I/O memory\n"); 329 return (ENXIO); 330 } 331 sc->sc_bst = rman_get_bustag(sc->sc_res); 332 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 333 sc->sc_busnr = 0; 334 335 ipreg = bus_read_4(sc->sc_res, REG_PEX_IP_BLK_REV1); 336 sc->sc_ip_min = (ipreg & IP_MN_M) >> IP_MN_S; 337 sc->sc_ip_maj = (ipreg & IP_MJ_M) >> IP_MJ_S; 338 mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN); 339 340 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 341 if (cfgreg != 0x1057 && cfgreg != 0x1957) 342 goto err; 343 344 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 345 while (capptr != 0) { 346 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 347 switch (cfgreg & 0xff) { 348 case PCIY_PCIX: 349 break; 350 case PCIY_EXPRESS: 351 sc->sc_pcie = 1; 352 sc->sc_pcie_capreg = capptr; 353 break; 354 } 355 capptr = (cfgreg >> 8) & 0xff; 356 } 357 358 node = ofw_bus_get_node(dev); 359 360 /* 361 * Initialize generic OF PCI interface (ranges, etc.) 362 */ 363 364 error = ofw_pci_init(dev); 365 if (error) 366 return (error); 367 368 /* 369 * Configure decode windows for PCI(E) access. 370 */ 371 if (fsl_pcib_decode_win(node, sc) != 0) 372 goto err; 373 374 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 375 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 376 PCIM_CMD_PORTEN; 377 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 378 379 /* Reset the bus. Needed for Radeon video cards. */ 380 brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0, 381 PCIR_BRIDGECTL_1, 1); 382 brctl |= PCIB_BCR_SECBUS_RESET; 383 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0, 384 PCIR_BRIDGECTL_1, brctl, 1); 385 DELAY(100000); 386 brctl &= ~PCIB_BCR_SECBUS_RESET; 387 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0, 388 PCIR_BRIDGECTL_1, brctl, 1); 389 DELAY(100000); 390 391 if (sc->sc_pcie) { 392 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 393 if (ltssm < LTSSM_STAT_L0) { 394 if (bootverbose) 395 printf("PCI %d: no PCIE link, skipping\n", 396 device_get_unit(dev)); 397 return (0); 398 } 399 } 400 401 /* Allocate irq */ 402 rid = 0; 403 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 404 RF_ACTIVE | RF_SHAREABLE); 405 if (sc->sc_irq_res == NULL) { 406 error = fsl_pcib_detach(dev); 407 if (error != 0) { 408 device_printf(dev, 409 "Detach of the driver failed with error %d\n", 410 error); 411 } 412 return (ENXIO); 413 } 414 415 /* Setup interrupt handler */ 416 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 417 NULL, fsl_pcib_err_intr, dev, &sc->sc_ih); 418 if (error != 0) { 419 device_printf(dev, "Could not setup irq, %d\n", error); 420 sc->sc_ih = NULL; 421 error = fsl_pcib_detach(dev); 422 if (error != 0) { 423 device_printf(dev, 424 "Detach of the driver failed with error %d\n", 425 error); 426 } 427 return (ENXIO); 428 } 429 430 fsl_pcib_err_init(dev); 431 432 return (ofw_pci_attach(dev)); 433 434err: 435 return (ENXIO); 436} 437 438static uint32_t 439fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 440 u_int reg, int bytes) 441{ 442 uint32_t addr, data; 443 444 addr = CONFIG_ACCESS_ENABLE; 445 addr |= (bus & 0xff) << 16; 446 addr |= (slot & 0x1f) << 11; 447 addr |= (func & 0x7) << 8; 448 addr |= reg & 0xfc; 449 if (sc->sc_pcie) 450 addr |= (reg & 0xf00) << 16; 451 452 mtx_lock_spin(&sc->sc_cfg_mtx); 453 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 454 455 switch (bytes) { 456 case 1: 457 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 458 REG_CFG_DATA + (reg & 3)); 459 break; 460 case 2: 461 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 462 REG_CFG_DATA + (reg & 2))); 463 break; 464 case 4: 465 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 466 REG_CFG_DATA)); 467 break; 468 default: 469 data = ~0; 470 break; 471 } 472 mtx_unlock_spin(&sc->sc_cfg_mtx); 473 return (data); 474} 475 476static void 477fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 478 u_int reg, uint32_t data, int bytes) 479{ 480 uint32_t addr; 481 482 addr = CONFIG_ACCESS_ENABLE; 483 addr |= (bus & 0xff) << 16; 484 addr |= (slot & 0x1f) << 11; 485 addr |= (func & 0x7) << 8; 486 addr |= reg & 0xfc; 487 if (sc->sc_pcie) 488 addr |= (reg & 0xf00) << 16; 489 490 mtx_lock_spin(&sc->sc_cfg_mtx); 491 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 492 493 switch (bytes) { 494 case 1: 495 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 496 REG_CFG_DATA + (reg & 3), data); 497 break; 498 case 2: 499 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 500 REG_CFG_DATA + (reg & 2), htole16(data)); 501 break; 502 case 4: 503 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 504 REG_CFG_DATA, htole32(data)); 505 break; 506 } 507 mtx_unlock_spin(&sc->sc_cfg_mtx); 508} 509 510#if 0 511static void 512dump(struct fsl_pcib_softc *sc) 513{ 514 unsigned int i; 515 516#define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 517 for (i = 0; i < 5; i++) { 518 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 519 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 520 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 521 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 522 } 523 printf("\n"); 524 for (i = 1; i < 4; i++) { 525 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 526 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 527 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 528 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 529 } 530 printf("\n"); 531#undef RD 532 533 for (i = 0; i < 0x48; i += 4) { 534 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 535 i, 4)); 536 } 537} 538#endif 539 540static int 541fsl_pcib_maxslots(device_t dev) 542{ 543 struct fsl_pcib_softc *sc = device_get_softc(dev); 544 545 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 546} 547 548static uint32_t 549fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 550 u_int reg, int bytes) 551{ 552 struct fsl_pcib_softc *sc = device_get_softc(dev); 553 u_int devfn; 554 555 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 556 return (~0); 557 devfn = DEVFN(bus, slot, func); 558 559 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 560} 561 562static void 563fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 564 u_int reg, uint32_t val, int bytes) 565{ 566 struct fsl_pcib_softc *sc = device_get_softc(dev); 567 568 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 569 return; 570 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 571} 572 573static void 574fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start, 575 uint64_t size, uint64_t pci_start) 576{ 577 uint32_t attr, bar, tar; 578 579 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 580 581 attr = PIWAR_EN; 582 583 switch (tgt) { 584 case -1: 585 attr &= ~PIWAR_EN; 586 break; 587 case PIWAR_TRGT_LOCAL: 588 attr |= (ffsl(size) - 2); 589 default: 590 attr |= (tgt << PIWAR_TRGT_S); 591 break; 592 } 593 tar = start >> 12; 594 bar = pci_start >> 12; 595 596 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 597 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 598 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 599 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 600} 601 602static void 603fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start, 604 uint64_t size, uint64_t pci_start) 605{ 606 uint32_t attr, bar, tar; 607 608 switch (res) { 609 case SYS_RES_MEMORY: 610 attr = 0x80044000 | (ffsll(size) - 2); 611 break; 612 case SYS_RES_IOPORT: 613 attr = 0x80088000 | (ffsll(size) - 2); 614 break; 615 default: 616 attr = 0x0004401f; 617 break; 618 } 619 bar = start >> 12; 620 tar = pci_start >> 12; 621 622 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 623 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 624 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 625 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 626} 627 628static void 629fsl_pcib_err_init(device_t dev) 630{ 631 struct fsl_pcib_softc *sc; 632 uint16_t sec_stat, dsr; 633 uint32_t dcr, err_en; 634 635 sc = device_get_softc(dev); 636 637 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 638 if (sec_stat) 639 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 640 if (sc->sc_pcie) { 641 /* Clear error bits */ 642 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 643 0xffffffff); 644 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 645 0xffffffff); 646 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 647 0xffffffff); 648 649 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 650 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); 651 if (dsr) 652 fsl_pcib_cfgwrite(sc, 0, 0, 0, 653 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 654 0xffff, 2); 655 656 /* Enable all errors reporting */ 657 err_en = 0x00bfff00; 658 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 659 err_en); 660 661 /* Enable error reporting: URR, FER, NFER */ 662 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 663 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); 664 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | 665 PCIEM_CTL_NFER_ENABLE; 666 fsl_pcib_cfgwrite(sc, 0, 0, 0, 667 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); 668 } 669} 670 671static int 672fsl_pcib_detach(device_t dev) 673{ 674 struct fsl_pcib_softc *sc; 675 676 sc = device_get_softc(dev); 677 678 mtx_destroy(&sc->sc_cfg_mtx); 679 680 return (bus_generic_detach(dev)); 681} 682 683static int 684fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 685{ 686 device_t dev; 687 int error, i, trgt; 688 689 dev = sc->sc_dev; 690 691 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 692 693 /* 694 * Configure LAW decode windows. 695 */ 696 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 697 &sc->sc_ioport_target); 698 if (error != 0) { 699 device_printf(dev, "could not retrieve PCI LAW target info\n"); 700 return (error); 701 } 702 703 for (i = 0; i < sc->pci_sc.sc_nrange; i++) { 704 switch (sc->pci_sc.sc_range[i].pci_hi & 705 OFW_PCI_PHYS_HI_SPACEMASK) { 706 case OFW_PCI_PHYS_HI_SPACE_CONFIG: 707 continue; 708 case OFW_PCI_PHYS_HI_SPACE_IO: 709 trgt = sc->sc_ioport_target; 710 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT, 711 sc->pci_sc.sc_range[i].host, 712 sc->pci_sc.sc_range[i].size, 713 sc->pci_sc.sc_range[i].pci); 714 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci; 715 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci + 716 sc->pci_sc.sc_range[i].size - 1; 717 break; 718 case OFW_PCI_PHYS_HI_SPACE_MEM32: 719 case OFW_PCI_PHYS_HI_SPACE_MEM64: 720 trgt = sc->sc_iomem_target; 721 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY, 722 sc->pci_sc.sc_range[i].host, 723 sc->pci_sc.sc_range[i].size, 724 sc->pci_sc.sc_range[i].pci); 725 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci; 726 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci + 727 sc->pci_sc.sc_range[i].size - 1; 728 break; 729 default: 730 panic("Unknown range type %#x\n", 731 sc->pci_sc.sc_range[i].pci_hi & 732 OFW_PCI_PHYS_HI_SPACEMASK); 733 } 734 error = law_enable(trgt, sc->pci_sc.sc_range[i].host, 735 sc->pci_sc.sc_range[i].size); 736 if (error != 0) { 737 device_printf(dev, "could not program LAW for range " 738 "%d\n", i); 739 return (error); 740 } 741 } 742 743 /* 744 * Set outbout and inbound windows. 745 */ 746 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 747 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 748 749 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 750 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 751 fsl_pcib_inbound(sc, 3, PIWAR_TRGT_LOCAL, 0, 752 ptoa(Maxmem), 0); 753 754 /* Direct-map the CCSR for MSIs. */ 755 /* Freescale PCIe 2.x has a dedicated MSI window. */ 756 /* inbound window 8 makes it hit 0xD00 offset, the MSI window. */ 757 if (sc->sc_ip_maj >= 2) 758 fsl_pcib_inbound(sc, 8, PIWAR_TRGT_CCSR, ccsrbar_pa, 759 ccsrbar_size, ccsrbar_pa); 760 else 761 fsl_pcib_inbound(sc, 1, PIWAR_TRGT_CCSR, ccsrbar_pa, 762 ccsrbar_size, ccsrbar_pa); 763 764 return (0); 765} 766 767static int fsl_pcib_alloc_msi(device_t dev, device_t child, 768 int count, int maxcount, int *irqs) 769{ 770 struct fsl_pcib_softc *sc; 771 vmem_addr_t start; 772 int err, i; 773 774 sc = device_get_softc(dev); 775 if (msi_vmem == NULL) 776 return (ENODEV); 777 778 err = vmem_xalloc(msi_vmem, count, powerof2(count), 0, 0, 779 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start); 780 781 if (err) 782 return (err); 783 784 for (i = 0; i < count; i++) 785 irqs[i] = start + i; 786 787 return (0); 788} 789 790static int fsl_pcib_release_msi(device_t dev, device_t child, 791 int count, int *irqs) 792{ 793 if (msi_vmem == NULL) 794 return (ENODEV); 795 796 vmem_xfree(msi_vmem, irqs[0], count); 797 return (0); 798} 799 800static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq) 801{ 802 return (fsl_pcib_alloc_msi(dev, child, 1, 1, irq)); 803} 804 805static int fsl_pcib_release_msix(device_t dev, device_t child, int irq) 806{ 807 return (fsl_pcib_release_msi(dev, child, 1, &irq)); 808} 809 810static int fsl_pcib_map_msi(device_t dev, device_t child, 811 int irq, uint64_t *addr, uint32_t *data) 812{ 813 struct fsl_msi_map *mp; 814 815 SLIST_FOREACH(mp, &fsl_msis, slist) { 816 if (irq >= mp->irq_base && irq < mp->irq_base + FSL_NUM_MSIS) 817 break; 818 } 819 820 if (mp == NULL) 821 return (ENODEV); 822 823 *data = (irq & 255); 824 *addr = ccsrbar_pa + mp->target; 825 826 return (0); 827} 828 829/* 830 * Linux device trees put the msi@<x> as children of the SoC, with ranges based 831 * on the CCSR. Since rman doesn't permit overlapping or sub-ranges between 832 * devices (bus_space_subregion(9) could do it, but let's not touch the PIC 833 * driver just to allocate a subregion for a sibling driver). This driver will 834 * use ccsr_write() and ccsr_read() instead. 835 */ 836 837#define FSL_NUM_IRQS 8 838#define FSL_NUM_MSI_PER_IRQ 32 839#define FSL_MSI_TARGET 0x140 840 841struct fsl_msi_softc { 842 vm_offset_t sc_base; 843 vm_offset_t sc_target; 844 int sc_msi_base_irq; 845 struct fsl_msi_map sc_map; 846 struct fsl_msi_irq { 847 /* This struct gets passed as the filter private data. */ 848 struct fsl_msi_softc *sc_ptr; /* Pointer back to softc. */ 849 struct resource *res; 850 int irq; 851 void *cookie; 852 int vectors[FSL_NUM_MSI_PER_IRQ]; 853 vm_offset_t reg; 854 } sc_msi_irq[FSL_NUM_IRQS]; 855}; 856 857static int 858fsl_msi_intr_filter(void *priv) 859{ 860 struct fsl_msi_irq *data = priv; 861 uint32_t reg; 862 int i; 863 864 reg = ccsr_read4(ccsrbar_va + data->reg); 865 i = 0; 866 while (reg != 0) { 867 if (reg & 1) 868 powerpc_dispatch_intr(data->vectors[i], NULL); 869 reg >>= 1; 870 i++; 871 } 872 873 return (FILTER_HANDLED); 874} 875 876static int 877fsl_msi_probe(device_t dev) 878{ 879 if (!ofw_bus_is_compatible(dev, "fsl,mpic-msi")) 880 return (ENXIO); 881 882 device_set_desc(dev, "Freescale MSI"); 883 884 return (BUS_PROBE_DEFAULT); 885} 886 887static int 888fsl_msi_attach(device_t dev) 889{ 890 struct fsl_msi_softc *sc; 891 struct fsl_msi_irq *irq; 892 int i; 893 894 sc = device_get_softc(dev); 895 896 if (msi_vmem == NULL) 897 msi_vmem = vmem_create("MPIC MSI", 0, 0, 1, 0, M_BESTFIT | M_WAITOK); 898 899 /* Manually play with resource entries. */ 900 sc->sc_base = bus_get_resource_start(dev, SYS_RES_MEMORY, 0); 901 sc->sc_map.target = bus_get_resource_start(dev, SYS_RES_MEMORY, 1); 902 903 if (sc->sc_map.target == 0) 904 sc->sc_map.target = sc->sc_base + FSL_MSI_TARGET; 905 906 for (i = 0; i < FSL_NUM_IRQS; i++) { 907 irq = &sc->sc_msi_irq[i]; 908 irq->irq = i; 909 irq->reg = sc->sc_base + 16 * i; 910 irq->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 911 &irq->irq, RF_ACTIVE); 912 bus_setup_intr(dev, irq->res, INTR_TYPE_MISC | INTR_MPSAFE, 913 fsl_msi_intr_filter, NULL, irq, &irq->cookie); 914 } 915 sc->sc_map.irq_base = powerpc_register_pic(dev, ofw_bus_get_node(dev), 916 FSL_NUM_MSIS, 0, 0); 917 918 /* Let vmem and the IRQ subsystem work their magic for allocations. */ 919 vmem_add(msi_vmem, sc->sc_map.irq_base, FSL_NUM_MSIS, M_WAITOK); 920 921 SLIST_INSERT_HEAD(&fsl_msis, &sc->sc_map, slist); 922 923 return (0); 924} 925 926static void 927fsl_msi_enable(device_t dev, u_int irq, u_int vector, void **priv) 928{ 929 struct fsl_msi_softc *sc; 930 struct fsl_msi_irq *irqd; 931 932 sc = device_get_softc(dev); 933 934 irqd = &sc->sc_msi_irq[irq / FSL_NUM_MSI_PER_IRQ]; 935 irqd->vectors[irq % FSL_NUM_MSI_PER_IRQ] = vector; 936} 937 938static device_method_t fsl_msi_methods[] = { 939 DEVMETHOD(device_probe, fsl_msi_probe), 940 DEVMETHOD(device_attach, fsl_msi_attach), 941 942 DEVMETHOD(pic_enable, fsl_msi_enable), 943 DEVMETHOD_END 944}; 945 946static devclass_t fsl_msi_devclass; 947 948static driver_t fsl_msi_driver = { 949 "fsl_msi", 950 fsl_msi_methods, 951 sizeof(struct fsl_msi_softc) 952}; 953 954EARLY_DRIVER_MODULE(fsl_msi, simplebus, fsl_msi_driver, fsl_msi_devclass, 0, 0, 955 BUS_PASS_INTERRUPT + 1); 956