1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2009 Marcel Moolenaar
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD$");
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/cpuset.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/rman.h>
38
39#include <machine/bus.h>
40#include <machine/intr_machdep.h>
41#include <machine/pio.h>
42
43#include <powerpc/mpc85xx/mpc85xx.h>
44
45#include <dev/ic/i8259.h>
46
47#include <isa/isareg.h>
48#include <isa/isavar.h>
49
50#include "pic_if.h"
51
52#define	ATPIC_MASTER	0
53#define	ATPIC_SLAVE	1
54
55struct atpic_softc {
56	device_t	sc_dev;
57
58	/* I/O port resources for master & slave. */
59	struct resource	*sc_res[2];
60	int		sc_rid[2];
61
62	/* Our "routing" interrupt */
63	struct resource *sc_ires;
64	void		*sc_icookie;
65	int		sc_irid;
66
67	int		sc_vector[16];
68	uint8_t		sc_mask[2];
69};
70
71static int	atpic_isa_attach(device_t);
72static void	atpic_isa_identify(driver_t *, device_t);
73static int	atpic_isa_probe(device_t);
74
75static void atpic_config(device_t, u_int, enum intr_trigger,
76    enum intr_polarity);
77static void atpic_dispatch(device_t, struct trapframe *);
78static void atpic_enable(device_t, u_int, u_int);
79static void atpic_eoi(device_t, u_int);
80static void atpic_ipi(device_t, u_int);
81static void atpic_mask(device_t, u_int);
82static void atpic_unmask(device_t, u_int);
83
84static void atpic_ofw_translate_code(device_t, u_int irq, int code,
85    enum intr_trigger *trig, enum intr_polarity *pol);
86
87static device_method_t atpic_isa_methods[] = {
88	/* Device interface */
89	DEVMETHOD(device_identify, 	atpic_isa_identify),
90	DEVMETHOD(device_probe,		atpic_isa_probe),
91	DEVMETHOD(device_attach,	atpic_isa_attach),
92
93	/* PIC interface */
94	DEVMETHOD(pic_config,		atpic_config),
95	DEVMETHOD(pic_dispatch,		atpic_dispatch),
96	DEVMETHOD(pic_enable,		atpic_enable),
97	DEVMETHOD(pic_eoi,		atpic_eoi),
98	DEVMETHOD(pic_ipi,		atpic_ipi),
99	DEVMETHOD(pic_mask,		atpic_mask),
100	DEVMETHOD(pic_unmask,		atpic_unmask),
101
102	DEVMETHOD(pic_translate_code,	atpic_ofw_translate_code),
103
104	{ 0, 0 },
105};
106
107static driver_t atpic_isa_driver = {
108	"atpic",
109	atpic_isa_methods,
110	sizeof(struct atpic_softc)
111};
112
113static devclass_t atpic_devclass;
114
115static struct isa_pnp_id atpic_ids[] = {
116	{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
117	{ 0 }
118};
119
120DRIVER_MODULE(atpic, isa, atpic_isa_driver, atpic_devclass, 0, 0);
121ISA_PNP_INFO(atpic_ids);
122
123static __inline uint8_t
124atpic_read(struct atpic_softc *sc, int icu, int ofs)
125{
126	uint8_t val;
127
128	val = bus_read_1(sc->sc_res[icu], ofs);
129	return (val);
130}
131
132static __inline void
133atpic_write(struct atpic_softc *sc, int icu, int ofs, uint8_t val)
134{
135
136	bus_write_1(sc->sc_res[icu], ofs, val);
137	bus_barrier(sc->sc_res[icu], ofs, 2 - ofs,
138	    BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
139}
140
141static void
142atpic_intr(void *arg)
143{
144
145	atpic_dispatch(arg, NULL);
146}
147
148static void
149atpic_isa_identify(driver_t *drv, device_t parent)
150{
151	device_t child;
152
153	child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, drv->name, -1);
154	device_set_driver(child, drv);
155	isa_set_logicalid(child, atpic_ids[0].ip_id);
156	isa_set_vendorid(child, atpic_ids[0].ip_id);
157
158	bus_set_resource(child, SYS_RES_IOPORT, ATPIC_MASTER, IO_ICU1, 2);
159	bus_set_resource(child, SYS_RES_IOPORT, ATPIC_SLAVE, IO_ICU2, 2);
160
161	/* ISA interrupts are routed through external interrupt 0. */
162	bus_set_resource(child, SYS_RES_IRQ, 0, 16, 1);
163}
164
165static int
166atpic_isa_probe(device_t dev)
167{
168	int res;
169
170	res = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
171	if (res > 0)
172		return (res);
173
174	device_set_desc(dev, "PC/AT compatible PIC");
175	return (res);
176}
177
178static void
179atpic_init(struct atpic_softc *sc, int icu)
180{
181
182	sc->sc_mask[icu] = 0xff - ((icu == ATPIC_MASTER) ? 4 : 0);
183
184	atpic_write(sc, icu, 0, ICW1_RESET | ICW1_IC4);
185	atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 8 : 0);
186	atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 2 : 4);
187	atpic_write(sc, icu, 1, ICW4_8086);
188	atpic_write(sc, icu, 1, sc->sc_mask[icu]);
189	atpic_write(sc, icu, 0, OCW3_SEL | OCW3_RR);
190}
191
192static int
193atpic_isa_attach(device_t dev)
194{
195	struct atpic_softc *sc;
196	int error;
197
198	sc = device_get_softc(dev);
199	sc->sc_dev = dev;
200
201	error = ENXIO;
202
203	sc->sc_rid[ATPIC_MASTER] = 0;
204	sc->sc_res[ATPIC_MASTER] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
205	    &sc->sc_rid[ATPIC_MASTER], RF_ACTIVE);
206	if (sc->sc_res[ATPIC_MASTER] == NULL)
207		goto fail;
208
209	sc->sc_rid[ATPIC_SLAVE] = 1;
210	sc->sc_res[ATPIC_SLAVE] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
211	    &sc->sc_rid[ATPIC_SLAVE], RF_ACTIVE);
212	if (sc->sc_res[ATPIC_SLAVE] == NULL)
213		goto fail;
214
215	sc->sc_irid = 0;
216	sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
217	    RF_ACTIVE);
218	if (sc->sc_ires == NULL)
219		goto fail;
220
221	error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_MISC | INTR_MPSAFE,
222	    NULL, atpic_intr, dev, &sc->sc_icookie);
223	if (error)
224		goto fail;
225
226	atpic_init(sc, ATPIC_SLAVE);
227	atpic_init(sc, ATPIC_MASTER);
228
229	powerpc_register_pic(dev, 0, 16, 0, TRUE);
230	return (0);
231
232 fail:
233	if (sc->sc_ires != NULL)
234		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
235		    sc->sc_ires);
236	if (sc->sc_res[ATPIC_SLAVE] != NULL)
237		bus_release_resource(dev, SYS_RES_IOPORT,
238		    sc->sc_rid[ATPIC_SLAVE], sc->sc_res[ATPIC_SLAVE]);
239	if (sc->sc_res[ATPIC_MASTER] != NULL)
240		bus_release_resource(dev, SYS_RES_IOPORT,
241		    sc->sc_rid[ATPIC_MASTER], sc->sc_res[ATPIC_MASTER]);
242	return (error);
243}
244
245/*
246 * PIC interface.
247 */
248
249static void
250atpic_config(device_t dev, u_int irq, enum intr_trigger trig,
251    enum intr_polarity pol)
252{
253}
254
255static void
256atpic_dispatch(device_t dev, struct trapframe *tf)
257{
258	struct atpic_softc *sc;
259	uint8_t irq;
260
261	sc = device_get_softc(dev);
262	atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_P);
263	irq = atpic_read(sc, ATPIC_MASTER, 0);
264	atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_RR);
265	if ((irq & 0x80) == 0)
266		return;
267
268	if (irq == 0x82) {
269		atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_P);
270		irq = atpic_read(sc, ATPIC_SLAVE, 0) + 8;
271		atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_RR);
272		if ((irq & 0x80) == 0)
273			return;
274	}
275
276	powerpc_dispatch_intr(sc->sc_vector[irq & 0x0f], tf);
277}
278
279static void
280atpic_enable(device_t dev, u_int irq, u_int vector)
281{
282	struct atpic_softc *sc;
283
284	sc = device_get_softc(dev);
285	sc->sc_vector[irq] = vector;
286	atpic_unmask(dev, irq);
287}
288
289static void
290atpic_eoi(device_t dev, u_int irq)
291{
292	struct atpic_softc *sc;
293
294	sc = device_get_softc(dev);
295	if (irq > 7)
296		atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI);
297	atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI);
298}
299
300static void
301atpic_ipi(device_t dev, u_int cpu)
302{
303	/* No SMP support. */
304}
305
306static void
307atpic_mask(device_t dev, u_int irq)
308{
309	struct atpic_softc *sc;
310
311	sc = device_get_softc(dev);
312	if (irq > 7) {
313		sc->sc_mask[ATPIC_SLAVE] |= 1 << (irq - 8);
314		atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
315	} else {
316		sc->sc_mask[ATPIC_MASTER] |= 1 << irq;
317		atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
318	}
319}
320
321static void
322atpic_unmask(device_t dev, u_int irq)
323{
324	struct atpic_softc *sc;
325
326	sc = device_get_softc(dev);
327	if (irq > 7) {
328		sc->sc_mask[ATPIC_SLAVE] &= ~(1 << (irq - 8));
329		atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
330	} else {
331		sc->sc_mask[ATPIC_MASTER] &= ~(1 << irq);
332		atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
333	}
334}
335
336static void
337atpic_ofw_translate_code(device_t dev, u_int irq, int code,
338    enum intr_trigger *trig, enum intr_polarity *pol)
339{
340	switch (code) {
341	case 0:
342		/* Active L level */
343		*trig = INTR_TRIGGER_LEVEL;
344		*pol = INTR_POLARITY_LOW;
345		break;
346	case 1:
347		/* Active H level */
348		*trig = INTR_TRIGGER_LEVEL;
349		*pol = INTR_POLARITY_HIGH;
350		break;
351	case 2:
352		/* H to L edge */
353		*trig = INTR_TRIGGER_EDGE;
354		*pol = INTR_POLARITY_LOW;
355		break;
356	case 3:
357		/* L to H edge */
358		*trig = INTR_TRIGGER_EDGE;
359		*pol = INTR_POLARITY_HIGH;
360		break;
361	default:
362		*trig = INTR_TRIGGER_CONFORM;
363		*pol = INTR_POLARITY_CONFORM;
364	}
365}
366