1/*-
2 * Copyright (c) 2017 Justin Hibbits
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD$");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/cpu.h>
34#include <sys/kernel.h>
35#include <sys/module.h>
36#include <sys/smp.h>
37
38#include <dev/ofw/ofw_bus.h>
39#include <dev/ofw/ofw_bus_subr.h>
40
41#include <machine/cpu.h>
42
43#include <powerpc/mpc85xx/mpc85xx.h>
44
45#include "cpufreq_if.h"
46
47/* No worries about uint32_t math overflow in here, because the highest
48 * multiplier supported is 4, and the highest speed part is still well below
49 * 2GHz.
50 */
51
52#define	GUTS_PORPLLSR		(CCSRBAR_VA + 0xe0000)
53#define	GUTS_PMJCR		(CCSRBAR_VA + 0xe007c)
54#define	  PMJCR_RATIO_M		  0x3f
55#define	  PMJCR_CORE_MULT(x,y)	  ((x) << (16 + ((y) * 8)))
56#define	  PMJCR_GET_CORE_MULT(x,y)	  (((x) >> (16 + ((y) * 8))) & 0x3f)
57#define	GUTS_POWMGTCSR		(CCSRBAR_VA + 0xe0080)
58#define	  POWMGTCSR_JOG		  0x00200000
59#define	  POWMGTCSR_INT_MASK	  0x00000f00
60
61#define	MHZ	1000000
62
63struct mpc85xx_jog_softc {
64	device_t dev;
65	int	cpu;
66	int	low;
67	int	high;
68	int	min_freq;
69};
70
71static struct ofw_compat_data *mpc85xx_jog_devcompat(void);
72static void	mpc85xx_jog_identify(driver_t *driver, device_t parent);
73static int	mpc85xx_jog_probe(device_t dev);
74static int	mpc85xx_jog_attach(device_t dev);
75static int	mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count);
76static int	mpc85xx_jog_set(device_t dev, const struct cf_setting *set);
77static int	mpc85xx_jog_get(device_t dev, struct cf_setting *set);
78static int	mpc85xx_jog_type(device_t dev, int *type);
79
80static device_method_t mpc85xx_jog_methods[] = {
81	/* Device interface */
82	DEVMETHOD(device_identify,	mpc85xx_jog_identify),
83	DEVMETHOD(device_probe,		mpc85xx_jog_probe),
84	DEVMETHOD(device_attach,	mpc85xx_jog_attach),
85
86	/* cpufreq interface */
87	DEVMETHOD(cpufreq_drv_set,	mpc85xx_jog_set),
88	DEVMETHOD(cpufreq_drv_get,	mpc85xx_jog_get),
89	DEVMETHOD(cpufreq_drv_type,	mpc85xx_jog_type),
90	DEVMETHOD(cpufreq_drv_settings,	mpc85xx_jog_settings),
91	{0, 0}
92};
93
94static driver_t mpc85xx_jog_driver = {
95	"jog",
96	mpc85xx_jog_methods,
97	sizeof(struct mpc85xx_jog_softc)
98};
99
100static devclass_t mpc85xx_jog_devclass;
101DRIVER_MODULE(mpc85xx_jog, cpu, mpc85xx_jog_driver, mpc85xx_jog_devclass, 0, 0);
102
103struct mpc85xx_constraints {
104	int threshold; /* Threshold frequency, in MHz, for setting CORE_SPD bit. */
105	int min_mult;  /* Minimum PLL multiplier. */
106};
107
108static struct mpc85xx_constraints mpc8536_constraints = {
109	800,
110	3
111};
112
113static struct mpc85xx_constraints p1022_constraints = {
114	500,
115	2
116};
117
118static struct ofw_compat_data jog_compat[] = {
119    {"fsl,mpc8536-guts", (uintptr_t)&mpc8536_constraints},
120    {"fsl,p1022-guts", (uintptr_t)&p1022_constraints},
121    {NULL, 0}
122};
123
124static struct ofw_compat_data *
125mpc85xx_jog_devcompat()
126{
127	phandle_t node;
128	int i;
129
130	node = OF_finddevice("/soc");
131	if (node == -1)
132		return (NULL);
133
134	for (i = 0; jog_compat[i].ocd_str != NULL; i++)
135		if (ofw_bus_find_compatible(node, jog_compat[i].ocd_str) > 0)
136			break;
137
138	if (jog_compat[i].ocd_str == NULL)
139		return (NULL);
140
141	return (&jog_compat[i]);
142}
143
144static void
145mpc85xx_jog_identify(driver_t *driver, device_t parent)
146{
147	struct ofw_compat_data *compat;
148
149	/* Make sure we're not being doubly invoked. */
150	if (device_find_child(parent, "mpc85xx_jog", -1) != NULL)
151		return;
152
153	compat = mpc85xx_jog_devcompat();
154	if (compat == NULL)
155		return;
156
157	/*
158	 * We attach a child for every CPU since settings need to
159	 * be performed on every CPU in the SMP case.
160	 */
161	if (BUS_ADD_CHILD(parent, 10, "jog", -1) == NULL)
162		device_printf(parent, "add jog child failed\n");
163}
164
165static int
166mpc85xx_jog_probe(device_t dev)
167{
168	struct ofw_compat_data *compat;
169
170	compat = mpc85xx_jog_devcompat();
171	if (compat == NULL || compat->ocd_str == NULL)
172		return (ENXIO);
173
174	device_set_desc(dev, "Freescale CPU Jogger");
175	return (0);
176}
177
178static int
179mpc85xx_jog_attach(device_t dev)
180{
181	struct ofw_compat_data *compat;
182	struct mpc85xx_jog_softc *sc;
183	struct mpc85xx_constraints *constraints;
184	phandle_t cpu;
185	uint32_t reg;
186
187	sc = device_get_softc(dev);
188	sc->dev = dev;
189
190	compat = mpc85xx_jog_devcompat();
191	constraints = (struct mpc85xx_constraints *)compat->ocd_data;
192	cpu = ofw_bus_get_node(device_get_parent(dev));
193
194	if (cpu <= 0) {
195		device_printf(dev,"No CPU device tree node!\n");
196		return (ENXIO);
197	}
198
199	OF_getencprop(cpu, "reg", &sc->cpu, sizeof(sc->cpu));
200
201	reg = ccsr_read4(GUTS_PORPLLSR);
202
203	/*
204	 * Assume power-on PLL is the highest PLL config supported on the
205	 * board.
206	 */
207	sc->high = PMJCR_GET_CORE_MULT(reg, sc->cpu);
208	sc->min_freq = constraints->threshold;
209	sc->low = constraints->min_mult;
210
211	cpufreq_register(dev);
212	return (0);
213}
214
215static int
216mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count)
217{
218	struct mpc85xx_jog_softc *sc;
219	uint32_t sysclk;
220	int i;
221
222	sc = device_get_softc(dev);
223	if (sets == NULL || count == NULL)
224		return (EINVAL);
225	if (*count < sc->high - 1)
226		return (E2BIG);
227
228	sysclk = mpc85xx_get_system_clock();
229	/* Return a list of valid settings for this driver. */
230	memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->high);
231
232	for (i = sc->high; i >= sc->low; --i) {
233		sets[sc->high - i].freq = sysclk * i / MHZ;
234		sets[sc->high - i].dev = dev;
235		sets[sc->high - i].spec[0] = i;
236	}
237	*count = sc->high - sc->low + 1;
238
239	return (0);
240}
241
242struct jog_rv_args {
243	int cpu;
244	int mult;
245	int slow;
246	volatile int inprogress;
247};
248
249static void
250mpc85xx_jog_set_int(void *arg)
251{
252	struct jog_rv_args *args = arg;
253	uint32_t reg;
254
255	if (PCPU_GET(cpuid) == args->cpu) {
256		reg = ccsr_read4(GUTS_PMJCR);
257		reg &= ~PMJCR_CORE_MULT(PMJCR_RATIO_M, args->cpu);
258		reg |= PMJCR_CORE_MULT(args->mult, args->cpu);
259		if (args->slow)
260			reg &= ~(1 << (12 + args->cpu));
261		else
262			reg |= (1 << (12 + args->cpu));
263
264		ccsr_write4(GUTS_PMJCR, reg);
265
266		reg = ccsr_read4(GUTS_POWMGTCSR);
267		reg |= POWMGTCSR_JOG | POWMGTCSR_INT_MASK;
268		ccsr_write4(GUTS_POWMGTCSR, reg);
269
270		/* Wait for completion */
271		do {
272			DELAY(100);
273			reg = ccsr_read4(GUTS_POWMGTCSR);
274		} while (reg & POWMGTCSR_JOG);
275
276		reg = ccsr_read4(GUTS_POWMGTCSR);
277		ccsr_write4(GUTS_POWMGTCSR, reg & ~POWMGTCSR_INT_MASK);
278		ccsr_read4(GUTS_POWMGTCSR);
279
280		args->inprogress = 0;
281	} else {
282		while (args->inprogress)
283			cpu_spinwait();
284	}
285}
286
287static int
288mpc85xx_jog_set(device_t dev, const struct cf_setting *set)
289{
290	struct mpc85xx_jog_softc *sc;
291	struct jog_rv_args args;
292
293	if (set == NULL)
294		return (EINVAL);
295
296	sc = device_get_softc(dev);
297
298	args.slow = (set->freq <= sc->min_freq);
299	args.mult = set->spec[0];
300	args.cpu = PCPU_GET(cpuid);
301	args.inprogress = 1;
302	smp_rendezvous(smp_no_rendezvous_barrier, mpc85xx_jog_set_int,
303	    smp_no_rendezvous_barrier, &args);
304
305	return (0);
306}
307
308static int
309mpc85xx_jog_get(device_t dev, struct cf_setting *set)
310{
311	struct mpc85xx_jog_softc *sc;
312	uint32_t pmjcr;
313	uint32_t freq;
314
315	if (set == NULL)
316		return (EINVAL);
317
318	sc = device_get_softc(dev);
319	memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
320
321	pmjcr = ccsr_read4(GUTS_PORPLLSR);
322	freq = PMJCR_GET_CORE_MULT(pmjcr, sc->cpu);
323	freq *= mpc85xx_get_system_clock();
324	freq /= MHZ;
325
326	set->freq = freq;
327	set->dev = dev;
328
329	return (0);
330}
331
332static int
333mpc85xx_jog_type(device_t dev, int *type)
334{
335
336	if (type == NULL)
337		return (EINVAL);
338
339	*type = CPUFREQ_TYPE_ABSOLUTE;
340	return (0);
341}
342