1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003-2012 Broadcom Corporation 5 * All Rights Reserved 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 25 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 26 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 27 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 28 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32#ifndef _NLM_HAL_GBU_H__ 33#define _NLM_HAL_GBU_H__ 34 35/* Global Bus Unit (GBU) for flash Specific registers */ 36 37#define GBU_CS_BASEADDR(cs) (0x0+cs) 38#define GBU_CS0_BASEADDR 0x0 39#define GBU_CS1_BASEADDR 0x1 40#define GBU_CS2_BASEADDR 0x2 41#define GBU_CS3_BASEADDR 0x3 42#define GBU_CS4_BASEADDR 0x4 43#define GBU_CS5_BASEADDR 0x5 44#define GBU_CS6_BASEADDR 0x6 45#define GBU_CS7_BASEADDR 0x7 46#define GBU_CS_BASELIMIT(cs) (0x8+cs) 47#define GBU_CS0_BASELIMIT 0x8 48#define GBU_CS1_BASELIMIT 0x9 49#define GBU_CS2_BASELIMIT 0xa 50#define GBU_CS3_BASELIMIT 0xb 51#define GBU_CS4_BASELIMIT 0xc 52#define GBU_CS5_BASELIMIT 0xd 53#define GBU_CS6_BASELIMIT 0xe 54#define GBU_CS7_BASELIMIT 0xf 55#define GBU_CS_DEVPARAM(cs) (0x10+cs) 56#define GBU_CS0_DEVPARAM 0x10 57#define GBU_CS1_DEVPARAM 0x11 58#define GBU_CS2_DEVPARAM 0x12 59#define GBU_CS3_DEVPARAM 0x13 60#define GBU_CS4_DEVPARAM 0x14 61#define GBU_CS5_DEVPARAM 0x15 62#define GBU_CS6_DEVPARAM 0x16 63#define GBU_CS7_DEVPARAM 0x17 64#define GBU_CS_DEVTIME0(cs) (0x18+cs) 65#define GBU_CS0_DEVTIME0 0x18 66#define GBU_CS1_DEVTIME0 0x1a 67#define GBU_CS2_DEVTIME0 0x1c 68#define GBU_CS3_DEVTIME0 0x1e 69#define GBU_CS4_DEVTIME0 0x20 70#define GBU_CS5_DEVTIME0 0x22 71#define GBU_CS6_DEVTIME0 0x24 72#define GBU_CS7_DEVTIME0 0x26 73#define GBU_CS_DEVTIME1(cs) (0x19+cs) 74#define GBU_CS0_DEVTIME1 0x19 75#define GBU_CS1_DEVTIME1 0x1b 76#define GBU_CS2_DEVTIME1 0x1d 77#define GBU_CS3_DEVTIME1 0x1f 78#define GBU_CS4_DEVTIME1 0x21 79#define GBU_CS5_DEVTIME1 0x23 80#define GBU_CS6_DEVTIME1 0x25 81#define GBU_CS7_DEVTIME1 0x27 82#define GBU_SYSCTRL 0x28 83#define GBU_BYTESWAP 0x29 84#define GBU_DI_TIMEOUT_VAL 0x2d 85#define GBU_INTSTAT 0x2e 86#define GBU_INTEN 0x2f 87#define GBU_STATUS 0x30 88#define GBU_ERRLOG0 0x2a 89#define GBU_ERRLOG1 0x2b 90#define GBU_ERRLOG2 0x2c 91 92#if !defined(LOCORE) && !defined(__ASSEMBLY__) 93 94#define nlm_read_gbu_reg(b, r) nlm_read_reg(b, r) 95#define nlm_write_gbu_reg(b, r, v) nlm_write_reg(b, r, v) 96#define nlm_get_gbu_pcibase(node) \ 97 nlm_pcicfg_base(XLP_IO_NOR_OFFSET(node)) 98#define nlm_get_gbu_regbase(node) \ 99 (nlm_get_gbu_pcibase(node) + XLP_IO_PCI_HDRSZ) 100 101#endif /* !LOCORE && !__ASSEMBLY__ */ 102#endif /* _NLM_HAL_GBU_H__ */ 103