1#
2# This file adds to the values in AR91XX_BASE.hints.
3#
4# $FreeBSD$
5
6# mdiobus on arge1
7hint.argemdio.0.at="nexus0"
8hint.argemdio.0.maddr=0x1a000000
9hint.argemdio.0.msize=0x1000
10hint.argemdio.0.order=0
11
12# Embedded Atheros Switch
13hint.arswitch.0.at="mdio0"
14
15# XXX this should really say it's an AR933x switch, as there
16# are some vlan specific differences here!
17hint.arswitch.0.is_7240=1
18hint.arswitch.0.numphys=4
19hint.arswitch.0.phy4cpu=1	# phy 4 is a "CPU" separate PHY
20hint.arswitch.0.is_rgmii=0
21hint.arswitch.0.is_gmii=1	# arge1 <-> switch PHY is GMII
22
23# arge0 - MII, autoneg, phy(4)
24hint.arge.0.phymask=0x10	# PHY4
25hint.arge.0.mdio=mdioproxy1	# .. off of the switch mdiobus
26hint.arge.0.eeprommac=0x1fff0000
27
28# arge1 - GMII, 1000/full
29hint.arge.1.phymask=0x0		# No directly mapped PHYs
30hint.arge.1.media=1000
31hint.arge.1.fduplex=1
32hint.arge.1.eeprommac=0x1fff0006
33
34
35# ART calibration data mapping
36hint.ar71xx_caldata.0.at="nexus0"
37hint.ar71xx_caldata.0.order=0
38# Where the ART is - last 64k in the first 8MB of flash
39hint.ar71xx_caldata.0.map.0.ath_fixup_addr=0x1fff0000
40hint.ar71xx_caldata.0.map.0.ath_fixup_size=16384
41
42# And now tell the ath(4) driver where to look!
43hint.ath.0.eeprom_firmware="ar71xx_caldata.0.map.0.eeprom_firmware"
44
45# The AP121 16MB flash layout:
46#
47# [    0.700000] 0x000000000000-0x000000040000 : "u-boot"
48# [    0.710000] 0x000000040000-0x000000050000 : "u-boot-env"
49# [    0.710000] 0x000000050000-0x000000250000 : "kernel"
50# [    0.720000] 0x000000250000-0x000000fe0000 : "rootfs"
51# [    0.720000] mtd: partition "rootfs" set to be root filesystem
52# [    0.730000] mtd: partition "rootfs_data" created automatically, ofs=480000, len=B60000 
53# [    0.740000] 0x000000480000-0x000000fe0000 : "rootfs_data"
54# [    0.740000] 0x000000fe0000-0x000000ff0000 : "nvram"
55# [    0.750000] 0x000000ff0000-0x000001000000 : "art"
56# [    0.750000] 0x000000050000-0x000000fe0000 : "firmware"
57
58hint.map.0.at="flash/spi0"
59hint.map.0.start=0x00000000
60hint.map.0.end=0x000040000
61hint.map.0.name="uboot"
62hint.map.0.readonly=1
63
64hint.map.1.at="flash/spi0"
65hint.map.1.start=0x00040000
66hint.map.1.end=0x00050000
67hint.map.1.name="uboot-env"
68hint.map.1.readonly=0
69
70hint.map.2.at="flash/spi0"
71hint.map.2.start=0x00050000
72hint.map.2.end="search:0x00050000:0x10000:.!/bin/sh"
73hint.map.2.name="kernel"
74hint.map.2.readonly=0
75
76hint.map.3.at="flash/spi0"
77hint.map.3.start="search:0x00050000:0x10000:.!/bin/sh"
78hint.map.3.end=0x00fe0000
79hint.map.3.name="rootfs"
80hint.map.3.readonly=0
81
82hint.map.4.at="flash/spi0"
83hint.map.4.start=0x00fe0000
84hint.map.4.end=0x00ff0000
85hint.map.4.name="cfg"
86hint.map.4.readonly=0
87
88# This is radio calibration section.  It is (or should be!) unique
89# for each board, to take into account thermal and electrical differences
90# as well as the regulatory compliance data.
91#
92hint.map.5.at="flash/spi0"
93hint.map.5.start=0x00ff0000
94hint.map.5.end=0x01000000
95hint.map.5.name="art"
96hint.map.5.readonly=1
97
98# GPIO specific configuration block
99
100# Don't flip on anything that isn't already enabled.
101# This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're
102# not used here.
103hint.gpio.0.function_set=0x00000000
104hint.gpio.0.function_clear=0x00000000
105
106# These are the GPIO LEDs and buttons which can be software controlled.
107hint.gpio.0.pinmask=0x00fc1803
108