1/*-
2 * Copyright 2000,2001,2002,2003 Broadcom Corporation.
3 * All rights reserved.
4 *
5 * This file is derived from the sbmips32.h header distributed
6 * by Broadcom with the CFE 1.4.2 sources.
7 *
8 * This software is furnished under license and may be used and
9 * copied only in accordance with the following terms and
10 * conditions.  Subject to these conditions, you may download,
11 * copy, install, use, modify and distribute modified or unmodified
12 * copies of this software in source and/or binary form.  No title
13 * or ownership is transferred hereby.
14 *
15 * 1) Any source code used, modified or distributed must reproduce
16 *    and retain this copyright notice and list of conditions
17 *    as they appear in the source file.
18 *
19 * 2) No right is granted to use any trade name, trademark, or
20 *    logo of Broadcom Corporation.  The "Broadcom Corporation"
21 *    name may not be used to endorse or promote products derived
22 *    from this software without the prior written permission of
23 *    Broadcom Corporation.
24 *
25 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
26 *    IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
27 *    WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
28 *    PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
29 *    SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
30 *    PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
31 *    INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32 *    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
33 *    GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
34 *    BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
35 *    OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 *    TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
37 *    THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 * $FreeBSD$
40 */
41
42/*  *********************************************************************
43    *  Broadcom Common Firmware Environment (CFE)
44    *
45    *  MIPS32 CPU definitions			File: sbmips32.h
46    *
47    *  This module contains constants and macros specific to the
48    *  Broadcom MIPS32 core.  In addition to generic MIPS32, it
49    *  includes definitions for the MIP32-01 and MIPS3302 OCP cores
50    *  for the Silicon Backplane.
51    *
52    *********************************************************************/
53
54#ifndef _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_
55#define _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_
56
57#include <machine/cpufunc.h>
58
59/*
60 * The following Broadcom Custom CP0 Registers appear in the Broadcom
61 * BMIPS330x MIPS32 core.
62 */
63
64#define	BMIPS_COP_0_BCMCFG	22
65
66/*
67 * Custom CP0 Accessors
68 */
69
70#define	BCM_BMIPS_RW32_COP0_SEL(n,r,s)				\
71static __inline uint32_t					\
72bcm_bmips_rd_ ## n(void)					\
73{								\
74	int v0;							\
75	__asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";"	\
76			  : [v0] "=&r"(v0));			\
77	mips_barrier();						\
78	return (v0);						\
79}								\
80static __inline void						\
81bcm_bmips_wr_ ## n(uint32_t a0)					\
82{								\
83	__asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";"	\
84			 __XSTRING(COP0_SYNC)";"		\
85			 "nop;"					\
86			 "nop;"					\
87			 :					\
88			 : [a0] "r"(a0));			\
89	mips_barrier();						\
90} struct __hack
91
92BCM_BMIPS_RW32_COP0_SEL(pllcfg1,	MIPS_COP_0_CONFIG,	1);
93BCM_BMIPS_RW32_COP0_SEL(pllcfg2,	MIPS_COP_0_CONFIG,	2);
94BCM_BMIPS_RW32_COP0_SEL(clksync,	MIPS_COP_0_CONFIG,	3);
95BCM_BMIPS_RW32_COP0_SEL(pllcfg3,	MIPS_COP_0_CONFIG,	4);
96BCM_BMIPS_RW32_COP0_SEL(rstcfg,		MIPS_COP_0_CONFIG,	5);
97
98/*
99 * Broadcom PLLConfig1 Register (22, select 1)
100 */
101
102/* SoftMIPSPLLCfg */
103#define	BMIPS_BCMCFG_PLLCFG1_MC_SHIFT	10
104#define	BMIPS_BCMCFG_PLLCFG1_MC_MASK	0xFFFFFC00
105
106/* SoftISBPLLCfg */
107#define	BMIPS_BCMCFG_PLLCFG1_BC_SHIFT	5
108#define	BMIPS_BCMCFG_PLLCFG1_BC_MASK	0x000003E0
109
110/* SoftRefPLLCfg */
111#define	BMIPS_BCMCFG_PLLCFG1_PC_SHIFT	0
112#define	BMIPS_BCMCFG_PLLCFG1_PC_MASK	0x0000001F
113
114/*
115 * Broadcom PLLConfig2 Register (22, select 2)
116 */
117
118/* Soft1to1ClkRatio */
119#define	BMIPS_BCMCFG_PLLCFG2_CR		(1<<23)
120
121/* SoftUSBxPLLCfg */
122#define	BMIPS_BCMCFG_PLLCFG2_UC_SHIFT	15
123#define	BMIPS_BCMCFG_PLLCFG2_UC_MASK	0x007F8000
124
125/* SoftIDExPLLCfg */
126#define	BMIPS_BCMCFG_PLLCFG2_IC_SHIFT	7
127#define	BMIPS_BCMCFG_PLLCFG2_IC_MASK	0x00007F80
128
129#define	BMIPS_BCMCFG_PLLCFG2_BE		(1<<6)	/* ISBxSoftCfgEnable */
130#define	BMIPS_BCMCFG_PLLCFG2_UE		(1<<5)	/* USBxSoftCfgEnable */
131#define	BMIPS_BCMCFG_PLLCFG2_IE		(1<<4)	/* IDExSoftCfgEnable */
132#define	BMIPS_BCMCFG_PLLCFG2_CA		(1<<3)	/* CfgActive */
133#define	BMIPS_BCMCFG_PLLCFG2_CF		(1<<2)	/* RefSoftCfgEnable */
134#define	BMIPS_BCMCFG_PLLCFG2_CI		(1<<1)	/* ISBSoftCfgEnable */
135#define	BMIPS_BCMCFG_PLLCFG2_CC		(1<<0)	/* MIPSSoftCfgEnable */
136
137/*
138 * Broadcom ClkSync Register (22, select 3)
139 */
140/* SoftClkCfgHigh */
141#define	BMIPS_BCMCFG_CLKSYNC_CH_SHIFT	16
142#define	BMIPS_BCMCFG_CLKSYNC_CH_MASK	0xFFFF0000
143
144/* SoftClkCfgLow */
145#define	BMIPS_BCMCFG_CLKSYNC_CL_SHIFT	0
146#define	BMIPS_BCMCFG_CLKSYNC_CL_MASK	0x0000FFFF
147
148/*
149 * Broadcom ISBxPLLConfig3 Register (22, select 4)
150 */
151
152/* AsyncClkRatio */
153#define	BMIPS_BCMCFG_PLLCFG3_AR_SHIFT	23
154#define	BMIPS_BCMCFG_PLLCFG3_AR_MASK	0x01800000
155
156#define	BMIPS_BCMCFG_PLLCFG3_SM		(1<<22)	/* SyncMode */
157
158/* SoftISBxPLLCfg */
159#define	BMIPS_BCMCFG_PLLCFG3_IC_SHIFT	0
160#define	BMIPS_BCMCFG_PLLCFG3_IC_MASK	0x003FFFFF
161
162/*
163 * Broadcom BRCMRstConfig Register (22, select 5)
164 */
165
166#define	BMIPS_BCMCFG_RSTCFG_SR		(1<<18)	/* SSMR */
167#define	BMIPS_BCMCFG_RSTCFG_DT		(1<<16)	/* BHTD */
168
169/* RStSt */
170#define	BMIPS_BCMCFG_RSTCFG_RS_SHIFT	8
171#define	BMIPS_BCMCFG_RSTCFG_RS_MASK	0x00001F00
172#define	  BMIPS_BCMCFG_RST_OTHER	0x00
173#define	  BMIPS_BCMCFG_RST_SH		0x01
174#define	  BMIPS_BCMCFG_RST_SS		0x02
175#define	  BMIPS_BCMCFG_RST_EJTAG	0x04
176#define	  BMIPS_BCMCFG_RST_WDOG		0x08
177#define	  BMIPS_BCMCFG_RST_CRC		0x10
178
179#define	BMIPS_BCMCFG_RSTCFG_CR		(1<<7)	/* RStCr */
180
181/* WBMD */
182#define	BMIPS_BCMCFG_RSTCFG_WD_SHIFT	3
183#define	BMIPS_BCMCFG_RSTCFG_WD_MASK	0x00000078
184
185#define	BMIPS_BCMCFG_RSTCFG_SS		(1<<2)	/* SSR */
186#define	BMIPS_BCMCFG_RSTCFG_SH		(1<<1)	/* SHR */
187#define	BMIPS_BCMCFG_RSTCFG_BR		(1<<0)	/* BdR */
188
189#endif /* _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_ */
190