1/* $FreeBSD$ */ 2/*- 3 * Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org> 4 * All rights reserved. 5 * 6 * This software was developed by SRI International and the University of 7 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 8 * ("CTSRD"), as part of the DARPA CRASH research programme. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#ifndef _SAF1761_OTG_REG_H_ 33#define _SAF1761_OTG_REG_H_ 34 35/* Global registers */ 36 37#define SOTG_VEND_PROD_ID 0x370 38#define SOTG_VEND_ID(x) ((x) & 0xFFFF) 39#define SOTG_PROD_ID(x) (((x) >> 16) & 0xFFFF) 40#define SOTG_CTRL_SET_CLR 0x374 41#define SOTG_CTRL_SET(x) ((x) & 0xFFFF) 42#define SOTG_CTRL_CLR(x) (((x) << 16) & 0xFFFF0000) 43#define SOTG_CTRL_OTG_DISABLE (1 << 10) 44#define SOTG_CTRL_OTG_SE0_EN (1 << 9) 45#define SOTG_CTRL_BDIS_ACON_EN (1 << 8) 46#define SOTG_CTRL_SW_SEL_HC_DC (1 << 7) 47#define SOTG_CTRL_VBUS_CHRG (1 << 6) 48#define SOTG_CTRL_VBUS_DISCHRG (1 << 5) 49#define SOTG_CTRL_VBUS_DRV (1 << 4) 50#define SOTG_CTRL_SEL_CP_EXT (1 << 3) 51#define SOTG_CTRL_DM_PULL_DOWN (1 << 2) 52#define SOTG_CTRL_DP_PULL_DOWN (1 << 1) 53#define SOTG_CTRL_DP_PULL_UP (1 << 0) 54#define SOTG_STATUS 0x378 55#define SOTG_STATUS_B_SE0_SRP (1 << 8) 56#define SOTG_STATUS_B_SESS_END (1 << 7) 57#define SOTG_STATUS_RMT_CONN (1 << 4) 58#define SOTG_STATUS_ID (1 << 3) 59#define SOTG_STATUS_DP_SRP (1 << 2) 60#define SOTG_STATUS_A_B_SESS_VLD (1 << 1) 61#define SOTG_STATUS_VBUS_VLD (1 << 0) 62#define SOTG_IRQ_LATCH_SET_CLR 0x37C 63#define SOTG_IRQ_LATCH_SET(x) ((x) & 0xFFFF) 64#define SOTG_IRQ_LATCH_CLR(x) (((x) << 16) & 0xFFFF0000) 65#define SOTG_IRQ_ENABLE_SET_CLR 0x380 66#define SOTG_IRQ_ENABLE_SET(x) ((x) & 0xFFFF) 67#define SOTG_IRQ_ENABLE_CLR(x) (((x) << 16) & 0xFFFF0000) 68#define SOTG_IRQ_RISE_SET_CLR 0x384 69#define SOTG_IRQ_RISE_SET(x) ((x) & 0xFFFF) 70#define SOTG_IRQ_RISE_CLR(x) (((x) << 16) & 0xFFFF0000) 71#define SOTG_IRQ_OTG_TMR_TIMEOUT (1 << 9) 72#define SOTG_IRQ_B_SE0_SRP (1 << 8) 73#define SOTG_IRQ_B_SESS_END (1 << 7) 74#define SOTG_IRQ_BDIS_ACON (1 << 6) 75#define SOTG_IRQ_OTG_RESUME (1 << 5) 76#define SOTG_IRQ_RMT_CONN (1 << 4) 77#define SOTG_IRQ_ID (1 << 3) 78#define SOTG_IRQ_DP_SRP (1 << 2) 79#define SOTG_IRQ_A_B_SESS_VLD (1 << 1) 80#define SOTG_IRQ_VBUS_VLD (1 << 0) 81#define SOTG_TIMER_LOW_SET_CLR 0x388 82#define SOTG_TIMER_LOW_SET(x) ((x) & 0xFFFF) 83#define SOTG_TIMER_LOW_CLR(x) (((x) << 16) & 0xFFFF0000) 84#define SOTG_TIMER_HIGH_SET_CLR 0x38C 85#define SOTG_TIMER_HIGH_SET(x) ((x) & 0xFFFF) 86#define SOTG_TIMER_HIGH_CLR(x) (((x) << 16) & 0xFFFF0000) 87#define SOTG_TIMER_HIGH_START (1U << 15) 88#define SOTG_MEMORY_REG 0x33c 89 90/* Peripheral controller specific registers */ 91 92#define SOTG_ADDRESS 0x200 93#define SOTG_ADDRESS_ENABLE (1 << 7) 94#define SOTG_MODE 0x20C 95#define SOTG_MODE_DMACLK_ON (1 << 9) 96#define SOTG_MODE_VBUSSTAT (1 << 8) 97#define SOTG_MODE_CLKAON (1 << 7) 98#define SOTG_MODE_SNDRSU (1 << 6) 99#define SOTG_MODE_GOSUSP (1 << 5) 100#define SOTG_MODE_SFRESET (1 << 4) 101#define SOTG_MODE_GLINTENA (1 << 3) 102#define SOTG_MODE_WKUPCS (1 << 2) 103#define SOTG_INTERRUPT_CFG 0x210 104#define SOTG_INTERRUPT_CFG_DEBUG_SET (1 << 16) 105#define SOTG_INTERRUPT_CFG_CDBGMOD (1 << 6) /* ACK only */ 106#define SOTG_INTERRUPT_CFG_DDBGMODIN (1 << 4) /* ACK only */ 107#define SOTG_INTERRUPT_CFG_DDBGMODOUT (1 << 2) /* ACK and NYET only */ 108#define SOTG_INTERRUPT_CFG_INTLVL (1 << 1) 109#define SOTG_INTERRUPT_CFG_INTPOL (1 << 0) 110#define SOTG_DCINTERRUPT_EN 0x214 111#define SOTG_HW_MODE_CTRL 0x300 112#define SOTG_HW_MODE_CTRL_ALL_ATX_RESET (1 << 31) 113#define SOTG_HW_MODE_CTRL_ANA_DIGI_OC (1 << 15) 114#define SOTG_HW_MODE_CTRL_DEV_DMA (1 << 11) 115#define SOTG_HW_MODE_CTRL_COMN_INT (1 << 10) 116#define SOTG_HW_MODE_CTRL_COMN_DMA (1 << 9) 117#define SOTG_HW_MODE_CTRL_DATA_BUS_WIDTH (1 << 8) 118#define SOTG_HW_MODE_CTRL_DACK_POL (1 << 6) 119#define SOTG_HW_MODE_CTRL_DREQ_POL (1 << 5) 120#define SOTG_HW_MODE_CTRL_INTR_POL (1 << 2) 121#define SOTG_HW_MODE_CTRL_INTR_LEVEL (1 << 1) 122#define SOTG_HW_MODE_CTRL_GLOBAL_INTR_EN (1 << 0) 123#define SOTG_OTG_CTRL 0x374 124#define SOTG_EP_INDEX 0x22c 125#define SOTG_EP_INDEX_EP0SETUP (1 << 5) 126#define SOTG_EP_INDEX_ENDP_INDEX_MASK (15 << 1) 127#define SOTG_EP_INDEX_ENDP_INDEX_SHIFT 1 128#define SOTG_EP_INDEX_DIR_IN (1 << 0) 129#define SOTG_EP_INDEX_DIR_OUT 0 130#define SOTG_CTRL_FUNC 0x228 131#define SOTG_CTRL_FUNC_CLBUF (1 << 4) 132#define SOTG_CTRL_FUNC_VENDP (1 << 3) 133#define SOTG_CTRL_FUNC_DSEN (1 << 2) 134#define SOTG_CTRL_FUNC_STATUS (1 << 1) 135#define SOTG_CTRL_FUNC_STALL (1 << 0) 136#define SOTG_DATA_PORT 0x220 137#define SOTG_BUF_LENGTH 0x21C 138#define SOTG_BUF_LENGTH_BUFLEN_MASK 0xFFFF 139#define SOTG_BUF_LENGTH_FILLED_MASK (3 << 16) 140#define SOTG_EP_MAXPACKET 0x204 141#define SOTG_EP_TYPE 0x208 142#define SOTG_EP_TYPE_NOEMPPKT (1 << 4) 143#define SOTG_EP_TYPE_ENABLE (1 << 3) 144#define SOTG_EP_TYPE_DBLBUF (1 << 2) 145#define SOTG_EP_TYPE_EP_TYPE (3 << 0) 146#define SOTG_DMA_CMD 0x230 147#define SOTG_DMA_XFER_COUNT 0x234 148#define SOTG_DCDMA_CFG 0x238 149#define SOTG_DMA_HW 0x23C 150#define SOTG_DMA_IRQ_REASON 0x250 151#define SOTG_DMA_IRQ_ENABLE 0x254 152#define SOTG_DMA_EP 0x258 153#define SOTG_BURST_COUNTER 0x264 154#define SOTG_DCINTERRUPT 0x218 155#define SOTG_DCINTERRUPT_IEPRX(n) (1 << (10 + (2*(n)))) 156#define SOTG_DCINTERRUPT_IEPTX(n) (1 << (11 + (2*(n)))) 157#define SOTG_DCINTERRUPT_IEP0SETUP (1 << 8) 158#define SOTG_DCINTERRUPT_IEVBUS (1 << 7) 159#define SOTG_DCINTERRUPT_IEDMA (1 << 6) 160#define SOTG_DCINTERRUPT_IEHS_STA (1 << 5) 161#define SOTG_DCINTERRUPT_IERESM (1 << 4) 162#define SOTG_DCINTERRUPT_IESUSP (1 << 3) 163#define SOTG_DCINTERRUPT_IEPSOF (1 << 2) 164#define SOTG_DCINTERRUPT_IESOF (1 << 1) 165#define SOTG_DCINTERRUPT_IEBRST (1 << 0) 166#define SOTG_DCCHIP_ID 0x270 167#define SOTG_FRAME_NUM 0x274 168#define SOTG_FRAME_NUM_MICROSOFR_MASK 0x3800 169#define SOTG_FRAME_NUM_MICROSOFR_SHIFT 11 170#define SOTG_FRAME_NUM_SOFR_MASK 0x7FF 171#define SOTG_DCSCRATCH 0x278 172#define SOTG_UNLOCK_DEVICE 0x27C 173#define SOTG_UNLOCK_DEVICE_CODE 0xAA37 174#define SOTG_IRQ_PULSE_WIDTH 0x280 175#define SOTG_TEST_MODE 0x284 176#define SOTG_TEST_MODE_FORCEHS (1 << 7) 177#define SOTG_TEST_MODE_FORCEFS (1 << 4) 178#define SOTG_TEST_MODE_PRBS (1 << 3) 179#define SOTG_TEST_MODE_KSTATE (1 << 2) 180#define SOTG_TEST_MODE_JSTATE (1 << 1) 181#define SOTG_TEST_MODE_SE0_NAK (1 << 0) 182 183/* Host controller specific registers */ 184 185#define SOTG_FRINDEX 0x002c 186#define SOTG_FRINDEX_MASK 0x3fff 187#define SOTG_CONFIGFLAG 0x0060 188#define SOTG_CONFIGFLAG_ENABLE (1 << 0) 189#define SOTG_PORTSC1 0x0064 190#define SOTG_PORTSC1_PIC (3 << 14) 191#define SOTG_PORTSC1_PO (1 << 13) 192#define SOTG_PORTSC1_PP (1 << 12) 193#define SOTG_PORTSC1_LS (3 << 10) 194#define SOTG_PORTSC1_PR (1 << 8) 195#define SOTG_PORTSC1_SUSP (1 << 7) 196#define SOTG_PORTSC1_FPR (1 << 6) 197#define SOTG_PORTSC1_PED (1 << 2) 198#define SOTG_PORTSC1_ECSC (1 << 1) 199#define SOTG_PORTSC1_ECCS (1 << 0) 200#define SOTG_PTD_DW0 0 201#define SOTG_PTD_DW0_VALID 1U 202#define SOTG_PTD_DW1 4 203#define SOTG_PTD_DW1_ENABLE_SPLIT (1 << 14) 204#define SOTG_PTD_DW2 8 205#define SOTG_PTD_DW2_RL (0xf << 25) 206#define SOTG_PTD_DW3 12 207#define SOTG_PTD_DW3_NRL (0xf << 19) 208#define SOTG_PTD_DW3_ACTIVE (1U << 31) 209#define SOTG_PTD_DW3_HALTED (1U << 30) 210#define SOTG_PTD_DW3_ERRORS (3U << 28) 211#define SOTG_PTD_DW3_CERR_3 (3U << 23) 212#define SOTG_PTD_DW3_CERR_2 (2U << 23) /* infinite NAKs */ 213#define SOTG_PTD_DW3_CERR_1 (1U << 23) 214#define SOTG_PTD_DW3_XFER_COUNT_HS 0x7FFF 215#define SOTG_PTD_DW3_XFER_COUNT_SPLIT 0x03FF 216#define SOTG_PTD_DW4 16 217#define SOTG_PTD_DW5 20 218#define SOTG_PTD_DW6 24 219#define SOTG_PTD_DW7 28 220#define SOTG_DATA_ADDR(x) (0x1000 + (512 * (x))) 221#define SOTG_ASYNC_PTD(x) (0xC00 + ((x) * 32)) 222#define SOTG_INTR_PTD(x) (0x800 + ((x) * 32)) 223#define SOTG_ISOC_PTD(x) (0x400 + ((x) * 32)) 224#define SOTG_PTD(x) (0x400 + ((x) * 32)) 225#define SOTG_HC_MEMORY_ADDR(x) (((x) - 0x400) >> 3) 226#define SOTG_SW_RESET 0x30C 227#define SOTG_SW_RESET_HC (1 << 1) 228#define SOTG_SW_RESET_ALL (1 << 0) 229#define SOTG_POWER_DOWN 0x354 230#define SOTG_POWER_DOWN_PORT3_PD (1 << 12) 231#define SOTG_POWER_DOWN_PORT2_PD (1 << 11) 232#define SOTG_POWER_DOWN_VBATDET_PWR (1 << 10) 233#define SOTG_POWER_DOWN_BIAS_EN (1 << 5) 234#define SOTG_POWER_DOWN_VREG_ON (1 << 4) 235#define SOTG_POWER_DOWN_OC3_PWR (1 << 3) 236#define SOTG_POWER_DOWN_OC2_PWR (1 << 2) 237#define SOTG_POWER_DOWN_OC1_PWR (1 << 1) 238#define SOTG_POWER_DOWN_HC_CLK_EN (1 << 0) 239#define SOTG_USBCMD 0x20 240#define SOTG_USBCMD_LHCR (1 << 7) 241#define SOTG_USBCMD_HCRESET (1 << 1) 242#define SOTG_USBCMD_RS (1 << 0) 243#define SOTG_HCSCRATCH 0x308 244#define SOTG_HCINTERRUPT 0x310 245#define SOTG_HCINTERRUPT_OTG_IRQ (1 << 10) 246#define SOTG_HCINTERRUPT_ISO_IRQ (1 << 9) 247#define SOTG_HCINTERRUPT_ALT_IRQ (1 << 8) 248#define SOTG_HCINTERRUPT_INT_IRQ (1 << 7) 249#define SOTG_HCINTERRUPT_CLKREADY (1 << 6) 250#define SOTG_HCINTERRUPT_HCSUSP (1 << 5) 251#define SOTG_HCINTERRUPT_DMAEOTINT (1 << 3) 252#define SOTG_HCINTERRUPT_SOFITLINT (1 << 1) 253#define SOTG_HCINTERRUPT_ENABLE 0x314 254#define SOTG_ATL_PTD_DONE_PTD 0x150 255#define SOTG_ATL_PTD_SKIP_PTD 0x154 256#define SOTG_ATL_PTD_LAST_PTD 0x158 257#define SOTG_INT_PTD_DONE_PTD 0x140 258#define SOTG_INT_PTD_SKIP_PTD 0x144 259#define SOTG_INT_PTD_LAST_PTD 0x148 260#define SOTG_ISO_PTD_DONE_PTD 0x130 261#define SOTG_ISO_PTD_SKIP_PTD 0x134 262#define SOTG_ISO_PTD_LAST_PTD 0x138 263#define SOTG_HCBUFFERSTATUS 0x334 264#define SOTG_HCBUFFERSTATUS_ISO_BUF_FILL (1 << 2) 265#define SOTG_HCBUFFERSTATUS_INT_BUF_FILL (1 << 1) 266#define SOTG_HCBUFFERSTATUS_ATL_BUF_FILL (1 << 0) 267#define SOTG_ISO_IRQ_MASK_OR 0x318 268#define SOTG_INT_IRQ_MASK_OR 0x31C 269#define SOTG_ATL_IRQ_MASK_OR 0x320 270#define SOTG_ISO_IRQ_MASK_AND 0x324 271#define SOTG_INT_IRQ_MASK_AND 0x328 272#define SOTG_ATL_IRQ_MASK_AND 0x32C 273 274#endif /* _SAF1761_OTG_REG_H_ */ 275