1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com> 5 * All rights reserved. 6 * 7 * This software was developed by SRI International and the University of 8 * Cambridge Computer Laboratory (Department of Computer Science and 9 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the 10 * DARPA SSITH research programme. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36#ifndef _UART_DEV_LOWRISC_H_ 37#define _UART_DEV_LOWRISC_H_ 38 39#define UART_DR 0x0000 40#define DR_DATA_S 0 41#define DR_DATA_M 0xff 42#define DR_RX_ERR (1 << 8) 43#define DR_RX_FIFO_EMPTY (1 << 9) 44#define DR_TX_FIFO_FULL (1 << 10) 45#define DR_RX_FIFO_FULL (1 << 11) 46#define UART_INT_STATUS 0x1000 47#define INT_STATUS_ACK 1 48#define UART_BAUD 0x2000 /* write-only */ 49#define BAUD_115200 108 50#define UART_STAT_RX 0x2000 /* read-only */ 51#define STAT_RX_FIFO_RD_COUNT_S 0 52#define STAT_RX_FIFO_RD_COUNT_M (0xffff << STAT_RX_FIFO_RD_COUNT_S) 53#define STAT_RX_FIFO_WR_COUNT_S 16 54#define STAT_RX_FIFO_WR_COUNT_M (0xffff << STAT_RX_FIFO_WR_COUNT_S) 55#define UART_STAT_TX 0x2004 56#define STAT_TX_FIFO_RD_COUNT_S 0 57#define STAT_TX_FIFO_RD_COUNT_M (0xffff << STAT_TX_FIFO_RD_COUNT_S) 58#define STAT_TX_FIFO_WR_COUNT_S 16 59#define STAT_TX_FIFO_WR_COUNT_M (0xffff << STAT_TX_FIFO_WR_COUNT_S) 60 61#define GETREG(bas, reg) \ 62 bus_space_read_2((bas)->bst, (bas)->bsh, (reg)) 63#define SETREG(bas, reg, value) \ 64 bus_space_write_2((bas)->bst, (bas)->bsh, (reg), (value)) 65 66#endif /* _UART_DEV_LOWRISC_H_ */ 67