1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004-07 Applied Micro Circuits Corporation. 5 * Copyright (c) 2004-05 Vinod Kashyap. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32/* 33 * AMCC'S 3ware driver for 9000 series storage controllers. 34 * 35 * Author: Vinod Kashyap 36 * Modifications by: Adam Radford 37 * Modifications by: Manjunath Ranganathaiah 38 */ 39 40#ifndef TW_OSL_H 41 42#define TW_OSL_H 43 44/* 45 * OS Layer internal macros, structures and functions. 46 */ 47 48#define TW_OSLI_DEVICE_NAME "3ware 9000 series Storage Controller" 49 50#define TW_OSLI_MALLOC_CLASS M_TWA 51#define TW_OSLI_MAX_NUM_REQUESTS TW_CL_MAX_SIMULTANEOUS_REQUESTS 52/* Reserve two command packets. One for ioctls and one for AENs */ 53#define TW_OSLI_MAX_NUM_IOS (TW_OSLI_MAX_NUM_REQUESTS - 2) 54#define TW_OSLI_MAX_NUM_AENS 0x100 55 56#ifdef PAE 57#define TW_OSLI_DMA_BOUNDARY (1u << 31) 58#else 59#define TW_OSLI_DMA_BOUNDARY ((bus_size_t)((uint64_t)1 << 32)) 60#endif 61 62/* Possible values of req->state. */ 63#define TW_OSLI_REQ_STATE_INIT 0x0 /* being initialized */ 64#define TW_OSLI_REQ_STATE_BUSY 0x1 /* submitted to CL */ 65#define TW_OSLI_REQ_STATE_PENDING 0x2 /* in pending queue */ 66#define TW_OSLI_REQ_STATE_COMPLETE 0x3 /* completed by CL */ 67 68/* Possible values of req->flags. */ 69#define TW_OSLI_REQ_FLAGS_DATA_IN (1<<0) /* read request */ 70#define TW_OSLI_REQ_FLAGS_DATA_OUT (1<<1) /* write request */ 71#define TW_OSLI_REQ_FLAGS_DATA_COPY_NEEDED (1<<2)/* data in ccb is misaligned, 72 have to copy to/from private buffer */ 73#define TW_OSLI_REQ_FLAGS_MAPPED (1<<3) /* request has been mapped */ 74#define TW_OSLI_REQ_FLAGS_IN_PROGRESS (1<<4) /* bus_dmamap_load returned 75 EINPROGRESS */ 76#define TW_OSLI_REQ_FLAGS_PASSTHRU (1<<5) /* pass through request */ 77#define TW_OSLI_REQ_FLAGS_SLEEPING (1<<6) /* owner sleeping on this cmd */ 78#define TW_OSLI_REQ_FLAGS_FAILED (1<<7) /* bus_dmamap_load() failed */ 79#define TW_OSLI_REQ_FLAGS_CCB (1<<8) /* req is ccb. */ 80 81#ifdef TW_OSL_DEBUG 82struct tw_osli_q_stats { 83 TW_UINT32 cur_len; /* current # of items in q */ 84 TW_UINT32 max_len; /* max value reached by q_length */ 85}; 86#endif /* TW_OSL_DEBUG */ 87 88/* Queues of OSL internal request context packets. */ 89#define TW_OSLI_FREE_Q 0 /* free q */ 90#define TW_OSLI_BUSY_Q 1 /* q of reqs submitted to CL */ 91#define TW_OSLI_Q_COUNT 2 /* total number of queues */ 92 93/* Driver's request packet. */ 94struct tw_osli_req_context { 95 struct tw_cl_req_handle req_handle;/* tag to track req b/w OSL & CL */ 96 struct mtx ioctl_wake_timeout_lock_handle;/* non-spin lock used to detect ioctl timeout */ 97 struct mtx *ioctl_wake_timeout_lock;/* ptr to above lock */ 98 struct twa_softc *ctlr; /* ptr to OSL's controller context */ 99 TW_VOID *data; /* ptr to data being passed to CL */ 100 TW_UINT32 length; /* length of buf being passed to CL */ 101 TW_UINT64 deadline;/* request timeout (in absolute time) */ 102 103 /* 104 * ptr to, and length of data passed to us from above, in case a buffer 105 * copy was done due to non-compliance to alignment requirements 106 */ 107 TW_VOID *real_data; 108 TW_UINT32 real_length; 109 110 TW_UINT32 state; /* request state */ 111 TW_UINT32 flags; /* request flags */ 112 113 /* error encountered before request submission to CL */ 114 TW_UINT32 error_code; 115 116 /* ptr to orig req for use during callback */ 117 TW_VOID *orig_req; 118 119 struct tw_cl_link link; /* to link this request in a list */ 120 bus_dmamap_t dma_map;/* DMA map for data */ 121 struct tw_cl_req_packet req_pkt;/* req pkt understood by CL */ 122}; 123 124/* Per-controller structure. */ 125struct twa_softc { 126 struct tw_cl_ctlr_handle ctlr_handle; 127 struct tw_osli_req_context *req_ctx_buf; 128 129 /* Controller state. */ 130 TW_UINT8 open; 131 TW_UINT32 flags; 132 133 TW_INT32 device_id; 134 TW_UINT32 alignment; 135 TW_UINT32 sg_size_factor; 136 137 TW_VOID *non_dma_mem; 138 TW_VOID *dma_mem; 139 TW_UINT64 dma_mem_phys; 140 141 /* Request queues and arrays. */ 142 struct tw_cl_link req_q_head[TW_OSLI_Q_COUNT]; 143 144 struct task deferred_intr_callback;/* taskqueue function */ 145 struct mtx io_lock_handle;/* general purpose lock */ 146 struct mtx *io_lock;/* ptr to general purpose lock */ 147 struct mtx q_lock_handle; /* queue manipulation lock */ 148 struct mtx *q_lock;/* ptr to queue manipulation lock */ 149 struct mtx sim_lock_handle;/* sim lock shared with cam */ 150 struct mtx *sim_lock;/* ptr to sim lock */ 151 152 struct callout watchdog_callout[2]; /* For command timeout */ 153 TW_UINT32 watchdog_index; 154 155#ifdef TW_OSL_DEBUG 156 struct tw_osli_q_stats q_stats[TW_OSLI_Q_COUNT];/* queue statistics */ 157#endif /* TW_OSL_DEBUG */ 158 159 device_t bus_dev; /* bus device */ 160 struct cdev *ctrl_dev; /* control device */ 161 struct resource *reg_res; /* register interface window */ 162 TW_INT32 reg_res_id; /* register resource id */ 163 bus_space_handle_t bus_handle; /* bus space handle */ 164 bus_space_tag_t bus_tag; /* bus space tag */ 165 bus_dma_tag_t parent_tag; /* parent DMA tag */ 166 bus_dma_tag_t cmd_tag; /* DMA tag for CL's DMA'able mem */ 167 bus_dma_tag_t dma_tag; /* data buffer DMA tag */ 168 bus_dma_tag_t ioctl_tag; /* ioctl data buffer DMA tag */ 169 bus_dmamap_t cmd_map; /* DMA map for CL's DMA'able mem */ 170 bus_dmamap_t ioctl_map; /* DMA map for ioctl data buffers */ 171 struct resource *irq_res; /* interrupt resource */ 172 TW_INT32 irq_res_id; /* register resource id */ 173 TW_VOID *intr_handle; /* interrupt handle */ 174 175 struct sysctl_ctx_list sysctl_ctxt; /* sysctl context */ 176 struct sysctl_oid *sysctl_tree; /* sysctl oid */ 177 178 struct cam_sim *sim; /* sim for this controller */ 179 struct cam_path *path; /* peripheral, path, tgt, lun 180 associated with this controller */ 181}; 182 183/* 184 * Queue primitives. 185 */ 186 187#ifdef TW_OSL_DEBUG 188 189#define TW_OSLI_Q_INIT(sc, q_type) do { \ 190 (sc)->q_stats[q_type].cur_len = 0; \ 191 (sc)->q_stats[q_type].max_len = 0; \ 192} while(0) 193 194#define TW_OSLI_Q_INSERT(sc, q_type) do { \ 195 struct tw_osli_q_stats *q_stats = &((sc)->q_stats[q_type]); \ 196 \ 197 if (++(q_stats->cur_len) > q_stats->max_len) \ 198 q_stats->max_len = q_stats->cur_len; \ 199} while(0) 200 201#define TW_OSLI_Q_REMOVE(sc, q_type) \ 202 (sc)->q_stats[q_type].cur_len-- 203 204#else /* TW_OSL_DEBUG */ 205 206#define TW_OSLI_Q_INIT(sc, q_index) 207#define TW_OSLI_Q_INSERT(sc, q_index) 208#define TW_OSLI_Q_REMOVE(sc, q_index) 209 210#endif /* TW_OSL_DEBUG */ 211 212/* Initialize a queue of requests. */ 213static __inline TW_VOID 214tw_osli_req_q_init(struct twa_softc *sc, TW_UINT8 q_type) 215{ 216 TW_CL_Q_INIT(&(sc->req_q_head[q_type])); 217 TW_OSLI_Q_INIT(sc, q_type); 218} 219 220/* Insert the given request at the head of the given queue (q_type). */ 221static __inline TW_VOID 222tw_osli_req_q_insert_head(struct tw_osli_req_context *req, TW_UINT8 q_type) 223{ 224 mtx_lock_spin(req->ctlr->q_lock); 225 TW_CL_Q_INSERT_HEAD(&(req->ctlr->req_q_head[q_type]), &(req->link)); 226 TW_OSLI_Q_INSERT(req->ctlr, q_type); 227 mtx_unlock_spin(req->ctlr->q_lock); 228} 229 230/* Insert the given request at the tail of the given queue (q_type). */ 231static __inline TW_VOID 232tw_osli_req_q_insert_tail(struct tw_osli_req_context *req, TW_UINT8 q_type) 233{ 234 mtx_lock_spin(req->ctlr->q_lock); 235 TW_CL_Q_INSERT_TAIL(&(req->ctlr->req_q_head[q_type]), &(req->link)); 236 TW_OSLI_Q_INSERT(req->ctlr, q_type); 237 mtx_unlock_spin(req->ctlr->q_lock); 238} 239 240/* Remove and return the request at the head of the given queue (q_type). */ 241static __inline struct tw_osli_req_context * 242tw_osli_req_q_remove_head(struct twa_softc *sc, TW_UINT8 q_type) 243{ 244 struct tw_osli_req_context *req = NULL; 245 struct tw_cl_link *link; 246 247 mtx_lock_spin(sc->q_lock); 248 if ((link = TW_CL_Q_FIRST_ITEM(&(sc->req_q_head[q_type]))) != 249 TW_CL_NULL) { 250 req = TW_CL_STRUCT_HEAD(link, 251 struct tw_osli_req_context, link); 252 TW_CL_Q_REMOVE_ITEM(&(sc->req_q_head[q_type]), &(req->link)); 253 TW_OSLI_Q_REMOVE(sc, q_type); 254 } 255 mtx_unlock_spin(sc->q_lock); 256 return(req); 257} 258 259/* Remove the given request from the given queue (q_type). */ 260static __inline TW_VOID 261tw_osli_req_q_remove_item(struct tw_osli_req_context *req, TW_UINT8 q_type) 262{ 263 mtx_lock_spin(req->ctlr->q_lock); 264 TW_CL_Q_REMOVE_ITEM(&(req->ctlr->req_q_head[q_type]), &(req->link)); 265 TW_OSLI_Q_REMOVE(req->ctlr, q_type); 266 mtx_unlock_spin(req->ctlr->q_lock); 267} 268 269#ifdef TW_OSL_DEBUG 270 271extern TW_INT32 TW_DEBUG_LEVEL_FOR_OSL; 272 273#define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...) \ 274 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \ 275 device_printf(sc->bus_dev, "%s: " fmt "\n", \ 276 __func__, ##args) 277 278#define tw_osli_dbg_printf(dbg_level, fmt, args...) \ 279 if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \ 280 printf("%s: " fmt "\n", __func__, ##args) 281 282#else /* TW_OSL_DEBUG */ 283 284#define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...) 285#define tw_osli_dbg_printf(dbg_level, fmt, args...) 286 287#endif /* TW_OSL_DEBUG */ 288 289/* For regular printing. */ 290#define twa_printf(sc, fmt, args...) \ 291 device_printf(((struct twa_softc *)(sc))->bus_dev, fmt, ##args) 292 293/* For printing in the "consistent error reporting" format. */ 294#define tw_osli_printf(sc, err_specific_desc, args...) \ 295 device_printf((sc)->bus_dev, \ 296 "%s: (0x%02X: 0x%04X): %s: " err_specific_desc "\n", ##args) 297 298#endif /* TW_OSL_H */ 299