1/* $FreeBSD$ */ 2/*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 1996-2008, 4Front Technologies 6 * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32/*--------------------------------------------------------------------------- 33 * Copyright (C) 1997-1999, ESS Technology, Inc. 34 * This source code, its compiled object code, and its associated data sets 35 * are copyright (C) 1997-1999 ESS Technology, Inc. 36 *--------------------------------------------------------------------------- 37 * This header contains data structures and registers taken from the 38 * 4Front OSS Allegro BSD licensed driver (in the Attic/ directory). 39 * Files used for this header include: 40 * hardware.h 41 * kernel.h and hckernel.h 42 * srcmgr.h 43 *--------------------------------------------------------------------------- 44 */ 45 46#ifndef _DEV_SOUND_PCI_ALLEGRO_REG_H 47#define _DEV_SOUND_PCI_ALLEGRO_REG_H 48 49/* Allegro PCI configuration registers */ 50#define PCI_LEGACY_AUDIO_CTRL 0x40 51#define SOUND_BLASTER_ENABLE 0x00000001 52#define FM_SYNTHESIS_ENABLE 0x00000002 53#define GAME_PORT_ENABLE 0x00000004 54#define MPU401_IO_ENABLE 0x00000008 55#define MPU401_IRQ_ENABLE 0x00000010 56#define ALIAS_10BIT_IO 0x00000020 57#define SB_DMA_MASK 0x000000C0 58#define SB_DMA_0 0x00000040 59#define SB_DMA_1 0x00000040 60#define SB_DMA_R 0x00000080 61#define SB_DMA_3 0x000000C0 62#define SB_IRQ_MASK 0x00000700 63#define SB_IRQ_5 0x00000000 64#define SB_IRQ_7 0x00000100 65#define SB_IRQ_9 0x00000200 66#define SB_IRQ_10 0x00000300 67#define MIDI_IRQ_MASK 0x00003800 68#define SERIAL_IRQ_ENABLE 0x00004000 69#define DISABLE_LEGACY 0x00008000 70 71#define PCI_ALLEGRO_CONFIG 0x50 72#define SB_ADDR_240 0x00000004 73#define MPU_ADDR_MASK 0x00000018 74#define MPU_ADDR_330 0x00000000 75#define MPU_ADDR_300 0x00000008 76#define MPU_ADDR_320 0x00000010 77#define MPU_ADDR_340 0x00000018 78#define USE_PCI_TIMING 0x00000040 79#define POSTED_WRITE_ENABLE 0x00000080 80#define DMA_POLICY_MASK 0x00000700 81#define DMA_DDMA 0x00000000 82#define DMA_TDMA 0x00000100 83#define DMA_PCPCI 0x00000200 84#define DMA_WBDMA16 0x00000400 85#define DMA_WBDMA4 0x00000500 86#define DMA_WBDMA2 0x00000600 87#define DMA_WBDMA1 0x00000700 88#define DMA_SAFE_GUARD 0x00000800 89#define HI_PERF_GP_ENABLE 0x00001000 90#define PIC_SNOOP_MODE_0 0x00002000 91#define PIC_SNOOP_MODE_1 0x00004000 92#define SOUNDBLASTER_IRQ_MASK 0x00008000 93#define RING_IN_ENABLE 0x00010000 94#define SPDIF_TEST_MODE 0x00020000 95#define CLK_MULT_MODE_SELECT_2 0x00040000 96#define EEPROM_WRITE_ENABLE 0x00080000 97#define CODEC_DIR_IN 0x00100000 98#define HV_BUTTON_FROM_GD 0x00200000 99#define REDUCED_DEBOUNCE 0x00400000 100#define HV_CTRL_ENABLE 0x00800000 101#define SPDIF_ENABLE 0x01000000 102#define CLK_DIV_SELECT 0x06000000 103#define CLK_DIV_BY_48 0x00000000 104#define CLK_DIV_BY_49 0x02000000 105#define CLK_DIV_BY_50 0x04000000 106#define CLK_DIV_RESERVED 0x06000000 107#define PM_CTRL_ENABLE 0x08000000 108#define CLK_MULT_MODE_SELECT 0x30000000 109#define CLK_MULT_MODE_SHIFT 28 110#define CLK_MULT_MODE_0 0x00000000 111#define CLK_MULT_MODE_1 0x10000000 112#define CLK_MULT_MODE_2 0x20000000 113#define CLK_MULT_MODE_3 0x30000000 114#define INT_CLK_SELECT 0x40000000 115#define INT_CLK_MULT_RESET 0x80000000 116 117/* M3 */ 118#define INT_CLK_SRC_NOT_PCI 0x00100000 119#define INT_CLK_MULT_ENABLE 0x80000000 120 121#define PCI_ACPI_CONTROL 0x54 122#define PCI_ACPI_D0 0x00000000 123#define PCI_ACPI_D1 0xB4F70000 124#define PCI_ACPI_D2 0xB4F7B4F7 125 126#define PCI_USER_CONFIG 0x58 127#define EXT_PCI_MASTER_ENABLE 0x00000001 128#define SPDIF_OUT_SELECT 0x00000002 129#define TEST_PIN_DIR_CTRL 0x00000004 130#define AC97_CODEC_TEST 0x00000020 131#define TRI_STATE_BUFFER 0x00000080 132#define IN_CLK_12MHZ_SELECT 0x00000100 133#define MULTI_FUNC_DISABLE 0x00000200 134#define EXT_MASTER_PAIR_SEL 0x00000400 135#define PCI_MASTER_SUPPORT 0x00000800 136#define STOP_CLOCK_ENABLE 0x00001000 137#define EAPD_DRIVE_ENABLE 0x00002000 138#define REQ_TRI_STATE_ENABLE 0x00004000 139#define REQ_LOW_ENABLE 0x00008000 140#define MIDI_1_ENABLE 0x00010000 141#define MIDI_2_ENABLE 0x00020000 142#define SB_AUDIO_SYNC 0x00040000 143#define HV_CTRL_TEST 0x00100000 144#define SOUNDBLASTER_TEST 0x00400000 145 146#define PCI_USER_CONFIG_C 0x5C 147 148#define PCI_DDMA_CTRL 0x60 149#define DDMA_ENABLE 0x00000001 150 151/* Allegro registers */ 152#define HOST_INT_CTRL 0x18 153#define SB_INT_ENABLE 0x0001 154#define MPU401_INT_ENABLE 0x0002 155#define ASSP_INT_ENABLE 0x0010 156#define RING_INT_ENABLE 0x0020 157#define HV_INT_ENABLE 0x0040 158#define CLKRUN_GEN_ENABLE 0x0100 159#define HV_CTRL_TO_PME 0x0400 160#define SOFTWARE_RESET_ENABLE 0x8000 161 162#define HOST_INT_STATUS 0x1A 163#define SB_INT_PENDING 0x01 164#define MPU401_INT_PENDING 0x02 165#define ASSP_INT_PENDING 0x10 166#define RING_INT_PENDING 0x20 167#define HV_INT_PENDING 0x40 168 169#define HARDWARE_VOL_CTRL 0x1B 170#define SHADOW_MIX_REG_VOICE 0x1C 171#define HW_VOL_COUNTER_VOICE 0x1D 172#define SHADOW_MIX_REG_MASTER 0x1E 173#define HW_VOL_COUNTER_MASTER 0x1F 174 175#define CODEC_COMMAND 0x30 176#define CODEC_READ_B 0x80 177 178#define CODEC_STATUS 0x30 179#define CODEC_BUSY_B 0x01 180 181#define CODEC_DATA 0x32 182 183/* AC97 registers */ 184#ifndef M3_MODEL 185#define AC97_RESET 0x00 186#endif 187 188#define AC97_VOL_MUTE_B 0x8000 189#define AC97_VOL_M 0x1F 190#define AC97_LEFT_VOL_S 8 191 192#define AC97_MASTER_VOL 0x02 193#define AC97_LINE_LEVEL_VOL 0x04 194#define AC97_MASTER_MONO_VOL 0x06 195#define AC97_PC_BEEP_VOL 0x0A 196#define AC97_PC_BEEP_VOL_M 0x0F 197#define AC97_SROUND_MASTER_VOL 0x38 198#define AC97_PC_BEEP_VOL_S 1 199 200#ifndef M3_MODEL 201#define AC97_PHONE_VOL 0x0C 202#define AC97_MIC_VOL 0x0E 203#endif 204#define AC97_MIC_20DB_ENABLE 0x40 205 206#ifndef M3_MODEL 207#define AC97_LINEIN_VOL 0x10 208#define AC97_CD_VOL 0x12 209#define AC97_VIDEO_VOL 0x14 210#define AC97_AUX_VOL 0x16 211#endif 212#define AC97_PCM_OUT_VOL 0x18 213#ifndef M3_MODEL 214#define AC97_RECORD_SELECT 0x1A 215#endif 216#define AC97_RECORD_MIC 0x00 217#define AC97_RECORD_CD 0x01 218#define AC97_RECORD_VIDEO 0x02 219#define AC97_RECORD_AUX 0x03 220#define AC97_RECORD_MONO_MUX 0x02 221#define AC97_RECORD_DIGITAL 0x03 222#define AC97_RECORD_LINE 0x04 223#define AC97_RECORD_STEREO 0x05 224#define AC97_RECORD_MONO 0x06 225#define AC97_RECORD_PHONE 0x07 226 227#ifndef M3_MODEL 228#define AC97_RECORD_GAIN 0x1C 229#endif 230#define AC97_RECORD_VOL_M 0x0F 231 232#ifndef M3_MODEL 233#define AC97_GENERAL_PURPOSE 0x20 234#endif 235#define AC97_POWER_DOWN_CTRL 0x26 236#define AC97_ADC_READY 0x0001 237#define AC97_DAC_READY 0x0002 238#define AC97_ANALOG_READY 0x0004 239#define AC97_VREF_ON 0x0008 240#define AC97_PR0 0x0100 241#define AC97_PR1 0x0200 242#define AC97_PR2 0x0400 243#define AC97_PR3 0x0800 244#define AC97_PR4 0x1000 245 246#define AC97_RESERVED1 0x28 247 248#define AC97_VENDOR_TEST 0x5A 249 250#define AC97_CLOCK_DELAY 0x5C 251#define AC97_LINEOUT_MUX_SEL 0x0001 252#define AC97_MONO_MUX_SEL 0x0002 253#define AC97_CLOCK_DELAY_SEL 0x1F 254#define AC97_DAC_CDS_SHIFT 6 255#define AC97_ADC_CDS_SHIFT 11 256 257#define AC97_MULTI_CHANNEL_SEL 0x74 258 259#ifndef M3_MODEL 260#define AC97_VENDOR_ID1 0x7C 261#define AC97_VENDOR_ID2 0x7E 262#endif 263 264#define RING_BUS_CTRL_A 0x36 265#define RAC_PME_ENABLE 0x0100 266#define RAC_SDFS_ENABLE 0x0200 267#define LAC_PME_ENABLE 0x0400 268#define LAC_SDFS_ENABLE 0x0800 269#define SERIAL_AC_LINK_ENABLE 0x1000 270#define IO_SRAM_ENABLE 0x2000 271#define IIS_INPUT_ENABLE 0x8000 272 273#define RING_BUS_CTRL_B 0x38 274#define SECOND_CODEC_ID_MASK 0x0003 275#define SPDIF_FUNC_ENABLE 0x0010 276#define SECOND_AC_ENABLE 0x0020 277#define SB_MODULE_INTF_ENABLE 0x0040 278#define SSPE_ENABLE 0x0040 279#define M3I_DOCK_ENABLE 0x0080 280 281#define SDO_OUT_DEST_CTRL 0x3A 282#define COMMAND_ADDR_OUT 0x0003 283#define PCM_LR_OUT_LOCAL 0x0000 284#define PCM_LR_OUT_REMOTE 0x0004 285#define PCM_LR_OUT_MUTE 0x0008 286#define PCM_LR_OUT_BOTH 0x000C 287#define LINE1_DAC_OUT_LOCAL 0x0000 288#define LINE1_DAC_OUT_REMOTE 0x0010 289#define LINE1_DAC_OUT_MUTE 0x0020 290#define LINE1_DAC_OUT_BOTH 0x0030 291#define PCM_CLS_OUT_LOCAL 0x0000 292#define PCM_CLS_OUT_REMOTE 0x0040 293#define PCM_CLS_OUT_MUTE 0x0080 294#define PCM_CLS_OUT_BOTH 0x00C0 295#define PCM_RLF_OUT_LOCAL 0x0000 296#define PCM_RLF_OUT_REMOTE 0x0100 297#define PCM_RLF_OUT_MUTE 0x0200 298#define PCM_RLF_OUT_BOTH 0x0300 299#define LINE2_DAC_OUT_LOCAL 0x0000 300#define LINE2_DAC_OUT_REMOTE 0x0400 301#define LINE2_DAC_OUT_MUTE 0x0800 302#define LINE2_DAC_OUT_BOTH 0x0C00 303#define HANDSET_OUT_LOCAL 0x0000 304#define HANDSET_OUT_REMOTE 0x1000 305#define HANDSET_OUT_MUTE 0x2000 306#define HANDSET_OUT_BOTH 0x3000 307#define IO_CTRL_OUT_LOCAL 0x0000 308#define IO_CTRL_OUT_REMOTE 0x4000 309#define IO_CTRL_OUT_MUTE 0x8000 310#define IO_CTRL_OUT_BOTH 0xC000 311 312#define SDO_IN_DEST_CTRL 0x3C 313#define STATUS_ADDR_IN 0x0003 314#define PCM_LR_IN_LOCAL 0x0000 315#define PCM_LR_IN_REMOTE 0x0004 316#define PCM_LR_RESERVED 0x0008 317#define PCM_LR_IN_BOTH 0x000C 318#define LINE1_ADC_IN_LOCAL 0x0000 319#define LINE1_ADC_IN_REMOTE 0x0010 320#define LINE1_ADC_IN_MUTE 0x0020 321#define MIC_ADC_IN_LOCAL 0x0000 322#define MIC_ADC_IN_REMOTE 0x0040 323#define MIC_ADC_IN_MUTE 0x0080 324#define LINE2_DAC_IN_LOCAL 0x0000 325#define LINE2_DAC_IN_REMOTE 0x0400 326#define LINE2_DAC_IN_MUTE 0x0800 327#define HANDSET_IN_LOCAL 0x0000 328#define HANDSET_IN_REMOTE 0x1000 329#define HANDSET_IN_MUTE 0x2000 330#define IO_STATUS_IN_LOCAL 0x0000 331#define IO_STATUS_IN_REMOTE 0x4000 332 333#define SPDIF_IN_CTRL 0x3E 334#define SPDIF_IN_ENABLE 0x0001 335 336#define GPIO_DATA 0x60 337#define GPIO_DATA_MASK 0x0FFF 338#define GPIO_HV_STATUS 0x3000 339#define GPIO_PME_STATUS 0x4000 340 341#define GPIO_MASK 0x64 342#define GPIO_DIRECTION 0x68 343#define GPO_PRIMARY_AC97 0x0001 344#define GPI_LINEOUT_SENSE 0x0004 345#define GPO_SECONDARY_AC97 0x0008 346#define GPI_VOL_DOWN 0x0010 347#define GPI_VOL_UP 0x0020 348#define GPI_IIS_CLK 0x0040 349#define GPI_IIS_LRCLK 0x0080 350#define GPI_IIS_DATA 0x0100 351#define GPI_DOCKING_STATUS 0x0100 352#define GPI_HEADPHONE_SENSE 0x0200 353#define GPO_EXT_AMP_SHUTDOWN 0x1000 354 355/* M3 */ 356#define GPO_M3_EXT_AMP_SHUTDN 0x0002 357 358#define ASSP_INDEX_PORT 0x80 359#define ASSP_MEMORY_PORT 0x82 360#define ASSP_DATA_PORT 0x84 361 362#define MPU401_DATA_PORT 0x98 363#define MPU401_STATUS_PORT 0x99 364 365#define CLK_MULT_DATA_PORT 0x9C 366 367#define ASSP_CONTROL_A 0xA2 368#define ASSP_0_WS_ENABLE 0x01 369#define ASSP_CTRL_A_RESERVED1 0x02 370#define ASSP_CTRL_A_RESERVED2 0x04 371#define ASSP_CLK_49MHZ_SELECT 0x08 372#define FAST_PLU_ENABLE 0x10 373#define ASSP_CTRL_A_RESERVED3 0x20 374#define DSP_CLK_36MHZ_SELECT 0x40 375 376#define ASSP_CONTROL_B 0xA4 377#define RESET_ASSP 0x00 378#define RUN_ASSP 0x01 379#define ENABLE_ASSP_CLOCK 0x00 380#define STOP_ASSP_CLOCK 0x10 381#define RESET_TOGGLE 0x40 382 383#define ASSP_CONTROL_C 0xA6 384#define ASSP_HOST_INT_ENABLE 0x01 385#define FM_ADDR_REMAP_DISABLE 0x02 386#define HOST_WRITE_PORT_ENABLE 0x08 387 388#define ASSP_HOST_INT_STATUS 0xAC 389#define DSP2HOST_REQ_PIORECORD 0x01 390#define DSP2HOST_REQ_I2SRATE 0x02 391#define DSP2HOST_REQ_TIMER 0x04 392 393/* 394 * DSP memory map 395 */ 396 397#define REV_A_CODE_MEMORY_BEGIN 0x0000 398#define REV_A_CODE_MEMORY_END 0x0FFF 399#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 400#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) 401 402#define REV_B_CODE_MEMORY_BEGIN 0x0000 403#define REV_B_CODE_MEMORY_END 0x0BFF 404#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 405#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) 406 407#if (REV_A_CODE_MEMORY_LENGTH % REV_A_CODE_MEMORY_UNIT_LENGTH) 408#error Assumption about code memory unit length failed. 409#endif 410#if (REV_B_CODE_MEMORY_LENGTH % REV_B_CODE_MEMORY_UNIT_LENGTH) 411#error Assumption about code memory unit length failed. 412#endif 413 414#define REV_A_DATA_MEMORY_BEGIN 0x1000 415#define REV_A_DATA_MEMORY_END 0x2FFF 416#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 417#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) 418 419#define REV_B_DATA_MEMORY_BEGIN 0x1000 420/*#define REV_B_DATA_MEMORY_END 0x23FF */ 421#define REV_B_DATA_MEMORY_END 0x2BFF 422#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 423#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) 424 425#if (REV_A_DATA_MEMORY_LENGTH % REV_A_DATA_MEMORY_UNIT_LENGTH) 426#error Assumption about data memory unit length failed. 427#endif 428#if (REV_B_DATA_MEMORY_LENGTH % REV_B_DATA_MEMORY_UNIT_LENGTH) 429#error Assumption about data memory unit length failed. 430#endif 431 432#define CODE_MEMORY_MAP_LENGTH (64 + 1) 433#define DATA_MEMORY_MAP_LENGTH (64 + 1) 434 435#if (CODE_MEMORY_MAP_LENGTH < ((REV_A_CODE_MEMORY_LENGTH / REV_A_CODE_MEMORY_UNIT_LENGTH) + 1)) 436#error Code memory map length too short. 437#endif 438#if (DATA_MEMORY_MAP_LENGTH < ((REV_A_DATA_MEMORY_LENGTH / REV_A_DATA_MEMORY_UNIT_LENGTH) + 1)) 439#error Data memory map length too short. 440#endif 441#if (CODE_MEMORY_MAP_LENGTH < ((REV_B_CODE_MEMORY_LENGTH / REV_B_CODE_MEMORY_UNIT_LENGTH) + 1)) 442#error Code memory map length too short. 443#endif 444#if (DATA_MEMORY_MAP_LENGTH < ((REV_B_DATA_MEMORY_LENGTH / REV_B_DATA_MEMORY_UNIT_LENGTH) + 1)) 445#error Data memory map length too short. 446#endif 447 448/* 449 * Kernel code memory definition 450 */ 451 452#define KCODE_VECTORS_BEGIN 0x0000 453#define KCODE_VECTORS_END 0x002F 454#define KCODE_VECTORS_UNIT_LENGTH 0x0002 455#define KCODE_VECTORS_LENGTH (KCODE_VECTORS_END - KCODE_VECTORS_BEGIN + 1) 456 457/* 458 * Kernel data memory definition 459 */ 460 461#define KDATA_BASE_ADDR 0x1000 462#define KDATA_BASE_ADDR2 0x1080 463 464#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) 465#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) 466#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) 467#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) 468#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) 469#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) 470#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) 471#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) 472#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) 473 474#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) 475#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) 476 477#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) 478#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) 479#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) 480#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) 481#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) 482#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) 483#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) 484#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) 485#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) 486#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) 487 488#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) 489#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) 490 491#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) 492#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) 493 494#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) 495#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) 496 497#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) 498#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) 499#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) 500 501#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) 502#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) 503#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) 504#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) 505#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) 506 507#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) 508#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) 509#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) 510 511#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) 512#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) 513#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) 514 515#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) 516#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) 517#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) 518#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) 519#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) 520#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) 521#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) 522#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) 523#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) 524#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) 525 526#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) 527#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) 528#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) 529 530#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) 531#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) 532 533#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) 534#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) 535#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) 536 537#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) 538#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) 539#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) 540#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) 541#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) 542#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) 543 544#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) 545#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) 546#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) 547#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) 548#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) 549#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) 550 551#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) 552#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) 553#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) 554#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) 555#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) 556#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) 557 558#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) 559#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) 560#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) 561#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) 562 563#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) 564#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) 565 566#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) 567#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) 568 569#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) 570#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) 571#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) 572#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) 573#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) 574 575#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) 576#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) 577 578/*AY SPDIF IN */ 579#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) 580#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) 581#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) 582 583#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) 584#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) 585 586#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) 587 588#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) 589#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) 590#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) 591#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) 592#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) 593#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) 594#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) 595#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) 596#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) 597#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) 598#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) 599#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) 600 601#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) 602#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) 603#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) 604#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) 605 606#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) 607#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) 608 609#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) 610#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) 611#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) 612#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) 613 614#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) 615#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) 616#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) 617#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) 618#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) 619 620/* 621 * second segment 622 */ 623 624/* smart mixer buffer */ 625 626#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) 627#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) 628#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) 629#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) 630#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) 631#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) 632#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) 633#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) 634#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) 635#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) 636#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) 637#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) 638#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) 639#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) 640#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) 641#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) 642 643#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) 644#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) 645#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) 646#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) 647#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) 648#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) 649#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) 650#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) 651#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) 652#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) 653#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) 654 655#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) 656#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) 657#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) 658#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) 659#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) 660#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) 661 662/* 663 * Client data memory definition 664 */ 665 666#define CDATA_INSTANCE_READY 0x00 667 668#define CDATA_HOST_SRC_ADDRL 0x01 669#define CDATA_HOST_SRC_ADDRH 0x02 670#define CDATA_HOST_SRC_END_PLUS_1L 0x03 671#define CDATA_HOST_SRC_END_PLUS_1H 0x04 672#define CDATA_HOST_SRC_CURRENTL 0x05 673#define CDATA_HOST_SRC_CURRENTH 0x06 674 675#define CDATA_IN_BUF_CONNECT 0x07 676#define CDATA_OUT_BUF_CONNECT 0x08 677 678#define CDATA_IN_BUF_BEGIN 0x09 679#define CDATA_IN_BUF_END_PLUS_1 0x0A 680#define CDATA_IN_BUF_HEAD 0x0B 681#define CDATA_IN_BUF_TAIL 0x0C 682 683#define CDATA_OUT_BUF_BEGIN 0x0D 684#define CDATA_OUT_BUF_END_PLUS_1 0x0E 685#define CDATA_OUT_BUF_HEAD 0x0F 686#define CDATA_OUT_BUF_TAIL 0x10 687 688#define CDATA_DMA_CONTROL 0x11 689#define CDATA_RESERVED 0x12 690 691#define CDATA_FREQUENCY 0x13 692#define CDATA_LEFT_VOLUME 0x14 693#define CDATA_RIGHT_VOLUME 0x15 694#define CDATA_LEFT_SUR_VOL 0x16 695#define CDATA_RIGHT_SUR_VOL 0x17 696 697/* These are from Allegro hckernel.h */ 698#define CDATA_HEADER_LEN 0x18 699#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN 700#define SRC3_MODE_OFFSET CDATA_HEADER_LEN + 1 701#define SRC3_WORD_LENGTH_OFFSET CDATA_HEADER_LEN + 2 702#define SRC3_PARAMETER_OFFSET CDATA_HEADER_LEN + 3 703#define SRC3_COEFF_ADDR_OFFSET CDATA_HEADER_LEN + 8 704#define SRC3_FILTAP_ADDR_OFFSET CDATA_HEADER_LEN + 10 705#define SRC3_TEMP_INBUF_ADDR_OFFSET CDATA_HEADER_LEN + 16 706#define SRC3_TEMP_OUTBUF_ADDR_OFFSET CDATA_HEADER_LEN + 17 707#define FOR_FUTURE_USE 10 /* for storing temporary variable in future */ 708 709/* 710 * DMA control definition 711 */ 712 713#define DMACONTROL_BLOCK_MASK 0x000F 714#define DMAC_BLOCK0_SELECTOR 0x0000 715#define DMAC_BLOCK1_SELECTOR 0x0001 716#define DMAC_BLOCK2_SELECTOR 0x0002 717#define DMAC_BLOCK3_SELECTOR 0x0003 718#define DMAC_BLOCK4_SELECTOR 0x0004 719#define DMAC_BLOCK5_SELECTOR 0x0005 720#define DMAC_BLOCK6_SELECTOR 0x0006 721#define DMAC_BLOCK7_SELECTOR 0x0007 722#define DMAC_BLOCK8_SELECTOR 0x0008 723#define DMAC_BLOCK9_SELECTOR 0x0009 724#define DMAC_BLOCKA_SELECTOR 0x000A 725#define DMAC_BLOCKB_SELECTOR 0x000B 726#define DMAC_BLOCKC_SELECTOR 0x000C 727#define DMAC_BLOCKD_SELECTOR 0x000D 728#define DMAC_BLOCKE_SELECTOR 0x000E 729#define DMAC_BLOCKF_SELECTOR 0x000F 730#define DMACONTROL_PAGE_MASK 0x00F0 731#define DMAC_PAGE0_SELECTOR 0x0030 732#define DMAC_PAGE1_SELECTOR 0x0020 733#define DMAC_PAGE2_SELECTOR 0x0010 734#define DMAC_PAGE3_SELECTOR 0x0000 735#define DMACONTROL_AUTOREPEAT 0x1000 736#define DMACONTROL_STOPPED 0x2000 737#define DMACONTROL_DIRECTION 0x0100 738 739/* 740 * Kernel/client memory allocation 741 */ 742 743#define NUM_UNITS_KERNEL_CODE 16 744#define NUM_UNITS_KERNEL_DATA 2 745 746#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 747#ifdef M3_MODEL 748#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 749#else 750#define NUM_UNITS_KERNEL_DATA_WITH_HSP 4 751#endif 752 753#define NUM_UNITS( BYTES, UNITLEN ) ((((BYTES+1)>>1) + (UNITLEN-1)) / UNITLEN) 754 755/* 756 * DSP hardware 757 */ 758 759#define DSP_PORT_TIMER_COUNT 0x06 760#define DSP_PORT_MEMORY_INDEX 0x80 761#define DSP_PORT_MEMORY_TYPE 0x82 762#define DSP_PORT_MEMORY_DATA 0x84 763#define DSP_PORT_CONTROL_REG_A 0xA2 764#define DSP_PORT_CONTROL_REG_B 0xA4 765#define DSP_PORT_CONTROL_REG_C 0xA6 766 767#define MEMTYPE_INTERNAL_CODE 0x0002 768#define MEMTYPE_INTERNAL_DATA 0x0003 769#define MEMTYPE_MASK 0x0003 770 771#define REGB_ENABLE_RESET 0x01 772#define REGB_STOP_CLOCK 0x10 773 774#define REGC_DISABLE_FM_MAPPING 0x02 775 776#define DP_SHIFT_COUNT 7 777 778#define DMA_BLOCK_LENGTH 32 779 780/* These are from Allegro srcmgr.h */ 781#define MINISRC_BIQUAD_STAGE 2 782#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) 783#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) 784#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) 785#define MINISRC_BIQUAD_STAGE 2 786/* M. SRC LPF coefficient could be changed in the DSP code */ 787#define MINISRC_COEF_LOC 0X175 788 789#endif /* !_DEV_SOUND_PCI_ALLEGRO_REG_H */ 790