1/* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3/*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000 7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Bill Paul. 20 * 4. Neither the name of the author nor the names of any co-contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 38 * 39 * Permission to use, copy, modify, and distribute this software for any 40 * purpose with or without fee is hereby granted, provided that the above 41 * copyright notice and this permission notice appear in all copies. 42 * 43 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 44 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 46 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 47 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 48 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 49 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 50 */ 51 52#include <sys/cdefs.h> 53__FBSDID("$FreeBSD$"); 54 55/* 56 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 57 * the SK-984x series adapters, both single port and dual port. 58 * References: 59 * The XaQti XMAC II datasheet, 60 * https://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 61 * The SysKonnect GEnesis manual, http://www.syskonnect.com 62 * 63 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 64 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 65 * convenience to others until Vitesse corrects this problem: 66 * 67 * https://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 68 * 69 * Written by Bill Paul <wpaul@ee.columbia.edu> 70 * Department of Electrical Engineering 71 * Columbia University, New York City 72 */ 73/* 74 * The SysKonnect gigabit ethernet adapters consist of two main 75 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 76 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 77 * components and a PHY while the GEnesis controller provides a PCI 78 * interface with DMA support. Each card may have between 512K and 79 * 2MB of SRAM on board depending on the configuration. 80 * 81 * The SysKonnect GEnesis controller can have either one or two XMAC 82 * chips connected to it, allowing single or dual port NIC configurations. 83 * SysKonnect has the distinction of being the only vendor on the market 84 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 85 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 86 * XMAC registers. This driver takes advantage of these features to allow 87 * both XMACs to operate as independent interfaces. 88 */ 89 90#include <sys/param.h> 91#include <sys/systm.h> 92#include <sys/bus.h> 93#include <sys/endian.h> 94#include <sys/mbuf.h> 95#include <sys/malloc.h> 96#include <sys/kernel.h> 97#include <sys/module.h> 98#include <sys/socket.h> 99#include <sys/sockio.h> 100#include <sys/queue.h> 101#include <sys/sysctl.h> 102 103#include <net/bpf.h> 104#include <net/ethernet.h> 105#include <net/if.h> 106#include <net/if_var.h> 107#include <net/if_arp.h> 108#include <net/if_dl.h> 109#include <net/if_media.h> 110#include <net/if_types.h> 111#include <net/if_vlan_var.h> 112 113#include <netinet/in.h> 114#include <netinet/in_systm.h> 115#include <netinet/ip.h> 116 117#include <machine/bus.h> 118#include <machine/in_cksum.h> 119#include <machine/resource.h> 120#include <sys/rman.h> 121 122#include <dev/mii/mii.h> 123#include <dev/mii/miivar.h> 124#include <dev/mii/brgphyreg.h> 125 126#include <dev/pci/pcireg.h> 127#include <dev/pci/pcivar.h> 128 129#if 0 130#define SK_USEIOSPACE 131#endif 132 133#include <dev/sk/if_skreg.h> 134#include <dev/sk/xmaciireg.h> 135#include <dev/sk/yukonreg.h> 136 137MODULE_DEPEND(sk, pci, 1, 1, 1); 138MODULE_DEPEND(sk, ether, 1, 1, 1); 139MODULE_DEPEND(sk, miibus, 1, 1, 1); 140 141/* "device miibus" required. See GENERIC if you get errors here. */ 142#include "miibus_if.h" 143 144static const struct sk_type sk_devs[] = { 145 { 146 VENDORID_SK, 147 DEVICEID_SK_V1, 148 "SysKonnect Gigabit Ethernet (V1.0)" 149 }, 150 { 151 VENDORID_SK, 152 DEVICEID_SK_V2, 153 "SysKonnect Gigabit Ethernet (V2.0)" 154 }, 155 { 156 VENDORID_MARVELL, 157 DEVICEID_SK_V2, 158 "Marvell Gigabit Ethernet" 159 }, 160 { 161 VENDORID_MARVELL, 162 DEVICEID_BELKIN_5005, 163 "Belkin F5D5005 Gigabit Ethernet" 164 }, 165 { 166 VENDORID_3COM, 167 DEVICEID_3COM_3C940, 168 "3Com 3C940 Gigabit Ethernet" 169 }, 170 { 171 VENDORID_LINKSYS, 172 DEVICEID_LINKSYS_EG1032, 173 "Linksys EG1032 Gigabit Ethernet" 174 }, 175 { 176 VENDORID_DLINK, 177 DEVICEID_DLINK_DGE530T_A1, 178 "D-Link DGE-530T Gigabit Ethernet" 179 }, 180 { 181 VENDORID_DLINK, 182 DEVICEID_DLINK_DGE530T_B1, 183 "D-Link DGE-530T Gigabit Ethernet" 184 }, 185 { 0, 0, NULL } 186}; 187 188static int skc_probe(device_t); 189static int skc_attach(device_t); 190static int skc_detach(device_t); 191static int skc_shutdown(device_t); 192static int skc_suspend(device_t); 193static int skc_resume(device_t); 194static bus_dma_tag_t skc_get_dma_tag(device_t, device_t); 195static int sk_detach(device_t); 196static int sk_probe(device_t); 197static int sk_attach(device_t); 198static void sk_tick(void *); 199static void sk_yukon_tick(void *); 200static void sk_intr(void *); 201static void sk_intr_xmac(struct sk_if_softc *); 202static void sk_intr_bcom(struct sk_if_softc *); 203static void sk_intr_yukon(struct sk_if_softc *); 204static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t); 205static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 206static void sk_rxeof(struct sk_if_softc *); 207static void sk_jumbo_rxeof(struct sk_if_softc *); 208static void sk_txeof(struct sk_if_softc *); 209static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *); 210static int sk_encap(struct sk_if_softc *, struct mbuf **); 211static void sk_start(struct ifnet *); 212static void sk_start_locked(struct ifnet *); 213static int sk_ioctl(struct ifnet *, u_long, caddr_t); 214static void sk_init(void *); 215static void sk_init_locked(struct sk_if_softc *); 216static void sk_init_xmac(struct sk_if_softc *); 217static void sk_init_yukon(struct sk_if_softc *); 218static void sk_stop(struct sk_if_softc *); 219static void sk_watchdog(void *); 220static int sk_ifmedia_upd(struct ifnet *); 221static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 222static void sk_reset(struct sk_softc *); 223static __inline void sk_discard_rxbuf(struct sk_if_softc *, int); 224static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int); 225static int sk_newbuf(struct sk_if_softc *, int); 226static int sk_jumbo_newbuf(struct sk_if_softc *, int); 227static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 228static int sk_dma_alloc(struct sk_if_softc *); 229static int sk_dma_jumbo_alloc(struct sk_if_softc *); 230static void sk_dma_free(struct sk_if_softc *); 231static void sk_dma_jumbo_free(struct sk_if_softc *); 232static int sk_init_rx_ring(struct sk_if_softc *); 233static int sk_init_jumbo_rx_ring(struct sk_if_softc *); 234static void sk_init_tx_ring(struct sk_if_softc *); 235static u_int32_t sk_win_read_4(struct sk_softc *, int); 236static u_int16_t sk_win_read_2(struct sk_softc *, int); 237static u_int8_t sk_win_read_1(struct sk_softc *, int); 238static void sk_win_write_4(struct sk_softc *, int, u_int32_t); 239static void sk_win_write_2(struct sk_softc *, int, u_int32_t); 240static void sk_win_write_1(struct sk_softc *, int, u_int32_t); 241 242static int sk_miibus_readreg(device_t, int, int); 243static int sk_miibus_writereg(device_t, int, int, int); 244static void sk_miibus_statchg(device_t); 245 246static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 247static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, 248 int); 249static void sk_xmac_miibus_statchg(struct sk_if_softc *); 250 251static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 252static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, 253 int); 254static void sk_marv_miibus_statchg(struct sk_if_softc *); 255 256static uint32_t sk_xmchash(const uint8_t *); 257static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int); 258static void sk_rxfilter(struct sk_if_softc *); 259static void sk_rxfilter_genesis(struct sk_if_softc *); 260static void sk_rxfilter_yukon(struct sk_if_softc *); 261 262static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); 263static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS); 264 265/* Tunables. */ 266static int jumbo_disable = 0; 267TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable); 268 269/* 270 * It seems that SK-NET GENESIS supports very simple checksum offload 271 * capability for Tx and I believe it can generate 0 checksum value for 272 * UDP packets in Tx as the hardware can't differenciate UDP packets from 273 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it 274 * means sender didn't perforam checksum computation. For the safety I 275 * disabled UDP checksum offload capability at the moment. 276 */ 277#define SK_CSUM_FEATURES (CSUM_TCP) 278 279/* 280 * Note that we have newbus methods for both the GEnesis controller 281 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 282 * the miibus code is a child of the XMACs. We need to do it this way 283 * so that the miibus drivers can access the PHY registers on the 284 * right PHY. It's not quite what I had in mind, but it's the only 285 * design that achieves the desired effect. 286 */ 287static device_method_t skc_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, skc_probe), 290 DEVMETHOD(device_attach, skc_attach), 291 DEVMETHOD(device_detach, skc_detach), 292 DEVMETHOD(device_suspend, skc_suspend), 293 DEVMETHOD(device_resume, skc_resume), 294 DEVMETHOD(device_shutdown, skc_shutdown), 295 296 DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag), 297 298 DEVMETHOD_END 299}; 300 301static driver_t skc_driver = { 302 "skc", 303 skc_methods, 304 sizeof(struct sk_softc) 305}; 306 307static devclass_t skc_devclass; 308 309static device_method_t sk_methods[] = { 310 /* Device interface */ 311 DEVMETHOD(device_probe, sk_probe), 312 DEVMETHOD(device_attach, sk_attach), 313 DEVMETHOD(device_detach, sk_detach), 314 DEVMETHOD(device_shutdown, bus_generic_shutdown), 315 316 /* MII interface */ 317 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 318 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 319 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 320 321 DEVMETHOD_END 322}; 323 324static driver_t sk_driver = { 325 "sk", 326 sk_methods, 327 sizeof(struct sk_if_softc) 328}; 329 330static devclass_t sk_devclass; 331 332DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, NULL, NULL); 333DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, NULL, NULL); 334DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL); 335 336static struct resource_spec sk_res_spec_io[] = { 337 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 338 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 339 { -1, 0, 0 } 340}; 341 342static struct resource_spec sk_res_spec_mem[] = { 343 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 344 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 345 { -1, 0, 0 } 346}; 347 348#define SK_SETBIT(sc, reg, x) \ 349 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 350 351#define SK_CLRBIT(sc, reg, x) \ 352 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 353 354#define SK_WIN_SETBIT_4(sc, reg, x) \ 355 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 356 357#define SK_WIN_CLRBIT_4(sc, reg, x) \ 358 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 359 360#define SK_WIN_SETBIT_2(sc, reg, x) \ 361 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 362 363#define SK_WIN_CLRBIT_2(sc, reg, x) \ 364 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 365 366static u_int32_t 367sk_win_read_4(sc, reg) 368 struct sk_softc *sc; 369 int reg; 370{ 371#ifdef SK_USEIOSPACE 372 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 373 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 374#else 375 return(CSR_READ_4(sc, reg)); 376#endif 377} 378 379static u_int16_t 380sk_win_read_2(sc, reg) 381 struct sk_softc *sc; 382 int reg; 383{ 384#ifdef SK_USEIOSPACE 385 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 386 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 387#else 388 return(CSR_READ_2(sc, reg)); 389#endif 390} 391 392static u_int8_t 393sk_win_read_1(sc, reg) 394 struct sk_softc *sc; 395 int reg; 396{ 397#ifdef SK_USEIOSPACE 398 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 399 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 400#else 401 return(CSR_READ_1(sc, reg)); 402#endif 403} 404 405static void 406sk_win_write_4(sc, reg, val) 407 struct sk_softc *sc; 408 int reg; 409 u_int32_t val; 410{ 411#ifdef SK_USEIOSPACE 412 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 413 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 414#else 415 CSR_WRITE_4(sc, reg, val); 416#endif 417 return; 418} 419 420static void 421sk_win_write_2(sc, reg, val) 422 struct sk_softc *sc; 423 int reg; 424 u_int32_t val; 425{ 426#ifdef SK_USEIOSPACE 427 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 428 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 429#else 430 CSR_WRITE_2(sc, reg, val); 431#endif 432 return; 433} 434 435static void 436sk_win_write_1(sc, reg, val) 437 struct sk_softc *sc; 438 int reg; 439 u_int32_t val; 440{ 441#ifdef SK_USEIOSPACE 442 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 443 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 444#else 445 CSR_WRITE_1(sc, reg, val); 446#endif 447 return; 448} 449 450static int 451sk_miibus_readreg(dev, phy, reg) 452 device_t dev; 453 int phy, reg; 454{ 455 struct sk_if_softc *sc_if; 456 int v; 457 458 sc_if = device_get_softc(dev); 459 460 SK_IF_MII_LOCK(sc_if); 461 switch(sc_if->sk_softc->sk_type) { 462 case SK_GENESIS: 463 v = sk_xmac_miibus_readreg(sc_if, phy, reg); 464 break; 465 case SK_YUKON: 466 case SK_YUKON_LITE: 467 case SK_YUKON_LP: 468 v = sk_marv_miibus_readreg(sc_if, phy, reg); 469 break; 470 default: 471 v = 0; 472 break; 473 } 474 SK_IF_MII_UNLOCK(sc_if); 475 476 return (v); 477} 478 479static int 480sk_miibus_writereg(dev, phy, reg, val) 481 device_t dev; 482 int phy, reg, val; 483{ 484 struct sk_if_softc *sc_if; 485 int v; 486 487 sc_if = device_get_softc(dev); 488 489 SK_IF_MII_LOCK(sc_if); 490 switch(sc_if->sk_softc->sk_type) { 491 case SK_GENESIS: 492 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val); 493 break; 494 case SK_YUKON: 495 case SK_YUKON_LITE: 496 case SK_YUKON_LP: 497 v = sk_marv_miibus_writereg(sc_if, phy, reg, val); 498 break; 499 default: 500 v = 0; 501 break; 502 } 503 SK_IF_MII_UNLOCK(sc_if); 504 505 return (v); 506} 507 508static void 509sk_miibus_statchg(dev) 510 device_t dev; 511{ 512 struct sk_if_softc *sc_if; 513 514 sc_if = device_get_softc(dev); 515 516 SK_IF_MII_LOCK(sc_if); 517 switch(sc_if->sk_softc->sk_type) { 518 case SK_GENESIS: 519 sk_xmac_miibus_statchg(sc_if); 520 break; 521 case SK_YUKON: 522 case SK_YUKON_LITE: 523 case SK_YUKON_LP: 524 sk_marv_miibus_statchg(sc_if); 525 break; 526 } 527 SK_IF_MII_UNLOCK(sc_if); 528 529 return; 530} 531 532static int 533sk_xmac_miibus_readreg(sc_if, phy, reg) 534 struct sk_if_softc *sc_if; 535 int phy, reg; 536{ 537 int i; 538 539 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 540 SK_XM_READ_2(sc_if, XM_PHY_DATA); 541 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 542 for (i = 0; i < SK_TIMEOUT; i++) { 543 DELAY(1); 544 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 545 XM_MMUCMD_PHYDATARDY) 546 break; 547 } 548 549 if (i == SK_TIMEOUT) { 550 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 551 return(0); 552 } 553 } 554 DELAY(1); 555 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 556 557 return(i); 558} 559 560static int 561sk_xmac_miibus_writereg(sc_if, phy, reg, val) 562 struct sk_if_softc *sc_if; 563 int phy, reg, val; 564{ 565 int i; 566 567 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 568 for (i = 0; i < SK_TIMEOUT; i++) { 569 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 570 break; 571 } 572 573 if (i == SK_TIMEOUT) { 574 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 575 return (ETIMEDOUT); 576 } 577 578 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 579 for (i = 0; i < SK_TIMEOUT; i++) { 580 DELAY(1); 581 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 582 break; 583 } 584 if (i == SK_TIMEOUT) 585 if_printf(sc_if->sk_ifp, "phy write timed out\n"); 586 587 return(0); 588} 589 590static void 591sk_xmac_miibus_statchg(sc_if) 592 struct sk_if_softc *sc_if; 593{ 594 struct mii_data *mii; 595 596 mii = device_get_softc(sc_if->sk_miibus); 597 598 /* 599 * If this is a GMII PHY, manually set the XMAC's 600 * duplex mode accordingly. 601 */ 602 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 603 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 604 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 605 } else { 606 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 607 } 608 } 609} 610 611static int 612sk_marv_miibus_readreg(sc_if, phy, reg) 613 struct sk_if_softc *sc_if; 614 int phy, reg; 615{ 616 u_int16_t val; 617 int i; 618 619 if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 620 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) { 621 return(0); 622 } 623 624 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 625 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 626 627 for (i = 0; i < SK_TIMEOUT; i++) { 628 DELAY(1); 629 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 630 if (val & YU_SMICR_READ_VALID) 631 break; 632 } 633 634 if (i == SK_TIMEOUT) { 635 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 636 return(0); 637 } 638 639 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 640 641 return(val); 642} 643 644static int 645sk_marv_miibus_writereg(sc_if, phy, reg, val) 646 struct sk_if_softc *sc_if; 647 int phy, reg, val; 648{ 649 int i; 650 651 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 652 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 653 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 654 655 for (i = 0; i < SK_TIMEOUT; i++) { 656 DELAY(1); 657 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0) 658 break; 659 } 660 if (i == SK_TIMEOUT) 661 if_printf(sc_if->sk_ifp, "phy write timeout\n"); 662 663 return(0); 664} 665 666static void 667sk_marv_miibus_statchg(sc_if) 668 struct sk_if_softc *sc_if; 669{ 670 return; 671} 672 673#define HASH_BITS 6 674 675static u_int32_t 676sk_xmchash(addr) 677 const uint8_t *addr; 678{ 679 uint32_t crc; 680 681 /* Compute CRC for the address value. */ 682 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 683 684 return (~crc & ((1 << HASH_BITS) - 1)); 685} 686 687static void 688sk_setfilt(sc_if, addr, slot) 689 struct sk_if_softc *sc_if; 690 u_int16_t *addr; 691 int slot; 692{ 693 int base; 694 695 base = XM_RXFILT_ENTRY(slot); 696 697 SK_XM_WRITE_2(sc_if, base, addr[0]); 698 SK_XM_WRITE_2(sc_if, base + 2, addr[1]); 699 SK_XM_WRITE_2(sc_if, base + 4, addr[2]); 700 701 return; 702} 703 704static void 705sk_rxfilter(sc_if) 706 struct sk_if_softc *sc_if; 707{ 708 struct sk_softc *sc; 709 710 SK_IF_LOCK_ASSERT(sc_if); 711 712 sc = sc_if->sk_softc; 713 if (sc->sk_type == SK_GENESIS) 714 sk_rxfilter_genesis(sc_if); 715 else 716 sk_rxfilter_yukon(sc_if); 717} 718 719struct sk_add_maddr_genesis_ctx { 720 struct sk_if_softc *sc_if; 721 uint32_t hashes[2]; 722 uint32_t mode; 723}; 724 725static u_int 726sk_add_maddr_genesis(void *arg, struct sockaddr_dl *sdl, u_int cnt) 727{ 728 struct sk_add_maddr_genesis_ctx *ctx = arg; 729 int h; 730 731 /* 732 * Program the first XM_RXFILT_MAX multicast groups 733 * into the perfect filter. 734 */ 735 if (cnt + 1 < XM_RXFILT_MAX) { 736 sk_setfilt(ctx->sc_if, (uint16_t *)LLADDR(sdl), cnt + 1); 737 ctx->mode |= XM_MODE_RX_USE_PERFECT; 738 return (1); 739 } 740 h = sk_xmchash((const uint8_t *)LLADDR(sdl)); 741 if (h < 32) 742 ctx->hashes[0] |= (1 << h); 743 else 744 ctx->hashes[1] |= (1 << (h - 32)); 745 ctx->mode |= XM_MODE_RX_USE_HASH; 746 747 return (1); 748} 749 750static void 751sk_rxfilter_genesis(struct sk_if_softc *sc_if) 752{ 753 struct ifnet *ifp = sc_if->sk_ifp; 754 struct sk_add_maddr_genesis_ctx ctx = { sc_if, { 0, 0 } }; 755 int i; 756 u_int16_t dummy[] = { 0, 0, 0 }; 757 758 SK_IF_LOCK_ASSERT(sc_if); 759 760 ctx.mode = SK_XM_READ_4(sc_if, XM_MODE); 761 ctx.mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH | 762 XM_MODE_RX_USE_PERFECT); 763 /* First, zot all the existing perfect filters. */ 764 for (i = 1; i < XM_RXFILT_MAX; i++) 765 sk_setfilt(sc_if, dummy, i); 766 767 /* Now program new ones. */ 768 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 769 if (ifp->if_flags & IFF_ALLMULTI) 770 ctx.mode |= XM_MODE_RX_USE_HASH; 771 if (ifp->if_flags & IFF_PROMISC) 772 ctx.mode |= XM_MODE_RX_PROMISC; 773 ctx.hashes[0] = 0xFFFFFFFF; 774 ctx.hashes[1] = 0xFFFFFFFF; 775 } else 776 /* XXX want to maintain reverse semantics */ 777 if_foreach_llmaddr(ifp, sk_add_maddr_genesis, &ctx); 778 779 SK_XM_WRITE_4(sc_if, XM_MODE, ctx.mode); 780 SK_XM_WRITE_4(sc_if, XM_MAR0, ctx.hashes[0]); 781 SK_XM_WRITE_4(sc_if, XM_MAR2, ctx.hashes[1]); 782} 783 784static u_int 785sk_hash_maddr_yukon(void *arg, struct sockaddr_dl *sdl, u_int cnt) 786{ 787 uint32_t crc, *hashes = arg; 788 789 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 790 /* Just want the 6 least significant bits. */ 791 crc &= 0x3f; 792 /* Set the corresponding bit in the hash table. */ 793 hashes[crc >> 5] |= 1 << (crc & 0x1f); 794 795 return (1); 796} 797 798static void 799sk_rxfilter_yukon(struct sk_if_softc *sc_if) 800{ 801 struct ifnet *ifp; 802 uint32_t hashes[2] = { 0, 0 }, mode; 803 804 SK_IF_LOCK_ASSERT(sc_if); 805 806 ifp = sc_if->sk_ifp; 807 mode = SK_YU_READ_2(sc_if, YUKON_RCR); 808 if (ifp->if_flags & IFF_PROMISC) 809 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 810 else if (ifp->if_flags & IFF_ALLMULTI) { 811 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN; 812 hashes[0] = 0xFFFFFFFF; 813 hashes[1] = 0xFFFFFFFF; 814 } else { 815 mode |= YU_RCR_UFLEN; 816 if_foreach_llmaddr(ifp, sk_hash_maddr_yukon, hashes); 817 if (hashes[0] != 0 || hashes[1] != 0) 818 mode |= YU_RCR_MUFLEN; 819 } 820 821 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 822 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 823 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 824 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 825 SK_YU_WRITE_2(sc_if, YUKON_RCR, mode); 826} 827 828static int 829sk_init_rx_ring(sc_if) 830 struct sk_if_softc *sc_if; 831{ 832 struct sk_ring_data *rd; 833 bus_addr_t addr; 834 u_int32_t csum_start; 835 int i; 836 837 sc_if->sk_cdata.sk_rx_cons = 0; 838 839 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 | 840 ETHER_HDR_LEN; 841 rd = &sc_if->sk_rdata; 842 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 843 for (i = 0; i < SK_RX_RING_CNT; i++) { 844 if (sk_newbuf(sc_if, i) != 0) 845 return (ENOBUFS); 846 if (i == (SK_RX_RING_CNT - 1)) 847 addr = SK_RX_RING_ADDR(sc_if, 0); 848 else 849 addr = SK_RX_RING_ADDR(sc_if, i + 1); 850 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 851 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start); 852 } 853 854 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 855 sc_if->sk_cdata.sk_rx_ring_map, 856 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 857 858 return(0); 859} 860 861static int 862sk_init_jumbo_rx_ring(sc_if) 863 struct sk_if_softc *sc_if; 864{ 865 struct sk_ring_data *rd; 866 bus_addr_t addr; 867 u_int32_t csum_start; 868 int i; 869 870 sc_if->sk_cdata.sk_jumbo_rx_cons = 0; 871 872 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) | 873 ETHER_HDR_LEN; 874 rd = &sc_if->sk_rdata; 875 bzero(rd->sk_jumbo_rx_ring, 876 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT); 877 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 878 if (sk_jumbo_newbuf(sc_if, i) != 0) 879 return (ENOBUFS); 880 if (i == (SK_JUMBO_RX_RING_CNT - 1)) 881 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0); 882 else 883 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1); 884 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 885 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start); 886 } 887 888 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 889 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 890 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 891 892 return (0); 893} 894 895static void 896sk_init_tx_ring(sc_if) 897 struct sk_if_softc *sc_if; 898{ 899 struct sk_ring_data *rd; 900 struct sk_txdesc *txd; 901 bus_addr_t addr; 902 int i; 903 904 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq); 905 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq); 906 907 sc_if->sk_cdata.sk_tx_prod = 0; 908 sc_if->sk_cdata.sk_tx_cons = 0; 909 sc_if->sk_cdata.sk_tx_cnt = 0; 910 911 rd = &sc_if->sk_rdata; 912 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 913 for (i = 0; i < SK_TX_RING_CNT; i++) { 914 if (i == (SK_TX_RING_CNT - 1)) 915 addr = SK_TX_RING_ADDR(sc_if, 0); 916 else 917 addr = SK_TX_RING_ADDR(sc_if, i + 1); 918 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 919 txd = &sc_if->sk_cdata.sk_txdesc[i]; 920 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 921 } 922 923 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 924 sc_if->sk_cdata.sk_tx_ring_map, 925 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 926} 927 928static __inline void 929sk_discard_rxbuf(sc_if, idx) 930 struct sk_if_softc *sc_if; 931 int idx; 932{ 933 struct sk_rx_desc *r; 934 struct sk_rxdesc *rxd; 935 struct mbuf *m; 936 937 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 938 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 939 m = rxd->rx_m; 940 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 941} 942 943static __inline void 944sk_discard_jumbo_rxbuf(sc_if, idx) 945 struct sk_if_softc *sc_if; 946 int idx; 947{ 948 struct sk_rx_desc *r; 949 struct sk_rxdesc *rxd; 950 struct mbuf *m; 951 952 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 953 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 954 m = rxd->rx_m; 955 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 956} 957 958static int 959sk_newbuf(sc_if, idx) 960 struct sk_if_softc *sc_if; 961 int idx; 962{ 963 struct sk_rx_desc *r; 964 struct sk_rxdesc *rxd; 965 struct mbuf *m; 966 bus_dma_segment_t segs[1]; 967 bus_dmamap_t map; 968 int nsegs; 969 970 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 971 if (m == NULL) 972 return (ENOBUFS); 973 m->m_len = m->m_pkthdr.len = MCLBYTES; 974 m_adj(m, ETHER_ALIGN); 975 976 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag, 977 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) { 978 m_freem(m); 979 return (ENOBUFS); 980 } 981 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 982 983 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 984 if (rxd->rx_m != NULL) { 985 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 986 BUS_DMASYNC_POSTREAD); 987 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap); 988 } 989 map = rxd->rx_dmamap; 990 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap; 991 sc_if->sk_cdata.sk_rx_sparemap = map; 992 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 993 BUS_DMASYNC_PREREAD); 994 rxd->rx_m = m; 995 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 996 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 997 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 998 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 999 1000 return (0); 1001} 1002 1003static int 1004sk_jumbo_newbuf(sc_if, idx) 1005 struct sk_if_softc *sc_if; 1006 int idx; 1007{ 1008 struct sk_rx_desc *r; 1009 struct sk_rxdesc *rxd; 1010 struct mbuf *m; 1011 bus_dma_segment_t segs[1]; 1012 bus_dmamap_t map; 1013 int nsegs; 1014 1015 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1016 if (m == NULL) 1017 return (ENOBUFS); 1018 m->m_pkthdr.len = m->m_len = MJUM9BYTES; 1019 /* 1020 * Adjust alignment so packet payload begins on a 1021 * longword boundary. Mandatory for Alpha, useful on 1022 * x86 too. 1023 */ 1024 m_adj(m, ETHER_ALIGN); 1025 1026 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag, 1027 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1028 m_freem(m); 1029 return (ENOBUFS); 1030 } 1031 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1032 1033 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 1034 if (rxd->rx_m != NULL) { 1035 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1036 BUS_DMASYNC_POSTREAD); 1037 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 1038 rxd->rx_dmamap); 1039 } 1040 map = rxd->rx_dmamap; 1041 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap; 1042 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map; 1043 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1044 BUS_DMASYNC_PREREAD); 1045 rxd->rx_m = m; 1046 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 1047 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1048 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1049 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1050 1051 return (0); 1052} 1053 1054/* 1055 * Set media options. 1056 */ 1057static int 1058sk_ifmedia_upd(ifp) 1059 struct ifnet *ifp; 1060{ 1061 struct sk_if_softc *sc_if = ifp->if_softc; 1062 struct mii_data *mii; 1063 1064 mii = device_get_softc(sc_if->sk_miibus); 1065 sk_init(sc_if); 1066 mii_mediachg(mii); 1067 1068 return(0); 1069} 1070 1071/* 1072 * Report current media status. 1073 */ 1074static void 1075sk_ifmedia_sts(ifp, ifmr) 1076 struct ifnet *ifp; 1077 struct ifmediareq *ifmr; 1078{ 1079 struct sk_if_softc *sc_if; 1080 struct mii_data *mii; 1081 1082 sc_if = ifp->if_softc; 1083 mii = device_get_softc(sc_if->sk_miibus); 1084 1085 mii_pollstat(mii); 1086 ifmr->ifm_active = mii->mii_media_active; 1087 ifmr->ifm_status = mii->mii_media_status; 1088 1089 return; 1090} 1091 1092static int 1093sk_ioctl(ifp, command, data) 1094 struct ifnet *ifp; 1095 u_long command; 1096 caddr_t data; 1097{ 1098 struct sk_if_softc *sc_if = ifp->if_softc; 1099 struct ifreq *ifr = (struct ifreq *) data; 1100 int error, mask; 1101 struct mii_data *mii; 1102 1103 error = 0; 1104 switch(command) { 1105 case SIOCSIFMTU: 1106 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU) 1107 error = EINVAL; 1108 else if (ifp->if_mtu != ifr->ifr_mtu) { 1109 if (sc_if->sk_jumbo_disable != 0 && 1110 ifr->ifr_mtu > SK_MAX_FRAMELEN) 1111 error = EINVAL; 1112 else { 1113 SK_IF_LOCK(sc_if); 1114 ifp->if_mtu = ifr->ifr_mtu; 1115 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1116 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1117 sk_init_locked(sc_if); 1118 } 1119 SK_IF_UNLOCK(sc_if); 1120 } 1121 } 1122 break; 1123 case SIOCSIFFLAGS: 1124 SK_IF_LOCK(sc_if); 1125 if (ifp->if_flags & IFF_UP) { 1126 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1127 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1128 & (IFF_PROMISC | IFF_ALLMULTI)) 1129 sk_rxfilter(sc_if); 1130 } else 1131 sk_init_locked(sc_if); 1132 } else { 1133 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1134 sk_stop(sc_if); 1135 } 1136 sc_if->sk_if_flags = ifp->if_flags; 1137 SK_IF_UNLOCK(sc_if); 1138 break; 1139 case SIOCADDMULTI: 1140 case SIOCDELMULTI: 1141 SK_IF_LOCK(sc_if); 1142 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1143 sk_rxfilter(sc_if); 1144 SK_IF_UNLOCK(sc_if); 1145 break; 1146 case SIOCGIFMEDIA: 1147 case SIOCSIFMEDIA: 1148 mii = device_get_softc(sc_if->sk_miibus); 1149 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1150 break; 1151 case SIOCSIFCAP: 1152 SK_IF_LOCK(sc_if); 1153 if (sc_if->sk_softc->sk_type == SK_GENESIS) { 1154 SK_IF_UNLOCK(sc_if); 1155 break; 1156 } 1157 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1158 if ((mask & IFCAP_TXCSUM) != 0 && 1159 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1160 ifp->if_capenable ^= IFCAP_TXCSUM; 1161 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1162 ifp->if_hwassist |= SK_CSUM_FEATURES; 1163 else 1164 ifp->if_hwassist &= ~SK_CSUM_FEATURES; 1165 } 1166 if ((mask & IFCAP_RXCSUM) != 0 && 1167 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 1168 ifp->if_capenable ^= IFCAP_RXCSUM; 1169 SK_IF_UNLOCK(sc_if); 1170 break; 1171 default: 1172 error = ether_ioctl(ifp, command, data); 1173 break; 1174 } 1175 1176 return (error); 1177} 1178 1179/* 1180 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1181 * IDs against our list and return a device name if we find a match. 1182 */ 1183static int 1184skc_probe(dev) 1185 device_t dev; 1186{ 1187 const struct sk_type *t = sk_devs; 1188 1189 while(t->sk_name != NULL) { 1190 if ((pci_get_vendor(dev) == t->sk_vid) && 1191 (pci_get_device(dev) == t->sk_did)) { 1192 /* 1193 * Only attach to rev. 2 of the Linksys EG1032 adapter. 1194 * Rev. 3 is supported by re(4). 1195 */ 1196 if ((t->sk_vid == VENDORID_LINKSYS) && 1197 (t->sk_did == DEVICEID_LINKSYS_EG1032) && 1198 (pci_get_subdevice(dev) != 1199 SUBDEVICEID_LINKSYS_EG1032_REV2)) { 1200 t++; 1201 continue; 1202 } 1203 device_set_desc(dev, t->sk_name); 1204 return (BUS_PROBE_DEFAULT); 1205 } 1206 t++; 1207 } 1208 1209 return(ENXIO); 1210} 1211 1212/* 1213 * Force the GEnesis into reset, then bring it out of reset. 1214 */ 1215static void 1216sk_reset(sc) 1217 struct sk_softc *sc; 1218{ 1219 1220 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1221 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1222 if (SK_YUKON_FAMILY(sc->sk_type)) 1223 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1224 1225 DELAY(1000); 1226 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1227 DELAY(2); 1228 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1229 if (SK_YUKON_FAMILY(sc->sk_type)) 1230 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1231 1232 if (sc->sk_type == SK_GENESIS) { 1233 /* Configure packet arbiter */ 1234 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1235 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1236 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1237 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1238 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1239 } 1240 1241 /* Enable RAM interface */ 1242 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1243 1244 /* 1245 * Configure interrupt moderation. The moderation timer 1246 * defers interrupts specified in the interrupt moderation 1247 * timer mask based on the timeout specified in the interrupt 1248 * moderation timer init register. Each bit in the timer 1249 * register represents one tick, so to specify a timeout in 1250 * microseconds, we have to multiply by the correct number of 1251 * ticks-per-microsecond. 1252 */ 1253 switch (sc->sk_type) { 1254 case SK_GENESIS: 1255 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS; 1256 break; 1257 default: 1258 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON; 1259 break; 1260 } 1261 if (bootverbose) 1262 device_printf(sc->sk_dev, "interrupt moderation is %d us\n", 1263 sc->sk_int_mod); 1264 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 1265 sc->sk_int_ticks)); 1266 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1267 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1268 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1269 1270 return; 1271} 1272 1273static int 1274sk_probe(dev) 1275 device_t dev; 1276{ 1277 struct sk_softc *sc; 1278 1279 sc = device_get_softc(device_get_parent(dev)); 1280 1281 /* 1282 * Not much to do here. We always know there will be 1283 * at least one XMAC present, and if there are two, 1284 * skc_attach() will create a second device instance 1285 * for us. 1286 */ 1287 switch (sc->sk_type) { 1288 case SK_GENESIS: 1289 device_set_desc(dev, "XaQti Corp. XMAC II"); 1290 break; 1291 case SK_YUKON: 1292 case SK_YUKON_LITE: 1293 case SK_YUKON_LP: 1294 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1295 break; 1296 } 1297 1298 return (BUS_PROBE_DEFAULT); 1299} 1300 1301/* 1302 * Each XMAC chip is attached as a separate logical IP interface. 1303 * Single port cards will have only one logical interface of course. 1304 */ 1305static int 1306sk_attach(dev) 1307 device_t dev; 1308{ 1309 struct sk_softc *sc; 1310 struct sk_if_softc *sc_if; 1311 struct ifnet *ifp; 1312 u_int32_t r; 1313 int error, i, phy, port; 1314 u_char eaddr[6]; 1315 u_char inv_mac[] = {0, 0, 0, 0, 0, 0}; 1316 1317 if (dev == NULL) 1318 return(EINVAL); 1319 1320 error = 0; 1321 sc_if = device_get_softc(dev); 1322 sc = device_get_softc(device_get_parent(dev)); 1323 port = *(int *)device_get_ivars(dev); 1324 1325 sc_if->sk_if_dev = dev; 1326 sc_if->sk_port = port; 1327 sc_if->sk_softc = sc; 1328 sc->sk_if[port] = sc_if; 1329 if (port == SK_PORT_A) 1330 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1331 if (port == SK_PORT_B) 1332 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1333 1334 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0); 1335 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0); 1336 1337 if (sk_dma_alloc(sc_if) != 0) { 1338 error = ENOMEM; 1339 goto fail; 1340 } 1341 sk_dma_jumbo_alloc(sc_if); 1342 1343 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER); 1344 if (ifp == NULL) { 1345 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n"); 1346 error = ENOSPC; 1347 goto fail; 1348 } 1349 ifp->if_softc = sc_if; 1350 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1351 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1352 /* 1353 * SK_GENESIS has a bug in checksum offload - From linux. 1354 */ 1355 if (sc_if->sk_softc->sk_type != SK_GENESIS) { 1356 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM; 1357 ifp->if_hwassist = 0; 1358 } else { 1359 ifp->if_capabilities = 0; 1360 ifp->if_hwassist = 0; 1361 } 1362 ifp->if_capenable = ifp->if_capabilities; 1363 /* 1364 * Some revision of Yukon controller generates corrupted 1365 * frame when TX checksum offloading is enabled. The 1366 * frame has a valid checksum value so payload might be 1367 * modified during TX checksum calculation. Disable TX 1368 * checksum offloading but give users chance to enable it 1369 * when they know their controller works without problems 1370 * with TX checksum offloading. 1371 */ 1372 ifp->if_capenable &= ~IFCAP_TXCSUM; 1373 ifp->if_ioctl = sk_ioctl; 1374 ifp->if_start = sk_start; 1375 ifp->if_init = sk_init; 1376 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1377 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1; 1378 IFQ_SET_READY(&ifp->if_snd); 1379 1380 /* 1381 * Get station address for this interface. Note that 1382 * dual port cards actually come with three station 1383 * addresses: one for each port, plus an extra. The 1384 * extra one is used by the SysKonnect driver software 1385 * as a 'virtual' station address for when both ports 1386 * are operating in failover mode. Currently we don't 1387 * use this extra address. 1388 */ 1389 SK_IF_LOCK(sc_if); 1390 for (i = 0; i < ETHER_ADDR_LEN; i++) 1391 eaddr[i] = 1392 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1393 1394 /* Verify whether the station address is invalid or not. */ 1395 if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) { 1396 device_printf(sc_if->sk_if_dev, 1397 "Generating random ethernet address\n"); 1398 r = arc4random(); 1399 /* 1400 * Set OUI to convenient locally assigned address. 'b' 1401 * is 0x62, which has the locally assigned bit set, and 1402 * the broadcast/multicast bit clear. 1403 */ 1404 eaddr[0] = 'b'; 1405 eaddr[1] = 's'; 1406 eaddr[2] = 'd'; 1407 eaddr[3] = (r >> 16) & 0xff; 1408 eaddr[4] = (r >> 8) & 0xff; 1409 eaddr[5] = (r >> 0) & 0xff; 1410 } 1411 /* 1412 * Set up RAM buffer addresses. The NIC will have a certain 1413 * amount of SRAM on it, somewhere between 512K and 2MB. We 1414 * need to divide this up a) between the transmitter and 1415 * receiver and b) between the two XMACs, if this is a 1416 * dual port NIC. Our algotithm is to divide up the memory 1417 * evenly so that everyone gets a fair share. 1418 * 1419 * Just to be contrary, Yukon2 appears to have separate memory 1420 * for each MAC. 1421 */ 1422 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1423 u_int32_t chunk, val; 1424 1425 chunk = sc->sk_ramsize / 2; 1426 val = sc->sk_rboff / sizeof(u_int64_t); 1427 sc_if->sk_rx_ramstart = val; 1428 val += (chunk / sizeof(u_int64_t)); 1429 sc_if->sk_rx_ramend = val - 1; 1430 sc_if->sk_tx_ramstart = val; 1431 val += (chunk / sizeof(u_int64_t)); 1432 sc_if->sk_tx_ramend = val - 1; 1433 } else { 1434 u_int32_t chunk, val; 1435 1436 chunk = sc->sk_ramsize / 4; 1437 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1438 sizeof(u_int64_t); 1439 sc_if->sk_rx_ramstart = val; 1440 val += (chunk / sizeof(u_int64_t)); 1441 sc_if->sk_rx_ramend = val - 1; 1442 sc_if->sk_tx_ramstart = val; 1443 val += (chunk / sizeof(u_int64_t)); 1444 sc_if->sk_tx_ramend = val - 1; 1445 } 1446 1447 /* Read and save PHY type and set PHY address */ 1448 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1449 if (!SK_YUKON_FAMILY(sc->sk_type)) { 1450 switch(sc_if->sk_phytype) { 1451 case SK_PHYTYPE_XMAC: 1452 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1453 break; 1454 case SK_PHYTYPE_BCOM: 1455 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1456 break; 1457 default: 1458 device_printf(sc->sk_dev, "unsupported PHY type: %d\n", 1459 sc_if->sk_phytype); 1460 error = ENODEV; 1461 SK_IF_UNLOCK(sc_if); 1462 goto fail; 1463 } 1464 } else { 1465 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1466 sc->sk_pmd != 'S') { 1467 /* not initialized, punt */ 1468 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1469 sc->sk_coppertype = 1; 1470 } 1471 1472 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1473 1474 if (!(sc->sk_coppertype)) 1475 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1476 } 1477 1478 /* 1479 * Call MI attach routine. Can't hold locks when calling into ether_*. 1480 */ 1481 SK_IF_UNLOCK(sc_if); 1482 ether_ifattach(ifp, eaddr); 1483 SK_IF_LOCK(sc_if); 1484 1485 /* 1486 * The hardware should be ready for VLAN_MTU by default: 1487 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially; 1488 * YU_SMR_MFL_VLAN is set by this driver in Yukon. 1489 * 1490 */ 1491 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1492 ifp->if_capenable |= IFCAP_VLAN_MTU; 1493 /* 1494 * Tell the upper layer(s) we support long frames. 1495 * Must appear after the call to ether_ifattach() because 1496 * ether_ifattach() sets ifi_hdrlen to the default value. 1497 */ 1498 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1499 1500 /* 1501 * Do miibus setup. 1502 */ 1503 phy = MII_PHY_ANY; 1504 switch (sc->sk_type) { 1505 case SK_GENESIS: 1506 sk_init_xmac(sc_if); 1507 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 1508 phy = 0; 1509 break; 1510 case SK_YUKON: 1511 case SK_YUKON_LITE: 1512 case SK_YUKON_LP: 1513 sk_init_yukon(sc_if); 1514 phy = 0; 1515 break; 1516 } 1517 1518 SK_IF_UNLOCK(sc_if); 1519 error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd, 1520 sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 1521 if (error != 0) { 1522 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n"); 1523 ether_ifdetach(ifp); 1524 goto fail; 1525 } 1526 1527fail: 1528 if (error) { 1529 /* Access should be ok even though lock has been dropped */ 1530 sc->sk_if[port] = NULL; 1531 sk_detach(dev); 1532 } 1533 1534 return(error); 1535} 1536 1537/* 1538 * Attach the interface. Allocate softc structures, do ifmedia 1539 * setup and ethernet/BPF attach. 1540 */ 1541static int 1542skc_attach(dev) 1543 device_t dev; 1544{ 1545 struct sk_softc *sc; 1546 int error = 0, *port; 1547 uint8_t skrs; 1548 const char *pname = NULL; 1549 char *revstr; 1550 1551 sc = device_get_softc(dev); 1552 sc->sk_dev = dev; 1553 1554 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1555 MTX_DEF); 1556 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF); 1557 /* 1558 * Map control/status registers. 1559 */ 1560 pci_enable_busmaster(dev); 1561 1562 /* Allocate resources */ 1563#ifdef SK_USEIOSPACE 1564 sc->sk_res_spec = sk_res_spec_io; 1565#else 1566 sc->sk_res_spec = sk_res_spec_mem; 1567#endif 1568 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1569 if (error) { 1570 if (sc->sk_res_spec == sk_res_spec_mem) 1571 sc->sk_res_spec = sk_res_spec_io; 1572 else 1573 sc->sk_res_spec = sk_res_spec_mem; 1574 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1575 if (error) { 1576 device_printf(dev, "couldn't allocate %s resources\n", 1577 sc->sk_res_spec == sk_res_spec_mem ? "memory" : 1578 "I/O"); 1579 goto fail; 1580 } 1581 } 1582 1583 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1584 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf; 1585 1586 /* Bail out if chip is not recognized. */ 1587 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) { 1588 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n", 1589 sc->sk_type, sc->sk_rev); 1590 error = ENXIO; 1591 goto fail; 1592 } 1593 1594 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1595 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1596 OID_AUTO, "int_mod", 1597 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1598 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I", 1599 "SK interrupt moderation"); 1600 1601 /* Pull in device tunables. */ 1602 sc->sk_int_mod = SK_IM_DEFAULT; 1603 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1604 "int_mod", &sc->sk_int_mod); 1605 if (error == 0) { 1606 if (sc->sk_int_mod < SK_IM_MIN || 1607 sc->sk_int_mod > SK_IM_MAX) { 1608 device_printf(dev, "int_mod value out of range; " 1609 "using default: %d\n", SK_IM_DEFAULT); 1610 sc->sk_int_mod = SK_IM_DEFAULT; 1611 } 1612 } 1613 1614 /* Reset the adapter. */ 1615 sk_reset(sc); 1616 1617 skrs = sk_win_read_1(sc, SK_EPROM0); 1618 if (sc->sk_type == SK_GENESIS) { 1619 /* Read and save RAM size and RAMbuffer offset */ 1620 switch(skrs) { 1621 case SK_RAMSIZE_512K_64: 1622 sc->sk_ramsize = 0x80000; 1623 sc->sk_rboff = SK_RBOFF_0; 1624 break; 1625 case SK_RAMSIZE_1024K_64: 1626 sc->sk_ramsize = 0x100000; 1627 sc->sk_rboff = SK_RBOFF_80000; 1628 break; 1629 case SK_RAMSIZE_1024K_128: 1630 sc->sk_ramsize = 0x100000; 1631 sc->sk_rboff = SK_RBOFF_0; 1632 break; 1633 case SK_RAMSIZE_2048K_128: 1634 sc->sk_ramsize = 0x200000; 1635 sc->sk_rboff = SK_RBOFF_0; 1636 break; 1637 default: 1638 device_printf(dev, "unknown ram size: %d\n", skrs); 1639 error = ENXIO; 1640 goto fail; 1641 } 1642 } else { /* SK_YUKON_FAMILY */ 1643 if (skrs == 0x00) 1644 sc->sk_ramsize = 0x20000; 1645 else 1646 sc->sk_ramsize = skrs * (1<<12); 1647 sc->sk_rboff = SK_RBOFF_0; 1648 } 1649 1650 /* Read and save physical media type */ 1651 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1652 1653 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1654 sc->sk_coppertype = 1; 1655 else 1656 sc->sk_coppertype = 0; 1657 1658 /* Determine whether to name it with VPD PN or just make it up. 1659 * Marvell Yukon VPD PN seems to freqently be bogus. */ 1660 switch (pci_get_device(dev)) { 1661 case DEVICEID_SK_V1: 1662 case DEVICEID_BELKIN_5005: 1663 case DEVICEID_3COM_3C940: 1664 case DEVICEID_LINKSYS_EG1032: 1665 case DEVICEID_DLINK_DGE530T_A1: 1666 case DEVICEID_DLINK_DGE530T_B1: 1667 /* Stay with VPD PN. */ 1668 (void) pci_get_vpd_ident(dev, &pname); 1669 break; 1670 case DEVICEID_SK_V2: 1671 /* YUKON VPD PN might bear no resemblance to reality. */ 1672 switch (sc->sk_type) { 1673 case SK_GENESIS: 1674 /* Stay with VPD PN. */ 1675 (void) pci_get_vpd_ident(dev, &pname); 1676 break; 1677 case SK_YUKON: 1678 pname = "Marvell Yukon Gigabit Ethernet"; 1679 break; 1680 case SK_YUKON_LITE: 1681 pname = "Marvell Yukon Lite Gigabit Ethernet"; 1682 break; 1683 case SK_YUKON_LP: 1684 pname = "Marvell Yukon LP Gigabit Ethernet"; 1685 break; 1686 default: 1687 pname = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1688 break; 1689 } 1690 1691 /* Yukon Lite Rev. A0 needs special test. */ 1692 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1693 u_int32_t far; 1694 u_int8_t testbyte; 1695 1696 /* Save flash address register before testing. */ 1697 far = sk_win_read_4(sc, SK_EP_ADDR); 1698 1699 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff); 1700 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03); 1701 1702 if (testbyte != 0x00) { 1703 /* Yukon Lite Rev. A0 detected. */ 1704 sc->sk_type = SK_YUKON_LITE; 1705 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1706 /* Restore flash address register. */ 1707 sk_win_write_4(sc, SK_EP_ADDR, far); 1708 } 1709 } 1710 break; 1711 default: 1712 device_printf(dev, "unknown device: vendor=%04x, device=%04x, " 1713 "chipver=%02x, rev=%x\n", 1714 pci_get_vendor(dev), pci_get_device(dev), 1715 sc->sk_type, sc->sk_rev); 1716 error = ENXIO; 1717 goto fail; 1718 } 1719 1720 if (sc->sk_type == SK_YUKON_LITE) { 1721 switch (sc->sk_rev) { 1722 case SK_YUKON_LITE_REV_A0: 1723 revstr = "A0"; 1724 break; 1725 case SK_YUKON_LITE_REV_A1: 1726 revstr = "A1"; 1727 break; 1728 case SK_YUKON_LITE_REV_A3: 1729 revstr = "A3"; 1730 break; 1731 default: 1732 revstr = ""; 1733 break; 1734 } 1735 } else { 1736 revstr = ""; 1737 } 1738 1739 /* Announce the product name and more VPD data if there. */ 1740 if (pname != NULL) 1741 device_printf(dev, "%s rev. %s(0x%x)\n", 1742 pname, revstr, sc->sk_rev); 1743 1744 if (bootverbose) { 1745 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type); 1746 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev); 1747 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1748 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1749 } 1750 1751 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1752 if (sc->sk_devs[SK_PORT_A] == NULL) { 1753 device_printf(dev, "failed to add child for PORT_A\n"); 1754 error = ENXIO; 1755 goto fail; 1756 } 1757 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1758 if (port == NULL) { 1759 device_printf(dev, "failed to allocate memory for " 1760 "ivars of PORT_A\n"); 1761 error = ENXIO; 1762 goto fail; 1763 } 1764 *port = SK_PORT_A; 1765 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1766 1767 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1768 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1769 if (sc->sk_devs[SK_PORT_B] == NULL) { 1770 device_printf(dev, "failed to add child for PORT_B\n"); 1771 error = ENXIO; 1772 goto fail; 1773 } 1774 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1775 if (port == NULL) { 1776 device_printf(dev, "failed to allocate memory for " 1777 "ivars of PORT_B\n"); 1778 error = ENXIO; 1779 goto fail; 1780 } 1781 *port = SK_PORT_B; 1782 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1783 } 1784 1785 /* Turn on the 'driver is loaded' LED. */ 1786 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1787 1788 error = bus_generic_attach(dev); 1789 if (error) { 1790 device_printf(dev, "failed to attach port(s)\n"); 1791 goto fail; 1792 } 1793 1794 /* Hook interrupt last to avoid having to lock softc */ 1795 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE, 1796 NULL, sk_intr, sc, &sc->sk_intrhand); 1797 1798 if (error) { 1799 device_printf(dev, "couldn't set up irq\n"); 1800 goto fail; 1801 } 1802 1803fail: 1804 if (error) 1805 skc_detach(dev); 1806 1807 return(error); 1808} 1809 1810/* 1811 * Shutdown hardware and free up resources. This can be called any 1812 * time after the mutex has been initialized. It is called in both 1813 * the error case in attach and the normal detach case so it needs 1814 * to be careful about only freeing resources that have actually been 1815 * allocated. 1816 */ 1817static int 1818sk_detach(dev) 1819 device_t dev; 1820{ 1821 struct sk_if_softc *sc_if; 1822 struct ifnet *ifp; 1823 1824 sc_if = device_get_softc(dev); 1825 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1826 ("sk mutex not initialized in sk_detach")); 1827 SK_IF_LOCK(sc_if); 1828 1829 ifp = sc_if->sk_ifp; 1830 /* These should only be active if attach_xmac succeeded */ 1831 if (device_is_attached(dev)) { 1832 sk_stop(sc_if); 1833 /* Can't hold locks while calling detach */ 1834 SK_IF_UNLOCK(sc_if); 1835 callout_drain(&sc_if->sk_tick_ch); 1836 callout_drain(&sc_if->sk_watchdog_ch); 1837 ether_ifdetach(ifp); 1838 SK_IF_LOCK(sc_if); 1839 } 1840 /* 1841 * We're generally called from skc_detach() which is using 1842 * device_delete_child() to get to here. It's already trashed 1843 * miibus for us, so don't do it here or we'll panic. 1844 */ 1845 /* 1846 if (sc_if->sk_miibus != NULL) 1847 device_delete_child(dev, sc_if->sk_miibus); 1848 */ 1849 bus_generic_detach(dev); 1850 sk_dma_jumbo_free(sc_if); 1851 sk_dma_free(sc_if); 1852 SK_IF_UNLOCK(sc_if); 1853 if (ifp) 1854 if_free(ifp); 1855 1856 return(0); 1857} 1858 1859static int 1860skc_detach(dev) 1861 device_t dev; 1862{ 1863 struct sk_softc *sc; 1864 1865 sc = device_get_softc(dev); 1866 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1867 1868 if (device_is_alive(dev)) { 1869 if (sc->sk_devs[SK_PORT_A] != NULL) { 1870 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF); 1871 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1872 } 1873 if (sc->sk_devs[SK_PORT_B] != NULL) { 1874 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF); 1875 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1876 } 1877 bus_generic_detach(dev); 1878 } 1879 1880 if (sc->sk_intrhand) 1881 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand); 1882 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res); 1883 1884 mtx_destroy(&sc->sk_mii_mtx); 1885 mtx_destroy(&sc->sk_mtx); 1886 1887 return(0); 1888} 1889 1890static bus_dma_tag_t 1891skc_get_dma_tag(device_t bus, device_t child __unused) 1892{ 1893 1894 return (bus_get_dma_tag(bus)); 1895} 1896 1897struct sk_dmamap_arg { 1898 bus_addr_t sk_busaddr; 1899}; 1900 1901static void 1902sk_dmamap_cb(arg, segs, nseg, error) 1903 void *arg; 1904 bus_dma_segment_t *segs; 1905 int nseg; 1906 int error; 1907{ 1908 struct sk_dmamap_arg *ctx; 1909 1910 if (error != 0) 1911 return; 1912 1913 ctx = arg; 1914 ctx->sk_busaddr = segs[0].ds_addr; 1915} 1916 1917/* 1918 * Allocate jumbo buffer storage. The SysKonnect adapters support 1919 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1920 * use them in their drivers. In order for us to use them, we need 1921 * large 9K receive buffers, however standard mbuf clusters are only 1922 * 2048 bytes in size. Consequently, we need to allocate and manage 1923 * our own jumbo buffer pool. Fortunately, this does not require an 1924 * excessive amount of additional code. 1925 */ 1926static int 1927sk_dma_alloc(sc_if) 1928 struct sk_if_softc *sc_if; 1929{ 1930 struct sk_dmamap_arg ctx; 1931 struct sk_txdesc *txd; 1932 struct sk_rxdesc *rxd; 1933 int error, i; 1934 1935 /* create parent tag */ 1936 /* 1937 * XXX 1938 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument 1939 * in bus_dma_tag_create(9) as the NIC would support DAC mode. 1940 * However bz@ reported that it does not work on amd64 with > 4GB 1941 * RAM. Until we have more clues of the breakage, disable DAC mode 1942 * by limiting DMA address to be in 32bit address space. 1943 */ 1944 error = bus_dma_tag_create( 1945 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */ 1946 1, 0, /* algnmnt, boundary */ 1947 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1948 BUS_SPACE_MAXADDR, /* highaddr */ 1949 NULL, NULL, /* filter, filterarg */ 1950 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1951 0, /* nsegments */ 1952 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1953 0, /* flags */ 1954 NULL, NULL, /* lockfunc, lockarg */ 1955 &sc_if->sk_cdata.sk_parent_tag); 1956 if (error != 0) { 1957 device_printf(sc_if->sk_if_dev, 1958 "failed to create parent DMA tag\n"); 1959 goto fail; 1960 } 1961 1962 /* create tag for Tx ring */ 1963 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1964 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1965 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1966 BUS_SPACE_MAXADDR, /* highaddr */ 1967 NULL, NULL, /* filter, filterarg */ 1968 SK_TX_RING_SZ, /* maxsize */ 1969 1, /* nsegments */ 1970 SK_TX_RING_SZ, /* maxsegsize */ 1971 0, /* flags */ 1972 NULL, NULL, /* lockfunc, lockarg */ 1973 &sc_if->sk_cdata.sk_tx_ring_tag); 1974 if (error != 0) { 1975 device_printf(sc_if->sk_if_dev, 1976 "failed to allocate Tx ring DMA tag\n"); 1977 goto fail; 1978 } 1979 1980 /* create tag for Rx ring */ 1981 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1982 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1983 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1984 BUS_SPACE_MAXADDR, /* highaddr */ 1985 NULL, NULL, /* filter, filterarg */ 1986 SK_RX_RING_SZ, /* maxsize */ 1987 1, /* nsegments */ 1988 SK_RX_RING_SZ, /* maxsegsize */ 1989 0, /* flags */ 1990 NULL, NULL, /* lockfunc, lockarg */ 1991 &sc_if->sk_cdata.sk_rx_ring_tag); 1992 if (error != 0) { 1993 device_printf(sc_if->sk_if_dev, 1994 "failed to allocate Rx ring DMA tag\n"); 1995 goto fail; 1996 } 1997 1998 /* create tag for Tx buffers */ 1999 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2000 1, 0, /* algnmnt, boundary */ 2001 BUS_SPACE_MAXADDR, /* lowaddr */ 2002 BUS_SPACE_MAXADDR, /* highaddr */ 2003 NULL, NULL, /* filter, filterarg */ 2004 MCLBYTES * SK_MAXTXSEGS, /* maxsize */ 2005 SK_MAXTXSEGS, /* nsegments */ 2006 MCLBYTES, /* maxsegsize */ 2007 0, /* flags */ 2008 NULL, NULL, /* lockfunc, lockarg */ 2009 &sc_if->sk_cdata.sk_tx_tag); 2010 if (error != 0) { 2011 device_printf(sc_if->sk_if_dev, 2012 "failed to allocate Tx DMA tag\n"); 2013 goto fail; 2014 } 2015 2016 /* create tag for Rx buffers */ 2017 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2018 1, 0, /* algnmnt, boundary */ 2019 BUS_SPACE_MAXADDR, /* lowaddr */ 2020 BUS_SPACE_MAXADDR, /* highaddr */ 2021 NULL, NULL, /* filter, filterarg */ 2022 MCLBYTES, /* maxsize */ 2023 1, /* nsegments */ 2024 MCLBYTES, /* maxsegsize */ 2025 0, /* flags */ 2026 NULL, NULL, /* lockfunc, lockarg */ 2027 &sc_if->sk_cdata.sk_rx_tag); 2028 if (error != 0) { 2029 device_printf(sc_if->sk_if_dev, 2030 "failed to allocate Rx DMA tag\n"); 2031 goto fail; 2032 } 2033 2034 /* allocate DMA'able memory and load the DMA map for Tx ring */ 2035 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag, 2036 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | 2037 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map); 2038 if (error != 0) { 2039 device_printf(sc_if->sk_if_dev, 2040 "failed to allocate DMA'able memory for Tx ring\n"); 2041 goto fail; 2042 } 2043 2044 ctx.sk_busaddr = 0; 2045 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag, 2046 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring, 2047 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2048 if (error != 0) { 2049 device_printf(sc_if->sk_if_dev, 2050 "failed to load DMA'able memory for Tx ring\n"); 2051 goto fail; 2052 } 2053 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr; 2054 2055 /* allocate DMA'able memory and load the DMA map for Rx ring */ 2056 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag, 2057 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | 2058 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map); 2059 if (error != 0) { 2060 device_printf(sc_if->sk_if_dev, 2061 "failed to allocate DMA'able memory for Rx ring\n"); 2062 goto fail; 2063 } 2064 2065 ctx.sk_busaddr = 0; 2066 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag, 2067 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring, 2068 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2069 if (error != 0) { 2070 device_printf(sc_if->sk_if_dev, 2071 "failed to load DMA'able memory for Rx ring\n"); 2072 goto fail; 2073 } 2074 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr; 2075 2076 /* create DMA maps for Tx buffers */ 2077 for (i = 0; i < SK_TX_RING_CNT; i++) { 2078 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2079 txd->tx_m = NULL; 2080 txd->tx_dmamap = NULL; 2081 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0, 2082 &txd->tx_dmamap); 2083 if (error != 0) { 2084 device_printf(sc_if->sk_if_dev, 2085 "failed to create Tx dmamap\n"); 2086 goto fail; 2087 } 2088 } 2089 2090 /* create DMA maps for Rx buffers */ 2091 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2092 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) { 2093 device_printf(sc_if->sk_if_dev, 2094 "failed to create spare Rx dmamap\n"); 2095 goto fail; 2096 } 2097 for (i = 0; i < SK_RX_RING_CNT; i++) { 2098 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2099 rxd->rx_m = NULL; 2100 rxd->rx_dmamap = NULL; 2101 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2102 &rxd->rx_dmamap); 2103 if (error != 0) { 2104 device_printf(sc_if->sk_if_dev, 2105 "failed to create Rx dmamap\n"); 2106 goto fail; 2107 } 2108 } 2109 2110fail: 2111 return (error); 2112} 2113 2114static int 2115sk_dma_jumbo_alloc(sc_if) 2116 struct sk_if_softc *sc_if; 2117{ 2118 struct sk_dmamap_arg ctx; 2119 struct sk_rxdesc *jrxd; 2120 int error, i; 2121 2122 if (jumbo_disable != 0) { 2123 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n"); 2124 sc_if->sk_jumbo_disable = 1; 2125 return (0); 2126 } 2127 /* create tag for jumbo Rx ring */ 2128 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2129 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2130 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2131 BUS_SPACE_MAXADDR, /* highaddr */ 2132 NULL, NULL, /* filter, filterarg */ 2133 SK_JUMBO_RX_RING_SZ, /* maxsize */ 2134 1, /* nsegments */ 2135 SK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2136 0, /* flags */ 2137 NULL, NULL, /* lockfunc, lockarg */ 2138 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2139 if (error != 0) { 2140 device_printf(sc_if->sk_if_dev, 2141 "failed to allocate jumbo Rx ring DMA tag\n"); 2142 goto jumbo_fail; 2143 } 2144 2145 /* create tag for jumbo Rx buffers */ 2146 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2147 1, 0, /* algnmnt, boundary */ 2148 BUS_SPACE_MAXADDR, /* lowaddr */ 2149 BUS_SPACE_MAXADDR, /* highaddr */ 2150 NULL, NULL, /* filter, filterarg */ 2151 MJUM9BYTES, /* maxsize */ 2152 1, /* nsegments */ 2153 MJUM9BYTES, /* maxsegsize */ 2154 0, /* flags */ 2155 NULL, NULL, /* lockfunc, lockarg */ 2156 &sc_if->sk_cdata.sk_jumbo_rx_tag); 2157 if (error != 0) { 2158 device_printf(sc_if->sk_if_dev, 2159 "failed to allocate jumbo Rx DMA tag\n"); 2160 goto jumbo_fail; 2161 } 2162 2163 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */ 2164 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2165 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT | 2166 BUS_DMA_COHERENT | BUS_DMA_ZERO, 2167 &sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2168 if (error != 0) { 2169 device_printf(sc_if->sk_if_dev, 2170 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2171 goto jumbo_fail; 2172 } 2173 2174 ctx.sk_busaddr = 0; 2175 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2176 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2177 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb, 2178 &ctx, BUS_DMA_NOWAIT); 2179 if (error != 0) { 2180 device_printf(sc_if->sk_if_dev, 2181 "failed to load DMA'able memory for jumbo Rx ring\n"); 2182 goto jumbo_fail; 2183 } 2184 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr; 2185 2186 /* create DMA maps for jumbo Rx buffers */ 2187 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2188 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) { 2189 device_printf(sc_if->sk_if_dev, 2190 "failed to create spare jumbo Rx dmamap\n"); 2191 goto jumbo_fail; 2192 } 2193 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2194 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2195 jrxd->rx_m = NULL; 2196 jrxd->rx_dmamap = NULL; 2197 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2198 &jrxd->rx_dmamap); 2199 if (error != 0) { 2200 device_printf(sc_if->sk_if_dev, 2201 "failed to create jumbo Rx dmamap\n"); 2202 goto jumbo_fail; 2203 } 2204 } 2205 2206 return (0); 2207 2208jumbo_fail: 2209 sk_dma_jumbo_free(sc_if); 2210 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to " 2211 "resource shortage\n"); 2212 sc_if->sk_jumbo_disable = 1; 2213 return (0); 2214} 2215 2216static void 2217sk_dma_free(sc_if) 2218 struct sk_if_softc *sc_if; 2219{ 2220 struct sk_txdesc *txd; 2221 struct sk_rxdesc *rxd; 2222 int i; 2223 2224 /* Tx ring */ 2225 if (sc_if->sk_cdata.sk_tx_ring_tag) { 2226 if (sc_if->sk_rdata.sk_tx_ring_paddr) 2227 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag, 2228 sc_if->sk_cdata.sk_tx_ring_map); 2229 if (sc_if->sk_rdata.sk_tx_ring) 2230 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag, 2231 sc_if->sk_rdata.sk_tx_ring, 2232 sc_if->sk_cdata.sk_tx_ring_map); 2233 sc_if->sk_rdata.sk_tx_ring = NULL; 2234 sc_if->sk_rdata.sk_tx_ring_paddr = 0; 2235 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag); 2236 sc_if->sk_cdata.sk_tx_ring_tag = NULL; 2237 } 2238 /* Rx ring */ 2239 if (sc_if->sk_cdata.sk_rx_ring_tag) { 2240 if (sc_if->sk_rdata.sk_rx_ring_paddr) 2241 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag, 2242 sc_if->sk_cdata.sk_rx_ring_map); 2243 if (sc_if->sk_rdata.sk_rx_ring) 2244 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag, 2245 sc_if->sk_rdata.sk_rx_ring, 2246 sc_if->sk_cdata.sk_rx_ring_map); 2247 sc_if->sk_rdata.sk_rx_ring = NULL; 2248 sc_if->sk_rdata.sk_rx_ring_paddr = 0; 2249 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag); 2250 sc_if->sk_cdata.sk_rx_ring_tag = NULL; 2251 } 2252 /* Tx buffers */ 2253 if (sc_if->sk_cdata.sk_tx_tag) { 2254 for (i = 0; i < SK_TX_RING_CNT; i++) { 2255 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2256 if (txd->tx_dmamap) { 2257 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag, 2258 txd->tx_dmamap); 2259 txd->tx_dmamap = NULL; 2260 } 2261 } 2262 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag); 2263 sc_if->sk_cdata.sk_tx_tag = NULL; 2264 } 2265 /* Rx buffers */ 2266 if (sc_if->sk_cdata.sk_rx_tag) { 2267 for (i = 0; i < SK_RX_RING_CNT; i++) { 2268 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2269 if (rxd->rx_dmamap) { 2270 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2271 rxd->rx_dmamap); 2272 rxd->rx_dmamap = NULL; 2273 } 2274 } 2275 if (sc_if->sk_cdata.sk_rx_sparemap) { 2276 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2277 sc_if->sk_cdata.sk_rx_sparemap); 2278 sc_if->sk_cdata.sk_rx_sparemap = NULL; 2279 } 2280 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag); 2281 sc_if->sk_cdata.sk_rx_tag = NULL; 2282 } 2283 2284 if (sc_if->sk_cdata.sk_parent_tag) { 2285 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag); 2286 sc_if->sk_cdata.sk_parent_tag = NULL; 2287 } 2288} 2289 2290static void 2291sk_dma_jumbo_free(sc_if) 2292 struct sk_if_softc *sc_if; 2293{ 2294 struct sk_rxdesc *jrxd; 2295 int i; 2296 2297 /* jumbo Rx ring */ 2298 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) { 2299 if (sc_if->sk_rdata.sk_jumbo_rx_ring_paddr) 2300 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2301 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2302 if (sc_if->sk_rdata.sk_jumbo_rx_ring) 2303 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2304 sc_if->sk_rdata.sk_jumbo_rx_ring, 2305 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2306 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL; 2307 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = 0; 2308 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2309 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL; 2310 } 2311 2312 /* jumbo Rx buffers */ 2313 if (sc_if->sk_cdata.sk_jumbo_rx_tag) { 2314 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2315 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2316 if (jrxd->rx_dmamap) { 2317 bus_dmamap_destroy( 2318 sc_if->sk_cdata.sk_jumbo_rx_tag, 2319 jrxd->rx_dmamap); 2320 jrxd->rx_dmamap = NULL; 2321 } 2322 } 2323 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) { 2324 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag, 2325 sc_if->sk_cdata.sk_jumbo_rx_sparemap); 2326 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL; 2327 } 2328 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag); 2329 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL; 2330 } 2331} 2332 2333static void 2334sk_txcksum(ifp, m, f) 2335 struct ifnet *ifp; 2336 struct mbuf *m; 2337 struct sk_tx_desc *f; 2338{ 2339 struct ip *ip; 2340 u_int16_t offset; 2341 u_int8_t *p; 2342 2343 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2344 for(; m && m->m_len == 0; m = m->m_next) 2345 ; 2346 if (m == NULL || m->m_len < ETHER_HDR_LEN) { 2347 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__); 2348 /* checksum may be corrupted */ 2349 goto sendit; 2350 } 2351 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) { 2352 if (m->m_len != ETHER_HDR_LEN) { 2353 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n", 2354 __func__); 2355 /* checksum may be corrupted */ 2356 goto sendit; 2357 } 2358 for(m = m->m_next; m && m->m_len == 0; m = m->m_next) 2359 ; 2360 if (m == NULL) { 2361 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2362 /* checksum may be corrupted */ 2363 goto sendit; 2364 } 2365 ip = mtod(m, struct ip *); 2366 } else { 2367 p = mtod(m, u_int8_t *); 2368 p += ETHER_HDR_LEN; 2369 ip = (struct ip *)p; 2370 } 2371 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN; 2372 2373sendit: 2374 f->sk_csum_startval = 0; 2375 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) | 2376 (offset << 16)); 2377} 2378 2379static int 2380sk_encap(sc_if, m_head) 2381 struct sk_if_softc *sc_if; 2382 struct mbuf **m_head; 2383{ 2384 struct sk_txdesc *txd; 2385 struct sk_tx_desc *f = NULL; 2386 struct mbuf *m; 2387 bus_dma_segment_t txsegs[SK_MAXTXSEGS]; 2388 u_int32_t cflags, frag, si, sk_ctl; 2389 int error, i, nseg; 2390 2391 SK_IF_LOCK_ASSERT(sc_if); 2392 2393 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL) 2394 return (ENOBUFS); 2395 2396 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2397 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2398 if (error == EFBIG) { 2399 m = m_defrag(*m_head, M_NOWAIT); 2400 if (m == NULL) { 2401 m_freem(*m_head); 2402 *m_head = NULL; 2403 return (ENOMEM); 2404 } 2405 *m_head = m; 2406 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2407 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2408 if (error != 0) { 2409 m_freem(*m_head); 2410 *m_head = NULL; 2411 return (error); 2412 } 2413 } else if (error != 0) 2414 return (error); 2415 if (nseg == 0) { 2416 m_freem(*m_head); 2417 *m_head = NULL; 2418 return (EIO); 2419 } 2420 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) { 2421 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2422 return (ENOBUFS); 2423 } 2424 2425 m = *m_head; 2426 if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0) 2427 cflags = SK_OPCODE_CSUM; 2428 else 2429 cflags = SK_OPCODE_DEFAULT; 2430 si = frag = sc_if->sk_cdata.sk_tx_prod; 2431 for (i = 0; i < nseg; i++) { 2432 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2433 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr)); 2434 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr)); 2435 sk_ctl = txsegs[i].ds_len | cflags; 2436 if (i == 0) { 2437 if (cflags == SK_OPCODE_CSUM) 2438 sk_txcksum(sc_if->sk_ifp, m, f); 2439 sk_ctl |= SK_TXCTL_FIRSTFRAG; 2440 } else 2441 sk_ctl |= SK_TXCTL_OWN; 2442 f->sk_ctl = htole32(sk_ctl); 2443 sc_if->sk_cdata.sk_tx_cnt++; 2444 SK_INC(frag, SK_TX_RING_CNT); 2445 } 2446 sc_if->sk_cdata.sk_tx_prod = frag; 2447 2448 /* set EOF on the last desciptor */ 2449 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT; 2450 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2451 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 2452 2453 /* turn the first descriptor ownership to NIC */ 2454 f = &sc_if->sk_rdata.sk_tx_ring[si]; 2455 f->sk_ctl |= htole32(SK_TXCTL_OWN); 2456 2457 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q); 2458 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q); 2459 txd->tx_m = m; 2460 2461 /* sync descriptors */ 2462 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2463 BUS_DMASYNC_PREWRITE); 2464 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2465 sc_if->sk_cdata.sk_tx_ring_map, 2466 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2467 2468 return (0); 2469} 2470 2471static void 2472sk_start(ifp) 2473 struct ifnet *ifp; 2474{ 2475 struct sk_if_softc *sc_if; 2476 2477 sc_if = ifp->if_softc; 2478 2479 SK_IF_LOCK(sc_if); 2480 sk_start_locked(ifp); 2481 SK_IF_UNLOCK(sc_if); 2482 2483 return; 2484} 2485 2486static void 2487sk_start_locked(ifp) 2488 struct ifnet *ifp; 2489{ 2490 struct sk_softc *sc; 2491 struct sk_if_softc *sc_if; 2492 struct mbuf *m_head; 2493 int enq; 2494 2495 sc_if = ifp->if_softc; 2496 sc = sc_if->sk_softc; 2497 2498 SK_IF_LOCK_ASSERT(sc_if); 2499 2500 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2501 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) { 2502 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2503 if (m_head == NULL) 2504 break; 2505 2506 /* 2507 * Pack the data into the transmit ring. If we 2508 * don't have room, set the OACTIVE flag and wait 2509 * for the NIC to drain the ring. 2510 */ 2511 if (sk_encap(sc_if, &m_head)) { 2512 if (m_head == NULL) 2513 break; 2514 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2515 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2516 break; 2517 } 2518 2519 enq++; 2520 /* 2521 * If there's a BPF listener, bounce a copy of this frame 2522 * to him. 2523 */ 2524 BPF_MTAP(ifp, m_head); 2525 } 2526 2527 if (enq > 0) { 2528 /* Transmit */ 2529 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2530 2531 /* Set a timeout in case the chip goes out to lunch. */ 2532 sc_if->sk_watchdog_timer = 5; 2533 } 2534} 2535 2536static void 2537sk_watchdog(arg) 2538 void *arg; 2539{ 2540 struct sk_if_softc *sc_if; 2541 struct ifnet *ifp; 2542 2543 ifp = arg; 2544 sc_if = ifp->if_softc; 2545 2546 SK_IF_LOCK_ASSERT(sc_if); 2547 2548 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer) 2549 goto done; 2550 2551 /* 2552 * Reclaim first as there is a possibility of losing Tx completion 2553 * interrupts. 2554 */ 2555 sk_txeof(sc_if); 2556 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2557 if_printf(sc_if->sk_ifp, "watchdog timeout\n"); 2558 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2559 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2560 sk_init_locked(sc_if); 2561 } 2562 2563done: 2564 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 2565 2566 return; 2567} 2568 2569static int 2570skc_shutdown(dev) 2571 device_t dev; 2572{ 2573 struct sk_softc *sc; 2574 2575 sc = device_get_softc(dev); 2576 SK_LOCK(sc); 2577 2578 /* Turn off the 'driver is loaded' LED. */ 2579 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2580 2581 /* 2582 * Reset the GEnesis controller. Doing this should also 2583 * assert the resets on the attached XMAC(s). 2584 */ 2585 sk_reset(sc); 2586 SK_UNLOCK(sc); 2587 2588 return (0); 2589} 2590 2591static int 2592skc_suspend(dev) 2593 device_t dev; 2594{ 2595 struct sk_softc *sc; 2596 struct sk_if_softc *sc_if0, *sc_if1; 2597 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2598 2599 sc = device_get_softc(dev); 2600 2601 SK_LOCK(sc); 2602 2603 sc_if0 = sc->sk_if[SK_PORT_A]; 2604 sc_if1 = sc->sk_if[SK_PORT_B]; 2605 if (sc_if0 != NULL) 2606 ifp0 = sc_if0->sk_ifp; 2607 if (sc_if1 != NULL) 2608 ifp1 = sc_if1->sk_ifp; 2609 if (ifp0 != NULL) 2610 sk_stop(sc_if0); 2611 if (ifp1 != NULL) 2612 sk_stop(sc_if1); 2613 sc->sk_suspended = 1; 2614 2615 SK_UNLOCK(sc); 2616 2617 return (0); 2618} 2619 2620static int 2621skc_resume(dev) 2622 device_t dev; 2623{ 2624 struct sk_softc *sc; 2625 struct sk_if_softc *sc_if0, *sc_if1; 2626 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2627 2628 sc = device_get_softc(dev); 2629 2630 SK_LOCK(sc); 2631 2632 sc_if0 = sc->sk_if[SK_PORT_A]; 2633 sc_if1 = sc->sk_if[SK_PORT_B]; 2634 if (sc_if0 != NULL) 2635 ifp0 = sc_if0->sk_ifp; 2636 if (sc_if1 != NULL) 2637 ifp1 = sc_if1->sk_ifp; 2638 if (ifp0 != NULL && ifp0->if_flags & IFF_UP) 2639 sk_init_locked(sc_if0); 2640 if (ifp1 != NULL && ifp1->if_flags & IFF_UP) 2641 sk_init_locked(sc_if1); 2642 sc->sk_suspended = 0; 2643 2644 SK_UNLOCK(sc); 2645 2646 return (0); 2647} 2648 2649/* 2650 * According to the data sheet from SK-NET GENESIS the hardware can compute 2651 * two Rx checksums at the same time(Each checksum start position is 2652 * programmed in Rx descriptors). However it seems that TCP/UDP checksum 2653 * does not work at least on my Yukon hardware. I tried every possible ways 2654 * to get correct checksum value but couldn't get correct one. So TCP/UDP 2655 * checksum offload was disabled at the moment and only IP checksum offload 2656 * was enabled. 2657 * As nomral IP header size is 20 bytes I can't expect it would give an 2658 * increase in throughput. However it seems it doesn't hurt performance in 2659 * my testing. If there is a more detailed information for checksum secret 2660 * of the hardware in question please contact yongari@FreeBSD.org to add 2661 * TCP/UDP checksum offload support. 2662 */ 2663static __inline void 2664sk_rxcksum(ifp, m, csum) 2665 struct ifnet *ifp; 2666 struct mbuf *m; 2667 u_int32_t csum; 2668{ 2669 struct ether_header *eh; 2670 struct ip *ip; 2671 int32_t hlen, len, pktlen; 2672 u_int16_t csum1, csum2, ipcsum; 2673 2674 pktlen = m->m_pkthdr.len; 2675 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 2676 return; 2677 eh = mtod(m, struct ether_header *); 2678 if (eh->ether_type != htons(ETHERTYPE_IP)) 2679 return; 2680 ip = (struct ip *)(eh + 1); 2681 if (ip->ip_v != IPVERSION) 2682 return; 2683 hlen = ip->ip_hl << 2; 2684 pktlen -= sizeof(struct ether_header); 2685 if (hlen < sizeof(struct ip)) 2686 return; 2687 if (ntohs(ip->ip_len) < hlen) 2688 return; 2689 if (ntohs(ip->ip_len) != pktlen) 2690 return; 2691 2692 csum1 = htons(csum & 0xffff); 2693 csum2 = htons((csum >> 16) & 0xffff); 2694 ipcsum = in_addword(csum1, ~csum2 & 0xffff); 2695 /* checksum fixup for IP options */ 2696 len = hlen - sizeof(struct ip); 2697 if (len > 0) { 2698 /* 2699 * If the second checksum value is correct we can compute IP 2700 * checksum with simple math. Unfortunately the second checksum 2701 * value is wrong so we can't verify the checksum from the 2702 * value(It seems there is some magic here to get correct 2703 * value). If the second checksum value is correct it also 2704 * means we can get TCP/UDP checksum) here. However, it still 2705 * needs pseudo header checksum calculation due to hardware 2706 * limitations. 2707 */ 2708 return; 2709 } 2710 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 2711 if (ipcsum == 0xffff) 2712 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2713} 2714 2715static __inline int 2716sk_rxvalid(sc, stat, len) 2717 struct sk_softc *sc; 2718 u_int32_t stat, len; 2719{ 2720 2721 if (sc->sk_type == SK_GENESIS) { 2722 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 2723 XM_RXSTAT_BYTES(stat) != len) 2724 return (0); 2725 } else { 2726 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2727 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2728 YU_RXSTAT_JABBER)) != 0 || 2729 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2730 YU_RXSTAT_BYTES(stat) != len) 2731 return (0); 2732 } 2733 2734 return (1); 2735} 2736 2737static void 2738sk_rxeof(sc_if) 2739 struct sk_if_softc *sc_if; 2740{ 2741 struct sk_softc *sc; 2742 struct mbuf *m; 2743 struct ifnet *ifp; 2744 struct sk_rx_desc *cur_rx; 2745 struct sk_rxdesc *rxd; 2746 int cons, prog; 2747 u_int32_t csum, rxstat, sk_ctl; 2748 2749 sc = sc_if->sk_softc; 2750 ifp = sc_if->sk_ifp; 2751 2752 SK_IF_LOCK_ASSERT(sc_if); 2753 2754 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2755 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD); 2756 2757 prog = 0; 2758 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT; 2759 prog++, SK_INC(cons, SK_RX_RING_CNT)) { 2760 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons]; 2761 sk_ctl = le32toh(cur_rx->sk_ctl); 2762 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2763 break; 2764 rxd = &sc_if->sk_cdata.sk_rxdesc[cons]; 2765 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2766 2767 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2768 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2769 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2770 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2771 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN || 2772 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2773 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2774 sk_discard_rxbuf(sc_if, cons); 2775 continue; 2776 } 2777 2778 m = rxd->rx_m; 2779 csum = le32toh(cur_rx->sk_csum); 2780 if (sk_newbuf(sc_if, cons) != 0) { 2781 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2782 /* reuse old buffer */ 2783 sk_discard_rxbuf(sc_if, cons); 2784 continue; 2785 } 2786 m->m_pkthdr.rcvif = ifp; 2787 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2788 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2789 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2790 sk_rxcksum(ifp, m, csum); 2791 SK_IF_UNLOCK(sc_if); 2792 (*ifp->if_input)(ifp, m); 2793 SK_IF_LOCK(sc_if); 2794 } 2795 2796 if (prog > 0) { 2797 sc_if->sk_cdata.sk_rx_cons = cons; 2798 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2799 sc_if->sk_cdata.sk_rx_ring_map, 2800 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2801 } 2802} 2803 2804static void 2805sk_jumbo_rxeof(sc_if) 2806 struct sk_if_softc *sc_if; 2807{ 2808 struct sk_softc *sc; 2809 struct mbuf *m; 2810 struct ifnet *ifp; 2811 struct sk_rx_desc *cur_rx; 2812 struct sk_rxdesc *jrxd; 2813 int cons, prog; 2814 u_int32_t csum, rxstat, sk_ctl; 2815 2816 sc = sc_if->sk_softc; 2817 ifp = sc_if->sk_ifp; 2818 2819 SK_IF_LOCK_ASSERT(sc_if); 2820 2821 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2822 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD); 2823 2824 prog = 0; 2825 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons; 2826 prog < SK_JUMBO_RX_RING_CNT; 2827 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) { 2828 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons]; 2829 sk_ctl = le32toh(cur_rx->sk_ctl); 2830 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2831 break; 2832 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons]; 2833 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2834 2835 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2836 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2837 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2838 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2839 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN || 2840 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2841 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2842 sk_discard_jumbo_rxbuf(sc_if, cons); 2843 continue; 2844 } 2845 2846 m = jrxd->rx_m; 2847 csum = le32toh(cur_rx->sk_csum); 2848 if (sk_jumbo_newbuf(sc_if, cons) != 0) { 2849 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2850 /* reuse old buffer */ 2851 sk_discard_jumbo_rxbuf(sc_if, cons); 2852 continue; 2853 } 2854 m->m_pkthdr.rcvif = ifp; 2855 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2856 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2857 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2858 sk_rxcksum(ifp, m, csum); 2859 SK_IF_UNLOCK(sc_if); 2860 (*ifp->if_input)(ifp, m); 2861 SK_IF_LOCK(sc_if); 2862 } 2863 2864 if (prog > 0) { 2865 sc_if->sk_cdata.sk_jumbo_rx_cons = cons; 2866 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2867 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2868 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2869 } 2870} 2871 2872static void 2873sk_txeof(sc_if) 2874 struct sk_if_softc *sc_if; 2875{ 2876 struct sk_txdesc *txd; 2877 struct sk_tx_desc *cur_tx; 2878 struct ifnet *ifp; 2879 u_int32_t idx, sk_ctl; 2880 2881 ifp = sc_if->sk_ifp; 2882 2883 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 2884 if (txd == NULL) 2885 return; 2886 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2887 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD); 2888 /* 2889 * Go through our tx ring and free mbufs for those 2890 * frames that have been sent. 2891 */ 2892 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) { 2893 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 2894 break; 2895 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx]; 2896 sk_ctl = le32toh(cur_tx->sk_ctl); 2897 if (sk_ctl & SK_TXCTL_OWN) 2898 break; 2899 sc_if->sk_cdata.sk_tx_cnt--; 2900 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2901 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0) 2902 continue; 2903 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2904 BUS_DMASYNC_POSTWRITE); 2905 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2906 2907 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2908 m_freem(txd->tx_m); 2909 txd->tx_m = NULL; 2910 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q); 2911 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 2912 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 2913 } 2914 sc_if->sk_cdata.sk_tx_cons = idx; 2915 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2916 2917 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2918 sc_if->sk_cdata.sk_tx_ring_map, 2919 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2920} 2921 2922static void 2923sk_tick(xsc_if) 2924 void *xsc_if; 2925{ 2926 struct sk_if_softc *sc_if; 2927 struct mii_data *mii; 2928 struct ifnet *ifp; 2929 int i; 2930 2931 sc_if = xsc_if; 2932 ifp = sc_if->sk_ifp; 2933 mii = device_get_softc(sc_if->sk_miibus); 2934 2935 if (!(ifp->if_flags & IFF_UP)) 2936 return; 2937 2938 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2939 sk_intr_bcom(sc_if); 2940 return; 2941 } 2942 2943 /* 2944 * According to SysKonnect, the correct way to verify that 2945 * the link has come back up is to poll bit 0 of the GPIO 2946 * register three times. This pin has the signal from the 2947 * link_sync pin connected to it; if we read the same link 2948 * state 3 times in a row, we know the link is up. 2949 */ 2950 for (i = 0; i < 3; i++) { 2951 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2952 break; 2953 } 2954 2955 if (i != 3) { 2956 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2957 return; 2958 } 2959 2960 /* Turn the GP0 interrupt back on. */ 2961 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2962 SK_XM_READ_2(sc_if, XM_ISR); 2963 mii_tick(mii); 2964 callout_stop(&sc_if->sk_tick_ch); 2965} 2966 2967static void 2968sk_yukon_tick(xsc_if) 2969 void *xsc_if; 2970{ 2971 struct sk_if_softc *sc_if; 2972 struct mii_data *mii; 2973 2974 sc_if = xsc_if; 2975 mii = device_get_softc(sc_if->sk_miibus); 2976 2977 mii_tick(mii); 2978 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 2979} 2980 2981static void 2982sk_intr_bcom(sc_if) 2983 struct sk_if_softc *sc_if; 2984{ 2985 struct mii_data *mii; 2986 struct ifnet *ifp; 2987 int status; 2988 mii = device_get_softc(sc_if->sk_miibus); 2989 ifp = sc_if->sk_ifp; 2990 2991 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2992 2993 /* 2994 * Read the PHY interrupt register to make sure 2995 * we clear any pending interrupts. 2996 */ 2997 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2998 2999 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3000 sk_init_xmac(sc_if); 3001 return; 3002 } 3003 3004 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 3005 int lstat; 3006 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 3007 BRGPHY_MII_AUXSTS); 3008 3009 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 3010 mii_mediachg(mii); 3011 /* Turn off the link LED. */ 3012 SK_IF_WRITE_1(sc_if, 0, 3013 SK_LINKLED1_CTL, SK_LINKLED_OFF); 3014 sc_if->sk_link = 0; 3015 } else if (status & BRGPHY_ISR_LNK_CHG) { 3016 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3017 BRGPHY_MII_IMR, 0xFF00); 3018 mii_tick(mii); 3019 sc_if->sk_link = 1; 3020 /* Turn on the link LED. */ 3021 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3022 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 3023 SK_LINKLED_BLINK_OFF); 3024 } else { 3025 mii_tick(mii); 3026 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3027 } 3028 } 3029 3030 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3031 3032 return; 3033} 3034 3035static void 3036sk_intr_xmac(sc_if) 3037 struct sk_if_softc *sc_if; 3038{ 3039 struct sk_softc *sc; 3040 u_int16_t status; 3041 3042 sc = sc_if->sk_softc; 3043 status = SK_XM_READ_2(sc_if, XM_ISR); 3044 3045 /* 3046 * Link has gone down. Start MII tick timeout to 3047 * watch for link resync. 3048 */ 3049 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 3050 if (status & XM_ISR_GP0_SET) { 3051 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3052 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3053 } 3054 3055 if (status & XM_ISR_AUTONEG_DONE) { 3056 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3057 } 3058 } 3059 3060 if (status & XM_IMR_TX_UNDERRUN) 3061 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 3062 3063 if (status & XM_IMR_RX_OVERRUN) 3064 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 3065 3066 status = SK_XM_READ_2(sc_if, XM_ISR); 3067 3068 return; 3069} 3070 3071static void 3072sk_intr_yukon(sc_if) 3073 struct sk_if_softc *sc_if; 3074{ 3075 u_int8_t status; 3076 3077 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 3078 /* RX overrun */ 3079 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 3080 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3081 SK_RFCTL_RX_FIFO_OVER); 3082 } 3083 /* TX underrun */ 3084 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 3085 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3086 SK_TFCTL_TX_FIFO_UNDER); 3087 } 3088} 3089 3090static void 3091sk_intr(xsc) 3092 void *xsc; 3093{ 3094 struct sk_softc *sc = xsc; 3095 struct sk_if_softc *sc_if0, *sc_if1; 3096 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 3097 u_int32_t status; 3098 3099 SK_LOCK(sc); 3100 3101 status = CSR_READ_4(sc, SK_ISSR); 3102 if (status == 0 || status == 0xffffffff || sc->sk_suspended) 3103 goto done_locked; 3104 3105 sc_if0 = sc->sk_if[SK_PORT_A]; 3106 sc_if1 = sc->sk_if[SK_PORT_B]; 3107 3108 if (sc_if0 != NULL) 3109 ifp0 = sc_if0->sk_ifp; 3110 if (sc_if1 != NULL) 3111 ifp1 = sc_if1->sk_ifp; 3112 3113 for (; (status &= sc->sk_intrmask) != 0;) { 3114 /* Handle receive interrupts first. */ 3115 if (status & SK_ISR_RX1_EOF) { 3116 if (ifp0->if_mtu > SK_MAX_FRAMELEN) 3117 sk_jumbo_rxeof(sc_if0); 3118 else 3119 sk_rxeof(sc_if0); 3120 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 3121 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3122 } 3123 if (status & SK_ISR_RX2_EOF) { 3124 if (ifp1->if_mtu > SK_MAX_FRAMELEN) 3125 sk_jumbo_rxeof(sc_if1); 3126 else 3127 sk_rxeof(sc_if1); 3128 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 3129 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3130 } 3131 3132 /* Then transmit interrupts. */ 3133 if (status & SK_ISR_TX1_S_EOF) { 3134 sk_txeof(sc_if0); 3135 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF); 3136 } 3137 if (status & SK_ISR_TX2_S_EOF) { 3138 sk_txeof(sc_if1); 3139 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF); 3140 } 3141 3142 /* Then MAC interrupts. */ 3143 if (status & SK_ISR_MAC1 && 3144 ifp0->if_drv_flags & IFF_DRV_RUNNING) { 3145 if (sc->sk_type == SK_GENESIS) 3146 sk_intr_xmac(sc_if0); 3147 else 3148 sk_intr_yukon(sc_if0); 3149 } 3150 3151 if (status & SK_ISR_MAC2 && 3152 ifp1->if_drv_flags & IFF_DRV_RUNNING) { 3153 if (sc->sk_type == SK_GENESIS) 3154 sk_intr_xmac(sc_if1); 3155 else 3156 sk_intr_yukon(sc_if1); 3157 } 3158 3159 if (status & SK_ISR_EXTERNAL_REG) { 3160 if (ifp0 != NULL && 3161 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 3162 sk_intr_bcom(sc_if0); 3163 if (ifp1 != NULL && 3164 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 3165 sk_intr_bcom(sc_if1); 3166 } 3167 status = CSR_READ_4(sc, SK_ISSR); 3168 } 3169 3170 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3171 3172 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3173 sk_start_locked(ifp0); 3174 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3175 sk_start_locked(ifp1); 3176 3177done_locked: 3178 SK_UNLOCK(sc); 3179} 3180 3181static void 3182sk_init_xmac(sc_if) 3183 struct sk_if_softc *sc_if; 3184{ 3185 struct sk_softc *sc; 3186 struct ifnet *ifp; 3187 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 3188 static const struct sk_bcom_hack bhack[] = { 3189 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 3190 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 3191 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 3192 { 0, 0 } }; 3193 3194 SK_IF_LOCK_ASSERT(sc_if); 3195 3196 sc = sc_if->sk_softc; 3197 ifp = sc_if->sk_ifp; 3198 3199 /* Unreset the XMAC. */ 3200 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 3201 DELAY(1000); 3202 3203 /* Reset the XMAC's internal state. */ 3204 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3205 3206 /* Save the XMAC II revision */ 3207 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 3208 3209 /* 3210 * Perform additional initialization for external PHYs, 3211 * namely for the 1000baseTX cards that use the XMAC's 3212 * GMII mode. 3213 */ 3214 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3215 int i = 0; 3216 u_int32_t val; 3217 3218 /* Take PHY out of reset. */ 3219 val = sk_win_read_4(sc, SK_GPIO); 3220 if (sc_if->sk_port == SK_PORT_A) 3221 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 3222 else 3223 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 3224 sk_win_write_4(sc, SK_GPIO, val); 3225 3226 /* Enable GMII mode on the XMAC. */ 3227 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 3228 3229 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3230 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 3231 DELAY(10000); 3232 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3233 BRGPHY_MII_IMR, 0xFFF0); 3234 3235 /* 3236 * Early versions of the BCM5400 apparently have 3237 * a bug that requires them to have their reserved 3238 * registers initialized to some magic values. I don't 3239 * know what the numbers do, I'm just the messenger. 3240 */ 3241 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 3242 == 0x6041) { 3243 while(bhack[i].reg) { 3244 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3245 bhack[i].reg, bhack[i].val); 3246 i++; 3247 } 3248 } 3249 } 3250 3251 /* Set station address */ 3252 bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN); 3253 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]); 3254 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]); 3255 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]); 3256 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 3257 3258 if (ifp->if_flags & IFF_BROADCAST) { 3259 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3260 } else { 3261 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3262 } 3263 3264 /* We don't need the FCS appended to the packet. */ 3265 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 3266 3267 /* We want short frames padded to 60 bytes. */ 3268 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 3269 3270 /* 3271 * Enable the reception of all error frames. This is is 3272 * a necessary evil due to the design of the XMAC. The 3273 * XMAC's receive FIFO is only 8K in size, however jumbo 3274 * frames can be up to 9000 bytes in length. When bad 3275 * frame filtering is enabled, the XMAC's RX FIFO operates 3276 * in 'store and forward' mode. For this to work, the 3277 * entire frame has to fit into the FIFO, but that means 3278 * that jumbo frames larger than 8192 bytes will be 3279 * truncated. Disabling all bad frame filtering causes 3280 * the RX FIFO to operate in streaming mode, in which 3281 * case the XMAC will start transferring frames out of the 3282 * RX FIFO as soon as the FIFO threshold is reached. 3283 */ 3284 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3285 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 3286 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 3287 XM_MODE_RX_INRANGELEN); 3288 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3289 } else 3290 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3291 3292 /* 3293 * Bump up the transmit threshold. This helps hold off transmit 3294 * underruns when we're blasting traffic from both ports at once. 3295 */ 3296 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 3297 3298 /* Set Rx filter */ 3299 sk_rxfilter_genesis(sc_if); 3300 3301 /* Clear and enable interrupts */ 3302 SK_XM_READ_2(sc_if, XM_ISR); 3303 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 3304 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 3305 else 3306 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3307 3308 /* Configure MAC arbiter */ 3309 switch(sc_if->sk_xmac_rev) { 3310 case XM_XMAC_REV_B2: 3311 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 3312 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 3313 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 3314 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 3315 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 3316 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 3317 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 3318 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 3319 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3320 break; 3321 case XM_XMAC_REV_C1: 3322 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 3323 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 3324 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 3325 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 3326 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 3327 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 3328 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 3329 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 3330 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3331 break; 3332 default: 3333 break; 3334 } 3335 sk_win_write_2(sc, SK_MACARB_CTL, 3336 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 3337 3338 sc_if->sk_link = 1; 3339 3340 return; 3341} 3342 3343static void 3344sk_init_yukon(sc_if) 3345 struct sk_if_softc *sc_if; 3346{ 3347 u_int32_t phy, v; 3348 u_int16_t reg; 3349 struct sk_softc *sc; 3350 struct ifnet *ifp; 3351 u_int8_t *eaddr; 3352 int i; 3353 3354 SK_IF_LOCK_ASSERT(sc_if); 3355 3356 sc = sc_if->sk_softc; 3357 ifp = sc_if->sk_ifp; 3358 3359 if (sc->sk_type == SK_YUKON_LITE && 3360 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3361 /* 3362 * Workaround code for COMA mode, set PHY reset. 3363 * Otherwise it will not correctly take chip out of 3364 * powerdown (coma) 3365 */ 3366 v = sk_win_read_4(sc, SK_GPIO); 3367 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 3368 sk_win_write_4(sc, SK_GPIO, v); 3369 } 3370 3371 /* GMAC and GPHY Reset */ 3372 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 3373 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 3374 DELAY(1000); 3375 3376 if (sc->sk_type == SK_YUKON_LITE && 3377 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3378 /* 3379 * Workaround code for COMA mode, clear PHY reset 3380 */ 3381 v = sk_win_read_4(sc, SK_GPIO); 3382 v |= SK_GPIO_DIR9; 3383 v &= ~SK_GPIO_DAT9; 3384 sk_win_write_4(sc, SK_GPIO, v); 3385 } 3386 3387 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 3388 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 3389 3390 if (sc->sk_coppertype) 3391 phy |= SK_GPHY_COPPER; 3392 else 3393 phy |= SK_GPHY_FIBER; 3394 3395 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 3396 DELAY(1000); 3397 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 3398 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 3399 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 3400 3401 /* unused read of the interrupt source register */ 3402 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 3403 3404 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 3405 3406 /* MIB Counter Clear Mode set */ 3407 reg |= YU_PAR_MIB_CLR; 3408 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3409 3410 /* MIB Counter Clear Mode clear */ 3411 reg &= ~YU_PAR_MIB_CLR; 3412 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3413 3414 /* receive control reg */ 3415 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 3416 3417 /* transmit parameter register */ 3418 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 3419 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 3420 3421 /* serial mode register */ 3422 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 3423 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3424 reg |= YU_SMR_MFL_JUMBO; 3425 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 3426 3427 /* Setup Yukon's station address */ 3428 eaddr = IF_LLADDR(sc_if->sk_ifp); 3429 for (i = 0; i < 3; i++) 3430 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4, 3431 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3432 /* Set GMAC source address of flow control. */ 3433 for (i = 0; i < 3; i++) 3434 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 3435 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3436 /* Set GMAC virtual address. */ 3437 for (i = 0; i < 3; i++) 3438 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, 3439 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3440 3441 /* Set Rx filter */ 3442 sk_rxfilter_yukon(sc_if); 3443 3444 /* enable interrupt mask for counter overflows */ 3445 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 3446 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 3447 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 3448 3449 /* Configure RX MAC FIFO Flush Mask */ 3450 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 3451 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 3452 YU_RXSTAT_JABBER; 3453 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 3454 3455 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 3456 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 3457 v = SK_TFCTL_OPERATION_ON; 3458 else 3459 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 3460 /* Configure RX MAC FIFO */ 3461 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 3462 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 3463 3464 /* Increase flush threshould to 64 bytes */ 3465 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 3466 SK_RFCTL_FIFO_THRESHOLD + 1); 3467 3468 /* Configure TX MAC FIFO */ 3469 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 3470 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 3471} 3472 3473/* 3474 * Note that to properly initialize any part of the GEnesis chip, 3475 * you first have to take it out of reset mode. 3476 */ 3477static void 3478sk_init(xsc) 3479 void *xsc; 3480{ 3481 struct sk_if_softc *sc_if = xsc; 3482 3483 SK_IF_LOCK(sc_if); 3484 sk_init_locked(sc_if); 3485 SK_IF_UNLOCK(sc_if); 3486 3487 return; 3488} 3489 3490static void 3491sk_init_locked(sc_if) 3492 struct sk_if_softc *sc_if; 3493{ 3494 struct sk_softc *sc; 3495 struct ifnet *ifp; 3496 struct mii_data *mii; 3497 u_int16_t reg; 3498 u_int32_t imr; 3499 int error; 3500 3501 SK_IF_LOCK_ASSERT(sc_if); 3502 3503 ifp = sc_if->sk_ifp; 3504 sc = sc_if->sk_softc; 3505 mii = device_get_softc(sc_if->sk_miibus); 3506 3507 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3508 return; 3509 3510 /* Cancel pending I/O and free all RX/TX buffers. */ 3511 sk_stop(sc_if); 3512 3513 if (sc->sk_type == SK_GENESIS) { 3514 /* Configure LINK_SYNC LED */ 3515 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 3516 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3517 SK_LINKLED_LINKSYNC_ON); 3518 3519 /* Configure RX LED */ 3520 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 3521 SK_RXLEDCTL_COUNTER_START); 3522 3523 /* Configure TX LED */ 3524 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 3525 SK_TXLEDCTL_COUNTER_START); 3526 } 3527 3528 /* 3529 * Configure descriptor poll timer 3530 * 3531 * SK-NET GENESIS data sheet says that possibility of losing Start 3532 * transmit command due to CPU/cache related interim storage problems 3533 * under certain conditions. The document recommends a polling 3534 * mechanism to send a Start transmit command to initiate transfer 3535 * of ready descriptors regulary. To cope with this issue sk(4) now 3536 * enables descriptor poll timer to initiate descriptor processing 3537 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 3538 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 3539 * command instead of waiting for next descriptor polling time. 3540 * The same rule may apply to Rx side too but it seems that is not 3541 * needed at the moment. 3542 * Since sk(4) uses descriptor polling as a last resort there is no 3543 * need to set smaller polling time than maximum allowable one. 3544 */ 3545 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 3546 3547 /* Configure I2C registers */ 3548 3549 /* Configure XMAC(s) */ 3550 switch (sc->sk_type) { 3551 case SK_GENESIS: 3552 sk_init_xmac(sc_if); 3553 break; 3554 case SK_YUKON: 3555 case SK_YUKON_LITE: 3556 case SK_YUKON_LP: 3557 sk_init_yukon(sc_if); 3558 break; 3559 } 3560 mii_mediachg(mii); 3561 3562 if (sc->sk_type == SK_GENESIS) { 3563 /* Configure MAC FIFOs */ 3564 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 3565 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 3566 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 3567 3568 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 3569 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 3570 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 3571 } 3572 3573 /* Configure transmit arbiter(s) */ 3574 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 3575 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 3576 3577 /* Configure RAMbuffers */ 3578 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 3579 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 3580 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 3581 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 3582 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 3583 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 3584 3585 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 3586 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 3587 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 3588 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 3589 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 3590 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 3591 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 3592 3593 /* Configure BMUs */ 3594 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 3595 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3596 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3597 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3598 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3599 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3600 } else { 3601 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3602 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0))); 3603 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3604 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0))); 3605 } 3606 3607 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 3608 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 3609 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0))); 3610 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 3611 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0))); 3612 3613 /* Init descriptors */ 3614 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3615 error = sk_init_jumbo_rx_ring(sc_if); 3616 else 3617 error = sk_init_rx_ring(sc_if); 3618 if (error != 0) { 3619 device_printf(sc_if->sk_if_dev, 3620 "initialization failed: no memory for rx buffers\n"); 3621 sk_stop(sc_if); 3622 return; 3623 } 3624 sk_init_tx_ring(sc_if); 3625 3626 /* Set interrupt moderation if changed via sysctl. */ 3627 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 3628 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) { 3629 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 3630 sc->sk_int_ticks)); 3631 if (bootverbose) 3632 device_printf(sc_if->sk_if_dev, 3633 "interrupt moderation is %d us.\n", 3634 sc->sk_int_mod); 3635 } 3636 3637 /* Configure interrupt handling */ 3638 CSR_READ_4(sc, SK_ISSR); 3639 if (sc_if->sk_port == SK_PORT_A) 3640 sc->sk_intrmask |= SK_INTRS1; 3641 else 3642 sc->sk_intrmask |= SK_INTRS2; 3643 3644 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 3645 3646 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3647 3648 /* Start BMUs. */ 3649 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 3650 3651 switch(sc->sk_type) { 3652 case SK_GENESIS: 3653 /* Enable XMACs TX and RX state machines */ 3654 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 3655 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3656 break; 3657 case SK_YUKON: 3658 case SK_YUKON_LITE: 3659 case SK_YUKON_LP: 3660 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 3661 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 3662#if 0 3663 /* XXX disable 100Mbps and full duplex mode? */ 3664 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 3665#endif 3666 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 3667 } 3668 3669 /* Activate descriptor polling timer */ 3670 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 3671 /* start transfer of Tx descriptors */ 3672 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 3673 3674 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3675 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3676 3677 switch (sc->sk_type) { 3678 case SK_YUKON: 3679 case SK_YUKON_LITE: 3680 case SK_YUKON_LP: 3681 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3682 break; 3683 } 3684 3685 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 3686 3687 return; 3688} 3689 3690static void 3691sk_stop(sc_if) 3692 struct sk_if_softc *sc_if; 3693{ 3694 int i; 3695 struct sk_softc *sc; 3696 struct sk_txdesc *txd; 3697 struct sk_rxdesc *rxd; 3698 struct sk_rxdesc *jrxd; 3699 struct ifnet *ifp; 3700 u_int32_t val; 3701 3702 SK_IF_LOCK_ASSERT(sc_if); 3703 sc = sc_if->sk_softc; 3704 ifp = sc_if->sk_ifp; 3705 3706 callout_stop(&sc_if->sk_tick_ch); 3707 callout_stop(&sc_if->sk_watchdog_ch); 3708 3709 /* stop Tx descriptor polling timer */ 3710 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 3711 /* stop transfer of Tx descriptors */ 3712 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 3713 for (i = 0; i < SK_TIMEOUT; i++) { 3714 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 3715 if ((val & SK_TXBMU_TX_STOP) == 0) 3716 break; 3717 DELAY(1); 3718 } 3719 if (i == SK_TIMEOUT) 3720 device_printf(sc_if->sk_if_dev, 3721 "can not stop transfer of Tx descriptor\n"); 3722 /* stop transfer of Rx descriptors */ 3723 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 3724 for (i = 0; i < SK_TIMEOUT; i++) { 3725 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 3726 if ((val & SK_RXBMU_RX_STOP) == 0) 3727 break; 3728 DELAY(1); 3729 } 3730 if (i == SK_TIMEOUT) 3731 device_printf(sc_if->sk_if_dev, 3732 "can not stop transfer of Rx descriptor\n"); 3733 3734 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3735 /* Put PHY back into reset. */ 3736 val = sk_win_read_4(sc, SK_GPIO); 3737 if (sc_if->sk_port == SK_PORT_A) { 3738 val |= SK_GPIO_DIR0; 3739 val &= ~SK_GPIO_DAT0; 3740 } else { 3741 val |= SK_GPIO_DIR2; 3742 val &= ~SK_GPIO_DAT2; 3743 } 3744 sk_win_write_4(sc, SK_GPIO, val); 3745 } 3746 3747 /* Turn off various components of this interface. */ 3748 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3749 switch (sc->sk_type) { 3750 case SK_GENESIS: 3751 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 3752 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 3753 break; 3754 case SK_YUKON: 3755 case SK_YUKON_LITE: 3756 case SK_YUKON_LP: 3757 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 3758 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 3759 break; 3760 } 3761 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 3762 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3763 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 3764 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3765 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 3766 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3767 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3768 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 3769 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 3770 3771 /* Disable interrupts */ 3772 if (sc_if->sk_port == SK_PORT_A) 3773 sc->sk_intrmask &= ~SK_INTRS1; 3774 else 3775 sc->sk_intrmask &= ~SK_INTRS2; 3776 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3777 3778 SK_XM_READ_2(sc_if, XM_ISR); 3779 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3780 3781 /* Free RX and TX mbufs still in the queues. */ 3782 for (i = 0; i < SK_RX_RING_CNT; i++) { 3783 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 3784 if (rxd->rx_m != NULL) { 3785 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, 3786 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3787 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, 3788 rxd->rx_dmamap); 3789 m_freem(rxd->rx_m); 3790 rxd->rx_m = NULL; 3791 } 3792 } 3793 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 3794 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 3795 if (jrxd->rx_m != NULL) { 3796 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, 3797 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3798 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 3799 jrxd->rx_dmamap); 3800 m_freem(jrxd->rx_m); 3801 jrxd->rx_m = NULL; 3802 } 3803 } 3804 for (i = 0; i < SK_TX_RING_CNT; i++) { 3805 txd = &sc_if->sk_cdata.sk_txdesc[i]; 3806 if (txd->tx_m != NULL) { 3807 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, 3808 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3809 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, 3810 txd->tx_dmamap); 3811 m_freem(txd->tx_m); 3812 txd->tx_m = NULL; 3813 } 3814 } 3815 3816 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 3817 3818 return; 3819} 3820 3821static int 3822sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3823{ 3824 int error, value; 3825 3826 if (!arg1) 3827 return (EINVAL); 3828 value = *(int *)arg1; 3829 error = sysctl_handle_int(oidp, &value, 0, req); 3830 if (error || !req->newptr) 3831 return (error); 3832 if (value < low || value > high) 3833 return (EINVAL); 3834 *(int *)arg1 = value; 3835 return (0); 3836} 3837 3838static int 3839sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS) 3840{ 3841 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX)); 3842} 3843