1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31/**************************************************************************** 32 * 33 * Name: mcp_public.h 34 * 35 * Description: MCP public data 36 * 37 * Created: 13/01/2013 yanivr 38 * 39 ****************************************************************************/ 40 41#ifndef MCP_PUBLIC_H 42#define MCP_PUBLIC_H 43 44#define VF_MAX_STATIC 192 /* In case of AH */ 45 46#define MCP_GLOB_PATH_MAX 2 47#define MCP_PORT_MAX 2 /* Global */ 48#define MCP_GLOB_PORT_MAX 4 /* Global */ 49#define MCP_GLOB_FUNC_MAX 16 /* Global */ 50 51typedef u32 offsize_t; /* In DWORDS !!! */ 52/* Offset from the beginning of the MCP scratchpad */ 53#define OFFSIZE_OFFSET_OFFSET 0 54#define OFFSIZE_OFFSET_MASK 0x0000ffff 55/* Size of specific element (not the whole array if any) */ 56#define OFFSIZE_SIZE_OFFSET 16 57#define OFFSIZE_SIZE_MASK 0xffff0000 58 59/* SECTION_OFFSET is calculating the offset in bytes out of offsize */ 60#define SECTION_OFFSET(_offsize) ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_OFFSET) << 2)) 61 62/* SECTION_SIZE is calculating the size in bytes out of offsize */ 63#define SECTION_SIZE(_offsize) (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_OFFSET) << 2) 64 65/* SECTION_ADDR returns the GRC addr of a section, given offsize and index within section */ 66#define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx)) 67 68/* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use offsetof, since the OFFSETUP collide with the firmware definition */ 69#define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base + offsetof(struct mcp_public_data, sections[_section])) 70/* PHY configuration */ 71struct eth_phy_cfg { 72 u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */ 73#define ETH_SPEED_AUTONEG 0 74#define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */ 75 76 u32 pause; /* bitmask */ 77#define ETH_PAUSE_NONE 0x0 78#define ETH_PAUSE_AUTONEG 0x1 79#define ETH_PAUSE_RX 0x2 80#define ETH_PAUSE_TX 0x4 81 82 u32 adv_speed; /* Default should be the speed_cap_mask */ 83 u32 loopback_mode; 84#define ETH_LOOPBACK_NONE (0) 85#define ETH_LOOPBACK_INT_PHY (1) /* Serdes loopback. In AH, it refers to Near End */ 86#define ETH_LOOPBACK_EXT_PHY (2) /* External PHY Loopback */ 87#define ETH_LOOPBACK_EXT (3) /* External Loopback (Require loopback plug) */ 88#define ETH_LOOPBACK_MAC (4) /* MAC Loopback - not supported */ 89#define ETH_LOOPBACK_CNIG_AH_ONLY_0123 (5) /* Port to itself */ 90#define ETH_LOOPBACK_CNIG_AH_ONLY_2301 (6) /* Port to Port */ 91#define ETH_LOOPBACK_PCS_AH_ONLY (7) /* PCS loopback (TX to RX) */ 92#define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8) /* Loop RX packet from PCS to TX */ 93#define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) /* Remote Serdes Loopback (RX to TX) */ 94 95 u32 eee_cfg; 96#define EEE_CFG_EEE_ENABLED (1<<0) /* EEE is enabled (configuration). Refer to eee_status->active for negotiated status */ 97#define EEE_CFG_TX_LPI (1<<1) 98#define EEE_CFG_ADV_SPEED_1G (1<<2) 99#define EEE_CFG_ADV_SPEED_10G (1<<3) 100#define EEE_TX_TIMER_USEC_MASK (0xfffffff0) 101#define EEE_TX_TIMER_USEC_OFFSET 4 102#define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00) 103#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100) 104#define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000) 105 106 u32 link_modes; /* Additional link modes */ 107#define LINK_MODE_SMARTLINQ_ENABLE 0x1 /* XXX Deprecate */ 108}; 109 110struct port_mf_cfg { 111 u32 dynamic_cfg; /* device control channel */ 112#define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff 113#define PORT_MF_CFG_OV_TAG_OFFSET 0 114#define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK 115 116 u32 reserved[1]; 117}; 118 119/* DO NOT add new fields in the middle 120 * MUST be synced with struct pmm_stats_map 121 */ 122struct eth_stats { 123 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/ 124 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/ 125 u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/ 126 u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/ 127 u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/ 128 u64 r1518; /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */ 129 union { 130 struct { /* bb */ 131 u64 r1522; /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */ 132 u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/ 133 u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/ 134 u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/ 135 u64 r16383; /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */ 136 137 } bb0; 138 struct { /* ah */ 139 u64 unused1; 140 u64 r1519_to_max; /* 0x07 (Offset 0x38 ) RX 1519 to max byte frame counter*/ 141 u64 unused2; 142 u64 unused3; 143 u64 unused4; 144 } ah0; 145 } u0; 146 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/ 147 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/ 148 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/ 149 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/ 150 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/ 151 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */ 152 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/ 153 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */ 154 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */ 155 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */ 156 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */ 157 u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */ 158 u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/ 159 u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/ 160 u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/ 161 u64 t1518; /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */ 162 union { 163 struct { /* bb */ 164 u64 t2047; /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */ 165 u64 t4095; /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */ 166 u64 t9216; /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */ 167 u64 t16383; /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */ 168 } bb1; 169 struct { /* ah */ 170 u64 t1519_to_max; /* 0x47 (Offset 0xd8 ) TX 1519 to max byte frame counter */ 171 u64 unused6; 172 u64 unused7; 173 u64 unused8; 174 } ah1; 175 } u1; 176 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */ 177 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */ 178 union { 179 struct { /* bb */ 180 u64 tlpiec; /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ 181 u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */ 182 } bb2; 183 struct { /* ah */ 184 u64 unused9; 185 u64 unused10; 186 } ah2; 187 } u2; 188 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */ 189 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */ 190 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */ 191 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */ 192 u64 rxpok; /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */ 193 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */ 194 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */ 195 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */ 196 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */ 197 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */ 198 /* HSI - Cannot add more stats to this struct. If needed, then need to open new struct */ 199}; 200 201struct brb_stats { 202 u64 brb_truncate[8]; 203 u64 brb_discard[8]; 204}; 205 206struct port_stats { 207 struct brb_stats brb; 208 struct eth_stats eth; 209}; 210 211/*-----+----------------------------------------------------------------------------- 212 * Chip | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines 213 * | rate of physical | team #1 | team #2 |are used|per path | (paths) enabled 214 * | ports | | | | | 215 *======+==================+=========+=========+========+==========+================= 216 * BB | 1x100G | This is special mode, where there are actually 2 HW func 217 * BB | 2x10/20Gbps | 0,1 | NA | No | 1 | 1 218 * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1 219 * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1 220 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional) 221 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional) 222 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional) 223 * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1 224 * AH | 2x10/20Gbps | 0,1 | NA | NA | 1 | NA 225 * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA 226 * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA 227 * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA 228 * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA 229 *======+==================+=========+=========+========+==========+=================== 230 */ 231 232#define CMT_TEAM0 0 233#define CMT_TEAM1 1 234#define CMT_TEAM_MAX 2 235 236struct couple_mode_teaming { 237 u8 port_cmt[MCP_GLOB_PORT_MAX]; 238#define PORT_CMT_IN_TEAM (1<<0) 239 240#define PORT_CMT_PORT_ROLE (1<<1) 241#define PORT_CMT_PORT_INACTIVE (0<<1) 242#define PORT_CMT_PORT_ACTIVE (1<<1) 243 244#define PORT_CMT_TEAM_MASK (1<<2) 245#define PORT_CMT_TEAM0 (0<<2) 246#define PORT_CMT_TEAM1 (1<<2) 247}; 248 249/************************************** 250 * LLDP and DCBX HSI structures 251 **************************************/ 252#define LLDP_CHASSIS_ID_STAT_LEN 4 253#define LLDP_PORT_ID_STAT_LEN 4 254#define DCBX_MAX_APP_PROTOCOL 32 255#define MAX_SYSTEM_LLDP_TLV_DATA 32 /* In dwords. 128 in bytes*/ 256#define MAX_TLV_BUFFER 128 /* In dwords. 512 in bytes*/ 257typedef enum _lldp_agent_e { 258 LLDP_NEAREST_BRIDGE = 0, 259 LLDP_NEAREST_NON_TPMR_BRIDGE, 260 LLDP_NEAREST_CUSTOMER_BRIDGE, 261 LLDP_MAX_LLDP_AGENTS 262} lldp_agent_e; 263 264struct lldp_config_params_s { 265 u32 config; 266#define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff 267#define LLDP_CONFIG_TX_INTERVAL_OFFSET 0 268#define LLDP_CONFIG_HOLD_MASK 0x00000f00 269#define LLDP_CONFIG_HOLD_OFFSET 8 270#define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 271#define LLDP_CONFIG_MAX_CREDIT_OFFSET 12 272#define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 273#define LLDP_CONFIG_ENABLE_RX_OFFSET 30 274#define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 275#define LLDP_CONFIG_ENABLE_TX_OFFSET 31 276 /* Holds local Chassis ID TLV header, subtype and 9B of payload. 277 If firtst byte is 0, then we will use default chassis ID */ 278 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 279 /* Holds local Port ID TLV header, subtype and 9B of payload. 280 If firtst byte is 0, then we will use default port ID */ 281 u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; 282}; 283 284struct lldp_status_params_s { 285 u32 prefix_seq_num; 286 u32 status; /* TBD */ 287 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 288 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 289 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 290 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; 291 u32 suffix_seq_num; 292}; 293 294struct dcbx_ets_feature { 295 u32 flags; 296#define DCBX_ETS_ENABLED_MASK 0x00000001 297#define DCBX_ETS_ENABLED_OFFSET 0 298#define DCBX_ETS_WILLING_MASK 0x00000002 299#define DCBX_ETS_WILLING_OFFSET 1 300#define DCBX_ETS_ERROR_MASK 0x00000004 301#define DCBX_ETS_ERROR_OFFSET 2 302#define DCBX_ETS_CBS_MASK 0x00000008 303#define DCBX_ETS_CBS_OFFSET 3 304#define DCBX_ETS_MAX_TCS_MASK 0x000000f0 305#define DCBX_ETS_MAX_TCS_OFFSET 4 306#define DCBX_OOO_TC_MASK 0x00000f00 307#define DCBX_OOO_TC_OFFSET 8 308 /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */ 309 u32 pri_tc_tbl[1]; 310/* Fixed TCP OOO TC usage is deprecated and used only for driver backward compatibility */ 311#define DCBX_TCP_OOO_TC (4) 312#define DCBX_TCP_OOO_K2_4PORT_TC (3) 313 314#define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1) 315#define DCBX_CEE_STRICT_PRIORITY 0xf 316 /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */ 317 u32 tc_bw_tbl[2]; 318 /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */ 319 u32 tc_tsa_tbl[2]; 320#define DCBX_ETS_TSA_STRICT 0 321#define DCBX_ETS_TSA_CBS 1 322#define DCBX_ETS_TSA_ETS 2 323}; 324 325struct dcbx_app_priority_entry { 326 u32 entry; 327#define DCBX_APP_PRI_MAP_MASK 0x000000ff 328#define DCBX_APP_PRI_MAP_OFFSET 0 329#define DCBX_APP_PRI_0 0x01 330#define DCBX_APP_PRI_1 0x02 331#define DCBX_APP_PRI_2 0x04 332#define DCBX_APP_PRI_3 0x08 333#define DCBX_APP_PRI_4 0x10 334#define DCBX_APP_PRI_5 0x20 335#define DCBX_APP_PRI_6 0x40 336#define DCBX_APP_PRI_7 0x80 337#define DCBX_APP_SF_MASK 0x00000300 338#define DCBX_APP_SF_OFFSET 8 339#define DCBX_APP_SF_ETHTYPE 0 340#define DCBX_APP_SF_PORT 1 341#define DCBX_APP_SF_IEEE_MASK 0x0000f000 342#define DCBX_APP_SF_IEEE_OFFSET 12 343#define DCBX_APP_SF_IEEE_RESERVED 0 344#define DCBX_APP_SF_IEEE_ETHTYPE 1 345#define DCBX_APP_SF_IEEE_TCP_PORT 2 346#define DCBX_APP_SF_IEEE_UDP_PORT 3 347#define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 348 349#define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 350#define DCBX_APP_PROTOCOL_ID_OFFSET 16 351}; 352 353/* FW structure in BE */ 354struct dcbx_app_priority_feature { 355 u32 flags; 356#define DCBX_APP_ENABLED_MASK 0x00000001 357#define DCBX_APP_ENABLED_OFFSET 0 358#define DCBX_APP_WILLING_MASK 0x00000002 359#define DCBX_APP_WILLING_OFFSET 1 360#define DCBX_APP_ERROR_MASK 0x00000004 361#define DCBX_APP_ERROR_OFFSET 2 362 /* Not in use 363 #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00 364 #define DCBX_APP_DEFAULT_PRI_OFFSET 8 365 */ 366#define DCBX_APP_MAX_TCS_MASK 0x0000f000 367#define DCBX_APP_MAX_TCS_OFFSET 12 368#define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 369#define DCBX_APP_NUM_ENTRIES_OFFSET 16 370 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 371}; 372 373/* FW structure in BE */ 374struct dcbx_features { 375 /* PG feature */ 376 struct dcbx_ets_feature ets; 377 /* PFC feature */ 378 u32 pfc; 379#define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff 380#define DCBX_PFC_PRI_EN_BITMAP_OFFSET 0 381#define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 382#define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 383#define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 384#define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 385#define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 386#define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 387#define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 388#define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 389 390#define DCBX_PFC_FLAGS_MASK 0x0000ff00 391#define DCBX_PFC_FLAGS_OFFSET 8 392#define DCBX_PFC_CAPS_MASK 0x00000f00 393#define DCBX_PFC_CAPS_OFFSET 8 394#define DCBX_PFC_MBC_MASK 0x00004000 395#define DCBX_PFC_MBC_OFFSET 14 396#define DCBX_PFC_WILLING_MASK 0x00008000 397#define DCBX_PFC_WILLING_OFFSET 15 398#define DCBX_PFC_ENABLED_MASK 0x00010000 399#define DCBX_PFC_ENABLED_OFFSET 16 400#define DCBX_PFC_ERROR_MASK 0x00020000 401#define DCBX_PFC_ERROR_OFFSET 17 402 403 /* APP feature */ 404 struct dcbx_app_priority_feature app; 405}; 406 407struct dcbx_local_params { 408 u32 config; 409#define DCBX_CONFIG_VERSION_MASK 0x00000007 410#define DCBX_CONFIG_VERSION_OFFSET 0 411#define DCBX_CONFIG_VERSION_DISABLED 0 412#define DCBX_CONFIG_VERSION_IEEE 1 413#define DCBX_CONFIG_VERSION_CEE 2 414#define DCBX_CONFIG_VERSION_DYNAMIC (DCBX_CONFIG_VERSION_IEEE | DCBX_CONFIG_VERSION_CEE) 415#define DCBX_CONFIG_VERSION_STATIC 4 416 417 u32 flags; 418 struct dcbx_features features; 419}; 420 421struct dcbx_mib { 422 u32 prefix_seq_num; 423 u32 flags; 424 /* 425 #define DCBX_CONFIG_VERSION_MASK 0x00000007 426 #define DCBX_CONFIG_VERSION_OFFSET 0 427 #define DCBX_CONFIG_VERSION_DISABLED 0 428 #define DCBX_CONFIG_VERSION_IEEE 1 429 #define DCBX_CONFIG_VERSION_CEE 2 430 #define DCBX_CONFIG_VERSION_STATIC 4 431 */ 432 struct dcbx_features features; 433 u32 suffix_seq_num; 434}; 435 436struct lldp_system_tlvs_buffer_s { 437 u32 flags; 438#define LLDP_SYSTEM_TLV_VALID_MASK 0x1 439#define LLDP_SYSTEM_TLV_VALID_OFFSET 0 440/* This bit defines if system TLVs are instead of mandatory TLVS or in 441 * addition to them. Set 1 for replacing mandatory TLVs 442 */ 443#define LLDP_SYSTEM_TLV_MANDATORY_MASK 0x2 444#define LLDP_SYSTEM_TLV_MANDATORY_OFFSET 1 445#define LLDP_SYSTEM_TLV_LENGTH_MASK 0xffff0000 446#define LLDP_SYSTEM_TLV_LENGTH_OFFSET 16 447 u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; 448}; 449 450/* Since this struct is written by MFW and read by driver need to add 451 * sequence guards (as in case of DCBX MIB) 452 */ 453struct lldp_received_tlvs_s { 454 u32 prefix_seq_num; 455 u32 length; 456 u32 tlvs_buffer[MAX_TLV_BUFFER]; 457 u32 suffix_seq_num; 458}; 459 460struct dcb_dscp_map { 461 u32 flags; 462#define DCB_DSCP_ENABLE_MASK 0x1 463#define DCB_DSCP_ENABLE_OFFSET 0 464#define DCB_DSCP_ENABLE 1 465 u32 dscp_pri_map[8]; 466 /* the map structure is the following: 467 each u32 is split into 4 bits chunks, each chunk holds priority for respective dscp 468 Lowest dscp is at lsb 469 31 28 24 20 16 12 8 4 0 470 dscp_pri_map[0]: | dscp7 pri | dscp6 pri | dscp5 pri | dscp4 pri | dscp3 pri | dscp2 pri | dscp1 pri | dscp0 pri | 471 dscp_pri_map[1]: | dscp15 pri| dscp14 pri| dscp13 pri| dscp12 pri| dscp11 pri| dscp10 pri| dscp9 pri | dscp8 pri | 472 etc.*/ 473}; 474 475struct mcp_val64 { 476 u32 lo; 477 u32 hi; 478}; 479 480/* generic_idc_msg_t to be used for inter driver communication. 481 * source_pf specifies the originating PF that sent messages to all target PFs 482 * msg contains 64 bit value of the message - opaque to the MFW 483 */ 484struct generic_idc_msg_s { 485 u32 source_pf; 486 struct mcp_val64 msg; 487}; 488 489/************************************** 490 * Attributes commands 491 **************************************/ 492 493enum _attribute_commands_e { 494 ATTRIBUTE_CMD_READ = 0, 495 ATTRIBUTE_CMD_WRITE, 496 ATTRIBUTE_CMD_READ_CLEAR, 497 ATTRIBUTE_CMD_CLEAR, 498 ATTRIBUTE_NUM_OF_COMMANDS 499}; 500 501/**************************************/ 502/* */ 503/* P U B L I C G L O B A L */ 504/* */ 505/**************************************/ 506struct public_global { 507 u32 max_path; /* 32bit is wasty, but this will be used often */ 508 u32 max_ports; /* (Global) 32bit is wasty, but this will be used often */ 509#define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */ 510#define MODE_2P 2 511#define MODE_3P 3 512#define MODE_4P 4 513 u32 debug_mb_offset; 514 u32 phymod_dbg_mb_offset; 515 struct couple_mode_teaming cmt; 516 s32 internal_temperature; /* Temperature in Celcius (-255C / +255C), measured every second. */ 517 u32 mfw_ver; 518 u32 running_bundle_id; 519 s32 external_temperature; 520 u32 mdump_reason; 521#define MDUMP_REASON_INTERNAL_ERROR (1 << 0) 522#define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1) 523#define MDUMP_REASON_DUMP_AGED (1 << 2) 524 u32 ext_phy_upgrade_fw; 525#define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff) 526#define EXT_PHY_FW_UPGRADE_STATUS_OFFSET (0) 527#define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS (1) 528#define EXT_PHY_FW_UPGRADE_STATUS_FAILED (2) 529#define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS (3) 530#define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000) 531#define EXT_PHY_FW_UPGRADE_TYPE_OFFSET (16) 532 533 u8 runtime_port_swap_map[MODE_4P]; 534 u32 data_ptr; 535 u32 data_size; 536}; 537 538/**************************************/ 539/* */ 540/* P U B L I C P A T H */ 541/* */ 542/**************************************/ 543 544/**************************************************************************** 545 * Shared Memory 2 Region * 546 ****************************************************************************/ 547/* The fw_flr_ack is actually built in the following way: */ 548/* 8 bit: PF ack */ 549/* 128 bit: VF ack */ 550/* 8 bit: ios_dis_ack */ 551/* In order to maintain endianity in the mailbox hsi, we want to keep using */ 552/* u32. The fw must have the VF right after the PF since this is how it */ 553/* access arrays(it expects always the VF to reside after the PF, and that */ 554/* makes the calculation much easier for it. ) */ 555/* In order to answer both limitations, and keep the struct small, the code */ 556/* will abuse the structure defined here to achieve the actual partition */ 557/* above */ 558/****************************************************************************/ 559struct fw_flr_mb { 560 u32 aggint; 561 u32 opgen_addr; 562 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */ 563#define ACCUM_ACK_PF_BASE 0 564#define ACCUM_ACK_PF_SHIFT 0 565 566#define ACCUM_ACK_VF_BASE 8 567#define ACCUM_ACK_VF_SHIFT 3 568 569#define ACCUM_ACK_IOV_DIS_BASE 256 570#define ACCUM_ACK_IOV_DIS_SHIFT 8 571 572}; 573 574struct public_path { 575 struct fw_flr_mb flr_mb; 576 /* 577 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 578 * which were disabled/flred 579 */ 580 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */ 581 582 u32 process_kill; /* Reset on mcp reset, and incremented for eveny process kill event. */ 583#define PROCESS_KILL_COUNTER_MASK 0x0000ffff 584#define PROCESS_KILL_COUNTER_OFFSET 0 585#define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 586#define PROCESS_KILL_GLOB_AEU_BIT_OFFSET 16 587#define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id*32 + aeu_bit) 588}; 589 590/**************************************/ 591/* */ 592/* P U B L I C P O R T */ 593/* */ 594/**************************************/ 595#define FC_NPIV_WWPN_SIZE 8 596#define FC_NPIV_WWNN_SIZE 8 597struct dci_npiv_settings { 598 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE]; 599 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE]; 600}; 601 602struct dci_fc_npiv_cfg { 603 /* hdr used internally by the MFW */ 604 u32 hdr; 605 u32 num_of_npiv; 606}; 607 608#define MAX_NUMBER_NPIV 64 609struct dci_fc_npiv_tbl { 610 struct dci_fc_npiv_cfg fc_npiv_cfg; 611 struct dci_npiv_settings settings[MAX_NUMBER_NPIV]; 612}; 613 614/**************************************************************************** 615 * Driver <-> FW Mailbox * 616 ****************************************************************************/ 617 618struct public_port { 619 u32 validity_map; /* 0x0 (4*2 = 0x8) */ 620 621 /* validity bits */ 622#define MCP_VALIDITY_PCI_CFG 0x00100000 623#define MCP_VALIDITY_MB 0x00200000 624#define MCP_VALIDITY_DEV_INFO 0x00400000 625#define MCP_VALIDITY_RESERVED 0x00000007 626 627 /* One licensing bit should be set */ 628#define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 /* yaniv - tbd ? license */ 629#define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 630#define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 631#define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 632 633 /* Active MFW */ 634#define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 635#define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 636#define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040 637#define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 638 639 u32 link_status; 640#define LINK_STATUS_LINK_UP 0x00000001 641#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e 642#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1<<1) 643#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2<<1) 644#define LINK_STATUS_SPEED_AND_DUPLEX_10G (3<<1) 645#define LINK_STATUS_SPEED_AND_DUPLEX_20G (4<<1) 646#define LINK_STATUS_SPEED_AND_DUPLEX_40G (5<<1) 647#define LINK_STATUS_SPEED_AND_DUPLEX_50G (6<<1) 648#define LINK_STATUS_SPEED_AND_DUPLEX_100G (7<<1) 649#define LINK_STATUS_SPEED_AND_DUPLEX_25G (8<<1) 650#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 651#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 652#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 653#define LINK_STATUS_PFC_ENABLED 0x00000100 654#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 655#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 656#define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 657#define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 658#define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 659#define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 660#define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 661#define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 662#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 663#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 664#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 665#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 666#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 667#define LINK_STATUS_SFP_TX_FAULT 0x00100000 668#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 669#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 670#define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 671#define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 672#define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 673#define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 674#define LINK_STATUS_FEC_MODE_MASK 0x38000000 675#define LINK_STATUS_FEC_MODE_NONE (0<<27) 676#define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1<<27) 677#define LINK_STATUS_FEC_MODE_RS_CL91 (2<<27) 678#define LINK_STATUS_EXT_PHY_LINK_UP 0x40000000 679 680 u32 link_status1; 681#define LP_PRESENCE_STATUS_OFFSET 0 682#define LP_PRESENCE_STATUS_MASK 0x3 683#define LP_PRESENCE_UNKNOWN 0x0 684#define LP_PRESENCE_PROBING 0x1 685#define LP_PRESENT 0x2 686#define LP_NOT_PRESENT 0x3 687 688 u32 ext_phy_fw_version; 689 u32 drv_phy_cfg_addr; /* Points to struct eth_phy_cfg (For READ-ONLY) */ 690 691 u32 port_stx; 692 693 u32 stat_nig_timer; 694 695 struct port_mf_cfg port_mf_config; 696 struct port_stats stats; 697 698 u32 media_type; 699#define MEDIA_UNSPECIFIED 0x0 700#define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */ 701#define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */ 702#define MEDIA_DA_TWINAX 0x3 703#define MEDIA_BASE_T 0x4 704#define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */ 705#define MEDIA_MODULE_FIBER 0x6 706#define MEDIA_KR 0xf0 707#define MEDIA_NOT_PRESENT 0xff 708 709 u32 lfa_status; 710#define LFA_LINK_FLAP_REASON_OFFSET 0 711#define LFA_LINK_FLAP_REASON_MASK 0x000000ff 712#define LFA_NO_REASON (0<<0) 713#define LFA_LINK_DOWN (1<<0) 714#define LFA_FORCE_INIT (1<<1) 715#define LFA_LOOPBACK_MISMATCH (1<<2) 716#define LFA_SPEED_MISMATCH (1<<3) 717#define LFA_FLOW_CTRL_MISMATCH (1<<4) 718#define LFA_ADV_SPEED_MISMATCH (1<<5) 719#define LFA_EEE_MISMATCH (1<<6) 720#define LFA_LINK_MODES_MISMATCH (1<<7) 721#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 722#define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 723#define LINK_FLAP_COUNT_OFFSET 16 724#define LINK_FLAP_COUNT_MASK 0x00ff0000 725 726 u32 link_change_count; 727 728 /* LLDP params */ 729 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; // offset: 536 bytes? 730 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; 731 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; 732 733 /* DCBX related MIB */ 734 struct dcbx_local_params local_admin_dcbx_mib; 735 struct dcbx_mib remote_dcbx_mib; 736 struct dcbx_mib operational_dcbx_mib; 737 738 /* FC_NPIV table offset & size in NVRAM value of 0 means not present */ 739 u32 fc_npiv_nvram_tbl_addr; 740#define NPIV_TBL_INVALID_ADDR 0xFFFFFFFF 741 742 u32 fc_npiv_nvram_tbl_size; 743 u32 transceiver_data; 744#define ETH_TRANSCEIVER_STATE_MASK 0x000000FF 745#define ETH_TRANSCEIVER_STATE_OFFSET 0x0 746#define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00 747#define ETH_TRANSCEIVER_STATE_PRESENT 0x01 748#define ETH_TRANSCEIVER_STATE_VALID 0x03 749#define ETH_TRANSCEIVER_STATE_UPDATING 0x08 750#define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00 751#define ETH_TRANSCEIVER_TYPE_OFFSET 0x8 752#define ETH_TRANSCEIVER_TYPE_NONE 0x00 753#define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xFF 754#define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 /* 1G Passive copper cable */ 755#define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 /* 1G Active copper cable */ 756#define ETH_TRANSCEIVER_TYPE_1G_LX 0x03 757#define ETH_TRANSCEIVER_TYPE_1G_SX 0x04 758#define ETH_TRANSCEIVER_TYPE_10G_SR 0x05 759#define ETH_TRANSCEIVER_TYPE_10G_LR 0x06 760#define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07 761#define ETH_TRANSCEIVER_TYPE_10G_ER 0x08 762#define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 /* 10G Passive copper cable */ 763#define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a /* 10G Active copper cable */ 764#define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b 765#define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c 766#define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d 767#define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e 768#define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f /* Active optical cable */ 769#define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10 770#define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11 771#define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12 772#define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 /* Active copper cable */ 773#define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14 774#define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15 775#define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 /* 25G Passive copper cable - short */ 776#define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 /* 25G Active copper cable - short */ 777#define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 /* 25G Passive copper cable - medium */ 778#define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 /* 25G Active copper cable - medium */ 779#define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a /* 25G Passive copper cable - long */ 780#define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b /* 25G Active copper cable - long */ 781#define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c 782#define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d 783#define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e 784#define ETH_TRANSCEIVER_TYPE_4x10G 0x1f 785#define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 786#define ETH_TRANSCEIVER_TYPE_1000BASET 0x21 787#define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22 788#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 789#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 790#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 791#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33 792#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34 793#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35 794#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36 795 u32 wol_info; 796 u32 wol_pkt_len; 797 u32 wol_pkt_details; 798 struct dcb_dscp_map dcb_dscp_map; 799 800 u32 eee_status; 801#define EEE_ACTIVE_BIT (1<<0) /* Set when EEE negotiation is complete. */ 802 803#define EEE_LD_ADV_STATUS_MASK 0x000000f0 /* Shows the Local Device EEE capabilities */ 804#define EEE_LD_ADV_STATUS_OFFSET 4 805 #define EEE_1G_ADV (1<<1) 806 #define EEE_10G_ADV (1<<2) 807#define EEE_LP_ADV_STATUS_MASK 0x00000f00 /* Same values as in EEE_LD_ADV, but for Link Parter */ 808#define EEE_LP_ADV_STATUS_OFFSET 8 809 810#define EEE_SUPPORTED_SPEED_MASK 0x0000f000 /* Supported speeds for EEE */ 811#define EEE_SUPPORTED_SPEED_OFFSET 12 812 #define EEE_1G_SUPPORTED (1 << 1) 813 #define EEE_10G_SUPPORTED (1 << 2) 814 815 u32 eee_remote; /* Used for EEE in LLDP */ 816#define EEE_REMOTE_TW_TX_MASK 0x0000ffff 817#define EEE_REMOTE_TW_TX_OFFSET 0 818#define EEE_REMOTE_TW_RX_MASK 0xffff0000 819#define EEE_REMOTE_TW_RX_OFFSET 16 820 821 u32 module_info; 822#define ETH_TRANSCEIVER_MONITORING_TYPE_MASK 0x000000FF 823#define ETH_TRANSCEIVER_MONITORING_TYPE_OFFSET 0 824#define ETH_TRANSCEIVER_ADDR_CHNG_REQUIRED (1 << 2) 825#define ETH_TRANSCEIVER_RCV_PWR_MEASURE_TYPE (1 << 3) 826#define ETH_TRANSCEIVER_EXTERNALLY_CALIBRATED (1 << 4) 827#define ETH_TRANSCEIVER_INTERNALLY_CALIBRATED (1 << 5) 828#define ETH_TRANSCEIVER_HAS_DIAGNOSTIC (1 << 6) 829#define ETH_TRANSCEIVER_IDENT_MASK 0x0000ff00 830#define ETH_TRANSCEIVER_IDENT_OFFSET 8 831 832 u32 oem_cfg_port; 833#define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003 834#define OEM_CFG_CHANNEL_TYPE_OFFSET 0 835#define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1 836#define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2 837 838#define OEM_CFG_SCHED_TYPE_MASK 0x0000000C 839#define OEM_CFG_SCHED_TYPE_OFFSET 2 840#define OEM_CFG_SCHED_TYPE_ETS 0x1 841#define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2 842 843 struct lldp_received_tlvs_s lldp_received_tlvs[LLDP_MAX_LLDP_AGENTS]; 844 u32 system_lldp_tlvs_buf2[MAX_SYSTEM_LLDP_TLV_DATA]; 845}; 846 847/**************************************/ 848/* */ 849/* P U B L I C F U N C */ 850/* */ 851/**************************************/ 852 853struct public_func { 854 u32 iscsi_boot_signature; 855 u32 iscsi_boot_block_offset; 856 857 /* MTU size per funciton is needed for the OV feature */ 858 u32 mtu_size; 859 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ 860 /* For PCP values 0-3 use the map lower */ 861 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, 862 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 863 */ 864 u32 c2s_pcp_map_lower; 865 /* For PCP values 4-7 use the map upper */ 866 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, 867 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 868 */ 869 u32 c2s_pcp_map_upper; 870 871 /* For PCP default value get the MSB byte of the map default */ 872 u32 c2s_pcp_map_default; 873 874 /* For generic inter driver communication channel messages between PFs via MFW*/ 875 struct generic_idc_msg_s generic_idc_msg; 876 877 u32 num_of_msix; 878 879 // replace old mf_cfg 880 u32 config; 881 /* E/R/I/D */ 882 /* function 0 of each port cannot be hidden */ 883#define FUNC_MF_CFG_FUNC_HIDE 0x00000001 884#define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 885#define FUNC_MF_CFG_PAUSE_ON_HOST_RING_OFFSET 0x00000001 886 887#define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 888#define FUNC_MF_CFG_PROTOCOL_OFFSET 4 889#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 890#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 891#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 892#define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 893#define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 894 895 /* MINBW, MAXBW */ 896 /* value range - 0..100, increments in 1 % */ 897#define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 898#define FUNC_MF_CFG_MIN_BW_OFFSET 8 899#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 900#define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 901#define FUNC_MF_CFG_MAX_BW_OFFSET 16 902#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 903 904 /*RDMA PROTOCL*/ 905#define FUNC_MF_CFG_RDMA_PROTOCOL_MASK 0x03000000 906#define FUNC_MF_CFG_RDMA_PROTOCOL_OFFSET 24 907#define FUNC_MF_CFG_RDMA_PROTOCOL_NONE 0x00000000 908#define FUNC_MF_CFG_RDMA_PROTOCOL_ROCE 0x01000000 909#define FUNC_MF_CFG_RDMA_PROTOCOL_IWARP 0x02000000 910 /*for future support*/ 911#define FUNC_MF_CFG_RDMA_PROTOCOL_BOTH 0x03000000 912 913#define FUNC_MF_CFG_BOOT_MODE_MASK 0x0C000000 914#define FUNC_MF_CFG_BOOT_MODE_OFFSET 26 915#define FUNC_MF_CFG_BOOT_MODE_BIOS_CTRL 0x00000000 916#define FUNC_MF_CFG_BOOT_MODE_DISABLED 0x04000000 917#define FUNC_MF_CFG_BOOT_MODE_ENABLED 0x08000000 918 919 u32 status; 920#define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001 921#define FUNC_STATUS_LOGICAL_LINK_UP 0x00000002 922#define FUNC_STATUS_FORCED_LINK 0x00000004 923 924 u32 mac_upper; /* MAC */ 925#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 926#define FUNC_MF_CFG_UPPERMAC_OFFSET 0 927#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 928 u32 mac_lower; 929#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 930 931 u32 fcoe_wwn_port_name_upper; 932 u32 fcoe_wwn_port_name_lower; 933 934 u32 fcoe_wwn_node_name_upper; 935 u32 fcoe_wwn_node_name_lower; 936 937 u32 ovlan_stag; /* tags */ 938#define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff 939#define FUNC_MF_CFG_OV_STAG_OFFSET 0 940#define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK 941 942 u32 pf_allocation; /* vf per pf */ 943 944 u32 preserve_data; /* Will be used bt CCM */ 945 946 u32 driver_last_activity_ts; 947 948 /* 949 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 950 * VFs 951 */ 952 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */ 953 954 u32 drv_id; 955#define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff 956#define DRV_ID_PDA_COMP_VER_OFFSET 0 957 958#define LOAD_REQ_HSI_VERSION 2 959#define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 960#define DRV_ID_MCP_HSI_VER_OFFSET 16 961#define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << DRV_ID_MCP_HSI_VER_OFFSET) 962 963#define DRV_ID_DRV_TYPE_MASK 0x7f000000 964#define DRV_ID_DRV_TYPE_OFFSET 24 965#define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_OFFSET) 966#define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_OFFSET) 967#define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_OFFSET) 968#define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_OFFSET) 969#define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_OFFSET) 970#define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_OFFSET) 971#define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_OFFSET) 972#define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_OFFSET) 973#define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_OFFSET) 974 975#define DRV_ID_DRV_TYPE_OS (DRV_ID_DRV_TYPE_LINUX | DRV_ID_DRV_TYPE_WINDOWS | \ 976 DRV_ID_DRV_TYPE_SOLARIS | DRV_ID_DRV_TYPE_VMWARE | \ 977 DRV_ID_DRV_TYPE_FREEBSD | DRV_ID_DRV_TYPE_AIX) 978 979#define DRV_ID_DRV_INIT_HW_MASK 0x80000000 980#define DRV_ID_DRV_INIT_HW_OFFSET 31 981#define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_OFFSET) 982 983 u32 oem_cfg_func; 984#define OEM_CFG_FUNC_TC_MASK 0x0000000F 985#define OEM_CFG_FUNC_TC_OFFSET 0 986#define OEM_CFG_FUNC_TC_0 0x0 987#define OEM_CFG_FUNC_TC_1 0x1 988#define OEM_CFG_FUNC_TC_2 0x2 989#define OEM_CFG_FUNC_TC_3 0x3 990#define OEM_CFG_FUNC_TC_4 0x4 991#define OEM_CFG_FUNC_TC_5 0x5 992#define OEM_CFG_FUNC_TC_6 0x6 993#define OEM_CFG_FUNC_TC_7 0x7 994 995#define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030 996#define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4 997#define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1 998#define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2 999}; 1000 1001/**************************************/ 1002/* */ 1003/* P U B L I C M B */ 1004/* */ 1005/**************************************/ 1006/* This is the only section that the driver can write to, and each */ 1007/* Basically each driver request to set feature parameters, 1008 * will be done using a different command, which will be linked 1009 * to a specific data structure from the union below. 1010 * For huge strucuture, the common blank structure should be used. 1011 */ 1012 1013struct mcp_mac { 1014 u32 mac_upper; /* Upper 16 bits are always zeroes */ 1015 u32 mac_lower; 1016}; 1017 1018struct mcp_file_att { 1019 u32 nvm_start_addr; 1020 u32 len; 1021}; 1022 1023struct bist_nvm_image_att { 1024 u32 return_code; 1025 u32 image_type; /* Image type */ 1026 u32 nvm_start_addr; /* NVM address of the image */ 1027 u32 len; /* Include CRC */ 1028}; 1029 1030#define MCP_DRV_VER_STR_SIZE 16 1031#define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) 1032#define MCP_DRV_NVM_BUF_LEN 32 1033struct drv_version_stc { 1034 u32 version; 1035 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 1036}; 1037 1038/* statistics for ncsi */ 1039struct lan_stats_stc { 1040 u64 ucast_rx_pkts; 1041 u64 ucast_tx_pkts; 1042 u32 fcs_err; 1043 u32 rserved; 1044}; 1045 1046struct fcoe_stats_stc { 1047 u64 rx_pkts; 1048 u64 tx_pkts; 1049 u32 fcs_err; 1050 u32 login_failure; 1051}; 1052 1053struct iscsi_stats_stc { 1054 u64 rx_pdus; 1055 u64 tx_pdus; 1056 u64 rx_bytes; 1057 u64 tx_bytes; 1058}; 1059 1060struct rdma_stats_stc { 1061 u64 rx_pkts; 1062 u64 tx_pkts; 1063 u64 rx_bytes; 1064 u64 tx_bytes; 1065}; 1066 1067struct ocbb_data_stc { 1068 u32 ocbb_host_addr; 1069 u32 ocsd_host_addr; 1070 u32 ocsd_req_update_interval; 1071}; 1072 1073#define MAX_NUM_OF_SENSORS 7 1074#define MFW_SENSOR_LOCATION_INTERNAL 1 1075#define MFW_SENSOR_LOCATION_EXTERNAL 2 1076#define MFW_SENSOR_LOCATION_SFP 3 1077 1078#define SENSOR_LOCATION_OFFSET 0 1079#define SENSOR_LOCATION_MASK 0x000000ff 1080#define THRESHOLD_HIGH_OFFSET 8 1081#define THRESHOLD_HIGH_MASK 0x0000ff00 1082#define CRITICAL_TEMPERATURE_OFFSET 16 1083#define CRITICAL_TEMPERATURE_MASK 0x00ff0000 1084#define CURRENT_TEMP_OFFSET 24 1085#define CURRENT_TEMP_MASK 0xff000000 1086struct temperature_status_stc { 1087 u32 num_of_sensors; 1088 u32 sensor[MAX_NUM_OF_SENSORS]; 1089}; 1090 1091/* crash dump configuration header */ 1092struct mdump_config_stc { 1093 u32 version; 1094 u32 config; 1095 u32 epoc; 1096 u32 num_of_logs; 1097 u32 valid_logs; 1098}; 1099 1100enum resource_id_enum { 1101 RESOURCE_NUM_SB_E = 0, 1102 RESOURCE_NUM_L2_QUEUE_E = 1, 1103 RESOURCE_NUM_VPORT_E = 2, 1104 RESOURCE_NUM_VMQ_E = 3, 1105 RESOURCE_FACTOR_NUM_RSS_PF_E = 4, /* Not a real resource!! it's a factor used to calculate others */ 1106 RESOURCE_FACTOR_RSS_PER_VF_E = 5, /* Not a real resource!! it's a factor used to calculate others */ 1107 RESOURCE_NUM_RL_E = 6, 1108 RESOURCE_NUM_PQ_E = 7, 1109 RESOURCE_NUM_VF_E = 8, 1110 RESOURCE_VFC_FILTER_E = 9, 1111 RESOURCE_ILT_E = 10, 1112 RESOURCE_CQS_E = 11, 1113 RESOURCE_GFT_PROFILES_E = 12, 1114 RESOURCE_NUM_TC_E = 13, 1115 RESOURCE_NUM_RSS_ENGINES_E = 14, 1116 RESOURCE_LL2_QUEUE_E = 15, 1117 RESOURCE_RDMA_STATS_QUEUE_E = 16, 1118 RESOURCE_BDQ_E = 17, 1119 RESOURCE_MAX_NUM, 1120 RESOURCE_NUM_INVALID = 0xFFFFFFFF 1121}; 1122 1123/* Resource ID is to be filled by the driver in the MB request 1124 * Size, offset & flags to be filled by the MFW in the MB response 1125 */ 1126struct resource_info { 1127 enum resource_id_enum res_id; 1128 u32 size; /* number of allocated resources */ 1129 u32 offset; /* Offset of the 1st resource */ 1130 u32 vf_size; 1131 u32 vf_offset; 1132 u32 flags; 1133#define RESOURCE_ELEMENT_STRICT (1 << 0) 1134}; 1135 1136struct mcp_wwn { 1137 u32 wwn_upper; 1138 u32 wwn_lower; 1139}; 1140 1141#define DRV_ROLE_NONE 0 1142#define DRV_ROLE_PREBOOT 1 1143#define DRV_ROLE_OS 2 1144#define DRV_ROLE_KDUMP 3 1145 1146struct load_req_stc { 1147 u32 drv_ver_0; 1148 u32 drv_ver_1; 1149 u32 fw_ver; 1150 u32 misc0; 1151#define LOAD_REQ_ROLE_MASK 0x000000FF 1152#define LOAD_REQ_ROLE_OFFSET 0 1153#define LOAD_REQ_LOCK_TO_MASK 0x0000FF00 1154#define LOAD_REQ_LOCK_TO_OFFSET 8 1155#define LOAD_REQ_LOCK_TO_DEFAULT 0 1156#define LOAD_REQ_LOCK_TO_NONE 255 1157#define LOAD_REQ_FORCE_MASK 0x000F0000 1158#define LOAD_REQ_FORCE_OFFSET 16 1159#define LOAD_REQ_FORCE_NONE 0 1160#define LOAD_REQ_FORCE_PF 1 1161#define LOAD_REQ_FORCE_ALL 2 1162#define LOAD_REQ_FLAGS0_MASK 0x00F00000 1163#define LOAD_REQ_FLAGS0_OFFSET 20 1164#define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0) 1165}; 1166 1167struct load_rsp_stc { 1168 u32 drv_ver_0; 1169 u32 drv_ver_1; 1170 u32 fw_ver; 1171 u32 misc0; 1172#define LOAD_RSP_ROLE_MASK 0x000000FF 1173#define LOAD_RSP_ROLE_OFFSET 0 1174#define LOAD_RSP_HSI_MASK 0x0000FF00 1175#define LOAD_RSP_HSI_OFFSET 8 1176#define LOAD_RSP_FLAGS0_MASK 0x000F0000 1177#define LOAD_RSP_FLAGS0_OFFSET 16 1178#define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0) 1179}; 1180 1181struct mdump_retain_data_stc { 1182 u32 valid; 1183 u32 epoch; 1184 u32 pf; 1185 u32 status; 1186}; 1187 1188struct attribute_cmd_write_stc { 1189 u32 val; 1190 u32 mask; 1191 u32 offset; 1192}; 1193 1194struct lldp_stats_stc { 1195 u32 tx_frames_total; 1196 u32 rx_frames_total; 1197 u32 rx_frames_discarded; 1198 u32 rx_age_outs; 1199}; 1200 1201union drv_union_data { 1202 struct mcp_mac wol_mac; /* UNLOAD_DONE */ 1203 1204 /* This configuration should be set by the driver for the LINK_SET command. */ 1205 struct eth_phy_cfg drv_phy_cfg; 1206 1207 struct mcp_val64 val64; /* For PHY / AVS commands */ 1208 1209 u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 1210 1211 struct mcp_file_att file_att; 1212 1213 u32 ack_vf_disabled[VF_MAX_STATIC / 32]; 1214 1215 struct drv_version_stc drv_version; 1216 1217 struct lan_stats_stc lan_stats; 1218 struct fcoe_stats_stc fcoe_stats; 1219 struct iscsi_stats_stc iscsi_stats; 1220 struct rdma_stats_stc rdma_stats; 1221 struct ocbb_data_stc ocbb_info; 1222 struct temperature_status_stc temp_info; 1223 struct resource_info resource; 1224 struct bist_nvm_image_att nvm_image_att; 1225 struct mdump_config_stc mdump_config; 1226 struct mcp_mac lldp_mac; 1227 struct mcp_wwn fcoe_fabric_name; 1228 u32 dword; 1229 1230 struct load_req_stc load_req; 1231 struct load_rsp_stc load_rsp; 1232 struct mdump_retain_data_stc mdump_retain; 1233 struct attribute_cmd_write_stc attribute_cmd_write; 1234 struct lldp_stats_stc lldp_stats; 1235 /* ... */ 1236}; 1237 1238struct public_drv_mb { 1239 u32 drv_mb_header; 1240#define DRV_MSG_CODE_MASK 0xffff0000 1241#define DRV_MSG_CODE_LOAD_REQ 0x10000000 1242#define DRV_MSG_CODE_LOAD_DONE 0x11000000 1243#define DRV_MSG_CODE_INIT_HW 0x12000000 1244#define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000 1245#define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 1246#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1247#define DRV_MSG_CODE_INIT_PHY 0x22000000 1248 /* Params - FORCE - Reinitialize the link regardless of LFA */ 1249 /* - DONT_CARE - Don't flap the link if up */ 1250#define DRV_MSG_CODE_LINK_RESET 0x23000000 1251 1252#define DRV_MSG_CODE_SET_LLDP 0x24000000 1253#define DRV_MSG_CODE_REGISTER_LLDP_TLVS_RX 0x24100000 1254#define DRV_MSG_CODE_SET_DCBX 0x25000000 1255 /* OneView feature driver HSI*/ 1256#define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 1257#define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 1258#define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 1259#define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000 1260#define DRV_MSG_CODE_NIG_DRAIN 0x30000000 1261#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000 1262#define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 1263#define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000 1264#define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp, data: struct resource_info */ 1265#define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000 1266#define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000 1267#define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000 1268#define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000 1269#define DRV_MSG_CODE_OEM_UPDATE_FCOE_CVID 0x3c000000 1270#define DRV_MSG_CODE_OEM_UPDATE_FCOE_FABRIC_NAME 0x3d000000 1271#define DRV_MSG_CODE_OEM_UPDATE_BOOT_CFG 0x3e000000 1272#define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT 0x3f000000 1273#define DRV_MSG_CODE_OV_GET_CURR_CFG 0x40000000 1274#define DRV_MSG_CODE_GET_OEM_UPDATES 0x41000000 1275#define DRV_MSG_CODE_GET_LLDP_STATS 0x42000000 1276#define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000 /* params [31:8] - reserved, [7:0] - bitmap */ 1277 1278#define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 /*deprecated don't use*/ 1279#define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 1280#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1281#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 1282#define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000 1283#define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */ 1284#define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 /* Param should be set to the transaction size (up to 64 bytes) */ 1285#define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 /* MFW will place the file offset and len in file_att struct */ 1286#define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 /* Read 32bytes of nvram data. Param is [0:23] ??? Offset [24:31] ??? Len in Bytes*/ 1287#define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 /* Writes up to 32Bytes to nvram. Param is [0:23] ??? Offset [24:31] ??? Len in Bytes. In case this address is in the range of secured file in secured mode, the operation will fail */ 1288#define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000 /* Delete a file from nvram. Param is image_type. */ 1289#define DRV_MSG_CODE_MCP_RESET 0x00090000 /* Reset MCP when no NVM operation is going on, and no drivers are loaded. In case operation succeed, MCP will not ack back. */ 1290#define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000 /* Temporary command to set secure mode, where the param is 0 (None secure) / 1 (Secure) / 2 (Full-Secure) */ 1291#define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, [30:31] - port*/ 1292#define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, [30:31] - port */ 1293#define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000 /* Param: [0:15] - Address, [30:31] - port */ 1294#define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 /* Param: [0:15] - Address, [30:31] - port */ 1295#define DRV_MSG_CODE_SET_VERSION 0x000f0000 /* Param: [0:3] - version, [4:15] - name (null terminated) */ 1296#define DRV_MSG_CODE_MCP_HALT 0x00100000 /* Halts the MCP. To resume MCP, user will need to use MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. */ 1297#define DRV_MSG_CODE_SET_VMAC 0x00110000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */ 1298#define DRV_MSG_CODE_GET_VMAC 0x00120000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */ 1299#define DRV_MSG_CODE_VMAC_TYPE_OFFSET 4 1300#define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30 1301#define DRV_MSG_CODE_VMAC_TYPE_MAC 1 1302#define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 1303#define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 1304 1305#define DRV_MSG_CODE_GET_STATS 0x00130000 /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */ 1306#define DRV_MSG_CODE_STATS_TYPE_LAN 1 1307#define DRV_MSG_CODE_STATS_TYPE_FCOE 2 1308#define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 1309#define DRV_MSG_CODE_STATS_TYPE_RDMA 4 1310#define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000 /* Host shall provide buffer and size for MFW */ 1311#define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000 /* Host shall provide buffer and size for MFW */ 1312#define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000 /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address, [16:31] - offset */ 1313#define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000 /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address, [16:31] - offset */ 1314#define DRV_MSG_CODE_OCBB_DATA 0x00180000 /* indicate OCBB related information */ 1315#define DRV_MSG_CODE_SET_BW 0x00190000 /* Set function BW, params[15:8] - min, params[7:0] - max */ 1316#define BW_MAX_MASK 0x000000ff 1317#define BW_MAX_OFFSET 0 1318#define BW_MIN_MASK 0x0000ff00 1319#define BW_MIN_OFFSET 8 1320 1321#define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 /* When param is set to 1, all parities will be masked(disabled). When params are set to 0, parities will be unmasked again. */ 1322#define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000 /* param[0] - Simulate fan failure, param[1] - simulate over temp. */ 1323#define DRV_MSG_FAN_FAILURE_TYPE (1 << 0) 1324#define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1) 1325#define DRV_MSG_CODE_GPIO_READ 0x001c0000 /* Param: [0:15] - gpio number */ 1326#define DRV_MSG_CODE_GPIO_WRITE 0x001d0000 /* Param: [0:15] - gpio number, [16:31] - gpio value */ 1327#define DRV_MSG_CODE_BIST_TEST 0x001e0000 /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */ 1328#define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000 1329#define DRV_MSG_CODE_SET_LED_MODE 0x00200000 /* Set LED mode params :0 operational, 1 LED turn ON, 2 LED turn OFF */ 1330#define DRV_MSG_CODE_TIMESTAMP 0x00210000 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] - driver version (MAJ MIN BUILD SUB) */ 1331#define DRV_MSG_CODE_EMPTY_MB 0x00220000 /* This is an empty mailbox just return OK*/ 1332 1333#define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode, param[15:8] - age */ 1334 1335#define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F 1336#define RESOURCE_CMD_REQ_RESC_OFFSET 0 1337#define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0 1338#define RESOURCE_CMD_REQ_OPCODE_OFFSET 5 1339#define RESOURCE_OPCODE_REQ 1 /* request resource ownership with default aging */ 1340#define RESOURCE_OPCODE_REQ_WO_AGING 2 /* request resource ownership without aging */ 1341#define RESOURCE_OPCODE_REQ_W_AGING 3 /* request resource ownership with specific aging timer (in seconds) */ 1342#define RESOURCE_OPCODE_RELEASE 4 /* release resource */ 1343#define RESOURCE_OPCODE_FORCE_RELEASE 5 /* force resource release */ 1344#define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00 1345#define RESOURCE_CMD_REQ_AGE_OFFSET 8 1346 1347#define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF 1348#define RESOURCE_CMD_RSP_OWNER_OFFSET 0 1349#define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700 1350#define RESOURCE_CMD_RSP_OPCODE_OFFSET 8 1351#define RESOURCE_OPCODE_GNT 1 /* resource is free and granted to requester */ 1352#define RESOURCE_OPCODE_BUSY 2 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, 16 = MFW, 17 = diag over serial */ 1353#define RESOURCE_OPCODE_RELEASED 3 /* indicate release request was acknowledged */ 1354#define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 /* indicate release request was previously received by other owner */ 1355#define RESOURCE_OPCODE_WRONG_OWNER 5 /* indicate wrong owner during release */ 1356#define RESOURCE_OPCODE_UNKNOWN_CMD 255 1357 1358#define RESOURCE_DUMP 0 /* dedicate resource 0 for dump */ 1359 1360#define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */ 1361#define DRV_MSG_CODE_MDUMP_CMD 0x00250000 /* Send crash dump commands with param[3:0] - opcode */ 1362#define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f 1363#define DRV_MSG_CODE_MDUMP_ACK 0x01 /* acknowledge reception of error indication */ 1364#define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 /* set epoc and personality as follow: drv_data[3:0] - epoch, drv_data[7:4] - personality */ 1365#define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 /* trigger crash dump procedure */ 1366#define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 /* Request valid logs and config words */ 1367#define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 /* Set triggers mask. drv_mb_param should indicate (bitwise) which trigger enabled */ 1368#define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 /* Clear all logs */ 1369#define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07 /* Get retained data */ 1370#define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08 /* Clear retain data */ 1371#define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */ 1372#define DRV_MSG_CODE_GPIO_INFO 0x00270000 /* Param: [0:15] - gpio number */ 1373#define DRV_MSG_CODE_EXT_PHY_READ 0x00280000 /* Value will be placed in union */ 1374#define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000 /* Value shoud be placed in union */ 1375#define DRV_MB_PARAM_ADDR_OFFSET 0 1376#define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF 1377#define DRV_MB_PARAM_DEVAD_OFFSET 16 1378#define DRV_MB_PARAM_DEVAD_MASK 0x001F0000 1379#define DRV_MB_PARAM_PORT_OFFSET 21 1380#define DRV_MB_PARAM_PORT_MASK 0x00600000 1381#define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000 1382#define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000 1383#define DRV_MSG_CODE_SET_LLDP_MAC 0x002c0000 1384#define DRV_MSG_CODE_GET_LLDP_MAC 0x002d0000 1385#define DRV_MSG_CODE_OS_WOL 0x002e0000 1386 1387#define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 /* Param: None */ 1388#define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000 /* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */ 1389#define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000 /* return FW_MB_PARAM_FEATURE_SUPPORT_* */ 1390 1391#define DRV_MSG_CODE_READ_WOL_REG 0X00320000 1392#define DRV_MSG_CODE_WRITE_WOL_REG 0X00330000 1393#define DRV_MSG_CODE_GET_WOL_BUFFER 0X00340000 1394#define DRV_MSG_CODE_ATTRIBUTE 0x00350000 /* Param: [0:23] Attribute key, [24:31] Attribute sub command */ 1395 1396#define DRV_MSG_CODE_ENCRYPT_PASSWORD 0x00360000 /* Param: Password len. Union: Plain Password */ 1397#define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000 /* Param: None */ 1398 1399 /* Pmbus commands */ 1400#define DRV_MSG_CODE_PMBUS_READ 0x00380000 /* Param: [0:7] - Cmd, [8:9] - len */ 1401#define DRV_MSG_CODE_PMBUS_WRITE 0x00390000 /* Param: [0:7] - Cmd, [8:9] - len, [16:31] -data*/ 1402 1403#define DRV_MB_PARAM_PMBUS_CMD_OFFSET 0 1404#define DRV_MB_PARAM_PMBUS_CMD_MASK 0xFF 1405#define DRV_MB_PARAM_PMBUS_LEN_OFFSET 8 1406#define DRV_MB_PARAM_PMBUS_LEN_MASK 0x300 1407#define DRV_MB_PARAM_PMBUS_DATA_OFFSET 16 1408#define DRV_MB_PARAM_PMBUS_DATA_MASK 0xFFFF0000 1409 1410#define DRV_MSG_CODE_GENERIC_IDC 0x003a0000 1411 1412#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1413 1414 u32 drv_mb_param; 1415 /* UNLOAD_REQ params */ 1416#define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 1417#define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 1418#define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 1419#define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 1420 1421 /* UNLOAD_DONE_params */ 1422#define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001 1423 1424 /* INIT_PHY params */ 1425#define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001 1426#define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 1427 1428 /* LLDP / DCBX params*/ 1429 /* To be used with SET_LLDP command */ 1430#define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 1431#define DRV_MB_PARAM_LLDP_SEND_OFFSET 0 1432 /* To be used with SET_LLDP and REGISTER_LLDP_TLVS_RX commands */ 1433#define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 1434#define DRV_MB_PARAM_LLDP_AGENT_OFFSET 1 1435 /* To be used with REGISTER_LLDP_TLVS_RX command */ 1436#define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK 0x00000001 1437#define DRV_MB_PARAM_LLDP_TLV_RX_VALID_OFFSET 0 1438#define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK 0x000007f0 1439#define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_OFFSET 4 1440 /* To be used with SET_DCBX command */ 1441#define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008 1442#define DRV_MB_PARAM_DCBX_NOTIFY_OFFSET 3 1443 1444#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF 1445#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_OFFSET 0 1446 1447#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1 1448#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2 1449 1450#define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0 1451#define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF 1452#define DRV_MB_PARAM_NVM_LEN_OFFSET 24 1453#define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000 1454 1455#define DRV_MB_PARAM_PHY_ADDR_OFFSET 0 1456#define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF 1457#define DRV_MB_PARAM_PHY_LANE_OFFSET 16 1458#define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000 1459#define DRV_MB_PARAM_PHY_SELECT_PORT_OFFSET 29 1460#define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000 1461#define DRV_MB_PARAM_PHY_PORT_OFFSET 30 1462#define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000 1463 1464#define DRV_MB_PARAM_PHYMOD_LANE_OFFSET 0 1465#define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF 1466#define DRV_MB_PARAM_PHYMOD_SIZE_OFFSET 8 1467#define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00 1468 /* configure vf MSIX params BB */ 1469#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET 0 1470#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF 1471#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET 8 1472#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 1473 /* configure vf MSIX for PF params AH*/ 1474#define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_OFFSET 0 1475#define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_MASK 0x000000FF 1476 1477 /* OneView configuration parametres */ 1478#define DRV_MB_PARAM_OV_CURR_CFG_OFFSET 0 1479#define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F 1480#define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 1481#define DRV_MB_PARAM_OV_CURR_CFG_OS 1 1482#define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 1483#define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 1484#define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4 1485#define DRV_MB_PARAM_OV_CURR_CFG_CNU 5 1486#define DRV_MB_PARAM_OV_CURR_CFG_DCI 6 1487#define DRV_MB_PARAM_OV_CURR_CFG_HII 7 1488 1489#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OFFSET 0 1490#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF 1491#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0) 1492#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1) 1493#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1) 1494#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2) 1495#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3) 1496#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3) 1497#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4) 1498#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5) 1499#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6) 1500#define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0 1501 1502#define DRV_MB_PARAM_OV_PCI_BUS_NUM_OFFSET 0 1503#define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF 1504 1505#define DRV_MB_PARAM_OV_STORM_FW_VER_OFFSET 0 1506#define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF 1507#define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 1508#define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 1509#define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 1510#define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF 1511 1512#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_OFFSET 0 1513#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF 1514#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 1515#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 /* Not Installed*/ 1516#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 1517#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 /* installed but disabled by user/admin/OS */ 1518#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 /* installed and active */ 1519 1520#define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET 0 1521#define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF 1522 1523#define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \ 1524 DRV_MB_PARAM_WOL_DISABLED | \ 1525 DRV_MB_PARAM_WOL_ENABLED) 1526#define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP 1527#define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED 1528#define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED 1529 1530#define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \ 1531 DRV_MB_PARAM_ESWITCH_MODE_VEB | \ 1532 DRV_MB_PARAM_ESWITCH_MODE_VEPA) 1533#define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0 1534#define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1 1535#define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2 1536 1537#define DRV_MB_PARAM_FCOE_CVID_MASK 0xFFF 1538#define DRV_MB_PARAM_FCOE_CVID_OFFSET 0 1539 1540#define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1 1541#define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0 1542 1543#define DRV_MB_PARAM_LLDP_STATS_AGENT_MASK 0xFF 1544#define DRV_MB_PARAM_LLDP_STATS_AGENT_OFFSET 0 1545 1546#define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 1547#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 1548#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 1549 1550#define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0 1551#define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 1552#define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2 1553#define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC 1554#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8 1555#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00 1556#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16 1557#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000 1558 1559#define DRV_MB_PARAM_GPIO_NUMBER_OFFSET 0 1560#define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF 1561#define DRV_MB_PARAM_GPIO_VALUE_OFFSET 16 1562#define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000 1563#define DRV_MB_PARAM_GPIO_DIRECTION_OFFSET 16 1564#define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000 1565#define DRV_MB_PARAM_GPIO_CTRL_OFFSET 24 1566#define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000 1567 1568 /* Resource Allocation params - Driver version support*/ 1569#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1570#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16 1571#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1572#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0 1573 1574#define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0 1575#define DRV_MB_PARAM_BIST_REGISTER_TEST 1 1576#define DRV_MB_PARAM_BIST_CLOCK_TEST 2 1577#define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 1578#define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 1579 1580#define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 1581#define DRV_MB_PARAM_BIST_RC_PASSED 1 1582#define DRV_MB_PARAM_BIST_RC_FAILED 2 1583#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 1584 1585#define DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET 0 1586#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF 1587#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET 8 1588#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 1589 1590#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF 1591#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0 1592#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001 /* driver supports SmartLinQ parameter */ 1593#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 /* driver supports EEE parameter */ 1594#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK 0xFFFF0000 1595#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_OFFSET 16 1596#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 /* driver supports virtual link parameter */ 1597 /* Driver attributes params */ 1598#define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0 1599#define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00FFFFFF 1600#define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24 1601#define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF000000 1602 1603 u32 fw_mb_header; 1604#define FW_MSG_CODE_MASK 0xffff0000 1605#define FW_MSG_CODE_UNSUPPORTED 0x00000000 1606#define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 1607#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1608#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1609#define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 1610#define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000 1611#define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 1612#define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000 1613#define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000 1614#define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000 1615#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1616#define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 1617#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 1618#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 1619#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1620#define FW_MSG_CODE_INIT_PHY_DONE 0x21200000 1621#define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000 1622#define FW_MSG_CODE_LINK_RESET_DONE 0x23000000 1623#define FW_MSG_CODE_SET_LLDP_DONE 0x24000000 1624#define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000 1625#define FW_MSG_CODE_REGISTER_LLDP_TLVS_RX_DONE 0x24100000 1626#define FW_MSG_CODE_SET_DCBX_DONE 0x25000000 1627#define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000 1628#define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000 1629#define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000 1630#define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000 1631#define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000 1632#define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000 1633#define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000 1634#define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000 1635#define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 1636#define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 1637#define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000 1638#define FW_MSG_CODE_UPDATE_WOL_DONE 0x38000000 1639#define FW_MSG_CODE_UPDATE_ESWITCH_MODE_DONE 0x39000000 1640#define FW_MSG_CODE_UPDATE_ERR 0x3a010000 1641#define FW_MSG_CODE_UPDATE_PARAM_ERR 0x3a020000 1642#define FW_MSG_CODE_UPDATE_NOT_ALLOWED 0x3a030000 1643#define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000 1644#define FW_MSG_CODE_UPDATE_FCOE_CVID_DONE 0x3c000000 1645#define FW_MSG_CODE_UPDATE_FCOE_FABRIC_NAME_DONE 0x3d000000 1646#define FW_MSG_CODE_UPDATE_BOOT_CFG_DONE 0x3e000000 1647#define FW_MSG_CODE_RESET_TO_DEFAULT_ACK 0x3f000000 1648#define FW_MSG_CODE_OV_GET_CURR_CFG_DONE 0x40000000 1649#define FW_MSG_CODE_GET_OEM_UPDATES_DONE 0x41000000 1650#define FW_MSG_CODE_GET_LLDP_STATS_DONE 0x42000000 1651#define FW_MSG_CODE_GET_LLDP_STATS_ERROR 0x42010000 1652 1653#define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000 1654#define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1655#define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 1656#define FW_MSG_CODE_FLR_ACK 0x02000000 1657#define FW_MSG_CODE_FLR_NACK 0x02100000 1658#define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000 1659#define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000 1660#define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000 1661 1662#define FW_MSG_CODE_NVM_OK 0x00010000 1663#define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000 1664#define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000 1665#define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000 1666#define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000 1667#define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000 1668#define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000 1669#define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000 1670#define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000 1671#define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000 1672#define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000 1673#define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000 1674#define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000 1675#define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000 1676#define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000 1677#define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000 1678#define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000 1679#define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000 1680#define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000 1681#define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000 /* MFW reject "mcp reset" command if one of the drivers is up */ 1682#define FW_MSG_CODE_NVM_FAILED_CALC_HASH 0x00310000 1683#define FW_MSG_CODE_NVM_PUBLIC_KEY_MISSING 0x00320000 1684#define FW_MSG_CODE_NVM_INVALID_PUBLIC_KEY 0x00330000 1685 1686#define FW_MSG_CODE_PHY_OK 0x00110000 1687#define FW_MSG_CODE_PHY_ERROR 0x00120000 1688#define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000 1689#define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000 1690#define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000 1691#define FW_MSG_CODE_OK 0x00160000 1692#define FW_MSG_CODE_ERROR 0x00170000 1693#define FW_MSG_CODE_LED_MODE_INVALID 0x00170000 1694#define FW_MSG_CODE_PHY_DIAG_OK 0x00160000 1695#define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000 1696#define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000 1697#define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000 1698#define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000 1699#define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000 1700#define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000 1701#define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000 1702#define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000 1703#define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000 1704#define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000 1705#define FW_MSG_CODE_GPIO_OK 0x00160000 1706#define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000 1707#define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000 1708#define FW_MSG_CODE_GPIO_INVALID 0x000f0000 1709#define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000 1710#define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000 1711#define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER 0x00700000 1712#define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE 0x00710000 1713#define FW_MSG_CODE_EXTPHY_OPERATION_FAILED 0x00720000 1714#define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED 0x00730000 1715#define FW_MSG_CODE_RECOVERY_MODE 0x00740000 1716 1717 /* mdump related response codes */ 1718#define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000 1719#define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000 1720#define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000 1721#define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000 1722#define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000 1723 1724#define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000 1725#define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000 1726 1727#define FW_MSG_CODE_WOL_READ_WRITE_OK 0x00820000 1728#define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL 0x00830000 1729#define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR 0x00840000 1730#define FW_MSG_CODE_WOL_READ_BUFFER_OK 0x00850000 1731#define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000 1732 1733#define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000 1734#define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000 1735 1736#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1737 1738#define FW_MSG_CODE_ATTRIBUTE_INVALID_KEY 0x00020000 1739#define FW_MSG_CODE_ATTRIBUTE_INVALID_CMD 0x00030000 1740 1741#define FW_MSG_CODE_IDC_BUSY 0x00010000 1742 1743 u32 fw_mb_param; 1744/* Resource Allocation params - MFW version support */ 1745#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1746#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16 1747#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1748#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0 1749 1750/* get pf rdma protocol command response */ 1751#define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0 1752#define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1 1753#define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2 1754#define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3 1755 1756/* get MFW feature support response */ 1757#define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 /* MFW supports SmartLinQ */ 1758#define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 /* MFW supports EEE */ 1759#define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO 0x00000004 /* MFW supports DRV_LOAD Timeout */ 1760#define FW_MB_PARAM_FEATURE_SUPPORT_LP_PRES_DET 0x00000008 /* MFW supports early detection of LP Presence */ 1761#define FW_MB_PARAM_FEATURE_SUPPORT_RELAXED_ORD 0x00000010 /* MFW supports relaxed ordering setting */ 1762#define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000 /* MFW supports virtual link */ 1763 1764#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1<<0) 1765 1766#define FW_MB_PARAM_OEM_UPDATE_MASK 0xFF 1767#define FW_MB_PARAM_OEM_UPDATE_OFFSET 0 1768#define FW_MB_PARAM_OEM_UPDATE_BW 0x01 1769#define FW_MB_PARAM_OEM_UPDATE_S_TAG 0x02 1770#define FW_MB_PARAM_OEM_UPDATE_CFG 0x04 1771 1772#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001 1773#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_OFFSET 0 1774#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002 1775#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_OFFSET 1 1776#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004 1777#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_OFFSET 2 1778#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008 1779#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_OFFSET 3 1780 1781#define FW_MB_PARAM_PPFID_BITMAP_MASK 0xFF 1782#define FW_MB_PARAM_PPFID_BITMAP_OFFSET 0 1783 1784 u32 drv_pulse_mb; 1785#define DRV_PULSE_SEQ_MASK 0x00007fff 1786#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1787 /* 1788 * The system time is in the format of 1789 * (year-2001)*12*32 + month*32 + day. 1790 */ 1791#define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1792 /* 1793 * Indicate to the firmware not to go into the 1794 * OS-absent when it is not getting driver pulse. 1795 * This is used for debugging as well for PXE(MBA). 1796 */ 1797 1798 u32 mcp_pulse_mb; 1799#define MCP_PULSE_SEQ_MASK 0x00007fff 1800#define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1801 /* Indicates to the driver not to assert due to lack 1802 * of MCP response */ 1803#define MCP_EVENT_MASK 0xffff0000 1804#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1805 1806 /* The union data is used by the driver to pass parameters to the scratchpad. */ 1807 union drv_union_data union_data; 1808 1809}; 1810 1811/* MFW - DRV MB */ 1812/********************************************************************** 1813 * Description 1814 * Incremental Aggregative 1815 * 8-bit MFW counter per message 1816 * 8-bit ack-counter per message 1817 * Capabilities 1818 * Provides up to 256 aggregative message per type 1819 * Provides 4 message types in dword 1820 * Message type pointers to byte offset 1821 * Backward Compatibility by using sizeof for the counters. 1822 * No lock requires for 32bit messages 1823 * Limitations: 1824 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock) 1825 * is required to prevent data corruption. 1826 **********************************************************************/ 1827enum MFW_DRV_MSG_TYPE { 1828 MFW_DRV_MSG_LINK_CHANGE, 1829 MFW_DRV_MSG_FLR_FW_ACK_FAILED, 1830 MFW_DRV_MSG_VF_DISABLED, 1831 MFW_DRV_MSG_LLDP_DATA_UPDATED, 1832 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, 1833 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, 1834 MFW_DRV_MSG_ERROR_RECOVERY, 1835 MFW_DRV_MSG_BW_UPDATE, 1836 MFW_DRV_MSG_S_TAG_UPDATE, 1837 MFW_DRV_MSG_GET_LAN_STATS, 1838 MFW_DRV_MSG_GET_FCOE_STATS, 1839 MFW_DRV_MSG_GET_ISCSI_STATS, 1840 MFW_DRV_MSG_GET_RDMA_STATS, 1841 MFW_DRV_MSG_FAILURE_DETECTED, 1842 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, 1843 MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, 1844 MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE, 1845 MFW_DRV_MSG_GET_TLV_REQ, 1846 MFW_DRV_MSG_OEM_CFG_UPDATE, 1847 MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED, 1848 MFW_DRV_MSG_GENERIC_IDC, /* Generic Inter Driver Communication message */ 1849 MFW_DRV_MSG_MAX 1850}; 1851 1852#define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) 1853#define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) 1854#define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) 1855#define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) 1856 1857#ifdef BIG_ENDIAN /* Like MFW */ 1858#define DRV_ACK_MSG(msg_p, msg_id) (u8)((u8*)msg_p)[msg_id]++; 1859#else 1860#define DRV_ACK_MSG(msg_p, msg_id) (u8)((u8*)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++; 1861#endif 1862 1863#define MFW_DRV_UPDATE(shmem_func, msg_id) (u8)((u8*)(MFW_MB_P(shmem_func)->msg))[msg_id]++; 1864 1865struct public_mfw_mb { 1866 u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */ 1867 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; /* Incremented by the MFW */ 1868 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; /* Incremented by the driver */ 1869}; 1870 1871/**************************************/ 1872/* */ 1873/* P U B L I C D A T A */ 1874/* */ 1875/**************************************/ 1876enum public_sections { 1877 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */ 1878 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */ 1879 PUBLIC_GLOBAL, 1880 PUBLIC_PATH, 1881 PUBLIC_PORT, 1882 PUBLIC_FUNC, 1883 PUBLIC_MAX_SECTIONS 1884}; 1885 1886struct drv_ver_info_stc { 1887 u32 ver; 1888 u8 name[32]; 1889}; 1890 1891/* Runtime data needs about 1/2K. We use 2K to be on the safe side. 1892 * Please make sure data does not exceed this size. 1893 */ 1894#define NUM_RUNTIME_DWORDS 16 1895struct drv_init_hw_stc { 1896 u32 init_hw_bitmask[NUM_RUNTIME_DWORDS]; 1897 u32 init_hw_data[NUM_RUNTIME_DWORDS * 32]; 1898}; 1899 1900struct mcp_public_data { 1901 /* The sections fields is an array */ 1902 u32 num_sections; 1903 offsize_t sections[PUBLIC_MAX_SECTIONS]; 1904 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; 1905 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; 1906 struct public_global global; 1907 struct public_path path[MCP_GLOB_PATH_MAX]; 1908 struct public_port port[MCP_GLOB_PORT_MAX]; 1909 struct public_func func[MCP_GLOB_FUNC_MAX]; 1910}; 1911 1912#define I2C_TRANSCEIVER_ADDR 0xa0 1913#define MAX_I2C_TRANSACTION_SIZE 16 1914#define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256 1915 1916/* OCBB definitions */ 1917enum tlvs { 1918 /* Category 1: Device Properties */ 1919 DRV_TLV_CLP_STR, 1920 DRV_TLV_CLP_STR_CTD, 1921 /* Category 6: Device Configuration */ 1922 DRV_TLV_SCSI_TO, 1923 DRV_TLV_R_T_TOV, 1924 DRV_TLV_R_A_TOV, 1925 DRV_TLV_E_D_TOV, 1926 DRV_TLV_CR_TOV, 1927 DRV_TLV_BOOT_TYPE, 1928 /* Category 8: Port Configuration */ 1929 DRV_TLV_NPIV_ENABLED, 1930 /* Category 10: Function Configuration */ 1931 DRV_TLV_FEATURE_FLAGS, 1932 DRV_TLV_LOCAL_ADMIN_ADDR, 1933 DRV_TLV_ADDITIONAL_MAC_ADDR_1, 1934 DRV_TLV_ADDITIONAL_MAC_ADDR_2, 1935 DRV_TLV_LSO_MAX_OFFLOAD_SIZE, 1936 DRV_TLV_LSO_MIN_SEGMENT_COUNT, 1937 DRV_TLV_PROMISCUOUS_MODE, 1938 DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE, 1939 DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE, 1940 DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG, 1941 DRV_TLV_FLEX_NIC_OUTER_VLAN_ID, 1942 DRV_TLV_OS_DRIVER_STATES, 1943 DRV_TLV_PXE_BOOT_PROGRESS, 1944 /* Category 12: FC/FCoE Configuration */ 1945 DRV_TLV_NPIV_STATE, 1946 DRV_TLV_NUM_OF_NPIV_IDS, 1947 DRV_TLV_SWITCH_NAME, 1948 DRV_TLV_SWITCH_PORT_NUM, 1949 DRV_TLV_SWITCH_PORT_ID, 1950 DRV_TLV_VENDOR_NAME, 1951 DRV_TLV_SWITCH_MODEL, 1952 DRV_TLV_SWITCH_FW_VER, 1953 DRV_TLV_QOS_PRIORITY_PER_802_1P, 1954 DRV_TLV_PORT_ALIAS, 1955 DRV_TLV_PORT_STATE, 1956 DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE, 1957 DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE, 1958 DRV_TLV_LINK_FAILURE_COUNT, 1959 DRV_TLV_FCOE_BOOT_PROGRESS, 1960 /* Category 13: iSCSI Configuration */ 1961 DRV_TLV_TARGET_LLMNR_ENABLED, 1962 DRV_TLV_HEADER_DIGEST_FLAG_ENABLED, 1963 DRV_TLV_DATA_DIGEST_FLAG_ENABLED, 1964 DRV_TLV_AUTHENTICATION_METHOD, 1965 DRV_TLV_ISCSI_BOOT_TARGET_PORTAL, 1966 DRV_TLV_MAX_FRAME_SIZE, 1967 DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE, 1968 DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE, 1969 DRV_TLV_ISCSI_BOOT_PROGRESS, 1970 /* Category 20: Device Data */ 1971 DRV_TLV_PCIE_BUS_RX_UTILIZATION, 1972 DRV_TLV_PCIE_BUS_TX_UTILIZATION, 1973 DRV_TLV_DEVICE_CPU_CORES_UTILIZATION, 1974 DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED, 1975 DRV_TLV_NCSI_RX_BYTES_RECEIVED, 1976 DRV_TLV_NCSI_TX_BYTES_SENT, 1977 /* Category 22: Base Port Data */ 1978 DRV_TLV_RX_DISCARDS, 1979 DRV_TLV_RX_ERRORS, 1980 DRV_TLV_TX_ERRORS, 1981 DRV_TLV_TX_DISCARDS, 1982 DRV_TLV_RX_FRAMES_RECEIVED, 1983 DRV_TLV_TX_FRAMES_SENT, 1984 /* Category 23: FC/FCoE Port Data */ 1985 DRV_TLV_RX_BROADCAST_PACKETS, 1986 DRV_TLV_TX_BROADCAST_PACKETS, 1987 /* Category 28: Base Function Data */ 1988 DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4, 1989 DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6, 1990 DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 1991 DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 1992 DRV_TLV_PF_RX_FRAMES_RECEIVED, 1993 DRV_TLV_RX_BYTES_RECEIVED, 1994 DRV_TLV_PF_TX_FRAMES_SENT, 1995 DRV_TLV_TX_BYTES_SENT, 1996 DRV_TLV_IOV_OFFLOAD, 1997 DRV_TLV_PCI_ERRORS_CAP_ID, 1998 DRV_TLV_UNCORRECTABLE_ERROR_STATUS, 1999 DRV_TLV_UNCORRECTABLE_ERROR_MASK, 2000 DRV_TLV_CORRECTABLE_ERROR_STATUS, 2001 DRV_TLV_CORRECTABLE_ERROR_MASK, 2002 DRV_TLV_PCI_ERRORS_AECC_REGISTER, 2003 DRV_TLV_TX_QUEUES_EMPTY, 2004 DRV_TLV_RX_QUEUES_EMPTY, 2005 DRV_TLV_TX_QUEUES_FULL, 2006 DRV_TLV_RX_QUEUES_FULL, 2007 /* Category 29: FC/FCoE Function Data */ 2008 DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 2009 DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 2010 DRV_TLV_FCOE_RX_FRAMES_RECEIVED, 2011 DRV_TLV_FCOE_RX_BYTES_RECEIVED, 2012 DRV_TLV_FCOE_TX_FRAMES_SENT, 2013 DRV_TLV_FCOE_TX_BYTES_SENT, 2014 DRV_TLV_CRC_ERROR_COUNT, 2015 DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID, 2016 DRV_TLV_CRC_ERROR_1_TIMESTAMP, 2017 DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID, 2018 DRV_TLV_CRC_ERROR_2_TIMESTAMP, 2019 DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID, 2020 DRV_TLV_CRC_ERROR_3_TIMESTAMP, 2021 DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID, 2022 DRV_TLV_CRC_ERROR_4_TIMESTAMP, 2023 DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID, 2024 DRV_TLV_CRC_ERROR_5_TIMESTAMP, 2025 DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT, 2026 DRV_TLV_LOSS_OF_SIGNAL_ERRORS, 2027 DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT, 2028 DRV_TLV_DISPARITY_ERROR_COUNT, 2029 DRV_TLV_CODE_VIOLATION_ERROR_COUNT, 2030 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1, 2031 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2, 2032 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3, 2033 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4, 2034 DRV_TLV_LAST_FLOGI_TIMESTAMP, 2035 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1, 2036 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2, 2037 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3, 2038 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4, 2039 DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP, 2040 DRV_TLV_LAST_FLOGI_RJT, 2041 DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP, 2042 DRV_TLV_FDISCS_SENT_COUNT, 2043 DRV_TLV_FDISC_ACCS_RECEIVED, 2044 DRV_TLV_FDISC_RJTS_RECEIVED, 2045 DRV_TLV_PLOGI_SENT_COUNT, 2046 DRV_TLV_PLOGI_ACCS_RECEIVED, 2047 DRV_TLV_PLOGI_RJTS_RECEIVED, 2048 DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID, 2049 DRV_TLV_PLOGI_1_TIMESTAMP, 2050 DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID, 2051 DRV_TLV_PLOGI_2_TIMESTAMP, 2052 DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID, 2053 DRV_TLV_PLOGI_3_TIMESTAMP, 2054 DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID, 2055 DRV_TLV_PLOGI_4_TIMESTAMP, 2056 DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID, 2057 DRV_TLV_PLOGI_5_TIMESTAMP, 2058 DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID, 2059 DRV_TLV_PLOGI_1_ACC_TIMESTAMP, 2060 DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID, 2061 DRV_TLV_PLOGI_2_ACC_TIMESTAMP, 2062 DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID, 2063 DRV_TLV_PLOGI_3_ACC_TIMESTAMP, 2064 DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID, 2065 DRV_TLV_PLOGI_4_ACC_TIMESTAMP, 2066 DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID, 2067 DRV_TLV_PLOGI_5_ACC_TIMESTAMP, 2068 DRV_TLV_LOGOS_ISSUED, 2069 DRV_TLV_LOGO_ACCS_RECEIVED, 2070 DRV_TLV_LOGO_RJTS_RECEIVED, 2071 DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID, 2072 DRV_TLV_LOGO_1_TIMESTAMP, 2073 DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID, 2074 DRV_TLV_LOGO_2_TIMESTAMP, 2075 DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID, 2076 DRV_TLV_LOGO_3_TIMESTAMP, 2077 DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID, 2078 DRV_TLV_LOGO_4_TIMESTAMP, 2079 DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID, 2080 DRV_TLV_LOGO_5_TIMESTAMP, 2081 DRV_TLV_LOGOS_RECEIVED, 2082 DRV_TLV_ACCS_ISSUED, 2083 DRV_TLV_PRLIS_ISSUED, 2084 DRV_TLV_ACCS_RECEIVED, 2085 DRV_TLV_ABTS_SENT_COUNT, 2086 DRV_TLV_ABTS_ACCS_RECEIVED, 2087 DRV_TLV_ABTS_RJTS_RECEIVED, 2088 DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID, 2089 DRV_TLV_ABTS_1_TIMESTAMP, 2090 DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID, 2091 DRV_TLV_ABTS_2_TIMESTAMP, 2092 DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID, 2093 DRV_TLV_ABTS_3_TIMESTAMP, 2094 DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID, 2095 DRV_TLV_ABTS_4_TIMESTAMP, 2096 DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID, 2097 DRV_TLV_ABTS_5_TIMESTAMP, 2098 DRV_TLV_RSCNS_RECEIVED, 2099 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1, 2100 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2, 2101 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3, 2102 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4, 2103 DRV_TLV_LUN_RESETS_ISSUED, 2104 DRV_TLV_ABORT_TASK_SETS_ISSUED, 2105 DRV_TLV_TPRLOS_SENT, 2106 DRV_TLV_NOS_SENT_COUNT, 2107 DRV_TLV_NOS_RECEIVED_COUNT, 2108 DRV_TLV_OLS_COUNT, 2109 DRV_TLV_LR_COUNT, 2110 DRV_TLV_LRR_COUNT, 2111 DRV_TLV_LIP_SENT_COUNT, 2112 DRV_TLV_LIP_RECEIVED_COUNT, 2113 DRV_TLV_EOFA_COUNT, 2114 DRV_TLV_EOFNI_COUNT, 2115 DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT, 2116 DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT, 2117 DRV_TLV_SCSI_STATUS_BUSY_COUNT, 2118 DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT, 2119 DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT, 2120 DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT, 2121 DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT, 2122 DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT, 2123 DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT, 2124 DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ, 2125 DRV_TLV_SCSI_CHECK_1_TIMESTAMP, 2126 DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ, 2127 DRV_TLV_SCSI_CHECK_2_TIMESTAMP, 2128 DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ, 2129 DRV_TLV_SCSI_CHECK_3_TIMESTAMP, 2130 DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ, 2131 DRV_TLV_SCSI_CHECK_4_TIMESTAMP, 2132 DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ, 2133 DRV_TLV_SCSI_CHECK_5_TIMESTAMP, 2134 /* Category 30: iSCSI Function Data */ 2135 DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 2136 DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 2137 DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED, 2138 DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED, 2139 DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT, 2140 DRV_TLV_ISCSI_PDU_TX_BYTES_SENT 2141}; 2142 2143#define I2C_DEV_ADDR_A2 0xa2 2144#define SFP_EEPROM_A2_TEMPERATURE_ADDR 0x60 2145#define SFP_EEPROM_A2_TEMPERATURE_SIZE 2 2146#define SFP_EEPROM_A2_VCC_ADDR 0x62 2147#define SFP_EEPROM_A2_VCC_SIZE 2 2148#define SFP_EEPROM_A2_TX_BIAS_ADDR 0x64 2149#define SFP_EEPROM_A2_TX_BIAS_SIZE 2 2150#define SFP_EEPROM_A2_TX_POWER_ADDR 0x66 2151#define SFP_EEPROM_A2_TX_POWER_SIZE 2 2152#define SFP_EEPROM_A2_RX_POWER_ADDR 0x68 2153#define SFP_EEPROM_A2_RX_POWER_SIZE 2 2154 2155#define I2C_DEV_ADDR_A0 0xa0 2156#define QSFP_EEPROM_A0_TEMPERATURE_ADDR 0x16 2157#define QSFP_EEPROM_A0_TEMPERATURE_SIZE 2 2158#define QSFP_EEPROM_A0_VCC_ADDR 0x1a 2159#define QSFP_EEPROM_A0_VCC_SIZE 2 2160#define QSFP_EEPROM_A0_TX1_BIAS_ADDR 0x2a 2161#define QSFP_EEPROM_A0_TX1_BIAS_SIZE 2 2162#define QSFP_EEPROM_A0_TX1_POWER_ADDR 0x32 2163#define QSFP_EEPROM_A0_TX1_POWER_SIZE 2 2164#define QSFP_EEPROM_A0_RX1_POWER_ADDR 0x22 2165#define QSFP_EEPROM_A0_RX1_POWER_SIZE 2 2166 2167/************************************** 2168 * eDiag NETWORK Mode (DON) 2169 **************************************/ 2170 2171#define ETH_DON_TYPE 0x0911 /* NETWORK Mode for QeDiag */ 2172#define ETH_DON_TRACE_TYPE 0x0912 /* NETWORK Mode Continous Trace */ 2173 2174#define DON_RESP_UNKNOWN_CMD_ID 0x10 /* Response Error */ 2175 2176/* Op Codes, Response is Op Code+1 */ 2177 2178#define DON_REG_READ_REQ_CMD_ID 0x11 2179#define DON_REG_WRITE_REQ_CMD_ID 0x22 2180#define DON_CHALLENGE_REQ_CMD_ID 0x33 2181#define DON_NVM_READ_REQ_CMD_ID 0x44 2182#define DON_BLOCK_READ_REQ_CMD_ID 0x55 2183 2184#define DON_MFW_MODE_TRACE_CONTINUOUS_ID 0x70 2185 2186#if defined(MFW) || defined(DIAG) || defined(WINEDIAG) 2187 2188#ifndef UEFI 2189#if defined(_MSC_VER) 2190#pragma pack(push,1) 2191#else 2192#pragma pack(1) 2193#endif 2194#endif 2195 2196typedef struct { 2197 u8 dst_addr[6]; 2198 u8 src_addr[6]; 2199 u16 ether_type; 2200 2201 /* DON Message data starts here, after L2 header */ 2202 /* Do not change alignment to keep backward compatability */ 2203 u16 cmd_id; /* Op code and response code */ 2204 2205 union { 2206 struct { /* DON Commands */ 2207 u32 address; 2208 u32 val; 2209 u32 resp_status; 2210 }; 2211 struct { /* DON Traces */ 2212 u16 mcp_clock; /* MCP Clock in MHz */ 2213 u16 trace_size; /* Trace size in bytes */ 2214 2215 u32 seconds; /* Seconds since last reset */ 2216 u32 ticks; /* Timestamp (NOW) */ 2217 }; 2218 }; 2219 union { 2220 u8 digest[32]; /* SHA256 */ 2221 u8 data[32]; 2222 /* u32 dword[8]; */ 2223 }; 2224} don_packet_t; 2225 2226#ifndef UEFI 2227#if defined(_MSC_VER) 2228#pragma pack(pop) 2229#else 2230#pragma pack(0) 2231#endif 2232#endif /* #ifndef UEFI */ 2233 2234#endif /* #if defined(MFW) || defined(DIAG) || defined(WINEDIAG) */ 2235 2236#endif /* MCP_PUBLIC_H */ 2237