1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31#ifndef __RT_DEFS_H__ 32#define __RT_DEFS_H__ 33 34/* Runtime array offsets */ 35#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0 36#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1 37#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2 38#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3 39#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4 40#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5 41#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6 42#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7 43#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8 44#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9 45#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10 46#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11 47#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12 48#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13 49#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14 50#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15 51#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16 52#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17 53#define DORQ_REG_GLB_MAX_ICID_0_RT_OFFSET 18 54#define DORQ_REG_GLB_MAX_ICID_1_RT_OFFSET 19 55#define DORQ_REG_GLB_RANGE2CONN_TYPE_0_RT_OFFSET 20 56#define DORQ_REG_GLB_RANGE2CONN_TYPE_1_RT_OFFSET 21 57#define DORQ_REG_PRV_PF_MAX_ICID_2_RT_OFFSET 22 58#define DORQ_REG_PRV_PF_MAX_ICID_3_RT_OFFSET 23 59#define DORQ_REG_PRV_PF_MAX_ICID_4_RT_OFFSET 24 60#define DORQ_REG_PRV_PF_MAX_ICID_5_RT_OFFSET 25 61#define DORQ_REG_PRV_VF_MAX_ICID_2_RT_OFFSET 26 62#define DORQ_REG_PRV_VF_MAX_ICID_3_RT_OFFSET 27 63#define DORQ_REG_PRV_VF_MAX_ICID_4_RT_OFFSET 28 64#define DORQ_REG_PRV_VF_MAX_ICID_5_RT_OFFSET 29 65#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_RT_OFFSET 30 66#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_RT_OFFSET 31 67#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_RT_OFFSET 32 68#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_RT_OFFSET 33 69#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_RT_OFFSET 34 70#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_RT_OFFSET 35 71#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_RT_OFFSET 36 72#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_RT_OFFSET 37 73#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 38 74#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 39 75#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 40 76#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 41 77#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 42 78#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 43 79#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 44 80#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 45 81#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 1024 82#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1069 83#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 1024 84#define CAU_REG_PI_MEMORY_RT_OFFSET 2093 85#define CAU_REG_PI_MEMORY_RT_SIZE 4416 86#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6509 87#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6510 88#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6511 89#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6512 90#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6513 91#define PRS_REG_SEARCH_TCP_RT_OFFSET 6514 92#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6515 93#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6516 94#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6517 95#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6518 96#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6519 97#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6520 98#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6521 99#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6522 100#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6523 101#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6524 102#define SRC_REG_FIRSTFREE_RT_OFFSET 6525 103#define SRC_REG_FIRSTFREE_RT_SIZE 2 104#define SRC_REG_LASTFREE_RT_OFFSET 6527 105#define SRC_REG_LASTFREE_RT_SIZE 2 106#define SRC_REG_COUNTFREE_RT_OFFSET 6529 107#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6530 108#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6531 109#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6532 110#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6533 111#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6534 112#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6535 113#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6536 114#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6537 115#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6538 116#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6539 117#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6540 118#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6541 119#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6542 120#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6543 121#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6544 122#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6545 123#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6546 124#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6547 125#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6548 126#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6549 127#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6550 128#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6551 129#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6552 130#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6553 131#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6554 132#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6555 133#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6556 134#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6557 135#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6558 136#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6559 137#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6560 138#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6561 139#define PSWRQ2_REG_TGSRC_FIRST_ILT_RT_OFFSET 6562 140#define PSWRQ2_REG_RGSRC_FIRST_ILT_RT_OFFSET 6563 141#define PSWRQ2_REG_TGSRC_LAST_ILT_RT_OFFSET 6564 142#define PSWRQ2_REG_RGSRC_LAST_ILT_RT_OFFSET 6565 143#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6566 144#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 26414 145#define PGLUE_REG_B_VF_BASE_RT_OFFSET 32980 146#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 32981 147#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 32982 148#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 32983 149#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 32984 150#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 32985 151#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 32986 152#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 32987 153#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 32988 154#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 32989 155#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 32990 156#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 32991 157#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 32992 158#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416 159#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 33408 160#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608 161#define QM_REG_MAXPQSIZE_0_RT_OFFSET 34016 162#define QM_REG_MAXPQSIZE_1_RT_OFFSET 34017 163#define QM_REG_MAXPQSIZE_2_RT_OFFSET 34018 164#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 34019 165#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 34020 166#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 34021 167#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 34022 168#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 34023 169#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 34024 170#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 34025 171#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 34026 172#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 34027 173#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 34028 174#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 34029 175#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 34030 176#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 34031 177#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 34032 178#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 34033 179#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 34034 180#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 34035 181#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 34036 182#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 34037 183#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 34038 184#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 34039 185#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 34040 186#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 34041 187#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 34042 188#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 34043 189#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 34044 190#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 34045 191#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 34046 192#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 34047 193#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 34048 194#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 34049 195#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 34050 196#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 34051 197#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 34052 198#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 34053 199#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 34054 200#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 34055 201#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 34056 202#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 34057 203#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 34058 204#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 34059 205#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 34060 206#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 34061 207#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 34062 208#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 34063 209#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 34064 210#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 34065 211#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 34066 212#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 34067 213#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 34068 214#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 34069 215#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 34070 216#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 34071 217#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 34072 218#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 34073 219#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 34074 220#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 34075 221#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 34076 222#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 34077 223#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 34078 224#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 34079 225#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 34080 226#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 34081 227#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 34082 228#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 34083 229#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 230#define QM_REG_PTRTBLOTHER_RT_OFFSET 34211 231#define QM_REG_PTRTBLOTHER_RT_SIZE 256 232#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 34467 233#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 34468 234#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 34469 235#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 34470 236#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 34471 237#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 34472 238#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 34473 239#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 34474 240#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 34475 241#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 34476 242#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 34477 243#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 34478 244#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 34479 245#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 34480 246#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 34481 247#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 34482 248#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 34483 249#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 34484 250#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 34485 251#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 34486 252#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 34487 253#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 34488 254#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 34489 255#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 34490 256#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 34491 257#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 34492 258#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 34493 259#define QM_REG_PQTX2PF_0_RT_OFFSET 34494 260#define QM_REG_PQTX2PF_1_RT_OFFSET 34495 261#define QM_REG_PQTX2PF_2_RT_OFFSET 34496 262#define QM_REG_PQTX2PF_3_RT_OFFSET 34497 263#define QM_REG_PQTX2PF_4_RT_OFFSET 34498 264#define QM_REG_PQTX2PF_5_RT_OFFSET 34499 265#define QM_REG_PQTX2PF_6_RT_OFFSET 34500 266#define QM_REG_PQTX2PF_7_RT_OFFSET 34501 267#define QM_REG_PQTX2PF_8_RT_OFFSET 34502 268#define QM_REG_PQTX2PF_9_RT_OFFSET 34503 269#define QM_REG_PQTX2PF_10_RT_OFFSET 34504 270#define QM_REG_PQTX2PF_11_RT_OFFSET 34505 271#define QM_REG_PQTX2PF_12_RT_OFFSET 34506 272#define QM_REG_PQTX2PF_13_RT_OFFSET 34507 273#define QM_REG_PQTX2PF_14_RT_OFFSET 34508 274#define QM_REG_PQTX2PF_15_RT_OFFSET 34509 275#define QM_REG_PQTX2PF_16_RT_OFFSET 34510 276#define QM_REG_PQTX2PF_17_RT_OFFSET 34511 277#define QM_REG_PQTX2PF_18_RT_OFFSET 34512 278#define QM_REG_PQTX2PF_19_RT_OFFSET 34513 279#define QM_REG_PQTX2PF_20_RT_OFFSET 34514 280#define QM_REG_PQTX2PF_21_RT_OFFSET 34515 281#define QM_REG_PQTX2PF_22_RT_OFFSET 34516 282#define QM_REG_PQTX2PF_23_RT_OFFSET 34517 283#define QM_REG_PQTX2PF_24_RT_OFFSET 34518 284#define QM_REG_PQTX2PF_25_RT_OFFSET 34519 285#define QM_REG_PQTX2PF_26_RT_OFFSET 34520 286#define QM_REG_PQTX2PF_27_RT_OFFSET 34521 287#define QM_REG_PQTX2PF_28_RT_OFFSET 34522 288#define QM_REG_PQTX2PF_29_RT_OFFSET 34523 289#define QM_REG_PQTX2PF_30_RT_OFFSET 34524 290#define QM_REG_PQTX2PF_31_RT_OFFSET 34525 291#define QM_REG_PQTX2PF_32_RT_OFFSET 34526 292#define QM_REG_PQTX2PF_33_RT_OFFSET 34527 293#define QM_REG_PQTX2PF_34_RT_OFFSET 34528 294#define QM_REG_PQTX2PF_35_RT_OFFSET 34529 295#define QM_REG_PQTX2PF_36_RT_OFFSET 34530 296#define QM_REG_PQTX2PF_37_RT_OFFSET 34531 297#define QM_REG_PQTX2PF_38_RT_OFFSET 34532 298#define QM_REG_PQTX2PF_39_RT_OFFSET 34533 299#define QM_REG_PQTX2PF_40_RT_OFFSET 34534 300#define QM_REG_PQTX2PF_41_RT_OFFSET 34535 301#define QM_REG_PQTX2PF_42_RT_OFFSET 34536 302#define QM_REG_PQTX2PF_43_RT_OFFSET 34537 303#define QM_REG_PQTX2PF_44_RT_OFFSET 34538 304#define QM_REG_PQTX2PF_45_RT_OFFSET 34539 305#define QM_REG_PQTX2PF_46_RT_OFFSET 34540 306#define QM_REG_PQTX2PF_47_RT_OFFSET 34541 307#define QM_REG_PQTX2PF_48_RT_OFFSET 34542 308#define QM_REG_PQTX2PF_49_RT_OFFSET 34543 309#define QM_REG_PQTX2PF_50_RT_OFFSET 34544 310#define QM_REG_PQTX2PF_51_RT_OFFSET 34545 311#define QM_REG_PQTX2PF_52_RT_OFFSET 34546 312#define QM_REG_PQTX2PF_53_RT_OFFSET 34547 313#define QM_REG_PQTX2PF_54_RT_OFFSET 34548 314#define QM_REG_PQTX2PF_55_RT_OFFSET 34549 315#define QM_REG_PQTX2PF_56_RT_OFFSET 34550 316#define QM_REG_PQTX2PF_57_RT_OFFSET 34551 317#define QM_REG_PQTX2PF_58_RT_OFFSET 34552 318#define QM_REG_PQTX2PF_59_RT_OFFSET 34553 319#define QM_REG_PQTX2PF_60_RT_OFFSET 34554 320#define QM_REG_PQTX2PF_61_RT_OFFSET 34555 321#define QM_REG_PQTX2PF_62_RT_OFFSET 34556 322#define QM_REG_PQTX2PF_63_RT_OFFSET 34557 323#define QM_REG_PQOTHER2PF_0_RT_OFFSET 34558 324#define QM_REG_PQOTHER2PF_1_RT_OFFSET 34559 325#define QM_REG_PQOTHER2PF_2_RT_OFFSET 34560 326#define QM_REG_PQOTHER2PF_3_RT_OFFSET 34561 327#define QM_REG_PQOTHER2PF_4_RT_OFFSET 34562 328#define QM_REG_PQOTHER2PF_5_RT_OFFSET 34563 329#define QM_REG_PQOTHER2PF_6_RT_OFFSET 34564 330#define QM_REG_PQOTHER2PF_7_RT_OFFSET 34565 331#define QM_REG_PQOTHER2PF_8_RT_OFFSET 34566 332#define QM_REG_PQOTHER2PF_9_RT_OFFSET 34567 333#define QM_REG_PQOTHER2PF_10_RT_OFFSET 34568 334#define QM_REG_PQOTHER2PF_11_RT_OFFSET 34569 335#define QM_REG_PQOTHER2PF_12_RT_OFFSET 34570 336#define QM_REG_PQOTHER2PF_13_RT_OFFSET 34571 337#define QM_REG_PQOTHER2PF_14_RT_OFFSET 34572 338#define QM_REG_PQOTHER2PF_15_RT_OFFSET 34573 339#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 34574 340#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 34575 341#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 34576 342#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 34577 343#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 34578 344#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 34579 345#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 34580 346#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 34581 347#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 34582 348#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 34583 349#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 34584 350#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 34585 351#define QM_REG_RLGLBLINCVAL_RT_OFFSET 34586 352#define QM_REG_RLGLBLINCVAL_RT_SIZE 256 353#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 34842 354#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 355#define QM_REG_RLGLBLCRD_RT_OFFSET 35098 356#define QM_REG_RLGLBLCRD_RT_SIZE 256 357#define QM_REG_RLGLBLENABLE_RT_OFFSET 35354 358#define QM_REG_RLPFPERIOD_RT_OFFSET 35355 359#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 35356 360#define QM_REG_RLPFINCVAL_RT_OFFSET 35357 361#define QM_REG_RLPFINCVAL_RT_SIZE 16 362#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 35373 363#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 364#define QM_REG_RLPFCRD_RT_OFFSET 35389 365#define QM_REG_RLPFCRD_RT_SIZE 16 366#define QM_REG_RLPFENABLE_RT_OFFSET 35405 367#define QM_REG_RLPFVOQENABLE_RT_OFFSET 35406 368#define QM_REG_WFQPFWEIGHT_RT_OFFSET 35407 369#define QM_REG_WFQPFWEIGHT_RT_SIZE 16 370#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 35423 371#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 372#define QM_REG_WFQPFCRD_RT_OFFSET 35439 373#define QM_REG_WFQPFCRD_RT_SIZE 256 374#define QM_REG_WFQPFENABLE_RT_OFFSET 35695 375#define QM_REG_WFQVPENABLE_RT_OFFSET 35696 376#define QM_REG_BASEADDRTXPQ_RT_OFFSET 35697 377#define QM_REG_BASEADDRTXPQ_RT_SIZE 512 378#define QM_REG_TXPQMAP_RT_OFFSET 36209 379#define QM_REG_TXPQMAP_RT_SIZE 512 380#define QM_REG_WFQVPWEIGHT_RT_OFFSET 36721 381#define QM_REG_WFQVPWEIGHT_RT_SIZE 512 382#define QM_REG_WFQVPCRD_RT_OFFSET 37233 383#define QM_REG_WFQVPCRD_RT_SIZE 512 384#define QM_REG_WFQVPMAP_RT_OFFSET 37745 385#define QM_REG_WFQVPMAP_RT_SIZE 512 386#define QM_REG_PTRTBLTX_RT_OFFSET 38257 387#define QM_REG_PTRTBLTX_RT_SIZE 1024 388#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 39281 389#define QM_REG_WFQPFCRD_MSB_RT_SIZE 320 390#define QM_REG_VOQCRDLINE_RT_OFFSET 39601 391#define QM_REG_VOQCRDLINE_RT_SIZE 36 392#define QM_REG_VOQINITCRDLINE_RT_OFFSET 39637 393#define QM_REG_VOQINITCRDLINE_RT_SIZE 36 394#define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET 39673 395#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 39674 396#define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 39675 397#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 39676 398#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 39677 399#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 39678 400#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 39679 401#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 39680 402#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 39681 403#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 404#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 39685 405#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 406#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 39689 407#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 408#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 39721 409#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 410#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 39737 411#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 412#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 39753 413#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 414#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 39769 415#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 416#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 39785 417#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 39786 418#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 39787 419#define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8 420#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 39795 421#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE 1024 422#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 40819 423#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE 512 424#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 41331 425#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE 512 426#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 41843 427#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 512 428#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 42355 429#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE 512 430#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 42867 431#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE 32 432#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 42899 433#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 42900 434#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 42901 435#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 42902 436#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 42903 437#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 42904 438#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 42905 439#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 42906 440#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 42907 441#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 42908 442#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 42909 443#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 42910 444#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 42911 445#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 42912 446#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 42913 447#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 42914 448#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 42915 449#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 42916 450#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 42917 451#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 42918 452#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 42919 453#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 42920 454#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 42921 455#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 42922 456#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 42923 457#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 42924 458#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 42925 459#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 42926 460#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 42927 461#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 42928 462#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 42929 463#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 42930 464#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 42931 465#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 42932 466#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 42933 467#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 42934 468#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 42935 469#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 42936 470#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 42937 471#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 42938 472#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 42939 473#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 42940 474#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 42941 475#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 42942 476#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 42943 477#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 42944 478#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 42945 479#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 42946 480#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 42947 481#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 42948 482#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 42949 483#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 42950 484#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 42951 485#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 42952 486#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 42953 487#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 42954 488#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 42955 489#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 42956 490#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 42957 491#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 42958 492#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 42959 493#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 42960 494#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 42961 495#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 42962 496#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 42963 497#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 42964 498#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 42965 499#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 42966 500#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 42967 501#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 42968 502#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 42969 503#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 42970 504#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 42971 505#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 42972 506#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 42973 507#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 42974 508#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 42975 509#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 42976 510#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 42977 511#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 42978 512#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 42979 513#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 42980 514#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 42981 515#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 42982 516#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 42983 517#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 42984 518#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 42985 519#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 42986 520#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 42987 521#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 42988 522#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 42989 523#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 42990 524#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 42991 525#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 42992 526#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 42993 527#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 42994 528#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 42995 529#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 42996 530#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 42997 531#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 42998 532#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 42999 533#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 43000 534#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 43001 535#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 43002 536#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 43003 537#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 43004 538#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 43005 539#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 43006 540#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 43007 541#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 43008 542#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 43009 543#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 43010 544#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 43011 545#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 43012 546#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 43013 547#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 43014 548#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 43015 549#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 43016 550#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 43017 551#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 43018 552#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 43019 553#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 43020 554#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 43021 555#define XCM_REG_CON_PHY_Q3_RT_OFFSET 43022 556 557#define RUNTIME_ARRAY_SIZE 43023 558 559/* Init Callbacks */ 560#define DMAE_READY_CB 0 561 562#endif /* __RT_DEFS_H__ */ 563