1/*- 2 * Copyright (C) 2018 Cavium Inc. 3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 4 * Copyright (c) 2014 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Semihalf under 8 * the sponsorship of the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32/* Generic ECAM PCIe driver */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD$"); 36 37#include "opt_platform.h" 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/malloc.h> 42#include <sys/kernel.h> 43#include <sys/rman.h> 44#include <sys/module.h> 45#include <sys/bus.h> 46#include <sys/endian.h> 47#include <sys/cpuset.h> 48#include <sys/rwlock.h> 49 50#include <contrib/dev/acpica/include/acpi.h> 51#include <contrib/dev/acpica/include/accommon.h> 52 53#include <dev/acpica/acpivar.h> 54#include <dev/acpica/acpi_pcibvar.h> 55 56#include <dev/pci/pcivar.h> 57#include <dev/pci/pcireg.h> 58#include <dev/pci/pcib_private.h> 59#include <dev/pci/pci_host_generic.h> 60#include <dev/pci/pci_host_generic_acpi.h> 61 62#include <machine/cpu.h> 63#include <machine/bus.h> 64#include <machine/intr.h> 65 66#include "pcib_if.h" 67#include "acpi_bus_if.h" 68 69/* Assembling ECAM Configuration Address */ 70#define PCIE_BUS_SHIFT 20 71#define PCIE_SLOT_SHIFT 15 72#define PCIE_FUNC_SHIFT 12 73#define PCIE_BUS_MASK 0xFF 74#define PCIE_SLOT_MASK 0x1F 75#define PCIE_FUNC_MASK 0x07 76#define PCIE_REG_MASK 0xFFF 77 78#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ 79 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ 80 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ 81 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ 82 ((reg) & PCIE_REG_MASK)) 83 84#define PCI_IO_WINDOW_OFFSET 0x1000 85 86#define SPACE_CODE_SHIFT 24 87#define SPACE_CODE_MASK 0x3 88#define SPACE_CODE_IO_SPACE 0x1 89#define PROPS_CELL_SIZE 1 90#define PCI_ADDR_CELL_SIZE 2 91 92/* Forward prototypes */ 93 94static int generic_pcie_acpi_probe(device_t dev); 95static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *); 96static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *); 97 98/* 99 * generic_pcie_acpi_probe - look for root bridge flag 100 */ 101static int 102generic_pcie_acpi_probe(device_t dev) 103{ 104 ACPI_DEVICE_INFO *devinfo; 105 ACPI_HANDLE h; 106 int root; 107 108 if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL || 109 ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo))) 110 return (ENXIO); 111 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0; 112 AcpiOsFree(devinfo); 113 if (!root) 114 return (ENXIO); 115 116 device_set_desc(dev, "Generic PCI host controller"); 117 return (BUS_PROBE_GENERIC); 118} 119 120/* 121 * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces 122 * 'produced' by this bridge 123 */ 124static ACPI_STATUS 125pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg) 126{ 127 device_t dev = (device_t)arg; 128 struct generic_pcie_acpi_softc *sc; 129 struct rman *rm; 130 rman_res_t min, max, off; 131 int r; 132 133 rm = NULL; 134 sc = device_get_softc(dev); 135 r = sc->base.nranges; 136 switch (res->Type) { 137 case ACPI_RESOURCE_TYPE_ADDRESS16: 138 min = res->Data.Address16.Address.Minimum; 139 max = res->Data.Address16.Address.Maximum; 140 break; 141 case ACPI_RESOURCE_TYPE_ADDRESS32: 142 min = res->Data.Address32.Address.Minimum; 143 max = res->Data.Address32.Address.Maximum; 144 off = res->Data.Address32.Address.TranslationOffset; 145 break; 146 case ACPI_RESOURCE_TYPE_ADDRESS64: 147 min = res->Data.Address64.Address.Minimum; 148 max = res->Data.Address64.Address.Maximum; 149 off = res->Data.Address64.Address.TranslationOffset; 150 break; 151 default: 152 return (AE_OK); 153 } 154 155 /* Save detected ranges */ 156 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE || 157 res->Data.Address.ResourceType == ACPI_IO_RANGE) { 158 sc->base.ranges[r].pci_base = min; 159 sc->base.ranges[r].phys_base = min + off; 160 sc->base.ranges[r].size = max - min + 1; 161 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE) 162 sc->base.ranges[r].flags |= FLAG_TYPE_MEM; 163 else if (res->Data.Address.ResourceType == ACPI_IO_RANGE) 164 sc->base.ranges[r].flags |= FLAG_TYPE_IO; 165 sc->base.nranges++; 166 } else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) { 167 sc->base.bus_start = min; 168 sc->base.bus_end = max; 169 } 170 return (AE_OK); 171} 172 173static int 174pci_host_acpi_get_ecam_resource(device_t dev) 175{ 176 struct generic_pcie_acpi_softc *sc; 177 struct acpi_device *ad; 178 struct resource_list *rl; 179 ACPI_TABLE_HEADER *hdr; 180 ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end; 181 ACPI_HANDLE handle; 182 ACPI_STATUS status; 183 rman_res_t base, start, end; 184 int found, val; 185 186 sc = device_get_softc(dev); 187 handle = acpi_get_handle(dev); 188 189 /* Try MCFG first */ 190 status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr); 191 if (ACPI_SUCCESS(status)) { 192 found = FALSE; 193 mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length); 194 mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1); 195 while (mcfg_entry < mcfg_end && !found) { 196 if (mcfg_entry->PciSegment == sc->base.ecam && 197 mcfg_entry->StartBusNumber <= sc->base.bus_start && 198 mcfg_entry->EndBusNumber >= sc->base.bus_start) 199 found = TRUE; 200 else 201 mcfg_entry++; 202 } 203 if (found) { 204 if (mcfg_entry->EndBusNumber < sc->base.bus_end) 205 sc->base.bus_end = mcfg_entry->EndBusNumber; 206 base = mcfg_entry->Address; 207 } else { 208 device_printf(dev, "MCFG exists, but does not have bus %d-%d\n", 209 sc->base.bus_start, sc->base.bus_end); 210 return (ENXIO); 211 } 212 } else { 213 status = acpi_GetInteger(handle, "_CBA", &val); 214 if (ACPI_SUCCESS(status)) 215 base = val; 216 else 217 return (ENXIO); 218 } 219 220 /* add as MEM rid 0 */ 221 ad = device_get_ivars(dev); 222 rl = &ad->ad_rl; 223 start = base + (sc->base.bus_start << PCIE_BUS_SHIFT); 224 end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1; 225 resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1); 226 if (bootverbose) 227 device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n", 228 sc->base.bus_start, sc->base.bus_end, start, end); 229 return (0); 230} 231 232int 233pci_host_generic_acpi_init(device_t dev) 234{ 235 struct generic_pcie_acpi_softc *sc; 236 ACPI_HANDLE handle; 237 ACPI_STATUS status; 238 int error; 239 240 sc = device_get_softc(dev); 241 handle = acpi_get_handle(dev); 242 243 /* Get Start bus number for the PCI host bus is from _BBN method */ 244 status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start); 245 if (ACPI_FAILURE(status)) { 246 device_printf(dev, "No _BBN, using start bus 0\n"); 247 sc->base.bus_start = 0; 248 } 249 sc->base.bus_end = 255; 250 251 /* Get PCI Segment (domain) needed for MCFG lookup */ 252 status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam); 253 if (ACPI_FAILURE(status)) { 254 device_printf(dev, "No _SEG for PCI Bus, using segment 0\n"); 255 sc->base.ecam = 0; 256 } 257 258 /* Bus decode ranges */ 259 status = AcpiWalkResources(handle, "_CRS", 260 pci_host_generic_acpi_parse_resource, (void *)dev); 261 if (ACPI_FAILURE(status)) 262 return (ENXIO); 263 264 /* Coherency attribute */ 265 if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent))) 266 sc->base.coherent = 0; 267 if (bootverbose) 268 device_printf(dev, "Bus is%s cache-coherent\n", 269 sc->base.coherent ? "" : " not"); 270 271 /* add config space resource */ 272 pci_host_acpi_get_ecam_resource(dev); 273 acpi_pcib_fetch_prt(dev, &sc->ap_prt); 274 275 error = pci_host_generic_core_attach(dev); 276 if (error != 0) 277 return (error); 278 279 return (0); 280} 281 282static int 283pci_host_generic_acpi_attach(device_t dev) 284{ 285 int error; 286 287 error = pci_host_generic_acpi_init(dev); 288 if (error != 0) 289 return (error); 290 291 device_add_child(dev, "pci", -1); 292 return (bus_generic_attach(dev)); 293} 294 295static int 296generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index, 297 uintptr_t *result) 298{ 299 struct generic_pcie_acpi_softc *sc; 300 301 sc = device_get_softc(dev); 302 303 if (index == PCIB_IVAR_BUS) { 304 *result = sc->base.bus_start; 305 return (0); 306 } 307 308 if (index == PCIB_IVAR_DOMAIN) { 309 *result = sc->base.ecam; 310 return (0); 311 } 312 313 if (bootverbose) 314 device_printf(dev, "ERROR: Unknown index %d.\n", index); 315 return (ENOENT); 316} 317 318static int 319generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin) 320{ 321 struct generic_pcie_acpi_softc *sc; 322 323 sc = device_get_softc(bus); 324 return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt)); 325} 326 327static u_int 328generic_pcie_get_xref(device_t pci, device_t child) 329{ 330 struct generic_pcie_acpi_softc *sc; 331 uintptr_t rid; 332 u_int xref, devid; 333 int err; 334 335 sc = device_get_softc(pci); 336 err = pcib_get_id(pci, child, PCI_ID_RID, &rid); 337 if (err != 0) 338 return (ACPI_MSI_XREF); 339 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid); 340 if (err != 0) 341 return (ACPI_MSI_XREF); 342 return (xref); 343} 344 345static u_int 346generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id) 347{ 348 struct generic_pcie_acpi_softc *sc; 349 uintptr_t rid; 350 u_int xref, devid; 351 int err; 352 353 sc = device_get_softc(pci); 354 err = pcib_get_id(pci, child, PCI_ID_RID, &rid); 355 if (err != 0) 356 return (err); 357 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid); 358 if (err == 0) 359 *id = devid; 360 else 361 *id = rid; /* RID not in IORT, likely FW bug, ignore */ 362 return (0); 363} 364 365static int 366generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count, 367 int maxcount, int *irqs) 368{ 369 370#if defined(INTRNG) 371 return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child), 372 count, maxcount, irqs)); 373#else 374 return (ENXIO); 375#endif 376} 377 378static int 379generic_pcie_acpi_release_msi(device_t pci, device_t child, int count, 380 int *irqs) 381{ 382 383#if defined(INTRNG) 384 return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child), 385 count, irqs)); 386#else 387 return (ENXIO); 388#endif 389} 390 391static int 392generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 393 uint32_t *data) 394{ 395 396#if defined(INTRNG) 397 return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq, 398 addr, data)); 399#else 400 return (ENXIO); 401#endif 402} 403 404static int 405generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq) 406{ 407 408#if defined(INTRNG) 409 return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child), 410 irq)); 411#else 412 return (ENXIO); 413#endif 414} 415 416static int 417generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq) 418{ 419 420#if defined(INTRNG) 421 return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child), 422 irq)); 423#else 424 return (ENXIO); 425#endif 426} 427 428static int 429generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type, 430 uintptr_t *id) 431{ 432 433 if (type == PCI_ID_MSI) 434 return (generic_pcie_map_id(pci, child, id)); 435 else 436 return (pcib_get_id(pci, child, type, id)); 437} 438 439static device_method_t generic_pcie_acpi_methods[] = { 440 DEVMETHOD(device_probe, generic_pcie_acpi_probe), 441 DEVMETHOD(device_attach, pci_host_generic_acpi_attach), 442 DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar), 443 444 /* pcib interface */ 445 DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt), 446 DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi), 447 DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi), 448 DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix), 449 DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix), 450 DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi), 451 DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id), 452 453 DEVMETHOD_END 454}; 455 456DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods, 457 sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver); 458 459static devclass_t generic_pcie_acpi_devclass; 460 461DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, generic_pcie_acpi_devclass, 462 0, 0); 463