1/*- 2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 23 * The full GNU General Public License is included in this distribution 24 * in the file called LICENSE.GPL. 25 * 26 * BSD LICENSE 27 * 28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 35 * * Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * * Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in 39 * the documentation and/or other materials provided with the 40 * distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 * 54 * $FreeBSD$ 55 */ 56#ifndef _SCIF_SAS_CONTROLLER_H_ 57#define _SCIF_SAS_CONTROLLER_H_ 58 59/** 60 * @file 61 * 62 * @brief This file contains the protected interface structures, constants, 63 * and methods for the SCIF_SAS_CONTROLLER object. 64 */ 65 66#ifdef __cplusplus 67extern "C" { 68#endif // __cplusplus 69 70#include <dev/isci/scil/sci_types.h> 71#include <dev/isci/scil/sci_abstract_list.h> 72#include <dev/isci/scil/sci_controller_constants.h> 73#include <dev/isci/scil/sci_memory_descriptor_list.h> 74#include <dev/isci/scil/sci_base_controller.h> 75#include <dev/isci/scil/scif_controller.h> 76#include <dev/isci/scil/scif_config_parameters.h> 77#include <dev/isci/scil/scif_sas_domain.h> 78#include <dev/isci/scil/scif_sas_io_request.h> 79#include <dev/isci/scil/scif_sas_task_request.h> 80#include <dev/isci/scil/scif_sas_constants.h> 81#include <dev/isci/scil/sci_pool.h> 82#include <dev/isci/scil/scif_sas_internal_io_request.h> 83#include <dev/isci/scil/scif_sas_high_priority_request_queue.h> 84#include <dev/isci/scil/scif_sas_smp_phy.h> 85 86 87// Currently there is only a need for 1 memory descriptor. This descriptor 88// describes the internal IO request memory. 89#define SCIF_SAS_MAX_MEMORY_DESCRIPTORS 1 90 91enum _SCIF_SAS_MAX_MEMORY_DESCRIPTORS 92{ 93 SCIF_SAS_MDE_INTERNAL_IO = 0 94 95}; 96 97/** 98 * @struct SCIF_SAS_CONTROLLER 99 * 100 * @brief The SCI SAS Framework controller object abstracts storage controller 101 * level behavior for the framework component. 102 */ 103typedef struct SCIF_SAS_CONTROLLER 104{ 105 /** 106 * The SCI_BASE_CONTROLLER is the parent object for the SCIF_SAS_CONTROLLER 107 * object. 108 */ 109 SCI_BASE_CONTROLLER_T parent; 110 111 /** 112 * This field contains the handle for the SCI Core controller object that 113 * is managed by this framework controller. 114 */ 115 SCI_CONTROLLER_HANDLE_T core_object; 116 117 /** 118 * This field references the list of state specific handler methods to 119 * be utilized for this controller instance. 120 */ 121 SCI_BASE_CONTROLLER_STATE_HANDLER_T * state_handlers; 122 123 /** 124 * This field contains the memory desciptors defining the physical 125 * memory requirements for this controller. 126 */ 127 SCI_PHYSICAL_MEMORY_DESCRIPTOR_T mdes[SCIF_SAS_MAX_MEMORY_DESCRIPTORS]; 128 129 /** 130 * This field contains the SAS domain objects managed by this controller. 131 */ 132 SCIF_SAS_DOMAIN_T domains[SCI_MAX_DOMAINS]; 133 134 /** 135 * This field represents the pool of available remote device objects 136 * supported by the controller. 137 */ 138 SCI_ABSTRACT_ELEMENT_POOL_T free_remote_device_pool; 139 140 /** 141 * This field contains the maximum number of abstract elements that 142 * can be placed in the pool. 143 */ 144 SCI_ABSTRACT_ELEMENT_T remote_device_pool_elements[SCI_MAX_REMOTE_DEVICES]; 145 146 /** 147 * This field provides the controller object a scratch area to indicate 148 * status of an ongoing operation. 149 */ 150 SCI_STATUS operation_status; 151 152 /** 153 * This field will contain an user specified parameter information 154 * to be utilized by the framework. 155 */ 156 SCIF_USER_PARAMETERS_T user_parameters; 157 158 /** 159 * This field records the index for the current domain to clear affiliation 160 * EA SATA remote devices, during the controller stop process. 161 */ 162 U8 current_domain_to_clear_affiliation; 163 164 U32 internal_request_entries; 165 166 /** 167 * This field provides a pool to manage the memory resource for all internal 168 * requests. 169 * requests. 170 */ 171 SCI_POOL_CREATE( 172 internal_request_memory_pool, 173 POINTER_UINT, 174 SCIF_SAS_MAX_INTERNAL_REQUEST_COUNT 175 ); 176 177 /** 178 * This field provides a queue for built internal requests waiting to be 179 * started. 180 */ 181 SCIF_SAS_HIGH_PRIORITY_REQUEST_QUEUE_T hprq; 182 183 /** 184 * This represents the number of available SMP phy objects that can 185 * be managed by the framework. 186 */ 187 SCIF_SAS_SMP_PHY_T smp_phy_array[SCIF_SAS_SMP_PHY_COUNT]; 188 189 /** 190 * This field provides a list to manage the memory resource for all 191 * smp_phy objects. 192 */ 193 SCI_FAST_LIST_T smp_phy_memory_list; 194 195#if !defined(DISABLE_INTERRUPTS) 196 /** 197 * This field saves the interrupt coalescing count before changing interrupt 198 * coalescence. 199 */ 200 U16 saved_interrupt_coalesce_number; 201 202 /** 203 * This field saves the interrupt coalescing timeout values in micorseconds 204 * before changing interrupt coalescence. 205 */ 206 U32 saved_interrupt_coalesce_timeout; 207#endif // !defined(DISABLE_INTERRUPTS) 208 209} SCIF_SAS_CONTROLLER_T; 210 211extern SCI_BASE_STATE_T scif_sas_controller_state_table[]; 212extern SCI_BASE_CONTROLLER_STATE_HANDLER_T 213 scif_sas_controller_state_handler_table[]; 214 215SCI_STATUS scif_sas_controller_continue_io( 216 SCI_CONTROLLER_HANDLE_T controller, 217 SCI_REMOTE_DEVICE_HANDLE_T remote_device, 218 SCI_IO_REQUEST_HANDLE_T io_request 219); 220 221void scif_sas_controller_destruct( 222 SCIF_SAS_CONTROLLER_T * fw_controller 223); 224 225void * scif_sas_controller_allocate_internal_request( 226 SCIF_SAS_CONTROLLER_T * fw_controller 227); 228 229void scif_sas_controller_free_internal_request( 230 SCIF_SAS_CONTROLLER_T * fw_controller, 231 void * fw_internal_request_buffer 232); 233 234void scif_sas_controller_start_high_priority_io( 235 SCIF_SAS_CONTROLLER_T * fw_controller 236); 237 238BOOL scif_sas_controller_sufficient_resource( 239 SCIF_SAS_CONTROLLER_T *fw_controller 240); 241 242SCI_STATUS scif_sas_controller_complete_high_priority_io( 243 SCIF_SAS_CONTROLLER_T * fw_controller, 244 SCIF_SAS_REMOTE_DEVICE_T * remote_device, 245 SCIF_SAS_REQUEST_T * io_request 246); 247 248SCIF_SAS_SMP_PHY_T * scif_sas_controller_allocate_smp_phy( 249 SCIF_SAS_CONTROLLER_T * fw_controller 250); 251 252void scif_sas_controller_free_smp_phy( 253 SCIF_SAS_CONTROLLER_T * fw_controller, 254 SCIF_SAS_SMP_PHY_T * smp_phy 255); 256 257SCI_STATUS scif_sas_controller_clear_affiliation( 258 SCIF_SAS_CONTROLLER_T * fw_controller 259); 260 261SCI_STATUS scif_sas_controller_continue_to_stop( 262 SCIF_SAS_CONTROLLER_T * fw_controller 263); 264 265void scif_sas_controller_set_default_config_parameters( 266 SCIF_SAS_CONTROLLER_T * this_controller 267); 268 269SCI_STATUS scif_sas_controller_release_resource( 270 SCIF_SAS_CONTROLLER_T * fw_controller 271); 272 273void scif_sas_controller_build_mdl( 274 SCIF_SAS_CONTROLLER_T * fw_controller 275); 276 277#if !defined(DISABLE_INTERRUPTS) 278 279void scif_sas_controller_save_interrupt_coalescence( 280 SCIF_SAS_CONTROLLER_T * fw_controller 281); 282 283void scif_sas_controller_restore_interrupt_coalescence( 284 SCIF_SAS_CONTROLLER_T * fw_controller 285); 286 287#else // !defined(DISABLE_INTERRUPTS) 288#define scif_sas_controller_save_interrupt_coalescence(controller) 289#define scif_sas_controller_restore_interrupt_coalescence(controller) 290#endif // !defined(DISABLE_INTERRUPTS) 291 292#ifdef SCI_LOGGING 293void scif_sas_controller_initialize_state_logging( 294 SCIF_SAS_CONTROLLER_T *this_controller 295); 296 297void scif_sas_controller_deinitialize_state_logging( 298 SCIF_SAS_CONTROLLER_T *this_controller 299); 300#else // SCI_LOGGING 301#define scif_sas_controller_initialize_state_logging(x) 302#define scif_sas_controller_deinitialize_state_logging(x) 303#endif // SCI_LOGGING 304 305#ifdef __cplusplus 306} 307#endif // __cplusplus 308 309#endif // _SCIF_SAS_CONTROLLER_H_ 310 311