1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004 Texas A&M University 5 * All rights reserved. 6 * 7 * Developer: Wm. Daryl Hawkins 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31/* 32 * Intel ICH Watchdog Timer (WDT) driver 33 * 34 * Originally developed by Wm. Daryl Hawkins of Texas A&M 35 * Heavily modified by <des@FreeBSD.org> 36 * 37 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 38 * device as it's actually an integrated function of the ICH LPC interface 39 * bridge. Detection is also awkward, because we can only infer the 40 * presence of the watchdog timer from the fact that the machine has an 41 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 42 * ACPI table (although this driver does not support the ACPI detection 43 * method). 44 * 45 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 46 * way of knowing if the WDT is permanently disabled (either by the BIOS 47 * or in hardware). 48 * 49 * The WDT is programmed through I/O registers in the ACPI I/O space. 50 * Intel swears it's always at offset 0x60, so we use that. 51 * 52 * For details about the ICH WDT, see Intel Application Note AP-725 53 * (document no. 292273-001). The WDT is also described in the individual 54 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 55 * (document no. 252516-001) sections 9.10 and 9.11. 56 * 57 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 58 * SoC PMC support by Denir Li <denir.li@cas-well.com> 59 */ 60 61#include <sys/cdefs.h> 62__FBSDID("$FreeBSD$"); 63 64#include <sys/param.h> 65#include <sys/eventhandler.h> 66#include <sys/kernel.h> 67#include <sys/module.h> 68#include <sys/systm.h> 69#include <sys/bus.h> 70#include <machine/bus.h> 71#include <sys/rman.h> 72#include <machine/resource.h> 73#include <sys/watchdog.h> 74 75#include <isa/isavar.h> 76#include <dev/pci/pcivar.h> 77 78#include <dev/ichwd/ichwd.h> 79 80#include <x86/pci_cfgreg.h> 81#include <dev/pci/pcivar.h> 82#include <dev/pci/pci_private.h> 83 84static struct ichwd_device ichwd_devices[] = { 85 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 }, 86 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 }, 87 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2, 1 }, 88 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2, 1 }, 89 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3, 1 }, 90 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3, 1 }, 91 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4, 1 }, 92 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4, 1 }, 93 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5, 1 }, 94 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5, 1 }, 95 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5, 1 }, 96 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5, 1 }, 97 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6, 2 }, 98 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6, 2 }, 99 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6, 2 }, 100 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7, 2 }, 101 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7, 2 }, 102 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7, 2 }, 103 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7, 2 }, 104 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7, 2 }, 105 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8, 2 }, 106 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8, 2 }, 107 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8, 2 }, 108 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8, 2 }, 109 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8, 2 }, 110 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8, 2 }, 111 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9, 2 }, 112 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9, 2 }, 113 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9, 2 }, 114 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9, 2 }, 115 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9, 2 }, 116 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9, 2 }, 117 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10, 2 }, 118 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10, 2 }, 119 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10, 2 }, 120 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10, 2 }, 121 { DEVICEID_PCH, "Intel PCH watchdog timer", 10, 2 }, 122 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10, 2 }, 123 { DEVICEID_P55, "Intel P55 watchdog timer", 10, 2 }, 124 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10, 2 }, 125 { DEVICEID_H55, "Intel H55 watchdog timer", 10, 2 }, 126 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10, 2 }, 127 { DEVICEID_H57, "Intel H57 watchdog timer", 10, 2 }, 128 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10, 2 }, 129 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10, 2 }, 130 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10, 2 }, 131 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10, 2 }, 132 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10, 2 }, 133 { DEVICEID_3400, "Intel 3400 watchdog timer", 10, 2 }, 134 { DEVICEID_3420, "Intel 3420 watchdog timer", 10, 2 }, 135 { DEVICEID_3450, "Intel 3450 watchdog timer", 10, 2 }, 136 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10, 2 }, 137 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10, 2 }, 138 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10, 2 }, 139 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10, 2 }, 140 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10, 2 }, 141 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10, 2 }, 142 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10, 2 }, 143 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10, 2 }, 144 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10, 2 }, 145 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10, 2 }, 146 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10, 2 }, 147 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10, 2 }, 148 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10, 2 }, 149 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10, 2 }, 150 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10, 2 }, 151 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10, 2 }, 152 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10, 2 }, 153 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10, 2 }, 154 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10, 2 }, 155 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10, 2 }, 156 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10, 2 }, 157 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10, 2 }, 158 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10, 2 }, 159 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10, 2 }, 160 { DEVICEID_CPT24, "Intel Cougar Point watchdog timer", 10, 2 }, 161 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10, 2 }, 162 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10, 2 }, 163 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10, 2 }, 164 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10, 2 }, 165 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10, 2 }, 166 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10, 2 }, 167 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10, 2 }, 168 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10, 2 }, 169 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10, 2 }, 170 { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10, 2 }, 171 { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10, 2 }, 172 { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10, 2 }, 173 { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10, 2 }, 174 { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10, 2 }, 175 { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10, 2 }, 176 { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10, 2 }, 177 { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10, 2 }, 178 { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10, 2 }, 179 { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10, 2 }, 180 { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10, 2 }, 181 { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10, 2 }, 182 { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10, 2 }, 183 { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10, 2 }, 184 { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10, 2 }, 185 { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10, 2 }, 186 { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10, 2 }, 187 { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10, 2 }, 188 { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10, 2 }, 189 { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10, 2 }, 190 { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10, 2 }, 191 { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10, 2 }, 192 { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10, 2 }, 193 { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10, 2 }, 194 { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10, 2 }, 195 { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10, 2 }, 196 { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10, 2 }, 197 { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10, 2 }, 198 { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10, 2 }, 199 { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10, 2 }, 200 { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10, 2 }, 201 { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10, 2 }, 202 { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10, 2 }, 203 { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10, 2 }, 204 { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10, 2 }, 205 { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10, 2 }, 206 { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10, 2 }, 207 { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10, 2 }, 208 { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10, 2 }, 209 { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10, 2 }, 210 { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10, 2 }, 211 { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10, 2 }, 212 { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10, 2 }, 213 { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10, 2 }, 214 { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10, 2 }, 215 { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10, 2 }, 216 { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10, 2 }, 217 { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10, 2 }, 218 { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10, 2 }, 219 { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10, 2 }, 220 { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10, 2 }, 221 { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10, 2 }, 222 { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10, 2 }, 223 { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10, 2 }, 224 { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10, 2 }, 225 { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10, 2 }, 226 { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10, 2 }, 227 { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10, 2 }, 228 { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10, 2 }, 229 { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10, 2 }, 230 { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10, 2 }, 231 { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10, 2 }, 232 { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10, 2 }, 233 { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10, 2 }, 234 { DEVICEID_WCPT1, "Intel Wildcat Point watchdog timer", 10, 2 }, 235 { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10, 2 }, 236 { DEVICEID_WCPT3, "Intel Wildcat Point watchdog timer", 10, 2 }, 237 { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10, 2 }, 238 { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10, 2 }, 239 { DEVICEID_WBG0, "Intel Wellsburg watchdog timer", 10, 2 }, 240 { DEVICEID_WBG1, "Intel Wellsburg watchdog timer", 10, 2 }, 241 { DEVICEID_WBG2, "Intel Wellsburg watchdog timer", 10, 2 }, 242 { DEVICEID_WBG3, "Intel Wellsburg watchdog timer", 10, 2 }, 243 { DEVICEID_WBG4, "Intel Wellsburg watchdog timer", 10, 2 }, 244 { DEVICEID_WBG5, "Intel Wellsburg watchdog timer", 10, 2 }, 245 { DEVICEID_WBG6, "Intel Wellsburg watchdog timer", 10, 2 }, 246 { DEVICEID_WBG7, "Intel Wellsburg watchdog timer", 10, 2 }, 247 { DEVICEID_WBG8, "Intel Wellsburg watchdog timer", 10, 2 }, 248 { DEVICEID_WBG9, "Intel Wellsburg watchdog timer", 10, 2 }, 249 { DEVICEID_WBG10, "Intel Wellsburg watchdog timer", 10, 2 }, 250 { DEVICEID_WBG11, "Intel Wellsburg watchdog timer", 10, 2 }, 251 { DEVICEID_WBG12, "Intel Wellsburg watchdog timer", 10, 2 }, 252 { DEVICEID_WBG13, "Intel Wellsburg watchdog timer", 10, 2 }, 253 { DEVICEID_WBG14, "Intel Wellsburg watchdog timer", 10, 2 }, 254 { DEVICEID_WBG15, "Intel Wellsburg watchdog timer", 10, 2 }, 255 { DEVICEID_WBG16, "Intel Wellsburg watchdog timer", 10, 2 }, 256 { DEVICEID_WBG17, "Intel Wellsburg watchdog timer", 10, 2 }, 257 { DEVICEID_WBG18, "Intel Wellsburg watchdog timer", 10, 2 }, 258 { DEVICEID_WBG19, "Intel Wellsburg watchdog timer", 10, 2 }, 259 { DEVICEID_WBG20, "Intel Wellsburg watchdog timer", 10, 2 }, 260 { DEVICEID_WBG21, "Intel Wellsburg watchdog timer", 10, 2 }, 261 { DEVICEID_WBG22, "Intel Wellsburg watchdog timer", 10, 2 }, 262 { DEVICEID_WBG23, "Intel Wellsburg watchdog timer", 10, 2 }, 263 { DEVICEID_WBG24, "Intel Wellsburg watchdog timer", 10, 2 }, 264 { DEVICEID_WBG25, "Intel Wellsburg watchdog timer", 10, 2 }, 265 { DEVICEID_WBG26, "Intel Wellsburg watchdog timer", 10, 2 }, 266 { DEVICEID_WBG27, "Intel Wellsburg watchdog timer", 10, 2 }, 267 { DEVICEID_WBG28, "Intel Wellsburg watchdog timer", 10, 2 }, 268 { DEVICEID_WBG29, "Intel Wellsburg watchdog timer", 10, 2 }, 269 { DEVICEID_WBG30, "Intel Wellsburg watchdog timer", 10, 2 }, 270 { DEVICEID_WBG31, "Intel Wellsburg watchdog timer", 10, 2 }, 271 { DEVICEID_LPT_LP0, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 272 { DEVICEID_LPT_LP1, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 273 { DEVICEID_LPT_LP2, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 274 { DEVICEID_LPT_LP3, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 275 { DEVICEID_LPT_LP4, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 276 { DEVICEID_LPT_LP5, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 277 { DEVICEID_LPT_LP6, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 278 { DEVICEID_LPT_LP7, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 279 { DEVICEID_WCPT_LP1, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 280 { DEVICEID_WCPT_LP2, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 281 { DEVICEID_WCPT_LP3, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 282 { DEVICEID_WCPT_LP5, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 283 { DEVICEID_WCPT_LP6, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 284 { DEVICEID_WCPT_LP7, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 285 { DEVICEID_WCPT_LP9, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 286 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10, 2 }, 287 { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10, 2 }, 288 { DEVICEID_AVN0, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 289 { DEVICEID_AVN1, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 290 { DEVICEID_AVN2, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 291 { DEVICEID_AVN3, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 292 { DEVICEID_BAYTRAIL, "Intel Bay Trail SoC watchdog timer", 10, 3 }, 293 { DEVICEID_BRASWELL, "Intel Braswell SoC watchdog timer", 10, 3 }, 294 { 0, NULL, 0, 0 }, 295}; 296 297static struct ichwd_device ichwd_smb_devices[] = { 298 { DEVICEID_LEWISBURG_SMB, "Lewisburg watchdog timer", 10, 4 }, 299 { DEVICEID_SRPTLP_SMB, "Sunrise Point-LP watchdog timer", 10, 4 }, 300 { DEVICEID_C3000, "Intel Atom C3000 watchdog timer", 10, 4 }, 301 { 0, NULL, 0, 0 }, 302}; 303 304static devclass_t ichwd_devclass; 305 306#define ichwd_read_tco_1(sc, off) \ 307 bus_read_1((sc)->tco_res, (off)) 308#define ichwd_read_tco_2(sc, off) \ 309 bus_read_2((sc)->tco_res, (off)) 310#define ichwd_read_tco_4(sc, off) \ 311 bus_read_4((sc)->tco_res, (off)) 312#define ichwd_read_smi_4(sc, off) \ 313 bus_read_4((sc)->smi_res, (off)) 314#define ichwd_read_gcs_4(sc, off) \ 315 bus_read_4((sc)->gcs_res, (off)) 316/* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 317#define ichwd_read_pmc_4(sc, off) \ 318 bus_read_4((sc)->gcs_res, (off)) 319#define ichwd_read_gc_4(sc, off) \ 320 bus_read_4((sc)->gc_res, (off)) 321 322#define ichwd_write_tco_1(sc, off, val) \ 323 bus_write_1((sc)->tco_res, (off), (val)) 324#define ichwd_write_tco_2(sc, off, val) \ 325 bus_write_2((sc)->tco_res, (off), (val)) 326#define ichwd_write_tco_4(sc, off, val) \ 327 bus_write_4((sc)->tco_res, (off), (val)) 328#define ichwd_write_smi_4(sc, off, val) \ 329 bus_write_4((sc)->smi_res, (off), (val)) 330#define ichwd_write_gcs_4(sc, off, val) \ 331 bus_write_4((sc)->gcs_res, (off), (val)) 332/* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 333#define ichwd_write_pmc_4(sc, off, val) \ 334 bus_write_4((sc)->gcs_res, (off), (val)) 335#define ichwd_write_gc_4(sc, off, val) \ 336 bus_write_4((sc)->gc_res, (off), (val)) 337 338#define ichwd_verbose_printf(dev, ...) \ 339 do { \ 340 if (bootverbose) \ 341 device_printf(dev, __VA_ARGS__);\ 342 } while (0) 343 344/* 345 * Disable the watchdog timeout SMI handler. 346 * 347 * Apparently, some BIOSes install handlers that reset or disable the 348 * watchdog timer instead of resetting the system, so we disable the SMI 349 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 350 * from happening. 351 */ 352static __inline void 353ichwd_smi_disable(struct ichwd_softc *sc) 354{ 355 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 356} 357 358/* 359 * Enable the watchdog timeout SMI handler. See above for details. 360 */ 361static __inline void 362ichwd_smi_enable(struct ichwd_softc *sc) 363{ 364 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 365} 366 367/* 368 * Check if the watchdog SMI triggering is enabled. 369 */ 370static __inline int 371ichwd_smi_is_enabled(struct ichwd_softc *sc) 372{ 373 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); 374} 375 376/* 377 * Reset the watchdog status bits. 378 */ 379static __inline void 380ichwd_sts_reset(struct ichwd_softc *sc) 381{ 382 /* 383 * The watchdog status bits are set to 1 by the hardware to 384 * indicate various conditions. They can be cleared by software 385 * by writing a 1, not a 0. 386 */ 387 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 388 /* 389 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 390 * be done in two separate operations. 391 */ 392 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 393 if (sc->tco_version < 4) 394 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 395} 396 397/* 398 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 399 * TCO1_CNT register. This is complicated by the need to preserve bit 9 400 * of that same register, and the requirement that all other bits must be 401 * written back as zero. 402 */ 403static __inline void 404ichwd_tmr_enable(struct ichwd_softc *sc) 405{ 406 uint16_t cnt; 407 408 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 409 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 410 sc->active = 1; 411 ichwd_verbose_printf(sc->device, "timer enabled\n"); 412} 413 414/* 415 * Disable the watchdog timer. See above for details. 416 */ 417static __inline void 418ichwd_tmr_disable(struct ichwd_softc *sc) 419{ 420 uint16_t cnt; 421 422 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 423 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 424 sc->active = 0; 425 ichwd_verbose_printf(sc->device, "timer disabled\n"); 426} 427 428/* 429 * Reload the watchdog timer: writing anything to any of the lower five 430 * bits of the TCO_RLD register reloads the timer from the last value 431 * written to TCO_TMR. 432 */ 433static __inline void 434ichwd_tmr_reload(struct ichwd_softc *sc) 435{ 436 if (sc->tco_version == 1) 437 ichwd_write_tco_1(sc, TCO_RLD, 1); 438 else 439 ichwd_write_tco_2(sc, TCO_RLD, 1); 440} 441 442/* 443 * Set the initial timeout value. Note that this must always be followed 444 * by a reload. 445 */ 446static __inline void 447ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 448{ 449 450 if (timeout < TCO_RLD_TMR_MIN) 451 timeout = TCO_RLD_TMR_MIN; 452 453 if (sc->tco_version == 1) { 454 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 455 456 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 457 if (timeout > TCO_RLD1_TMR_MAX) 458 timeout = TCO_RLD1_TMR_MAX; 459 tmr_val8 |= timeout; 460 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 461 } else { 462 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 463 464 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 465 if (timeout > TCO_RLD2_TMR_MAX) 466 timeout = TCO_RLD2_TMR_MAX; 467 tmr_val16 |= timeout; 468 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 469 } 470 471 sc->timeout = timeout; 472 473 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 474} 475 476static __inline int 477ichwd_clear_noreboot(struct ichwd_softc *sc) 478{ 479 uint32_t status; 480 int rc = 0; 481 482 /* try to clear the NO_REBOOT bit */ 483 switch (sc->tco_version) { 484 case 1: 485 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 486 status &= ~ICH_GEN_STA_NO_REBOOT; 487 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 488 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 489 if (status & ICH_GEN_STA_NO_REBOOT) 490 rc = EIO; 491 break; 492 case 2: 493 status = ichwd_read_gcs_4(sc, 0); 494 status &= ~ICH_GCS_NO_REBOOT; 495 ichwd_write_gcs_4(sc, 0, status); 496 status = ichwd_read_gcs_4(sc, 0); 497 if (status & ICH_GCS_NO_REBOOT) 498 rc = EIO; 499 break; 500 case 3: 501 status = ichwd_read_pmc_4(sc, 0); 502 status &= ~ICH_PMC_NO_REBOOT; 503 ichwd_write_pmc_4(sc, 0, status); 504 status = ichwd_read_pmc_4(sc, 0); 505 if (status & ICH_PMC_NO_REBOOT) 506 rc = EIO; 507 break; 508 case 4: 509 status = ichwd_read_gc_4(sc, 0); 510 status &= ~SMB_GC_NO_REBOOT; 511 ichwd_write_gc_4(sc, 0, status); 512 status = ichwd_read_gc_4(sc, 0); 513 if (status & SMB_GC_NO_REBOOT) 514 rc = EIO; 515 break; 516 default: 517 ichwd_verbose_printf(sc->device, 518 "Unknown TCO Version: %d, can't set NO_REBOOT.\n", 519 sc->tco_version); 520 break; 521 } 522 523 if (rc) 524 device_printf(sc->device, 525 "ICH WDT present but disabled in BIOS or hardware\n"); 526 527 return (rc); 528} 529 530/* 531 * Watchdog event handler - called by the framework to enable or disable 532 * the watchdog or change the initial timeout value. 533 */ 534static void 535ichwd_event(void *arg, unsigned int cmd, int *error) 536{ 537 struct ichwd_softc *sc = arg; 538 unsigned int timeout; 539 540 /* convert from power-of-two-ns to WDT ticks */ 541 cmd &= WD_INTERVAL; 542 543 if (sc->tco_version == 3) { 544 timeout = ((uint64_t)1 << cmd) / ICHWD_TCO_V3_TICK; 545 } else { 546 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 547 } 548 549 if (cmd) { 550 if (!sc->active) 551 ichwd_tmr_enable(sc); 552 if (timeout != sc->timeout) 553 ichwd_tmr_set(sc, timeout); 554 ichwd_tmr_reload(sc); 555 *error = 0; 556 } else { 557 if (sc->active) 558 ichwd_tmr_disable(sc); 559 } 560} 561 562static device_t 563ichwd_find_ich_lpc_bridge(device_t isa, struct ichwd_device **id_p) 564{ 565 struct ichwd_device *id; 566 device_t isab, pci; 567 uint16_t devid; 568 569 /* Check whether parent ISA bridge looks familiar. */ 570 isab = device_get_parent(isa); 571 pci = device_get_parent(isab); 572 if (pci == NULL || device_get_devclass(pci) != devclass_find("pci")) 573 return (NULL); 574 if (pci_get_vendor(isab) != VENDORID_INTEL) 575 return (NULL); 576 devid = pci_get_device(isab); 577 for (id = ichwd_devices; id->desc != NULL; ++id) { 578 if (devid == id->device) { 579 if (id_p != NULL) 580 *id_p = id; 581 return (isab); 582 } 583 } 584 585 return (NULL); 586} 587 588static device_t 589ichwd_find_smb_dev(device_t isa, struct ichwd_device **id_p) 590{ 591 struct ichwd_device *id; 592 device_t isab, smb; 593 uint16_t devid; 594 595 /* 596 * Check if SMBus controller provides TCO configuration. 597 * The controller's device and function are fixed and we expect 598 * it to be on the same bus as ISA bridge. 599 */ 600 isab = device_get_parent(isa); 601 smb = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 4); 602 if (smb == NULL) 603 return (NULL); 604 if (pci_get_vendor(smb) != VENDORID_INTEL) 605 return (NULL); 606 devid = pci_get_device(smb); 607 for (id = ichwd_smb_devices; id->desc != NULL; ++id) { 608 if (devid == id->device) { 609 if (id_p != NULL) 610 *id_p = id; 611 return (smb); 612 } 613 } 614 615 return (NULL); 616} 617 618/* 619 * Look for an ICH LPC interface bridge. If one is found, register an 620 * ichwd device. There can be only one. 621 */ 622static void 623ichwd_identify(driver_t *driver, device_t parent) 624{ 625 struct ichwd_device *id_p; 626 device_t ich, smb; 627 device_t dev; 628 uint64_t base_address64; 629 uint32_t base_address; 630 uint32_t ctl; 631 int rc; 632 633 ich = ichwd_find_ich_lpc_bridge(parent, &id_p); 634 if (ich == NULL) { 635 smb = ichwd_find_smb_dev(parent, &id_p); 636 if (smb == NULL) 637 return; 638 } 639 640 KASSERT(id_p->tco_version >= 1, 641 ("unexpected TCO version %d", id_p->tco_version)); 642 KASSERT(id_p->tco_version != 4 || smb != NULL, 643 ("could not find PCI SMBus device for TCOv4")); 644 KASSERT(id_p->tco_version >= 4 || ich != NULL, 645 ("could not find PCI LPC bridge device for TCOv1-3")); 646 647 /* good, add child to bus */ 648 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 649 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 650 651 if (dev == NULL) 652 return; 653 654 switch (id_p->tco_version) { 655 case 1: 656 break; 657 case 2: 658 /* get RCBA (root complex base address) */ 659 base_address = pci_read_config(ich, ICH_RCBA, 4); 660 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 661 (base_address & 0xffffc000) + ICH_GCS_OFFSET, 662 ICH_GCS_SIZE); 663 if (rc) 664 ichwd_verbose_printf(dev, 665 "Can not set TCO v%d memory resource for RCBA\n", 666 id_p->tco_version); 667 break; 668 case 3: 669 /* get PBASE (Power Management Controller base address) */ 670 base_address = pci_read_config(ich, ICH_PBASE, 4); 671 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 672 (base_address & 0xfffffe00) + ICH_PMC_OFFSET, 673 ICH_PMC_SIZE); 674 if (rc) 675 ichwd_verbose_printf(dev, 676 "Can not set TCO v%d memory resource for PBASE\n", 677 id_p->tco_version); 678 break; 679 case 4: 680 /* Get TCO base address. */ 681 ctl = pci_read_config(smb, ICH_TCOCTL, 4); 682 if ((ctl & ICH_TCOCTL_TCO_BASE_EN) == 0) { 683 ichwd_verbose_printf(dev, 684 "TCO v%d decoding is not enabled\n", 685 id_p->tco_version); 686 break; 687 } 688 base_address = pci_read_config(smb, ICH_TCOBASE, 4); 689 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, 690 base_address & ICH_TCOBASE_ADDRMASK, ICH_TCOBASE_SIZE); 691 if (rc != 0) { 692 ichwd_verbose_printf(dev, 693 "Can not set TCO v%d I/O resource (err = %d)\n", 694 id_p->tco_version, rc); 695 } 696 697 /* 698 * Unhide Primary to Sideband Bridge (P2SB) PCI device, so that 699 * we can discover the base address of Private Configuration 700 * Space via the bridge's BAR. 701 * Then hide back the bridge. 702 */ 703 pci_cfgregwrite(0, 31, 1, 0xe1, 0, 1); 704 base_address64 = pci_cfgregread(0, 31, 1, SBREG_BAR + 4, 4); 705 base_address64 <<= 32; 706 base_address64 |= pci_cfgregread(0, 31, 1, SBREG_BAR, 4); 707 base_address64 &= ~0xfull; 708 pci_cfgregwrite(0, 31, 1, 0xe1, 1, 1); 709 710 /* 711 * No Reboot bit is in General Control register, offset 0xc, 712 * within the SMBus target port, ID 0xc6. 713 */ 714 base_address64 += PCR_REG_OFF(SMB_PORT_ID, SMB_GC_REG); 715 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, base_address64, 716 SMB_GC_SIZE); 717 if (rc != 0) { 718 ichwd_verbose_printf(dev, 719 "Can not set TCO v%d PCR I/O resource (err = %d)\n", 720 id_p->tco_version, rc); 721 } 722 723 break; 724 default: 725 ichwd_verbose_printf(dev, 726 "Can not set unknown TCO v%d memory resource for unknown base address\n", 727 id_p->tco_version); 728 break; 729 } 730} 731 732static int 733ichwd_probe(device_t dev) 734{ 735 struct ichwd_device *id_p; 736 737 /* Do not claim some ISA PnP device by accident. */ 738 if (isa_get_logicalid(dev) != 0) 739 return (ENXIO); 740 741 if (ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p) == NULL && 742 ichwd_find_smb_dev(device_get_parent(dev), &id_p) == NULL) 743 return (ENXIO); 744 745 device_set_desc_copy(dev, id_p->desc); 746 return (0); 747} 748 749static int 750ichwd_smb_attach(device_t dev) 751{ 752 struct ichwd_softc *sc; 753 struct ichwd_device *id_p; 754 device_t isab, pmdev; 755 device_t smb; 756 uint32_t acpi_base; 757 758 sc = device_get_softc(dev); 759 smb = ichwd_find_smb_dev(device_get_parent(dev), &id_p); 760 if (smb == NULL) 761 return (ENXIO); 762 763 sc->ich_version = id_p->ich_version; 764 sc->tco_version = id_p->tco_version; 765 766 /* Allocate TCO control I/O register space. */ 767 sc->tco_rid = 0; 768 sc->tco_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->tco_rid, 769 RF_ACTIVE | RF_SHAREABLE); 770 if (sc->tco_res == NULL) { 771 device_printf(dev, "unable to reserve TCO registers\n"); 772 return (ENXIO); 773 } 774 775 /* 776 * Allocate General Control I/O register in PCH 777 * Private Configuration Space (PCR). 778 */ 779 sc->gc_rid = 1; 780 sc->gc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->gc_rid, 781 RF_ACTIVE | RF_SHAREABLE); 782 if (sc->gc_res == NULL) { 783 device_printf(dev, "unable to reserve hidden P2SB registers\n"); 784 return (ENXIO); 785 } 786 787 /* Get ACPI base address. */ 788 isab = device_get_parent(device_get_parent(dev)); 789 pmdev = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 2); 790 if (pmdev == NULL) { 791 device_printf(dev, "unable to find Power Management device\n"); 792 return (ENXIO); 793 } 794 acpi_base = pci_read_config(pmdev, ICH_PMBASE, 4) & 0xffffff00; 795 if (acpi_base == 0) { 796 device_printf(dev, "ACPI base address is not set\n"); 797 return (ENXIO); 798 } 799 800 /* Allocate SMI control I/O register space. */ 801 sc->smi_rid = 2; 802 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 803 acpi_base + SMI_BASE, acpi_base + SMI_BASE + SMI_LEN - 1, SMI_LEN, 804 RF_ACTIVE | RF_SHAREABLE); 805 if (sc->smi_res == NULL) { 806 device_printf(dev, "unable to reserve SMI registers\n"); 807 return (ENXIO); 808 } 809 810 return (0); 811} 812 813static int 814ichwd_lpc_attach(device_t dev) 815{ 816 struct ichwd_softc *sc; 817 struct ichwd_device *id_p; 818 device_t ich; 819 unsigned int pmbase = 0; 820 821 sc = device_get_softc(dev); 822 823 ich = ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p); 824 if (ich == NULL) 825 return (ENXIO); 826 827 sc->ich = ich; 828 sc->ich_version = id_p->ich_version; 829 sc->tco_version = id_p->tco_version; 830 831 /* get ACPI base address */ 832 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 833 if (pmbase == 0) { 834 device_printf(dev, "ICH PMBASE register is empty\n"); 835 return (ENXIO); 836 } 837 838 /* allocate I/O register space */ 839 sc->smi_rid = 0; 840 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 841 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 842 RF_ACTIVE | RF_SHAREABLE); 843 if (sc->smi_res == NULL) { 844 device_printf(dev, "unable to reserve SMI registers\n"); 845 return (ENXIO); 846 } 847 848 sc->tco_rid = 1; 849 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 850 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 851 RF_ACTIVE | RF_SHAREABLE); 852 if (sc->tco_res == NULL) { 853 device_printf(dev, "unable to reserve TCO registers\n"); 854 return (ENXIO); 855 } 856 857 sc->gcs_rid = 0; 858 if (sc->tco_version >= 2) { 859 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 860 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 861 if (sc->gcs_res == NULL) { 862 device_printf(dev, "unable to reserve GCS registers\n"); 863 return (ENXIO); 864 } 865 } 866 867 return (0); 868} 869 870static int 871ichwd_attach(device_t dev) 872{ 873 struct ichwd_softc *sc; 874 875 sc = device_get_softc(dev); 876 sc->device = dev; 877 878 if (ichwd_lpc_attach(dev) != 0 && ichwd_smb_attach(dev) != 0) 879 goto fail; 880 881 if (ichwd_clear_noreboot(sc) != 0) 882 goto fail; 883 884 /* 885 * Determine if we are coming up after a watchdog-induced reset. Some 886 * BIOSes may clear this bit at bootup, preventing us from reporting 887 * this case on such systems. We clear this bit in ichwd_sts_reset(). 888 */ 889 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 890 device_printf(dev, 891 "resuming after hardware watchdog timeout\n"); 892 893 /* reset the watchdog status registers */ 894 ichwd_sts_reset(sc); 895 896 /* make sure the WDT starts out inactive */ 897 ichwd_tmr_disable(sc); 898 899 /* register the watchdog event handler */ 900 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 901 902 /* disable the SMI handler */ 903 sc->smi_enabled = ichwd_smi_is_enabled(sc); 904 ichwd_smi_disable(sc); 905 906 return (0); 907 fail: 908 sc = device_get_softc(dev); 909 if (sc->tco_res != NULL) 910 bus_release_resource(dev, SYS_RES_IOPORT, 911 sc->tco_rid, sc->tco_res); 912 if (sc->smi_res != NULL) 913 bus_release_resource(dev, SYS_RES_IOPORT, 914 sc->smi_rid, sc->smi_res); 915 if (sc->gcs_res != NULL) 916 bus_release_resource(sc->ich, SYS_RES_MEMORY, 917 sc->gcs_rid, sc->gcs_res); 918 if (sc->gc_res != NULL) 919 bus_release_resource(dev, SYS_RES_MEMORY, 920 sc->gc_rid, sc->gc_res); 921 922 return (ENXIO); 923} 924 925static int 926ichwd_detach(device_t dev) 927{ 928 struct ichwd_softc *sc; 929 930 sc = device_get_softc(dev); 931 932 /* halt the watchdog timer */ 933 if (sc->active) 934 ichwd_tmr_disable(sc); 935 936 /* enable the SMI handler */ 937 if (sc->smi_enabled != 0) 938 ichwd_smi_enable(sc); 939 940 /* deregister event handler */ 941 if (sc->ev_tag != NULL) 942 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 943 sc->ev_tag = NULL; 944 945 /* reset the watchdog status registers */ 946 ichwd_sts_reset(sc); 947 948 /* deallocate I/O register space */ 949 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 950 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 951 952 /* deallocate memory resource */ 953 if (sc->gcs_res) 954 bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid, 955 sc->gcs_res); 956 if (sc->gc_res) 957 bus_release_resource(dev, SYS_RES_MEMORY, sc->gc_rid, 958 sc->gc_res); 959 960 return (0); 961} 962 963static device_method_t ichwd_methods[] = { 964 DEVMETHOD(device_identify, ichwd_identify), 965 DEVMETHOD(device_probe, ichwd_probe), 966 DEVMETHOD(device_attach, ichwd_attach), 967 DEVMETHOD(device_detach, ichwd_detach), 968 DEVMETHOD(device_shutdown, ichwd_detach), 969 {0,0} 970}; 971 972static driver_t ichwd_driver = { 973 "ichwd", 974 ichwd_methods, 975 sizeof(struct ichwd_softc), 976}; 977 978DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 979