1/* SPDX-License-Identifier: BSD-3-Clause */ 2/* Copyright (c) 2021, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31/*$FreeBSD$*/ 32 33#ifndef _ICE_TYPE_H_ 34#define _ICE_TYPE_H_ 35 36#define ETH_ALEN 6 37 38#define ETH_HEADER_LEN 14 39 40#define BIT(a) (1UL << (a)) 41#ifndef BIT_ULL 42#define BIT_ULL(a) (1ULL << (a)) 43#endif /* BIT_ULL */ 44 45#define BITS_PER_BYTE 8 46 47#define _FORCE_ 48 49#define ICE_BYTES_PER_WORD 2 50#define ICE_BYTES_PER_DWORD 4 51#define ICE_MAX_TRAFFIC_CLASS 8 52 53#ifndef MIN_T 54#define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b)) 55#endif 56 57#define IS_ASCII(_ch) ((_ch) < 0x80) 58 59#define STRUCT_HACK_VAR_LEN 60/** 61 * ice_struct_size - size of struct with C99 flexible array member 62 * @ptr: pointer to structure 63 * @field: flexible array member (last member of the structure) 64 * @num: number of elements of that flexible array member 65 */ 66#define ice_struct_size(ptr, field, num) \ 67 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num)) 68 69#define FLEX_ARRAY_SIZE(_ptr, _mem, cnt) ((cnt) * sizeof(_ptr->_mem[0])) 70 71#include "ice_status.h" 72#include "ice_hw_autogen.h" 73#include "ice_devids.h" 74#include "ice_osdep.h" 75#include "ice_bitops.h" /* Must come before ice_controlq.h */ 76#include "ice_controlq.h" 77#include "ice_lan_tx_rx.h" 78#include "ice_flex_type.h" 79#include "ice_protocol_type.h" 80#include "ice_vlan_mode.h" 81 82static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc) 83{ 84 return !!(bitmap & BIT(tc)); 85} 86 87#define DIV_64BIT(n, d) ((n) / (d)) 88 89static inline u64 round_up_64bit(u64 a, u32 b) 90{ 91 return DIV_64BIT(((a) + (b) / 2), (b)); 92} 93 94static inline u32 ice_round_to_num(u32 N, u32 R) 95{ 96 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 97 ((((N) + (R) - 1) / (R)) * (R))); 98} 99 100/* Driver always calls main vsi_handle first */ 101#define ICE_MAIN_VSI_HANDLE 0 102 103/* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 104#define ICE_MS_TO_GTIME(time) ((time) * 1000) 105 106/* Data type manipulation macros. */ 107#define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 108#define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 109#define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 110#define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF)) 111 112/* debug masks - set these bits in hw->debug_mask to control output */ 113#define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */ 114#define ICE_DBG_INIT BIT_ULL(1) 115#define ICE_DBG_RELEASE BIT_ULL(2) 116#define ICE_DBG_FW_LOG BIT_ULL(3) 117#define ICE_DBG_LINK BIT_ULL(4) 118#define ICE_DBG_PHY BIT_ULL(5) 119#define ICE_DBG_QCTX BIT_ULL(6) 120#define ICE_DBG_NVM BIT_ULL(7) 121#define ICE_DBG_LAN BIT_ULL(8) 122#define ICE_DBG_FLOW BIT_ULL(9) 123#define ICE_DBG_DCB BIT_ULL(10) 124#define ICE_DBG_DIAG BIT_ULL(11) 125#define ICE_DBG_FD BIT_ULL(12) 126#define ICE_DBG_SW BIT_ULL(13) 127#define ICE_DBG_SCHED BIT_ULL(14) 128 129#define ICE_DBG_PKG BIT_ULL(16) 130#define ICE_DBG_RES BIT_ULL(17) 131#define ICE_DBG_AQ_MSG BIT_ULL(24) 132#define ICE_DBG_AQ_DESC BIT_ULL(25) 133#define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 134#define ICE_DBG_AQ_CMD BIT_ULL(27) 135#define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \ 136 ICE_DBG_AQ_DESC | \ 137 ICE_DBG_AQ_DESC_BUF | \ 138 ICE_DBG_AQ_CMD) 139 140#define ICE_DBG_USER BIT_ULL(31) 141#define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL 142 143#define IS_UNICAST_ETHER_ADDR(addr) \ 144 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0)) 145 146#define IS_MULTICAST_ETHER_ADDR(addr) \ 147 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1)) 148 149/* Check whether an address is broadcast. */ 150#define IS_BROADCAST_ETHER_ADDR(addr) \ 151 ((bool)((((u16 *)(addr))[0] == ((u16)0xffff)))) 152 153#define IS_ZERO_ETHER_ADDR(addr) \ 154 (((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \ 155 ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \ 156 ((bool)((((u16 *)(addr))[2] == ((u16)0x0))))) 157 158#ifndef IS_ETHER_ADDR_EQUAL 159#define IS_ETHER_ADDR_EQUAL(addr1, addr2) \ 160 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \ 161 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \ 162 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2])))) 163#endif 164 165enum ice_aq_res_ids { 166 ICE_NVM_RES_ID = 1, 167 ICE_SPD_RES_ID, 168 ICE_CHANGE_LOCK_RES_ID, 169 ICE_GLOBAL_CFG_LOCK_RES_ID 170}; 171 172/* FW update timeout definitions are in milliseconds */ 173#define ICE_NVM_TIMEOUT 180000 174#define ICE_CHANGE_LOCK_TIMEOUT 1000 175#define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 176 177enum ice_aq_res_access_type { 178 ICE_RES_READ = 1, 179 ICE_RES_WRITE 180}; 181 182struct ice_driver_ver { 183 u8 major_ver; 184 u8 minor_ver; 185 u8 build_ver; 186 u8 subbuild_ver; 187 u8 driver_string[32]; 188}; 189 190enum ice_fc_mode { 191 ICE_FC_NONE = 0, 192 ICE_FC_RX_PAUSE, 193 ICE_FC_TX_PAUSE, 194 ICE_FC_FULL, 195 ICE_FC_AUTO, 196 ICE_FC_PFC, 197 ICE_FC_DFLT 198}; 199 200enum ice_phy_cache_mode { 201 ICE_FC_MODE = 0, 202 ICE_SPEED_MODE, 203 ICE_FEC_MODE 204}; 205 206enum ice_fec_mode { 207 ICE_FEC_NONE = 0, 208 ICE_FEC_RS, 209 ICE_FEC_BASER, 210 ICE_FEC_AUTO 211}; 212 213struct ice_phy_cache_mode_data { 214 union { 215 enum ice_fec_mode curr_user_fec_req; 216 enum ice_fc_mode curr_user_fc_req; 217 u16 curr_user_speed_req; 218 } data; 219}; 220 221enum ice_set_fc_aq_failures { 222 ICE_SET_FC_AQ_FAIL_NONE = 0, 223 ICE_SET_FC_AQ_FAIL_GET, 224 ICE_SET_FC_AQ_FAIL_SET, 225 ICE_SET_FC_AQ_FAIL_UPDATE 226}; 227 228/* These are structs for managing the hardware information and the operations */ 229/* MAC types */ 230enum ice_mac_type { 231 ICE_MAC_UNKNOWN = 0, 232 ICE_MAC_VF, 233 ICE_MAC_E810, 234 ICE_MAC_GENERIC, 235}; 236 237/* Media Types */ 238enum ice_media_type { 239 ICE_MEDIA_UNKNOWN = 0, 240 ICE_MEDIA_FIBER, 241 ICE_MEDIA_BASET, 242 ICE_MEDIA_BACKPLANE, 243 ICE_MEDIA_DA, 244 ICE_MEDIA_AUI, 245}; 246 247/* Software VSI types. */ 248enum ice_vsi_type { 249 ICE_VSI_PF = 0, 250 ICE_VSI_VF = 1, 251 ICE_VSI_LB = 6, 252}; 253 254struct ice_link_status { 255 /* Refer to ice_aq_phy_type for bits definition */ 256 u64 phy_type_low; 257 u64 phy_type_high; 258 u8 topo_media_conflict; 259 u16 max_frame_size; 260 u16 link_speed; 261 u16 req_speeds; 262 u8 lse_ena; /* Link Status Event notification */ 263 u8 link_info; 264 u8 an_info; 265 u8 ext_info; 266 u8 fec_info; 267 u8 pacing; 268 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 269 * ice_aqc_get_phy_caps structure 270 */ 271 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 272}; 273 274/* Different data queue types: These are mainly for SW consumption. */ 275enum ice_q { 276 ICE_DATA_Q_DOORBELL, 277 ICE_DATA_Q_CMPL, 278 ICE_DATA_Q_QUANTA, 279 ICE_DATA_Q_RX, 280 ICE_DATA_Q_TX, 281}; 282 283/* Different reset sources for which a disable queue AQ call has to be made in 284 * order to clean the Tx scheduler as a part of the reset 285 */ 286enum ice_disq_rst_src { 287 ICE_NO_RESET = 0, 288 ICE_VM_RESET, 289 ICE_VF_RESET, 290}; 291 292/* PHY info such as phy_type, etc... */ 293struct ice_phy_info { 294 struct ice_link_status link_info; 295 struct ice_link_status link_info_old; 296 u64 phy_type_low; 297 u64 phy_type_high; 298 enum ice_media_type media_type; 299 u8 get_link_info; 300 /* Please refer to struct ice_aqc_get_link_status_data to get 301 * detail of enable bit in curr_user_speed_req 302 */ 303 u16 curr_user_speed_req; 304 enum ice_fec_mode curr_user_fec_req; 305 enum ice_fc_mode curr_user_fc_req; 306 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 307}; 308 309#define ICE_MAX_NUM_MIRROR_RULES 64 310 311/* Common HW capabilities for SW use */ 312struct ice_hw_common_caps { 313 /* Write CSR protection */ 314 u64 wr_csr_prot; 315 u32 switching_mode; 316 /* switching mode supported - EVB switching (including cloud) */ 317#define ICE_NVM_IMAGE_TYPE_EVB 0x0 318 319 /* Manageablity mode & supported protocols over MCTP */ 320 u32 mgmt_mode; 321#define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF 322#define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0 323#define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00 324 325 u32 mgmt_protocols_mctp; 326#define ICE_MGMT_MODE_PROTO_RSVD BIT(0) 327#define ICE_MGMT_MODE_PROTO_PLDM BIT(1) 328#define ICE_MGMT_MODE_PROTO_OEM BIT(2) 329#define ICE_MGMT_MODE_PROTO_NC_SI BIT(3) 330 331 u32 os2bmc; 332 u32 valid_functions; 333 /* DCB capabilities */ 334 u32 active_tc_bitmap; 335 u32 maxtc; 336 337 /* RSS related capabilities */ 338 u32 rss_table_size; /* 512 for PFs and 64 for VFs */ 339 u32 rss_table_entry_width; /* RSS Entry width in bits */ 340 341 /* Tx/Rx queues */ 342 u32 num_rxq; /* Number/Total Rx queues */ 343 u32 rxq_first_id; /* First queue ID for Rx queues */ 344 u32 num_txq; /* Number/Total Tx queues */ 345 u32 txq_first_id; /* First queue ID for Tx queues */ 346 347 /* MSI-X vectors */ 348 u32 num_msix_vectors; 349 u32 msix_vector_first_id; 350 351 /* Max MTU for function or device */ 352 u32 max_mtu; 353 354 /* WOL related */ 355 u32 num_wol_proxy_fltr; 356 u32 wol_proxy_vsi_seid; 357 358 /* LED/SDP pin count */ 359 u32 led_pin_num; 360 u32 sdp_pin_num; 361 362 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */ 363#define ICE_MAX_SUPPORTED_GPIO_LED 12 364#define ICE_MAX_SUPPORTED_GPIO_SDP 8 365 u8 led[ICE_MAX_SUPPORTED_GPIO_LED]; 366 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP]; 367 368 /* SR-IOV virtualization */ 369 u8 sr_iov_1_1; /* SR-IOV enabled */ 370 371 /* EVB capabilities */ 372 u8 evb_802_1_qbg; /* Edge Virtual Bridging */ 373 u8 evb_802_1_qbh; /* Bridge Port Extension */ 374 375 u8 dcb; 376 u8 iscsi; 377 u8 mgmt_cem; 378 379 /* WoL and APM support */ 380#define ICE_WOL_SUPPORT_M BIT(0) 381#define ICE_ACPI_PROG_MTHD_M BIT(1) 382#define ICE_PROXY_SUPPORT_M BIT(2) 383 u8 apm_wol_support; 384 u8 acpi_prog_mthd; 385 u8 proxy_support; 386 bool sec_rev_disabled; 387 bool update_disabled; 388 bool nvm_unified_update; 389#define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0) 390#define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1) 391#define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 392}; 393 394/* Function specific capabilities */ 395struct ice_hw_func_caps { 396 struct ice_hw_common_caps common_cap; 397 u32 num_allocd_vfs; /* Number of allocated VFs */ 398 u32 vf_base_id; /* Logical ID of the first VF */ 399 u32 guar_num_vsi; 400}; 401 402/* Device wide capabilities */ 403struct ice_hw_dev_caps { 404 struct ice_hw_common_caps common_cap; 405 u32 num_vfs_exposed; /* Total number of VFs exposed */ 406 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 407 u32 num_funcs; 408}; 409 410/* Information about MAC such as address, etc... */ 411struct ice_mac_info { 412 u8 lan_addr[ETH_ALEN]; 413 u8 perm_addr[ETH_ALEN]; 414 u8 port_addr[ETH_ALEN]; 415 u8 wol_addr[ETH_ALEN]; 416}; 417 418/* PCI bus types */ 419enum ice_bus_type { 420 ice_bus_unknown = 0, 421 ice_bus_pci_express, 422 ice_bus_embedded, /* Is device Embedded versus card */ 423 ice_bus_reserved 424}; 425 426/* PCI bus speeds */ 427enum ice_pcie_bus_speed { 428 ice_pcie_speed_unknown = 0xff, 429 ice_pcie_speed_2_5GT = 0x14, 430 ice_pcie_speed_5_0GT = 0x15, 431 ice_pcie_speed_8_0GT = 0x16, 432 ice_pcie_speed_16_0GT = 0x17 433}; 434 435/* PCI bus widths */ 436enum ice_pcie_link_width { 437 ice_pcie_lnk_width_resrv = 0x00, 438 ice_pcie_lnk_x1 = 0x01, 439 ice_pcie_lnk_x2 = 0x02, 440 ice_pcie_lnk_x4 = 0x04, 441 ice_pcie_lnk_x8 = 0x08, 442 ice_pcie_lnk_x12 = 0x0C, 443 ice_pcie_lnk_x16 = 0x10, 444 ice_pcie_lnk_x32 = 0x20, 445 ice_pcie_lnk_width_unknown = 0xff, 446}; 447 448/* Reset types used to determine which kind of reset was requested. These 449 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 450 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 451 * because its reset source is different than the other types listed. 452 */ 453enum ice_reset_req { 454 ICE_RESET_POR = 0, 455 ICE_RESET_INVAL = 0, 456 ICE_RESET_CORER = 1, 457 ICE_RESET_GLOBR = 2, 458 ICE_RESET_EMPR = 3, 459 ICE_RESET_PFR = 4, 460}; 461 462/* Bus parameters */ 463struct ice_bus_info { 464 enum ice_pcie_bus_speed speed; 465 enum ice_pcie_link_width width; 466 enum ice_bus_type type; 467 u16 domain_num; 468 u16 device; 469 u8 func; 470 u8 bus_num; 471}; 472 473/* Flow control (FC) parameters */ 474struct ice_fc_info { 475 enum ice_fc_mode current_mode; /* FC mode in effect */ 476 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 477}; 478 479/* Option ROM version information */ 480struct ice_orom_info { 481 u8 major; /* Major version of OROM */ 482 u8 patch; /* Patch version of OROM */ 483 u16 build; /* Build version of OROM */ 484 u32 srev; /* Security revision */ 485}; 486 487/* NVM version information */ 488struct ice_nvm_info { 489 u32 eetrack; 490 u32 srev; 491 u8 major; 492 u8 minor; 493}; 494 495/* Minimum Security Revision information */ 496struct ice_minsrev_info { 497 u32 nvm; 498 u32 orom; 499 u8 nvm_valid : 1; 500 u8 orom_valid : 1; 501}; 502 503/* netlist version information */ 504struct ice_netlist_info { 505 u32 major; /* major high/low */ 506 u32 minor; /* minor high/low */ 507 u32 type; /* type high/low */ 508 u32 rev; /* revision high/low */ 509 u32 hash; /* SHA-1 hash word */ 510 u16 cust_ver; /* customer version */ 511}; 512 513/* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 514 * of the flash image. 515 */ 516enum ice_flash_bank { 517 ICE_INVALID_FLASH_BANK, 518 ICE_1ST_FLASH_BANK, 519 ICE_2ND_FLASH_BANK, 520}; 521 522/* Enumeration of which flash bank is desired to read from, either the active 523 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 524 * code which just wants to read the active or inactive flash bank. 525 */ 526enum ice_bank_select { 527 ICE_ACTIVE_FLASH_BANK, 528 ICE_INACTIVE_FLASH_BANK, 529}; 530 531/* information for accessing NVM, OROM, and Netlist flash banks */ 532struct ice_bank_info { 533 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 534 u32 nvm_size; /* Size of NVM bank */ 535 u32 orom_ptr; /* Pointer to 1st OROM bank */ 536 u32 orom_size; /* Size of OROM bank */ 537 u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 538 u32 netlist_size; /* Size of Netlist bank */ 539 enum ice_flash_bank nvm_bank; /* Active NVM bank */ 540 enum ice_flash_bank orom_bank; /* Active OROM bank */ 541 enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 542}; 543 544/* Flash Chip Information */ 545struct ice_flash_info { 546 struct ice_orom_info orom; /* Option ROM version info */ 547 struct ice_nvm_info nvm; /* NVM version information */ 548 struct ice_netlist_info netlist;/* Netlist version info */ 549 struct ice_bank_info banks; /* Flash Bank information */ 550 u16 sr_words; /* Shadow RAM size in words */ 551 u32 flash_size; /* Size of available flash in bytes */ 552 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 553}; 554 555struct ice_link_default_override_tlv { 556 u8 options; 557#define ICE_LINK_OVERRIDE_OPT_M 0x3F 558#define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 559#define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 560#define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 561#define ICE_LINK_OVERRIDE_EN BIT(3) 562#define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 563#define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 564 u8 phy_config; 565#define ICE_LINK_OVERRIDE_PHY_CFG_S 8 566#define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 567#define ICE_LINK_OVERRIDE_PAUSE_M 0x3 568#define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 569#define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 570 u8 fec_options; 571#define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 572 u8 rsvd1; 573 u64 phy_type_low; 574 u64 phy_type_high; 575}; 576 577#define ICE_NVM_VER_LEN 32 578 579/* Max number of port to queue branches w.r.t topology */ 580#define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 581 582#define ice_for_each_traffic_class(_i) \ 583 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 584 585/* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 586 * to driver defined policy for default aggregator 587 */ 588#define ICE_INVAL_TEID 0xFFFFFFFF 589#define ICE_DFLT_AGG_ID 0 590 591struct ice_sched_node { 592 struct ice_sched_node *parent; 593 struct ice_sched_node *sibling; /* next sibling in the same layer */ 594 struct ice_sched_node **children; 595 struct ice_aqc_txsched_elem_data info; 596 u32 agg_id; /* aggregator group ID */ 597 u16 vsi_handle; 598 u8 in_use; /* suspended or in use */ 599 u8 tx_sched_layer; /* Logical Layer (1-9) */ 600 u8 num_children; 601 u8 tc_num; 602 u8 owner; 603#define ICE_SCHED_NODE_OWNER_LAN 0 604#define ICE_SCHED_NODE_OWNER_AE 1 605#define ICE_SCHED_NODE_OWNER_RDMA 2 606}; 607 608/* Access Macros for Tx Sched Elements data */ 609#define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid) 610#define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid) 611#define ICE_TXSCHED_GET_CIR_RL_ID(x) \ 612 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx) 613#define ICE_TXSCHED_GET_EIR_RL_ID(x) \ 614 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx) 615#define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id) 616#define ICE_TXSCHED_GET_CIR_BWALLOC(x) \ 617 LE16_TO_CPU((x)->info.cir_bw.bw_alloc) 618#define ICE_TXSCHED_GET_EIR_BWALLOC(x) \ 619 LE16_TO_CPU((x)->info.eir_bw.bw_alloc) 620 621struct ice_sched_rl_profile { 622 u32 rate; /* In Kbps */ 623 struct ice_aqc_rl_profile_elem info; 624}; 625 626/* The aggregator type determines if identifier is for a VSI group, 627 * aggregator group, aggregator of queues, or queue group. 628 */ 629enum ice_agg_type { 630 ICE_AGG_TYPE_UNKNOWN = 0, 631 ICE_AGG_TYPE_TC, 632 ICE_AGG_TYPE_AGG, /* aggregator */ 633 ICE_AGG_TYPE_VSI, 634 ICE_AGG_TYPE_QG, 635 ICE_AGG_TYPE_Q 636}; 637 638/* Rate limit types */ 639enum ice_rl_type { 640 ICE_UNKNOWN_BW = 0, 641 ICE_MIN_BW, /* for CIR profile */ 642 ICE_MAX_BW, /* for EIR profile */ 643 ICE_SHARED_BW /* for shared profile */ 644}; 645 646#define ICE_SCHED_MIN_BW 500 /* in Kbps */ 647#define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 648#define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 649#define ICE_SCHED_NO_PRIORITY 0 650#define ICE_SCHED_NO_BW_WT 0 651#define ICE_SCHED_DFLT_RL_PROF_ID 0 652#define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 653#define ICE_SCHED_DFLT_BW_WT 4 654#define ICE_SCHED_INVAL_PROF_ID 0xFFFF 655#define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 656 657/* Access Macros for Tx Sched RL Profile data */ 658#define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id) 659#define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size) 660#define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply) 661#define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc) 662#define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode) 663 664/* The following tree example shows the naming conventions followed under 665 * ice_port_info struct for default scheduler tree topology. 666 * 667 * A tree on a port 668 * * ---> root node 669 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8) 670 * * * * * * * * * | 671 * / | 672 * * | 673 * / |-> num_elements (range:1 - 9) 674 * * | implies num_of_layers 675 * / | 676 * (a)* | 677 * 678 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under 679 * (a) as child node where queues get added, add Tx/Rx queue admin commands; 680 * need TEID of (a) to add queues. 681 * 682 * This tree 683 * -> has 8 branches (one for each TC) 684 * -> First branch (TC0) has 4 elements 685 * -> has 4 layers 686 * -> (a) is the topmost layer node created by firmware on branch 0 687 * 688 * Note: Above asterisk tree covers only basic terminology and scenario. 689 * Refer to the documentation for more info. 690 */ 691 692 /* Data structure for saving BW information */ 693enum ice_bw_type { 694 ICE_BW_TYPE_PRIO, 695 ICE_BW_TYPE_CIR, 696 ICE_BW_TYPE_CIR_WT, 697 ICE_BW_TYPE_EIR, 698 ICE_BW_TYPE_EIR_WT, 699 ICE_BW_TYPE_SHARED, 700 ICE_BW_TYPE_CNT /* This must be last */ 701}; 702 703struct ice_bw { 704 u32 bw; 705 u16 bw_alloc; 706}; 707 708struct ice_bw_type_info { 709 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT); 710 u8 generic; 711 struct ice_bw cir_bw; 712 struct ice_bw eir_bw; 713 u32 shared_bw; 714}; 715 716/* VSI queue context structure for given TC */ 717struct ice_q_ctx { 718 u16 q_handle; 719 u32 q_teid; 720 /* bw_t_info saves queue BW information */ 721 struct ice_bw_type_info bw_t_info; 722}; 723 724/* VSI type list entry to locate corresponding VSI/aggregator nodes */ 725struct ice_sched_vsi_info { 726 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 727 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 728 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 729 /* bw_t_info saves VSI BW information */ 730 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 731}; 732 733/* CEE or IEEE 802.1Qaz ETS Configuration data */ 734struct ice_dcb_ets_cfg { 735 u8 willing; 736 u8 cbs; 737 u8 maxtcs; 738 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 739 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 740 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 741}; 742 743/* CEE or IEEE 802.1Qaz PFC Configuration data */ 744struct ice_dcb_pfc_cfg { 745 u8 willing; 746 u8 mbc; 747 u8 pfccap; 748 u8 pfcena; 749}; 750 751/* CEE or IEEE 802.1Qaz Application Priority data */ 752struct ice_dcb_app_priority_table { 753 u16 prot_id; 754 u8 priority; 755 u8 selector; 756}; 757 758#define ICE_MAX_USER_PRIORITY 8 759#define ICE_DCBX_MAX_APPS 32 760#define ICE_LLDPDU_SIZE 1500 761#define ICE_TLV_STATUS_OPER 0x1 762#define ICE_TLV_STATUS_SYNC 0x2 763#define ICE_TLV_STATUS_ERR 0x4 764#define ICE_APP_PROT_ID_FCOE 0x8906 765#define ICE_APP_PROT_ID_ISCSI 0x0cbc 766#define ICE_APP_PROT_ID_ISCSI_860 0x035c 767#define ICE_APP_PROT_ID_FIP 0x8914 768#define ICE_APP_SEL_ETHTYPE 0x1 769#define ICE_APP_SEL_TCPIP 0x2 770#define ICE_CEE_APP_SEL_ETHTYPE 0x0 771#define ICE_CEE_APP_SEL_TCPIP 0x1 772 773struct ice_dcbx_cfg { 774 u32 numapps; 775 u32 tlv_status; /* CEE mode TLV status */ 776 struct ice_dcb_ets_cfg etscfg; 777 struct ice_dcb_ets_cfg etsrec; 778 struct ice_dcb_pfc_cfg pfc; 779 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 780 u8 dcbx_mode; 781#define ICE_DCBX_MODE_CEE 0x1 782#define ICE_DCBX_MODE_IEEE 0x2 783 u8 app_mode; 784#define ICE_DCBX_APPS_NON_WILLING 0x1 785}; 786 787struct ice_qos_cfg { 788 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 789 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 790 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 791 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 792 u8 is_sw_lldp : 1; 793}; 794 795struct ice_port_info { 796 struct ice_sched_node *root; /* Root Node per Port */ 797 struct ice_hw *hw; /* back pointer to HW instance */ 798 u32 last_node_teid; /* scheduler last node info */ 799 u16 sw_id; /* Initial switch ID belongs to port */ 800 u16 pf_vf_num; 801 u8 port_state; 802#define ICE_SCHED_PORT_STATE_INIT 0x0 803#define ICE_SCHED_PORT_STATE_READY 0x1 804 u8 lport; 805#define ICE_LPORT_MASK 0xff 806 u16 dflt_tx_vsi_rule_id; 807 u16 dflt_tx_vsi_num; 808 u16 dflt_rx_vsi_rule_id; 809 u16 dflt_rx_vsi_num; 810 struct ice_fc_info fc; 811 struct ice_mac_info mac; 812 struct ice_phy_info phy; 813 struct ice_lock sched_lock; /* protect access to TXSched tree */ 814 struct ice_sched_node * 815 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 816 struct ice_bw_type_info root_node_bw_t_info; 817 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 818 struct ice_qos_cfg qos_cfg; 819 u8 is_vf:1; 820}; 821 822struct ice_switch_info { 823 struct LIST_HEAD_TYPE vsi_list_map_head; 824 struct ice_sw_recipe *recp_list; 825 u16 prof_res_bm_init; 826 u16 max_used_prof_index; 827 828 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); 829}; 830 831/* Enum defining the different states of the mailbox snapshot in the 832 * PF-VF mailbox overflow detection algorithm. The snapshot can be in 833 * states: 834 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot 835 * within the mailbox buffer. 836 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot 837 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the 838 * mailbox and mark any VFs sending more messages than the threshold limit set. 839 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. 840 */ 841enum ice_mbx_snapshot_state { 842 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, 843 ICE_MAL_VF_DETECT_STATE_TRAVERSE, 844 ICE_MAL_VF_DETECT_STATE_DETECT, 845 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, 846}; 847 848/* Structure to hold information of the static snapshot and the mailbox 849 * buffer data used to generate and track the snapshot. 850 * 1. state: the state of the mailbox snapshot in the malicious VF 851 * detection state handler ice_mbx_vf_state_handler() 852 * 2. head : head of the mailbox snapshot in a circular mailbox buffer 853 * 3. tail : tail of the mailbox snapshot in a circular mailbox buffer 854 * 4. num_iterations: number of messages traversed in circular mailbox buffer 855 * 5. num_msg_proc: number of messages processed in mailbox 856 * 6. num_pending_arq: number of pending asynchronous messages 857 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently 858 * serviced work item or interrupt. 859 */ 860struct ice_mbx_snap_buffer_data { 861 enum ice_mbx_snapshot_state state; 862 u32 head; 863 u32 tail; 864 u32 num_iterations; 865 u16 num_msg_proc; 866 u16 num_pending_arq; 867 u16 max_num_msgs_mbx; 868}; 869 870/* Structure to track messages sent by VFs on mailbox: 871 * 1. vf_cntr : a counter array of VFs to track the number of 872 * asynchronous messages sent by each VF 873 * 2. vfcntr_len : number of entries in VF counter array 874 */ 875struct ice_mbx_vf_counter { 876 u32 *vf_cntr; 877 u32 vfcntr_len; 878}; 879 880/* Structure to hold data relevant to the captured static snapshot 881 * of the PF-VF mailbox. 882 */ 883struct ice_mbx_snapshot { 884 struct ice_mbx_snap_buffer_data mbx_buf; 885 struct ice_mbx_vf_counter mbx_vf; 886}; 887 888/* Structure to hold data to be used for capturing or updating a 889 * static snapshot. 890 * 1. num_msg_proc: number of messages processed in mailbox 891 * 2. num_pending_arq: number of pending asynchronous messages 892 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently 893 * serviced work item or interrupt. 894 * 4. async_watermark_val: An upper threshold set by caller to determine 895 * if the pending arq count is large enough to assume that there is 896 * the possibility of a mailicious VF. 897 */ 898struct ice_mbx_data { 899 u16 num_msg_proc; 900 u16 num_pending_arq; 901 u16 max_num_msgs_mbx; 902 u16 async_watermark_val; 903}; 904 905/* Port hardware description */ 906struct ice_hw { 907 u8 *hw_addr; 908 void *back; 909 struct ice_aqc_layer_props *layer_info; 910 struct ice_port_info *port_info; 911 /* 2D Array for each Tx Sched RL Profile type */ 912 struct ice_sched_rl_profile **cir_profiles; 913 struct ice_sched_rl_profile **eir_profiles; 914 struct ice_sched_rl_profile **srl_profiles; 915 /* PSM clock frequency for calculating RL profile params */ 916 u32 psm_clk_freq; 917 u64 debug_mask; /* BITMAP for debug mask */ 918 enum ice_mac_type mac_type; 919 920 /* pci info */ 921 u16 device_id; 922 u16 vendor_id; 923 u16 subsystem_device_id; 924 u16 subsystem_vendor_id; 925 u8 revision_id; 926 927 u8 pf_id; /* device profile info */ 928 929 u16 max_burst_size; /* driver sets this value */ 930 931 /* Tx Scheduler values */ 932 u8 num_tx_sched_layers; 933 u8 num_tx_sched_phys_layers; 934 u8 flattened_layers; 935 u8 max_cgds; 936 u8 sw_entry_point_layer; 937 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 938 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */ 939 /* List contain profile ID(s) and other params per layer */ 940 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 941 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 942 u8 evb_veb; /* true for VEB, false for VEPA */ 943 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 944 struct ice_bus_info bus; 945 struct ice_flash_info flash; 946 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 947 struct ice_hw_func_caps func_caps; /* function capabilities */ 948 949 struct ice_switch_info *switch_info; /* switch filter lists */ 950 951 /* Control Queue info */ 952 struct ice_ctl_q_info adminq; 953 struct ice_ctl_q_info mailboxq; 954 u8 api_branch; /* API branch version */ 955 u8 api_maj_ver; /* API major version */ 956 u8 api_min_ver; /* API minor version */ 957 u8 api_patch; /* API patch version */ 958 u8 fw_branch; /* firmware branch version */ 959 u8 fw_maj_ver; /* firmware major version */ 960 u8 fw_min_ver; /* firmware minor version */ 961 u8 fw_patch; /* firmware patch version */ 962 u32 fw_build; /* firmware build number */ 963 964/* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 965 * register. Used for determining the ITR/INTRL granularity during 966 * initialization. 967 */ 968#define ICE_MAX_AGG_BW_200G 0x0 969#define ICE_MAX_AGG_BW_100G 0X1 970#define ICE_MAX_AGG_BW_50G 0x2 971#define ICE_MAX_AGG_BW_25G 0x3 972 /* ITR granularity for different speeds */ 973#define ICE_ITR_GRAN_ABOVE_25 2 974#define ICE_ITR_GRAN_MAX_25 4 975 /* ITR granularity in 1 us */ 976 u8 itr_gran; 977 /* INTRL granularity for different speeds */ 978#define ICE_INTRL_GRAN_ABOVE_25 4 979#define ICE_INTRL_GRAN_MAX_25 8 980 /* INTRL granularity in 1 us */ 981 u8 intrl_gran; 982 983 u8 ucast_shared; /* true if VSIs can share unicast addr */ 984 985#define ICE_PHY_PER_NAC 1 986#define ICE_MAX_QUAD 2 987#define ICE_NUM_QUAD_TYPE 2 988#define ICE_PORTS_PER_QUAD 4 989#define ICE_PHY_0_LAST_QUAD 1 990#define ICE_PORTS_PER_PHY 8 991#define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY 992 993 /* Active package version (currently active) */ 994 struct ice_pkg_ver active_pkg_ver; 995 u32 active_track_id; 996 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 997 u8 active_pkg_in_nvm; 998 999 enum ice_aq_err pkg_dwnld_status; 1000 1001 /* Driver's package ver - (from the Ice Metadata section) */ 1002 struct ice_pkg_ver pkg_ver; 1003 u8 pkg_name[ICE_PKG_NAME_SIZE]; 1004 1005 /* Driver's Ice segment format version and id (from the Ice seg) */ 1006 struct ice_pkg_ver ice_seg_fmt_ver; 1007 u8 ice_seg_id[ICE_SEG_ID_SIZE]; 1008 1009 /* Pointer to the ice segment */ 1010 struct ice_seg *seg; 1011 1012 /* Pointer to allocated copy of pkg memory */ 1013 u8 *pkg_copy; 1014 u32 pkg_size; 1015 1016 /* tunneling info */ 1017 struct ice_lock tnl_lock; 1018 struct ice_tunnel_table tnl; 1019 1020 /* HW block tables */ 1021 struct ice_blk_info blk[ICE_BLK_COUNT]; 1022 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 1023 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT]; 1024 struct ice_lock rss_locks; /* protect RSS configuration */ 1025 struct LIST_HEAD_TYPE rss_list_head; 1026 struct ice_mbx_snapshot mbx_snapshot; 1027 struct ice_vlan_mode_ops vlan_mode_ops; 1028}; 1029 1030/* Statistics collected by each port, VSI, VEB, and S-channel */ 1031struct ice_eth_stats { 1032 u64 rx_bytes; /* gorc */ 1033 u64 rx_unicast; /* uprc */ 1034 u64 rx_multicast; /* mprc */ 1035 u64 rx_broadcast; /* bprc */ 1036 u64 rx_discards; /* rdpc */ 1037 u64 rx_unknown_protocol; /* rupp */ 1038 u64 tx_bytes; /* gotc */ 1039 u64 tx_unicast; /* uptc */ 1040 u64 tx_multicast; /* mptc */ 1041 u64 tx_broadcast; /* bptc */ 1042 u64 tx_discards; /* tdpc */ 1043 u64 tx_errors; /* tepc */ 1044 u64 rx_no_desc; /* repc */ 1045 u64 rx_errors; /* repc */ 1046}; 1047 1048#define ICE_MAX_UP 8 1049 1050/* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */ 1051struct ice_veb_up_stats { 1052 u64 up_rx_pkts[ICE_MAX_UP]; 1053 u64 up_rx_bytes[ICE_MAX_UP]; 1054 u64 up_tx_pkts[ICE_MAX_UP]; 1055 u64 up_tx_bytes[ICE_MAX_UP]; 1056}; 1057 1058/* Statistics collected by the MAC */ 1059struct ice_hw_port_stats { 1060 /* eth stats collected by the port */ 1061 struct ice_eth_stats eth; 1062 /* additional port specific stats */ 1063 u64 tx_dropped_link_down; /* tdold */ 1064 u64 crc_errors; /* crcerrs */ 1065 u64 illegal_bytes; /* illerrc */ 1066 u64 error_bytes; /* errbc */ 1067 u64 mac_local_faults; /* mlfc */ 1068 u64 mac_remote_faults; /* mrfc */ 1069 u64 rx_len_errors; /* rlec */ 1070 u64 link_xon_rx; /* lxonrxc */ 1071 u64 link_xoff_rx; /* lxoffrxc */ 1072 u64 link_xon_tx; /* lxontxc */ 1073 u64 link_xoff_tx; /* lxofftxc */ 1074 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1075 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1076 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1077 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1078 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1079 u64 rx_size_64; /* prc64 */ 1080 u64 rx_size_127; /* prc127 */ 1081 u64 rx_size_255; /* prc255 */ 1082 u64 rx_size_511; /* prc511 */ 1083 u64 rx_size_1023; /* prc1023 */ 1084 u64 rx_size_1522; /* prc1522 */ 1085 u64 rx_size_big; /* prc9522 */ 1086 u64 rx_undersize; /* ruc */ 1087 u64 rx_fragments; /* rfc */ 1088 u64 rx_oversize; /* roc */ 1089 u64 rx_jabber; /* rjc */ 1090 u64 tx_size_64; /* ptc64 */ 1091 u64 tx_size_127; /* ptc127 */ 1092 u64 tx_size_255; /* ptc255 */ 1093 u64 tx_size_511; /* ptc511 */ 1094 u64 tx_size_1023; /* ptc1023 */ 1095 u64 tx_size_1522; /* ptc1522 */ 1096 u64 tx_size_big; /* ptc9522 */ 1097 u64 mac_short_pkt_dropped; /* mspdc */ 1098 /* EEE LPI */ 1099 u32 tx_lpi_status; 1100 u32 rx_lpi_status; 1101 u64 tx_lpi_count; /* etlpic */ 1102 u64 rx_lpi_count; /* erlpic */ 1103}; 1104 1105enum ice_sw_fwd_act_type { 1106 ICE_FWD_TO_VSI = 0, 1107 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */ 1108 ICE_FWD_TO_Q, 1109 ICE_FWD_TO_QGRP, 1110 ICE_DROP_PACKET, 1111 ICE_INVAL_ACT 1112}; 1113 1114struct ice_aq_get_set_rss_lut_params { 1115 u16 vsi_handle; /* software VSI handle */ 1116 u16 lut_size; /* size of the LUT buffer */ 1117 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */ 1118 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ 1119 u8 global_lut_id; /* only valid when lut_type is global */ 1120}; 1121 1122/* Checksum and Shadow RAM pointers */ 1123#define ICE_SR_NVM_CTRL_WORD 0x00 1124#define ICE_SR_PHY_ANALOG_PTR 0x04 1125#define ICE_SR_OPTION_ROM_PTR 0x05 1126#define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 1127#define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07 1128#define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 1129#define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09 1130#define ICE_SR_EMP_IMAGE_PTR 0x0B 1131#define ICE_SR_PE_IMAGE_PTR 0x0C 1132#define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D 1133#define ICE_SR_MNG_CFG_PTR 0x0E 1134#define ICE_SR_EMP_MODULE_PTR 0x0F 1135#define ICE_SR_PBA_BLOCK_PTR 0x16 1136#define ICE_SR_BOOT_CFG_PTR 0x132 1137#define ICE_SR_NVM_WOL_CFG 0x19 1138#define ICE_NVM_OROM_VER_OFF 0x02 1139#define ICE_SR_NVM_DEV_STARTER_VER 0x18 1140#define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27 1141#define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28 1142#define ICE_SR_NVM_MAP_VER 0x29 1143#define ICE_SR_NVM_IMAGE_VER 0x2A 1144#define ICE_SR_NVM_STRUCTURE_VER 0x2B 1145#define ICE_SR_NVM_EETRACK_LO 0x2D 1146#define ICE_SR_NVM_EETRACK_HI 0x2E 1147#define ICE_NVM_VER_LO_SHIFT 0 1148#define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 1149#define ICE_NVM_VER_HI_SHIFT 12 1150#define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 1151#define ICE_OEM_EETRACK_ID 0xffffffff 1152#define ICE_OROM_VER_PATCH_SHIFT 0 1153#define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 1154#define ICE_OROM_VER_BUILD_SHIFT 8 1155#define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 1156#define ICE_OROM_VER_SHIFT 24 1157#define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 1158#define ICE_SR_VPD_PTR 0x2F 1159#define ICE_SR_PXE_SETUP_PTR 0x30 1160#define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31 1161#define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34 1162#define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35 1163#define ICE_SR_VLAN_CFG_PTR 0x37 1164#define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1165#define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1166#define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1167#define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1168#define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D 1169#define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1170#define ICE_SR_SW_CHECKSUM_WORD 0x3F 1171#define ICE_SR_PFA_PTR 0x40 1172#define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41 1173#define ICE_SR_1ST_NVM_BANK_PTR 0x42 1174#define ICE_SR_NVM_BANK_SIZE 0x43 1175#define ICE_SR_1ST_OROM_BANK_PTR 0x44 1176#define ICE_SR_OROM_BANK_SIZE 0x45 1177#define ICE_SR_NETLIST_BANK_PTR 0x46 1178#define ICE_SR_NETLIST_BANK_SIZE 0x47 1179#define ICE_SR_EMP_SR_SETTINGS_PTR 0x48 1180#define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D 1181#define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E 1182#define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 1183#define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118 1184 1185/* CSS Header words */ 1186#define ICE_NVM_CSS_SREV_L 0x14 1187#define ICE_NVM_CSS_SREV_H 0x15 1188 1189/* Length of CSS header section in words */ 1190#define ICE_CSS_HEADER_LENGTH 330 1191 1192/* Offset of Shadow RAM copy in the NVM bank area. */ 1193#define ICE_NVM_SR_COPY_WORD_OFFSET ROUND_UP(ICE_CSS_HEADER_LENGTH, 32) 1194 1195/* Size in bytes of Option ROM trailer */ 1196#define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) 1197 1198/* The Link Topology Netlist section is stored as a series of words. It is 1199 * stored in the NVM as a TLV, with the first two words containing the type 1200 * and length. 1201 */ 1202#define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 1203#define ICE_NETLIST_TYPE_OFFSET 0x0000 1204#define ICE_NETLIST_LEN_OFFSET 0x0001 1205 1206/* The Link Topology section follows the TLV header. When reading the netlist 1207 * using ice_read_netlist_module, we need to account for the 2-word TLV 1208 * header. 1209 */ 1210#define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 1211 1212#define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 1213#define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 1214 1215#define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0) 1216 1217/* The Netlist ID Block is located after all of the Link Topology nodes. */ 1218#define ICE_NETLIST_ID_BLK_SIZE 0x30 1219#define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 1220 1221/* netlist ID block field offsets (word offsets) */ 1222#define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 1223#define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 1224#define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 1225#define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 1226#define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 1227#define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 1228#define ICE_NETLIST_ID_BLK_REV_LOW 0x08 1229#define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 1230#define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 1231#define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 1232 1233/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1234#define ICE_SR_VPD_SIZE_WORDS 512 1235#define ICE_SR_PCIE_ALT_SIZE_WORDS 512 1236#define ICE_SR_CTRL_WORD_1_S 0x06 1237#define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 1238#define ICE_SR_CTRL_WORD_VALID 0x1 1239#define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 1240#define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 1241#define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 1242 1243#define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 1244 1245/* Shadow RAM related */ 1246#define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 1247#define ICE_SR_BUF_ALIGNMENT 4096 1248#define ICE_SR_WORDS_IN_1KB 512 1249/* Checksum should be calculated such that after adding all the words, 1250 * including the checksum word itself, the sum should be 0xBABA. 1251 */ 1252#define ICE_SR_SW_CHECKSUM_BASE 0xBABA 1253 1254/* Link override related */ 1255#define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 1256#define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1257#define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1258#define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1259#define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1260#define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1261#define ICE_FW_API_LINK_OVERRIDE_MIN 5 1262#define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1263 1264#define ICE_PBA_FLAG_DFLT 0xFAFA 1265/* Hash redirection LUT for VSI - maximum array size */ 1266#define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 1267 1268/* 1269 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register. 1270 * This is needed to determine the BAR0 space for the VFs 1271 */ 1272#define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0 1273#define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1 1274#define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2 1275 1276/* AQ API version for LLDP_FILTER_CONTROL */ 1277#define ICE_FW_API_LLDP_FLTR_MAJ 1 1278#define ICE_FW_API_LLDP_FLTR_MIN 7 1279#define ICE_FW_API_LLDP_FLTR_PATCH 1 1280#endif /* _ICE_TYPE_H_ */ 1281