1/*-
2 * Copyright (c) 2015 Semihalf
3 * Copyright (c) 2015 Stormshield
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 *
29 */
30
31#ifndef _E6000SWREG_H_
32#define	_E6000SWREG_H_
33
34struct atu_opt {
35	uint16_t mac_01;
36	uint16_t mac_23;
37	uint16_t mac_45;
38	uint16_t fid;
39};
40
41/*
42 * Definitions for the Marvell 88E6000 series Ethernet Switch.
43 */
44
45/* Switch IDs. */
46#define	MV88E6141	0x3400
47#define	MV88E6341	0x3410
48#define	MV88E6352	0x3520
49#define	MV88E6172	0x1720
50#define	MV88E6176	0x1760
51#define	MV88E6190	0x1900
52
53#define	MVSWITCH(_sc, id)	((_sc)->swid == (id))
54#define	MVSWITCH_MULTICHIP(_sc)	((_sc)->sw_addr != 0)
55
56/*
57 * Switch Registers
58 */
59#define	REG_GLOBAL			0x1b
60#define	REG_GLOBAL2			0x1c
61#define	REG_PORT(_sc, p)		((MVSWITCH((_sc), MV88E6190) ? 0 : 0x10) + (p))
62
63#define	REG_NUM_MAX			31
64
65/*
66 * Per-Port Switch Registers
67 */
68#define	PORT_STATUS			0x0
69#define	PORT_STATUS_SPEED_MASK		0x300
70#define	PORT_STATUS_SPEED_10		0
71#define	PORT_STATUS_SPEED_100		1
72#define	PORT_STATUS_SPEED_1000		2
73#define	PORT_STATUS_DUPLEX_MASK		(1 << 10)
74#define	PORT_STATUS_LINK_MASK		(1 << 11)
75#define	PORT_STATUS_PHY_DETECT_MASK	(1 << 12)
76
77#define	PSC_CONTROL			0x1
78#define	PSC_CONTROL_FORCED_SPD		(1 << 13)
79#define	PSC_CONTROL_ALT_SPD		(1 << 12)
80#define	PSC_CONTROL_EEE_ON		(1 << 9)
81#define	PSC_CONTROL_FORCED_EEE		(1 << 8)
82#define	PSC_CONTROL_FC_ON		(1 << 7)
83#define	PSC_CONTROL_FORCED_FC		(1 << 6)
84#define	PSC_CONTROL_LINK_UP		(1 << 5)
85#define	PSC_CONTROL_FORCED_LINK		(1 << 4)
86#define	PSC_CONTROL_FULLDPX		(1 << 3)
87#define	PSC_CONTROL_FORCED_DPX		(1 << 2)
88#define	PSC_CONTROL_SPD10G		0x3
89#define	PSC_CONTROL_SPD2500		PSC_CONTROL_SPD10G
90#define	PSC_CONTROL_SPD1000		0x2
91#define	SWITCH_ID			0x3
92#define	PORT_CONTROL			0x4
93#define	PORT_CONTROL1			0x5
94#define	 PORT_CONTROL1_LAG_PORT		(1 << 14)
95#define	 PORT_CONTROL1_LAG_ID_MASK	0xf
96#define	 PORT_CONTROL1_LAG_ID_SHIFT	8
97#define	 PORT_CONTROL1_FID_MASK		0xf
98#define	PORT_VLAN_MAP			0x6
99#define	PORT_VID			0x7
100#define	PORT_CONTROL2			0x8
101#define	PORT_ASSOCIATION_VECTOR		0xb
102#define	PORT_ATU_CTRL			0xc
103#define	RX_COUNTER			0x12
104#define	TX_COUNTER			0x13
105
106#define	PORT_MASK(_sc)			0x7f
107#define	PORT_VID_DEF_VID		0
108#define	PORT_VID_DEF_VID_MASK		0xfff
109#define	PORT_VID_PRIORITY_MASK		0xc00
110
111#define	PORT_CONTROL_DISABLED		0
112#define	PORT_CONTROL_BLOCKING		1
113#define	PORT_CONTROL_LEARNING		2
114#define	PORT_CONTROL_FORWARDING		3
115#define	PORT_CONTROL_ENABLE		3
116#define	PORT_CONTROL_FRAME		0x0300
117#define	PORT_CONTROL_EGRESS		0x3000
118#define	PORT_CONTROL2_DOT1Q		0x0c00
119#define	PORT_CONTROL2_DISC_TAGGED	(1 << 9)
120#define	PORT_CONTROL2_DISC_UNTAGGED	(1 << 8)
121
122/* PORT_VLAN fields */
123#define	PORT_VLAN_MAP_FID		12
124#define	PORT_VLAN_MAP_FID_MASK		0xf000
125
126/*
127 * Switch Global Register 1 accessed via REG_GLOBAL_ADDR
128 */
129#define	SWITCH_GLOBAL_STATUS		0
130#define	SWITCH_GLOBAL_STATUS_IR		(1 << 11)
131#define	SWITCH_GLOBAL_CONTROL		4
132#define	SWITCH_GLOBAL_CONTROL2		28
133
134#define	MONITOR_CONTROL			26
135
136/* VTU operation */
137#define	VTU_FID				2
138#define	VTU_OPERATION			5
139#define	VTU_VID				6
140#define	VTU_DATA			7
141#define	VTU_DATA2			8
142
143#define	VTU_FID_MASK(_sc)		(MVSWITCH((_sc), MV88E6190) ? 0xfff : 0xff)
144#define	VTU_FID_POLICY			(1 << 12)
145#define	VTU_PORT_UNMODIFIED		0
146#define	VTU_PORT_UNTAGGED		1
147#define	VTU_PORT_TAGGED			2
148#define	VTU_PORT_DISCARD		3
149#define	VTU_PPREG(_sc)			(MVSWITCH((_sc), MV88E6190) ? 8 : 4)
150#define	VTU_PORT(_sc, p)		(((p) % VTU_PPREG(_sc)) * (16 / VTU_PPREG(_sc)))
151#define	VTU_PORT_MASK			3
152#define	VTU_BUSY			(1 << 15)
153#define	VTU_VID_VALID			(1 << 12)
154#define	VTU_VID_MASK			0xfff
155
156/* VTU opcodes */
157#define	VTU_OP_MASK			(7 << 12)
158#define	VTU_NOP				(0 << 12)
159#define	VTU_FLUSH			(1 << 12)
160#define	VTU_LOAD			(3 << 12)
161#define	VTU_PURGE			(3 << 12)
162#define	VTU_GET_NEXT			(4 << 12)
163#define	STU_LOAD			(5 << 12)
164#define	STU_PURGE			(5 << 12)
165#define	STU_GET_NEXT			(6 << 12)
166#define	VTU_GET_VIOLATION_DATA		(7 << 12)
167#define	VTU_CLEAR_VIOLATION_DATA	(7 << 12)
168
169/* ATU operation */
170#define	ATU_FID				1
171#define	ATU_CONTROL			10
172#define	ATU_OPERATION			11
173#define	ATU_DATA			12
174#define	ATU_MAC_ADDR01			13
175#define	ATU_MAC_ADDR23			14
176#define	ATU_MAC_ADDR45			15
177
178#define	ATU_DATA_LAG                    (1 << 15)
179#define	ATU_PORT_MASK(_sc)		(MVSWITCH((_sc), MV88E6190) ? 0xfff0 : 0xff0)
180#define	ATU_PORT_SHIFT                  4
181#define	ATU_LAG_MASK                    0xf0
182#define	ATU_LAG_SHIFT                   4
183#define	ATU_STATE_MASK                  0xf
184#define	ATU_UNIT_BUSY			(1 << 15)
185#define	ENTRY_STATE			0xf
186
187/* ATU_CONTROL fields */
188#define	ATU_CONTROL_AGETIME		4
189#define	ATU_CONTROL_AGETIME_MASK	0xff0
190#define	ATU_CONTROL_LEARN2ALL		3
191
192/* ATU opcode */
193#define	ATU_OP_MASK                     (7 << 12)
194#define	NO_OPERATION                    (0 << 12)
195#define	FLUSH_ALL                       (1 << 12)
196#define	FLUSH_NON_STATIC                (2 << 12)
197#define	LOAD_FROM_FIB                   (3 << 12)
198#define	PURGE_FROM_FIB                  (3 << 12)
199#define	GET_NEXT_IN_FIB                 (4 << 12)
200#define	FLUSH_ALL_IN_FIB                (5 << 12)
201#define	FLUSH_NON_STATIC_IN_FIB         (6 << 12)
202#define	GET_VIOLATION_DATA              (7 << 12)
203#define	CLEAR_VIOLATION_DATA            (7 << 12)
204
205/* ATU Stats */
206#define	COUNT_ALL			(0 << 0)
207
208/*
209 * Switch Global Register 2 accessed via REG_GLOBAL2_ADDR
210 */
211#define	MGMT_EN_2x			2
212#define	MGMT_EN_0x			3
213#define	SWITCH_MGMT			5
214#define	LAG_MASK			7
215#define	LAG_MAPPING			8
216#define	ATU_STATS			14
217
218#define	MGMT_EN_ALL			0xffff
219#define	LAG_UPDATE			(1 << 15)
220#define	LAG_MASKNUM_SHIFT		12
221#define	LAGID_SHIFT			11
222
223/* SWITCH_MGMT fields */
224
225#define	SWITCH_MGMT_PRI			0
226#define	SWITCH_MGMT_PRI_MASK		7
227#define	SWITCH_MGMT_RSVD2CPU		3
228#define	SWITCH_MGMT_FC_PRI		4
229#define	SWITCH_MGMT_FC_PRI_MASK		(7 << 4)
230#define	SWITCH_MGMT_FORCEFLOW		7
231
232/* ATU_STATS fields */
233
234#define	ATU_STATS_BIN			14
235#define	ATU_STATS_FLAG			12
236
237/* Offset of SMI registers in multi-chip setup. */
238#define	SMI_CMD				0
239#define	SMI_DATA			1
240
241/*
242 * 'Switch Global Registers 2' (REG_GLOBAL2).
243 */
244
245/* EEPROM registers */
246#define	EEPROM_CMD			0x14
247#define	 EEPROM_BUSY			(1 << 15)
248#define	 EEPROM_READ_CMD		(4 << 12)
249#define	 EEPROM_WRITE_CMD		(3 << 12)
250#define	 EEPROM_WRITE_EN		(1 << 10)
251#define	 EEPROM_DATA_MASK		0xff
252#define	EEPROM_ADDR			0x15
253
254/* PHY registers */
255#define	SMI_PHY_CMD_REG			0x18
256#define	 SMI_CMD_BUSY			(1 << 15)
257#define	 SMI_CMD_MODE_C22		(1 << 12)
258#define	 SMI_CMD_C22_WRITE		(1 << 10)
259#define	 SMI_CMD_C22_READ		(2 << 10)
260#define	 SMI_CMD_OP_C22_WRITE						\
261	 (SMI_CMD_C22_WRITE | SMI_CMD_BUSY | SMI_CMD_MODE_C22)
262#define	 SMI_CMD_OP_C22_READ						\
263	 (SMI_CMD_C22_READ | SMI_CMD_BUSY | SMI_CMD_MODE_C22)
264#define	 SMI_CMD_C45			(0 << 12)
265#define	 SMI_CMD_C45_ADDR		(0 << 10)
266#define	 SMI_CMD_C45_WRITE		(1 << 10)
267#define	 SMI_CMD_C45_READ		(3 << 10)
268#define	 SMI_CMD_OP_C45_ADDR						\
269	 (SMI_CMD_C45_ADDR | SMI_CMD_BUSY | SMI_CMD_C45)
270#define	 SMI_CMD_OP_C45_WRITE						\
271	 (SMI_CMD_C45_WRITE | SMI_CMD_BUSY | SMI_CMD_C45)
272#define	 SMI_CMD_OP_C45_READ						\
273	 (SMI_CMD_C45_READ | SMI_CMD_BUSY | SMI_CMD_C45)
274#define	 SMI_CMD_DEV_ADDR		5
275#define	 SMI_CMD_DEV_ADDR_MASK		0x3e0
276#define	 SMI_CMD_REG_ADDR_MASK		0x1f
277#define	SMI_PHY_DATA_REG		0x19
278#define	 PHY_DATA_MASK			0xffff
279
280#define	PHY_PAGE_REG			22
281
282/*
283 * Scratch and Misc register accessed via
284 * 'Switch Global Registers' (REG_GLOBAL2)
285 */
286#define	SCR_AND_MISC_REG		0x1a
287
288#define	SCR_AND_MISC_PTR_CFG		0x7000
289#define	SCR_AND_MISC_DATA_CFG_MASK	0xf0
290
291/* SERDES registers. */
292#define	E6000SW_SERDES_DEV		4
293#define	E6000SW_SERDES_PCS_CTL1		0x1000
294#define	E6000SW_SERDES_SGMII_CTL	0x2000
295#define	 E6000SW_SERDES_PDOWN		(1 << 11)
296
297#define	E6000SW_NUM_VLANS		128
298#define	E6000SW_NUM_LAGMASK		8
299#define	E6000SW_NUM_PHY_REGS		29
300#define	E6000SW_MAX_PORTS		11
301#define	E6000SW_DEFAULT_AGETIME		20
302#define	E6000SW_RETRIES			100
303#define	E6000SW_SMI_TIMEOUT		16
304
305#endif /* _E6000SWREG_H_ */
306