1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD$
31 */
32
33/*
34 * Ethernet media access controller (EMAC)
35 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
36 *
37 * EMAC is an instance of the Synopsys DesignWare 3504-0
38 * Universal 10/100/1000 Ethernet MAC (DWC_gmac).
39 */
40
41#ifndef	__IF_DWCVAR_H__
42#define	__IF_DWCVAR_H__
43
44/*
45 * Driver data and defines.
46 */
47#define	RX_DESC_COUNT	1024
48#define	RX_DESC_SIZE	(sizeof(struct dwc_hwdesc) * RX_DESC_COUNT)
49#define	TX_DESC_COUNT	1024
50#define	TX_MAP_COUNT	TX_DESC_COUNT
51#define	TX_DESC_SIZE	(sizeof(struct dwc_hwdesc) * TX_DESC_COUNT)
52#define	TX_MAP_MAX_SEGS	32
53
54struct dwc_bufmap {
55	bus_dmamap_t		map;
56	struct mbuf		*mbuf;
57	/* Only used for TX descirptors */
58	int			last_desc_idx;
59};
60
61struct dwc_softc {
62	struct resource		*res[2];
63	device_t		dev;
64	int			mactype;
65	int			mii_clk;
66	device_t		miibus;
67	struct mii_data *	mii_softc;
68	struct ifnet		*ifp;
69	int			if_flags;
70	struct mtx		mtx;
71	void *			intr_cookie;
72	struct callout		dwc_callout;
73	boolean_t		link_is_up;
74	boolean_t		is_attached;
75	boolean_t		is_detaching;
76	int			tx_watchdog_count;
77	int			stats_harvest_count;
78	int			phy_mode;
79
80	/* RX */
81	bus_dma_tag_t		rxdesc_tag;
82	bus_dmamap_t		rxdesc_map;
83	struct dwc_hwdesc	*rxdesc_ring;
84	bus_addr_t		rxdesc_ring_paddr;
85	bus_dma_tag_t		rxbuf_tag;
86	struct dwc_bufmap	rxbuf_map[RX_DESC_COUNT];
87	uint32_t		rx_idx;
88
89	/* TX */
90	bus_dma_tag_t		txdesc_tag;
91	bus_dmamap_t		txdesc_map;
92	struct dwc_hwdesc	*txdesc_ring;
93	bus_addr_t		txdesc_ring_paddr;
94	bus_dma_tag_t		txbuf_tag;
95	struct dwc_bufmap	txbuf_map[TX_DESC_COUNT];
96	uint32_t		tx_desc_head;
97	uint32_t		tx_desc_tail;
98	uint32_t		tx_map_head;
99	uint32_t		tx_map_tail;
100	int			tx_desccount;
101	int			tx_mapcount;
102};
103
104#endif	/* __IF_DWCVAR_H__ */
105