1/* 2 * Copyright (C) 2015 Alexander Kabaev 3 * Copyright (C) 2010 Andrew Turner 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* A driver for the Davicom DM9000 MAC. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/bus.h> 38#include <sys/lock.h> 39#include <sys/mbuf.h> 40#include <sys/mutex.h> 41#include <sys/rman.h> 42#include <sys/socket.h> 43#include <sys/sockio.h> 44#include <sys/gpio.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54#include <net/ethernet.h> 55#include <net/bpf.h> 56 57#include <dev/mii/mii.h> 58#include <dev/mii/miivar.h> 59 60#include <dev/dme/if_dmereg.h> 61#include <dev/dme/if_dmevar.h> 62 63#include <dev/ofw/ofw_bus.h> 64#include <dev/ofw/ofw_bus_subr.h> 65 66#include <dev/extres/regulator/regulator.h> 67#include <dev/gpio/gpiobusvar.h> 68 69#include "miibus_if.h" 70 71struct dme_softc { 72 struct ifnet *dme_ifp; 73 device_t dme_dev; 74 device_t dme_miibus; 75 bus_space_handle_t dme_handle; 76 bus_space_tag_t dme_tag; 77 int dme_rev; 78 int dme_bits; 79 struct resource *dme_res; 80 struct resource *dme_irq; 81 void *dme_intrhand; 82 struct mtx dme_mtx; 83 struct callout dme_tick_ch; 84 struct gpiobus_pin *gpio_rset; 85 uint32_t dme_ticks; 86 uint8_t dme_macaddr[ETHER_ADDR_LEN]; 87 regulator_t dme_vcc_regulator; 88 uint8_t dme_txbusy: 1; 89 uint8_t dme_txready: 1; 90 uint16_t dme_txlen; 91}; 92 93#define DME_CHIP_DM9000 0x00 94#define DME_CHIP_DM9000A 0x19 95#define DME_CHIP_DM9000B 0x1a 96 97#define DME_INT_PHY 1 98 99static int dme_probe(device_t); 100static int dme_attach(device_t); 101static int dme_detach(device_t); 102 103static void dme_intr(void *arg); 104static void dme_init_locked(struct dme_softc *); 105 106static void dme_prepare(struct dme_softc *); 107static void dme_transmit(struct dme_softc *); 108 109static int dme_miibus_writereg(device_t dev, int phy, int reg, int data); 110static int dme_miibus_readreg(device_t dev, int phy, int reg); 111 112/* The bit on the address bus attached to the CMD pin */ 113#define BASE_ADDR 0x000 114#define CMD_ADDR BASE_ADDR 115#define DATA_BIT 1 116#define DATA_ADDR 0x002 117 118#undef DME_TRACE 119 120#ifdef DME_TRACE 121#define DTR3 TR3 122#define DTR4 TR4 123#else 124#define NOTR(args...) (void)0 125#define DTR3 NOTR 126#define DTR4 NOTR 127#endif 128 129static uint8_t 130dme_read_reg(struct dme_softc *sc, uint8_t reg) 131{ 132 133 /* Send the register to read from */ 134 bus_space_write_1(sc->dme_tag, sc->dme_handle, CMD_ADDR, reg); 135 bus_space_barrier(sc->dme_tag, sc->dme_handle, CMD_ADDR, 1, 136 BUS_SPACE_BARRIER_WRITE); 137 138 /* Get the value of the register */ 139 return bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR); 140} 141 142static void 143dme_write_reg(struct dme_softc *sc, uint8_t reg, uint8_t value) 144{ 145 146 /* Send the register to write to */ 147 bus_space_write_1(sc->dme_tag, sc->dme_handle, CMD_ADDR, reg); 148 bus_space_barrier(sc->dme_tag, sc->dme_handle, CMD_ADDR, 1, 149 BUS_SPACE_BARRIER_WRITE); 150 151 /* Write the value to the register */ 152 bus_space_write_1(sc->dme_tag, sc->dme_handle, DATA_ADDR, value); 153 bus_space_barrier(sc->dme_tag, sc->dme_handle, DATA_ADDR, 1, 154 BUS_SPACE_BARRIER_WRITE); 155} 156 157static void 158dme_reset(struct dme_softc *sc) 159{ 160 u_int ncr; 161 162 /* Send a soft reset #1 */ 163 dme_write_reg(sc, DME_NCR, NCR_RST | NCR_LBK_MAC); 164 DELAY(100); /* Wait for the MAC to reset */ 165 ncr = dme_read_reg(sc, DME_NCR); 166 if (ncr & NCR_RST) 167 device_printf(sc->dme_dev, "device did not complete first reset\n"); 168 169 /* Send a soft reset #2 per Application Notes v1.22 */ 170 dme_write_reg(sc, DME_NCR, 0); 171 dme_write_reg(sc, DME_NCR, NCR_RST | NCR_LBK_MAC); 172 DELAY(100); /* Wait for the MAC to reset */ 173 ncr = dme_read_reg(sc, DME_NCR); 174 if (ncr & NCR_RST) 175 device_printf(sc->dme_dev, "device did not complete second reset\n"); 176 177 /* Reset trasmit state */ 178 sc->dme_txbusy = 0; 179 sc->dme_txready = 0; 180 181 DTR3("dme_reset, flags %#x busy %d ready %d", 182 sc->dme_ifp ? sc->dme_ifp->if_drv_flags : 0, 183 sc->dme_txbusy, sc->dme_txready); 184} 185 186/* 187 * Parse string MAC address into usable form 188 */ 189static int 190dme_parse_macaddr(const char *str, uint8_t *mac) 191{ 192 int count, i; 193 unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */ 194 195 count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x", 196 &amac[0], &amac[1], &amac[2], 197 &amac[3], &amac[4], &amac[5]); 198 if (count < ETHER_ADDR_LEN) { 199 memset(mac, 0, ETHER_ADDR_LEN); 200 return (1); 201 } 202 203 /* Copy aligned to result */ 204 for (i = 0; i < ETHER_ADDR_LEN; i ++) 205 mac[i] = (amac[i] & 0xff); 206 207 return (0); 208} 209 210/* 211 * Try to determine our own MAC address 212 */ 213static void 214dme_get_macaddr(struct dme_softc *sc) 215{ 216 char devid_str[32]; 217 char *var; 218 int i; 219 220 /* Cannot use resource_string_value with static hints mode */ 221 snprintf(devid_str, 32, "hint.%s.%d.macaddr", 222 device_get_name(sc->dme_dev), 223 device_get_unit(sc->dme_dev)); 224 225 /* Try resource hints */ 226 if ((var = kern_getenv(devid_str)) != NULL) { 227 if (!dme_parse_macaddr(var, sc->dme_macaddr)) { 228 device_printf(sc->dme_dev, "MAC address: %s (hints)\n", var); 229 return; 230 } 231 } 232 233 /* 234 * Try to read MAC address from the device, in case U-Boot has 235 * pre-programmed one for us. 236 */ 237 for (i = 0; i < ETHER_ADDR_LEN; i++) 238 sc->dme_macaddr[i] = dme_read_reg(sc, DME_PAR(i)); 239 240 device_printf(sc->dme_dev, "MAC address %6D (existing)\n", 241 sc->dme_macaddr, ":"); 242} 243 244static void 245dme_config(struct dme_softc *sc) 246{ 247 int i; 248 249 /* Mask all interrupts and reset receive pointer */ 250 dme_write_reg(sc, DME_IMR, IMR_PAR); 251 252 /* Disable GPIO0 to enable the internal PHY */ 253 dme_write_reg(sc, DME_GPCR, 1); 254 dme_write_reg(sc, DME_GPR, 0); 255 256#if 0 257 /* 258 * Supposedly requires special initialization for DSP PHYs 259 * used by DM9000B. Maybe belongs in dedicated PHY driver? 260 */ 261 if (sc->dme_rev == DME_CHIP_DM9000B) { 262 dme_miibus_writereg(sc->dme_dev, DME_INT_PHY, MII_BMCR, 263 BMCR_RESET); 264 dme_miibus_writereg(sc->dme_dev, DME_INT_PHY, MII_DME_DSPCR, 265 DSPCR_INIT); 266 /* Wait 100ms for it to complete. */ 267 for (i = 0; i < 100; i++) { 268 int reg; 269 270 reg = dme_miibus_readreg(sc->dme_dev, DME_INT_PHY, MII_BMCR); 271 if ((reg & BMCR_RESET) == 0) 272 break; 273 DELAY(1000); 274 } 275 } 276#endif 277 278 /* Select the internal PHY and normal loopback */ 279 dme_write_reg(sc, DME_NCR, NCR_LBK_NORMAL); 280 /* Clear any TX requests */ 281 dme_write_reg(sc, DME_TCR, 0); 282 /* Setup backpressure thresholds to 4k and 600us */ 283 dme_write_reg(sc, DME_BPTR, BPTR_BPHW(3) | BPTR_JPT(0x0f)); 284 /* Setup flow control */ 285 dme_write_reg(sc, DME_FCTR, FCTR_HWOT(0x3) | FCTR_LWOT(0x08)); 286 /* Enable flow control */ 287 dme_write_reg(sc, DME_FCR, 0xff); 288 /* Clear special modes */ 289 dme_write_reg(sc, DME_SMCR, 0); 290 /* Clear TX status */ 291 dme_write_reg(sc, DME_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); 292 /* Clear interrrupts */ 293 dme_write_reg(sc, DME_ISR, 0xff); 294 /* Set multicast address filter */ 295 for (i = 0; i < 8; i++) 296 dme_write_reg(sc, DME_MAR(i), 0xff); 297 /* Set the MAC address */ 298 for (i = 0; i < ETHER_ADDR_LEN; i++) 299 dme_write_reg(sc, DME_PAR(i), sc->dme_macaddr[i]); 300 /* Enable the RX buffer */ 301 dme_write_reg(sc, DME_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); 302 303 /* Enable interrupts we care about */ 304 dme_write_reg(sc, DME_IMR, IMR_PAR | IMR_PRI | IMR_PTI); 305} 306 307void 308dme_prepare(struct dme_softc *sc) 309{ 310 struct ifnet *ifp; 311 struct mbuf *m, *mp; 312 uint16_t total_len, len; 313 314 DME_ASSERT_LOCKED(sc); 315 316 KASSERT(sc->dme_txready == 0, 317 ("dme_prepare: called with txready set\n")); 318 319 ifp = sc->dme_ifp; 320 IFQ_DEQUEUE(&ifp->if_snd, m); 321 if (m == NULL) { 322 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 323 DTR3("dme_prepare none, flags %#x busy %d ready %d", 324 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready); 325 return; /* Nothing to transmit */ 326 } 327 328 /* Element has now been removed from the queue, so we better send it */ 329 BPF_MTAP(ifp, m); 330 331 /* Setup the controller to accept the writes */ 332 bus_space_write_1(sc->dme_tag, sc->dme_handle, CMD_ADDR, DME_MWCMD); 333 334 /* 335 * TODO: Fix the case where an mbuf is 336 * not a multiple of the write size. 337 */ 338 total_len = 0; 339 for (mp = m; mp != NULL; mp = mp->m_next) { 340 len = mp->m_len; 341 342 /* Ignore empty parts */ 343 if (len == 0) 344 continue; 345 346 total_len += len; 347 348#if 0 349 bus_space_write_multi_2(sc->dme_tag, sc->dme_handle, 350 DATA_ADDR, mtod(mp, uint16_t *), (len + 1) / 2); 351#else 352 bus_space_write_multi_1(sc->dme_tag, sc->dme_handle, 353 DATA_ADDR, mtod(mp, uint8_t *), len); 354#endif 355 } 356 357 if (total_len % (sc->dme_bits >> 3) != 0) 358 panic("dme_prepare: length is not compatible with IO_MODE"); 359 360 sc->dme_txlen = total_len; 361 sc->dme_txready = 1; 362 DTR3("dme_prepare done, flags %#x busy %d ready %d", 363 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready); 364 365 m_freem(m); 366} 367 368void 369dme_transmit(struct dme_softc *sc) 370{ 371 372 DME_ASSERT_LOCKED(sc); 373 KASSERT(sc->dme_txready, ("transmit without txready")); 374 375 dme_write_reg(sc, DME_TXPLL, sc->dme_txlen & 0xff); 376 dme_write_reg(sc, DME_TXPLH, (sc->dme_txlen >> 8) & 0xff ); 377 378 /* Request to send the packet */ 379 dme_read_reg(sc, DME_ISR); 380 381 dme_write_reg(sc, DME_TCR, TCR_TXREQ); 382 383 sc->dme_txready = 0; 384 sc->dme_txbusy = 1; 385 DTR3("dme_transmit done, flags %#x busy %d ready %d", 386 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready); 387} 388 389 390static void 391dme_start_locked(struct ifnet *ifp) 392{ 393 struct dme_softc *sc; 394 395 sc = ifp->if_softc; 396 DME_ASSERT_LOCKED(sc); 397 398 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 399 IFF_DRV_RUNNING) 400 return; 401 402 DTR3("dme_start, flags %#x busy %d ready %d", 403 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready); 404 KASSERT(sc->dme_txbusy == 0 || sc->dme_txready == 0, 405 ("dme: send without empty queue\n")); 406 407 dme_prepare(sc); 408 409 if (sc->dme_txbusy == 0) { 410 /* We are ready to transmit right away */ 411 dme_transmit(sc); 412 dme_prepare(sc); /* Prepare next one */ 413 } 414 /* 415 * We need to wait until the current packet has 416 * been transmitted. 417 */ 418 if (sc->dme_txready != 0) 419 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 420} 421 422static void 423dme_start(struct ifnet *ifp) 424{ 425 struct dme_softc *sc; 426 427 sc = ifp->if_softc; 428 DME_LOCK(sc); 429 dme_start_locked(ifp); 430 DME_UNLOCK(sc); 431} 432 433static void 434dme_stop(struct dme_softc *sc) 435{ 436 struct ifnet *ifp; 437 438 DME_ASSERT_LOCKED(sc); 439 /* Disable receiver */ 440 dme_write_reg(sc, DME_RCR, 0x00); 441 /* Mask interrupts */ 442 dme_write_reg(sc, DME_IMR, 0x00); 443 /* Stop poll */ 444 callout_stop(&sc->dme_tick_ch); 445 446 ifp = sc->dme_ifp; 447 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 448 449 DTR3("dme_stop, flags %#x busy %d ready %d", 450 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready); 451 sc->dme_txbusy = 0; 452 sc->dme_txready = 0; 453} 454 455static int 456dme_rxeof(struct dme_softc *sc) 457{ 458 struct ifnet *ifp; 459 struct mbuf *m; 460 int len, i; 461 462 DME_ASSERT_LOCKED(sc); 463 464 ifp = sc->dme_ifp; 465 466 /* Read the first byte to check it correct */ 467 (void)dme_read_reg(sc, DME_MRCMDX); 468 i = bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR); 469 switch(bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR)) { 470 case 1: 471 /* Correct value */ 472 break; 473 case 0: 474 return 1; 475 default: 476 /* Error */ 477 return -1; 478 } 479 480 i = dme_read_reg(sc, DME_MRRL); 481 i |= dme_read_reg(sc, DME_MRRH) << 8; 482 483 len = dme_read_reg(sc, DME_ROCR); 484 485 bus_space_write_1(sc->dme_tag, sc->dme_handle, CMD_ADDR, DME_MRCMD); 486 len = 0; 487 switch(sc->dme_bits) { 488 case 8: 489 i = bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR); 490 i <<= 8; 491 i |= bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR); 492 493 len = bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR); 494 len |= bus_space_read_1(sc->dme_tag, sc->dme_handle, 495 DATA_ADDR) << 8; 496 break; 497 case 16: 498 bus_space_read_2(sc->dme_tag, sc->dme_handle, DATA_ADDR); 499 len = bus_space_read_2(sc->dme_tag, sc->dme_handle, DATA_ADDR); 500 break; 501 case 32: 502 { 503 uint32_t reg; 504 505 reg = bus_space_read_4(sc->dme_tag, sc->dme_handle, DATA_ADDR); 506 len = reg & 0xFFFF; 507 break; 508 } 509 } 510 511 MGETHDR(m, M_NOWAIT, MT_DATA); 512 if (m == NULL) 513 return -1; 514 515 if (len > MHLEN - ETHER_ALIGN) { 516 MCLGET(m, M_NOWAIT); 517 if (!(m->m_flags & M_EXT)) { 518 m_freem(m); 519 return -1; 520 } 521 } 522 523 m->m_pkthdr.rcvif = ifp; 524 m->m_len = m->m_pkthdr.len = len; 525 m_adj(m, ETHER_ALIGN); 526 527 /* Read the data */ 528#if 0 529 bus_space_read_multi_2(sc->dme_tag, sc->dme_handle, DATA_ADDR, 530 mtod(m, uint16_t *), (len + 1) / 2); 531#else 532 bus_space_read_multi_1(sc->dme_tag, sc->dme_handle, DATA_ADDR, 533 mtod(m, uint8_t *), len); 534#endif 535 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 536 DME_UNLOCK(sc); 537 (*ifp->if_input)(ifp, m); 538 DME_LOCK(sc); 539 540 return 0; 541} 542 543static void 544dme_tick(void *arg) 545{ 546 struct dme_softc *sc; 547 struct mii_data *mii; 548 549 sc = (struct dme_softc *)arg; 550 551 /* Probably too frequent? */ 552 mii = device_get_softc(sc->dme_miibus); 553 mii_tick(mii); 554 555 callout_reset(&sc->dme_tick_ch, hz, dme_tick, sc); 556} 557 558static void 559dme_intr(void *arg) 560{ 561 struct dme_softc *sc; 562 uint32_t intr_status; 563 564 sc = (struct dme_softc *)arg; 565 566 DME_LOCK(sc); 567 568 intr_status = dme_read_reg(sc, DME_ISR); 569 dme_write_reg(sc, DME_ISR, intr_status); 570 571 DTR4("dme_intr flags %#x busy %d ready %d intr %#x", 572 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, 573 sc->dme_txready, intr_status); 574 575 if (intr_status & ISR_PT) { 576 uint8_t nsr, tx_status; 577 578 sc->dme_txbusy = 0; 579 580 nsr = dme_read_reg(sc, DME_NSR); 581 582 if (nsr & NSR_TX1END) 583 tx_status = dme_read_reg(sc, DME_TSR1); 584 else if (nsr & NSR_TX2END) 585 tx_status = dme_read_reg(sc, DME_TSR2); 586 else 587 tx_status = 1; 588 589 DTR4("dme_intr flags %#x busy %d ready %d nsr %#x", 590 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, 591 sc->dme_txready, nsr); 592 593 /* Prepare packet to send if none is currently pending */ 594 if (sc->dme_txready == 0) 595 dme_prepare(sc); 596 /* Send the packet out of one is waiting for transmit */ 597 if (sc->dme_txready != 0) { 598 /* Initiate transmission of the prepared packet */ 599 dme_transmit(sc); 600 /* Prepare next packet to send */ 601 dme_prepare(sc); 602 /* 603 * We need to wait until the current packet has 604 * been transmitted. 605 */ 606 if (sc->dme_txready != 0) 607 sc->dme_ifp->if_drv_flags |= IFF_DRV_OACTIVE; 608 } 609 } 610 611 if (intr_status & ISR_PR) { 612 /* Read the packets off the device */ 613 while (dme_rxeof(sc) == 0) 614 continue; 615 } 616 DME_UNLOCK(sc); 617} 618 619static void 620dme_setmode(struct dme_softc *sc) 621{ 622} 623 624static int 625dme_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 626{ 627 struct dme_softc *sc; 628 struct mii_data *mii; 629 struct ifreq *ifr; 630 int error = 0; 631 632 sc = ifp->if_softc; 633 ifr = (struct ifreq *)data; 634 635 switch (command) { 636 case SIOCSIFFLAGS: 637 /* 638 * Switch interface state between "running" and 639 * "stopped", reflecting the UP flag. 640 */ 641 DME_LOCK(sc); 642 if (ifp->if_flags & IFF_UP) { 643 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 644 dme_init_locked(sc); 645 } 646 } else { 647 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 648 dme_stop(sc); 649 } 650 } 651 dme_setmode(sc); 652 DME_UNLOCK(sc); 653 break; 654 case SIOCGIFMEDIA: 655 case SIOCSIFMEDIA: 656 mii = device_get_softc(sc->dme_miibus); 657 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 658 break; 659 default: 660 error = ether_ioctl(ifp, command, data); 661 break; 662 } 663 return (error); 664} 665 666static void dme_init_locked(struct dme_softc *sc) 667{ 668 struct ifnet *ifp = sc->dme_ifp; 669 670 DME_ASSERT_LOCKED(sc); 671 672 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 673 return; 674 675 dme_reset(sc); 676 dme_config(sc); 677 678 ifp->if_drv_flags |= IFF_DRV_RUNNING; 679 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 680 681 callout_reset(&sc->dme_tick_ch, hz, dme_tick, sc); 682} 683 684static void 685dme_init(void *xcs) 686{ 687 struct dme_softc *sc = xcs; 688 689 DME_LOCK(sc); 690 dme_init_locked(sc); 691 DME_UNLOCK(sc); 692} 693 694static int 695dme_ifmedia_upd(struct ifnet *ifp) 696{ 697 struct dme_softc *sc; 698 struct mii_data *mii; 699 700 sc = ifp->if_softc; 701 mii = device_get_softc(sc->dme_miibus); 702 703 DME_LOCK(sc); 704 mii_mediachg(mii); 705 DME_UNLOCK(sc); 706 707 return (0); 708} 709 710static void 711dme_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 712{ 713 struct dme_softc *sc; 714 struct mii_data *mii; 715 716 sc = ifp->if_softc; 717 mii = device_get_softc(sc->dme_miibus); 718 719 DME_LOCK(sc); 720 mii_pollstat(mii); 721 ifmr->ifm_active = mii->mii_media_active; 722 ifmr->ifm_status = mii->mii_media_status; 723 DME_UNLOCK(sc); 724} 725 726static struct ofw_compat_data compat_data[] = { 727 { "davicom,dm9000", true }, 728 { NULL, false } 729}; 730 731static int 732dme_probe(device_t dev) 733{ 734 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 735 return (ENXIO); 736 device_set_desc(dev, "Davicom DM9000"); 737 return (0); 738} 739 740static int 741dme_attach(device_t dev) 742{ 743 struct dme_softc *sc; 744 struct ifnet *ifp; 745 int error, rid; 746 uint32_t data; 747 748 sc = device_get_softc(dev); 749 sc->dme_dev = dev; 750 751 error = 0; 752 753 mtx_init(&sc->dme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 754 MTX_DEF); 755 callout_init_mtx(&sc->dme_tick_ch, &sc->dme_mtx, 0); 756 757 rid = 0; 758 sc->dme_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 759 RF_ACTIVE); 760 if (sc->dme_res == NULL) { 761 device_printf(dev, "unable to map memory\n"); 762 error = ENXIO; 763 goto fail; 764 } 765 766 rid = 0; 767 sc->dme_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 768 RF_ACTIVE); 769 if (sc->dme_irq == NULL) { 770 device_printf(dev, "unable to map memory\n"); 771 error = ENXIO; 772 goto fail; 773 } 774 /* 775 * Power the chip up, if necessary 776 */ 777 error = regulator_get_by_ofw_property(dev, 0, "vcc-supply", &sc->dme_vcc_regulator); 778 if (error == 0) { 779 error = regulator_enable(sc->dme_vcc_regulator); 780 if (error != 0) { 781 device_printf(dev, "unable to enable power supply\n"); 782 error = ENXIO; 783 goto fail; 784 } 785 } 786 787 /* 788 * Delay a little. This seems required on rev-1 boards (green.) 789 */ 790 DELAY(100000); 791 792 /* Bring controller out of reset */ 793 error = ofw_gpiobus_parse_gpios(dev, "reset-gpios", &sc->gpio_rset); 794 if (error > 1) { 795 device_printf(dev, "too many reset gpios\n"); 796 sc->gpio_rset = NULL; 797 error = ENXIO; 798 goto fail; 799 } 800 801 if (sc->gpio_rset != NULL) { 802 error = GPIO_PIN_SET(sc->gpio_rset->dev, sc->gpio_rset->pin, 0); 803 if (error != 0) { 804 device_printf(dev, "Cannot configure GPIO pin %d on %s\n", 805 sc->gpio_rset->pin, device_get_nameunit(sc->gpio_rset->dev)); 806 goto fail; 807 } 808 809 error = GPIO_PIN_SETFLAGS(sc->gpio_rset->dev, sc->gpio_rset->pin, 810 GPIO_PIN_OUTPUT); 811 if (error != 0) { 812 device_printf(dev, "Cannot configure GPIO pin %d on %s\n", 813 sc->gpio_rset->pin, device_get_nameunit(sc->gpio_rset->dev)); 814 goto fail; 815 } 816 817 DELAY(2000); 818 819 error = GPIO_PIN_SET(sc->gpio_rset->dev, sc->gpio_rset->pin, 1); 820 if (error != 0) { 821 device_printf(dev, "Cannot configure GPIO pin %d on %s\n", 822 sc->gpio_rset->pin, device_get_nameunit(sc->gpio_rset->dev)); 823 goto fail; 824 } 825 826 DELAY(4000); 827 } else 828 device_printf(dev, "Unable to find reset GPIO\n"); 829 830 sc->dme_tag = rman_get_bustag(sc->dme_res); 831 sc->dme_handle = rman_get_bushandle(sc->dme_res); 832 833 /* Reset the chip as soon as possible */ 834 dme_reset(sc); 835 836 /* Figure IO mode */ 837 switch((dme_read_reg(sc, DME_ISR) >> 6) & 0x03) { 838 case 0: 839 /* 16 bit */ 840 sc->dme_bits = 16; 841 break; 842 case 1: 843 /* 32 bit */ 844 sc->dme_bits = 32; 845 break; 846 case 2: 847 /* 8 bit */ 848 sc->dme_bits = 8; 849 break; 850 default: 851 /* reserved */ 852 device_printf(dev, "Unable to determine device mode\n"); 853 error = ENXIO; 854 goto fail; 855 } 856 857 DELAY(100000); 858 859 /* Read vendor and device id's */ 860 data = dme_read_reg(sc, DME_VIDH) << 8; 861 data |= dme_read_reg(sc, DME_VIDL); 862 device_printf(dev, "Vendor ID: 0x%04x\n", data); 863 864 /* Read vendor and device id's */ 865 data = dme_read_reg(sc, DME_PIDH) << 8; 866 data |= dme_read_reg(sc, DME_PIDL); 867 device_printf(dev, "Product ID: 0x%04x\n", data); 868 869 /* Chip revision */ 870 data = dme_read_reg(sc, DME_CHIPR); 871 device_printf(dev, "Revision: 0x%04x\n", data); 872 if (data != DME_CHIP_DM9000A && data != DME_CHIP_DM9000B) 873 data = DME_CHIP_DM9000; 874 sc->dme_rev = data; 875 876 device_printf(dev, "using %d-bit IO mode\n", sc->dme_bits); 877 KASSERT(sc->dme_bits == 8, ("wrong io mode")); 878 879 /* Try to figure our mac address */ 880 dme_get_macaddr(sc); 881 882 /* Configure chip after reset */ 883 dme_config(sc); 884 885 ifp = sc->dme_ifp = if_alloc(IFT_ETHER); 886 if (ifp == NULL) { 887 device_printf(dev, "unable to allocate ifp\n"); 888 error = ENOSPC; 889 goto fail; 890 } 891 ifp->if_softc = sc; 892 893 /* Setup MII */ 894 error = mii_attach(dev, &sc->dme_miibus, ifp, dme_ifmedia_upd, 895 dme_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 896 /* This should never happen as the DM9000 contains it's own PHY */ 897 if (error != 0) { 898 device_printf(dev, "PHY probe failed\n"); 899 goto fail; 900 } 901 902 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 903 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 904 ifp->if_start = dme_start; 905 ifp->if_ioctl = dme_ioctl; 906 ifp->if_init = dme_init; 907 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 908 909 ether_ifattach(ifp, sc->dme_macaddr); 910 911 error = bus_setup_intr(dev, sc->dme_irq, INTR_TYPE_NET | INTR_MPSAFE, 912 NULL, dme_intr, sc, &sc->dme_intrhand); 913 if (error) { 914 device_printf(dev, "couldn't set up irq\n"); 915 ether_ifdetach(ifp); 916 goto fail; 917 } 918 919fail: 920 if (error != 0) 921 dme_detach(dev); 922 return (error); 923} 924 925static int 926dme_detach(device_t dev) 927{ 928 struct dme_softc *sc; 929 struct ifnet *ifp; 930 931 sc = device_get_softc(dev); 932 KASSERT(mtx_initialized(&sc->dme_mtx), ("dme mutex not initialized")); 933 934 ifp = sc->dme_ifp; 935 936 if (device_is_attached(dev)) { 937 DME_LOCK(sc); 938 dme_stop(sc); 939 DME_UNLOCK(sc); 940 ether_ifdetach(ifp); 941 callout_drain(&sc->dme_tick_ch); 942 } 943 944 if (sc->dme_miibus) 945 device_delete_child(dev, sc->dme_miibus); 946 bus_generic_detach(dev); 947 948 if (sc->dme_vcc_regulator != 0) 949 regulator_release(sc->dme_vcc_regulator); 950 if (sc->dme_intrhand) 951 bus_teardown_intr(dev, sc->dme_irq, sc->dme_intrhand); 952 if (sc->dme_irq) 953 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dme_irq); 954 if (sc->dme_res) 955 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->dme_res); 956 957 if (ifp != NULL) 958 if_free(ifp); 959 960 mtx_destroy(&sc->dme_mtx); 961 962 return (0); 963} 964 965/* 966 * The MII bus interface 967 */ 968static int 969dme_miibus_readreg(device_t dev, int phy, int reg) 970{ 971 struct dme_softc *sc; 972 int i, rval; 973 974 /* We have up to 4 PHY's */ 975 if (phy >= 4) 976 return (0); 977 978 sc = device_get_softc(dev); 979 980 /* Send the register to read to the phy and start the read */ 981 dme_write_reg(sc, DME_EPAR, (phy << 6) | reg); 982 dme_write_reg(sc, DME_EPCR, EPCR_EPOS | EPCR_ERPRR); 983 984 /* Wait for the data to be read */ 985 for (i = 0; i < DME_TIMEOUT; i++) { 986 if ((dme_read_reg(sc, DME_EPCR) & EPCR_ERRE) == 0) 987 break; 988 DELAY(1); 989 } 990 991 /* Clear the comand */ 992 dme_write_reg(sc, DME_EPCR, 0); 993 994 if (i == DME_TIMEOUT) 995 return (0); 996 997 rval = (dme_read_reg(sc, DME_EPDRH) << 8) | dme_read_reg(sc, DME_EPDRL); 998 return (rval); 999} 1000 1001static int 1002dme_miibus_writereg(device_t dev, int phy, int reg, int data) 1003{ 1004 struct dme_softc *sc; 1005 int i; 1006 1007 /* We have up to 4 PHY's */ 1008 if (phy > 3) 1009 return (0); 1010 1011 sc = device_get_softc(dev); 1012 1013 /* Send the register and data to write to the phy */ 1014 dme_write_reg(sc, DME_EPAR, (phy << 6) | reg); 1015 dme_write_reg(sc, DME_EPDRL, data & 0xFF); 1016 dme_write_reg(sc, DME_EPDRH, (data >> 8) & 0xFF); 1017 /* Start the write */ 1018 dme_write_reg(sc, DME_EPCR, EPCR_EPOS | EPCR_ERPRW); 1019 1020 /* Wait for the data to be written */ 1021 for (i = 0; i < DME_TIMEOUT; i++) { 1022 if ((dme_read_reg(sc, DME_EPCR) & EPCR_ERRE) == 0) 1023 break; 1024 DELAY(1); 1025 } 1026 1027 /* Clear the comand */ 1028 dme_write_reg(sc, DME_EPCR, 0); 1029 1030 return (0); 1031} 1032 1033static device_method_t dme_methods[] = { 1034 /* Device interface */ 1035 DEVMETHOD(device_probe, dme_probe), 1036 DEVMETHOD(device_attach, dme_attach), 1037 DEVMETHOD(device_detach, dme_detach), 1038 1039 /* bus interface, for miibus */ 1040 DEVMETHOD(bus_print_child, bus_generic_print_child), 1041 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1042 1043 /* MII interface */ 1044 DEVMETHOD(miibus_readreg, dme_miibus_readreg), 1045 DEVMETHOD(miibus_writereg, dme_miibus_writereg), 1046 1047 { 0, 0 } 1048}; 1049 1050static driver_t dme_driver = { 1051 "dme", 1052 dme_methods, 1053 sizeof(struct dme_softc) 1054}; 1055 1056static devclass_t dme_devclass; 1057 1058MODULE_DEPEND(dme, ether, 1, 1, 1); 1059MODULE_DEPEND(dme, miibus, 1, 1, 1); 1060DRIVER_MODULE(dme, simplebus, dme_driver, dme_devclass, 0, 0); 1061DRIVER_MODULE(miibus, dme, miibus_driver, miibus_devclass, 0, 0); 1062 1063