1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD$"); 31 32#include "opt_inet.h" 33 34#include <sys/param.h> 35#include <sys/eventhandler.h> 36 37#include "common.h" 38#include "t4_regs.h" 39#include "t4_regs_values.h" 40#include "firmware/t4fw_interface.h" 41 42#undef msleep 43#define msleep(x) do { \ 44 if (cold) \ 45 DELAY((x) * 1000); \ 46 else \ 47 pause("t4hw", (x) * hz / 1000); \ 48} while (0) 49 50/** 51 * t4_wait_op_done_val - wait until an operation is completed 52 * @adapter: the adapter performing the operation 53 * @reg: the register to check for completion 54 * @mask: a single-bit field within @reg that indicates completion 55 * @polarity: the value of the field when the operation is completed 56 * @attempts: number of check iterations 57 * @delay: delay in usecs between iterations 58 * @valp: where to store the value of the register at completion time 59 * 60 * Wait until an operation is completed by checking a bit in a register 61 * up to @attempts times. If @valp is not NULL the value of the register 62 * at the time it indicated completion is stored there. Returns 0 if the 63 * operation completes and -EAGAIN otherwise. 64 */ 65static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 66 int polarity, int attempts, int delay, u32 *valp) 67{ 68 while (1) { 69 u32 val = t4_read_reg(adapter, reg); 70 71 if (!!(val & mask) == polarity) { 72 if (valp) 73 *valp = val; 74 return 0; 75 } 76 if (--attempts == 0) 77 return -EAGAIN; 78 if (delay) 79 udelay(delay); 80 } 81} 82 83static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 84 int polarity, int attempts, int delay) 85{ 86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 87 delay, NULL); 88} 89 90/** 91 * t4_set_reg_field - set a register field to a value 92 * @adapter: the adapter to program 93 * @addr: the register address 94 * @mask: specifies the portion of the register to modify 95 * @val: the new value for the register field 96 * 97 * Sets a register field specified by the supplied mask to the 98 * given value. 99 */ 100void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 101 u32 val) 102{ 103 u32 v = t4_read_reg(adapter, addr) & ~mask; 104 105 t4_write_reg(adapter, addr, v | val); 106 (void) t4_read_reg(adapter, addr); /* flush */ 107} 108 109/** 110 * t4_read_indirect - read indirectly addressed registers 111 * @adap: the adapter 112 * @addr_reg: register holding the indirect address 113 * @data_reg: register holding the value of the indirect register 114 * @vals: where the read register values are stored 115 * @nregs: how many indirect registers to read 116 * @start_idx: index of first indirect register to read 117 * 118 * Reads registers that are accessed indirectly through an address/data 119 * register pair. 120 */ 121void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 122 unsigned int data_reg, u32 *vals, 123 unsigned int nregs, unsigned int start_idx) 124{ 125 while (nregs--) { 126 t4_write_reg(adap, addr_reg, start_idx); 127 *vals++ = t4_read_reg(adap, data_reg); 128 start_idx++; 129 } 130} 131 132/** 133 * t4_write_indirect - write indirectly addressed registers 134 * @adap: the adapter 135 * @addr_reg: register holding the indirect addresses 136 * @data_reg: register holding the value for the indirect registers 137 * @vals: values to write 138 * @nregs: how many indirect registers to write 139 * @start_idx: address of first indirect register to write 140 * 141 * Writes a sequential block of registers that are accessed indirectly 142 * through an address/data register pair. 143 */ 144void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 145 unsigned int data_reg, const u32 *vals, 146 unsigned int nregs, unsigned int start_idx) 147{ 148 while (nregs--) { 149 t4_write_reg(adap, addr_reg, start_idx++); 150 t4_write_reg(adap, data_reg, *vals++); 151 } 152} 153 154/* 155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 156 * mechanism. This guarantees that we get the real value even if we're 157 * operating within a Virtual Machine and the Hypervisor is trapping our 158 * Configuration Space accesses. 159 * 160 * N.B. This routine should only be used as a last resort: the firmware uses 161 * the backdoor registers on a regular basis and we can end up 162 * conflicting with it's uses! 163 */ 164u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 165{ 166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 167 u32 val; 168 169 if (chip_id(adap) <= CHELSIO_T5) 170 req |= F_ENABLE; 171 else 172 req |= F_T6_ENABLE; 173 174 if (is_t4(adap)) 175 req |= F_LOCALCFG; 176 177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 179 180 /* 181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 182 * Configuration Space read. (None of the other fields matter when 183 * F_ENABLE is 0 so a simple register write is easier than a 184 * read-modify-write via t4_set_reg_field().) 185 */ 186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 187 188 return val; 189} 190 191/* 192 * t4_report_fw_error - report firmware error 193 * @adap: the adapter 194 * 195 * The adapter firmware can indicate error conditions to the host. 196 * If the firmware has indicated an error, print out the reason for 197 * the firmware error. 198 */ 199static void t4_report_fw_error(struct adapter *adap) 200{ 201 static const char *const reason[] = { 202 "Crash", /* PCIE_FW_EVAL_CRASH */ 203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 209 "Reserved", /* reserved */ 210 }; 211 u32 pcie_fw; 212 213 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 214 if (pcie_fw & F_PCIE_FW_ERR) { 215 adap->flags &= ~FW_OK; 216 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n", 217 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw); 218 if (pcie_fw != 0xffffffff) 219 t4_os_dump_devlog(adap); 220 } 221} 222 223/* 224 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 225 */ 226static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 227 u32 mbox_addr) 228{ 229 for ( ; nflit; nflit--, mbox_addr += 8) 230 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 231} 232 233/* 234 * Handle a FW assertion reported in a mailbox. 235 */ 236static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 237{ 238 CH_ALERT(adap, 239 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 240 asrt->u.assert.filename_0_7, 241 be32_to_cpu(asrt->u.assert.line), 242 be32_to_cpu(asrt->u.assert.x), 243 be32_to_cpu(asrt->u.assert.y)); 244} 245 246struct port_tx_state { 247 uint64_t rx_pause; 248 uint64_t tx_frames; 249}; 250 251static void 252read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state) 253{ 254 uint32_t rx_pause_reg, tx_frames_reg; 255 256 if (is_t4(sc)) { 257 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 258 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 259 } else { 260 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 261 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 262 } 263 264 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); 265 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); 266} 267 268static void 269read_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 270{ 271 int i; 272 273 for_each_port(sc, i) 274 read_tx_state_one(sc, i, &tx_state[i]); 275} 276 277static void 278check_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 279{ 280 uint32_t port_ctl_reg; 281 uint64_t tx_frames, rx_pause; 282 int i; 283 284 for_each_port(sc, i) { 285 rx_pause = tx_state[i].rx_pause; 286 tx_frames = tx_state[i].tx_frames; 287 read_tx_state_one(sc, i, &tx_state[i]); /* update */ 288 289 if (is_t4(sc)) 290 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL); 291 else 292 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL); 293 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN && 294 rx_pause != tx_state[i].rx_pause && 295 tx_frames == tx_state[i].tx_frames) { 296 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); 297 mdelay(1); 298 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN); 299 } 300 } 301} 302 303#define X_CIM_PF_NOACCESS 0xeeeeeeee 304/** 305 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 306 * @adap: the adapter 307 * @mbox: index of the mailbox to use 308 * @cmd: the command to write 309 * @size: command length in bytes 310 * @rpl: where to optionally store the reply 311 * @sleep_ok: if true we may sleep while awaiting command completion 312 * @timeout: time to wait for command to finish before timing out 313 * (negative implies @sleep_ok=false) 314 * 315 * Sends the given command to FW through the selected mailbox and waits 316 * for the FW to execute the command. If @rpl is not %NULL it is used to 317 * store the FW's reply to the command. The command and its optional 318 * reply are of the same length. Some FW commands like RESET and 319 * INITIALIZE can take a considerable amount of time to execute. 320 * @sleep_ok determines whether we may sleep while awaiting the response. 321 * If sleeping is allowed we use progressive backoff otherwise we spin. 322 * Note that passing in a negative @timeout is an alternate mechanism 323 * for specifying @sleep_ok=false. This is useful when a higher level 324 * interface allows for specification of @timeout but not @sleep_ok ... 325 * 326 * The return value is 0 on success or a negative errno on failure. A 327 * failure can happen either because we are not able to execute the 328 * command or FW executes it but signals an error. In the latter case 329 * the return value is the error code indicated by FW (negated). 330 */ 331int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 332 int size, void *rpl, bool sleep_ok, int timeout) 333{ 334 /* 335 * We delay in small increments at first in an effort to maintain 336 * responsiveness for simple, fast executing commands but then back 337 * off to larger delays to a maximum retry delay. 338 */ 339 static const int delay[] = { 340 1, 1, 3, 5, 10, 10, 20, 50, 100 341 }; 342 u32 v; 343 u64 res; 344 int i, ms, delay_idx, ret, next_tx_check; 345 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 346 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 347 u32 ctl; 348 __be64 cmd_rpl[MBOX_LEN/8]; 349 u32 pcie_fw; 350 struct port_tx_state tx_state[MAX_NPORTS]; 351 352 if (adap->flags & CHK_MBOX_ACCESS) 353 ASSERT_SYNCHRONIZED_OP(adap); 354 355 if (size <= 0 || (size & 15) || size > MBOX_LEN) 356 return -EINVAL; 357 358 if (adap->flags & IS_VF) { 359 if (is_t6(adap)) 360 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 361 else 362 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 363 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 364 } 365 366 /* 367 * If we have a negative timeout, that implies that we can't sleep. 368 */ 369 if (timeout < 0) { 370 sleep_ok = false; 371 timeout = -timeout; 372 } 373 374 /* 375 * Attempt to gain access to the mailbox. 376 */ 377 for (i = 0; i < 4; i++) { 378 ctl = t4_read_reg(adap, ctl_reg); 379 v = G_MBOWNER(ctl); 380 if (v != X_MBOWNER_NONE) 381 break; 382 } 383 384 /* 385 * If we were unable to gain access, report the error to our caller. 386 */ 387 if (v != X_MBOWNER_PL) { 388 t4_report_fw_error(adap); 389 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 390 return ret; 391 } 392 393 /* 394 * If we gain ownership of the mailbox and there's a "valid" message 395 * in it, this is likely an asynchronous error message from the 396 * firmware. So we'll report that and then proceed on with attempting 397 * to issue our own command ... which may well fail if the error 398 * presaged the firmware crashing ... 399 */ 400 if (ctl & F_MBMSGVALID) { 401 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true); 402 } 403 404 /* 405 * Copy in the new mailbox command and send it on its way ... 406 */ 407 memset(cmd_rpl, 0, sizeof(cmd_rpl)); 408 memcpy(cmd_rpl, cmd, size); 409 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false); 410 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++) 411 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i])); 412 413 if (adap->flags & IS_VF) { 414 /* 415 * For the VFs, the Mailbox Data "registers" are 416 * actually backed by T4's "MA" interface rather than 417 * PL Registers (as is the case for the PFs). Because 418 * these are in different coherency domains, the write 419 * to the VF's PL-register-backed Mailbox Control can 420 * race in front of the writes to the MA-backed VF 421 * Mailbox Data "registers". So we need to do a 422 * read-back on at least one byte of the VF Mailbox 423 * Data registers before doing the write to the VF 424 * Mailbox Control register. 425 */ 426 t4_read_reg(adap, data_reg); 427 } 428 429 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 430 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */ 431 next_tx_check = 1000; 432 delay_idx = 0; 433 ms = delay[0]; 434 435 /* 436 * Loop waiting for the reply; bail out if we time out or the firmware 437 * reports an error. 438 */ 439 pcie_fw = 0; 440 for (i = 0; i < timeout; i += ms) { 441 if (!(adap->flags & IS_VF)) { 442 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 443 if (pcie_fw & F_PCIE_FW_ERR) 444 break; 445 } 446 447 if (i >= next_tx_check) { 448 check_tx_state(adap, &tx_state[0]); 449 next_tx_check = i + 1000; 450 } 451 452 if (sleep_ok) { 453 ms = delay[delay_idx]; /* last element may repeat */ 454 if (delay_idx < ARRAY_SIZE(delay) - 1) 455 delay_idx++; 456 msleep(ms); 457 } else { 458 mdelay(ms); 459 } 460 461 v = t4_read_reg(adap, ctl_reg); 462 if (v == X_CIM_PF_NOACCESS) 463 continue; 464 if (G_MBOWNER(v) == X_MBOWNER_PL) { 465 if (!(v & F_MBMSGVALID)) { 466 t4_write_reg(adap, ctl_reg, 467 V_MBOWNER(X_MBOWNER_NONE)); 468 continue; 469 } 470 471 /* 472 * Retrieve the command reply and release the mailbox. 473 */ 474 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 475 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false); 476 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 477 478 res = be64_to_cpu(cmd_rpl[0]); 479 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 480 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 481 res = V_FW_CMD_RETVAL(EIO); 482 } else if (rpl) 483 memcpy(rpl, cmd_rpl, size); 484 return -G_FW_CMD_RETVAL((int)res); 485 } 486 } 487 488 /* 489 * We timed out waiting for a reply to our mailbox command. Report 490 * the error and also check to see if the firmware reported any 491 * errors ... 492 */ 493 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n", 494 *(const u8 *)cmd, mbox, pcie_fw); 495 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true); 496 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true); 497 498 if (pcie_fw & F_PCIE_FW_ERR) { 499 ret = -ENXIO; 500 t4_report_fw_error(adap); 501 } else { 502 ret = -ETIMEDOUT; 503 t4_os_dump_devlog(adap); 504 } 505 506 t4_fatal_err(adap, true); 507 return ret; 508} 509 510int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 511 void *rpl, bool sleep_ok) 512{ 513 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 514 sleep_ok, FW_CMD_MAX_TIMEOUT); 515 516} 517 518static int t4_edc_err_read(struct adapter *adap, int idx) 519{ 520 u32 edc_ecc_err_addr_reg; 521 u32 edc_bist_status_rdata_reg; 522 523 if (is_t4(adap)) { 524 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 525 return 0; 526 } 527 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 528 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 529 return 0; 530 } 531 532 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 533 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 534 535 CH_WARN(adap, 536 "edc%d err addr 0x%x: 0x%x.\n", 537 idx, edc_ecc_err_addr_reg, 538 t4_read_reg(adap, edc_ecc_err_addr_reg)); 539 CH_WARN(adap, 540 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 541 edc_bist_status_rdata_reg, 542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 543 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 544 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 545 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 546 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 547 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 548 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 549 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 550 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 551 552 return 0; 553} 554 555/** 556 * t4_mc_read - read from MC through backdoor accesses 557 * @adap: the adapter 558 * @idx: which MC to access 559 * @addr: address of first byte requested 560 * @data: 64 bytes of data containing the requested address 561 * @ecc: where to store the corresponding 64-bit ECC word 562 * 563 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 564 * that covers the requested address @addr. If @parity is not %NULL it 565 * is assigned the 64-bit ECC word for the read data. 566 */ 567int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 568{ 569 int i; 570 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 571 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 572 573 if (is_t4(adap)) { 574 mc_bist_cmd_reg = A_MC_BIST_CMD; 575 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 576 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 577 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 578 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 579 } else { 580 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 581 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 582 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 583 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 584 idx); 585 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 586 idx); 587 } 588 589 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 590 return -EBUSY; 591 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 592 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 593 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 594 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 595 F_START_BIST | V_BIST_CMD_GAP(1)); 596 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 597 if (i) 598 return i; 599 600#define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 601 602 for (i = 15; i >= 0; i--) 603 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 604 if (ecc) 605 *ecc = t4_read_reg64(adap, MC_DATA(16)); 606#undef MC_DATA 607 return 0; 608} 609 610/** 611 * t4_edc_read - read from EDC through backdoor accesses 612 * @adap: the adapter 613 * @idx: which EDC to access 614 * @addr: address of first byte requested 615 * @data: 64 bytes of data containing the requested address 616 * @ecc: where to store the corresponding 64-bit ECC word 617 * 618 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 619 * that covers the requested address @addr. If @parity is not %NULL it 620 * is assigned the 64-bit ECC word for the read data. 621 */ 622int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 623{ 624 int i; 625 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 626 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 627 628 if (is_t4(adap)) { 629 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 630 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 631 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 632 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 633 idx); 634 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 635 idx); 636 } else { 637/* 638 * These macro are missing in t4_regs.h file. 639 * Added temporarily for testing. 640 */ 641#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 642#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 643 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 644 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 645 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 646 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 647 idx); 648 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 649 idx); 650#undef EDC_REG_T5 651#undef EDC_STRIDE_T5 652 } 653 654 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 655 return -EBUSY; 656 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 657 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 658 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 659 t4_write_reg(adap, edc_bist_cmd_reg, 660 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 661 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 662 if (i) 663 return i; 664 665#define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 666 667 for (i = 15; i >= 0; i--) 668 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 669 if (ecc) 670 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 671#undef EDC_DATA 672 return 0; 673} 674 675/** 676 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 677 * @adap: the adapter 678 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 679 * @addr: address within indicated memory type 680 * @len: amount of memory to read 681 * @buf: host memory buffer 682 * 683 * Reads an [almost] arbitrary memory region in the firmware: the 684 * firmware memory address, length and host buffer must be aligned on 685 * 32-bit boudaries. The memory is returned as a raw byte sequence from 686 * the firmware's memory. If this memory contains data structures which 687 * contain multi-byte integers, it's the callers responsibility to 688 * perform appropriate byte order conversions. 689 */ 690int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 691 __be32 *buf) 692{ 693 u32 pos, start, end, offset; 694 int ret; 695 696 /* 697 * Argument sanity checks ... 698 */ 699 if ((addr & 0x3) || (len & 0x3)) 700 return -EINVAL; 701 702 /* 703 * The underlaying EDC/MC read routines read 64 bytes at a time so we 704 * need to round down the start and round up the end. We'll start 705 * copying out of the first line at (addr - start) a word at a time. 706 */ 707 start = rounddown2(addr, 64); 708 end = roundup2(addr + len, 64); 709 offset = (addr - start)/sizeof(__be32); 710 711 for (pos = start; pos < end; pos += 64, offset = 0) { 712 __be32 data[16]; 713 714 /* 715 * Read the chip's memory block and bail if there's an error. 716 */ 717 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 718 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 719 else 720 ret = t4_edc_read(adap, mtype, pos, data, NULL); 721 if (ret) 722 return ret; 723 724 /* 725 * Copy the data into the caller's memory buffer. 726 */ 727 while (offset < 16 && len > 0) { 728 *buf++ = data[offset++]; 729 len -= sizeof(__be32); 730 } 731 } 732 733 return 0; 734} 735 736/* 737 * Return the specified PCI-E Configuration Space register from our Physical 738 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 739 * since we prefer to let the firmware own all of these registers, but if that 740 * fails we go for it directly ourselves. 741 */ 742u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 743{ 744 745 /* 746 * If fw_attach != 0, construct and send the Firmware LDST Command to 747 * retrieve the specified PCI-E Configuration Space register. 748 */ 749 if (drv_fw_attach != 0) { 750 struct fw_ldst_cmd ldst_cmd; 751 int ret; 752 753 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 754 ldst_cmd.op_to_addrspace = 755 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 756 F_FW_CMD_REQUEST | 757 F_FW_CMD_READ | 758 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 759 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 760 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 761 ldst_cmd.u.pcie.ctrl_to_fn = 762 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 763 ldst_cmd.u.pcie.r = reg; 764 765 /* 766 * If the LDST Command succeeds, return the result, otherwise 767 * fall through to reading it directly ourselves ... 768 */ 769 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 770 &ldst_cmd); 771 if (ret == 0) 772 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 773 774 CH_WARN(adap, "Firmware failed to return " 775 "Configuration Space register %d, err = %d\n", 776 reg, -ret); 777 } 778 779 /* 780 * Read the desired Configuration Space register via the PCI-E 781 * Backdoor mechanism. 782 */ 783 return t4_hw_pci_read_cfg4(adap, reg); 784} 785 786/** 787 * t4_get_regs_len - return the size of the chips register set 788 * @adapter: the adapter 789 * 790 * Returns the size of the chip's BAR0 register space. 791 */ 792unsigned int t4_get_regs_len(struct adapter *adapter) 793{ 794 unsigned int chip_version = chip_id(adapter); 795 796 switch (chip_version) { 797 case CHELSIO_T4: 798 if (adapter->flags & IS_VF) 799 return FW_T4VF_REGMAP_SIZE; 800 return T4_REGMAP_SIZE; 801 802 case CHELSIO_T5: 803 case CHELSIO_T6: 804 if (adapter->flags & IS_VF) 805 return FW_T4VF_REGMAP_SIZE; 806 return T5_REGMAP_SIZE; 807 } 808 809 CH_ERR(adapter, 810 "Unsupported chip version %d\n", chip_version); 811 return 0; 812} 813 814/** 815 * t4_get_regs - read chip registers into provided buffer 816 * @adap: the adapter 817 * @buf: register buffer 818 * @buf_size: size (in bytes) of register buffer 819 * 820 * If the provided register buffer isn't large enough for the chip's 821 * full register range, the register dump will be truncated to the 822 * register buffer's size. 823 */ 824void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 825{ 826 static const unsigned int t4_reg_ranges[] = { 827 0x1008, 0x1108, 828 0x1180, 0x1184, 829 0x1190, 0x1194, 830 0x11a0, 0x11a4, 831 0x11b0, 0x11b4, 832 0x11fc, 0x123c, 833 0x1300, 0x173c, 834 0x1800, 0x18fc, 835 0x3000, 0x30d8, 836 0x30e0, 0x30e4, 837 0x30ec, 0x5910, 838 0x5920, 0x5924, 839 0x5960, 0x5960, 840 0x5968, 0x5968, 841 0x5970, 0x5970, 842 0x5978, 0x5978, 843 0x5980, 0x5980, 844 0x5988, 0x5988, 845 0x5990, 0x5990, 846 0x5998, 0x5998, 847 0x59a0, 0x59d4, 848 0x5a00, 0x5ae0, 849 0x5ae8, 0x5ae8, 850 0x5af0, 0x5af0, 851 0x5af8, 0x5af8, 852 0x6000, 0x6098, 853 0x6100, 0x6150, 854 0x6200, 0x6208, 855 0x6240, 0x6248, 856 0x6280, 0x62b0, 857 0x62c0, 0x6338, 858 0x6370, 0x638c, 859 0x6400, 0x643c, 860 0x6500, 0x6524, 861 0x6a00, 0x6a04, 862 0x6a14, 0x6a38, 863 0x6a60, 0x6a70, 864 0x6a78, 0x6a78, 865 0x6b00, 0x6b0c, 866 0x6b1c, 0x6b84, 867 0x6bf0, 0x6bf8, 868 0x6c00, 0x6c0c, 869 0x6c1c, 0x6c84, 870 0x6cf0, 0x6cf8, 871 0x6d00, 0x6d0c, 872 0x6d1c, 0x6d84, 873 0x6df0, 0x6df8, 874 0x6e00, 0x6e0c, 875 0x6e1c, 0x6e84, 876 0x6ef0, 0x6ef8, 877 0x6f00, 0x6f0c, 878 0x6f1c, 0x6f84, 879 0x6ff0, 0x6ff8, 880 0x7000, 0x700c, 881 0x701c, 0x7084, 882 0x70f0, 0x70f8, 883 0x7100, 0x710c, 884 0x711c, 0x7184, 885 0x71f0, 0x71f8, 886 0x7200, 0x720c, 887 0x721c, 0x7284, 888 0x72f0, 0x72f8, 889 0x7300, 0x730c, 890 0x731c, 0x7384, 891 0x73f0, 0x73f8, 892 0x7400, 0x7450, 893 0x7500, 0x7530, 894 0x7600, 0x760c, 895 0x7614, 0x761c, 896 0x7680, 0x76cc, 897 0x7700, 0x7798, 898 0x77c0, 0x77fc, 899 0x7900, 0x79fc, 900 0x7b00, 0x7b58, 901 0x7b60, 0x7b84, 902 0x7b8c, 0x7c38, 903 0x7d00, 0x7d38, 904 0x7d40, 0x7d80, 905 0x7d8c, 0x7ddc, 906 0x7de4, 0x7e04, 907 0x7e10, 0x7e1c, 908 0x7e24, 0x7e38, 909 0x7e40, 0x7e44, 910 0x7e4c, 0x7e78, 911 0x7e80, 0x7ea4, 912 0x7eac, 0x7edc, 913 0x7ee8, 0x7efc, 914 0x8dc0, 0x8e04, 915 0x8e10, 0x8e1c, 916 0x8e30, 0x8e78, 917 0x8ea0, 0x8eb8, 918 0x8ec0, 0x8f6c, 919 0x8fc0, 0x9008, 920 0x9010, 0x9058, 921 0x9060, 0x9060, 922 0x9068, 0x9074, 923 0x90fc, 0x90fc, 924 0x9400, 0x9408, 925 0x9410, 0x9458, 926 0x9600, 0x9600, 927 0x9608, 0x9638, 928 0x9640, 0x96bc, 929 0x9800, 0x9808, 930 0x9820, 0x983c, 931 0x9850, 0x9864, 932 0x9c00, 0x9c6c, 933 0x9c80, 0x9cec, 934 0x9d00, 0x9d6c, 935 0x9d80, 0x9dec, 936 0x9e00, 0x9e6c, 937 0x9e80, 0x9eec, 938 0x9f00, 0x9f6c, 939 0x9f80, 0x9fec, 940 0xd004, 0xd004, 941 0xd010, 0xd03c, 942 0xdfc0, 0xdfe0, 943 0xe000, 0xea7c, 944 0xf000, 0x11110, 945 0x11118, 0x11190, 946 0x19040, 0x1906c, 947 0x19078, 0x19080, 948 0x1908c, 0x190e4, 949 0x190f0, 0x190f8, 950 0x19100, 0x19110, 951 0x19120, 0x19124, 952 0x19150, 0x19194, 953 0x1919c, 0x191b0, 954 0x191d0, 0x191e8, 955 0x19238, 0x1924c, 956 0x193f8, 0x1943c, 957 0x1944c, 0x19474, 958 0x19490, 0x194e0, 959 0x194f0, 0x194f8, 960 0x19800, 0x19c08, 961 0x19c10, 0x19c90, 962 0x19ca0, 0x19ce4, 963 0x19cf0, 0x19d40, 964 0x19d50, 0x19d94, 965 0x19da0, 0x19de8, 966 0x19df0, 0x19e40, 967 0x19e50, 0x19e90, 968 0x19ea0, 0x19f4c, 969 0x1a000, 0x1a004, 970 0x1a010, 0x1a06c, 971 0x1a0b0, 0x1a0e4, 972 0x1a0ec, 0x1a0f4, 973 0x1a100, 0x1a108, 974 0x1a114, 0x1a120, 975 0x1a128, 0x1a130, 976 0x1a138, 0x1a138, 977 0x1a190, 0x1a1c4, 978 0x1a1fc, 0x1a1fc, 979 0x1e040, 0x1e04c, 980 0x1e284, 0x1e28c, 981 0x1e2c0, 0x1e2c0, 982 0x1e2e0, 0x1e2e0, 983 0x1e300, 0x1e384, 984 0x1e3c0, 0x1e3c8, 985 0x1e440, 0x1e44c, 986 0x1e684, 0x1e68c, 987 0x1e6c0, 0x1e6c0, 988 0x1e6e0, 0x1e6e0, 989 0x1e700, 0x1e784, 990 0x1e7c0, 0x1e7c8, 991 0x1e840, 0x1e84c, 992 0x1ea84, 0x1ea8c, 993 0x1eac0, 0x1eac0, 994 0x1eae0, 0x1eae0, 995 0x1eb00, 0x1eb84, 996 0x1ebc0, 0x1ebc8, 997 0x1ec40, 0x1ec4c, 998 0x1ee84, 0x1ee8c, 999 0x1eec0, 0x1eec0, 1000 0x1eee0, 0x1eee0, 1001 0x1ef00, 0x1ef84, 1002 0x1efc0, 0x1efc8, 1003 0x1f040, 0x1f04c, 1004 0x1f284, 0x1f28c, 1005 0x1f2c0, 0x1f2c0, 1006 0x1f2e0, 0x1f2e0, 1007 0x1f300, 0x1f384, 1008 0x1f3c0, 0x1f3c8, 1009 0x1f440, 0x1f44c, 1010 0x1f684, 0x1f68c, 1011 0x1f6c0, 0x1f6c0, 1012 0x1f6e0, 0x1f6e0, 1013 0x1f700, 0x1f784, 1014 0x1f7c0, 0x1f7c8, 1015 0x1f840, 0x1f84c, 1016 0x1fa84, 0x1fa8c, 1017 0x1fac0, 0x1fac0, 1018 0x1fae0, 0x1fae0, 1019 0x1fb00, 0x1fb84, 1020 0x1fbc0, 0x1fbc8, 1021 0x1fc40, 0x1fc4c, 1022 0x1fe84, 0x1fe8c, 1023 0x1fec0, 0x1fec0, 1024 0x1fee0, 0x1fee0, 1025 0x1ff00, 0x1ff84, 1026 0x1ffc0, 0x1ffc8, 1027 0x20000, 0x2002c, 1028 0x20100, 0x2013c, 1029 0x20190, 0x201a0, 1030 0x201a8, 0x201b8, 1031 0x201c4, 0x201c8, 1032 0x20200, 0x20318, 1033 0x20400, 0x204b4, 1034 0x204c0, 0x20528, 1035 0x20540, 0x20614, 1036 0x21000, 0x21040, 1037 0x2104c, 0x21060, 1038 0x210c0, 0x210ec, 1039 0x21200, 0x21268, 1040 0x21270, 0x21284, 1041 0x212fc, 0x21388, 1042 0x21400, 0x21404, 1043 0x21500, 0x21500, 1044 0x21510, 0x21518, 1045 0x2152c, 0x21530, 1046 0x2153c, 0x2153c, 1047 0x21550, 0x21554, 1048 0x21600, 0x21600, 1049 0x21608, 0x2161c, 1050 0x21624, 0x21628, 1051 0x21630, 0x21634, 1052 0x2163c, 0x2163c, 1053 0x21700, 0x2171c, 1054 0x21780, 0x2178c, 1055 0x21800, 0x21818, 1056 0x21820, 0x21828, 1057 0x21830, 0x21848, 1058 0x21850, 0x21854, 1059 0x21860, 0x21868, 1060 0x21870, 0x21870, 1061 0x21878, 0x21898, 1062 0x218a0, 0x218a8, 1063 0x218b0, 0x218c8, 1064 0x218d0, 0x218d4, 1065 0x218e0, 0x218e8, 1066 0x218f0, 0x218f0, 1067 0x218f8, 0x21a18, 1068 0x21a20, 0x21a28, 1069 0x21a30, 0x21a48, 1070 0x21a50, 0x21a54, 1071 0x21a60, 0x21a68, 1072 0x21a70, 0x21a70, 1073 0x21a78, 0x21a98, 1074 0x21aa0, 0x21aa8, 1075 0x21ab0, 0x21ac8, 1076 0x21ad0, 0x21ad4, 1077 0x21ae0, 0x21ae8, 1078 0x21af0, 0x21af0, 1079 0x21af8, 0x21c18, 1080 0x21c20, 0x21c20, 1081 0x21c28, 0x21c30, 1082 0x21c38, 0x21c38, 1083 0x21c80, 0x21c98, 1084 0x21ca0, 0x21ca8, 1085 0x21cb0, 0x21cc8, 1086 0x21cd0, 0x21cd4, 1087 0x21ce0, 0x21ce8, 1088 0x21cf0, 0x21cf0, 1089 0x21cf8, 0x21d7c, 1090 0x21e00, 0x21e04, 1091 0x22000, 0x2202c, 1092 0x22100, 0x2213c, 1093 0x22190, 0x221a0, 1094 0x221a8, 0x221b8, 1095 0x221c4, 0x221c8, 1096 0x22200, 0x22318, 1097 0x22400, 0x224b4, 1098 0x224c0, 0x22528, 1099 0x22540, 0x22614, 1100 0x23000, 0x23040, 1101 0x2304c, 0x23060, 1102 0x230c0, 0x230ec, 1103 0x23200, 0x23268, 1104 0x23270, 0x23284, 1105 0x232fc, 0x23388, 1106 0x23400, 0x23404, 1107 0x23500, 0x23500, 1108 0x23510, 0x23518, 1109 0x2352c, 0x23530, 1110 0x2353c, 0x2353c, 1111 0x23550, 0x23554, 1112 0x23600, 0x23600, 1113 0x23608, 0x2361c, 1114 0x23624, 0x23628, 1115 0x23630, 0x23634, 1116 0x2363c, 0x2363c, 1117 0x23700, 0x2371c, 1118 0x23780, 0x2378c, 1119 0x23800, 0x23818, 1120 0x23820, 0x23828, 1121 0x23830, 0x23848, 1122 0x23850, 0x23854, 1123 0x23860, 0x23868, 1124 0x23870, 0x23870, 1125 0x23878, 0x23898, 1126 0x238a0, 0x238a8, 1127 0x238b0, 0x238c8, 1128 0x238d0, 0x238d4, 1129 0x238e0, 0x238e8, 1130 0x238f0, 0x238f0, 1131 0x238f8, 0x23a18, 1132 0x23a20, 0x23a28, 1133 0x23a30, 0x23a48, 1134 0x23a50, 0x23a54, 1135 0x23a60, 0x23a68, 1136 0x23a70, 0x23a70, 1137 0x23a78, 0x23a98, 1138 0x23aa0, 0x23aa8, 1139 0x23ab0, 0x23ac8, 1140 0x23ad0, 0x23ad4, 1141 0x23ae0, 0x23ae8, 1142 0x23af0, 0x23af0, 1143 0x23af8, 0x23c18, 1144 0x23c20, 0x23c20, 1145 0x23c28, 0x23c30, 1146 0x23c38, 0x23c38, 1147 0x23c80, 0x23c98, 1148 0x23ca0, 0x23ca8, 1149 0x23cb0, 0x23cc8, 1150 0x23cd0, 0x23cd4, 1151 0x23ce0, 0x23ce8, 1152 0x23cf0, 0x23cf0, 1153 0x23cf8, 0x23d7c, 1154 0x23e00, 0x23e04, 1155 0x24000, 0x2402c, 1156 0x24100, 0x2413c, 1157 0x24190, 0x241a0, 1158 0x241a8, 0x241b8, 1159 0x241c4, 0x241c8, 1160 0x24200, 0x24318, 1161 0x24400, 0x244b4, 1162 0x244c0, 0x24528, 1163 0x24540, 0x24614, 1164 0x25000, 0x25040, 1165 0x2504c, 0x25060, 1166 0x250c0, 0x250ec, 1167 0x25200, 0x25268, 1168 0x25270, 0x25284, 1169 0x252fc, 0x25388, 1170 0x25400, 0x25404, 1171 0x25500, 0x25500, 1172 0x25510, 0x25518, 1173 0x2552c, 0x25530, 1174 0x2553c, 0x2553c, 1175 0x25550, 0x25554, 1176 0x25600, 0x25600, 1177 0x25608, 0x2561c, 1178 0x25624, 0x25628, 1179 0x25630, 0x25634, 1180 0x2563c, 0x2563c, 1181 0x25700, 0x2571c, 1182 0x25780, 0x2578c, 1183 0x25800, 0x25818, 1184 0x25820, 0x25828, 1185 0x25830, 0x25848, 1186 0x25850, 0x25854, 1187 0x25860, 0x25868, 1188 0x25870, 0x25870, 1189 0x25878, 0x25898, 1190 0x258a0, 0x258a8, 1191 0x258b0, 0x258c8, 1192 0x258d0, 0x258d4, 1193 0x258e0, 0x258e8, 1194 0x258f0, 0x258f0, 1195 0x258f8, 0x25a18, 1196 0x25a20, 0x25a28, 1197 0x25a30, 0x25a48, 1198 0x25a50, 0x25a54, 1199 0x25a60, 0x25a68, 1200 0x25a70, 0x25a70, 1201 0x25a78, 0x25a98, 1202 0x25aa0, 0x25aa8, 1203 0x25ab0, 0x25ac8, 1204 0x25ad0, 0x25ad4, 1205 0x25ae0, 0x25ae8, 1206 0x25af0, 0x25af0, 1207 0x25af8, 0x25c18, 1208 0x25c20, 0x25c20, 1209 0x25c28, 0x25c30, 1210 0x25c38, 0x25c38, 1211 0x25c80, 0x25c98, 1212 0x25ca0, 0x25ca8, 1213 0x25cb0, 0x25cc8, 1214 0x25cd0, 0x25cd4, 1215 0x25ce0, 0x25ce8, 1216 0x25cf0, 0x25cf0, 1217 0x25cf8, 0x25d7c, 1218 0x25e00, 0x25e04, 1219 0x26000, 0x2602c, 1220 0x26100, 0x2613c, 1221 0x26190, 0x261a0, 1222 0x261a8, 0x261b8, 1223 0x261c4, 0x261c8, 1224 0x26200, 0x26318, 1225 0x26400, 0x264b4, 1226 0x264c0, 0x26528, 1227 0x26540, 0x26614, 1228 0x27000, 0x27040, 1229 0x2704c, 0x27060, 1230 0x270c0, 0x270ec, 1231 0x27200, 0x27268, 1232 0x27270, 0x27284, 1233 0x272fc, 0x27388, 1234 0x27400, 0x27404, 1235 0x27500, 0x27500, 1236 0x27510, 0x27518, 1237 0x2752c, 0x27530, 1238 0x2753c, 0x2753c, 1239 0x27550, 0x27554, 1240 0x27600, 0x27600, 1241 0x27608, 0x2761c, 1242 0x27624, 0x27628, 1243 0x27630, 0x27634, 1244 0x2763c, 0x2763c, 1245 0x27700, 0x2771c, 1246 0x27780, 0x2778c, 1247 0x27800, 0x27818, 1248 0x27820, 0x27828, 1249 0x27830, 0x27848, 1250 0x27850, 0x27854, 1251 0x27860, 0x27868, 1252 0x27870, 0x27870, 1253 0x27878, 0x27898, 1254 0x278a0, 0x278a8, 1255 0x278b0, 0x278c8, 1256 0x278d0, 0x278d4, 1257 0x278e0, 0x278e8, 1258 0x278f0, 0x278f0, 1259 0x278f8, 0x27a18, 1260 0x27a20, 0x27a28, 1261 0x27a30, 0x27a48, 1262 0x27a50, 0x27a54, 1263 0x27a60, 0x27a68, 1264 0x27a70, 0x27a70, 1265 0x27a78, 0x27a98, 1266 0x27aa0, 0x27aa8, 1267 0x27ab0, 0x27ac8, 1268 0x27ad0, 0x27ad4, 1269 0x27ae0, 0x27ae8, 1270 0x27af0, 0x27af0, 1271 0x27af8, 0x27c18, 1272 0x27c20, 0x27c20, 1273 0x27c28, 0x27c30, 1274 0x27c38, 0x27c38, 1275 0x27c80, 0x27c98, 1276 0x27ca0, 0x27ca8, 1277 0x27cb0, 0x27cc8, 1278 0x27cd0, 0x27cd4, 1279 0x27ce0, 0x27ce8, 1280 0x27cf0, 0x27cf0, 1281 0x27cf8, 0x27d7c, 1282 0x27e00, 0x27e04, 1283 }; 1284 1285 static const unsigned int t4vf_reg_ranges[] = { 1286 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1287 VF_MPS_REG(A_MPS_VF_CTL), 1288 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1289 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1290 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1291 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1292 FW_T4VF_MBDATA_BASE_ADDR, 1293 FW_T4VF_MBDATA_BASE_ADDR + 1294 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1295 }; 1296 1297 static const unsigned int t5_reg_ranges[] = { 1298 0x1008, 0x10c0, 1299 0x10cc, 0x10f8, 1300 0x1100, 0x1100, 1301 0x110c, 0x1148, 1302 0x1180, 0x1184, 1303 0x1190, 0x1194, 1304 0x11a0, 0x11a4, 1305 0x11b0, 0x11b4, 1306 0x11fc, 0x123c, 1307 0x1280, 0x173c, 1308 0x1800, 0x18fc, 1309 0x3000, 0x3028, 1310 0x3060, 0x30b0, 1311 0x30b8, 0x30d8, 1312 0x30e0, 0x30fc, 1313 0x3140, 0x357c, 1314 0x35a8, 0x35cc, 1315 0x35ec, 0x35ec, 1316 0x3600, 0x5624, 1317 0x56cc, 0x56ec, 1318 0x56f4, 0x5720, 1319 0x5728, 0x575c, 1320 0x580c, 0x5814, 1321 0x5890, 0x589c, 1322 0x58a4, 0x58ac, 1323 0x58b8, 0x58bc, 1324 0x5940, 0x59c8, 1325 0x59d0, 0x59dc, 1326 0x59fc, 0x5a18, 1327 0x5a60, 0x5a70, 1328 0x5a80, 0x5a9c, 1329 0x5b94, 0x5bfc, 1330 0x6000, 0x6020, 1331 0x6028, 0x6040, 1332 0x6058, 0x609c, 1333 0x60a8, 0x614c, 1334 0x7700, 0x7798, 1335 0x77c0, 0x78fc, 1336 0x7b00, 0x7b58, 1337 0x7b60, 0x7b84, 1338 0x7b8c, 0x7c54, 1339 0x7d00, 0x7d38, 1340 0x7d40, 0x7d80, 1341 0x7d8c, 0x7ddc, 1342 0x7de4, 0x7e04, 1343 0x7e10, 0x7e1c, 1344 0x7e24, 0x7e38, 1345 0x7e40, 0x7e44, 1346 0x7e4c, 0x7e78, 1347 0x7e80, 0x7edc, 1348 0x7ee8, 0x7efc, 1349 0x8dc0, 0x8de0, 1350 0x8df8, 0x8e04, 1351 0x8e10, 0x8e84, 1352 0x8ea0, 0x8f84, 1353 0x8fc0, 0x9058, 1354 0x9060, 0x9060, 1355 0x9068, 0x90f8, 1356 0x9400, 0x9408, 1357 0x9410, 0x9470, 1358 0x9600, 0x9600, 1359 0x9608, 0x9638, 1360 0x9640, 0x96f4, 1361 0x9800, 0x9808, 1362 0x9810, 0x9864, 1363 0x9c00, 0x9c6c, 1364 0x9c80, 0x9cec, 1365 0x9d00, 0x9d6c, 1366 0x9d80, 0x9dec, 1367 0x9e00, 0x9e6c, 1368 0x9e80, 0x9eec, 1369 0x9f00, 0x9f6c, 1370 0x9f80, 0xa020, 1371 0xd000, 0xd004, 1372 0xd010, 0xd03c, 1373 0xdfc0, 0xdfe0, 1374 0xe000, 0x1106c, 1375 0x11074, 0x11088, 1376 0x1109c, 0x1117c, 1377 0x11190, 0x11204, 1378 0x19040, 0x1906c, 1379 0x19078, 0x19080, 1380 0x1908c, 0x190e8, 1381 0x190f0, 0x190f8, 1382 0x19100, 0x19110, 1383 0x19120, 0x19124, 1384 0x19150, 0x19194, 1385 0x1919c, 0x191b0, 1386 0x191d0, 0x191e8, 1387 0x19238, 0x19290, 1388 0x193f8, 0x19428, 1389 0x19430, 0x19444, 1390 0x1944c, 0x1946c, 1391 0x19474, 0x19474, 1392 0x19490, 0x194cc, 1393 0x194f0, 0x194f8, 1394 0x19c00, 0x19c08, 1395 0x19c10, 0x19c60, 1396 0x19c94, 0x19ce4, 1397 0x19cf0, 0x19d40, 1398 0x19d50, 0x19d94, 1399 0x19da0, 0x19de8, 1400 0x19df0, 0x19e10, 1401 0x19e50, 0x19e90, 1402 0x19ea0, 0x19f24, 1403 0x19f34, 0x19f34, 1404 0x19f40, 0x19f50, 1405 0x19f90, 0x19fb4, 1406 0x19fc4, 0x19fe4, 1407 0x1a000, 0x1a004, 1408 0x1a010, 0x1a06c, 1409 0x1a0b0, 0x1a0e4, 1410 0x1a0ec, 0x1a0f8, 1411 0x1a100, 0x1a108, 1412 0x1a114, 0x1a130, 1413 0x1a138, 0x1a1c4, 1414 0x1a1fc, 0x1a1fc, 1415 0x1e008, 0x1e00c, 1416 0x1e040, 0x1e044, 1417 0x1e04c, 0x1e04c, 1418 0x1e284, 0x1e290, 1419 0x1e2c0, 0x1e2c0, 1420 0x1e2e0, 0x1e2e0, 1421 0x1e300, 0x1e384, 1422 0x1e3c0, 0x1e3c8, 1423 0x1e408, 0x1e40c, 1424 0x1e440, 0x1e444, 1425 0x1e44c, 0x1e44c, 1426 0x1e684, 0x1e690, 1427 0x1e6c0, 0x1e6c0, 1428 0x1e6e0, 0x1e6e0, 1429 0x1e700, 0x1e784, 1430 0x1e7c0, 0x1e7c8, 1431 0x1e808, 0x1e80c, 1432 0x1e840, 0x1e844, 1433 0x1e84c, 0x1e84c, 1434 0x1ea84, 0x1ea90, 1435 0x1eac0, 0x1eac0, 1436 0x1eae0, 0x1eae0, 1437 0x1eb00, 0x1eb84, 1438 0x1ebc0, 0x1ebc8, 1439 0x1ec08, 0x1ec0c, 1440 0x1ec40, 0x1ec44, 1441 0x1ec4c, 0x1ec4c, 1442 0x1ee84, 0x1ee90, 1443 0x1eec0, 0x1eec0, 1444 0x1eee0, 0x1eee0, 1445 0x1ef00, 0x1ef84, 1446 0x1efc0, 0x1efc8, 1447 0x1f008, 0x1f00c, 1448 0x1f040, 0x1f044, 1449 0x1f04c, 0x1f04c, 1450 0x1f284, 0x1f290, 1451 0x1f2c0, 0x1f2c0, 1452 0x1f2e0, 0x1f2e0, 1453 0x1f300, 0x1f384, 1454 0x1f3c0, 0x1f3c8, 1455 0x1f408, 0x1f40c, 1456 0x1f440, 0x1f444, 1457 0x1f44c, 0x1f44c, 1458 0x1f684, 0x1f690, 1459 0x1f6c0, 0x1f6c0, 1460 0x1f6e0, 0x1f6e0, 1461 0x1f700, 0x1f784, 1462 0x1f7c0, 0x1f7c8, 1463 0x1f808, 0x1f80c, 1464 0x1f840, 0x1f844, 1465 0x1f84c, 0x1f84c, 1466 0x1fa84, 0x1fa90, 1467 0x1fac0, 0x1fac0, 1468 0x1fae0, 0x1fae0, 1469 0x1fb00, 0x1fb84, 1470 0x1fbc0, 0x1fbc8, 1471 0x1fc08, 0x1fc0c, 1472 0x1fc40, 0x1fc44, 1473 0x1fc4c, 0x1fc4c, 1474 0x1fe84, 0x1fe90, 1475 0x1fec0, 0x1fec0, 1476 0x1fee0, 0x1fee0, 1477 0x1ff00, 0x1ff84, 1478 0x1ffc0, 0x1ffc8, 1479 0x30000, 0x30030, 1480 0x30100, 0x30144, 1481 0x30190, 0x301a0, 1482 0x301a8, 0x301b8, 1483 0x301c4, 0x301c8, 1484 0x301d0, 0x301d0, 1485 0x30200, 0x30318, 1486 0x30400, 0x304b4, 1487 0x304c0, 0x3052c, 1488 0x30540, 0x3061c, 1489 0x30800, 0x30828, 1490 0x30834, 0x30834, 1491 0x308c0, 0x30908, 1492 0x30910, 0x309ac, 1493 0x30a00, 0x30a14, 1494 0x30a1c, 0x30a2c, 1495 0x30a44, 0x30a50, 1496 0x30a74, 0x30a74, 1497 0x30a7c, 0x30afc, 1498 0x30b08, 0x30c24, 1499 0x30d00, 0x30d00, 1500 0x30d08, 0x30d14, 1501 0x30d1c, 0x30d20, 1502 0x30d3c, 0x30d3c, 1503 0x30d48, 0x30d50, 1504 0x31200, 0x3120c, 1505 0x31220, 0x31220, 1506 0x31240, 0x31240, 1507 0x31600, 0x3160c, 1508 0x31a00, 0x31a1c, 1509 0x31e00, 0x31e20, 1510 0x31e38, 0x31e3c, 1511 0x31e80, 0x31e80, 1512 0x31e88, 0x31ea8, 1513 0x31eb0, 0x31eb4, 1514 0x31ec8, 0x31ed4, 1515 0x31fb8, 0x32004, 1516 0x32200, 0x32200, 1517 0x32208, 0x32240, 1518 0x32248, 0x32280, 1519 0x32288, 0x322c0, 1520 0x322c8, 0x322fc, 1521 0x32600, 0x32630, 1522 0x32a00, 0x32abc, 1523 0x32b00, 0x32b10, 1524 0x32b20, 0x32b30, 1525 0x32b40, 0x32b50, 1526 0x32b60, 0x32b70, 1527 0x33000, 0x33028, 1528 0x33030, 0x33048, 1529 0x33060, 0x33068, 1530 0x33070, 0x3309c, 1531 0x330f0, 0x33128, 1532 0x33130, 0x33148, 1533 0x33160, 0x33168, 1534 0x33170, 0x3319c, 1535 0x331f0, 0x33238, 1536 0x33240, 0x33240, 1537 0x33248, 0x33250, 1538 0x3325c, 0x33264, 1539 0x33270, 0x332b8, 1540 0x332c0, 0x332e4, 1541 0x332f8, 0x33338, 1542 0x33340, 0x33340, 1543 0x33348, 0x33350, 1544 0x3335c, 0x33364, 1545 0x33370, 0x333b8, 1546 0x333c0, 0x333e4, 1547 0x333f8, 0x33428, 1548 0x33430, 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1592 0x341a8, 0x341b8, 1593 0x341c4, 0x341c8, 1594 0x341d0, 0x341d0, 1595 0x34200, 0x34318, 1596 0x34400, 0x344b4, 1597 0x344c0, 0x3452c, 1598 0x34540, 0x3461c, 1599 0x34800, 0x34828, 1600 0x34834, 0x34834, 1601 0x348c0, 0x34908, 1602 0x34910, 0x349ac, 1603 0x34a00, 0x34a14, 1604 0x34a1c, 0x34a2c, 1605 0x34a44, 0x34a50, 1606 0x34a74, 0x34a74, 1607 0x34a7c, 0x34afc, 1608 0x34b08, 0x34c24, 1609 0x34d00, 0x34d00, 1610 0x34d08, 0x34d14, 1611 0x34d1c, 0x34d20, 1612 0x34d3c, 0x34d3c, 1613 0x34d48, 0x34d50, 1614 0x35200, 0x3520c, 1615 0x35220, 0x35220, 1616 0x35240, 0x35240, 1617 0x35600, 0x3560c, 1618 0x35a00, 0x35a1c, 1619 0x35e00, 0x35e20, 1620 0x35e38, 0x35e3c, 1621 0x35e80, 0x35e80, 1622 0x35e88, 0x35ea8, 1623 0x35eb0, 0x35eb4, 1624 0x35ec8, 0x35ed4, 1625 0x35fb8, 0x36004, 1626 0x36200, 0x36200, 1627 0x36208, 0x36240, 1628 0x36248, 0x36280, 1629 0x36288, 0x362c0, 1630 0x362c8, 0x362fc, 1631 0x36600, 0x36630, 1632 0x36a00, 0x36abc, 1633 0x36b00, 0x36b10, 1634 0x36b20, 0x36b30, 1635 0x36b40, 0x36b50, 1636 0x36b60, 0x36b70, 1637 0x37000, 0x37028, 1638 0x37030, 0x37048, 1639 0x37060, 0x37068, 1640 0x37070, 0x3709c, 1641 0x370f0, 0x37128, 1642 0x37130, 0x37148, 1643 0x37160, 0x37168, 1644 0x37170, 0x3719c, 1645 0x371f0, 0x37238, 1646 0x37240, 0x37240, 1647 0x37248, 0x37250, 1648 0x3725c, 0x37264, 1649 0x37270, 0x372b8, 1650 0x372c0, 0x372e4, 1651 0x372f8, 0x37338, 1652 0x37340, 0x37340, 1653 0x37348, 0x37350, 1654 0x3735c, 0x37364, 1655 0x37370, 0x373b8, 1656 0x373c0, 0x373e4, 1657 0x373f8, 0x37428, 1658 0x37430, 0x37448, 1659 0x37460, 0x37468, 1660 0x37470, 0x3749c, 1661 0x374f0, 0x37528, 1662 0x37530, 0x37548, 1663 0x37560, 0x37568, 1664 0x37570, 0x3759c, 1665 0x375f0, 0x37638, 1666 0x37640, 0x37640, 1667 0x37648, 0x37650, 1668 0x3765c, 0x37664, 1669 0x37670, 0x376b8, 1670 0x376c0, 0x376e4, 1671 0x376f8, 0x37738, 1672 0x37740, 0x37740, 1673 0x37748, 0x37750, 1674 0x3775c, 0x37764, 1675 0x37770, 0x377b8, 1676 0x377c0, 0x377e4, 1677 0x377f8, 0x377fc, 1678 0x37814, 0x37814, 1679 0x3782c, 0x3782c, 1680 0x37880, 0x3788c, 1681 0x378e8, 0x378ec, 1682 0x37900, 0x37928, 1683 0x37930, 0x37948, 1684 0x37960, 0x37968, 1685 0x37970, 0x3799c, 1686 0x379f0, 0x37a38, 1687 0x37a40, 0x37a40, 1688 0x37a48, 0x37a50, 1689 0x37a5c, 0x37a64, 1690 0x37a70, 0x37ab8, 1691 0x37ac0, 0x37ae4, 1692 0x37af8, 0x37b10, 1693 0x37b28, 0x37b28, 1694 0x37b3c, 0x37b50, 1695 0x37bf0, 0x37c10, 1696 0x37c28, 0x37c28, 1697 0x37c3c, 0x37c50, 1698 0x37cf0, 0x37cfc, 1699 0x38000, 0x38030, 1700 0x38100, 0x38144, 1701 0x38190, 0x381a0, 1702 0x381a8, 0x381b8, 1703 0x381c4, 0x381c8, 1704 0x381d0, 0x381d0, 1705 0x38200, 0x38318, 1706 0x38400, 0x384b4, 1707 0x384c0, 0x3852c, 1708 0x38540, 0x3861c, 1709 0x38800, 0x38828, 1710 0x38834, 0x38834, 1711 0x388c0, 0x38908, 1712 0x38910, 0x389ac, 1713 0x38a00, 0x38a14, 1714 0x38a1c, 0x38a2c, 1715 0x38a44, 0x38a50, 1716 0x38a74, 0x38a74, 1717 0x38a7c, 0x38afc, 1718 0x38b08, 0x38c24, 1719 0x38d00, 0x38d00, 1720 0x38d08, 0x38d14, 1721 0x38d1c, 0x38d20, 1722 0x38d3c, 0x38d3c, 1723 0x38d48, 0x38d50, 1724 0x39200, 0x3920c, 1725 0x39220, 0x39220, 1726 0x39240, 0x39240, 1727 0x39600, 0x3960c, 1728 0x39a00, 0x39a1c, 1729 0x39e00, 0x39e20, 1730 0x39e38, 0x39e3c, 1731 0x39e80, 0x39e80, 1732 0x39e88, 0x39ea8, 1733 0x39eb0, 0x39eb4, 1734 0x39ec8, 0x39ed4, 1735 0x39fb8, 0x3a004, 1736 0x3a200, 0x3a200, 1737 0x3a208, 0x3a240, 1738 0x3a248, 0x3a280, 1739 0x3a288, 0x3a2c0, 1740 0x3a2c8, 0x3a2fc, 1741 0x3a600, 0x3a630, 1742 0x3aa00, 0x3aabc, 1743 0x3ab00, 0x3ab10, 1744 0x3ab20, 0x3ab30, 1745 0x3ab40, 0x3ab50, 1746 0x3ab60, 0x3ab70, 1747 0x3b000, 0x3b028, 1748 0x3b030, 0x3b048, 1749 0x3b060, 0x3b068, 1750 0x3b070, 0x3b09c, 1751 0x3b0f0, 0x3b128, 1752 0x3b130, 0x3b148, 1753 0x3b160, 0x3b168, 1754 0x3b170, 0x3b19c, 1755 0x3b1f0, 0x3b238, 1756 0x3b240, 0x3b240, 1757 0x3b248, 0x3b250, 1758 0x3b25c, 0x3b264, 1759 0x3b270, 0x3b2b8, 1760 0x3b2c0, 0x3b2e4, 1761 0x3b2f8, 0x3b338, 1762 0x3b340, 0x3b340, 1763 0x3b348, 0x3b350, 1764 0x3b35c, 0x3b364, 1765 0x3b370, 0x3b3b8, 1766 0x3b3c0, 0x3b3e4, 1767 0x3b3f8, 0x3b428, 1768 0x3b430, 0x3b448, 1769 0x3b460, 0x3b468, 1770 0x3b470, 0x3b49c, 1771 0x3b4f0, 0x3b528, 1772 0x3b530, 0x3b548, 1773 0x3b560, 0x3b568, 1774 0x3b570, 0x3b59c, 1775 0x3b5f0, 0x3b638, 1776 0x3b640, 0x3b640, 1777 0x3b648, 0x3b650, 1778 0x3b65c, 0x3b664, 1779 0x3b670, 0x3b6b8, 1780 0x3b6c0, 0x3b6e4, 1781 0x3b6f8, 0x3b738, 1782 0x3b740, 0x3b740, 1783 0x3b748, 0x3b750, 1784 0x3b75c, 0x3b764, 1785 0x3b770, 0x3b7b8, 1786 0x3b7c0, 0x3b7e4, 1787 0x3b7f8, 0x3b7fc, 1788 0x3b814, 0x3b814, 1789 0x3b82c, 0x3b82c, 1790 0x3b880, 0x3b88c, 1791 0x3b8e8, 0x3b8ec, 1792 0x3b900, 0x3b928, 1793 0x3b930, 0x3b948, 1794 0x3b960, 0x3b968, 1795 0x3b970, 0x3b99c, 1796 0x3b9f0, 0x3ba38, 1797 0x3ba40, 0x3ba40, 1798 0x3ba48, 0x3ba50, 1799 0x3ba5c, 0x3ba64, 1800 0x3ba70, 0x3bab8, 1801 0x3bac0, 0x3bae4, 1802 0x3baf8, 0x3bb10, 1803 0x3bb28, 0x3bb28, 1804 0x3bb3c, 0x3bb50, 1805 0x3bbf0, 0x3bc10, 1806 0x3bc28, 0x3bc28, 1807 0x3bc3c, 0x3bc50, 1808 0x3bcf0, 0x3bcfc, 1809 0x3c000, 0x3c030, 1810 0x3c100, 0x3c144, 1811 0x3c190, 0x3c1a0, 1812 0x3c1a8, 0x3c1b8, 1813 0x3c1c4, 0x3c1c8, 1814 0x3c1d0, 0x3c1d0, 1815 0x3c200, 0x3c318, 1816 0x3c400, 0x3c4b4, 1817 0x3c4c0, 0x3c52c, 1818 0x3c540, 0x3c61c, 1819 0x3c800, 0x3c828, 1820 0x3c834, 0x3c834, 1821 0x3c8c0, 0x3c908, 1822 0x3c910, 0x3c9ac, 1823 0x3ca00, 0x3ca14, 1824 0x3ca1c, 0x3ca2c, 1825 0x3ca44, 0x3ca50, 1826 0x3ca74, 0x3ca74, 1827 0x3ca7c, 0x3cafc, 1828 0x3cb08, 0x3cc24, 1829 0x3cd00, 0x3cd00, 1830 0x3cd08, 0x3cd14, 1831 0x3cd1c, 0x3cd20, 1832 0x3cd3c, 0x3cd3c, 1833 0x3cd48, 0x3cd50, 1834 0x3d200, 0x3d20c, 1835 0x3d220, 0x3d220, 1836 0x3d240, 0x3d240, 1837 0x3d600, 0x3d60c, 1838 0x3da00, 0x3da1c, 1839 0x3de00, 0x3de20, 1840 0x3de38, 0x3de3c, 1841 0x3de80, 0x3de80, 1842 0x3de88, 0x3dea8, 1843 0x3deb0, 0x3deb4, 1844 0x3dec8, 0x3ded4, 1845 0x3dfb8, 0x3e004, 1846 0x3e200, 0x3e200, 1847 0x3e208, 0x3e240, 1848 0x3e248, 0x3e280, 1849 0x3e288, 0x3e2c0, 1850 0x3e2c8, 0x3e2fc, 1851 0x3e600, 0x3e630, 1852 0x3ea00, 0x3eabc, 1853 0x3eb00, 0x3eb10, 1854 0x3eb20, 0x3eb30, 1855 0x3eb40, 0x3eb50, 1856 0x3eb60, 0x3eb70, 1857 0x3f000, 0x3f028, 1858 0x3f030, 0x3f048, 1859 0x3f060, 0x3f068, 1860 0x3f070, 0x3f09c, 1861 0x3f0f0, 0x3f128, 1862 0x3f130, 0x3f148, 1863 0x3f160, 0x3f168, 1864 0x3f170, 0x3f19c, 1865 0x3f1f0, 0x3f238, 1866 0x3f240, 0x3f240, 1867 0x3f248, 0x3f250, 1868 0x3f25c, 0x3f264, 1869 0x3f270, 0x3f2b8, 1870 0x3f2c0, 0x3f2e4, 1871 0x3f2f8, 0x3f338, 1872 0x3f340, 0x3f340, 1873 0x3f348, 0x3f350, 1874 0x3f35c, 0x3f364, 1875 0x3f370, 0x3f3b8, 1876 0x3f3c0, 0x3f3e4, 1877 0x3f3f8, 0x3f428, 1878 0x3f430, 0x3f448, 1879 0x3f460, 0x3f468, 1880 0x3f470, 0x3f49c, 1881 0x3f4f0, 0x3f528, 1882 0x3f530, 0x3f548, 1883 0x3f560, 0x3f568, 1884 0x3f570, 0x3f59c, 1885 0x3f5f0, 0x3f638, 1886 0x3f640, 0x3f640, 1887 0x3f648, 0x3f650, 1888 0x3f65c, 0x3f664, 1889 0x3f670, 0x3f6b8, 1890 0x3f6c0, 0x3f6e4, 1891 0x3f6f8, 0x3f738, 1892 0x3f740, 0x3f740, 1893 0x3f748, 0x3f750, 1894 0x3f75c, 0x3f764, 1895 0x3f770, 0x3f7b8, 1896 0x3f7c0, 0x3f7e4, 1897 0x3f7f8, 0x3f7fc, 1898 0x3f814, 0x3f814, 1899 0x3f82c, 0x3f82c, 1900 0x3f880, 0x3f88c, 1901 0x3f8e8, 0x3f8ec, 1902 0x3f900, 0x3f928, 1903 0x3f930, 0x3f948, 1904 0x3f960, 0x3f968, 1905 0x3f970, 0x3f99c, 1906 0x3f9f0, 0x3fa38, 1907 0x3fa40, 0x3fa40, 1908 0x3fa48, 0x3fa50, 1909 0x3fa5c, 0x3fa64, 1910 0x3fa70, 0x3fab8, 1911 0x3fac0, 0x3fae4, 1912 0x3faf8, 0x3fb10, 1913 0x3fb28, 0x3fb28, 1914 0x3fb3c, 0x3fb50, 1915 0x3fbf0, 0x3fc10, 1916 0x3fc28, 0x3fc28, 1917 0x3fc3c, 0x3fc50, 1918 0x3fcf0, 0x3fcfc, 1919 0x40000, 0x4000c, 1920 0x40040, 0x40050, 1921 0x40060, 0x40068, 1922 0x4007c, 0x4008c, 1923 0x40094, 0x400b0, 1924 0x400c0, 0x40144, 1925 0x40180, 0x4018c, 1926 0x40200, 0x40254, 1927 0x40260, 0x40264, 1928 0x40270, 0x40288, 1929 0x40290, 0x40298, 1930 0x402ac, 0x402c8, 1931 0x402d0, 0x402e0, 1932 0x402f0, 0x402f0, 1933 0x40300, 0x4033c, 1934 0x403f8, 0x403fc, 1935 0x41304, 0x413c4, 1936 0x41400, 0x4140c, 1937 0x41414, 0x4141c, 1938 0x41480, 0x414d0, 1939 0x44000, 0x44054, 1940 0x4405c, 0x44078, 1941 0x440c0, 0x44174, 1942 0x44180, 0x441ac, 1943 0x441b4, 0x441b8, 1944 0x441c0, 0x44254, 1945 0x4425c, 0x44278, 1946 0x442c0, 0x44374, 1947 0x44380, 0x443ac, 1948 0x443b4, 0x443b8, 1949 0x443c0, 0x44454, 1950 0x4445c, 0x44478, 1951 0x444c0, 0x44574, 1952 0x44580, 0x445ac, 1953 0x445b4, 0x445b8, 1954 0x445c0, 0x44654, 1955 0x4465c, 0x44678, 1956 0x446c0, 0x44774, 1957 0x44780, 0x447ac, 1958 0x447b4, 0x447b8, 1959 0x447c0, 0x44854, 1960 0x4485c, 0x44878, 1961 0x448c0, 0x44974, 1962 0x44980, 0x449ac, 1963 0x449b4, 0x449b8, 1964 0x449c0, 0x449fc, 1965 0x45000, 0x45004, 1966 0x45010, 0x45030, 1967 0x45040, 0x45060, 1968 0x45068, 0x45068, 1969 0x45080, 0x45084, 1970 0x450a0, 0x450b0, 1971 0x45200, 0x45204, 1972 0x45210, 0x45230, 1973 0x45240, 0x45260, 1974 0x45268, 0x45268, 1975 0x45280, 0x45284, 1976 0x452a0, 0x452b0, 1977 0x460c0, 0x460e4, 1978 0x47000, 0x4703c, 1979 0x47044, 0x4708c, 1980 0x47200, 0x47250, 1981 0x47400, 0x47408, 1982 0x47414, 0x47420, 1983 0x47600, 0x47618, 1984 0x47800, 0x47814, 1985 0x48000, 0x4800c, 1986 0x48040, 0x48050, 1987 0x48060, 0x48068, 1988 0x4807c, 0x4808c, 1989 0x48094, 0x480b0, 1990 0x480c0, 0x48144, 1991 0x48180, 0x4818c, 1992 0x48200, 0x48254, 1993 0x48260, 0x48264, 1994 0x48270, 0x48288, 1995 0x48290, 0x48298, 1996 0x482ac, 0x482c8, 1997 0x482d0, 0x482e0, 1998 0x482f0, 0x482f0, 1999 0x48300, 0x4833c, 2000 0x483f8, 0x483fc, 2001 0x49304, 0x493c4, 2002 0x49400, 0x4940c, 2003 0x49414, 0x4941c, 2004 0x49480, 0x494d0, 2005 0x4c000, 0x4c054, 2006 0x4c05c, 0x4c078, 2007 0x4c0c0, 0x4c174, 2008 0x4c180, 0x4c1ac, 2009 0x4c1b4, 0x4c1b8, 2010 0x4c1c0, 0x4c254, 2011 0x4c25c, 0x4c278, 2012 0x4c2c0, 0x4c374, 2013 0x4c380, 0x4c3ac, 2014 0x4c3b4, 0x4c3b8, 2015 0x4c3c0, 0x4c454, 2016 0x4c45c, 0x4c478, 2017 0x4c4c0, 0x4c574, 2018 0x4c580, 0x4c5ac, 2019 0x4c5b4, 0x4c5b8, 2020 0x4c5c0, 0x4c654, 2021 0x4c65c, 0x4c678, 2022 0x4c6c0, 0x4c774, 2023 0x4c780, 0x4c7ac, 2024 0x4c7b4, 0x4c7b8, 2025 0x4c7c0, 0x4c854, 2026 0x4c85c, 0x4c878, 2027 0x4c8c0, 0x4c974, 2028 0x4c980, 0x4c9ac, 2029 0x4c9b4, 0x4c9b8, 2030 0x4c9c0, 0x4c9fc, 2031 0x4d000, 0x4d004, 2032 0x4d010, 0x4d030, 2033 0x4d040, 0x4d060, 2034 0x4d068, 0x4d068, 2035 0x4d080, 0x4d084, 2036 0x4d0a0, 0x4d0b0, 2037 0x4d200, 0x4d204, 2038 0x4d210, 0x4d230, 2039 0x4d240, 0x4d260, 2040 0x4d268, 0x4d268, 2041 0x4d280, 0x4d284, 2042 0x4d2a0, 0x4d2b0, 2043 0x4e0c0, 0x4e0e4, 2044 0x4f000, 0x4f03c, 2045 0x4f044, 0x4f08c, 2046 0x4f200, 0x4f250, 2047 0x4f400, 0x4f408, 2048 0x4f414, 0x4f420, 2049 0x4f600, 0x4f618, 2050 0x4f800, 0x4f814, 2051 0x50000, 0x50084, 2052 0x50090, 0x500cc, 2053 0x50400, 0x50400, 2054 0x50800, 0x50884, 2055 0x50890, 0x508cc, 2056 0x50c00, 0x50c00, 2057 0x51000, 0x5101c, 2058 0x51300, 0x51308, 2059 }; 2060 2061 static const unsigned int t5vf_reg_ranges[] = { 2062 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2063 VF_MPS_REG(A_MPS_VF_CTL), 2064 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2065 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2066 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2067 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2068 FW_T4VF_MBDATA_BASE_ADDR, 2069 FW_T4VF_MBDATA_BASE_ADDR + 2070 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2071 }; 2072 2073 static const unsigned int t6_reg_ranges[] = { 2074 0x1008, 0x101c, 2075 0x1024, 0x10a8, 2076 0x10b4, 0x10f8, 2077 0x1100, 0x1114, 2078 0x111c, 0x112c, 2079 0x1138, 0x113c, 2080 0x1144, 0x114c, 2081 0x1180, 0x1184, 2082 0x1190, 0x1194, 2083 0x11a0, 0x11a4, 2084 0x11b0, 0x11c4, 2085 0x11fc, 0x1274, 2086 0x1280, 0x133c, 2087 0x1800, 0x18fc, 2088 0x3000, 0x302c, 2089 0x3060, 0x30b0, 2090 0x30b8, 0x30d8, 2091 0x30e0, 0x30fc, 2092 0x3140, 0x357c, 2093 0x35a8, 0x35cc, 2094 0x35ec, 0x35ec, 2095 0x3600, 0x5624, 2096 0x56cc, 0x56ec, 2097 0x56f4, 0x5720, 2098 0x5728, 0x575c, 2099 0x580c, 0x5814, 2100 0x5890, 0x589c, 2101 0x58a4, 0x58ac, 2102 0x58b8, 0x58bc, 2103 0x5940, 0x595c, 2104 0x5980, 0x598c, 2105 0x59b0, 0x59c8, 2106 0x59d0, 0x59dc, 2107 0x59fc, 0x5a18, 2108 0x5a60, 0x5a6c, 2109 0x5a80, 0x5a8c, 2110 0x5a94, 0x5a9c, 2111 0x5b94, 0x5bfc, 2112 0x5c10, 0x5e48, 2113 0x5e50, 0x5e94, 2114 0x5ea0, 0x5eb0, 2115 0x5ec0, 0x5ec0, 2116 0x5ec8, 0x5ed0, 2117 0x5ee0, 0x5ee0, 2118 0x5ef0, 0x5ef0, 2119 0x5f00, 0x5f00, 2120 0x6000, 0x6020, 2121 0x6028, 0x6040, 2122 0x6058, 0x609c, 2123 0x60a8, 0x619c, 2124 0x7700, 0x7798, 2125 0x77c0, 0x7880, 2126 0x78cc, 0x78fc, 2127 0x7b00, 0x7b58, 2128 0x7b60, 0x7b84, 2129 0x7b8c, 0x7c54, 2130 0x7d00, 0x7d38, 2131 0x7d40, 0x7d84, 2132 0x7d8c, 0x7ddc, 2133 0x7de4, 0x7e04, 2134 0x7e10, 0x7e1c, 2135 0x7e24, 0x7e38, 2136 0x7e40, 0x7e44, 2137 0x7e4c, 0x7e78, 2138 0x7e80, 0x7edc, 2139 0x7ee8, 0x7efc, 2140 0x8dc0, 0x8de0, 2141 0x8df8, 0x8e04, 2142 0x8e10, 0x8e84, 2143 0x8ea0, 0x8f88, 2144 0x8fb8, 0x9058, 2145 0x9060, 0x9060, 2146 0x9068, 0x90f8, 2147 0x9100, 0x9124, 2148 0x9400, 0x9470, 2149 0x9600, 0x9600, 2150 0x9608, 0x9638, 2151 0x9640, 0x9704, 2152 0x9710, 0x971c, 2153 0x9800, 0x9808, 2154 0x9810, 0x9864, 2155 0x9c00, 0x9c6c, 2156 0x9c80, 0x9cec, 2157 0x9d00, 0x9d6c, 2158 0x9d80, 0x9dec, 2159 0x9e00, 0x9e6c, 2160 0x9e80, 0x9eec, 2161 0x9f00, 0x9f6c, 2162 0x9f80, 0xa020, 2163 0xd000, 0xd03c, 2164 0xd100, 0xd118, 2165 0xd200, 0xd214, 2166 0xd220, 0xd234, 2167 0xd240, 0xd254, 2168 0xd260, 0xd274, 2169 0xd280, 0xd294, 2170 0xd2a0, 0xd2b4, 2171 0xd2c0, 0xd2d4, 2172 0xd2e0, 0xd2f4, 2173 0xd300, 0xd31c, 2174 0xdfc0, 0xdfe0, 2175 0xe000, 0xf008, 2176 0xf010, 0xf018, 2177 0xf020, 0xf028, 2178 0x11000, 0x11014, 2179 0x11048, 0x1106c, 2180 0x11074, 0x11088, 2181 0x11098, 0x11120, 2182 0x1112c, 0x1117c, 2183 0x11190, 0x112e0, 2184 0x11300, 0x1130c, 2185 0x12000, 0x1206c, 2186 0x19040, 0x1906c, 2187 0x19078, 0x19080, 2188 0x1908c, 0x190e8, 2189 0x190f0, 0x190f8, 2190 0x19100, 0x19110, 2191 0x19120, 0x19124, 2192 0x19150, 0x19194, 2193 0x1919c, 0x191b0, 2194 0x191d0, 0x191e8, 2195 0x19238, 0x19290, 2196 0x192a4, 0x192b0, 2197 0x19348, 0x1934c, 2198 0x193f8, 0x19418, 2199 0x19420, 0x19428, 2200 0x19430, 0x19444, 2201 0x1944c, 0x1946c, 2202 0x19474, 0x19474, 2203 0x19490, 0x194cc, 2204 0x194f0, 0x194f8, 2205 0x19c00, 0x19c48, 2206 0x19c50, 0x19c80, 2207 0x19c94, 0x19c98, 2208 0x19ca0, 0x19cbc, 2209 0x19ce4, 0x19ce4, 2210 0x19cf0, 0x19cf8, 2211 0x19d00, 0x19d28, 2212 0x19d50, 0x19d78, 2213 0x19d94, 0x19d98, 2214 0x19da0, 0x19de0, 2215 0x19df0, 0x19e10, 2216 0x19e50, 0x19e6c, 2217 0x19ea0, 0x19ebc, 2218 0x19ec4, 0x19ef4, 2219 0x19f04, 0x19f2c, 2220 0x19f34, 0x19f34, 2221 0x19f40, 0x19f50, 2222 0x19f90, 0x19fac, 2223 0x19fc4, 0x19fc8, 2224 0x19fd0, 0x19fe4, 2225 0x1a000, 0x1a004, 2226 0x1a010, 0x1a06c, 2227 0x1a0b0, 0x1a0e4, 2228 0x1a0ec, 0x1a0f8, 2229 0x1a100, 0x1a108, 2230 0x1a114, 0x1a130, 2231 0x1a138, 0x1a1c4, 2232 0x1a1fc, 0x1a1fc, 2233 0x1e008, 0x1e00c, 2234 0x1e040, 0x1e044, 2235 0x1e04c, 0x1e04c, 2236 0x1e284, 0x1e290, 2237 0x1e2c0, 0x1e2c0, 2238 0x1e2e0, 0x1e2e0, 2239 0x1e300, 0x1e384, 2240 0x1e3c0, 0x1e3c8, 2241 0x1e408, 0x1e40c, 2242 0x1e440, 0x1e444, 2243 0x1e44c, 0x1e44c, 2244 0x1e684, 0x1e690, 2245 0x1e6c0, 0x1e6c0, 2246 0x1e6e0, 0x1e6e0, 2247 0x1e700, 0x1e784, 2248 0x1e7c0, 0x1e7c8, 2249 0x1e808, 0x1e80c, 2250 0x1e840, 0x1e844, 2251 0x1e84c, 0x1e84c, 2252 0x1ea84, 0x1ea90, 2253 0x1eac0, 0x1eac0, 2254 0x1eae0, 0x1eae0, 2255 0x1eb00, 0x1eb84, 2256 0x1ebc0, 0x1ebc8, 2257 0x1ec08, 0x1ec0c, 2258 0x1ec40, 0x1ec44, 2259 0x1ec4c, 0x1ec4c, 2260 0x1ee84, 0x1ee90, 2261 0x1eec0, 0x1eec0, 2262 0x1eee0, 0x1eee0, 2263 0x1ef00, 0x1ef84, 2264 0x1efc0, 0x1efc8, 2265 0x1f008, 0x1f00c, 2266 0x1f040, 0x1f044, 2267 0x1f04c, 0x1f04c, 2268 0x1f284, 0x1f290, 2269 0x1f2c0, 0x1f2c0, 2270 0x1f2e0, 0x1f2e0, 2271 0x1f300, 0x1f384, 2272 0x1f3c0, 0x1f3c8, 2273 0x1f408, 0x1f40c, 2274 0x1f440, 0x1f444, 2275 0x1f44c, 0x1f44c, 2276 0x1f684, 0x1f690, 2277 0x1f6c0, 0x1f6c0, 2278 0x1f6e0, 0x1f6e0, 2279 0x1f700, 0x1f784, 2280 0x1f7c0, 0x1f7c8, 2281 0x1f808, 0x1f80c, 2282 0x1f840, 0x1f844, 2283 0x1f84c, 0x1f84c, 2284 0x1fa84, 0x1fa90, 2285 0x1fac0, 0x1fac0, 2286 0x1fae0, 0x1fae0, 2287 0x1fb00, 0x1fb84, 2288 0x1fbc0, 0x1fbc8, 2289 0x1fc08, 0x1fc0c, 2290 0x1fc40, 0x1fc44, 2291 0x1fc4c, 0x1fc4c, 2292 0x1fe84, 0x1fe90, 2293 0x1fec0, 0x1fec0, 2294 0x1fee0, 0x1fee0, 2295 0x1ff00, 0x1ff84, 2296 0x1ffc0, 0x1ffc8, 2297 0x30000, 0x30030, 2298 0x30100, 0x30168, 2299 0x30190, 0x301a0, 2300 0x301a8, 0x301b8, 2301 0x301c4, 0x301c8, 2302 0x301d0, 0x301d0, 2303 0x30200, 0x30320, 2304 0x30400, 0x304b4, 2305 0x304c0, 0x3052c, 2306 0x30540, 0x3061c, 2307 0x30800, 0x308a0, 2308 0x308c0, 0x30908, 2309 0x30910, 0x309b8, 2310 0x30a00, 0x30a04, 2311 0x30a0c, 0x30a14, 2312 0x30a1c, 0x30a2c, 2313 0x30a44, 0x30a50, 2314 0x30a74, 0x30a74, 2315 0x30a7c, 0x30afc, 2316 0x30b08, 0x30c24, 2317 0x30d00, 0x30d14, 2318 0x30d1c, 0x30d3c, 2319 0x30d44, 0x30d4c, 2320 0x30d54, 0x30d74, 2321 0x30d7c, 0x30d7c, 2322 0x30de0, 0x30de0, 2323 0x30e00, 0x30ed4, 2324 0x30f00, 0x30fa4, 2325 0x30fc0, 0x30fc4, 2326 0x31000, 0x31004, 2327 0x31080, 0x310fc, 2328 0x31208, 0x31220, 2329 0x3123c, 0x31254, 2330 0x31300, 0x31300, 2331 0x31308, 0x3131c, 2332 0x31338, 0x3133c, 2333 0x31380, 0x31380, 2334 0x31388, 0x313a8, 2335 0x313b4, 0x313b4, 2336 0x31400, 0x31420, 2337 0x31438, 0x3143c, 2338 0x31480, 0x31480, 2339 0x314a8, 0x314a8, 2340 0x314b0, 0x314b4, 2341 0x314c8, 0x314d4, 2342 0x31a40, 0x31a4c, 2343 0x31af0, 0x31b20, 2344 0x31b38, 0x31b3c, 2345 0x31b80, 0x31b80, 2346 0x31ba8, 0x31ba8, 2347 0x31bb0, 0x31bb4, 2348 0x31bc8, 0x31bd4, 2349 0x32140, 0x3218c, 2350 0x321f0, 0x321f4, 2351 0x32200, 0x32200, 2352 0x32218, 0x32218, 2353 0x32400, 0x32400, 2354 0x32408, 0x3241c, 2355 0x32618, 0x32620, 2356 0x32664, 0x32664, 2357 0x326a8, 0x326a8, 2358 0x326ec, 0x326ec, 2359 0x32a00, 0x32abc, 2360 0x32b00, 0x32b18, 2361 0x32b20, 0x32b38, 2362 0x32b40, 0x32b58, 2363 0x32b60, 0x32b78, 2364 0x32c00, 0x32c00, 2365 0x32c08, 0x32c3c, 2366 0x33000, 0x3302c, 2367 0x33034, 0x33050, 2368 0x33058, 0x33058, 2369 0x33060, 0x3308c, 2370 0x3309c, 0x330ac, 2371 0x330c0, 0x330c0, 2372 0x330c8, 0x330d0, 2373 0x330d8, 0x330e0, 2374 0x330ec, 0x3312c, 2375 0x33134, 0x33150, 2376 0x33158, 0x33158, 2377 0x33160, 0x3318c, 2378 0x3319c, 0x331ac, 2379 0x331c0, 0x331c0, 2380 0x331c8, 0x331d0, 2381 0x331d8, 0x331e0, 2382 0x331ec, 0x33290, 2383 0x33298, 0x332c4, 2384 0x332e4, 0x33390, 2385 0x33398, 0x333c4, 2386 0x333e4, 0x3342c, 2387 0x33434, 0x33450, 2388 0x33458, 0x33458, 2389 0x33460, 0x3348c, 2390 0x3349c, 0x334ac, 2391 0x334c0, 0x334c0, 2392 0x334c8, 0x334d0, 2393 0x334d8, 0x334e0, 2394 0x334ec, 0x3352c, 2395 0x33534, 0x33550, 2396 0x33558, 0x33558, 2397 0x33560, 0x3358c, 2398 0x3359c, 0x335ac, 2399 0x335c0, 0x335c0, 2400 0x335c8, 0x335d0, 2401 0x335d8, 0x335e0, 2402 0x335ec, 0x33690, 2403 0x33698, 0x336c4, 2404 0x336e4, 0x33790, 2405 0x33798, 0x337c4, 2406 0x337e4, 0x337fc, 2407 0x33814, 0x33814, 2408 0x33854, 0x33868, 2409 0x33880, 0x3388c, 2410 0x338c0, 0x338d0, 2411 0x338e8, 0x338ec, 2412 0x33900, 0x3392c, 2413 0x33934, 0x33950, 2414 0x33958, 0x33958, 2415 0x33960, 0x3398c, 2416 0x3399c, 0x339ac, 2417 0x339c0, 0x339c0, 2418 0x339c8, 0x339d0, 2419 0x339d8, 0x339e0, 2420 0x339ec, 0x33a90, 2421 0x33a98, 0x33ac4, 2422 0x33ae4, 0x33b10, 2423 0x33b24, 0x33b28, 2424 0x33b38, 0x33b50, 2425 0x33bf0, 0x33c10, 2426 0x33c24, 0x33c28, 2427 0x33c38, 0x33c50, 2428 0x33cf0, 0x33cfc, 2429 0x34000, 0x34030, 2430 0x34100, 0x34168, 2431 0x34190, 0x341a0, 2432 0x341a8, 0x341b8, 2433 0x341c4, 0x341c8, 2434 0x341d0, 0x341d0, 2435 0x34200, 0x34320, 2436 0x34400, 0x344b4, 2437 0x344c0, 0x3452c, 2438 0x34540, 0x3461c, 2439 0x34800, 0x348a0, 2440 0x348c0, 0x34908, 2441 0x34910, 0x349b8, 2442 0x34a00, 0x34a04, 2443 0x34a0c, 0x34a14, 2444 0x34a1c, 0x34a2c, 2445 0x34a44, 0x34a50, 2446 0x34a74, 0x34a74, 2447 0x34a7c, 0x34afc, 2448 0x34b08, 0x34c24, 2449 0x34d00, 0x34d14, 2450 0x34d1c, 0x34d3c, 2451 0x34d44, 0x34d4c, 2452 0x34d54, 0x34d74, 2453 0x34d7c, 0x34d7c, 2454 0x34de0, 0x34de0, 2455 0x34e00, 0x34ed4, 2456 0x34f00, 0x34fa4, 2457 0x34fc0, 0x34fc4, 2458 0x35000, 0x35004, 2459 0x35080, 0x350fc, 2460 0x35208, 0x35220, 2461 0x3523c, 0x35254, 2462 0x35300, 0x35300, 2463 0x35308, 0x3531c, 2464 0x35338, 0x3533c, 2465 0x35380, 0x35380, 2466 0x35388, 0x353a8, 2467 0x353b4, 0x353b4, 2468 0x35400, 0x35420, 2469 0x35438, 0x3543c, 2470 0x35480, 0x35480, 2471 0x354a8, 0x354a8, 2472 0x354b0, 0x354b4, 2473 0x354c8, 0x354d4, 2474 0x35a40, 0x35a4c, 2475 0x35af0, 0x35b20, 2476 0x35b38, 0x35b3c, 2477 0x35b80, 0x35b80, 2478 0x35ba8, 0x35ba8, 2479 0x35bb0, 0x35bb4, 2480 0x35bc8, 0x35bd4, 2481 0x36140, 0x3618c, 2482 0x361f0, 0x361f4, 2483 0x36200, 0x36200, 2484 0x36218, 0x36218, 2485 0x36400, 0x36400, 2486 0x36408, 0x3641c, 2487 0x36618, 0x36620, 2488 0x36664, 0x36664, 2489 0x366a8, 0x366a8, 2490 0x366ec, 0x366ec, 2491 0x36a00, 0x36abc, 2492 0x36b00, 0x36b18, 2493 0x36b20, 0x36b38, 2494 0x36b40, 0x36b58, 2495 0x36b60, 0x36b78, 2496 0x36c00, 0x36c00, 2497 0x36c08, 0x36c3c, 2498 0x37000, 0x3702c, 2499 0x37034, 0x37050, 2500 0x37058, 0x37058, 2501 0x37060, 0x3708c, 2502 0x3709c, 0x370ac, 2503 0x370c0, 0x370c0, 2504 0x370c8, 0x370d0, 2505 0x370d8, 0x370e0, 2506 0x370ec, 0x3712c, 2507 0x37134, 0x37150, 2508 0x37158, 0x37158, 2509 0x37160, 0x3718c, 2510 0x3719c, 0x371ac, 2511 0x371c0, 0x371c0, 2512 0x371c8, 0x371d0, 2513 0x371d8, 0x371e0, 2514 0x371ec, 0x37290, 2515 0x37298, 0x372c4, 2516 0x372e4, 0x37390, 2517 0x37398, 0x373c4, 2518 0x373e4, 0x3742c, 2519 0x37434, 0x37450, 2520 0x37458, 0x37458, 2521 0x37460, 0x3748c, 2522 0x3749c, 0x374ac, 2523 0x374c0, 0x374c0, 2524 0x374c8, 0x374d0, 2525 0x374d8, 0x374e0, 2526 0x374ec, 0x3752c, 2527 0x37534, 0x37550, 2528 0x37558, 0x37558, 2529 0x37560, 0x3758c, 2530 0x3759c, 0x375ac, 2531 0x375c0, 0x375c0, 2532 0x375c8, 0x375d0, 2533 0x375d8, 0x375e0, 2534 0x375ec, 0x37690, 2535 0x37698, 0x376c4, 2536 0x376e4, 0x37790, 2537 0x37798, 0x377c4, 2538 0x377e4, 0x377fc, 2539 0x37814, 0x37814, 2540 0x37854, 0x37868, 2541 0x37880, 0x3788c, 2542 0x378c0, 0x378d0, 2543 0x378e8, 0x378ec, 2544 0x37900, 0x3792c, 2545 0x37934, 0x37950, 2546 0x37958, 0x37958, 2547 0x37960, 0x3798c, 2548 0x3799c, 0x379ac, 2549 0x379c0, 0x379c0, 2550 0x379c8, 0x379d0, 2551 0x379d8, 0x379e0, 2552 0x379ec, 0x37a90, 2553 0x37a98, 0x37ac4, 2554 0x37ae4, 0x37b10, 2555 0x37b24, 0x37b28, 2556 0x37b38, 0x37b50, 2557 0x37bf0, 0x37c10, 2558 0x37c24, 0x37c28, 2559 0x37c38, 0x37c50, 2560 0x37cf0, 0x37cfc, 2561 0x40040, 0x40040, 2562 0x40080, 0x40084, 2563 0x40100, 0x40100, 2564 0x40140, 0x401bc, 2565 0x40200, 0x40214, 2566 0x40228, 0x40228, 2567 0x40240, 0x40258, 2568 0x40280, 0x40280, 2569 0x40304, 0x40304, 2570 0x40330, 0x4033c, 2571 0x41304, 0x413c8, 2572 0x413d0, 0x413dc, 2573 0x413f0, 0x413f0, 2574 0x41400, 0x4140c, 2575 0x41414, 0x4141c, 2576 0x41480, 0x414d0, 2577 0x44000, 0x4407c, 2578 0x440c0, 0x441ac, 2579 0x441b4, 0x4427c, 2580 0x442c0, 0x443ac, 2581 0x443b4, 0x4447c, 2582 0x444c0, 0x445ac, 2583 0x445b4, 0x4467c, 2584 0x446c0, 0x447ac, 2585 0x447b4, 0x4487c, 2586 0x448c0, 0x449ac, 2587 0x449b4, 0x44a7c, 2588 0x44ac0, 0x44bac, 2589 0x44bb4, 0x44c7c, 2590 0x44cc0, 0x44dac, 2591 0x44db4, 0x44e7c, 2592 0x44ec0, 0x44fac, 2593 0x44fb4, 0x4507c, 2594 0x450c0, 0x451ac, 2595 0x451b4, 0x451fc, 2596 0x45800, 0x45804, 2597 0x45810, 0x45830, 2598 0x45840, 0x45860, 2599 0x45868, 0x45868, 2600 0x45880, 0x45884, 2601 0x458a0, 0x458b0, 2602 0x45a00, 0x45a04, 2603 0x45a10, 0x45a30, 2604 0x45a40, 0x45a60, 2605 0x45a68, 0x45a68, 2606 0x45a80, 0x45a84, 2607 0x45aa0, 0x45ab0, 2608 0x460c0, 0x460e4, 2609 0x47000, 0x4703c, 2610 0x47044, 0x4708c, 2611 0x47200, 0x47250, 2612 0x47400, 0x47408, 2613 0x47414, 0x47420, 2614 0x47600, 0x47618, 2615 0x47800, 0x47814, 2616 0x47820, 0x4782c, 2617 0x50000, 0x50084, 2618 0x50090, 0x500cc, 2619 0x50300, 0x50384, 2620 0x50400, 0x50400, 2621 0x50800, 0x50884, 2622 0x50890, 0x508cc, 2623 0x50b00, 0x50b84, 2624 0x50c00, 0x50c00, 2625 0x51000, 0x51020, 2626 0x51028, 0x510b0, 2627 0x51300, 0x51324, 2628 }; 2629 2630 static const unsigned int t6vf_reg_ranges[] = { 2631 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2632 VF_MPS_REG(A_MPS_VF_CTL), 2633 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2634 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2635 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2636 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2637 FW_T6VF_MBDATA_BASE_ADDR, 2638 FW_T6VF_MBDATA_BASE_ADDR + 2639 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2640 }; 2641 2642 u32 *buf_end = (u32 *)(buf + buf_size); 2643 const unsigned int *reg_ranges; 2644 int reg_ranges_size, range; 2645 unsigned int chip_version = chip_id(adap); 2646 2647 /* 2648 * Select the right set of register ranges to dump depending on the 2649 * adapter chip type. 2650 */ 2651 switch (chip_version) { 2652 case CHELSIO_T4: 2653 if (adap->flags & IS_VF) { 2654 reg_ranges = t4vf_reg_ranges; 2655 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2656 } else { 2657 reg_ranges = t4_reg_ranges; 2658 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2659 } 2660 break; 2661 2662 case CHELSIO_T5: 2663 if (adap->flags & IS_VF) { 2664 reg_ranges = t5vf_reg_ranges; 2665 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2666 } else { 2667 reg_ranges = t5_reg_ranges; 2668 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2669 } 2670 break; 2671 2672 case CHELSIO_T6: 2673 if (adap->flags & IS_VF) { 2674 reg_ranges = t6vf_reg_ranges; 2675 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2676 } else { 2677 reg_ranges = t6_reg_ranges; 2678 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2679 } 2680 break; 2681 2682 default: 2683 CH_ERR(adap, 2684 "Unsupported chip version %d\n", chip_version); 2685 return; 2686 } 2687 2688 /* 2689 * Clear the register buffer and insert the appropriate register 2690 * values selected by the above register ranges. 2691 */ 2692 memset(buf, 0, buf_size); 2693 for (range = 0; range < reg_ranges_size; range += 2) { 2694 unsigned int reg = reg_ranges[range]; 2695 unsigned int last_reg = reg_ranges[range + 1]; 2696 u32 *bufp = (u32 *)(buf + reg); 2697 2698 /* 2699 * Iterate across the register range filling in the register 2700 * buffer but don't write past the end of the register buffer. 2701 */ 2702 while (reg <= last_reg && bufp < buf_end) { 2703 *bufp++ = t4_read_reg(adap, reg); 2704 reg += sizeof(u32); 2705 } 2706 } 2707} 2708 2709/* 2710 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID 2711 * header followed by one or more VPD-R sections, each with its own header. 2712 */ 2713struct t4_vpd_hdr { 2714 u8 id_tag; 2715 u8 id_len[2]; 2716 u8 id_data[ID_LEN]; 2717}; 2718 2719struct t4_vpdr_hdr { 2720 u8 vpdr_tag; 2721 u8 vpdr_len[2]; 2722}; 2723 2724/* 2725 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2726 */ 2727#define EEPROM_DELAY 10 /* 10us per poll spin */ 2728#define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2729 2730#define EEPROM_STAT_ADDR 0x7bfc 2731#define VPD_SIZE 0x800 2732#define VPD_BASE 0x400 2733#define VPD_BASE_OLD 0 2734#define VPD_LEN 1024 2735#define VPD_INFO_FLD_HDR_SIZE 3 2736#define CHELSIO_VPD_UNIQUE_ID 0x82 2737 2738/* 2739 * Small utility function to wait till any outstanding VPD Access is complete. 2740 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2741 * VPD Access in flight. This allows us to handle the problem of having a 2742 * previous VPD Access time out and prevent an attempt to inject a new VPD 2743 * Request before any in-flight VPD reguest has completed. 2744 */ 2745static int t4_seeprom_wait(struct adapter *adapter) 2746{ 2747 unsigned int base = adapter->params.pci.vpd_cap_addr; 2748 int max_poll; 2749 2750 /* 2751 * If no VPD Access is in flight, we can just return success right 2752 * away. 2753 */ 2754 if (!adapter->vpd_busy) 2755 return 0; 2756 2757 /* 2758 * Poll the VPD Capability Address/Flag register waiting for it 2759 * to indicate that the operation is complete. 2760 */ 2761 max_poll = EEPROM_MAX_POLL; 2762 do { 2763 u16 val; 2764 2765 udelay(EEPROM_DELAY); 2766 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2767 2768 /* 2769 * If the operation is complete, mark the VPD as no longer 2770 * busy and return success. 2771 */ 2772 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2773 adapter->vpd_busy = 0; 2774 return 0; 2775 } 2776 } while (--max_poll); 2777 2778 /* 2779 * Failure! Note that we leave the VPD Busy status set in order to 2780 * avoid pushing a new VPD Access request into the VPD Capability till 2781 * the current operation eventually succeeds. It's a bug to issue a 2782 * new request when an existing request is in flight and will result 2783 * in corrupt hardware state. 2784 */ 2785 return -ETIMEDOUT; 2786} 2787 2788/** 2789 * t4_seeprom_read - read a serial EEPROM location 2790 * @adapter: adapter to read 2791 * @addr: EEPROM virtual address 2792 * @data: where to store the read data 2793 * 2794 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2795 * VPD capability. Note that this function must be called with a virtual 2796 * address. 2797 */ 2798int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2799{ 2800 unsigned int base = adapter->params.pci.vpd_cap_addr; 2801 int ret; 2802 2803 /* 2804 * VPD Accesses must alway be 4-byte aligned! 2805 */ 2806 if (addr >= EEPROMVSIZE || (addr & 3)) 2807 return -EINVAL; 2808 2809 /* 2810 * Wait for any previous operation which may still be in flight to 2811 * complete. 2812 */ 2813 ret = t4_seeprom_wait(adapter); 2814 if (ret) { 2815 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2816 return ret; 2817 } 2818 2819 /* 2820 * Issue our new VPD Read request, mark the VPD as being busy and wait 2821 * for our request to complete. If it doesn't complete, note the 2822 * error and return it to our caller. Note that we do not reset the 2823 * VPD Busy status! 2824 */ 2825 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2826 adapter->vpd_busy = 1; 2827 adapter->vpd_flag = PCI_VPD_ADDR_F; 2828 ret = t4_seeprom_wait(adapter); 2829 if (ret) { 2830 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2831 return ret; 2832 } 2833 2834 /* 2835 * Grab the returned data, swizzle it into our endianness and 2836 * return success. 2837 */ 2838 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2839 *data = le32_to_cpu(*data); 2840 return 0; 2841} 2842 2843/** 2844 * t4_seeprom_write - write a serial EEPROM location 2845 * @adapter: adapter to write 2846 * @addr: virtual EEPROM address 2847 * @data: value to write 2848 * 2849 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2850 * VPD capability. Note that this function must be called with a virtual 2851 * address. 2852 */ 2853int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2854{ 2855 unsigned int base = adapter->params.pci.vpd_cap_addr; 2856 int ret; 2857 u32 stats_reg; 2858 int max_poll; 2859 2860 /* 2861 * VPD Accesses must alway be 4-byte aligned! 2862 */ 2863 if (addr >= EEPROMVSIZE || (addr & 3)) 2864 return -EINVAL; 2865 2866 /* 2867 * Wait for any previous operation which may still be in flight to 2868 * complete. 2869 */ 2870 ret = t4_seeprom_wait(adapter); 2871 if (ret) { 2872 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2873 return ret; 2874 } 2875 2876 /* 2877 * Issue our new VPD Read request, mark the VPD as being busy and wait 2878 * for our request to complete. If it doesn't complete, note the 2879 * error and return it to our caller. Note that we do not reset the 2880 * VPD Busy status! 2881 */ 2882 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2883 cpu_to_le32(data)); 2884 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2885 (u16)addr | PCI_VPD_ADDR_F); 2886 adapter->vpd_busy = 1; 2887 adapter->vpd_flag = 0; 2888 ret = t4_seeprom_wait(adapter); 2889 if (ret) { 2890 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2891 return ret; 2892 } 2893 2894 /* 2895 * Reset PCI_VPD_DATA register after a transaction and wait for our 2896 * request to complete. If it doesn't complete, return error. 2897 */ 2898 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2899 max_poll = EEPROM_MAX_POLL; 2900 do { 2901 udelay(EEPROM_DELAY); 2902 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2903 } while ((stats_reg & 0x1) && --max_poll); 2904 if (!max_poll) 2905 return -ETIMEDOUT; 2906 2907 /* Return success! */ 2908 return 0; 2909} 2910 2911/** 2912 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2913 * @phys_addr: the physical EEPROM address 2914 * @fn: the PCI function number 2915 * @sz: size of function-specific area 2916 * 2917 * Translate a physical EEPROM address to virtual. The first 1K is 2918 * accessed through virtual addresses starting at 31K, the rest is 2919 * accessed through virtual addresses starting at 0. 2920 * 2921 * The mapping is as follows: 2922 * [0..1K) -> [31K..32K) 2923 * [1K..1K+A) -> [ES-A..ES) 2924 * [1K+A..ES) -> [0..ES-A-1K) 2925 * 2926 * where A = @fn * @sz, and ES = EEPROM size. 2927 */ 2928int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2929{ 2930 fn *= sz; 2931 if (phys_addr < 1024) 2932 return phys_addr + (31 << 10); 2933 if (phys_addr < 1024 + fn) 2934 return EEPROMSIZE - fn + phys_addr - 1024; 2935 if (phys_addr < EEPROMSIZE) 2936 return phys_addr - 1024 - fn; 2937 return -EINVAL; 2938} 2939 2940/** 2941 * t4_seeprom_wp - enable/disable EEPROM write protection 2942 * @adapter: the adapter 2943 * @enable: whether to enable or disable write protection 2944 * 2945 * Enables or disables write protection on the serial EEPROM. 2946 */ 2947int t4_seeprom_wp(struct adapter *adapter, int enable) 2948{ 2949 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2950} 2951 2952/** 2953 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2954 * @vpd: Pointer to buffered vpd data structure 2955 * @kw: The keyword to search for 2956 * @region: VPD region to search (starting from 0) 2957 * 2958 * Returns the value of the information field keyword or 2959 * -ENOENT otherwise. 2960 */ 2961static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region) 2962{ 2963 int i, tag; 2964 unsigned int offset, len; 2965 const struct t4_vpdr_hdr *vpdr; 2966 2967 offset = sizeof(struct t4_vpd_hdr); 2968 vpdr = (const void *)(vpd + offset); 2969 tag = vpdr->vpdr_tag; 2970 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2971 while (region--) { 2972 offset += sizeof(struct t4_vpdr_hdr) + len; 2973 vpdr = (const void *)(vpd + offset); 2974 if (++tag != vpdr->vpdr_tag) 2975 return -ENOENT; 2976 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2977 } 2978 offset += sizeof(struct t4_vpdr_hdr); 2979 2980 if (offset + len > VPD_LEN) { 2981 return -ENOENT; 2982 } 2983 2984 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 2985 if (memcmp(vpd + i , kw , 2) == 0){ 2986 i += VPD_INFO_FLD_HDR_SIZE; 2987 return i; 2988 } 2989 2990 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2]; 2991 } 2992 2993 return -ENOENT; 2994} 2995 2996 2997/** 2998 * get_vpd_params - read VPD parameters from VPD EEPROM 2999 * @adapter: adapter to read 3000 * @p: where to store the parameters 3001 * @vpd: caller provided temporary space to read the VPD into 3002 * 3003 * Reads card parameters stored in VPD EEPROM. 3004 */ 3005static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 3006 uint16_t device_id, u32 *buf) 3007{ 3008 int i, ret, addr; 3009 int ec, sn, pn, na, md; 3010 u8 csum; 3011 const u8 *vpd = (const u8 *)buf; 3012 3013 /* 3014 * Card information normally starts at VPD_BASE but early cards had 3015 * it at 0. 3016 */ 3017 ret = t4_seeprom_read(adapter, VPD_BASE, buf); 3018 if (ret) 3019 return (ret); 3020 3021 /* 3022 * The VPD shall have a unique identifier specified by the PCI SIG. 3023 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 3024 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 3025 * is expected to automatically put this entry at the 3026 * beginning of the VPD. 3027 */ 3028 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 3029 3030 for (i = 0; i < VPD_LEN; i += 4) { 3031 ret = t4_seeprom_read(adapter, addr + i, buf++); 3032 if (ret) 3033 return ret; 3034 } 3035 3036#define FIND_VPD_KW(var,name) do { \ 3037 var = get_vpd_keyword_val(vpd, name, 0); \ 3038 if (var < 0) { \ 3039 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 3040 return -EINVAL; \ 3041 } \ 3042} while (0) 3043 3044 FIND_VPD_KW(i, "RV"); 3045 for (csum = 0; i >= 0; i--) 3046 csum += vpd[i]; 3047 3048 if (csum) { 3049 CH_ERR(adapter, 3050 "corrupted VPD EEPROM, actual csum %u\n", csum); 3051 return -EINVAL; 3052 } 3053 3054 FIND_VPD_KW(ec, "EC"); 3055 FIND_VPD_KW(sn, "SN"); 3056 FIND_VPD_KW(pn, "PN"); 3057 FIND_VPD_KW(na, "NA"); 3058#undef FIND_VPD_KW 3059 3060 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); 3061 strstrip(p->id); 3062 memcpy(p->ec, vpd + ec, EC_LEN); 3063 strstrip(p->ec); 3064 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3065 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3066 strstrip(p->sn); 3067 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3068 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3069 strstrip((char *)p->pn); 3070 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3071 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3072 strstrip((char *)p->na); 3073 3074 if (device_id & 0x80) 3075 return 0; /* Custom card */ 3076 3077 md = get_vpd_keyword_val(vpd, "VF", 1); 3078 if (md < 0) { 3079 snprintf(p->md, sizeof(p->md), "unknown"); 3080 } else { 3081 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; 3082 memcpy(p->md, vpd + md, min(i, MD_LEN)); 3083 strstrip((char *)p->md); 3084 } 3085 3086 return 0; 3087} 3088 3089/* serial flash and firmware constants and flash config file constants */ 3090enum { 3091 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3092 3093 /* flash command opcodes */ 3094 SF_PROG_PAGE = 2, /* program 256B page */ 3095 SF_WR_DISABLE = 4, /* disable writes */ 3096 SF_RD_STATUS = 5, /* read status register */ 3097 SF_WR_ENABLE = 6, /* enable writes */ 3098 SF_RD_DATA_FAST = 0xb, /* read flash */ 3099 SF_RD_ID = 0x9f, /* read ID */ 3100 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3101}; 3102 3103/** 3104 * sf1_read - read data from the serial flash 3105 * @adapter: the adapter 3106 * @byte_cnt: number of bytes to read 3107 * @cont: whether another operation will be chained 3108 * @lock: whether to lock SF for PL access only 3109 * @valp: where to store the read data 3110 * 3111 * Reads up to 4 bytes of data from the serial flash. The location of 3112 * the read needs to be specified prior to calling this by issuing the 3113 * appropriate commands to the serial flash. 3114 */ 3115static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3116 int lock, u32 *valp) 3117{ 3118 int ret; 3119 3120 if (!byte_cnt || byte_cnt > 4) 3121 return -EINVAL; 3122 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3123 return -EBUSY; 3124 t4_write_reg(adapter, A_SF_OP, 3125 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3126 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3127 if (!ret) 3128 *valp = t4_read_reg(adapter, A_SF_DATA); 3129 return ret; 3130} 3131 3132/** 3133 * sf1_write - write data to the serial flash 3134 * @adapter: the adapter 3135 * @byte_cnt: number of bytes to write 3136 * @cont: whether another operation will be chained 3137 * @lock: whether to lock SF for PL access only 3138 * @val: value to write 3139 * 3140 * Writes up to 4 bytes of data to the serial flash. The location of 3141 * the write needs to be specified prior to calling this by issuing the 3142 * appropriate commands to the serial flash. 3143 */ 3144static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3145 int lock, u32 val) 3146{ 3147 if (!byte_cnt || byte_cnt > 4) 3148 return -EINVAL; 3149 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3150 return -EBUSY; 3151 t4_write_reg(adapter, A_SF_DATA, val); 3152 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3153 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3154 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3155} 3156 3157/** 3158 * flash_wait_op - wait for a flash operation to complete 3159 * @adapter: the adapter 3160 * @attempts: max number of polls of the status register 3161 * @delay: delay between polls in ms 3162 * 3163 * Wait for a flash operation to complete by polling the status register. 3164 */ 3165static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3166{ 3167 int ret; 3168 u32 status; 3169 3170 while (1) { 3171 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3172 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3173 return ret; 3174 if (!(status & 1)) 3175 return 0; 3176 if (--attempts == 0) 3177 return -EAGAIN; 3178 if (delay) 3179 msleep(delay); 3180 } 3181} 3182 3183/** 3184 * t4_read_flash - read words from serial flash 3185 * @adapter: the adapter 3186 * @addr: the start address for the read 3187 * @nwords: how many 32-bit words to read 3188 * @data: where to store the read data 3189 * @byte_oriented: whether to store data as bytes or as words 3190 * 3191 * Read the specified number of 32-bit words from the serial flash. 3192 * If @byte_oriented is set the read data is stored as a byte array 3193 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3194 * natural endianness. 3195 */ 3196int t4_read_flash(struct adapter *adapter, unsigned int addr, 3197 unsigned int nwords, u32 *data, int byte_oriented) 3198{ 3199 int ret; 3200 3201 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3202 return -EINVAL; 3203 3204 addr = swab32(addr) | SF_RD_DATA_FAST; 3205 3206 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3207 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3208 return ret; 3209 3210 for ( ; nwords; nwords--, data++) { 3211 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3212 if (nwords == 1) 3213 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3214 if (ret) 3215 return ret; 3216 if (byte_oriented) 3217 *data = (__force __u32)(cpu_to_be32(*data)); 3218 } 3219 return 0; 3220} 3221 3222/** 3223 * t4_write_flash - write up to a page of data to the serial flash 3224 * @adapter: the adapter 3225 * @addr: the start address to write 3226 * @n: length of data to write in bytes 3227 * @data: the data to write 3228 * @byte_oriented: whether to store data as bytes or as words 3229 * 3230 * Writes up to a page of data (256 bytes) to the serial flash starting 3231 * at the given address. All the data must be written to the same page. 3232 * If @byte_oriented is set the write data is stored as byte stream 3233 * (i.e. matches what on disk), otherwise in big-endian. 3234 */ 3235int t4_write_flash(struct adapter *adapter, unsigned int addr, 3236 unsigned int n, const u8 *data, int byte_oriented) 3237{ 3238 int ret; 3239 u32 buf[SF_PAGE_SIZE / 4]; 3240 unsigned int i, c, left, val, offset = addr & 0xff; 3241 3242 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3243 return -EINVAL; 3244 3245 val = swab32(addr) | SF_PROG_PAGE; 3246 3247 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3248 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3249 goto unlock; 3250 3251 for (left = n; left; left -= c) { 3252 c = min(left, 4U); 3253 for (val = 0, i = 0; i < c; ++i) 3254 val = (val << 8) + *data++; 3255 3256 if (!byte_oriented) 3257 val = cpu_to_be32(val); 3258 3259 ret = sf1_write(adapter, c, c != left, 1, val); 3260 if (ret) 3261 goto unlock; 3262 } 3263 ret = flash_wait_op(adapter, 8, 1); 3264 if (ret) 3265 goto unlock; 3266 3267 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3268 3269 /* Read the page to verify the write succeeded */ 3270 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3271 byte_oriented); 3272 if (ret) 3273 return ret; 3274 3275 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3276 CH_ERR(adapter, 3277 "failed to correctly write the flash page at %#x\n", 3278 addr); 3279 return -EIO; 3280 } 3281 return 0; 3282 3283unlock: 3284 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3285 return ret; 3286} 3287 3288/** 3289 * t4_get_fw_version - read the firmware version 3290 * @adapter: the adapter 3291 * @vers: where to place the version 3292 * 3293 * Reads the FW version from flash. 3294 */ 3295int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3296{ 3297 return t4_read_flash(adapter, FLASH_FW_START + 3298 offsetof(struct fw_hdr, fw_ver), 1, 3299 vers, 0); 3300} 3301 3302/** 3303 * t4_get_fw_hdr - read the firmware header 3304 * @adapter: the adapter 3305 * @hdr: where to place the version 3306 * 3307 * Reads the FW header from flash into caller provided buffer. 3308 */ 3309int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr) 3310{ 3311 return t4_read_flash(adapter, FLASH_FW_START, 3312 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1); 3313} 3314 3315/** 3316 * t4_get_bs_version - read the firmware bootstrap version 3317 * @adapter: the adapter 3318 * @vers: where to place the version 3319 * 3320 * Reads the FW Bootstrap version from flash. 3321 */ 3322int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3323{ 3324 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3325 offsetof(struct fw_hdr, fw_ver), 1, 3326 vers, 0); 3327} 3328 3329/** 3330 * t4_get_tp_version - read the TP microcode version 3331 * @adapter: the adapter 3332 * @vers: where to place the version 3333 * 3334 * Reads the TP microcode version from flash. 3335 */ 3336int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3337{ 3338 return t4_read_flash(adapter, FLASH_FW_START + 3339 offsetof(struct fw_hdr, tp_microcode_ver), 3340 1, vers, 0); 3341} 3342 3343/** 3344 * t4_get_exprom_version - return the Expansion ROM version (if any) 3345 * @adapter: the adapter 3346 * @vers: where to place the version 3347 * 3348 * Reads the Expansion ROM header from FLASH and returns the version 3349 * number (if present) through the @vers return value pointer. We return 3350 * this in the Firmware Version Format since it's convenient. Return 3351 * 0 on success, -ENOENT if no Expansion ROM is present. 3352 */ 3353int t4_get_exprom_version(struct adapter *adapter, u32 *vers) 3354{ 3355 struct exprom_header { 3356 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3357 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3358 } *hdr; 3359 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3360 sizeof(u32))]; 3361 int ret; 3362 3363 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START, 3364 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3365 0); 3366 if (ret) 3367 return ret; 3368 3369 hdr = (struct exprom_header *)exprom_header_buf; 3370 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3371 return -ENOENT; 3372 3373 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3374 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3375 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3376 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3377 return 0; 3378} 3379 3380/** 3381 * t4_get_scfg_version - return the Serial Configuration version 3382 * @adapter: the adapter 3383 * @vers: where to place the version 3384 * 3385 * Reads the Serial Configuration Version via the Firmware interface 3386 * (thus this can only be called once we're ready to issue Firmware 3387 * commands). The format of the Serial Configuration version is 3388 * adapter specific. Returns 0 on success, an error on failure. 3389 * 3390 * Note that early versions of the Firmware didn't include the ability 3391 * to retrieve the Serial Configuration version, so we zero-out the 3392 * return-value parameter in that case to avoid leaving it with 3393 * garbage in it. 3394 * 3395 * Also note that the Firmware will return its cached copy of the Serial 3396 * Initialization Revision ID, not the actual Revision ID as written in 3397 * the Serial EEPROM. This is only an issue if a new VPD has been written 3398 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3399 * it's best to defer calling this routine till after a FW_RESET_CMD has 3400 * been issued if the Host Driver will be performing a full adapter 3401 * initialization. 3402 */ 3403int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3404{ 3405 u32 scfgrev_param; 3406 int ret; 3407 3408 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3409 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3410 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3411 1, &scfgrev_param, vers); 3412 if (ret) 3413 *vers = 0; 3414 return ret; 3415} 3416 3417/** 3418 * t4_get_vpd_version - return the VPD version 3419 * @adapter: the adapter 3420 * @vers: where to place the version 3421 * 3422 * Reads the VPD via the Firmware interface (thus this can only be called 3423 * once we're ready to issue Firmware commands). The format of the 3424 * VPD version is adapter specific. Returns 0 on success, an error on 3425 * failure. 3426 * 3427 * Note that early versions of the Firmware didn't include the ability 3428 * to retrieve the VPD version, so we zero-out the return-value parameter 3429 * in that case to avoid leaving it with garbage in it. 3430 * 3431 * Also note that the Firmware will return its cached copy of the VPD 3432 * Revision ID, not the actual Revision ID as written in the Serial 3433 * EEPROM. This is only an issue if a new VPD has been written and the 3434 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3435 * to defer calling this routine till after a FW_RESET_CMD has been issued 3436 * if the Host Driver will be performing a full adapter initialization. 3437 */ 3438int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3439{ 3440 u32 vpdrev_param; 3441 int ret; 3442 3443 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3444 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3445 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3446 1, &vpdrev_param, vers); 3447 if (ret) 3448 *vers = 0; 3449 return ret; 3450} 3451 3452/** 3453 * t4_get_version_info - extract various chip/firmware version information 3454 * @adapter: the adapter 3455 * 3456 * Reads various chip/firmware version numbers and stores them into the 3457 * adapter Adapter Parameters structure. If any of the efforts fails 3458 * the first failure will be returned, but all of the version numbers 3459 * will be read. 3460 */ 3461int t4_get_version_info(struct adapter *adapter) 3462{ 3463 int ret = 0; 3464 3465 #define FIRST_RET(__getvinfo) \ 3466 do { \ 3467 int __ret = __getvinfo; \ 3468 if (__ret && !ret) \ 3469 ret = __ret; \ 3470 } while (0) 3471 3472 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3473 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3474 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3475 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3476 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3477 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3478 3479 #undef FIRST_RET 3480 3481 return ret; 3482} 3483 3484/** 3485 * t4_flash_erase_sectors - erase a range of flash sectors 3486 * @adapter: the adapter 3487 * @start: the first sector to erase 3488 * @end: the last sector to erase 3489 * 3490 * Erases the sectors in the given inclusive range. 3491 */ 3492int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3493{ 3494 int ret = 0; 3495 3496 if (end >= adapter->params.sf_nsec) 3497 return -EINVAL; 3498 3499 while (start <= end) { 3500 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3501 (ret = sf1_write(adapter, 4, 0, 1, 3502 SF_ERASE_SECTOR | (start << 8))) != 0 || 3503 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3504 CH_ERR(adapter, 3505 "erase of flash sector %d failed, error %d\n", 3506 start, ret); 3507 break; 3508 } 3509 start++; 3510 } 3511 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3512 return ret; 3513} 3514 3515/** 3516 * t4_flash_cfg_addr - return the address of the flash configuration file 3517 * @adapter: the adapter 3518 * 3519 * Return the address within the flash where the Firmware Configuration 3520 * File is stored, or an error if the device FLASH is too small to contain 3521 * a Firmware Configuration File. 3522 */ 3523int t4_flash_cfg_addr(struct adapter *adapter) 3524{ 3525 /* 3526 * If the device FLASH isn't large enough to hold a Firmware 3527 * Configuration File, return an error. 3528 */ 3529 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3530 return -ENOSPC; 3531 3532 return FLASH_CFG_START; 3533} 3534 3535/* 3536 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3537 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3538 * and emit an error message for mismatched firmware to save our caller the 3539 * effort ... 3540 */ 3541static int t4_fw_matches_chip(struct adapter *adap, 3542 const struct fw_hdr *hdr) 3543{ 3544 /* 3545 * The expression below will return FALSE for any unsupported adapter 3546 * which will keep us "honest" in the future ... 3547 */ 3548 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3549 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3550 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3551 return 1; 3552 3553 CH_ERR(adap, 3554 "FW image (%d) is not suitable for this adapter (%d)\n", 3555 hdr->chip, chip_id(adap)); 3556 return 0; 3557} 3558 3559/** 3560 * t4_load_fw - download firmware 3561 * @adap: the adapter 3562 * @fw_data: the firmware image to write 3563 * @size: image size 3564 * 3565 * Write the supplied firmware image to the card's serial flash. 3566 */ 3567int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3568{ 3569 u32 csum; 3570 int ret, addr; 3571 unsigned int i; 3572 u8 first_page[SF_PAGE_SIZE]; 3573 const u32 *p = (const u32 *)fw_data; 3574 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3575 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3576 unsigned int fw_start_sec; 3577 unsigned int fw_start; 3578 unsigned int fw_size; 3579 3580 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3581 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3582 fw_start = FLASH_FWBOOTSTRAP_START; 3583 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3584 } else { 3585 fw_start_sec = FLASH_FW_START_SEC; 3586 fw_start = FLASH_FW_START; 3587 fw_size = FLASH_FW_MAX_SIZE; 3588 } 3589 3590 if (!size) { 3591 CH_ERR(adap, "FW image has no data\n"); 3592 return -EINVAL; 3593 } 3594 if (size & 511) { 3595 CH_ERR(adap, 3596 "FW image size not multiple of 512 bytes\n"); 3597 return -EINVAL; 3598 } 3599 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3600 CH_ERR(adap, 3601 "FW image size differs from size in FW header\n"); 3602 return -EINVAL; 3603 } 3604 if (size > fw_size) { 3605 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3606 fw_size); 3607 return -EFBIG; 3608 } 3609 if (!t4_fw_matches_chip(adap, hdr)) 3610 return -EINVAL; 3611 3612 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3613 csum += be32_to_cpu(p[i]); 3614 3615 if (csum != 0xffffffff) { 3616 CH_ERR(adap, 3617 "corrupted firmware image, checksum %#x\n", csum); 3618 return -EINVAL; 3619 } 3620 3621 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3622 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3623 if (ret) 3624 goto out; 3625 3626 /* 3627 * We write the correct version at the end so the driver can see a bad 3628 * version if the FW write fails. Start by writing a copy of the 3629 * first page with a bad version. 3630 */ 3631 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3632 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3633 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3634 if (ret) 3635 goto out; 3636 3637 addr = fw_start; 3638 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3639 addr += SF_PAGE_SIZE; 3640 fw_data += SF_PAGE_SIZE; 3641 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3642 if (ret) 3643 goto out; 3644 } 3645 3646 ret = t4_write_flash(adap, 3647 fw_start + offsetof(struct fw_hdr, fw_ver), 3648 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3649out: 3650 if (ret) 3651 CH_ERR(adap, "firmware download failed, error %d\n", 3652 ret); 3653 return ret; 3654} 3655 3656/** 3657 * t4_fwcache - firmware cache operation 3658 * @adap: the adapter 3659 * @op : the operation (flush or flush and invalidate) 3660 */ 3661int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3662{ 3663 struct fw_params_cmd c; 3664 3665 memset(&c, 0, sizeof(c)); 3666 c.op_to_vfn = 3667 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3668 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3669 V_FW_PARAMS_CMD_PFN(adap->pf) | 3670 V_FW_PARAMS_CMD_VFN(0)); 3671 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3672 c.param[0].mnem = 3673 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3674 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3675 c.param[0].val = (__force __be32)op; 3676 3677 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3678} 3679 3680void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3681 unsigned int *pif_req_wrptr, 3682 unsigned int *pif_rsp_wrptr) 3683{ 3684 int i, j; 3685 u32 cfg, val, req, rsp; 3686 3687 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3688 if (cfg & F_LADBGEN) 3689 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3690 3691 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3692 req = G_POLADBGWRPTR(val); 3693 rsp = G_PILADBGWRPTR(val); 3694 if (pif_req_wrptr) 3695 *pif_req_wrptr = req; 3696 if (pif_rsp_wrptr) 3697 *pif_rsp_wrptr = rsp; 3698 3699 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3700 for (j = 0; j < 6; j++) { 3701 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3702 V_PILADBGRDPTR(rsp)); 3703 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3704 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3705 req++; 3706 rsp++; 3707 } 3708 req = (req + 2) & M_POLADBGRDPTR; 3709 rsp = (rsp + 2) & M_PILADBGRDPTR; 3710 } 3711 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3712} 3713 3714void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3715{ 3716 u32 cfg; 3717 int i, j, idx; 3718 3719 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3720 if (cfg & F_LADBGEN) 3721 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3722 3723 for (i = 0; i < CIM_MALA_SIZE; i++) { 3724 for (j = 0; j < 5; j++) { 3725 idx = 8 * i + j; 3726 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3727 V_PILADBGRDPTR(idx)); 3728 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3729 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3730 } 3731 } 3732 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3733} 3734 3735void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3736{ 3737 unsigned int i, j; 3738 3739 for (i = 0; i < 8; i++) { 3740 u32 *p = la_buf + i; 3741 3742 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3743 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3744 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3745 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3746 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3747 } 3748} 3749 3750/** 3751 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits 3752 * @caps16: a 16-bit Port Capabilities value 3753 * 3754 * Returns the equivalent 32-bit Port Capabilities value. 3755 */ 3756static uint32_t fwcaps16_to_caps32(uint16_t caps16) 3757{ 3758 uint32_t caps32 = 0; 3759 3760 #define CAP16_TO_CAP32(__cap) \ 3761 do { \ 3762 if (caps16 & FW_PORT_CAP_##__cap) \ 3763 caps32 |= FW_PORT_CAP32_##__cap; \ 3764 } while (0) 3765 3766 CAP16_TO_CAP32(SPEED_100M); 3767 CAP16_TO_CAP32(SPEED_1G); 3768 CAP16_TO_CAP32(SPEED_25G); 3769 CAP16_TO_CAP32(SPEED_10G); 3770 CAP16_TO_CAP32(SPEED_40G); 3771 CAP16_TO_CAP32(SPEED_100G); 3772 CAP16_TO_CAP32(FC_RX); 3773 CAP16_TO_CAP32(FC_TX); 3774 CAP16_TO_CAP32(ANEG); 3775 CAP16_TO_CAP32(FORCE_PAUSE); 3776 CAP16_TO_CAP32(MDIAUTO); 3777 CAP16_TO_CAP32(MDISTRAIGHT); 3778 CAP16_TO_CAP32(FEC_RS); 3779 CAP16_TO_CAP32(FEC_BASER_RS); 3780 CAP16_TO_CAP32(802_3_PAUSE); 3781 CAP16_TO_CAP32(802_3_ASM_DIR); 3782 3783 #undef CAP16_TO_CAP32 3784 3785 return caps32; 3786} 3787 3788/** 3789 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits 3790 * @caps32: a 32-bit Port Capabilities value 3791 * 3792 * Returns the equivalent 16-bit Port Capabilities value. Note that 3793 * not all 32-bit Port Capabilities can be represented in the 16-bit 3794 * Port Capabilities and some fields/values may not make it. 3795 */ 3796static uint16_t fwcaps32_to_caps16(uint32_t caps32) 3797{ 3798 uint16_t caps16 = 0; 3799 3800 #define CAP32_TO_CAP16(__cap) \ 3801 do { \ 3802 if (caps32 & FW_PORT_CAP32_##__cap) \ 3803 caps16 |= FW_PORT_CAP_##__cap; \ 3804 } while (0) 3805 3806 CAP32_TO_CAP16(SPEED_100M); 3807 CAP32_TO_CAP16(SPEED_1G); 3808 CAP32_TO_CAP16(SPEED_10G); 3809 CAP32_TO_CAP16(SPEED_25G); 3810 CAP32_TO_CAP16(SPEED_40G); 3811 CAP32_TO_CAP16(SPEED_100G); 3812 CAP32_TO_CAP16(FC_RX); 3813 CAP32_TO_CAP16(FC_TX); 3814 CAP32_TO_CAP16(802_3_PAUSE); 3815 CAP32_TO_CAP16(802_3_ASM_DIR); 3816 CAP32_TO_CAP16(ANEG); 3817 CAP32_TO_CAP16(FORCE_PAUSE); 3818 CAP32_TO_CAP16(MDIAUTO); 3819 CAP32_TO_CAP16(MDISTRAIGHT); 3820 CAP32_TO_CAP16(FEC_RS); 3821 CAP32_TO_CAP16(FEC_BASER_RS); 3822 3823 #undef CAP32_TO_CAP16 3824 3825 return caps16; 3826} 3827 3828static bool 3829is_bt(struct port_info *pi) 3830{ 3831 3832 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 3833 pi->port_type == FW_PORT_TYPE_BT_XFI || 3834 pi->port_type == FW_PORT_TYPE_BT_XAUI); 3835} 3836 3837static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none) 3838{ 3839 int8_t fec = 0; 3840 3841 if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0) 3842 return (unset_means_none ? FEC_NONE : 0); 3843 3844 if (caps & FW_PORT_CAP32_FEC_RS) 3845 fec |= FEC_RS; 3846 if (caps & FW_PORT_CAP32_FEC_BASER_RS) 3847 fec |= FEC_BASER_RS; 3848 if (caps & FW_PORT_CAP32_FEC_NO_FEC) 3849 fec |= FEC_NONE; 3850 3851 return (fec); 3852} 3853 3854/* 3855 * Note that 0 is not translated to NO_FEC. 3856 */ 3857static uint32_t fec_to_fwcap(int8_t fec) 3858{ 3859 uint32_t caps = 0; 3860 3861 /* Only real FECs allowed. */ 3862 MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0); 3863 3864 if (fec & FEC_RS) 3865 caps |= FW_PORT_CAP32_FEC_RS; 3866 if (fec & FEC_BASER_RS) 3867 caps |= FW_PORT_CAP32_FEC_BASER_RS; 3868 if (fec & FEC_NONE) 3869 caps |= FW_PORT_CAP32_FEC_NO_FEC; 3870 3871 return (caps); 3872} 3873 3874/** 3875 * t4_link_l1cfg - apply link configuration to MAC/PHY 3876 * @phy: the PHY to setup 3877 * @mac: the MAC to setup 3878 * @lc: the requested link configuration 3879 * 3880 * Set up a port's MAC and PHY according to a desired link configuration. 3881 * - If the PHY can auto-negotiate first decide what to advertise, then 3882 * enable/disable auto-negotiation as desired, and reset. 3883 * - If the PHY does not auto-negotiate just reset it. 3884 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3885 * otherwise do it later based on the outcome of auto-negotiation. 3886 */ 3887int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3888 struct link_config *lc) 3889{ 3890 struct fw_port_cmd c; 3891 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO); 3892 unsigned int aneg, fc, fec, speed, rcap; 3893 3894 fc = 0; 3895 if (lc->requested_fc & PAUSE_RX) 3896 fc |= FW_PORT_CAP32_FC_RX; 3897 if (lc->requested_fc & PAUSE_TX) 3898 fc |= FW_PORT_CAP32_FC_TX; 3899 if (!(lc->requested_fc & PAUSE_AUTONEG)) 3900 fc |= FW_PORT_CAP32_FORCE_PAUSE; 3901 3902 if (lc->requested_aneg == AUTONEG_DISABLE) 3903 aneg = 0; 3904 else if (lc->requested_aneg == AUTONEG_ENABLE) 3905 aneg = FW_PORT_CAP32_ANEG; 3906 else 3907 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3908 3909 if (aneg) { 3910 speed = lc->pcaps & 3911 V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED); 3912 } else if (lc->requested_speed != 0) 3913 speed = speed_to_fwcap(lc->requested_speed); 3914 else 3915 speed = fwcap_top_speed(lc->pcaps); 3916 3917 fec = 0; 3918 if (fec_supported(speed)) { 3919 if (lc->requested_fec == FEC_AUTO) { 3920 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) { 3921 if (speed & FW_PORT_CAP32_SPEED_100G) { 3922 fec |= FW_PORT_CAP32_FEC_RS; 3923 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3924 } else { 3925 fec |= FW_PORT_CAP32_FEC_RS; 3926 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3927 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3928 } 3929 } else { 3930 /* Set only 1b with old firmwares. */ 3931 fec |= fec_to_fwcap(lc->fec_hint); 3932 } 3933 } else { 3934 fec |= fec_to_fwcap(lc->requested_fec & 3935 M_FW_PORT_CAP32_FEC); 3936 if (lc->requested_fec & FEC_MODULE) 3937 fec |= fec_to_fwcap(lc->fec_hint); 3938 } 3939 3940 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) 3941 fec |= FW_PORT_CAP32_FORCE_FEC; 3942 else if (fec == FW_PORT_CAP32_FEC_NO_FEC) 3943 fec = 0; 3944 } 3945 3946 /* Force AN on for BT cards. */ 3947 if (is_bt(adap->port[adap->chan_map[port]])) 3948 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3949 3950 rcap = aneg | speed | fc | fec; 3951 if ((rcap | lc->pcaps) != lc->pcaps) { 3952#ifdef INVARIANTS 3953 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap, 3954 lc->pcaps, rcap & (rcap ^ lc->pcaps)); 3955#endif 3956 rcap &= lc->pcaps; 3957 } 3958 rcap |= mdi; 3959 3960 memset(&c, 0, sizeof(c)); 3961 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3962 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3963 V_FW_PORT_CMD_PORTID(port)); 3964 if (adap->params.port_caps32) { 3965 c.action_to_len16 = 3966 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) | 3967 FW_LEN16(c)); 3968 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap); 3969 } else { 3970 c.action_to_len16 = 3971 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3972 FW_LEN16(c)); 3973 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap)); 3974 } 3975 3976 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 3977} 3978 3979/** 3980 * t4_restart_aneg - restart autonegotiation 3981 * @adap: the adapter 3982 * @mbox: mbox to use for the FW command 3983 * @port: the port id 3984 * 3985 * Restarts autonegotiation for the selected port. 3986 */ 3987int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 3988{ 3989 struct fw_port_cmd c; 3990 3991 memset(&c, 0, sizeof(c)); 3992 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3993 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3994 V_FW_PORT_CMD_PORTID(port)); 3995 c.action_to_len16 = 3996 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3997 FW_LEN16(c)); 3998 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 3999 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4000} 4001 4002struct intr_details { 4003 u32 mask; 4004 const char *msg; 4005}; 4006 4007struct intr_action { 4008 u32 mask; 4009 int arg; 4010 bool (*action)(struct adapter *, int, bool); 4011}; 4012 4013#define NONFATAL_IF_DISABLED 1 4014struct intr_info { 4015 const char *name; /* name of the INT_CAUSE register */ 4016 int cause_reg; /* INT_CAUSE register */ 4017 int enable_reg; /* INT_ENABLE register */ 4018 u32 fatal; /* bits that are fatal */ 4019 int flags; /* hints */ 4020 const struct intr_details *details; 4021 const struct intr_action *actions; 4022}; 4023 4024static inline char 4025intr_alert_char(u32 cause, u32 enable, u32 fatal) 4026{ 4027 4028 if (cause & fatal) 4029 return ('!'); 4030 if (cause & enable) 4031 return ('*'); 4032 return ('-'); 4033} 4034 4035static void 4036t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause) 4037{ 4038 u32 enable, fatal, leftover; 4039 const struct intr_details *details; 4040 char alert; 4041 4042 enable = t4_read_reg(adap, ii->enable_reg); 4043 if (ii->flags & NONFATAL_IF_DISABLED) 4044 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg); 4045 else 4046 fatal = ii->fatal; 4047 alert = intr_alert_char(cause, enable, fatal); 4048 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n", 4049 alert, ii->name, ii->cause_reg, cause, enable, fatal); 4050 4051 leftover = cause; 4052 for (details = ii->details; details && details->mask != 0; details++) { 4053 u32 msgbits = details->mask & cause; 4054 if (msgbits == 0) 4055 continue; 4056 alert = intr_alert_char(msgbits, enable, ii->fatal); 4057 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits, 4058 details->msg); 4059 leftover &= ~msgbits; 4060 } 4061 if (leftover != 0 && leftover != cause) 4062 CH_ALERT(adap, " ? [0x%08x]\n", leftover); 4063} 4064 4065/* 4066 * Returns true for fatal error. 4067 */ 4068static bool 4069t4_handle_intr(struct adapter *adap, const struct intr_info *ii, 4070 u32 additional_cause, bool verbose) 4071{ 4072 u32 cause, fatal; 4073 bool rc; 4074 const struct intr_action *action; 4075 4076 /* 4077 * Read and display cause. Note that the top level PL_INT_CAUSE is a 4078 * bit special and we need to completely ignore the bits that are not in 4079 * PL_INT_ENABLE. 4080 */ 4081 cause = t4_read_reg(adap, ii->cause_reg); 4082 if (ii->cause_reg == A_PL_INT_CAUSE) 4083 cause &= t4_read_reg(adap, ii->enable_reg); 4084 if (verbose || cause != 0) 4085 t4_show_intr_info(adap, ii, cause); 4086 fatal = cause & ii->fatal; 4087 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED) 4088 fatal &= t4_read_reg(adap, ii->enable_reg); 4089 cause |= additional_cause; 4090 if (cause == 0) 4091 return (false); 4092 4093 rc = fatal != 0; 4094 for (action = ii->actions; action && action->mask != 0; action++) { 4095 if (!(action->mask & cause)) 4096 continue; 4097 rc |= (action->action)(adap, action->arg, verbose); 4098 } 4099 4100 /* clear */ 4101 t4_write_reg(adap, ii->cause_reg, cause); 4102 (void)t4_read_reg(adap, ii->cause_reg); 4103 4104 return (rc); 4105} 4106 4107/* 4108 * Interrupt handler for the PCIE module. 4109 */ 4110static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose) 4111{ 4112 static const struct intr_details sysbus_intr_details[] = { 4113 { F_RNPP, "RXNP array parity error" }, 4114 { F_RPCP, "RXPC array parity error" }, 4115 { F_RCIP, "RXCIF array parity error" }, 4116 { F_RCCP, "Rx completions control array parity error" }, 4117 { F_RFTP, "RXFT array parity error" }, 4118 { 0 } 4119 }; 4120 static const struct intr_info sysbus_intr_info = { 4121 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS", 4122 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4123 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE, 4124 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP, 4125 .flags = 0, 4126 .details = sysbus_intr_details, 4127 .actions = NULL, 4128 }; 4129 static const struct intr_details pcie_port_intr_details[] = { 4130 { F_TPCP, "TXPC array parity error" }, 4131 { F_TNPP, "TXNP array parity error" }, 4132 { F_TFTP, "TXFT array parity error" }, 4133 { F_TCAP, "TXCA array parity error" }, 4134 { F_TCIP, "TXCIF array parity error" }, 4135 { F_RCAP, "RXCA array parity error" }, 4136 { F_OTDD, "outbound request TLP discarded" }, 4137 { F_RDPE, "Rx data parity error" }, 4138 { F_TDUE, "Tx uncorrectable data error" }, 4139 { 0 } 4140 }; 4141 static const struct intr_info pcie_port_intr_info = { 4142 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS", 4143 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4144 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE, 4145 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP | 4146 F_OTDD | F_RDPE | F_TDUE, 4147 .flags = 0, 4148 .details = pcie_port_intr_details, 4149 .actions = NULL, 4150 }; 4151 static const struct intr_details pcie_intr_details[] = { 4152 { F_MSIADDRLPERR, "MSI AddrL parity error" }, 4153 { F_MSIADDRHPERR, "MSI AddrH parity error" }, 4154 { F_MSIDATAPERR, "MSI data parity error" }, 4155 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" }, 4156 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" }, 4157 { F_MSIXDATAPERR, "MSI-X data parity error" }, 4158 { F_MSIXDIPERR, "MSI-X DI parity error" }, 4159 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" }, 4160 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" }, 4161 { F_TARTAGPERR, "PCIe target tag FIFO parity error" }, 4162 { F_CCNTPERR, "PCIe CMD channel count parity error" }, 4163 { F_CREQPERR, "PCIe CMD channel request parity error" }, 4164 { F_CRSPPERR, "PCIe CMD channel response parity error" }, 4165 { F_DCNTPERR, "PCIe DMA channel count parity error" }, 4166 { F_DREQPERR, "PCIe DMA channel request parity error" }, 4167 { F_DRSPPERR, "PCIe DMA channel response parity error" }, 4168 { F_HCNTPERR, "PCIe HMA channel count parity error" }, 4169 { F_HREQPERR, "PCIe HMA channel request parity error" }, 4170 { F_HRSPPERR, "PCIe HMA channel response parity error" }, 4171 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" }, 4172 { F_FIDPERR, "PCIe FID parity error" }, 4173 { F_INTXCLRPERR, "PCIe INTx clear parity error" }, 4174 { F_MATAGPERR, "PCIe MA tag parity error" }, 4175 { F_PIOTAGPERR, "PCIe PIO tag parity error" }, 4176 { F_RXCPLPERR, "PCIe Rx completion parity error" }, 4177 { F_RXWRPERR, "PCIe Rx write parity error" }, 4178 { F_RPLPERR, "PCIe replay buffer parity error" }, 4179 { F_PCIESINT, "PCIe core secondary fault" }, 4180 { F_PCIEPINT, "PCIe core primary fault" }, 4181 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" }, 4182 { 0 } 4183 }; 4184 static const struct intr_details t5_pcie_intr_details[] = { 4185 { F_IPGRPPERR, "Parity errors observed by IP" }, 4186 { F_NONFATALERR, "PCIe non-fatal error" }, 4187 { F_READRSPERR, "Outbound read error" }, 4188 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" }, 4189 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" }, 4190 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" }, 4191 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" }, 4192 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" }, 4193 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" }, 4194 { F_MAGRPPERR, "MA group FIFO parity error" }, 4195 { F_VFIDPERR, "VFID SRAM parity error" }, 4196 { F_FIDPERR, "FID SRAM parity error" }, 4197 { F_CFGSNPPERR, "config snoop FIFO parity error" }, 4198 { F_HRSPPERR, "HMA channel response data SRAM parity error" }, 4199 { F_HREQRDPERR, "HMA channel read request SRAM parity error" }, 4200 { F_HREQWRPERR, "HMA channel write request SRAM parity error" }, 4201 { F_DRSPPERR, "DMA channel response data SRAM parity error" }, 4202 { F_DREQRDPERR, "DMA channel write request SRAM parity error" }, 4203 { F_CRSPPERR, "CMD channel response data SRAM parity error" }, 4204 { F_CREQRDPERR, "CMD channel read request SRAM parity error" }, 4205 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" }, 4206 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" }, 4207 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" }, 4208 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" }, 4209 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" }, 4210 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" }, 4211 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" }, 4212 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" }, 4213 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" }, 4214 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" }, 4215 { F_MSTGRPPERR, "Master response read queue SRAM parity error" }, 4216 { 0 } 4217 }; 4218 struct intr_info pcie_intr_info = { 4219 .name = "PCIE_INT_CAUSE", 4220 .cause_reg = A_PCIE_INT_CAUSE, 4221 .enable_reg = A_PCIE_INT_ENABLE, 4222 .fatal = 0xffffffff, 4223 .flags = NONFATAL_IF_DISABLED, 4224 .details = NULL, 4225 .actions = NULL, 4226 }; 4227 bool fatal = false; 4228 4229 if (is_t4(adap)) { 4230 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose); 4231 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose); 4232 4233 pcie_intr_info.details = pcie_intr_details; 4234 } else { 4235 pcie_intr_info.details = t5_pcie_intr_details; 4236 } 4237 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose); 4238 4239 return (fatal); 4240} 4241 4242/* 4243 * TP interrupt handler. 4244 */ 4245static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose) 4246{ 4247 static const struct intr_details tp_intr_details[] = { 4248 { 0x3fffffff, "TP parity error" }, 4249 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" }, 4250 { 0 } 4251 }; 4252 static const struct intr_info tp_intr_info = { 4253 .name = "TP_INT_CAUSE", 4254 .cause_reg = A_TP_INT_CAUSE, 4255 .enable_reg = A_TP_INT_ENABLE, 4256 .fatal = 0x7fffffff, 4257 .flags = NONFATAL_IF_DISABLED, 4258 .details = tp_intr_details, 4259 .actions = NULL, 4260 }; 4261 4262 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose)); 4263} 4264 4265/* 4266 * SGE interrupt handler. 4267 */ 4268static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose) 4269{ 4270 static const struct intr_info sge_int1_info = { 4271 .name = "SGE_INT_CAUSE1", 4272 .cause_reg = A_SGE_INT_CAUSE1, 4273 .enable_reg = A_SGE_INT_ENABLE1, 4274 .fatal = 0xffffffff, 4275 .flags = NONFATAL_IF_DISABLED, 4276 .details = NULL, 4277 .actions = NULL, 4278 }; 4279 static const struct intr_info sge_int2_info = { 4280 .name = "SGE_INT_CAUSE2", 4281 .cause_reg = A_SGE_INT_CAUSE2, 4282 .enable_reg = A_SGE_INT_ENABLE2, 4283 .fatal = 0xffffffff, 4284 .flags = NONFATAL_IF_DISABLED, 4285 .details = NULL, 4286 .actions = NULL, 4287 }; 4288 static const struct intr_details sge_int3_details[] = { 4289 { F_ERR_FLM_DBP, 4290 "DBP pointer delivery for invalid context or QID" }, 4291 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4292 "Invalid QID or header request by IDMA" }, 4293 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4294 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4295 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4296 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4297 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4298 { F_ERR_TIMER_ABOVE_MAX_QID, 4299 "SGE GTS with timer 0-5 for IQID > 1023" }, 4300 { F_ERR_CPL_EXCEED_IQE_SIZE, 4301 "SGE received CPL exceeding IQE size" }, 4302 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4303 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4304 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4305 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4306 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4307 "SGE IQID > 1023 received CPL for FL" }, 4308 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4309 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4310 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4311 { F_ERR_ING_CTXT_PRIO, 4312 "Ingress context manager priority user error" }, 4313 { F_ERR_EGR_CTXT_PRIO, 4314 "Egress context manager priority user error" }, 4315 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" }, 4316 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" }, 4317 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4318 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4319 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4320 { 0x0000000f, "SGE context access for invalid queue" }, 4321 { 0 } 4322 }; 4323 static const struct intr_details t6_sge_int3_details[] = { 4324 { F_ERR_FLM_DBP, 4325 "DBP pointer delivery for invalid context or QID" }, 4326 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4327 "Invalid QID or header request by IDMA" }, 4328 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4329 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4330 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4331 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4332 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4333 { F_ERR_TIMER_ABOVE_MAX_QID, 4334 "SGE GTS with timer 0-5 for IQID > 1023" }, 4335 { F_ERR_CPL_EXCEED_IQE_SIZE, 4336 "SGE received CPL exceeding IQE size" }, 4337 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4338 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4339 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4340 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4341 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4342 "SGE IQID > 1023 received CPL for FL" }, 4343 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4344 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4345 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4346 { F_ERR_ING_CTXT_PRIO, 4347 "Ingress context manager priority user error" }, 4348 { F_ERR_EGR_CTXT_PRIO, 4349 "Egress context manager priority user error" }, 4350 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" }, 4351 { F_FATAL_WRE_LEN, 4352 "SGE WRE packet less than advertized length" }, 4353 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4354 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4355 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4356 { 0x0000000f, "SGE context access for invalid queue" }, 4357 { 0 } 4358 }; 4359 struct intr_info sge_int3_info = { 4360 .name = "SGE_INT_CAUSE3", 4361 .cause_reg = A_SGE_INT_CAUSE3, 4362 .enable_reg = A_SGE_INT_ENABLE3, 4363 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE, 4364 .flags = 0, 4365 .details = NULL, 4366 .actions = NULL, 4367 }; 4368 static const struct intr_info sge_int4_info = { 4369 .name = "SGE_INT_CAUSE4", 4370 .cause_reg = A_SGE_INT_CAUSE4, 4371 .enable_reg = A_SGE_INT_ENABLE4, 4372 .fatal = 0, 4373 .flags = 0, 4374 .details = NULL, 4375 .actions = NULL, 4376 }; 4377 static const struct intr_info sge_int5_info = { 4378 .name = "SGE_INT_CAUSE5", 4379 .cause_reg = A_SGE_INT_CAUSE5, 4380 .enable_reg = A_SGE_INT_ENABLE5, 4381 .fatal = 0xffffffff, 4382 .flags = NONFATAL_IF_DISABLED, 4383 .details = NULL, 4384 .actions = NULL, 4385 }; 4386 static const struct intr_info sge_int6_info = { 4387 .name = "SGE_INT_CAUSE6", 4388 .cause_reg = A_SGE_INT_CAUSE6, 4389 .enable_reg = A_SGE_INT_ENABLE6, 4390 .fatal = 0, 4391 .flags = 0, 4392 .details = NULL, 4393 .actions = NULL, 4394 }; 4395 4396 bool fatal; 4397 u32 v; 4398 4399 if (chip_id(adap) <= CHELSIO_T5) { 4400 sge_int3_info.details = sge_int3_details; 4401 } else { 4402 sge_int3_info.details = t6_sge_int3_details; 4403 } 4404 4405 fatal = false; 4406 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose); 4407 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose); 4408 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose); 4409 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose); 4410 if (chip_id(adap) >= CHELSIO_T5) 4411 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose); 4412 if (chip_id(adap) >= CHELSIO_T6) 4413 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose); 4414 4415 v = t4_read_reg(adap, A_SGE_ERROR_STATS); 4416 if (v & F_ERROR_QID_VALID) { 4417 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v)); 4418 if (v & F_UNCAPTURED_ERROR) 4419 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4420 t4_write_reg(adap, A_SGE_ERROR_STATS, 4421 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR); 4422 } 4423 4424 return (fatal); 4425} 4426 4427/* 4428 * CIM interrupt handler. 4429 */ 4430static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose) 4431{ 4432 static const struct intr_action cim_host_intr_actions[] = { 4433 { F_TIMER0INT, 0, t4_os_dump_cimla }, 4434 { 0 }, 4435 }; 4436 static const struct intr_details cim_host_intr_details[] = { 4437 /* T6+ */ 4438 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" }, 4439 4440 /* T5+ */ 4441 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" }, 4442 { F_PLCIM_MSTRSPDATAPARERR, 4443 "PL2CIM master response data parity error" }, 4444 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" }, 4445 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" }, 4446 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" }, 4447 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" }, 4448 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" }, 4449 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" }, 4450 4451 /* T4+ */ 4452 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" }, 4453 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" }, 4454 { F_MBHOSTPARERR, "CIM mailbox host read parity error" }, 4455 { F_MBUPPARERR, "CIM mailbox uP parity error" }, 4456 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" }, 4457 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" }, 4458 { F_IBQULPPARERR, "CIM IBQ ULP parity error" }, 4459 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" }, 4460 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */ 4461 "CIM IBQ PCIe/SGE_HI parity error" }, 4462 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" }, 4463 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" }, 4464 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" }, 4465 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" }, 4466 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" }, 4467 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" }, 4468 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" }, 4469 { F_TIMER1INT, "CIM TIMER0 interrupt" }, 4470 { F_TIMER0INT, "CIM TIMER0 interrupt" }, 4471 { F_PREFDROPINT, "CIM control register prefetch drop" }, 4472 { 0} 4473 }; 4474 static const struct intr_info cim_host_intr_info = { 4475 .name = "CIM_HOST_INT_CAUSE", 4476 .cause_reg = A_CIM_HOST_INT_CAUSE, 4477 .enable_reg = A_CIM_HOST_INT_ENABLE, 4478 .fatal = 0x007fffe6, 4479 .flags = NONFATAL_IF_DISABLED, 4480 .details = cim_host_intr_details, 4481 .actions = cim_host_intr_actions, 4482 }; 4483 static const struct intr_details cim_host_upacc_intr_details[] = { 4484 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" }, 4485 { F_TIMEOUTMAINT, "CIM PIF MA timeout" }, 4486 { F_TIMEOUTINT, "CIM PIF timeout" }, 4487 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" }, 4488 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" }, 4489 { F_BLKWRPLINT, "CIM block write to PL space" }, 4490 { F_BLKRDPLINT, "CIM block read from PL space" }, 4491 { F_SGLWRPLINT, 4492 "CIM single write to PL space with illegal BEs" }, 4493 { F_SGLRDPLINT, 4494 "CIM single read from PL space with illegal BEs" }, 4495 { F_BLKWRCTLINT, "CIM block write to CTL space" }, 4496 { F_BLKRDCTLINT, "CIM block read from CTL space" }, 4497 { F_SGLWRCTLINT, 4498 "CIM single write to CTL space with illegal BEs" }, 4499 { F_SGLRDCTLINT, 4500 "CIM single read from CTL space with illegal BEs" }, 4501 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" }, 4502 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" }, 4503 { F_SGLWREEPROMINT, 4504 "CIM single write to EEPROM space with illegal BEs" }, 4505 { F_SGLRDEEPROMINT, 4506 "CIM single read from EEPROM space with illegal BEs" }, 4507 { F_BLKWRFLASHINT, "CIM block write to flash space" }, 4508 { F_BLKRDFLASHINT, "CIM block read from flash space" }, 4509 { F_SGLWRFLASHINT, "CIM single write to flash space" }, 4510 { F_SGLRDFLASHINT, 4511 "CIM single read from flash space with illegal BEs" }, 4512 { F_BLKWRBOOTINT, "CIM block write to boot space" }, 4513 { F_BLKRDBOOTINT, "CIM block read from boot space" }, 4514 { F_SGLWRBOOTINT, "CIM single write to boot space" }, 4515 { F_SGLRDBOOTINT, 4516 "CIM single read from boot space with illegal BEs" }, 4517 { F_ILLWRBEINT, "CIM illegal write BEs" }, 4518 { F_ILLRDBEINT, "CIM illegal read BEs" }, 4519 { F_ILLRDINT, "CIM illegal read" }, 4520 { F_ILLWRINT, "CIM illegal write" }, 4521 { F_ILLTRANSINT, "CIM illegal transaction" }, 4522 { F_RSVDSPACEINT, "CIM reserved space access" }, 4523 {0} 4524 }; 4525 static const struct intr_info cim_host_upacc_intr_info = { 4526 .name = "CIM_HOST_UPACC_INT_CAUSE", 4527 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE, 4528 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE, 4529 .fatal = 0x3fffeeff, 4530 .flags = NONFATAL_IF_DISABLED, 4531 .details = cim_host_upacc_intr_details, 4532 .actions = NULL, 4533 }; 4534 static const struct intr_info cim_pf_host_intr_info = { 4535 .name = "CIM_PF_HOST_INT_CAUSE", 4536 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4537 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE), 4538 .fatal = 0, 4539 .flags = 0, 4540 .details = NULL, 4541 .actions = NULL, 4542 }; 4543 u32 val, fw_err; 4544 bool fatal; 4545 4546 fw_err = t4_read_reg(adap, A_PCIE_FW); 4547 if (fw_err & F_PCIE_FW_ERR) 4548 t4_report_fw_error(adap); 4549 4550 /* 4551 * When the Firmware detects an internal error which normally wouldn't 4552 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4553 * to make sure the Host sees the Firmware Crash. So if we have a 4554 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4555 * interrupt. 4556 */ 4557 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE); 4558 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) || 4559 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) { 4560 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT); 4561 } 4562 4563 fatal = false; 4564 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose); 4565 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose); 4566 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose); 4567 4568 return (fatal); 4569} 4570 4571/* 4572 * ULP RX interrupt handler. 4573 */ 4574static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose) 4575{ 4576 static const struct intr_details ulprx_intr_details[] = { 4577 /* T5+ */ 4578 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" }, 4579 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" }, 4580 4581 /* T4+ */ 4582 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" }, 4583 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" }, 4584 { 0x007fffff, "ULPRX parity error" }, 4585 { 0 } 4586 }; 4587 static const struct intr_info ulprx_intr_info = { 4588 .name = "ULP_RX_INT_CAUSE", 4589 .cause_reg = A_ULP_RX_INT_CAUSE, 4590 .enable_reg = A_ULP_RX_INT_ENABLE, 4591 .fatal = 0x07ffffff, 4592 .flags = NONFATAL_IF_DISABLED, 4593 .details = ulprx_intr_details, 4594 .actions = NULL, 4595 }; 4596 static const struct intr_info ulprx_intr2_info = { 4597 .name = "ULP_RX_INT_CAUSE_2", 4598 .cause_reg = A_ULP_RX_INT_CAUSE_2, 4599 .enable_reg = A_ULP_RX_INT_ENABLE_2, 4600 .fatal = 0, 4601 .flags = 0, 4602 .details = NULL, 4603 .actions = NULL, 4604 }; 4605 bool fatal = false; 4606 4607 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose); 4608 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose); 4609 4610 return (fatal); 4611} 4612 4613/* 4614 * ULP TX interrupt handler. 4615 */ 4616static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose) 4617{ 4618 static const struct intr_details ulptx_intr_details[] = { 4619 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" }, 4620 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" }, 4621 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" }, 4622 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" }, 4623 { 0x0fffffff, "ULPTX parity error" }, 4624 { 0 } 4625 }; 4626 static const struct intr_info ulptx_intr_info = { 4627 .name = "ULP_TX_INT_CAUSE", 4628 .cause_reg = A_ULP_TX_INT_CAUSE, 4629 .enable_reg = A_ULP_TX_INT_ENABLE, 4630 .fatal = 0x0fffffff, 4631 .flags = NONFATAL_IF_DISABLED, 4632 .details = ulptx_intr_details, 4633 .actions = NULL, 4634 }; 4635 static const struct intr_info ulptx_intr2_info = { 4636 .name = "ULP_TX_INT_CAUSE_2", 4637 .cause_reg = A_ULP_TX_INT_CAUSE_2, 4638 .enable_reg = A_ULP_TX_INT_ENABLE_2, 4639 .fatal = 0xf0, 4640 .flags = NONFATAL_IF_DISABLED, 4641 .details = NULL, 4642 .actions = NULL, 4643 }; 4644 bool fatal = false; 4645 4646 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose); 4647 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose); 4648 4649 return (fatal); 4650} 4651 4652static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose) 4653{ 4654 int i; 4655 u32 data[17]; 4656 4657 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0], 4658 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0); 4659 for (i = 0; i < ARRAY_SIZE(data); i++) { 4660 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i, 4661 A_PM_TX_DBG_STAT0 + i, data[i]); 4662 } 4663 4664 return (false); 4665} 4666 4667/* 4668 * PM TX interrupt handler. 4669 */ 4670static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose) 4671{ 4672 static const struct intr_action pmtx_intr_actions[] = { 4673 { 0xffffffff, 0, pmtx_dump_dbg_stats }, 4674 { 0 }, 4675 }; 4676 static const struct intr_details pmtx_intr_details[] = { 4677 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" }, 4678 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" }, 4679 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" }, 4680 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, 4681 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" }, 4682 { 0x00f00000, "PMTX icspi FIFO Rx framing error" }, 4683 { 0x000f0000, "PMTX icspi FIFO Tx framing error" }, 4684 { 0x0000f000, "PMTX oespi FIFO Rx framing error" }, 4685 { 0x00000f00, "PMTX oespi FIFO Tx framing error" }, 4686 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" }, 4687 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" }, 4688 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" }, 4689 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" }, 4690 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" }, 4691 { 0 } 4692 }; 4693 static const struct intr_info pmtx_intr_info = { 4694 .name = "PM_TX_INT_CAUSE", 4695 .cause_reg = A_PM_TX_INT_CAUSE, 4696 .enable_reg = A_PM_TX_INT_ENABLE, 4697 .fatal = 0xffffffff, 4698 .flags = 0, 4699 .details = pmtx_intr_details, 4700 .actions = pmtx_intr_actions, 4701 }; 4702 4703 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose)); 4704} 4705 4706/* 4707 * PM RX interrupt handler. 4708 */ 4709static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose) 4710{ 4711 static const struct intr_details pmrx_intr_details[] = { 4712 /* T6+ */ 4713 { 0x18000000, "PMRX ospi overflow" }, 4714 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" }, 4715 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" }, 4716 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" }, 4717 { F_SDC_ERR, "PMRX SDC error" }, 4718 4719 /* T4+ */ 4720 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, 4721 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" }, 4722 { 0x0003c000, "PMRX iespi Rx framing error" }, 4723 { 0x00003c00, "PMRX iespi Tx framing error" }, 4724 { 0x00000300, "PMRX ocspi Rx framing error" }, 4725 { 0x000000c0, "PMRX ocspi Tx framing error" }, 4726 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" }, 4727 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" }, 4728 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" }, 4729 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" }, 4730 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"}, 4731 { 0 } 4732 }; 4733 static const struct intr_info pmrx_intr_info = { 4734 .name = "PM_RX_INT_CAUSE", 4735 .cause_reg = A_PM_RX_INT_CAUSE, 4736 .enable_reg = A_PM_RX_INT_ENABLE, 4737 .fatal = 0x1fffffff, 4738 .flags = NONFATAL_IF_DISABLED, 4739 .details = pmrx_intr_details, 4740 .actions = NULL, 4741 }; 4742 4743 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose)); 4744} 4745 4746/* 4747 * CPL switch interrupt handler. 4748 */ 4749static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose) 4750{ 4751 static const struct intr_details cplsw_intr_details[] = { 4752 /* T5+ */ 4753 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" }, 4754 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" }, 4755 4756 /* T4+ */ 4757 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" }, 4758 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" }, 4759 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" }, 4760 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" }, 4761 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" }, 4762 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" }, 4763 { 0 } 4764 }; 4765 static const struct intr_info cplsw_intr_info = { 4766 .name = "CPL_INTR_CAUSE", 4767 .cause_reg = A_CPL_INTR_CAUSE, 4768 .enable_reg = A_CPL_INTR_ENABLE, 4769 .fatal = 0xff, 4770 .flags = NONFATAL_IF_DISABLED, 4771 .details = cplsw_intr_details, 4772 .actions = NULL, 4773 }; 4774 4775 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose)); 4776} 4777 4778#define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR) 4779#define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR) 4780#define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \ 4781 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \ 4782 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \ 4783 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR) 4784#define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \ 4785 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \ 4786 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR) 4787 4788/* 4789 * LE interrupt handler. 4790 */ 4791static bool le_intr_handler(struct adapter *adap, int arg, bool verbose) 4792{ 4793 static const struct intr_details le_intr_details[] = { 4794 { F_REQQPARERR, "LE request queue parity error" }, 4795 { F_UNKNOWNCMD, "LE unknown command" }, 4796 { F_ACTRGNFULL, "LE active region full" }, 4797 { F_PARITYERR, "LE parity error" }, 4798 { F_LIPMISS, "LE LIP miss" }, 4799 { F_LIP0, "LE 0 LIP error" }, 4800 { 0 } 4801 }; 4802 static const struct intr_details t6_le_intr_details[] = { 4803 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" }, 4804 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" }, 4805 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" }, 4806 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" }, 4807 { F_TOTCNTERR, "LE total active < TCAM count" }, 4808 { F_CMDPRSRINTERR, "LE internal error in parser" }, 4809 { F_CMDTIDERR, "Incorrect tid in LE command" }, 4810 { F_T6_ACTRGNFULL, "LE active region full" }, 4811 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" }, 4812 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" }, 4813 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" }, 4814 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" }, 4815 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" }, 4816 { F_TCAMACCFAIL, "LE TCAM access failure" }, 4817 { F_T6_UNKNOWNCMD, "LE unknown command" }, 4818 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" }, 4819 { F_T6_LIPMISS, "LE CLIP lookup miss" }, 4820 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" }, 4821 { 0 } 4822 }; 4823 struct intr_info le_intr_info = { 4824 .name = "LE_DB_INT_CAUSE", 4825 .cause_reg = A_LE_DB_INT_CAUSE, 4826 .enable_reg = A_LE_DB_INT_ENABLE, 4827 .fatal = 0, 4828 .flags = NONFATAL_IF_DISABLED, 4829 .details = NULL, 4830 .actions = NULL, 4831 }; 4832 4833 if (chip_id(adap) <= CHELSIO_T5) { 4834 le_intr_info.details = le_intr_details; 4835 le_intr_info.fatal = T5_LE_FATAL_MASK; 4836 } else { 4837 le_intr_info.details = t6_le_intr_details; 4838 le_intr_info.fatal = T6_LE_FATAL_MASK; 4839 } 4840 4841 return (t4_handle_intr(adap, &le_intr_info, 0, verbose)); 4842} 4843 4844/* 4845 * MPS interrupt handler. 4846 */ 4847static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose) 4848{ 4849 static const struct intr_details mps_rx_perr_intr_details[] = { 4850 { 0xffffffff, "MPS Rx parity error" }, 4851 { 0 } 4852 }; 4853 static const struct intr_info mps_rx_perr_intr_info = { 4854 .name = "MPS_RX_PERR_INT_CAUSE", 4855 .cause_reg = A_MPS_RX_PERR_INT_CAUSE, 4856 .enable_reg = A_MPS_RX_PERR_INT_ENABLE, 4857 .fatal = 0xffffffff, 4858 .flags = NONFATAL_IF_DISABLED, 4859 .details = mps_rx_perr_intr_details, 4860 .actions = NULL, 4861 }; 4862 static const struct intr_details mps_tx_intr_details[] = { 4863 { F_PORTERR, "MPS Tx destination port is disabled" }, 4864 { F_FRMERR, "MPS Tx framing error" }, 4865 { F_SECNTERR, "MPS Tx SOP/EOP error" }, 4866 { F_BUBBLE, "MPS Tx underflow" }, 4867 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" }, 4868 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" }, 4869 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" }, 4870 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" }, 4871 { 0 } 4872 }; 4873 static const struct intr_info mps_tx_intr_info = { 4874 .name = "MPS_TX_INT_CAUSE", 4875 .cause_reg = A_MPS_TX_INT_CAUSE, 4876 .enable_reg = A_MPS_TX_INT_ENABLE, 4877 .fatal = 0x1ffff, 4878 .flags = NONFATAL_IF_DISABLED, 4879 .details = mps_tx_intr_details, 4880 .actions = NULL, 4881 }; 4882 static const struct intr_details mps_trc_intr_details[] = { 4883 { F_MISCPERR, "MPS TRC misc parity error" }, 4884 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" }, 4885 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" }, 4886 { 0 } 4887 }; 4888 static const struct intr_info mps_trc_intr_info = { 4889 .name = "MPS_TRC_INT_CAUSE", 4890 .cause_reg = A_MPS_TRC_INT_CAUSE, 4891 .enable_reg = A_MPS_TRC_INT_ENABLE, 4892 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM), 4893 .flags = 0, 4894 .details = mps_trc_intr_details, 4895 .actions = NULL, 4896 }; 4897 static const struct intr_details mps_stat_sram_intr_details[] = { 4898 { 0xffffffff, "MPS statistics SRAM parity error" }, 4899 { 0 } 4900 }; 4901 static const struct intr_info mps_stat_sram_intr_info = { 4902 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM", 4903 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4904 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM, 4905 .fatal = 0x1fffffff, 4906 .flags = NONFATAL_IF_DISABLED, 4907 .details = mps_stat_sram_intr_details, 4908 .actions = NULL, 4909 }; 4910 static const struct intr_details mps_stat_tx_intr_details[] = { 4911 { 0xffffff, "MPS statistics Tx FIFO parity error" }, 4912 { 0 } 4913 }; 4914 static const struct intr_info mps_stat_tx_intr_info = { 4915 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 4916 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4917 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO, 4918 .fatal = 0xffffff, 4919 .flags = NONFATAL_IF_DISABLED, 4920 .details = mps_stat_tx_intr_details, 4921 .actions = NULL, 4922 }; 4923 static const struct intr_details mps_stat_rx_intr_details[] = { 4924 { 0xffffff, "MPS statistics Rx FIFO parity error" }, 4925 { 0 } 4926 }; 4927 static const struct intr_info mps_stat_rx_intr_info = { 4928 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 4929 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4930 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO, 4931 .fatal = 0xffffff, 4932 .flags = 0, 4933 .details = mps_stat_rx_intr_details, 4934 .actions = NULL, 4935 }; 4936 static const struct intr_details mps_cls_intr_details[] = { 4937 { F_HASHSRAM, "MPS hash SRAM parity error" }, 4938 { F_MATCHTCAM, "MPS match TCAM parity error" }, 4939 { F_MATCHSRAM, "MPS match SRAM parity error" }, 4940 { 0 } 4941 }; 4942 static const struct intr_info mps_cls_intr_info = { 4943 .name = "MPS_CLS_INT_CAUSE", 4944 .cause_reg = A_MPS_CLS_INT_CAUSE, 4945 .enable_reg = A_MPS_CLS_INT_ENABLE, 4946 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM, 4947 .flags = 0, 4948 .details = mps_cls_intr_details, 4949 .actions = NULL, 4950 }; 4951 static const struct intr_details mps_stat_sram1_intr_details[] = { 4952 { 0xff, "MPS statistics SRAM1 parity error" }, 4953 { 0 } 4954 }; 4955 static const struct intr_info mps_stat_sram1_intr_info = { 4956 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1", 4957 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 4958 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1, 4959 .fatal = 0xff, 4960 .flags = 0, 4961 .details = mps_stat_sram1_intr_details, 4962 .actions = NULL, 4963 }; 4964 4965 bool fatal; 4966 4967 fatal = false; 4968 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose); 4969 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose); 4970 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose); 4971 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose); 4972 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose); 4973 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose); 4974 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose); 4975 if (chip_id(adap) > CHELSIO_T4) { 4976 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0, 4977 verbose); 4978 } 4979 4980 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 4981 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */ 4982 4983 return (fatal); 4984 4985} 4986 4987/* 4988 * EDC/MC interrupt handler. 4989 */ 4990static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose) 4991{ 4992 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" }; 4993 unsigned int count_reg, v; 4994 static const struct intr_details mem_intr_details[] = { 4995 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" }, 4996 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" }, 4997 { F_PERR_INT_CAUSE, "FIFO parity error" }, 4998 { 0 } 4999 }; 5000 struct intr_info ii = { 5001 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE, 5002 .details = mem_intr_details, 5003 .flags = 0, 5004 .actions = NULL, 5005 }; 5006 bool fatal; 5007 5008 switch (idx) { 5009 case MEM_EDC0: 5010 ii.name = "EDC0_INT_CAUSE"; 5011 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0); 5012 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0); 5013 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0); 5014 break; 5015 case MEM_EDC1: 5016 ii.name = "EDC1_INT_CAUSE"; 5017 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1); 5018 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1); 5019 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1); 5020 break; 5021 case MEM_MC0: 5022 ii.name = "MC0_INT_CAUSE"; 5023 if (is_t4(adap)) { 5024 ii.cause_reg = A_MC_INT_CAUSE; 5025 ii.enable_reg = A_MC_INT_ENABLE; 5026 count_reg = A_MC_ECC_STATUS; 5027 } else { 5028 ii.cause_reg = A_MC_P_INT_CAUSE; 5029 ii.enable_reg = A_MC_P_INT_ENABLE; 5030 count_reg = A_MC_P_ECC_STATUS; 5031 } 5032 break; 5033 case MEM_MC1: 5034 ii.name = "MC1_INT_CAUSE"; 5035 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1); 5036 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1); 5037 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1); 5038 break; 5039 } 5040 5041 fatal = t4_handle_intr(adap, &ii, 0, verbose); 5042 5043 v = t4_read_reg(adap, count_reg); 5044 if (v != 0) { 5045 if (G_ECC_UECNT(v) != 0) { 5046 CH_ALERT(adap, 5047 "%s: %u uncorrectable ECC data error(s)\n", 5048 name[idx], G_ECC_UECNT(v)); 5049 } 5050 if (G_ECC_CECNT(v) != 0) { 5051 if (idx <= MEM_EDC1) 5052 t4_edc_err_read(adap, idx); 5053 CH_WARN_RATELIMIT(adap, 5054 "%s: %u correctable ECC data error(s)\n", 5055 name[idx], G_ECC_CECNT(v)); 5056 } 5057 t4_write_reg(adap, count_reg, 0xffffffff); 5058 } 5059 5060 return (fatal); 5061} 5062 5063static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose) 5064{ 5065 u32 v; 5066 5067 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS); 5068 CH_ALERT(adap, 5069 "MA address wrap-around error by client %u to address %#x\n", 5070 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4); 5071 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v); 5072 5073 return (false); 5074} 5075 5076 5077/* 5078 * MA interrupt handler. 5079 */ 5080static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose) 5081{ 5082 static const struct intr_action ma_intr_actions[] = { 5083 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status }, 5084 { 0 }, 5085 }; 5086 static const struct intr_info ma_intr_info = { 5087 .name = "MA_INT_CAUSE", 5088 .cause_reg = A_MA_INT_CAUSE, 5089 .enable_reg = A_MA_INT_ENABLE, 5090 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE, 5091 .flags = NONFATAL_IF_DISABLED, 5092 .details = NULL, 5093 .actions = ma_intr_actions, 5094 }; 5095 static const struct intr_info ma_perr_status1 = { 5096 .name = "MA_PARITY_ERROR_STATUS1", 5097 .cause_reg = A_MA_PARITY_ERROR_STATUS1, 5098 .enable_reg = A_MA_PARITY_ERROR_ENABLE1, 5099 .fatal = 0xffffffff, 5100 .flags = 0, 5101 .details = NULL, 5102 .actions = NULL, 5103 }; 5104 static const struct intr_info ma_perr_status2 = { 5105 .name = "MA_PARITY_ERROR_STATUS2", 5106 .cause_reg = A_MA_PARITY_ERROR_STATUS2, 5107 .enable_reg = A_MA_PARITY_ERROR_ENABLE2, 5108 .fatal = 0xffffffff, 5109 .flags = 0, 5110 .details = NULL, 5111 .actions = NULL, 5112 }; 5113 bool fatal; 5114 5115 fatal = false; 5116 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose); 5117 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose); 5118 if (chip_id(adap) > CHELSIO_T4) 5119 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose); 5120 5121 return (fatal); 5122} 5123 5124/* 5125 * SMB interrupt handler. 5126 */ 5127static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose) 5128{ 5129 static const struct intr_details smb_intr_details[] = { 5130 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" }, 5131 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" }, 5132 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" }, 5133 { 0 } 5134 }; 5135 static const struct intr_info smb_intr_info = { 5136 .name = "SMB_INT_CAUSE", 5137 .cause_reg = A_SMB_INT_CAUSE, 5138 .enable_reg = A_SMB_INT_ENABLE, 5139 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT, 5140 .flags = 0, 5141 .details = smb_intr_details, 5142 .actions = NULL, 5143 }; 5144 5145 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose)); 5146} 5147 5148/* 5149 * NC-SI interrupt handler. 5150 */ 5151static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose) 5152{ 5153 static const struct intr_details ncsi_intr_details[] = { 5154 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" }, 5155 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" }, 5156 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" }, 5157 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" }, 5158 { 0 } 5159 }; 5160 static const struct intr_info ncsi_intr_info = { 5161 .name = "NCSI_INT_CAUSE", 5162 .cause_reg = A_NCSI_INT_CAUSE, 5163 .enable_reg = A_NCSI_INT_ENABLE, 5164 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR | 5165 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR, 5166 .flags = 0, 5167 .details = ncsi_intr_details, 5168 .actions = NULL, 5169 }; 5170 5171 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose)); 5172} 5173 5174/* 5175 * MAC interrupt handler. 5176 */ 5177static bool mac_intr_handler(struct adapter *adap, int port, bool verbose) 5178{ 5179 static const struct intr_details mac_intr_details[] = { 5180 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" }, 5181 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" }, 5182 { 0 } 5183 }; 5184 char name[32]; 5185 struct intr_info ii; 5186 bool fatal = false; 5187 5188 if (is_t4(adap)) { 5189 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port); 5190 ii.name = &name[0]; 5191 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 5192 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN); 5193 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5194 ii.flags = 0; 5195 ii.details = mac_intr_details; 5196 ii.actions = NULL; 5197 } else { 5198 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port); 5199 ii.name = &name[0]; 5200 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 5201 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN); 5202 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5203 ii.flags = 0; 5204 ii.details = mac_intr_details; 5205 ii.actions = NULL; 5206 } 5207 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5208 5209 if (chip_id(adap) >= CHELSIO_T5) { 5210 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port); 5211 ii.name = &name[0]; 5212 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE); 5213 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN); 5214 ii.fatal = 0; 5215 ii.flags = 0; 5216 ii.details = NULL; 5217 ii.actions = NULL; 5218 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5219 } 5220 5221 if (chip_id(adap) >= CHELSIO_T6) { 5222 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port); 5223 ii.name = &name[0]; 5224 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G); 5225 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G); 5226 ii.fatal = 0; 5227 ii.flags = 0; 5228 ii.details = NULL; 5229 ii.actions = NULL; 5230 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5231 } 5232 5233 return (fatal); 5234} 5235 5236static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose) 5237{ 5238 static const struct intr_details plpl_intr_details[] = { 5239 { F_FATALPERR, "Fatal parity error" }, 5240 { F_PERRVFID, "VFID_MAP parity error" }, 5241 { 0 } 5242 }; 5243 static const struct intr_info plpl_intr_info = { 5244 .name = "PL_PL_INT_CAUSE", 5245 .cause_reg = A_PL_PL_INT_CAUSE, 5246 .enable_reg = A_PL_PL_INT_ENABLE, 5247 .fatal = F_FATALPERR | F_PERRVFID, 5248 .flags = NONFATAL_IF_DISABLED, 5249 .details = plpl_intr_details, 5250 .actions = NULL, 5251 }; 5252 5253 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose)); 5254} 5255 5256/** 5257 * t4_slow_intr_handler - control path interrupt handler 5258 * @adap: the adapter 5259 * @verbose: increased verbosity, for debug 5260 * 5261 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 5262 * The designation 'slow' is because it involves register reads, while 5263 * data interrupts typically don't involve any MMIOs. 5264 */ 5265int t4_slow_intr_handler(struct adapter *adap, bool verbose) 5266{ 5267 static const struct intr_details pl_intr_details[] = { 5268 { F_MC1, "MC1" }, 5269 { F_UART, "UART" }, 5270 { F_ULP_TX, "ULP TX" }, 5271 { F_SGE, "SGE" }, 5272 { F_HMA, "HMA" }, 5273 { F_CPL_SWITCH, "CPL Switch" }, 5274 { F_ULP_RX, "ULP RX" }, 5275 { F_PM_RX, "PM RX" }, 5276 { F_PM_TX, "PM TX" }, 5277 { F_MA, "MA" }, 5278 { F_TP, "TP" }, 5279 { F_LE, "LE" }, 5280 { F_EDC1, "EDC1" }, 5281 { F_EDC0, "EDC0" }, 5282 { F_MC, "MC0" }, 5283 { F_PCIE, "PCIE" }, 5284 { F_PMU, "PMU" }, 5285 { F_MAC3, "MAC3" }, 5286 { F_MAC2, "MAC2" }, 5287 { F_MAC1, "MAC1" }, 5288 { F_MAC0, "MAC0" }, 5289 { F_SMB, "SMB" }, 5290 { F_SF, "SF" }, 5291 { F_PL, "PL" }, 5292 { F_NCSI, "NC-SI" }, 5293 { F_MPS, "MPS" }, 5294 { F_MI, "MI" }, 5295 { F_DBG, "DBG" }, 5296 { F_I2CM, "I2CM" }, 5297 { F_CIM, "CIM" }, 5298 { 0 } 5299 }; 5300 static const struct intr_info pl_perr_cause = { 5301 .name = "PL_PERR_CAUSE", 5302 .cause_reg = A_PL_PERR_CAUSE, 5303 .enable_reg = A_PL_PERR_ENABLE, 5304 .fatal = 0xffffffff, 5305 .flags = 0, 5306 .details = pl_intr_details, 5307 .actions = NULL, 5308 }; 5309 static const struct intr_action pl_intr_action[] = { 5310 { F_MC1, MEM_MC1, mem_intr_handler }, 5311 { F_ULP_TX, -1, ulptx_intr_handler }, 5312 { F_SGE, -1, sge_intr_handler }, 5313 { F_CPL_SWITCH, -1, cplsw_intr_handler }, 5314 { F_ULP_RX, -1, ulprx_intr_handler }, 5315 { F_PM_RX, -1, pmrx_intr_handler}, 5316 { F_PM_TX, -1, pmtx_intr_handler}, 5317 { F_MA, -1, ma_intr_handler }, 5318 { F_TP, -1, tp_intr_handler }, 5319 { F_LE, -1, le_intr_handler }, 5320 { F_EDC1, MEM_EDC1, mem_intr_handler }, 5321 { F_EDC0, MEM_EDC0, mem_intr_handler }, 5322 { F_MC0, MEM_MC0, mem_intr_handler }, 5323 { F_PCIE, -1, pcie_intr_handler }, 5324 { F_MAC3, 3, mac_intr_handler}, 5325 { F_MAC2, 2, mac_intr_handler}, 5326 { F_MAC1, 1, mac_intr_handler}, 5327 { F_MAC0, 0, mac_intr_handler}, 5328 { F_SMB, -1, smb_intr_handler}, 5329 { F_PL, -1, plpl_intr_handler }, 5330 { F_NCSI, -1, ncsi_intr_handler}, 5331 { F_MPS, -1, mps_intr_handler }, 5332 { F_CIM, -1, cim_intr_handler }, 5333 { 0 } 5334 }; 5335 static const struct intr_info pl_intr_info = { 5336 .name = "PL_INT_CAUSE", 5337 .cause_reg = A_PL_INT_CAUSE, 5338 .enable_reg = A_PL_INT_ENABLE, 5339 .fatal = 0, 5340 .flags = 0, 5341 .details = pl_intr_details, 5342 .actions = pl_intr_action, 5343 }; 5344 bool fatal; 5345 u32 perr; 5346 5347 perr = t4_read_reg(adap, pl_perr_cause.cause_reg); 5348 if (verbose || perr != 0) { 5349 t4_show_intr_info(adap, &pl_perr_cause, perr); 5350 if (perr != 0) 5351 t4_write_reg(adap, pl_perr_cause.cause_reg, perr); 5352 if (verbose) 5353 perr |= t4_read_reg(adap, pl_intr_info.enable_reg); 5354 } 5355 fatal = t4_handle_intr(adap, &pl_intr_info, perr, verbose); 5356 if (fatal) 5357 t4_fatal_err(adap, false); 5358 5359 return (0); 5360} 5361 5362#define PF_INTR_MASK (F_PFSW | F_PFCIM) 5363 5364/** 5365 * t4_intr_enable - enable interrupts 5366 * @adapter: the adapter whose interrupts should be enabled 5367 * 5368 * Enable PF-specific interrupts for the calling function and the top-level 5369 * interrupt concentrator for global interrupts. Interrupts are already 5370 * enabled at each module, here we just enable the roots of the interrupt 5371 * hierarchies. 5372 * 5373 * Note: this function should be called only when the driver manages 5374 * non PF-specific interrupts from the various HW modules. Only one PCI 5375 * function at a time should be doing this. 5376 */ 5377void t4_intr_enable(struct adapter *adap) 5378{ 5379 u32 val = 0; 5380 5381 if (chip_id(adap) <= CHELSIO_T5) 5382 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 5383 else 5384 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 5385 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC | 5386 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 | 5387 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 | 5388 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 5389 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT | 5390 F_EGRESS_SIZE_ERR; 5391 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val); 5392 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 5393 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0); 5394 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf); 5395} 5396 5397/** 5398 * t4_intr_disable - disable interrupts 5399 * @adap: the adapter whose interrupts should be disabled 5400 * 5401 * Disable interrupts. We only disable the top-level interrupt 5402 * concentrators. The caller must be a PCI function managing global 5403 * interrupts. 5404 */ 5405void t4_intr_disable(struct adapter *adap) 5406{ 5407 5408 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 5409 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0); 5410} 5411 5412/** 5413 * t4_intr_clear - clear all interrupts 5414 * @adap: the adapter whose interrupts should be cleared 5415 * 5416 * Clears all interrupts. The caller must be a PCI function managing 5417 * global interrupts. 5418 */ 5419void t4_intr_clear(struct adapter *adap) 5420{ 5421 static const u32 cause_reg[] = { 5422 A_CIM_HOST_INT_CAUSE, 5423 A_CIM_HOST_UPACC_INT_CAUSE, 5424 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 5425 A_CPL_INTR_CAUSE, 5426 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1), 5427 A_LE_DB_INT_CAUSE, 5428 A_MA_INT_WRAP_STATUS, 5429 A_MA_PARITY_ERROR_STATUS1, 5430 A_MA_INT_CAUSE, 5431 A_MPS_CLS_INT_CAUSE, 5432 A_MPS_RX_PERR_INT_CAUSE, 5433 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 5434 A_MPS_STAT_PERR_INT_CAUSE_SRAM, 5435 A_MPS_TRC_INT_CAUSE, 5436 A_MPS_TX_INT_CAUSE, 5437 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 5438 A_NCSI_INT_CAUSE, 5439 A_PCIE_INT_CAUSE, 5440 A_PCIE_NONFAT_ERR, 5441 A_PL_PL_INT_CAUSE, 5442 A_PM_RX_INT_CAUSE, 5443 A_PM_TX_INT_CAUSE, 5444 A_SGE_INT_CAUSE1, 5445 A_SGE_INT_CAUSE2, 5446 A_SGE_INT_CAUSE3, 5447 A_SGE_INT_CAUSE4, 5448 A_SMB_INT_CAUSE, 5449 A_TP_INT_CAUSE, 5450 A_ULP_RX_INT_CAUSE, 5451 A_ULP_RX_INT_CAUSE_2, 5452 A_ULP_TX_INT_CAUSE, 5453 A_ULP_TX_INT_CAUSE_2, 5454 5455 MYPF_REG(A_PL_PF_INT_CAUSE), 5456 }; 5457 int i; 5458 const int nchan = adap->chip_params->nchan; 5459 5460 for (i = 0; i < ARRAY_SIZE(cause_reg); i++) 5461 t4_write_reg(adap, cause_reg[i], 0xffffffff); 5462 5463 if (is_t4(adap)) { 5464 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 5465 0xffffffff); 5466 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 5467 0xffffffff); 5468 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff); 5469 for (i = 0; i < nchan; i++) { 5470 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE), 5471 0xffffffff); 5472 } 5473 } 5474 if (chip_id(adap) >= CHELSIO_T5) { 5475 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 5476 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff); 5477 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff); 5478 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff); 5479 if (is_t5(adap)) { 5480 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1), 5481 0xffffffff); 5482 } 5483 for (i = 0; i < nchan; i++) { 5484 t4_write_reg(adap, T5_PORT_REG(i, 5485 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff); 5486 if (chip_id(adap) > CHELSIO_T5) { 5487 t4_write_reg(adap, T5_PORT_REG(i, 5488 A_MAC_PORT_PERR_INT_CAUSE_100G), 5489 0xffffffff); 5490 } 5491 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE), 5492 0xffffffff); 5493 } 5494 } 5495 if (chip_id(adap) >= CHELSIO_T6) { 5496 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff); 5497 } 5498 5499 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5500 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff); 5501 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff); 5502 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */ 5503} 5504 5505/** 5506 * hash_mac_addr - return the hash value of a MAC address 5507 * @addr: the 48-bit Ethernet MAC address 5508 * 5509 * Hashes a MAC address according to the hash function used by HW inexact 5510 * (hash) address matching. 5511 */ 5512static int hash_mac_addr(const u8 *addr) 5513{ 5514 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 5515 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 5516 a ^= b; 5517 a ^= (a >> 12); 5518 a ^= (a >> 6); 5519 return a & 0x3f; 5520} 5521 5522/** 5523 * t4_config_rss_range - configure a portion of the RSS mapping table 5524 * @adapter: the adapter 5525 * @mbox: mbox to use for the FW command 5526 * @viid: virtual interface whose RSS subtable is to be written 5527 * @start: start entry in the table to write 5528 * @n: how many table entries to write 5529 * @rspq: values for the "response queue" (Ingress Queue) lookup table 5530 * @nrspq: number of values in @rspq 5531 * 5532 * Programs the selected part of the VI's RSS mapping table with the 5533 * provided values. If @nrspq < @n the supplied values are used repeatedly 5534 * until the full table range is populated. 5535 * 5536 * The caller must ensure the values in @rspq are in the range allowed for 5537 * @viid. 5538 */ 5539int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 5540 int start, int n, const u16 *rspq, unsigned int nrspq) 5541{ 5542 int ret; 5543 const u16 *rsp = rspq; 5544 const u16 *rsp_end = rspq + nrspq; 5545 struct fw_rss_ind_tbl_cmd cmd; 5546 5547 memset(&cmd, 0, sizeof(cmd)); 5548 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 5549 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5550 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 5551 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 5552 5553 /* 5554 * Each firmware RSS command can accommodate up to 32 RSS Ingress 5555 * Queue Identifiers. These Ingress Queue IDs are packed three to 5556 * a 32-bit word as 10-bit values with the upper remaining 2 bits 5557 * reserved. 5558 */ 5559 while (n > 0) { 5560 int nq = min(n, 32); 5561 int nq_packed = 0; 5562 __be32 *qp = &cmd.iq0_to_iq2; 5563 5564 /* 5565 * Set up the firmware RSS command header to send the next 5566 * "nq" Ingress Queue IDs to the firmware. 5567 */ 5568 cmd.niqid = cpu_to_be16(nq); 5569 cmd.startidx = cpu_to_be16(start); 5570 5571 /* 5572 * "nq" more done for the start of the next loop. 5573 */ 5574 start += nq; 5575 n -= nq; 5576 5577 /* 5578 * While there are still Ingress Queue IDs to stuff into the 5579 * current firmware RSS command, retrieve them from the 5580 * Ingress Queue ID array and insert them into the command. 5581 */ 5582 while (nq > 0) { 5583 /* 5584 * Grab up to the next 3 Ingress Queue IDs (wrapping 5585 * around the Ingress Queue ID array if necessary) and 5586 * insert them into the firmware RSS command at the 5587 * current 3-tuple position within the commad. 5588 */ 5589 u16 qbuf[3]; 5590 u16 *qbp = qbuf; 5591 int nqbuf = min(3, nq); 5592 5593 nq -= nqbuf; 5594 qbuf[0] = qbuf[1] = qbuf[2] = 0; 5595 while (nqbuf && nq_packed < 32) { 5596 nqbuf--; 5597 nq_packed++; 5598 *qbp++ = *rsp++; 5599 if (rsp >= rsp_end) 5600 rsp = rspq; 5601 } 5602 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 5603 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 5604 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 5605 } 5606 5607 /* 5608 * Send this portion of the RRS table update to the firmware; 5609 * bail out on any errors. 5610 */ 5611 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 5612 if (ret) 5613 return ret; 5614 } 5615 return 0; 5616} 5617 5618/** 5619 * t4_config_glbl_rss - configure the global RSS mode 5620 * @adapter: the adapter 5621 * @mbox: mbox to use for the FW command 5622 * @mode: global RSS mode 5623 * @flags: mode-specific flags 5624 * 5625 * Sets the global RSS mode. 5626 */ 5627int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 5628 unsigned int flags) 5629{ 5630 struct fw_rss_glb_config_cmd c; 5631 5632 memset(&c, 0, sizeof(c)); 5633 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 5634 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5635 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5636 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 5637 c.u.manual.mode_pkd = 5638 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5639 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 5640 c.u.basicvirtual.mode_keymode = 5641 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5642 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 5643 } else 5644 return -EINVAL; 5645 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5646} 5647 5648/** 5649 * t4_config_vi_rss - configure per VI RSS settings 5650 * @adapter: the adapter 5651 * @mbox: mbox to use for the FW command 5652 * @viid: the VI id 5653 * @flags: RSS flags 5654 * @defq: id of the default RSS queue for the VI. 5655 * @skeyidx: RSS secret key table index for non-global mode 5656 * @skey: RSS vf_scramble key for VI. 5657 * 5658 * Configures VI-specific RSS properties. 5659 */ 5660int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 5661 unsigned int flags, unsigned int defq, unsigned int skeyidx, 5662 unsigned int skey) 5663{ 5664 struct fw_rss_vi_config_cmd c; 5665 5666 memset(&c, 0, sizeof(c)); 5667 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 5668 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5669 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 5670 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5671 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 5672 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 5673 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 5674 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 5675 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 5676 5677 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5678} 5679 5680/* Read an RSS table row */ 5681static int rd_rss_row(struct adapter *adap, int row, u32 *val) 5682{ 5683 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 5684 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 5685 5, 0, val); 5686} 5687 5688/** 5689 * t4_read_rss - read the contents of the RSS mapping table 5690 * @adapter: the adapter 5691 * @map: holds the contents of the RSS mapping table 5692 * 5693 * Reads the contents of the RSS hash->queue mapping table. 5694 */ 5695int t4_read_rss(struct adapter *adapter, u16 *map) 5696{ 5697 u32 val; 5698 int i, ret; 5699 int rss_nentries = adapter->chip_params->rss_nentries; 5700 5701 for (i = 0; i < rss_nentries / 2; ++i) { 5702 ret = rd_rss_row(adapter, i, &val); 5703 if (ret) 5704 return ret; 5705 *map++ = G_LKPTBLQUEUE0(val); 5706 *map++ = G_LKPTBLQUEUE1(val); 5707 } 5708 return 0; 5709} 5710 5711/** 5712 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 5713 * @adap: the adapter 5714 * @cmd: TP fw ldst address space type 5715 * @vals: where the indirect register values are stored/written 5716 * @nregs: how many indirect registers to read/write 5717 * @start_idx: index of first indirect register to read/write 5718 * @rw: Read (1) or Write (0) 5719 * @sleep_ok: if true we may sleep while awaiting command completion 5720 * 5721 * Access TP indirect registers through LDST 5722 **/ 5723static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 5724 unsigned int nregs, unsigned int start_index, 5725 unsigned int rw, bool sleep_ok) 5726{ 5727 int ret = 0; 5728 unsigned int i; 5729 struct fw_ldst_cmd c; 5730 5731 for (i = 0; i < nregs; i++) { 5732 memset(&c, 0, sizeof(c)); 5733 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 5734 F_FW_CMD_REQUEST | 5735 (rw ? F_FW_CMD_READ : 5736 F_FW_CMD_WRITE) | 5737 V_FW_LDST_CMD_ADDRSPACE(cmd)); 5738 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 5739 5740 c.u.addrval.addr = cpu_to_be32(start_index + i); 5741 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 5742 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 5743 sleep_ok); 5744 if (ret) 5745 return ret; 5746 5747 if (rw) 5748 vals[i] = be32_to_cpu(c.u.addrval.val); 5749 } 5750 return 0; 5751} 5752 5753/** 5754 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 5755 * @adap: the adapter 5756 * @reg_addr: Address Register 5757 * @reg_data: Data register 5758 * @buff: where the indirect register values are stored/written 5759 * @nregs: how many indirect registers to read/write 5760 * @start_index: index of first indirect register to read/write 5761 * @rw: READ(1) or WRITE(0) 5762 * @sleep_ok: if true we may sleep while awaiting command completion 5763 * 5764 * Read/Write TP indirect registers through LDST if possible. 5765 * Else, use backdoor access 5766 **/ 5767static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 5768 u32 *buff, u32 nregs, u32 start_index, int rw, 5769 bool sleep_ok) 5770{ 5771 int rc = -EINVAL; 5772 int cmd; 5773 5774 switch (reg_addr) { 5775 case A_TP_PIO_ADDR: 5776 cmd = FW_LDST_ADDRSPC_TP_PIO; 5777 break; 5778 case A_TP_TM_PIO_ADDR: 5779 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 5780 break; 5781 case A_TP_MIB_INDEX: 5782 cmd = FW_LDST_ADDRSPC_TP_MIB; 5783 break; 5784 default: 5785 goto indirect_access; 5786 } 5787 5788 if (t4_use_ldst(adap)) 5789 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 5790 sleep_ok); 5791 5792indirect_access: 5793 5794 if (rc) { 5795 if (rw) 5796 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 5797 start_index); 5798 else 5799 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 5800 start_index); 5801 } 5802} 5803 5804/** 5805 * t4_tp_pio_read - Read TP PIO registers 5806 * @adap: the adapter 5807 * @buff: where the indirect register values are written 5808 * @nregs: how many indirect registers to read 5809 * @start_index: index of first indirect register to read 5810 * @sleep_ok: if true we may sleep while awaiting command completion 5811 * 5812 * Read TP PIO Registers 5813 **/ 5814void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5815 u32 start_index, bool sleep_ok) 5816{ 5817 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 5818 start_index, 1, sleep_ok); 5819} 5820 5821/** 5822 * t4_tp_pio_write - Write TP PIO registers 5823 * @adap: the adapter 5824 * @buff: where the indirect register values are stored 5825 * @nregs: how many indirect registers to write 5826 * @start_index: index of first indirect register to write 5827 * @sleep_ok: if true we may sleep while awaiting command completion 5828 * 5829 * Write TP PIO Registers 5830 **/ 5831void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 5832 u32 start_index, bool sleep_ok) 5833{ 5834 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5835 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 5836} 5837 5838/** 5839 * t4_tp_tm_pio_read - Read TP TM PIO registers 5840 * @adap: the adapter 5841 * @buff: where the indirect register values are written 5842 * @nregs: how many indirect registers to read 5843 * @start_index: index of first indirect register to read 5844 * @sleep_ok: if true we may sleep while awaiting command completion 5845 * 5846 * Read TP TM PIO Registers 5847 **/ 5848void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5849 u32 start_index, bool sleep_ok) 5850{ 5851 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 5852 nregs, start_index, 1, sleep_ok); 5853} 5854 5855/** 5856 * t4_tp_mib_read - Read TP MIB registers 5857 * @adap: the adapter 5858 * @buff: where the indirect register values are written 5859 * @nregs: how many indirect registers to read 5860 * @start_index: index of first indirect register to read 5861 * @sleep_ok: if true we may sleep while awaiting command completion 5862 * 5863 * Read TP MIB Registers 5864 **/ 5865void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5866 bool sleep_ok) 5867{ 5868 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5869 start_index, 1, sleep_ok); 5870} 5871 5872/** 5873 * t4_read_rss_key - read the global RSS key 5874 * @adap: the adapter 5875 * @key: 10-entry array holding the 320-bit RSS key 5876 * @sleep_ok: if true we may sleep while awaiting command completion 5877 * 5878 * Reads the global 320-bit RSS key. 5879 */ 5880void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5881{ 5882 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5883} 5884 5885/** 5886 * t4_write_rss_key - program one of the RSS keys 5887 * @adap: the adapter 5888 * @key: 10-entry array holding the 320-bit RSS key 5889 * @idx: which RSS key to write 5890 * @sleep_ok: if true we may sleep while awaiting command completion 5891 * 5892 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5893 * 0..15 the corresponding entry in the RSS key table is written, 5894 * otherwise the global RSS key is written. 5895 */ 5896void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5897 bool sleep_ok) 5898{ 5899 u8 rss_key_addr_cnt = 16; 5900 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5901 5902 /* 5903 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5904 * allows access to key addresses 16-63 by using KeyWrAddrX 5905 * as index[5:4](upper 2) into key table 5906 */ 5907 if ((chip_id(adap) > CHELSIO_T5) && 5908 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5909 rss_key_addr_cnt = 32; 5910 5911 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5912 5913 if (idx >= 0 && idx < rss_key_addr_cnt) { 5914 if (rss_key_addr_cnt > 16) 5915 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5916 vrt | V_KEYWRADDRX(idx >> 4) | 5917 V_T6_VFWRADDR(idx) | F_KEYWREN); 5918 else 5919 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5920 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5921 } 5922} 5923 5924/** 5925 * t4_read_rss_pf_config - read PF RSS Configuration Table 5926 * @adapter: the adapter 5927 * @index: the entry in the PF RSS table to read 5928 * @valp: where to store the returned value 5929 * @sleep_ok: if true we may sleep while awaiting command completion 5930 * 5931 * Reads the PF RSS Configuration Table at the specified index and returns 5932 * the value found there. 5933 */ 5934void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5935 u32 *valp, bool sleep_ok) 5936{ 5937 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5938} 5939 5940/** 5941 * t4_write_rss_pf_config - write PF RSS Configuration Table 5942 * @adapter: the adapter 5943 * @index: the entry in the VF RSS table to read 5944 * @val: the value to store 5945 * @sleep_ok: if true we may sleep while awaiting command completion 5946 * 5947 * Writes the PF RSS Configuration Table at the specified index with the 5948 * specified value. 5949 */ 5950void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5951 u32 val, bool sleep_ok) 5952{ 5953 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5954 sleep_ok); 5955} 5956 5957/** 5958 * t4_read_rss_vf_config - read VF RSS Configuration Table 5959 * @adapter: the adapter 5960 * @index: the entry in the VF RSS table to read 5961 * @vfl: where to store the returned VFL 5962 * @vfh: where to store the returned VFH 5963 * @sleep_ok: if true we may sleep while awaiting command completion 5964 * 5965 * Reads the VF RSS Configuration Table at the specified index and returns 5966 * the (VFL, VFH) values found there. 5967 */ 5968void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 5969 u32 *vfl, u32 *vfh, bool sleep_ok) 5970{ 5971 u32 vrt, mask, data; 5972 5973 if (chip_id(adapter) <= CHELSIO_T5) { 5974 mask = V_VFWRADDR(M_VFWRADDR); 5975 data = V_VFWRADDR(index); 5976 } else { 5977 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5978 data = V_T6_VFWRADDR(index); 5979 } 5980 /* 5981 * Request that the index'th VF Table values be read into VFL/VFH. 5982 */ 5983 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5984 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5985 vrt |= data | F_VFRDEN; 5986 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5987 5988 /* 5989 * Grab the VFL/VFH values ... 5990 */ 5991 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5992 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5993} 5994 5995/** 5996 * t4_write_rss_vf_config - write VF RSS Configuration Table 5997 * 5998 * @adapter: the adapter 5999 * @index: the entry in the VF RSS table to write 6000 * @vfl: the VFL to store 6001 * @vfh: the VFH to store 6002 * 6003 * Writes the VF RSS Configuration Table at the specified index with the 6004 * specified (VFL, VFH) values. 6005 */ 6006void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 6007 u32 vfl, u32 vfh, bool sleep_ok) 6008{ 6009 u32 vrt, mask, data; 6010 6011 if (chip_id(adapter) <= CHELSIO_T5) { 6012 mask = V_VFWRADDR(M_VFWRADDR); 6013 data = V_VFWRADDR(index); 6014 } else { 6015 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 6016 data = V_T6_VFWRADDR(index); 6017 } 6018 6019 /* 6020 * Load up VFL/VFH with the values to be written ... 6021 */ 6022 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 6023 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 6024 6025 /* 6026 * Write the VFL/VFH into the VF Table at index'th location. 6027 */ 6028 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 6029 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 6030 vrt |= data | F_VFRDEN; 6031 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 6032} 6033 6034/** 6035 * t4_read_rss_pf_map - read PF RSS Map 6036 * @adapter: the adapter 6037 * @sleep_ok: if true we may sleep while awaiting command completion 6038 * 6039 * Reads the PF RSS Map register and returns its value. 6040 */ 6041u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 6042{ 6043 u32 pfmap; 6044 6045 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6046 6047 return pfmap; 6048} 6049 6050/** 6051 * t4_write_rss_pf_map - write PF RSS Map 6052 * @adapter: the adapter 6053 * @pfmap: PF RSS Map value 6054 * 6055 * Writes the specified value to the PF RSS Map register. 6056 */ 6057void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 6058{ 6059 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6060} 6061 6062/** 6063 * t4_read_rss_pf_mask - read PF RSS Mask 6064 * @adapter: the adapter 6065 * @sleep_ok: if true we may sleep while awaiting command completion 6066 * 6067 * Reads the PF RSS Mask register and returns its value. 6068 */ 6069u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 6070{ 6071 u32 pfmask; 6072 6073 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6074 6075 return pfmask; 6076} 6077 6078/** 6079 * t4_write_rss_pf_mask - write PF RSS Mask 6080 * @adapter: the adapter 6081 * @pfmask: PF RSS Mask value 6082 * 6083 * Writes the specified value to the PF RSS Mask register. 6084 */ 6085void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 6086{ 6087 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6088} 6089 6090/** 6091 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 6092 * @adap: the adapter 6093 * @v4: holds the TCP/IP counter values 6094 * @v6: holds the TCP/IPv6 counter values 6095 * @sleep_ok: if true we may sleep while awaiting command completion 6096 * 6097 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 6098 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 6099 */ 6100void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 6101 struct tp_tcp_stats *v6, bool sleep_ok) 6102{ 6103 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 6104 6105#define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 6106#define STAT(x) val[STAT_IDX(x)] 6107#define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 6108 6109 if (v4) { 6110 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6111 A_TP_MIB_TCP_OUT_RST, sleep_ok); 6112 v4->tcp_out_rsts = STAT(OUT_RST); 6113 v4->tcp_in_segs = STAT64(IN_SEG); 6114 v4->tcp_out_segs = STAT64(OUT_SEG); 6115 v4->tcp_retrans_segs = STAT64(RXT_SEG); 6116 } 6117 if (v6) { 6118 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6119 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 6120 v6->tcp_out_rsts = STAT(OUT_RST); 6121 v6->tcp_in_segs = STAT64(IN_SEG); 6122 v6->tcp_out_segs = STAT64(OUT_SEG); 6123 v6->tcp_retrans_segs = STAT64(RXT_SEG); 6124 } 6125#undef STAT64 6126#undef STAT 6127#undef STAT_IDX 6128} 6129 6130/** 6131 * t4_tp_get_err_stats - read TP's error MIB counters 6132 * @adap: the adapter 6133 * @st: holds the counter values 6134 * @sleep_ok: if true we may sleep while awaiting command completion 6135 * 6136 * Returns the values of TP's error counters. 6137 */ 6138void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 6139 bool sleep_ok) 6140{ 6141 int nchan = adap->chip_params->nchan; 6142 6143 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 6144 sleep_ok); 6145 6146 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 6147 sleep_ok); 6148 6149 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 6150 sleep_ok); 6151 6152 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 6153 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 6154 6155 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 6156 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 6157 6158 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 6159 sleep_ok); 6160 6161 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 6162 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 6163 6164 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 6165 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 6166 6167 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 6168 sleep_ok); 6169} 6170 6171/** 6172 * t4_tp_get_err_stats - read TP's error MIB counters 6173 * @adap: the adapter 6174 * @st: holds the counter values 6175 * @sleep_ok: if true we may sleep while awaiting command completion 6176 * 6177 * Returns the values of TP's error counters. 6178 */ 6179void t4_tp_get_tnl_stats(struct adapter *adap, struct tp_tnl_stats *st, 6180 bool sleep_ok) 6181{ 6182 int nchan = adap->chip_params->nchan; 6183 6184 t4_tp_mib_read(adap, st->out_pkt, nchan, A_TP_MIB_TNL_OUT_PKT_0, 6185 sleep_ok); 6186 t4_tp_mib_read(adap, st->in_pkt, nchan, A_TP_MIB_TNL_IN_PKT_0, 6187 sleep_ok); 6188} 6189 6190/** 6191 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 6192 * @adap: the adapter 6193 * @st: holds the counter values 6194 * 6195 * Returns the values of TP's proxy counters. 6196 */ 6197void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 6198 bool sleep_ok) 6199{ 6200 int nchan = adap->chip_params->nchan; 6201 6202 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 6203} 6204 6205/** 6206 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 6207 * @adap: the adapter 6208 * @st: holds the counter values 6209 * @sleep_ok: if true we may sleep while awaiting command completion 6210 * 6211 * Returns the values of TP's CPL counters. 6212 */ 6213void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 6214 bool sleep_ok) 6215{ 6216 int nchan = adap->chip_params->nchan; 6217 6218 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 6219 6220 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 6221} 6222 6223/** 6224 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 6225 * @adap: the adapter 6226 * @st: holds the counter values 6227 * 6228 * Returns the values of TP's RDMA counters. 6229 */ 6230void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 6231 bool sleep_ok) 6232{ 6233 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 6234 sleep_ok); 6235} 6236 6237/** 6238 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 6239 * @adap: the adapter 6240 * @idx: the port index 6241 * @st: holds the counter values 6242 * @sleep_ok: if true we may sleep while awaiting command completion 6243 * 6244 * Returns the values of TP's FCoE counters for the selected port. 6245 */ 6246void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 6247 struct tp_fcoe_stats *st, bool sleep_ok) 6248{ 6249 u32 val[2]; 6250 6251 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 6252 sleep_ok); 6253 6254 t4_tp_mib_read(adap, &st->frames_drop, 1, 6255 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 6256 6257 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 6258 sleep_ok); 6259 6260 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 6261} 6262 6263/** 6264 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 6265 * @adap: the adapter 6266 * @st: holds the counter values 6267 * @sleep_ok: if true we may sleep while awaiting command completion 6268 * 6269 * Returns the values of TP's counters for non-TCP directly-placed packets. 6270 */ 6271void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 6272 bool sleep_ok) 6273{ 6274 u32 val[4]; 6275 6276 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 6277 6278 st->frames = val[0]; 6279 st->drops = val[1]; 6280 st->octets = ((u64)val[2] << 32) | val[3]; 6281} 6282 6283/** 6284 * t4_tp_get_tid_stats - read TP's tid MIB counters. 6285 * @adap: the adapter 6286 * @st: holds the counter values 6287 * @sleep_ok: if true we may sleep while awaiting command completion 6288 * 6289 * Returns the values of TP's counters for tids. 6290 */ 6291void t4_tp_get_tid_stats(struct adapter *adap, struct tp_tid_stats *st, 6292 bool sleep_ok) 6293{ 6294 6295 t4_tp_mib_read(adap, &st->del, 4, A_TP_MIB_TID_DEL, sleep_ok); 6296} 6297 6298/** 6299 * t4_read_mtu_tbl - returns the values in the HW path MTU table 6300 * @adap: the adapter 6301 * @mtus: where to store the MTU values 6302 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 6303 * 6304 * Reads the HW path MTU table. 6305 */ 6306void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 6307{ 6308 u32 v; 6309 int i; 6310 6311 for (i = 0; i < NMTUS; ++i) { 6312 t4_write_reg(adap, A_TP_MTU_TABLE, 6313 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 6314 v = t4_read_reg(adap, A_TP_MTU_TABLE); 6315 mtus[i] = G_MTUVALUE(v); 6316 if (mtu_log) 6317 mtu_log[i] = G_MTUWIDTH(v); 6318 } 6319} 6320 6321/** 6322 * t4_read_cong_tbl - reads the congestion control table 6323 * @adap: the adapter 6324 * @incr: where to store the alpha values 6325 * 6326 * Reads the additive increments programmed into the HW congestion 6327 * control table. 6328 */ 6329void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 6330{ 6331 unsigned int mtu, w; 6332 6333 for (mtu = 0; mtu < NMTUS; ++mtu) 6334 for (w = 0; w < NCCTRL_WIN; ++w) { 6335 t4_write_reg(adap, A_TP_CCTRL_TABLE, 6336 V_ROWINDEX(0xffff) | (mtu << 5) | w); 6337 incr[mtu][w] = (u16)t4_read_reg(adap, 6338 A_TP_CCTRL_TABLE) & 0x1fff; 6339 } 6340} 6341 6342/** 6343 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 6344 * @adap: the adapter 6345 * @addr: the indirect TP register address 6346 * @mask: specifies the field within the register to modify 6347 * @val: new value for the field 6348 * 6349 * Sets a field of an indirect TP register to the given value. 6350 */ 6351void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 6352 unsigned int mask, unsigned int val) 6353{ 6354 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 6355 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 6356 t4_write_reg(adap, A_TP_PIO_DATA, val); 6357} 6358 6359/** 6360 * init_cong_ctrl - initialize congestion control parameters 6361 * @a: the alpha values for congestion control 6362 * @b: the beta values for congestion control 6363 * 6364 * Initialize the congestion control parameters. 6365 */ 6366static void init_cong_ctrl(unsigned short *a, unsigned short *b) 6367{ 6368 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 6369 a[9] = 2; 6370 a[10] = 3; 6371 a[11] = 4; 6372 a[12] = 5; 6373 a[13] = 6; 6374 a[14] = 7; 6375 a[15] = 8; 6376 a[16] = 9; 6377 a[17] = 10; 6378 a[18] = 14; 6379 a[19] = 17; 6380 a[20] = 21; 6381 a[21] = 25; 6382 a[22] = 30; 6383 a[23] = 35; 6384 a[24] = 45; 6385 a[25] = 60; 6386 a[26] = 80; 6387 a[27] = 100; 6388 a[28] = 200; 6389 a[29] = 300; 6390 a[30] = 400; 6391 a[31] = 500; 6392 6393 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 6394 b[9] = b[10] = 1; 6395 b[11] = b[12] = 2; 6396 b[13] = b[14] = b[15] = b[16] = 3; 6397 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 6398 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 6399 b[28] = b[29] = 6; 6400 b[30] = b[31] = 7; 6401} 6402 6403/* The minimum additive increment value for the congestion control table */ 6404#define CC_MIN_INCR 2U 6405 6406/** 6407 * t4_load_mtus - write the MTU and congestion control HW tables 6408 * @adap: the adapter 6409 * @mtus: the values for the MTU table 6410 * @alpha: the values for the congestion control alpha parameter 6411 * @beta: the values for the congestion control beta parameter 6412 * 6413 * Write the HW MTU table with the supplied MTUs and the high-speed 6414 * congestion control table with the supplied alpha, beta, and MTUs. 6415 * We write the two tables together because the additive increments 6416 * depend on the MTUs. 6417 */ 6418void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 6419 const unsigned short *alpha, const unsigned short *beta) 6420{ 6421 static const unsigned int avg_pkts[NCCTRL_WIN] = { 6422 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 6423 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 6424 28672, 40960, 57344, 81920, 114688, 163840, 229376 6425 }; 6426 6427 unsigned int i, w; 6428 6429 for (i = 0; i < NMTUS; ++i) { 6430 unsigned int mtu = mtus[i]; 6431 unsigned int log2 = fls(mtu); 6432 6433 if (!(mtu & ((1 << log2) >> 2))) /* round */ 6434 log2--; 6435 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 6436 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 6437 6438 for (w = 0; w < NCCTRL_WIN; ++w) { 6439 unsigned int inc; 6440 6441 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 6442 CC_MIN_INCR); 6443 6444 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 6445 (w << 16) | (beta[w] << 13) | inc); 6446 } 6447 } 6448} 6449 6450/** 6451 * t4_set_pace_tbl - set the pace table 6452 * @adap: the adapter 6453 * @pace_vals: the pace values in microseconds 6454 * @start: index of the first entry in the HW pace table to set 6455 * @n: how many entries to set 6456 * 6457 * Sets (a subset of the) HW pace table. 6458 */ 6459int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 6460 unsigned int start, unsigned int n) 6461{ 6462 unsigned int vals[NTX_SCHED], i; 6463 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 6464 6465 if (n > NTX_SCHED) 6466 return -ERANGE; 6467 6468 /* convert values from us to dack ticks, rounding to closest value */ 6469 for (i = 0; i < n; i++, pace_vals++) { 6470 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 6471 if (vals[i] > 0x7ff) 6472 return -ERANGE; 6473 if (*pace_vals && vals[i] == 0) 6474 return -ERANGE; 6475 } 6476 for (i = 0; i < n; i++, start++) 6477 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 6478 return 0; 6479} 6480 6481/** 6482 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 6483 * @adap: the adapter 6484 * @kbps: target rate in Kbps 6485 * @sched: the scheduler index 6486 * 6487 * Configure a Tx HW scheduler for the target rate. 6488 */ 6489int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 6490{ 6491 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 6492 unsigned int clk = adap->params.vpd.cclk * 1000; 6493 unsigned int selected_cpt = 0, selected_bpt = 0; 6494 6495 if (kbps > 0) { 6496 kbps *= 125; /* -> bytes */ 6497 for (cpt = 1; cpt <= 255; cpt++) { 6498 tps = clk / cpt; 6499 bpt = (kbps + tps / 2) / tps; 6500 if (bpt > 0 && bpt <= 255) { 6501 v = bpt * tps; 6502 delta = v >= kbps ? v - kbps : kbps - v; 6503 if (delta < mindelta) { 6504 mindelta = delta; 6505 selected_cpt = cpt; 6506 selected_bpt = bpt; 6507 } 6508 } else if (selected_cpt) 6509 break; 6510 } 6511 if (!selected_cpt) 6512 return -EINVAL; 6513 } 6514 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 6515 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 6516 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6517 if (sched & 1) 6518 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 6519 else 6520 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 6521 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6522 return 0; 6523} 6524 6525/** 6526 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 6527 * @adap: the adapter 6528 * @sched: the scheduler index 6529 * @ipg: the interpacket delay in tenths of nanoseconds 6530 * 6531 * Set the interpacket delay for a HW packet rate scheduler. 6532 */ 6533int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 6534{ 6535 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 6536 6537 /* convert ipg to nearest number of core clocks */ 6538 ipg *= core_ticks_per_usec(adap); 6539 ipg = (ipg + 5000) / 10000; 6540 if (ipg > M_TXTIMERSEPQ0) 6541 return -EINVAL; 6542 6543 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 6544 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6545 if (sched & 1) 6546 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 6547 else 6548 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 6549 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6550 t4_read_reg(adap, A_TP_TM_PIO_DATA); 6551 return 0; 6552} 6553 6554/* 6555 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 6556 * clocks. The formula is 6557 * 6558 * bytes/s = bytes256 * 256 * ClkFreq / 4096 6559 * 6560 * which is equivalent to 6561 * 6562 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 6563 */ 6564static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 6565{ 6566 u64 v = (u64)bytes256 * adap->params.vpd.cclk; 6567 6568 return v * 62 + v / 2; 6569} 6570 6571/** 6572 * t4_get_chan_txrate - get the current per channel Tx rates 6573 * @adap: the adapter 6574 * @nic_rate: rates for NIC traffic 6575 * @ofld_rate: rates for offloaded traffic 6576 * 6577 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 6578 * for each channel. 6579 */ 6580void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 6581{ 6582 u32 v; 6583 6584 v = t4_read_reg(adap, A_TP_TX_TRATE); 6585 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 6586 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 6587 if (adap->chip_params->nchan > 2) { 6588 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 6589 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 6590 } 6591 6592 v = t4_read_reg(adap, A_TP_TX_ORATE); 6593 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 6594 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 6595 if (adap->chip_params->nchan > 2) { 6596 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 6597 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 6598 } 6599} 6600 6601/** 6602 * t4_set_trace_filter - configure one of the tracing filters 6603 * @adap: the adapter 6604 * @tp: the desired trace filter parameters 6605 * @idx: which filter to configure 6606 * @enable: whether to enable or disable the filter 6607 * 6608 * Configures one of the tracing filters available in HW. If @tp is %NULL 6609 * it indicates that the filter is already written in the register and it 6610 * just needs to be enabled or disabled. 6611 */ 6612int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 6613 int idx, int enable) 6614{ 6615 int i, ofst = idx * 4; 6616 u32 data_reg, mask_reg, cfg; 6617 u32 multitrc = F_TRCMULTIFILTER; 6618 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 6619 6620 if (idx < 0 || idx >= NTRACE) 6621 return -EINVAL; 6622 6623 if (tp == NULL || !enable) { 6624 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 6625 enable ? en : 0); 6626 return 0; 6627 } 6628 6629 /* 6630 * TODO - After T4 data book is updated, specify the exact 6631 * section below. 6632 * 6633 * See T4 data book - MPS section for a complete description 6634 * of the below if..else handling of A_MPS_TRC_CFG register 6635 * value. 6636 */ 6637 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 6638 if (cfg & F_TRCMULTIFILTER) { 6639 /* 6640 * If multiple tracers are enabled, then maximum 6641 * capture size is 2.5KB (FIFO size of a single channel) 6642 * minus 2 flits for CPL_TRACE_PKT header. 6643 */ 6644 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 6645 return -EINVAL; 6646 } else { 6647 /* 6648 * If multiple tracers are disabled, to avoid deadlocks 6649 * maximum packet capture size of 9600 bytes is recommended. 6650 * Also in this mode, only trace0 can be enabled and running. 6651 */ 6652 multitrc = 0; 6653 if (tp->snap_len > 9600 || idx) 6654 return -EINVAL; 6655 } 6656 6657 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 6658 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 6659 tp->min_len > M_TFMINPKTSIZE) 6660 return -EINVAL; 6661 6662 /* stop the tracer we'll be changing */ 6663 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 6664 6665 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 6666 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 6667 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 6668 6669 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6670 t4_write_reg(adap, data_reg, tp->data[i]); 6671 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 6672 } 6673 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 6674 V_TFCAPTUREMAX(tp->snap_len) | 6675 V_TFMINPKTSIZE(tp->min_len)); 6676 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 6677 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 6678 (is_t4(adap) ? 6679 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 6680 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 6681 6682 return 0; 6683} 6684 6685/** 6686 * t4_get_trace_filter - query one of the tracing filters 6687 * @adap: the adapter 6688 * @tp: the current trace filter parameters 6689 * @idx: which trace filter to query 6690 * @enabled: non-zero if the filter is enabled 6691 * 6692 * Returns the current settings of one of the HW tracing filters. 6693 */ 6694void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 6695 int *enabled) 6696{ 6697 u32 ctla, ctlb; 6698 int i, ofst = idx * 4; 6699 u32 data_reg, mask_reg; 6700 6701 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 6702 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 6703 6704 if (is_t4(adap)) { 6705 *enabled = !!(ctla & F_TFEN); 6706 tp->port = G_TFPORT(ctla); 6707 tp->invert = !!(ctla & F_TFINVERTMATCH); 6708 } else { 6709 *enabled = !!(ctla & F_T5_TFEN); 6710 tp->port = G_T5_TFPORT(ctla); 6711 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 6712 } 6713 tp->snap_len = G_TFCAPTUREMAX(ctlb); 6714 tp->min_len = G_TFMINPKTSIZE(ctlb); 6715 tp->skip_ofst = G_TFOFFSET(ctla); 6716 tp->skip_len = G_TFLENGTH(ctla); 6717 6718 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 6719 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 6720 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 6721 6722 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6723 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 6724 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 6725 } 6726} 6727 6728/** 6729 * t4_pmtx_get_stats - returns the HW stats from PMTX 6730 * @adap: the adapter 6731 * @cnt: where to store the count statistics 6732 * @cycles: where to store the cycle statistics 6733 * 6734 * Returns performance statistics from PMTX. 6735 */ 6736void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6737{ 6738 int i; 6739 u32 data[2]; 6740 6741 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6742 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 6743 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 6744 if (is_t4(adap)) 6745 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 6746 else { 6747 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 6748 A_PM_TX_DBG_DATA, data, 2, 6749 A_PM_TX_DBG_STAT_MSB); 6750 cycles[i] = (((u64)data[0] << 32) | data[1]); 6751 } 6752 } 6753} 6754 6755/** 6756 * t4_pmrx_get_stats - returns the HW stats from PMRX 6757 * @adap: the adapter 6758 * @cnt: where to store the count statistics 6759 * @cycles: where to store the cycle statistics 6760 * 6761 * Returns performance statistics from PMRX. 6762 */ 6763void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6764{ 6765 int i; 6766 u32 data[2]; 6767 6768 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6769 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 6770 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 6771 if (is_t4(adap)) { 6772 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 6773 } else { 6774 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 6775 A_PM_RX_DBG_DATA, data, 2, 6776 A_PM_RX_DBG_STAT_MSB); 6777 cycles[i] = (((u64)data[0] << 32) | data[1]); 6778 } 6779 } 6780} 6781 6782/** 6783 * t4_get_mps_bg_map - return the buffer groups associated with a port 6784 * @adap: the adapter 6785 * @idx: the port index 6786 * 6787 * Returns a bitmap indicating which MPS buffer groups are associated 6788 * with the given port. Bit i is set if buffer group i is used by the 6789 * port. 6790 */ 6791static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 6792{ 6793 u32 n; 6794 6795 if (adap->params.mps_bg_map) 6796 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 6797 6798 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6799 if (n == 0) 6800 return idx == 0 ? 0xf : 0; 6801 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6802 return idx < 2 ? (3 << (2 * idx)) : 0; 6803 return 1 << idx; 6804} 6805 6806/* 6807 * TP RX e-channels associated with the port. 6808 */ 6809static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 6810{ 6811 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6812 const u32 all_chan = (1 << adap->chip_params->nchan) - 1; 6813 6814 if (n == 0) 6815 return idx == 0 ? all_chan : 0; 6816 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6817 return idx < 2 ? (3 << (2 * idx)) : 0; 6818 return 1 << idx; 6819} 6820 6821/* 6822 * TP RX c-channel associated with the port. 6823 */ 6824static unsigned int t4_get_rx_c_chan(struct adapter *adap, int idx) 6825{ 6826 u32 param, val; 6827 int ret; 6828 6829 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6830 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_TPCHMAP)); 6831 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 6832 if (!ret) 6833 return (val >> (8 * idx)) & 0xff; 6834 6835 return 0; 6836} 6837 6838/** 6839 * t4_get_port_type_description - return Port Type string description 6840 * @port_type: firmware Port Type enumeration 6841 */ 6842const char *t4_get_port_type_description(enum fw_port_type port_type) 6843{ 6844 static const char *const port_type_description[] = { 6845 "Fiber_XFI", 6846 "Fiber_XAUI", 6847 "BT_SGMII", 6848 "BT_XFI", 6849 "BT_XAUI", 6850 "KX4", 6851 "CX4", 6852 "KX", 6853 "KR", 6854 "SFP", 6855 "BP_AP", 6856 "BP4_AP", 6857 "QSFP_10G", 6858 "QSA", 6859 "QSFP", 6860 "BP40_BA", 6861 "KR4_100G", 6862 "CR4_QSFP", 6863 "CR_QSFP", 6864 "CR2_QSFP", 6865 "SFP28", 6866 "KR_SFP28", 6867 }; 6868 6869 if (port_type < ARRAY_SIZE(port_type_description)) 6870 return port_type_description[port_type]; 6871 return "UNKNOWN"; 6872} 6873 6874/** 6875 * t4_get_port_stats_offset - collect port stats relative to a previous 6876 * snapshot 6877 * @adap: The adapter 6878 * @idx: The port 6879 * @stats: Current stats to fill 6880 * @offset: Previous stats snapshot 6881 */ 6882void t4_get_port_stats_offset(struct adapter *adap, int idx, 6883 struct port_stats *stats, 6884 struct port_stats *offset) 6885{ 6886 u64 *s, *o; 6887 int i; 6888 6889 t4_get_port_stats(adap, idx, stats); 6890 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 6891 i < (sizeof(struct port_stats)/sizeof(u64)) ; 6892 i++, s++, o++) 6893 *s -= *o; 6894} 6895 6896/** 6897 * t4_get_port_stats - collect port statistics 6898 * @adap: the adapter 6899 * @idx: the port index 6900 * @p: the stats structure to fill 6901 * 6902 * Collect statistics related to the given port from HW. 6903 */ 6904void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 6905{ 6906 struct port_info *pi = adap->port[idx]; 6907 u32 bgmap = pi->mps_bg_map; 6908 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 6909 6910#define GET_STAT(name) \ 6911 t4_read_reg64(adap, \ 6912 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ 6913 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) 6914#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6915 6916 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6917 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6918 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6919 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6920 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6921 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6922 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6923 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6924 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6925 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6926 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6927 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6928 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6929 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6930 p->tx_drop = GET_STAT(TX_PORT_DROP); 6931 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6932 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6933 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6934 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6935 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6936 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6937 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6938 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6939 6940 if (chip_id(adap) >= CHELSIO_T5) { 6941 if (stat_ctl & F_COUNTPAUSESTATTX) { 6942 p->tx_frames -= p->tx_pause; 6943 p->tx_octets -= p->tx_pause * 64; 6944 } 6945 if (stat_ctl & F_COUNTPAUSEMCTX) 6946 p->tx_mcast_frames -= p->tx_pause; 6947 } 6948 6949 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6950 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6951 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6952 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6953 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6954 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6955 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6956 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 6957 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 6958 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 6959 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 6960 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 6961 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 6962 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 6963 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 6964 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 6965 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 6966 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 6967 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 6968 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 6969 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 6970 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 6971 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 6972 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 6973 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 6974 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 6975 6976 if (pi->fcs_reg != -1) 6977 p->rx_fcs_err = t4_read_reg64(adap, pi->fcs_reg) - pi->fcs_base; 6978 6979 if (chip_id(adap) >= CHELSIO_T5) { 6980 if (stat_ctl & F_COUNTPAUSESTATRX) { 6981 p->rx_frames -= p->rx_pause; 6982 p->rx_octets -= p->rx_pause * 64; 6983 } 6984 if (stat_ctl & F_COUNTPAUSEMCRX) 6985 p->rx_mcast_frames -= p->rx_pause; 6986 } 6987 6988 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 6989 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 6990 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 6991 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 6992 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 6993 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 6994 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 6995 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 6996 6997#undef GET_STAT 6998#undef GET_STAT_COM 6999} 7000 7001/** 7002 * t4_get_lb_stats - collect loopback port statistics 7003 * @adap: the adapter 7004 * @idx: the loopback port index 7005 * @p: the stats structure to fill 7006 * 7007 * Return HW statistics for the given loopback port. 7008 */ 7009void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 7010{ 7011 7012#define GET_STAT(name) \ 7013 t4_read_reg64(adap, \ 7014 (is_t4(adap) ? \ 7015 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 7016 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 7017#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 7018 7019 p->octets = GET_STAT(BYTES); 7020 p->frames = GET_STAT(FRAMES); 7021 p->bcast_frames = GET_STAT(BCAST); 7022 p->mcast_frames = GET_STAT(MCAST); 7023 p->ucast_frames = GET_STAT(UCAST); 7024 p->error_frames = GET_STAT(ERROR); 7025 7026 p->frames_64 = GET_STAT(64B); 7027 p->frames_65_127 = GET_STAT(65B_127B); 7028 p->frames_128_255 = GET_STAT(128B_255B); 7029 p->frames_256_511 = GET_STAT(256B_511B); 7030 p->frames_512_1023 = GET_STAT(512B_1023B); 7031 p->frames_1024_1518 = GET_STAT(1024B_1518B); 7032 p->frames_1519_max = GET_STAT(1519B_MAX); 7033 p->drop = GET_STAT(DROP_FRAMES); 7034 7035 if (idx < adap->params.nports) { 7036 u32 bg = adap2pinfo(adap, idx)->mps_bg_map; 7037 7038 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 7039 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 7040 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 7041 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 7042 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 7043 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 7044 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 7045 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 7046 } 7047 7048#undef GET_STAT 7049#undef GET_STAT_COM 7050} 7051 7052/** 7053 * t4_wol_magic_enable - enable/disable magic packet WoL 7054 * @adap: the adapter 7055 * @port: the physical port index 7056 * @addr: MAC address expected in magic packets, %NULL to disable 7057 * 7058 * Enables/disables magic packet wake-on-LAN for the selected port. 7059 */ 7060void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 7061 const u8 *addr) 7062{ 7063 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 7064 7065 if (is_t4(adap)) { 7066 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 7067 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 7068 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7069 } else { 7070 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 7071 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 7072 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7073 } 7074 7075 if (addr) { 7076 t4_write_reg(adap, mag_id_reg_l, 7077 (addr[2] << 24) | (addr[3] << 16) | 7078 (addr[4] << 8) | addr[5]); 7079 t4_write_reg(adap, mag_id_reg_h, 7080 (addr[0] << 8) | addr[1]); 7081 } 7082 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 7083 V_MAGICEN(addr != NULL)); 7084} 7085 7086/** 7087 * t4_wol_pat_enable - enable/disable pattern-based WoL 7088 * @adap: the adapter 7089 * @port: the physical port index 7090 * @map: bitmap of which HW pattern filters to set 7091 * @mask0: byte mask for bytes 0-63 of a packet 7092 * @mask1: byte mask for bytes 64-127 of a packet 7093 * @crc: Ethernet CRC for selected bytes 7094 * @enable: enable/disable switch 7095 * 7096 * Sets the pattern filters indicated in @map to mask out the bytes 7097 * specified in @mask0/@mask1 in received packets and compare the CRC of 7098 * the resulting packet against @crc. If @enable is %true pattern-based 7099 * WoL is enabled, otherwise disabled. 7100 */ 7101int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 7102 u64 mask0, u64 mask1, unsigned int crc, bool enable) 7103{ 7104 int i; 7105 u32 port_cfg_reg; 7106 7107 if (is_t4(adap)) 7108 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7109 else 7110 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7111 7112 if (!enable) { 7113 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 7114 return 0; 7115 } 7116 if (map > 0xff) 7117 return -EINVAL; 7118 7119#define EPIO_REG(name) \ 7120 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 7121 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 7122 7123 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 7124 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 7125 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 7126 7127 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 7128 if (!(map & 1)) 7129 continue; 7130 7131 /* write byte masks */ 7132 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 7133 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 7134 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7135 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7136 return -ETIMEDOUT; 7137 7138 /* write CRC */ 7139 t4_write_reg(adap, EPIO_REG(DATA0), crc); 7140 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 7141 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7142 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7143 return -ETIMEDOUT; 7144 } 7145#undef EPIO_REG 7146 7147 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 7148 return 0; 7149} 7150 7151/* t4_mk_filtdelwr - create a delete filter WR 7152 * @ftid: the filter ID 7153 * @wr: the filter work request to populate 7154 * @qid: ingress queue to receive the delete notification 7155 * 7156 * Creates a filter work request to delete the supplied filter. If @qid is 7157 * negative the delete notification is suppressed. 7158 */ 7159void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 7160{ 7161 memset(wr, 0, sizeof(*wr)); 7162 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 7163 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 7164 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 7165 V_FW_FILTER_WR_NOREPLY(qid < 0)); 7166 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 7167 if (qid >= 0) 7168 wr->rx_chan_rx_rpl_iq = 7169 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 7170} 7171 7172#define INIT_CMD(var, cmd, rd_wr) do { \ 7173 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 7174 F_FW_CMD_REQUEST | \ 7175 F_FW_CMD_##rd_wr); \ 7176 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 7177} while (0) 7178 7179int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 7180 u32 addr, u32 val) 7181{ 7182 u32 ldst_addrspace; 7183 struct fw_ldst_cmd c; 7184 7185 memset(&c, 0, sizeof(c)); 7186 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 7187 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7188 F_FW_CMD_REQUEST | 7189 F_FW_CMD_WRITE | 7190 ldst_addrspace); 7191 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7192 c.u.addrval.addr = cpu_to_be32(addr); 7193 c.u.addrval.val = cpu_to_be32(val); 7194 7195 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7196} 7197 7198/** 7199 * t4_mdio_rd - read a PHY register through MDIO 7200 * @adap: the adapter 7201 * @mbox: mailbox to use for the FW command 7202 * @phy_addr: the PHY address 7203 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7204 * @reg: the register to read 7205 * @valp: where to store the value 7206 * 7207 * Issues a FW command through the given mailbox to read a PHY register. 7208 */ 7209int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7210 unsigned int mmd, unsigned int reg, unsigned int *valp) 7211{ 7212 int ret; 7213 u32 ldst_addrspace; 7214 struct fw_ldst_cmd c; 7215 7216 memset(&c, 0, sizeof(c)); 7217 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7218 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7219 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7220 ldst_addrspace); 7221 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7222 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7223 V_FW_LDST_CMD_MMD(mmd)); 7224 c.u.mdio.raddr = cpu_to_be16(reg); 7225 7226 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7227 if (ret == 0) 7228 *valp = be16_to_cpu(c.u.mdio.rval); 7229 return ret; 7230} 7231 7232/** 7233 * t4_mdio_wr - write a PHY register through MDIO 7234 * @adap: the adapter 7235 * @mbox: mailbox to use for the FW command 7236 * @phy_addr: the PHY address 7237 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7238 * @reg: the register to write 7239 * @valp: value to write 7240 * 7241 * Issues a FW command through the given mailbox to write a PHY register. 7242 */ 7243int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7244 unsigned int mmd, unsigned int reg, unsigned int val) 7245{ 7246 u32 ldst_addrspace; 7247 struct fw_ldst_cmd c; 7248 7249 memset(&c, 0, sizeof(c)); 7250 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7251 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7252 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7253 ldst_addrspace); 7254 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7255 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7256 V_FW_LDST_CMD_MMD(mmd)); 7257 c.u.mdio.raddr = cpu_to_be16(reg); 7258 c.u.mdio.rval = cpu_to_be16(val); 7259 7260 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7261} 7262 7263/** 7264 * 7265 * t4_sge_decode_idma_state - decode the idma state 7266 * @adap: the adapter 7267 * @state: the state idma is stuck in 7268 */ 7269void t4_sge_decode_idma_state(struct adapter *adapter, int state) 7270{ 7271 static const char * const t4_decode[] = { 7272 "IDMA_IDLE", 7273 "IDMA_PUSH_MORE_CPL_FIFO", 7274 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7275 "Not used", 7276 "IDMA_PHYSADDR_SEND_PCIEHDR", 7277 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7278 "IDMA_PHYSADDR_SEND_PAYLOAD", 7279 "IDMA_SEND_FIFO_TO_IMSG", 7280 "IDMA_FL_REQ_DATA_FL_PREP", 7281 "IDMA_FL_REQ_DATA_FL", 7282 "IDMA_FL_DROP", 7283 "IDMA_FL_H_REQ_HEADER_FL", 7284 "IDMA_FL_H_SEND_PCIEHDR", 7285 "IDMA_FL_H_PUSH_CPL_FIFO", 7286 "IDMA_FL_H_SEND_CPL", 7287 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7288 "IDMA_FL_H_SEND_IP_HDR", 7289 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7290 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7291 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7292 "IDMA_FL_D_SEND_PCIEHDR", 7293 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7294 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7295 "IDMA_FL_SEND_PCIEHDR", 7296 "IDMA_FL_PUSH_CPL_FIFO", 7297 "IDMA_FL_SEND_CPL", 7298 "IDMA_FL_SEND_PAYLOAD_FIRST", 7299 "IDMA_FL_SEND_PAYLOAD", 7300 "IDMA_FL_REQ_NEXT_DATA_FL", 7301 "IDMA_FL_SEND_NEXT_PCIEHDR", 7302 "IDMA_FL_SEND_PADDING", 7303 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7304 "IDMA_FL_SEND_FIFO_TO_IMSG", 7305 "IDMA_FL_REQ_DATAFL_DONE", 7306 "IDMA_FL_REQ_HEADERFL_DONE", 7307 }; 7308 static const char * const t5_decode[] = { 7309 "IDMA_IDLE", 7310 "IDMA_ALMOST_IDLE", 7311 "IDMA_PUSH_MORE_CPL_FIFO", 7312 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7313 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7314 "IDMA_PHYSADDR_SEND_PCIEHDR", 7315 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7316 "IDMA_PHYSADDR_SEND_PAYLOAD", 7317 "IDMA_SEND_FIFO_TO_IMSG", 7318 "IDMA_FL_REQ_DATA_FL", 7319 "IDMA_FL_DROP", 7320 "IDMA_FL_DROP_SEND_INC", 7321 "IDMA_FL_H_REQ_HEADER_FL", 7322 "IDMA_FL_H_SEND_PCIEHDR", 7323 "IDMA_FL_H_PUSH_CPL_FIFO", 7324 "IDMA_FL_H_SEND_CPL", 7325 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7326 "IDMA_FL_H_SEND_IP_HDR", 7327 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7328 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7329 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7330 "IDMA_FL_D_SEND_PCIEHDR", 7331 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7332 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7333 "IDMA_FL_SEND_PCIEHDR", 7334 "IDMA_FL_PUSH_CPL_FIFO", 7335 "IDMA_FL_SEND_CPL", 7336 "IDMA_FL_SEND_PAYLOAD_FIRST", 7337 "IDMA_FL_SEND_PAYLOAD", 7338 "IDMA_FL_REQ_NEXT_DATA_FL", 7339 "IDMA_FL_SEND_NEXT_PCIEHDR", 7340 "IDMA_FL_SEND_PADDING", 7341 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7342 }; 7343 static const char * const t6_decode[] = { 7344 "IDMA_IDLE", 7345 "IDMA_PUSH_MORE_CPL_FIFO", 7346 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7347 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7348 "IDMA_PHYSADDR_SEND_PCIEHDR", 7349 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7350 "IDMA_PHYSADDR_SEND_PAYLOAD", 7351 "IDMA_FL_REQ_DATA_FL", 7352 "IDMA_FL_DROP", 7353 "IDMA_FL_DROP_SEND_INC", 7354 "IDMA_FL_H_REQ_HEADER_FL", 7355 "IDMA_FL_H_SEND_PCIEHDR", 7356 "IDMA_FL_H_PUSH_CPL_FIFO", 7357 "IDMA_FL_H_SEND_CPL", 7358 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7359 "IDMA_FL_H_SEND_IP_HDR", 7360 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7361 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7362 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7363 "IDMA_FL_D_SEND_PCIEHDR", 7364 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7365 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7366 "IDMA_FL_SEND_PCIEHDR", 7367 "IDMA_FL_PUSH_CPL_FIFO", 7368 "IDMA_FL_SEND_CPL", 7369 "IDMA_FL_SEND_PAYLOAD_FIRST", 7370 "IDMA_FL_SEND_PAYLOAD", 7371 "IDMA_FL_REQ_NEXT_DATA_FL", 7372 "IDMA_FL_SEND_NEXT_PCIEHDR", 7373 "IDMA_FL_SEND_PADDING", 7374 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7375 }; 7376 static const u32 sge_regs[] = { 7377 A_SGE_DEBUG_DATA_LOW_INDEX_2, 7378 A_SGE_DEBUG_DATA_LOW_INDEX_3, 7379 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 7380 }; 7381 const char * const *sge_idma_decode; 7382 int sge_idma_decode_nstates; 7383 int i; 7384 unsigned int chip_version = chip_id(adapter); 7385 7386 /* Select the right set of decode strings to dump depending on the 7387 * adapter chip type. 7388 */ 7389 switch (chip_version) { 7390 case CHELSIO_T4: 7391 sge_idma_decode = (const char * const *)t4_decode; 7392 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 7393 break; 7394 7395 case CHELSIO_T5: 7396 sge_idma_decode = (const char * const *)t5_decode; 7397 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 7398 break; 7399 7400 case CHELSIO_T6: 7401 sge_idma_decode = (const char * const *)t6_decode; 7402 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 7403 break; 7404 7405 default: 7406 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 7407 return; 7408 } 7409 7410 if (state < sge_idma_decode_nstates) 7411 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 7412 else 7413 CH_WARN(adapter, "idma state %d unknown\n", state); 7414 7415 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 7416 CH_WARN(adapter, "SGE register %#x value %#x\n", 7417 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 7418} 7419 7420/** 7421 * t4_sge_ctxt_flush - flush the SGE context cache 7422 * @adap: the adapter 7423 * @mbox: mailbox to use for the FW command 7424 * 7425 * Issues a FW command through the given mailbox to flush the 7426 * SGE context cache. 7427 */ 7428int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type) 7429{ 7430 int ret; 7431 u32 ldst_addrspace; 7432 struct fw_ldst_cmd c; 7433 7434 memset(&c, 0, sizeof(c)); 7435 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(ctxt_type == CTXT_EGRESS ? 7436 FW_LDST_ADDRSPC_SGE_EGRC : 7437 FW_LDST_ADDRSPC_SGE_INGC); 7438 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7439 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7440 ldst_addrspace); 7441 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7442 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 7443 7444 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7445 return ret; 7446} 7447 7448/** 7449 * t4_fw_hello - establish communication with FW 7450 * @adap: the adapter 7451 * @mbox: mailbox to use for the FW command 7452 * @evt_mbox: mailbox to receive async FW events 7453 * @master: specifies the caller's willingness to be the device master 7454 * @state: returns the current device state (if non-NULL) 7455 * 7456 * Issues a command to establish communication with FW. Returns either 7457 * an error (negative integer) or the mailbox of the Master PF. 7458 */ 7459int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 7460 enum dev_master master, enum dev_state *state) 7461{ 7462 int ret; 7463 struct fw_hello_cmd c; 7464 u32 v; 7465 unsigned int master_mbox; 7466 int retries = FW_CMD_HELLO_RETRIES; 7467 7468retry: 7469 memset(&c, 0, sizeof(c)); 7470 INIT_CMD(c, HELLO, WRITE); 7471 c.err_to_clearinit = cpu_to_be32( 7472 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 7473 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 7474 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 7475 mbox : M_FW_HELLO_CMD_MBMASTER) | 7476 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 7477 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 7478 F_FW_HELLO_CMD_CLEARINIT); 7479 7480 /* 7481 * Issue the HELLO command to the firmware. If it's not successful 7482 * but indicates that we got a "busy" or "timeout" condition, retry 7483 * the HELLO until we exhaust our retry limit. If we do exceed our 7484 * retry limit, check to see if the firmware left us any error 7485 * information and report that if so ... 7486 */ 7487 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7488 if (ret != FW_SUCCESS) { 7489 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 7490 goto retry; 7491 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 7492 t4_report_fw_error(adap); 7493 return ret; 7494 } 7495 7496 v = be32_to_cpu(c.err_to_clearinit); 7497 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 7498 if (state) { 7499 if (v & F_FW_HELLO_CMD_ERR) 7500 *state = DEV_STATE_ERR; 7501 else if (v & F_FW_HELLO_CMD_INIT) 7502 *state = DEV_STATE_INIT; 7503 else 7504 *state = DEV_STATE_UNINIT; 7505 } 7506 7507 /* 7508 * If we're not the Master PF then we need to wait around for the 7509 * Master PF Driver to finish setting up the adapter. 7510 * 7511 * Note that we also do this wait if we're a non-Master-capable PF and 7512 * there is no current Master PF; a Master PF may show up momentarily 7513 * and we wouldn't want to fail pointlessly. (This can happen when an 7514 * OS loads lots of different drivers rapidly at the same time). In 7515 * this case, the Master PF returned by the firmware will be 7516 * M_PCIE_FW_MASTER so the test below will work ... 7517 */ 7518 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 7519 master_mbox != mbox) { 7520 int waiting = FW_CMD_HELLO_TIMEOUT; 7521 7522 /* 7523 * Wait for the firmware to either indicate an error or 7524 * initialized state. If we see either of these we bail out 7525 * and report the issue to the caller. If we exhaust the 7526 * "hello timeout" and we haven't exhausted our retries, try 7527 * again. Otherwise bail with a timeout error. 7528 */ 7529 for (;;) { 7530 u32 pcie_fw; 7531 7532 msleep(50); 7533 waiting -= 50; 7534 7535 /* 7536 * If neither Error nor Initialialized are indicated 7537 * by the firmware keep waiting till we exhaust our 7538 * timeout ... and then retry if we haven't exhausted 7539 * our retries ... 7540 */ 7541 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 7542 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 7543 if (waiting <= 0) { 7544 if (retries-- > 0) 7545 goto retry; 7546 7547 return -ETIMEDOUT; 7548 } 7549 continue; 7550 } 7551 7552 /* 7553 * We either have an Error or Initialized condition 7554 * report errors preferentially. 7555 */ 7556 if (state) { 7557 if (pcie_fw & F_PCIE_FW_ERR) 7558 *state = DEV_STATE_ERR; 7559 else if (pcie_fw & F_PCIE_FW_INIT) 7560 *state = DEV_STATE_INIT; 7561 } 7562 7563 /* 7564 * If we arrived before a Master PF was selected and 7565 * there's not a valid Master PF, grab its identity 7566 * for our caller. 7567 */ 7568 if (master_mbox == M_PCIE_FW_MASTER && 7569 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 7570 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 7571 break; 7572 } 7573 } 7574 7575 return master_mbox; 7576} 7577 7578/** 7579 * t4_fw_bye - end communication with FW 7580 * @adap: the adapter 7581 * @mbox: mailbox to use for the FW command 7582 * 7583 * Issues a command to terminate communication with FW. 7584 */ 7585int t4_fw_bye(struct adapter *adap, unsigned int mbox) 7586{ 7587 struct fw_bye_cmd c; 7588 7589 memset(&c, 0, sizeof(c)); 7590 INIT_CMD(c, BYE, WRITE); 7591 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7592} 7593 7594/** 7595 * t4_fw_reset - issue a reset to FW 7596 * @adap: the adapter 7597 * @mbox: mailbox to use for the FW command 7598 * @reset: specifies the type of reset to perform 7599 * 7600 * Issues a reset command of the specified type to FW. 7601 */ 7602int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 7603{ 7604 struct fw_reset_cmd c; 7605 7606 memset(&c, 0, sizeof(c)); 7607 INIT_CMD(c, RESET, WRITE); 7608 c.val = cpu_to_be32(reset); 7609 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7610} 7611 7612/** 7613 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 7614 * @adap: the adapter 7615 * @mbox: mailbox to use for the FW RESET command (if desired) 7616 * @force: force uP into RESET even if FW RESET command fails 7617 * 7618 * Issues a RESET command to firmware (if desired) with a HALT indication 7619 * and then puts the microprocessor into RESET state. The RESET command 7620 * will only be issued if a legitimate mailbox is provided (mbox <= 7621 * M_PCIE_FW_MASTER). 7622 * 7623 * This is generally used in order for the host to safely manipulate the 7624 * adapter without fear of conflicting with whatever the firmware might 7625 * be doing. The only way out of this state is to RESTART the firmware 7626 * ... 7627 */ 7628int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 7629{ 7630 int ret = 0; 7631 7632 /* 7633 * If a legitimate mailbox is provided, issue a RESET command 7634 * with a HALT indication. 7635 */ 7636 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) { 7637 struct fw_reset_cmd c; 7638 7639 memset(&c, 0, sizeof(c)); 7640 INIT_CMD(c, RESET, WRITE); 7641 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 7642 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 7643 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7644 } 7645 7646 /* 7647 * Normally we won't complete the operation if the firmware RESET 7648 * command fails but if our caller insists we'll go ahead and put the 7649 * uP into RESET. This can be useful if the firmware is hung or even 7650 * missing ... We'll have to take the risk of putting the uP into 7651 * RESET without the cooperation of firmware in that case. 7652 * 7653 * We also force the firmware's HALT flag to be on in case we bypassed 7654 * the firmware RESET command above or we're dealing with old firmware 7655 * which doesn't have the HALT capability. This will serve as a flag 7656 * for the incoming firmware to know that it's coming out of a HALT 7657 * rather than a RESET ... if it's new enough to understand that ... 7658 */ 7659 if (ret == 0 || force) { 7660 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 7661 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 7662 F_PCIE_FW_HALT); 7663 } 7664 7665 /* 7666 * And we always return the result of the firmware RESET command 7667 * even when we force the uP into RESET ... 7668 */ 7669 return ret; 7670} 7671 7672/** 7673 * t4_fw_restart - restart the firmware by taking the uP out of RESET 7674 * @adap: the adapter 7675 * 7676 * Restart firmware previously halted by t4_fw_halt(). On successful 7677 * return the previous PF Master remains as the new PF Master and there 7678 * is no need to issue a new HELLO command, etc. 7679 */ 7680int t4_fw_restart(struct adapter *adap, unsigned int mbox) 7681{ 7682 int ms; 7683 7684 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 7685 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 7686 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 7687 return FW_SUCCESS; 7688 msleep(100); 7689 ms += 100; 7690 } 7691 7692 return -ETIMEDOUT; 7693} 7694 7695/** 7696 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 7697 * @adap: the adapter 7698 * @mbox: mailbox to use for the FW RESET command (if desired) 7699 * @fw_data: the firmware image to write 7700 * @size: image size 7701 * @force: force upgrade even if firmware doesn't cooperate 7702 * 7703 * Perform all of the steps necessary for upgrading an adapter's 7704 * firmware image. Normally this requires the cooperation of the 7705 * existing firmware in order to halt all existing activities 7706 * but if an invalid mailbox token is passed in we skip that step 7707 * (though we'll still put the adapter microprocessor into RESET in 7708 * that case). 7709 * 7710 * On successful return the new firmware will have been loaded and 7711 * the adapter will have been fully RESET losing all previous setup 7712 * state. On unsuccessful return the adapter may be completely hosed ... 7713 * positive errno indicates that the adapter is ~probably~ intact, a 7714 * negative errno indicates that things are looking bad ... 7715 */ 7716int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 7717 const u8 *fw_data, unsigned int size, int force) 7718{ 7719 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 7720 unsigned int bootstrap = 7721 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 7722 int ret; 7723 7724 if (!t4_fw_matches_chip(adap, fw_hdr)) 7725 return -EINVAL; 7726 7727 if (!bootstrap) { 7728 ret = t4_fw_halt(adap, mbox, force); 7729 if (ret < 0 && !force) 7730 return ret; 7731 } 7732 7733 ret = t4_load_fw(adap, fw_data, size); 7734 if (ret < 0 || bootstrap) 7735 return ret; 7736 7737 return t4_fw_restart(adap, mbox); 7738} 7739 7740/** 7741 * t4_fw_initialize - ask FW to initialize the device 7742 * @adap: the adapter 7743 * @mbox: mailbox to use for the FW command 7744 * 7745 * Issues a command to FW to partially initialize the device. This 7746 * performs initialization that generally doesn't depend on user input. 7747 */ 7748int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 7749{ 7750 struct fw_initialize_cmd c; 7751 7752 memset(&c, 0, sizeof(c)); 7753 INIT_CMD(c, INITIALIZE, WRITE); 7754 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7755} 7756 7757/** 7758 * t4_query_params_rw - query FW or device parameters 7759 * @adap: the adapter 7760 * @mbox: mailbox to use for the FW command 7761 * @pf: the PF 7762 * @vf: the VF 7763 * @nparams: the number of parameters 7764 * @params: the parameter names 7765 * @val: the parameter values 7766 * @rw: Write and read flag 7767 * 7768 * Reads the value of FW or device parameters. Up to 7 parameters can be 7769 * queried at once. 7770 */ 7771int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 7772 unsigned int vf, unsigned int nparams, const u32 *params, 7773 u32 *val, int rw) 7774{ 7775 int i, ret; 7776 struct fw_params_cmd c; 7777 __be32 *p = &c.param[0].mnem; 7778 7779 if (nparams > 7) 7780 return -EINVAL; 7781 7782 memset(&c, 0, sizeof(c)); 7783 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7784 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7785 V_FW_PARAMS_CMD_PFN(pf) | 7786 V_FW_PARAMS_CMD_VFN(vf)); 7787 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7788 7789 for (i = 0; i < nparams; i++) { 7790 *p++ = cpu_to_be32(*params++); 7791 if (rw) 7792 *p = cpu_to_be32(*(val + i)); 7793 p++; 7794 } 7795 7796 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7797 if (ret == 0) 7798 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 7799 *val++ = be32_to_cpu(*p); 7800 return ret; 7801} 7802 7803int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7804 unsigned int vf, unsigned int nparams, const u32 *params, 7805 u32 *val) 7806{ 7807 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 7808} 7809 7810/** 7811 * t4_set_params_timeout - sets FW or device parameters 7812 * @adap: the adapter 7813 * @mbox: mailbox to use for the FW command 7814 * @pf: the PF 7815 * @vf: the VF 7816 * @nparams: the number of parameters 7817 * @params: the parameter names 7818 * @val: the parameter values 7819 * @timeout: the timeout time 7820 * 7821 * Sets the value of FW or device parameters. Up to 7 parameters can be 7822 * specified at once. 7823 */ 7824int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 7825 unsigned int pf, unsigned int vf, 7826 unsigned int nparams, const u32 *params, 7827 const u32 *val, int timeout) 7828{ 7829 struct fw_params_cmd c; 7830 __be32 *p = &c.param[0].mnem; 7831 7832 if (nparams > 7) 7833 return -EINVAL; 7834 7835 memset(&c, 0, sizeof(c)); 7836 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7837 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7838 V_FW_PARAMS_CMD_PFN(pf) | 7839 V_FW_PARAMS_CMD_VFN(vf)); 7840 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7841 7842 while (nparams--) { 7843 *p++ = cpu_to_be32(*params++); 7844 *p++ = cpu_to_be32(*val++); 7845 } 7846 7847 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7848} 7849 7850/** 7851 * t4_set_params - sets FW or device parameters 7852 * @adap: the adapter 7853 * @mbox: mailbox to use for the FW command 7854 * @pf: the PF 7855 * @vf: the VF 7856 * @nparams: the number of parameters 7857 * @params: the parameter names 7858 * @val: the parameter values 7859 * 7860 * Sets the value of FW or device parameters. Up to 7 parameters can be 7861 * specified at once. 7862 */ 7863int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7864 unsigned int vf, unsigned int nparams, const u32 *params, 7865 const u32 *val) 7866{ 7867 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7868 FW_CMD_MAX_TIMEOUT); 7869} 7870 7871/** 7872 * t4_cfg_pfvf - configure PF/VF resource limits 7873 * @adap: the adapter 7874 * @mbox: mailbox to use for the FW command 7875 * @pf: the PF being configured 7876 * @vf: the VF being configured 7877 * @txq: the max number of egress queues 7878 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7879 * @rxqi: the max number of interrupt-capable ingress queues 7880 * @rxq: the max number of interruptless ingress queues 7881 * @tc: the PCI traffic class 7882 * @vi: the max number of virtual interfaces 7883 * @cmask: the channel access rights mask for the PF/VF 7884 * @pmask: the port access rights mask for the PF/VF 7885 * @nexact: the maximum number of exact MPS filters 7886 * @rcaps: read capabilities 7887 * @wxcaps: write/execute capabilities 7888 * 7889 * Configures resource limits and capabilities for a physical or virtual 7890 * function. 7891 */ 7892int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7893 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7894 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7895 unsigned int vi, unsigned int cmask, unsigned int pmask, 7896 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7897{ 7898 struct fw_pfvf_cmd c; 7899 7900 memset(&c, 0, sizeof(c)); 7901 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7902 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7903 V_FW_PFVF_CMD_VFN(vf)); 7904 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7905 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7906 V_FW_PFVF_CMD_NIQ(rxq)); 7907 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7908 V_FW_PFVF_CMD_PMASK(pmask) | 7909 V_FW_PFVF_CMD_NEQ(txq)); 7910 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7911 V_FW_PFVF_CMD_NVI(vi) | 7912 V_FW_PFVF_CMD_NEXACTF(nexact)); 7913 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7914 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7915 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7916 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7917} 7918 7919/** 7920 * t4_alloc_vi_func - allocate a virtual interface 7921 * @adap: the adapter 7922 * @mbox: mailbox to use for the FW command 7923 * @port: physical port associated with the VI 7924 * @pf: the PF owning the VI 7925 * @vf: the VF owning the VI 7926 * @nmac: number of MAC addresses needed (1 to 5) 7927 * @mac: the MAC addresses of the VI 7928 * @rss_size: size of RSS table slice associated with this VI 7929 * @portfunc: which Port Application Function MAC Address is desired 7930 * @idstype: Intrusion Detection Type 7931 * 7932 * Allocates a virtual interface for the given physical port. If @mac is 7933 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7934 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7935 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7936 * stored consecutively so the space needed is @nmac * 6 bytes. 7937 * Returns a negative error number or the non-negative VI id. 7938 */ 7939int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7940 unsigned int port, unsigned int pf, unsigned int vf, 7941 unsigned int nmac, u8 *mac, u16 *rss_size, 7942 uint8_t *vfvld, uint16_t *vin, 7943 unsigned int portfunc, unsigned int idstype) 7944{ 7945 int ret; 7946 struct fw_vi_cmd c; 7947 7948 memset(&c, 0, sizeof(c)); 7949 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7950 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7951 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7952 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7953 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7954 V_FW_VI_CMD_FUNC(portfunc)); 7955 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7956 c.nmac = nmac - 1; 7957 if(!rss_size) 7958 c.norss_rsssize = F_FW_VI_CMD_NORSS; 7959 7960 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7961 if (ret) 7962 return ret; 7963 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 7964 7965 if (mac) { 7966 memcpy(mac, c.mac, sizeof(c.mac)); 7967 switch (nmac) { 7968 case 5: 7969 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 7970 case 4: 7971 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 7972 case 3: 7973 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 7974 case 2: 7975 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 7976 } 7977 } 7978 if (rss_size) 7979 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 7980 if (vfvld) { 7981 *vfvld = adap->params.viid_smt_extn_support ? 7982 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) : 7983 G_FW_VIID_VIVLD(ret); 7984 } 7985 if (vin) { 7986 *vin = adap->params.viid_smt_extn_support ? 7987 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) : 7988 G_FW_VIID_VIN(ret); 7989 } 7990 7991 return ret; 7992} 7993 7994/** 7995 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 7996 * @adap: the adapter 7997 * @mbox: mailbox to use for the FW command 7998 * @port: physical port associated with the VI 7999 * @pf: the PF owning the VI 8000 * @vf: the VF owning the VI 8001 * @nmac: number of MAC addresses needed (1 to 5) 8002 * @mac: the MAC addresses of the VI 8003 * @rss_size: size of RSS table slice associated with this VI 8004 * 8005 * backwards compatible and convieniance routine to allocate a Virtual 8006 * Interface with a Ethernet Port Application Function and Intrustion 8007 * Detection System disabled. 8008 */ 8009int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 8010 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 8011 u16 *rss_size, uint8_t *vfvld, uint16_t *vin) 8012{ 8013 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 8014 vfvld, vin, FW_VI_FUNC_ETH, 0); 8015} 8016 8017/** 8018 * t4_free_vi - free a virtual interface 8019 * @adap: the adapter 8020 * @mbox: mailbox to use for the FW command 8021 * @pf: the PF owning the VI 8022 * @vf: the VF owning the VI 8023 * @viid: virtual interface identifiler 8024 * 8025 * Free a previously allocated virtual interface. 8026 */ 8027int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 8028 unsigned int vf, unsigned int viid) 8029{ 8030 struct fw_vi_cmd c; 8031 8032 memset(&c, 0, sizeof(c)); 8033 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 8034 F_FW_CMD_REQUEST | 8035 F_FW_CMD_EXEC | 8036 V_FW_VI_CMD_PFN(pf) | 8037 V_FW_VI_CMD_VFN(vf)); 8038 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 8039 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 8040 8041 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8042} 8043 8044/** 8045 * t4_set_rxmode - set Rx properties of a virtual interface 8046 * @adap: the adapter 8047 * @mbox: mailbox to use for the FW command 8048 * @viid: the VI id 8049 * @mtu: the new MTU or -1 8050 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 8051 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 8052 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 8053 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 8054 * @sleep_ok: if true we may sleep while awaiting command completion 8055 * 8056 * Sets Rx properties of a virtual interface. 8057 */ 8058int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 8059 int mtu, int promisc, int all_multi, int bcast, int vlanex, 8060 bool sleep_ok) 8061{ 8062 struct fw_vi_rxmode_cmd c; 8063 8064 /* convert to FW values */ 8065 if (mtu < 0) 8066 mtu = M_FW_VI_RXMODE_CMD_MTU; 8067 if (promisc < 0) 8068 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 8069 if (all_multi < 0) 8070 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 8071 if (bcast < 0) 8072 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 8073 if (vlanex < 0) 8074 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 8075 8076 memset(&c, 0, sizeof(c)); 8077 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 8078 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8079 V_FW_VI_RXMODE_CMD_VIID(viid)); 8080 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 8081 c.mtu_to_vlanexen = 8082 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 8083 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 8084 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 8085 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 8086 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 8087 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8088} 8089 8090/** 8091 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support 8092 * @adap: the adapter 8093 * @viid: the VI id 8094 * @mac: the MAC address 8095 * @mask: the mask 8096 * @vni: the VNI id for the tunnel protocol 8097 * @vni_mask: mask for the VNI id 8098 * @dip_hit: to enable DIP match for the MPS entry 8099 * @lookup_type: MAC address for inner (1) or outer (0) header 8100 * @sleep_ok: call is allowed to sleep 8101 * 8102 * Allocates an MPS entry with specified MAC address and VNI value. 8103 * 8104 * Returns a negative error number or the allocated index for this mac. 8105 */ 8106int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 8107 const u8 *addr, const u8 *mask, unsigned int vni, 8108 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 8109 bool sleep_ok) 8110{ 8111 struct fw_vi_mac_cmd c; 8112 struct fw_vi_mac_vni *p = c.u.exact_vni; 8113 int ret = 0; 8114 u32 val; 8115 8116 memset(&c, 0, sizeof(c)); 8117 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8118 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8119 V_FW_VI_MAC_CMD_VIID(viid)); 8120 val = V_FW_CMD_LEN16(1) | 8121 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC_VNI); 8122 c.freemacs_to_len16 = cpu_to_be32(val); 8123 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8124 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8125 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8126 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask)); 8127 8128 p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) | 8129 V_FW_VI_MAC_CMD_DIP_HIT(dip_hit) | 8130 V_FW_VI_MAC_CMD_LOOKUP_TYPE(lookup_type)); 8131 p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask)); 8132 8133 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8134 if (ret == 0) 8135 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8136 return ret; 8137} 8138 8139/** 8140 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam 8141 * @adap: the adapter 8142 * @viid: the VI id 8143 * @mac: the MAC address 8144 * @mask: the mask 8145 * @idx: index at which to add this entry 8146 * @port_id: the port index 8147 * @lookup_type: MAC address for inner (1) or outer (0) header 8148 * @sleep_ok: call is allowed to sleep 8149 * 8150 * Adds the mac entry at the specified index using raw mac interface. 8151 * 8152 * Returns a negative error number or the allocated index for this mac. 8153 */ 8154int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 8155 const u8 *addr, const u8 *mask, unsigned int idx, 8156 u8 lookup_type, u8 port_id, bool sleep_ok) 8157{ 8158 int ret = 0; 8159 struct fw_vi_mac_cmd c; 8160 struct fw_vi_mac_raw *p = &c.u.raw; 8161 u32 val; 8162 8163 memset(&c, 0, sizeof(c)); 8164 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8165 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8166 V_FW_VI_MAC_CMD_VIID(viid)); 8167 val = V_FW_CMD_LEN16(1) | 8168 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8169 c.freemacs_to_len16 = cpu_to_be32(val); 8170 8171 /* Specify that this is an inner mac address */ 8172 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx)); 8173 8174 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8175 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8176 V_DATAPORTNUM(port_id)); 8177 /* Lookup mask and port mask */ 8178 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8179 V_DATAPORTNUM(M_DATAPORTNUM)); 8180 8181 /* Copy the address and the mask */ 8182 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8183 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8184 8185 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8186 if (ret == 0) { 8187 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd)); 8188 if (ret != idx) 8189 ret = -ENOMEM; 8190 } 8191 8192 return ret; 8193} 8194 8195/** 8196 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 8197 * @adap: the adapter 8198 * @mbox: mailbox to use for the FW command 8199 * @viid: the VI id 8200 * @free: if true any existing filters for this VI id are first removed 8201 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8202 * @addr: the MAC address(es) 8203 * @idx: where to store the index of each allocated filter 8204 * @hash: pointer to hash address filter bitmap 8205 * @sleep_ok: call is allowed to sleep 8206 * 8207 * Allocates an exact-match filter for each of the supplied addresses and 8208 * sets it to the corresponding address. If @idx is not %NULL it should 8209 * have at least @naddr entries, each of which will be set to the index of 8210 * the filter allocated for the corresponding MAC address. If a filter 8211 * could not be allocated for an address its index is set to 0xffff. 8212 * If @hash is not %NULL addresses that fail to allocate an exact filter 8213 * are hashed and update the hash filter bitmap pointed at by @hash. 8214 * 8215 * Returns a negative error number or the number of filters allocated. 8216 */ 8217int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 8218 unsigned int viid, bool free, unsigned int naddr, 8219 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 8220{ 8221 int offset, ret = 0; 8222 struct fw_vi_mac_cmd c; 8223 unsigned int nfilters = 0; 8224 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8225 unsigned int rem = naddr; 8226 8227 if (naddr > max_naddr) 8228 return -EINVAL; 8229 8230 for (offset = 0; offset < naddr ; /**/) { 8231 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8232 ? rem 8233 : ARRAY_SIZE(c.u.exact)); 8234 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8235 u.exact[fw_naddr]), 16); 8236 struct fw_vi_mac_exact *p; 8237 int i; 8238 8239 memset(&c, 0, sizeof(c)); 8240 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8241 F_FW_CMD_REQUEST | 8242 F_FW_CMD_WRITE | 8243 V_FW_CMD_EXEC(free) | 8244 V_FW_VI_MAC_CMD_VIID(viid)); 8245 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 8246 V_FW_CMD_LEN16(len16)); 8247 8248 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8249 p->valid_to_idx = 8250 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8251 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8252 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8253 } 8254 8255 /* 8256 * It's okay if we run out of space in our MAC address arena. 8257 * Some of the addresses we submit may get stored so we need 8258 * to run through the reply to see what the results were ... 8259 */ 8260 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8261 if (ret && ret != -FW_ENOMEM) 8262 break; 8263 8264 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8265 u16 index = G_FW_VI_MAC_CMD_IDX( 8266 be16_to_cpu(p->valid_to_idx)); 8267 8268 if (idx) 8269 idx[offset+i] = (index >= max_naddr 8270 ? 0xffff 8271 : index); 8272 if (index < max_naddr) 8273 nfilters++; 8274 else if (hash) 8275 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 8276 } 8277 8278 free = false; 8279 offset += fw_naddr; 8280 rem -= fw_naddr; 8281 } 8282 8283 if (ret == 0 || ret == -FW_ENOMEM) 8284 ret = nfilters; 8285 return ret; 8286} 8287 8288/** 8289 * t4_free_encap_mac_filt - frees MPS entry at given index 8290 * @adap: the adapter 8291 * @viid: the VI id 8292 * @idx: index of MPS entry to be freed 8293 * @sleep_ok: call is allowed to sleep 8294 * 8295 * Frees the MPS entry at supplied index 8296 * 8297 * Returns a negative error number or zero on success 8298 */ 8299int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 8300 int idx, bool sleep_ok) 8301{ 8302 struct fw_vi_mac_exact *p; 8303 struct fw_vi_mac_cmd c; 8304 u8 addr[] = {0,0,0,0,0,0}; 8305 int ret = 0; 8306 u32 exact; 8307 8308 memset(&c, 0, sizeof(c)); 8309 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8310 F_FW_CMD_REQUEST | 8311 F_FW_CMD_WRITE | 8312 V_FW_CMD_EXEC(0) | 8313 V_FW_VI_MAC_CMD_VIID(viid)); 8314 exact = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC); 8315 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8316 exact | 8317 V_FW_CMD_LEN16(1)); 8318 p = c.u.exact; 8319 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8320 V_FW_VI_MAC_CMD_IDX(idx)); 8321 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8322 8323 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8324 return ret; 8325} 8326 8327/** 8328 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam 8329 * @adap: the adapter 8330 * @viid: the VI id 8331 * @addr: the MAC address 8332 * @mask: the mask 8333 * @idx: index of the entry in mps tcam 8334 * @lookup_type: MAC address for inner (1) or outer (0) header 8335 * @port_id: the port index 8336 * @sleep_ok: call is allowed to sleep 8337 * 8338 * Removes the mac entry at the specified index using raw mac interface. 8339 * 8340 * Returns a negative error number on failure. 8341 */ 8342int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 8343 const u8 *addr, const u8 *mask, unsigned int idx, 8344 u8 lookup_type, u8 port_id, bool sleep_ok) 8345{ 8346 struct fw_vi_mac_cmd c; 8347 struct fw_vi_mac_raw *p = &c.u.raw; 8348 u32 raw; 8349 8350 memset(&c, 0, sizeof(c)); 8351 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8352 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8353 V_FW_CMD_EXEC(0) | 8354 V_FW_VI_MAC_CMD_VIID(viid)); 8355 raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8356 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8357 raw | 8358 V_FW_CMD_LEN16(1)); 8359 8360 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) | 8361 FW_VI_MAC_ID_BASED_FREE); 8362 8363 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8364 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8365 V_DATAPORTNUM(port_id)); 8366 /* Lookup mask and port mask */ 8367 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8368 V_DATAPORTNUM(M_DATAPORTNUM)); 8369 8370 /* Copy the address and the mask */ 8371 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8372 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8373 8374 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8375} 8376 8377/** 8378 * t4_free_mac_filt - frees exact-match filters of given MAC addresses 8379 * @adap: the adapter 8380 * @mbox: mailbox to use for the FW command 8381 * @viid: the VI id 8382 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8383 * @addr: the MAC address(es) 8384 * @sleep_ok: call is allowed to sleep 8385 * 8386 * Frees the exact-match filter for each of the supplied addresses 8387 * 8388 * Returns a negative error number or the number of filters freed. 8389 */ 8390int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 8391 unsigned int viid, unsigned int naddr, 8392 const u8 **addr, bool sleep_ok) 8393{ 8394 int offset, ret = 0; 8395 struct fw_vi_mac_cmd c; 8396 unsigned int nfilters = 0; 8397 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8398 unsigned int rem = naddr; 8399 8400 if (naddr > max_naddr) 8401 return -EINVAL; 8402 8403 for (offset = 0; offset < (int)naddr ; /**/) { 8404 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8405 ? rem 8406 : ARRAY_SIZE(c.u.exact)); 8407 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8408 u.exact[fw_naddr]), 16); 8409 struct fw_vi_mac_exact *p; 8410 int i; 8411 8412 memset(&c, 0, sizeof(c)); 8413 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8414 F_FW_CMD_REQUEST | 8415 F_FW_CMD_WRITE | 8416 V_FW_CMD_EXEC(0) | 8417 V_FW_VI_MAC_CMD_VIID(viid)); 8418 c.freemacs_to_len16 = 8419 cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8420 V_FW_CMD_LEN16(len16)); 8421 8422 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) { 8423 p->valid_to_idx = cpu_to_be16( 8424 F_FW_VI_MAC_CMD_VALID | 8425 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 8426 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8427 } 8428 8429 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8430 if (ret) 8431 break; 8432 8433 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8434 u16 index = G_FW_VI_MAC_CMD_IDX( 8435 be16_to_cpu(p->valid_to_idx)); 8436 8437 if (index < max_naddr) 8438 nfilters++; 8439 } 8440 8441 offset += fw_naddr; 8442 rem -= fw_naddr; 8443 } 8444 8445 if (ret == 0) 8446 ret = nfilters; 8447 return ret; 8448} 8449 8450/** 8451 * t4_change_mac - modifies the exact-match filter for a MAC address 8452 * @adap: the adapter 8453 * @mbox: mailbox to use for the FW command 8454 * @viid: the VI id 8455 * @idx: index of existing filter for old value of MAC address, or -1 8456 * @addr: the new MAC address value 8457 * @persist: whether a new MAC allocation should be persistent 8458 * @smt_idx: add MAC to SMT and return its index, or NULL 8459 * 8460 * Modifies an exact-match filter and sets it to the new MAC address if 8461 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 8462 * latter case the address is added persistently if @persist is %true. 8463 * 8464 * Note that in general it is not possible to modify the value of a given 8465 * filter so the generic way to modify an address filter is to free the one 8466 * being used by the old address value and allocate a new filter for the 8467 * new address value. 8468 * 8469 * Returns a negative error number or the index of the filter with the new 8470 * MAC value. Note that this index may differ from @idx. 8471 */ 8472int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 8473 int idx, const u8 *addr, bool persist, uint16_t *smt_idx) 8474{ 8475 int ret, mode; 8476 struct fw_vi_mac_cmd c; 8477 struct fw_vi_mac_exact *p = c.u.exact; 8478 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 8479 8480 if (idx < 0) /* new allocation */ 8481 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 8482 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 8483 8484 memset(&c, 0, sizeof(c)); 8485 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8486 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8487 V_FW_VI_MAC_CMD_VIID(viid)); 8488 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 8489 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8490 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 8491 V_FW_VI_MAC_CMD_IDX(idx)); 8492 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8493 8494 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8495 if (ret == 0) { 8496 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8497 if (ret >= max_mac_addr) 8498 ret = -ENOMEM; 8499 if (smt_idx) { 8500 if (adap->params.viid_smt_extn_support) 8501 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 8502 else { 8503 if (chip_id(adap) <= CHELSIO_T5) 8504 *smt_idx = (viid & M_FW_VIID_VIN) << 1; 8505 else 8506 *smt_idx = viid & M_FW_VIID_VIN; 8507 } 8508 } 8509 } 8510 return ret; 8511} 8512 8513/** 8514 * t4_set_addr_hash - program the MAC inexact-match hash filter 8515 * @adap: the adapter 8516 * @mbox: mailbox to use for the FW command 8517 * @viid: the VI id 8518 * @ucast: whether the hash filter should also match unicast addresses 8519 * @vec: the value to be written to the hash filter 8520 * @sleep_ok: call is allowed to sleep 8521 * 8522 * Sets the 64-bit inexact-match hash filter for a virtual interface. 8523 */ 8524int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 8525 bool ucast, u64 vec, bool sleep_ok) 8526{ 8527 struct fw_vi_mac_cmd c; 8528 u32 val; 8529 8530 memset(&c, 0, sizeof(c)); 8531 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8532 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8533 V_FW_VI_ENABLE_CMD_VIID(viid)); 8534 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 8535 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 8536 c.freemacs_to_len16 = cpu_to_be32(val); 8537 c.u.hash.hashvec = cpu_to_be64(vec); 8538 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8539} 8540 8541/** 8542 * t4_enable_vi_params - enable/disable a virtual interface 8543 * @adap: the adapter 8544 * @mbox: mailbox to use for the FW command 8545 * @viid: the VI id 8546 * @rx_en: 1=enable Rx, 0=disable Rx 8547 * @tx_en: 1=enable Tx, 0=disable Tx 8548 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 8549 * 8550 * Enables/disables a virtual interface. Note that setting DCB Enable 8551 * only makes sense when enabling a Virtual Interface ... 8552 */ 8553int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 8554 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 8555{ 8556 struct fw_vi_enable_cmd c; 8557 8558 memset(&c, 0, sizeof(c)); 8559 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8560 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8561 V_FW_VI_ENABLE_CMD_VIID(viid)); 8562 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 8563 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 8564 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 8565 FW_LEN16(c)); 8566 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 8567} 8568 8569/** 8570 * t4_enable_vi - enable/disable a virtual interface 8571 * @adap: the adapter 8572 * @mbox: mailbox to use for the FW command 8573 * @viid: the VI id 8574 * @rx_en: 1=enable Rx, 0=disable Rx 8575 * @tx_en: 1=enable Tx, 0=disable Tx 8576 * 8577 * Enables/disables a virtual interface. Note that setting DCB Enable 8578 * only makes sense when enabling a Virtual Interface ... 8579 */ 8580int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 8581 bool rx_en, bool tx_en) 8582{ 8583 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 8584} 8585 8586/** 8587 * t4_identify_port - identify a VI's port by blinking its LED 8588 * @adap: the adapter 8589 * @mbox: mailbox to use for the FW command 8590 * @viid: the VI id 8591 * @nblinks: how many times to blink LED at 2.5 Hz 8592 * 8593 * Identifies a VI's port by blinking its LED. 8594 */ 8595int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 8596 unsigned int nblinks) 8597{ 8598 struct fw_vi_enable_cmd c; 8599 8600 memset(&c, 0, sizeof(c)); 8601 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8602 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8603 V_FW_VI_ENABLE_CMD_VIID(viid)); 8604 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 8605 c.blinkdur = cpu_to_be16(nblinks); 8606 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8607} 8608 8609/** 8610 * t4_iq_stop - stop an ingress queue and its FLs 8611 * @adap: the adapter 8612 * @mbox: mailbox to use for the FW command 8613 * @pf: the PF owning the queues 8614 * @vf: the VF owning the queues 8615 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8616 * @iqid: ingress queue id 8617 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8618 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8619 * 8620 * Stops an ingress queue and its associated FLs, if any. This causes 8621 * any current or future data/messages destined for these queues to be 8622 * tossed. 8623 */ 8624int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8625 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8626 unsigned int fl0id, unsigned int fl1id) 8627{ 8628 struct fw_iq_cmd c; 8629 8630 memset(&c, 0, sizeof(c)); 8631 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8632 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8633 V_FW_IQ_CMD_VFN(vf)); 8634 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 8635 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8636 c.iqid = cpu_to_be16(iqid); 8637 c.fl0id = cpu_to_be16(fl0id); 8638 c.fl1id = cpu_to_be16(fl1id); 8639 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8640} 8641 8642/** 8643 * t4_iq_free - free an ingress queue and its FLs 8644 * @adap: the adapter 8645 * @mbox: mailbox to use for the FW command 8646 * @pf: the PF owning the queues 8647 * @vf: the VF owning the queues 8648 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8649 * @iqid: ingress queue id 8650 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8651 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8652 * 8653 * Frees an ingress queue and its associated FLs, if any. 8654 */ 8655int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8656 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8657 unsigned int fl0id, unsigned int fl1id) 8658{ 8659 struct fw_iq_cmd c; 8660 8661 memset(&c, 0, sizeof(c)); 8662 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8663 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8664 V_FW_IQ_CMD_VFN(vf)); 8665 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 8666 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8667 c.iqid = cpu_to_be16(iqid); 8668 c.fl0id = cpu_to_be16(fl0id); 8669 c.fl1id = cpu_to_be16(fl1id); 8670 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8671} 8672 8673/** 8674 * t4_eth_eq_stop - stop an Ethernet egress queue 8675 * @adap: the adapter 8676 * @mbox: mailbox to use for the FW command 8677 * @pf: the PF owning the queues 8678 * @vf: the VF owning the queues 8679 * @eqid: egress queue id 8680 * 8681 * Stops an Ethernet egress queue. The queue can be reinitialized or 8682 * freed but is not otherwise functional after this call. 8683 */ 8684int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8685 unsigned int vf, unsigned int eqid) 8686{ 8687 struct fw_eq_eth_cmd c; 8688 8689 memset(&c, 0, sizeof(c)); 8690 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8691 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8692 V_FW_EQ_ETH_CMD_PFN(pf) | 8693 V_FW_EQ_ETH_CMD_VFN(vf)); 8694 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_EQSTOP | FW_LEN16(c)); 8695 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8696 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8697} 8698 8699/** 8700 * t4_eth_eq_free - free an Ethernet egress queue 8701 * @adap: the adapter 8702 * @mbox: mailbox to use for the FW command 8703 * @pf: the PF owning the queue 8704 * @vf: the VF owning the queue 8705 * @eqid: egress queue id 8706 * 8707 * Frees an Ethernet egress queue. 8708 */ 8709int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8710 unsigned int vf, unsigned int eqid) 8711{ 8712 struct fw_eq_eth_cmd c; 8713 8714 memset(&c, 0, sizeof(c)); 8715 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8716 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8717 V_FW_EQ_ETH_CMD_PFN(pf) | 8718 V_FW_EQ_ETH_CMD_VFN(vf)); 8719 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 8720 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8721 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8722} 8723 8724/** 8725 * t4_ctrl_eq_free - free a control egress queue 8726 * @adap: the adapter 8727 * @mbox: mailbox to use for the FW command 8728 * @pf: the PF owning the queue 8729 * @vf: the VF owning the queue 8730 * @eqid: egress queue id 8731 * 8732 * Frees a control egress queue. 8733 */ 8734int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8735 unsigned int vf, unsigned int eqid) 8736{ 8737 struct fw_eq_ctrl_cmd c; 8738 8739 memset(&c, 0, sizeof(c)); 8740 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 8741 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8742 V_FW_EQ_CTRL_CMD_PFN(pf) | 8743 V_FW_EQ_CTRL_CMD_VFN(vf)); 8744 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 8745 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 8746 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8747} 8748 8749/** 8750 * t4_ofld_eq_free - free an offload egress queue 8751 * @adap: the adapter 8752 * @mbox: mailbox to use for the FW command 8753 * @pf: the PF owning the queue 8754 * @vf: the VF owning the queue 8755 * @eqid: egress queue id 8756 * 8757 * Frees a control egress queue. 8758 */ 8759int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8760 unsigned int vf, unsigned int eqid) 8761{ 8762 struct fw_eq_ofld_cmd c; 8763 8764 memset(&c, 0, sizeof(c)); 8765 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 8766 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8767 V_FW_EQ_OFLD_CMD_PFN(pf) | 8768 V_FW_EQ_OFLD_CMD_VFN(vf)); 8769 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 8770 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 8771 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8772} 8773 8774/** 8775 * t4_link_down_rc_str - return a string for a Link Down Reason Code 8776 * @link_down_rc: Link Down Reason Code 8777 * 8778 * Returns a string representation of the Link Down Reason Code. 8779 */ 8780const char *t4_link_down_rc_str(unsigned char link_down_rc) 8781{ 8782 static const char *reason[] = { 8783 "Link Down", 8784 "Remote Fault", 8785 "Auto-negotiation Failure", 8786 "Reserved3", 8787 "Insufficient Airflow", 8788 "Unable To Determine Reason", 8789 "No RX Signal Detected", 8790 "Reserved7", 8791 }; 8792 8793 if (link_down_rc >= ARRAY_SIZE(reason)) 8794 return "Bad Reason Code"; 8795 8796 return reason[link_down_rc]; 8797} 8798 8799/* 8800 * Return the highest speed set in the port capabilities, in Mb/s. 8801 */ 8802unsigned int fwcap_to_speed(uint32_t caps) 8803{ 8804 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8805 do { \ 8806 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8807 return __speed; \ 8808 } while (0) 8809 8810 TEST_SPEED_RETURN(400G, 400000); 8811 TEST_SPEED_RETURN(200G, 200000); 8812 TEST_SPEED_RETURN(100G, 100000); 8813 TEST_SPEED_RETURN(50G, 50000); 8814 TEST_SPEED_RETURN(40G, 40000); 8815 TEST_SPEED_RETURN(25G, 25000); 8816 TEST_SPEED_RETURN(10G, 10000); 8817 TEST_SPEED_RETURN(1G, 1000); 8818 TEST_SPEED_RETURN(100M, 100); 8819 8820 #undef TEST_SPEED_RETURN 8821 8822 return 0; 8823} 8824 8825/* 8826 * Return the port capabilities bit for the given speed, which is in Mb/s. 8827 */ 8828uint32_t speed_to_fwcap(unsigned int speed) 8829{ 8830 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8831 do { \ 8832 if (speed == __speed) \ 8833 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8834 } while (0) 8835 8836 TEST_SPEED_RETURN(400G, 400000); 8837 TEST_SPEED_RETURN(200G, 200000); 8838 TEST_SPEED_RETURN(100G, 100000); 8839 TEST_SPEED_RETURN(50G, 50000); 8840 TEST_SPEED_RETURN(40G, 40000); 8841 TEST_SPEED_RETURN(25G, 25000); 8842 TEST_SPEED_RETURN(10G, 10000); 8843 TEST_SPEED_RETURN(1G, 1000); 8844 TEST_SPEED_RETURN(100M, 100); 8845 8846 #undef TEST_SPEED_RETURN 8847 8848 return 0; 8849} 8850 8851/* 8852 * Return the port capabilities bit for the highest speed in the capabilities. 8853 */ 8854uint32_t fwcap_top_speed(uint32_t caps) 8855{ 8856 #define TEST_SPEED_RETURN(__caps_speed) \ 8857 do { \ 8858 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8859 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8860 } while (0) 8861 8862 TEST_SPEED_RETURN(400G); 8863 TEST_SPEED_RETURN(200G); 8864 TEST_SPEED_RETURN(100G); 8865 TEST_SPEED_RETURN(50G); 8866 TEST_SPEED_RETURN(40G); 8867 TEST_SPEED_RETURN(25G); 8868 TEST_SPEED_RETURN(10G); 8869 TEST_SPEED_RETURN(1G); 8870 TEST_SPEED_RETURN(100M); 8871 8872 #undef TEST_SPEED_RETURN 8873 8874 return 0; 8875} 8876 8877/** 8878 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities 8879 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value 8880 * 8881 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new 8882 * 32-bit Port Capabilities value. 8883 */ 8884static uint32_t lstatus_to_fwcap(u32 lstatus) 8885{ 8886 uint32_t linkattr = 0; 8887 8888 /* 8889 * Unfortunately the format of the Link Status in the old 8890 * 16-bit Port Information message isn't the same as the 8891 * 16-bit Port Capabilities bitfield used everywhere else ... 8892 */ 8893 if (lstatus & F_FW_PORT_CMD_RXPAUSE) 8894 linkattr |= FW_PORT_CAP32_FC_RX; 8895 if (lstatus & F_FW_PORT_CMD_TXPAUSE) 8896 linkattr |= FW_PORT_CAP32_FC_TX; 8897 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 8898 linkattr |= FW_PORT_CAP32_SPEED_100M; 8899 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 8900 linkattr |= FW_PORT_CAP32_SPEED_1G; 8901 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 8902 linkattr |= FW_PORT_CAP32_SPEED_10G; 8903 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 8904 linkattr |= FW_PORT_CAP32_SPEED_25G; 8905 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 8906 linkattr |= FW_PORT_CAP32_SPEED_40G; 8907 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 8908 linkattr |= FW_PORT_CAP32_SPEED_100G; 8909 8910 return linkattr; 8911} 8912 8913/* 8914 * Updates all fields owned by the common code in port_info and link_config 8915 * based on information provided by the firmware. Does not touch any 8916 * requested_* field. 8917 */ 8918static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p, 8919 enum fw_port_action action, bool *mod_changed, bool *link_changed) 8920{ 8921 struct link_config old_lc, *lc = &pi->link_cfg; 8922 unsigned char fc; 8923 u32 stat, linkattr; 8924 int old_ptype, old_mtype; 8925 8926 old_ptype = pi->port_type; 8927 old_mtype = pi->mod_type; 8928 old_lc = *lc; 8929 if (action == FW_PORT_ACTION_GET_PORT_INFO) { 8930 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 8931 8932 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 8933 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 8934 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 8935 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 8936 8937 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); 8938 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); 8939 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); 8940 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 8941 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 8942 8943 linkattr = lstatus_to_fwcap(stat); 8944 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) { 8945 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); 8946 8947 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); 8948 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); 8949 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? 8950 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; 8951 8952 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32); 8953 lc->acaps = be32_to_cpu(p->u.info32.acaps32); 8954 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32); 8955 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; 8956 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); 8957 8958 linkattr = be32_to_cpu(p->u.info32.linkattr32); 8959 } else { 8960 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); 8961 return; 8962 } 8963 8964 lc->speed = fwcap_to_speed(linkattr); 8965 lc->fec = fwcap_to_fec(linkattr, true); 8966 8967 fc = 0; 8968 if (linkattr & FW_PORT_CAP32_FC_RX) 8969 fc |= PAUSE_RX; 8970 if (linkattr & FW_PORT_CAP32_FC_TX) 8971 fc |= PAUSE_TX; 8972 lc->fc = fc; 8973 8974 if (mod_changed != NULL) 8975 *mod_changed = false; 8976 if (link_changed != NULL) 8977 *link_changed = false; 8978 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || 8979 old_lc.pcaps != lc->pcaps) { 8980 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) 8981 lc->fec_hint = fwcap_to_fec(lc->acaps, true); 8982 if (mod_changed != NULL) 8983 *mod_changed = true; 8984 } 8985 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || 8986 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { 8987 if (link_changed != NULL) 8988 *link_changed = true; 8989 } 8990} 8991 8992/** 8993 * t4_update_port_info - retrieve and update port information if changed 8994 * @pi: the port_info 8995 * 8996 * We issue a Get Port Information Command to the Firmware and, if 8997 * successful, we check to see if anything is different from what we 8998 * last recorded and update things accordingly. 8999 */ 9000 int t4_update_port_info(struct port_info *pi) 9001 { 9002 struct adapter *sc = pi->adapter; 9003 struct fw_port_cmd cmd; 9004 enum fw_port_action action; 9005 int ret; 9006 9007 memset(&cmd, 0, sizeof(cmd)); 9008 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 9009 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9010 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 9011 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : 9012 FW_PORT_ACTION_GET_PORT_INFO; 9013 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) | 9014 FW_LEN16(cmd)); 9015 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); 9016 if (ret) 9017 return ret; 9018 9019 handle_port_info(pi, &cmd, action, NULL, NULL); 9020 return 0; 9021} 9022 9023/** 9024 * t4_handle_fw_rpl - process a FW reply message 9025 * @adap: the adapter 9026 * @rpl: start of the FW message 9027 * 9028 * Processes a FW message, such as link state change messages. 9029 */ 9030int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 9031{ 9032 u8 opcode = *(const u8 *)rpl; 9033 const struct fw_port_cmd *p = (const void *)rpl; 9034 enum fw_port_action action = 9035 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 9036 bool mod_changed, link_changed; 9037 9038 if (opcode == FW_PORT_CMD && 9039 (action == FW_PORT_ACTION_GET_PORT_INFO || 9040 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 9041 /* link/module state change message */ 9042 int i; 9043 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 9044 struct port_info *pi = NULL; 9045 struct link_config *lc; 9046 9047 for_each_port(adap, i) { 9048 pi = adap2pinfo(adap, i); 9049 if (pi->tx_chan == chan) 9050 break; 9051 } 9052 9053 lc = &pi->link_cfg; 9054 PORT_LOCK(pi); 9055 handle_port_info(pi, p, action, &mod_changed, &link_changed); 9056 PORT_UNLOCK(pi); 9057 if (mod_changed) 9058 t4_os_portmod_changed(pi); 9059 if (link_changed) { 9060 PORT_LOCK(pi); 9061 t4_os_link_changed(pi); 9062 PORT_UNLOCK(pi); 9063 } 9064 } else { 9065 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 9066 return -EINVAL; 9067 } 9068 return 0; 9069} 9070 9071/** 9072 * get_pci_mode - determine a card's PCI mode 9073 * @adapter: the adapter 9074 * @p: where to store the PCI settings 9075 * 9076 * Determines a card's PCI mode and associated parameters, such as speed 9077 * and width. 9078 */ 9079static void get_pci_mode(struct adapter *adapter, 9080 struct pci_params *p) 9081{ 9082 u16 val; 9083 u32 pcie_cap; 9084 9085 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9086 if (pcie_cap) { 9087 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 9088 p->speed = val & PCI_EXP_LNKSTA_CLS; 9089 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 9090 } 9091} 9092 9093struct flash_desc { 9094 u32 vendor_and_model_id; 9095 u32 size_mb; 9096}; 9097 9098int t4_get_flash_params(struct adapter *adapter) 9099{ 9100 /* 9101 * Table for non-standard supported Flash parts. Note, all Flash 9102 * parts must have 64KB sectors. 9103 */ 9104 static struct flash_desc supported_flash[] = { 9105 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 9106 }; 9107 9108 int ret; 9109 u32 flashid = 0; 9110 unsigned int part, manufacturer; 9111 unsigned int density, size = 0; 9112 9113 9114 /* 9115 * Issue a Read ID Command to the Flash part. We decode supported 9116 * Flash parts and their sizes from this. There's a newer Query 9117 * Command which can retrieve detailed geometry information but many 9118 * Flash parts don't support it. 9119 */ 9120 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 9121 if (!ret) 9122 ret = sf1_read(adapter, 3, 0, 1, &flashid); 9123 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 9124 if (ret < 0) 9125 return ret; 9126 9127 /* 9128 * Check to see if it's one of our non-standard supported Flash parts. 9129 */ 9130 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 9131 if (supported_flash[part].vendor_and_model_id == flashid) { 9132 adapter->params.sf_size = 9133 supported_flash[part].size_mb; 9134 adapter->params.sf_nsec = 9135 adapter->params.sf_size / SF_SEC_SIZE; 9136 goto found; 9137 } 9138 9139 /* 9140 * Decode Flash part size. The code below looks repetative with 9141 * common encodings, but that's not guaranteed in the JEDEC 9142 * specification for the Read JADEC ID command. The only thing that 9143 * we're guaranteed by the JADEC specification is where the 9144 * Manufacturer ID is in the returned result. After that each 9145 * Manufacturer ~could~ encode things completely differently. 9146 * Note, all Flash parts must have 64KB sectors. 9147 */ 9148 manufacturer = flashid & 0xff; 9149 switch (manufacturer) { 9150 case 0x20: /* Micron/Numonix */ 9151 /* 9152 * This Density -> Size decoding table is taken from Micron 9153 * Data Sheets. 9154 */ 9155 density = (flashid >> 16) & 0xff; 9156 switch (density) { 9157 case 0x14: size = 1 << 20; break; /* 1MB */ 9158 case 0x15: size = 1 << 21; break; /* 2MB */ 9159 case 0x16: size = 1 << 22; break; /* 4MB */ 9160 case 0x17: size = 1 << 23; break; /* 8MB */ 9161 case 0x18: size = 1 << 24; break; /* 16MB */ 9162 case 0x19: size = 1 << 25; break; /* 32MB */ 9163 case 0x20: size = 1 << 26; break; /* 64MB */ 9164 case 0x21: size = 1 << 27; break; /* 128MB */ 9165 case 0x22: size = 1 << 28; break; /* 256MB */ 9166 } 9167 break; 9168 9169 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ 9170 /* 9171 * This Density -> Size decoding table is taken from ISSI 9172 * Data Sheets. 9173 */ 9174 density = (flashid >> 16) & 0xff; 9175 switch (density) { 9176 case 0x16: size = 1 << 25; break; /* 32MB */ 9177 case 0x17: size = 1 << 26; break; /* 64MB */ 9178 } 9179 break; 9180 9181 case 0xc2: /* Macronix */ 9182 /* 9183 * This Density -> Size decoding table is taken from Macronix 9184 * Data Sheets. 9185 */ 9186 density = (flashid >> 16) & 0xff; 9187 switch (density) { 9188 case 0x17: size = 1 << 23; break; /* 8MB */ 9189 case 0x18: size = 1 << 24; break; /* 16MB */ 9190 } 9191 break; 9192 9193 case 0xef: /* Winbond */ 9194 /* 9195 * This Density -> Size decoding table is taken from Winbond 9196 * Data Sheets. 9197 */ 9198 density = (flashid >> 16) & 0xff; 9199 switch (density) { 9200 case 0x17: size = 1 << 23; break; /* 8MB */ 9201 case 0x18: size = 1 << 24; break; /* 16MB */ 9202 } 9203 break; 9204 } 9205 9206 /* If we didn't recognize the FLASH part, that's no real issue: the 9207 * Hardware/Software contract says that Hardware will _*ALWAYS*_ 9208 * use a FLASH part which is at least 4MB in size and has 64KB 9209 * sectors. The unrecognized FLASH part is likely to be much larger 9210 * than 4MB, but that's all we really need. 9211 */ 9212 if (size == 0) { 9213 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid); 9214 size = 1 << 22; 9215 } 9216 9217 /* 9218 * Store decoded Flash size and fall through into vetting code. 9219 */ 9220 adapter->params.sf_size = size; 9221 adapter->params.sf_nsec = size / SF_SEC_SIZE; 9222 9223 found: 9224 /* 9225 * We should ~probably~ reject adapters with FLASHes which are too 9226 * small but we have some legacy FPGAs with small FLASHes that we'd 9227 * still like to use. So instead we emit a scary message ... 9228 */ 9229 if (adapter->params.sf_size < FLASH_MIN_SIZE) 9230 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 9231 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 9232 9233 return 0; 9234} 9235 9236static void set_pcie_completion_timeout(struct adapter *adapter, 9237 u8 range) 9238{ 9239 u16 val; 9240 u32 pcie_cap; 9241 9242 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9243 if (pcie_cap) { 9244 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 9245 val &= 0xfff0; 9246 val |= range ; 9247 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 9248 } 9249} 9250 9251const struct chip_params *t4_get_chip_params(int chipid) 9252{ 9253 static const struct chip_params chip_params[] = { 9254 { 9255 /* T4 */ 9256 .nchan = NCHAN, 9257 .pm_stats_cnt = PM_NSTATS, 9258 .cng_ch_bits_log = 2, 9259 .nsched_cls = 15, 9260 .cim_num_obq = CIM_NUM_OBQ, 9261 .filter_opt_len = FILTER_OPT_LEN, 9262 .mps_rplc_size = 128, 9263 .vfcount = 128, 9264 .sge_fl_db = F_DBPRIO, 9265 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 9266 .rss_nentries = RSS_NENTRIES, 9267 }, 9268 { 9269 /* T5 */ 9270 .nchan = NCHAN, 9271 .pm_stats_cnt = PM_NSTATS, 9272 .cng_ch_bits_log = 2, 9273 .nsched_cls = 16, 9274 .cim_num_obq = CIM_NUM_OBQ_T5, 9275 .filter_opt_len = T5_FILTER_OPT_LEN, 9276 .mps_rplc_size = 128, 9277 .vfcount = 128, 9278 .sge_fl_db = F_DBPRIO | F_DBTYPE, 9279 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9280 .rss_nentries = RSS_NENTRIES, 9281 }, 9282 { 9283 /* T6 */ 9284 .nchan = T6_NCHAN, 9285 .pm_stats_cnt = T6_PM_NSTATS, 9286 .cng_ch_bits_log = 3, 9287 .nsched_cls = 16, 9288 .cim_num_obq = CIM_NUM_OBQ_T5, 9289 .filter_opt_len = T5_FILTER_OPT_LEN, 9290 .mps_rplc_size = 256, 9291 .vfcount = 256, 9292 .sge_fl_db = 0, 9293 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9294 .rss_nentries = T6_RSS_NENTRIES, 9295 }, 9296 }; 9297 9298 chipid -= CHELSIO_T4; 9299 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 9300 return NULL; 9301 9302 return &chip_params[chipid]; 9303} 9304 9305/** 9306 * t4_prep_adapter - prepare SW and HW for operation 9307 * @adapter: the adapter 9308 * @buf: temporary space of at least VPD_LEN size provided by the caller. 9309 * 9310 * Initialize adapter SW state for the various HW modules, set initial 9311 * values for some adapter tunables, take PHYs out of reset, and 9312 * initialize the MDIO interface. 9313 */ 9314int t4_prep_adapter(struct adapter *adapter, u32 *buf) 9315{ 9316 int ret; 9317 uint16_t device_id; 9318 uint32_t pl_rev; 9319 9320 get_pci_mode(adapter, &adapter->params.pci); 9321 9322 pl_rev = t4_read_reg(adapter, A_PL_REV); 9323 adapter->params.chipid = G_CHIPID(pl_rev); 9324 adapter->params.rev = G_REV(pl_rev); 9325 if (adapter->params.chipid == 0) { 9326 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 9327 adapter->params.chipid = CHELSIO_T4; 9328 9329 /* T4A1 chip is not supported */ 9330 if (adapter->params.rev == 1) { 9331 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 9332 return -EINVAL; 9333 } 9334 } 9335 9336 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 9337 if (adapter->chip_params == NULL) 9338 return -EINVAL; 9339 9340 adapter->params.pci.vpd_cap_addr = 9341 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 9342 9343 ret = t4_get_flash_params(adapter); 9344 if (ret < 0) 9345 return ret; 9346 9347 /* Cards with real ASICs have the chipid in the PCIe device id */ 9348 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 9349 if (device_id >> 12 == chip_id(adapter)) 9350 adapter->params.cim_la_size = CIMLA_SIZE; 9351 else { 9352 /* FPGA */ 9353 adapter->params.fpga = 1; 9354 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 9355 } 9356 9357 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); 9358 if (ret < 0) 9359 return ret; 9360 9361 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 9362 9363 /* 9364 * Default port and clock for debugging in case we can't reach FW. 9365 */ 9366 adapter->params.nports = 1; 9367 adapter->params.portvec = 1; 9368 adapter->params.vpd.cclk = 50000; 9369 9370 /* Set pci completion timeout value to 4 seconds. */ 9371 set_pcie_completion_timeout(adapter, 0xd); 9372 return 0; 9373} 9374 9375/** 9376 * t4_shutdown_adapter - shut down adapter, host & wire 9377 * @adapter: the adapter 9378 * 9379 * Perform an emergency shutdown of the adapter and stop it from 9380 * continuing any further communication on the ports or DMA to the 9381 * host. This is typically used when the adapter and/or firmware 9382 * have crashed and we want to prevent any further accidental 9383 * communication with the rest of the world. This will also force 9384 * the port Link Status to go down -- if register writes work -- 9385 * which should help our peers figure out that we're down. 9386 */ 9387int t4_shutdown_adapter(struct adapter *adapter) 9388{ 9389 int port; 9390 9391 t4_intr_disable(adapter); 9392 t4_write_reg(adapter, A_DBG_GPIO_EN, 0); 9393 for_each_port(adapter, port) { 9394 u32 a_port_cfg = is_t4(adapter) ? 9395 PORT_REG(port, A_XGMAC_PORT_CFG) : 9396 T5_PORT_REG(port, A_MAC_PORT_CFG); 9397 9398 t4_write_reg(adapter, a_port_cfg, 9399 t4_read_reg(adapter, a_port_cfg) 9400 & ~V_SIGNAL_DET(1)); 9401 } 9402 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 9403 9404 return 0; 9405} 9406 9407/** 9408 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 9409 * @adapter: the adapter 9410 * @qid: the Queue ID 9411 * @qtype: the Ingress or Egress type for @qid 9412 * @user: true if this request is for a user mode queue 9413 * @pbar2_qoffset: BAR2 Queue Offset 9414 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 9415 * 9416 * Returns the BAR2 SGE Queue Registers information associated with the 9417 * indicated Absolute Queue ID. These are passed back in return value 9418 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 9419 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 9420 * 9421 * This may return an error which indicates that BAR2 SGE Queue 9422 * registers aren't available. If an error is not returned, then the 9423 * following values are returned: 9424 * 9425 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 9426 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 9427 * 9428 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 9429 * require the "Inferred Queue ID" ability may be used. E.g. the 9430 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 9431 * then these "Inferred Queue ID" register may not be used. 9432 */ 9433int t4_bar2_sge_qregs(struct adapter *adapter, 9434 unsigned int qid, 9435 enum t4_bar2_qtype qtype, 9436 int user, 9437 u64 *pbar2_qoffset, 9438 unsigned int *pbar2_qid) 9439{ 9440 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 9441 u64 bar2_page_offset, bar2_qoffset; 9442 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 9443 9444 /* T4 doesn't support BAR2 SGE Queue registers for kernel 9445 * mode queues. 9446 */ 9447 if (!user && is_t4(adapter)) 9448 return -EINVAL; 9449 9450 /* Get our SGE Page Size parameters. 9451 */ 9452 page_shift = adapter->params.sge.page_shift; 9453 page_size = 1 << page_shift; 9454 9455 /* Get the right Queues per Page parameters for our Queue. 9456 */ 9457 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 9458 ? adapter->params.sge.eq_s_qpp 9459 : adapter->params.sge.iq_s_qpp); 9460 qpp_mask = (1 << qpp_shift) - 1; 9461 9462 /* Calculate the basics of the BAR2 SGE Queue register area: 9463 * o The BAR2 page the Queue registers will be in. 9464 * o The BAR2 Queue ID. 9465 * o The BAR2 Queue ID Offset into the BAR2 page. 9466 */ 9467 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 9468 bar2_qid = qid & qpp_mask; 9469 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 9470 9471 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 9472 * hardware will infer the Absolute Queue ID simply from the writes to 9473 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 9474 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 9475 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 9476 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 9477 * from the BAR2 Page and BAR2 Queue ID. 9478 * 9479 * One important censequence of this is that some BAR2 SGE registers 9480 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 9481 * there. But other registers synthesize the SGE Queue ID purely 9482 * from the writes to the registers -- the Write Combined Doorbell 9483 * Buffer is a good example. These BAR2 SGE Registers are only 9484 * available for those BAR2 SGE Register areas where the SGE Absolute 9485 * Queue ID can be inferred from simple writes. 9486 */ 9487 bar2_qoffset = bar2_page_offset; 9488 bar2_qinferred = (bar2_qid_offset < page_size); 9489 if (bar2_qinferred) { 9490 bar2_qoffset += bar2_qid_offset; 9491 bar2_qid = 0; 9492 } 9493 9494 *pbar2_qoffset = bar2_qoffset; 9495 *pbar2_qid = bar2_qid; 9496 return 0; 9497} 9498 9499/** 9500 * t4_init_devlog_params - initialize adapter->params.devlog 9501 * @adap: the adapter 9502 * @fw_attach: whether we can talk to the firmware 9503 * 9504 * Initialize various fields of the adapter's Firmware Device Log 9505 * Parameters structure. 9506 */ 9507int t4_init_devlog_params(struct adapter *adap, int fw_attach) 9508{ 9509 struct devlog_params *dparams = &adap->params.devlog; 9510 u32 pf_dparams; 9511 unsigned int devlog_meminfo; 9512 struct fw_devlog_cmd devlog_cmd; 9513 int ret; 9514 9515 /* If we're dealing with newer firmware, the Device Log Paramerters 9516 * are stored in a designated register which allows us to access the 9517 * Device Log even if we can't talk to the firmware. 9518 */ 9519 pf_dparams = 9520 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 9521 if (pf_dparams) { 9522 unsigned int nentries, nentries128; 9523 9524 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 9525 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 9526 9527 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 9528 nentries = (nentries128 + 1) * 128; 9529 dparams->size = nentries * sizeof(struct fw_devlog_e); 9530 9531 return 0; 9532 } 9533 9534 /* 9535 * For any failing returns ... 9536 */ 9537 memset(dparams, 0, sizeof *dparams); 9538 9539 /* 9540 * If we can't talk to the firmware, there's really nothing we can do 9541 * at this point. 9542 */ 9543 if (!fw_attach) 9544 return -ENXIO; 9545 9546 /* Otherwise, ask the firmware for it's Device Log Parameters. 9547 */ 9548 memset(&devlog_cmd, 0, sizeof devlog_cmd); 9549 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9550 F_FW_CMD_REQUEST | F_FW_CMD_READ); 9551 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9552 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 9553 &devlog_cmd); 9554 if (ret) 9555 return ret; 9556 9557 devlog_meminfo = 9558 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 9559 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 9560 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 9561 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 9562 9563 return 0; 9564} 9565 9566/** 9567 * t4_init_sge_params - initialize adap->params.sge 9568 * @adapter: the adapter 9569 * 9570 * Initialize various fields of the adapter's SGE Parameters structure. 9571 */ 9572int t4_init_sge_params(struct adapter *adapter) 9573{ 9574 u32 r; 9575 struct sge_params *sp = &adapter->params.sge; 9576 unsigned i, tscale = 1; 9577 9578 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 9579 sp->counter_val[0] = G_THRESHOLD_0(r); 9580 sp->counter_val[1] = G_THRESHOLD_1(r); 9581 sp->counter_val[2] = G_THRESHOLD_2(r); 9582 sp->counter_val[3] = G_THRESHOLD_3(r); 9583 9584 if (chip_id(adapter) >= CHELSIO_T6) { 9585 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 9586 tscale = G_TSCALE(r); 9587 if (tscale == 0) 9588 tscale = 1; 9589 else 9590 tscale += 2; 9591 } 9592 9593 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 9594 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 9595 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 9596 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 9597 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 9598 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 9599 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 9600 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 9601 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 9602 9603 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 9604 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 9605 if (is_t4(adapter)) 9606 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 9607 else if (is_t5(adapter)) 9608 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 9609 else 9610 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 9611 9612 /* egress queues: log2 of # of doorbells per BAR2 page */ 9613 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 9614 r >>= S_QUEUESPERPAGEPF0 + 9615 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9616 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 9617 9618 /* ingress queues: log2 of # of doorbells per BAR2 page */ 9619 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 9620 r >>= S_QUEUESPERPAGEPF0 + 9621 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9622 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 9623 9624 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 9625 r >>= S_HOSTPAGESIZEPF0 + 9626 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 9627 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 9628 9629 r = t4_read_reg(adapter, A_SGE_CONTROL); 9630 sp->sge_control = r; 9631 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 9632 sp->fl_pktshift = G_PKTSHIFT(r); 9633 if (chip_id(adapter) <= CHELSIO_T5) { 9634 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9635 X_INGPADBOUNDARY_SHIFT); 9636 } else { 9637 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9638 X_T6_INGPADBOUNDARY_SHIFT); 9639 } 9640 if (is_t4(adapter)) 9641 sp->pack_boundary = sp->pad_boundary; 9642 else { 9643 r = t4_read_reg(adapter, A_SGE_CONTROL2); 9644 if (G_INGPACKBOUNDARY(r) == 0) 9645 sp->pack_boundary = 16; 9646 else 9647 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 9648 } 9649 for (i = 0; i < SGE_FLBUF_SIZES; i++) 9650 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 9651 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 9652 9653 return 0; 9654} 9655 9656/* Convert the LE's hardware hash mask to a shorter filter mask. */ 9657static inline uint16_t 9658hashmask_to_filtermask(uint64_t hashmask, uint16_t filter_mode) 9659{ 9660 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 9661 int i; 9662 uint16_t filter_mask; 9663 uint64_t mask; /* field mask */ 9664 9665 filter_mask = 0; 9666 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 9667 if ((filter_mode & (1 << i)) == 0) 9668 continue; 9669 mask = (1 << width[i]) - 1; 9670 if ((hashmask & mask) == mask) 9671 filter_mask |= 1 << i; 9672 hashmask >>= width[i]; 9673 } 9674 9675 return (filter_mask); 9676} 9677 9678/* 9679 * Read and cache the adapter's compressed filter mode and ingress config. 9680 */ 9681static void 9682read_filter_mode_and_ingress_config(struct adapter *adap) 9683{ 9684 int rc; 9685 uint32_t v, param[2], val[2]; 9686 struct tp_params *tpp = &adap->params.tp; 9687 uint64_t hash_mask; 9688 9689 param[0] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9690 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9691 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 9692 param[1] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9693 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9694 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 9695 rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val); 9696 if (rc == 0) { 9697 tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]); 9698 tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]); 9699 tpp->vnic_mode = val[1]; 9700 } else { 9701 /* 9702 * Old firmware. Read filter mode/mask and ingress config 9703 * straight from the hardware. 9704 */ 9705 t4_tp_pio_read(adap, &v, 1, A_TP_VLAN_PRI_MAP, true); 9706 tpp->filter_mode = v & 0xffff; 9707 9708 hash_mask = 0; 9709 if (chip_id(adap) > CHELSIO_T4) { 9710 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3)); 9711 hash_mask = v; 9712 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4)); 9713 hash_mask |= (u64)v << 32; 9714 } 9715 tpp->filter_mask = hashmask_to_filtermask(hash_mask, 9716 tpp->filter_mode); 9717 9718 t4_tp_pio_read(adap, &v, 1, A_TP_INGRESS_CONFIG, true); 9719 if (v & F_VNIC) 9720 tpp->vnic_mode = FW_VNIC_MODE_PF_VF; 9721 else 9722 tpp->vnic_mode = FW_VNIC_MODE_OUTER_VLAN; 9723 } 9724 9725 /* 9726 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 9727 * shift positions of several elements of the Compressed Filter Tuple 9728 * for this adapter which we need frequently ... 9729 */ 9730 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 9731 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 9732 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 9733 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 9734 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 9735 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 9736 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 9737 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 9738 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 9739 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 9740} 9741 9742/** 9743 * t4_init_tp_params - initialize adap->params.tp 9744 * @adap: the adapter 9745 * 9746 * Initialize various fields of the adapter's TP Parameters structure. 9747 */ 9748int t4_init_tp_params(struct adapter *adap) 9749{ 9750 int chan; 9751 u32 tx_len, rx_len, r, v; 9752 struct tp_params *tpp = &adap->params.tp; 9753 9754 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 9755 tpp->tre = G_TIMERRESOLUTION(v); 9756 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 9757 9758 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 9759 for (chan = 0; chan < MAX_NCHAN; chan++) 9760 tpp->tx_modq[chan] = chan; 9761 9762 read_filter_mode_and_ingress_config(adap); 9763 9764 if (chip_id(adap) > CHELSIO_T5) { 9765 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 9766 tpp->rx_pkt_encap = v & F_CRXPKTENC; 9767 } else 9768 tpp->rx_pkt_encap = false; 9769 9770 rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE); 9771 tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE); 9772 9773 r = t4_read_reg(adap, A_TP_PARA_REG2); 9774 rx_len = min(rx_len, G_MAXRXDATA(r)); 9775 tx_len = min(tx_len, G_MAXRXDATA(r)); 9776 9777 r = t4_read_reg(adap, A_TP_PARA_REG7); 9778 v = min(G_PMMAXXFERLEN0(r), G_PMMAXXFERLEN1(r)); 9779 rx_len = min(rx_len, v); 9780 tx_len = min(tx_len, v); 9781 9782 tpp->max_tx_pdu = tx_len; 9783 tpp->max_rx_pdu = rx_len; 9784 9785 return 0; 9786} 9787 9788/** 9789 * t4_filter_field_shift - calculate filter field shift 9790 * @adap: the adapter 9791 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 9792 * 9793 * Return the shift position of a filter field within the Compressed 9794 * Filter Tuple. The filter field is specified via its selection bit 9795 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 9796 */ 9797int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 9798{ 9799 const unsigned int filter_mode = adap->params.tp.filter_mode; 9800 unsigned int sel; 9801 int field_shift; 9802 9803 if ((filter_mode & filter_sel) == 0) 9804 return -1; 9805 9806 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 9807 switch (filter_mode & sel) { 9808 case F_FCOE: 9809 field_shift += W_FT_FCOE; 9810 break; 9811 case F_PORT: 9812 field_shift += W_FT_PORT; 9813 break; 9814 case F_VNIC_ID: 9815 field_shift += W_FT_VNIC_ID; 9816 break; 9817 case F_VLAN: 9818 field_shift += W_FT_VLAN; 9819 break; 9820 case F_TOS: 9821 field_shift += W_FT_TOS; 9822 break; 9823 case F_PROTOCOL: 9824 field_shift += W_FT_PROTOCOL; 9825 break; 9826 case F_ETHERTYPE: 9827 field_shift += W_FT_ETHERTYPE; 9828 break; 9829 case F_MACMATCH: 9830 field_shift += W_FT_MACMATCH; 9831 break; 9832 case F_MPSHITTYPE: 9833 field_shift += W_FT_MPSHITTYPE; 9834 break; 9835 case F_FRAGMENTATION: 9836 field_shift += W_FT_FRAGMENTATION; 9837 break; 9838 } 9839 } 9840 return field_shift; 9841} 9842 9843int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 9844{ 9845 u8 addr[6]; 9846 int ret, i, j; 9847 struct port_info *p = adap2pinfo(adap, port_id); 9848 u32 param, val; 9849 struct vi_info *vi = &p->vi[0]; 9850 9851 for (i = 0, j = -1; i <= p->port_id; i++) { 9852 do { 9853 j++; 9854 } while ((adap->params.portvec & (1 << j)) == 0); 9855 } 9856 9857 p->tx_chan = j; 9858 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 9859 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 9860 p->rx_c_chan = t4_get_rx_c_chan(adap, j); 9861 p->lport = j; 9862 9863 if (!(adap->flags & IS_VF) || 9864 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 9865 t4_update_port_info(p); 9866 } 9867 9868 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size, 9869 &vi->vfvld, &vi->vin); 9870 if (ret < 0) 9871 return ret; 9872 9873 vi->viid = ret; 9874 t4_os_set_hw_addr(p, addr); 9875 9876 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9877 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 9878 V_FW_PARAMS_PARAM_YZ(vi->viid); 9879 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 9880 if (ret) 9881 vi->rss_base = 0xffff; 9882 else { 9883 /* MPASS((val >> 16) == rss_size); */ 9884 vi->rss_base = val & 0xffff; 9885 } 9886 9887 return 0; 9888} 9889 9890/** 9891 * t4_read_cimq_cfg - read CIM queue configuration 9892 * @adap: the adapter 9893 * @base: holds the queue base addresses in bytes 9894 * @size: holds the queue sizes in bytes 9895 * @thres: holds the queue full thresholds in bytes 9896 * 9897 * Returns the current configuration of the CIM queues, starting with 9898 * the IBQs, then the OBQs. 9899 */ 9900void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 9901{ 9902 unsigned int i, v; 9903 int cim_num_obq = adap->chip_params->cim_num_obq; 9904 9905 for (i = 0; i < CIM_NUM_IBQ; i++) { 9906 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 9907 V_QUENUMSELECT(i)); 9908 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9909 /* value is in 256-byte units */ 9910 *base++ = G_CIMQBASE(v) * 256; 9911 *size++ = G_CIMQSIZE(v) * 256; 9912 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 9913 } 9914 for (i = 0; i < cim_num_obq; i++) { 9915 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9916 V_QUENUMSELECT(i)); 9917 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9918 /* value is in 256-byte units */ 9919 *base++ = G_CIMQBASE(v) * 256; 9920 *size++ = G_CIMQSIZE(v) * 256; 9921 } 9922} 9923 9924/** 9925 * t4_read_cim_ibq - read the contents of a CIM inbound queue 9926 * @adap: the adapter 9927 * @qid: the queue index 9928 * @data: where to store the queue contents 9929 * @n: capacity of @data in 32-bit words 9930 * 9931 * Reads the contents of the selected CIM queue starting at address 0 up 9932 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9933 * error and the number of 32-bit words actually read on success. 9934 */ 9935int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9936{ 9937 int i, err, attempts; 9938 unsigned int addr; 9939 const unsigned int nwords = CIM_IBQ_SIZE * 4; 9940 9941 if (qid > 5 || (n & 3)) 9942 return -EINVAL; 9943 9944 addr = qid * nwords; 9945 if (n > nwords) 9946 n = nwords; 9947 9948 /* It might take 3-10ms before the IBQ debug read access is allowed. 9949 * Wait for 1 Sec with a delay of 1 usec. 9950 */ 9951 attempts = 1000000; 9952 9953 for (i = 0; i < n; i++, addr++) { 9954 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 9955 F_IBQDBGEN); 9956 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 9957 attempts, 1); 9958 if (err) 9959 return err; 9960 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 9961 } 9962 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 9963 return i; 9964} 9965 9966/** 9967 * t4_read_cim_obq - read the contents of a CIM outbound queue 9968 * @adap: the adapter 9969 * @qid: the queue index 9970 * @data: where to store the queue contents 9971 * @n: capacity of @data in 32-bit words 9972 * 9973 * Reads the contents of the selected CIM queue starting at address 0 up 9974 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9975 * error and the number of 32-bit words actually read on success. 9976 */ 9977int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9978{ 9979 int i, err; 9980 unsigned int addr, v, nwords; 9981 int cim_num_obq = adap->chip_params->cim_num_obq; 9982 9983 if ((qid > (cim_num_obq - 1)) || (n & 3)) 9984 return -EINVAL; 9985 9986 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9987 V_QUENUMSELECT(qid)); 9988 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9989 9990 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 9991 nwords = G_CIMQSIZE(v) * 64; /* same */ 9992 if (n > nwords) 9993 n = nwords; 9994 9995 for (i = 0; i < n; i++, addr++) { 9996 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 9997 F_OBQDBGEN); 9998 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 9999 2, 1); 10000 if (err) 10001 return err; 10002 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 10003 } 10004 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 10005 return i; 10006} 10007 10008enum { 10009 CIM_QCTL_BASE = 0, 10010 CIM_CTL_BASE = 0x2000, 10011 CIM_PBT_ADDR_BASE = 0x2800, 10012 CIM_PBT_LRF_BASE = 0x3000, 10013 CIM_PBT_DATA_BASE = 0x3800 10014}; 10015 10016/** 10017 * t4_cim_read - read a block from CIM internal address space 10018 * @adap: the adapter 10019 * @addr: the start address within the CIM address space 10020 * @n: number of words to read 10021 * @valp: where to store the result 10022 * 10023 * Reads a block of 4-byte words from the CIM intenal address space. 10024 */ 10025int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 10026 unsigned int *valp) 10027{ 10028 int ret = 0; 10029 10030 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10031 return -EBUSY; 10032 10033 for ( ; !ret && n--; addr += 4) { 10034 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 10035 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10036 0, 5, 2); 10037 if (!ret) 10038 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 10039 } 10040 return ret; 10041} 10042 10043/** 10044 * t4_cim_write - write a block into CIM internal address space 10045 * @adap: the adapter 10046 * @addr: the start address within the CIM address space 10047 * @n: number of words to write 10048 * @valp: set of values to write 10049 * 10050 * Writes a block of 4-byte words into the CIM intenal address space. 10051 */ 10052int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 10053 const unsigned int *valp) 10054{ 10055 int ret = 0; 10056 10057 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10058 return -EBUSY; 10059 10060 for ( ; !ret && n--; addr += 4) { 10061 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 10062 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 10063 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10064 0, 5, 2); 10065 } 10066 return ret; 10067} 10068 10069static int t4_cim_write1(struct adapter *adap, unsigned int addr, 10070 unsigned int val) 10071{ 10072 return t4_cim_write(adap, addr, 1, &val); 10073} 10074 10075/** 10076 * t4_cim_ctl_read - read a block from CIM control region 10077 * @adap: the adapter 10078 * @addr: the start address within the CIM control region 10079 * @n: number of words to read 10080 * @valp: where to store the result 10081 * 10082 * Reads a block of 4-byte words from the CIM control region. 10083 */ 10084int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 10085 unsigned int *valp) 10086{ 10087 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 10088} 10089 10090/** 10091 * t4_cim_read_la - read CIM LA capture buffer 10092 * @adap: the adapter 10093 * @la_buf: where to store the LA data 10094 * @wrptr: the HW write pointer within the capture buffer 10095 * 10096 * Reads the contents of the CIM LA buffer with the most recent entry at 10097 * the end of the returned data and with the entry at @wrptr first. 10098 * We try to leave the LA in the running state we find it in. 10099 */ 10100int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 10101{ 10102 int i, ret; 10103 unsigned int cfg, val, idx; 10104 10105 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 10106 if (ret) 10107 return ret; 10108 10109 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 10110 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 10111 if (ret) 10112 return ret; 10113 } 10114 10115 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10116 if (ret) 10117 goto restart; 10118 10119 idx = G_UPDBGLAWRPTR(val); 10120 if (wrptr) 10121 *wrptr = idx; 10122 10123 for (i = 0; i < adap->params.cim_la_size; i++) { 10124 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10125 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 10126 if (ret) 10127 break; 10128 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10129 if (ret) 10130 break; 10131 if (val & F_UPDBGLARDEN) { 10132 ret = -ETIMEDOUT; 10133 break; 10134 } 10135 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 10136 if (ret) 10137 break; 10138 10139 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 10140 * identify the 32-bit portion of the full 312-bit data 10141 */ 10142 if (is_t6(adap) && (idx & 0xf) >= 9) 10143 idx = (idx & 0xff0) + 0x10; 10144 else 10145 idx++; 10146 /* address can't exceed 0xfff */ 10147 idx &= M_UPDBGLARDPTR; 10148 } 10149restart: 10150 if (cfg & F_UPDBGLAEN) { 10151 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10152 cfg & ~F_UPDBGLARDEN); 10153 if (!ret) 10154 ret = r; 10155 } 10156 return ret; 10157} 10158 10159/** 10160 * t4_tp_read_la - read TP LA capture buffer 10161 * @adap: the adapter 10162 * @la_buf: where to store the LA data 10163 * @wrptr: the HW write pointer within the capture buffer 10164 * 10165 * Reads the contents of the TP LA buffer with the most recent entry at 10166 * the end of the returned data and with the entry at @wrptr first. 10167 * We leave the LA in the running state we find it in. 10168 */ 10169void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 10170{ 10171 bool last_incomplete; 10172 unsigned int i, cfg, val, idx; 10173 10174 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 10175 if (cfg & F_DBGLAENABLE) /* freeze LA */ 10176 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10177 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 10178 10179 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 10180 idx = G_DBGLAWPTR(val); 10181 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 10182 if (last_incomplete) 10183 idx = (idx + 1) & M_DBGLARPTR; 10184 if (wrptr) 10185 *wrptr = idx; 10186 10187 val &= 0xffff; 10188 val &= ~V_DBGLARPTR(M_DBGLARPTR); 10189 val |= adap->params.tp.la_mask; 10190 10191 for (i = 0; i < TPLA_SIZE; i++) { 10192 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 10193 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 10194 idx = (idx + 1) & M_DBGLARPTR; 10195 } 10196 10197 /* Wipe out last entry if it isn't valid */ 10198 if (last_incomplete) 10199 la_buf[TPLA_SIZE - 1] = ~0ULL; 10200 10201 if (cfg & F_DBGLAENABLE) /* restore running state */ 10202 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10203 cfg | adap->params.tp.la_mask); 10204} 10205 10206/* 10207 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 10208 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 10209 * state for more than the Warning Threshold then we'll issue a warning about 10210 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 10211 * appears to be hung every Warning Repeat second till the situation clears. 10212 * If the situation clears, we'll note that as well. 10213 */ 10214#define SGE_IDMA_WARN_THRESH 1 10215#define SGE_IDMA_WARN_REPEAT 300 10216 10217/** 10218 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 10219 * @adapter: the adapter 10220 * @idma: the adapter IDMA Monitor state 10221 * 10222 * Initialize the state of an SGE Ingress DMA Monitor. 10223 */ 10224void t4_idma_monitor_init(struct adapter *adapter, 10225 struct sge_idma_monitor_state *idma) 10226{ 10227 /* Initialize the state variables for detecting an SGE Ingress DMA 10228 * hang. The SGE has internal counters which count up on each clock 10229 * tick whenever the SGE finds its Ingress DMA State Engines in the 10230 * same state they were on the previous clock tick. The clock used is 10231 * the Core Clock so we have a limit on the maximum "time" they can 10232 * record; typically a very small number of seconds. For instance, 10233 * with a 600MHz Core Clock, we can only count up to a bit more than 10234 * 7s. So we'll synthesize a larger counter in order to not run the 10235 * risk of having the "timers" overflow and give us the flexibility to 10236 * maintain a Hung SGE State Machine of our own which operates across 10237 * a longer time frame. 10238 */ 10239 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 10240 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 10241} 10242 10243/** 10244 * t4_idma_monitor - monitor SGE Ingress DMA state 10245 * @adapter: the adapter 10246 * @idma: the adapter IDMA Monitor state 10247 * @hz: number of ticks/second 10248 * @ticks: number of ticks since the last IDMA Monitor call 10249 */ 10250void t4_idma_monitor(struct adapter *adapter, 10251 struct sge_idma_monitor_state *idma, 10252 int hz, int ticks) 10253{ 10254 int i, idma_same_state_cnt[2]; 10255 10256 /* Read the SGE Debug Ingress DMA Same State Count registers. These 10257 * are counters inside the SGE which count up on each clock when the 10258 * SGE finds its Ingress DMA State Engines in the same states they 10259 * were in the previous clock. The counters will peg out at 10260 * 0xffffffff without wrapping around so once they pass the 1s 10261 * threshold they'll stay above that till the IDMA state changes. 10262 */ 10263 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 10264 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 10265 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10266 10267 for (i = 0; i < 2; i++) { 10268 u32 debug0, debug11; 10269 10270 /* If the Ingress DMA Same State Counter ("timer") is less 10271 * than 1s, then we can reset our synthesized Stall Timer and 10272 * continue. If we have previously emitted warnings about a 10273 * potential stalled Ingress Queue, issue a note indicating 10274 * that the Ingress Queue has resumed forward progress. 10275 */ 10276 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 10277 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 10278 CH_WARN(adapter, "SGE idma%d, queue %u, " 10279 "resumed after %d seconds\n", 10280 i, idma->idma_qid[i], 10281 idma->idma_stalled[i]/hz); 10282 idma->idma_stalled[i] = 0; 10283 continue; 10284 } 10285 10286 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 10287 * domain. The first time we get here it'll be because we 10288 * passed the 1s Threshold; each additional time it'll be 10289 * because the RX Timer Callback is being fired on its regular 10290 * schedule. 10291 * 10292 * If the stall is below our Potential Hung Ingress Queue 10293 * Warning Threshold, continue. 10294 */ 10295 if (idma->idma_stalled[i] == 0) { 10296 idma->idma_stalled[i] = hz; 10297 idma->idma_warn[i] = 0; 10298 } else { 10299 idma->idma_stalled[i] += ticks; 10300 idma->idma_warn[i] -= ticks; 10301 } 10302 10303 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 10304 continue; 10305 10306 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 10307 */ 10308 if (idma->idma_warn[i] > 0) 10309 continue; 10310 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 10311 10312 /* Read and save the SGE IDMA State and Queue ID information. 10313 * We do this every time in case it changes across time ... 10314 * can't be too careful ... 10315 */ 10316 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 10317 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10318 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 10319 10320 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 10321 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10322 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 10323 10324 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 10325 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 10326 i, idma->idma_qid[i], idma->idma_state[i], 10327 idma->idma_stalled[i]/hz, 10328 debug0, debug11); 10329 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 10330 } 10331} 10332 10333/** 10334 * t4_set_vf_mac - Set MAC address for the specified VF 10335 * @adapter: The adapter 10336 * @pf: the PF used to instantiate the VFs 10337 * @vf: one of the VFs instantiated by the specified PF 10338 * @naddr: the number of MAC addresses 10339 * @addr: the MAC address(es) to be set to the specified VF 10340 */ 10341int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf, 10342 unsigned int naddr, u8 *addr) 10343{ 10344 struct fw_acl_mac_cmd cmd; 10345 10346 memset(&cmd, 0, sizeof(cmd)); 10347 cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_MAC_CMD) | 10348 F_FW_CMD_REQUEST | 10349 F_FW_CMD_WRITE | 10350 V_FW_ACL_MAC_CMD_PFN(pf) | 10351 V_FW_ACL_MAC_CMD_VFN(vf)); 10352 10353 /* Note: Do not enable the ACL */ 10354 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd)); 10355 cmd.nmac = naddr; 10356 10357 switch (pf) { 10358 case 3: 10359 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3)); 10360 break; 10361 case 2: 10362 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2)); 10363 break; 10364 case 1: 10365 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1)); 10366 break; 10367 case 0: 10368 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0)); 10369 break; 10370 } 10371 10372 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd); 10373} 10374 10375/** 10376 * t4_read_pace_tbl - read the pace table 10377 * @adap: the adapter 10378 * @pace_vals: holds the returned values 10379 * 10380 * Returns the values of TP's pace table in microseconds. 10381 */ 10382void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 10383{ 10384 unsigned int i, v; 10385 10386 for (i = 0; i < NTX_SCHED; i++) { 10387 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 10388 v = t4_read_reg(adap, A_TP_PACE_TABLE); 10389 pace_vals[i] = dack_ticks_to_usec(adap, v); 10390 } 10391} 10392 10393/** 10394 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 10395 * @adap: the adapter 10396 * @sched: the scheduler index 10397 * @kbps: the byte rate in Kbps 10398 * @ipg: the interpacket delay in tenths of nanoseconds 10399 * 10400 * Return the current configuration of a HW Tx scheduler. 10401 */ 10402void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 10403 unsigned int *ipg, bool sleep_ok) 10404{ 10405 unsigned int v, addr, bpt, cpt; 10406 10407 if (kbps) { 10408 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 10409 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10410 if (sched & 1) 10411 v >>= 16; 10412 bpt = (v >> 8) & 0xff; 10413 cpt = v & 0xff; 10414 if (!cpt) 10415 *kbps = 0; /* scheduler disabled */ 10416 else { 10417 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 10418 *kbps = (v * bpt) / 125; 10419 } 10420 } 10421 if (ipg) { 10422 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 10423 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10424 if (sched & 1) 10425 v >>= 16; 10426 v &= 0xffff; 10427 *ipg = (10000 * v) / core_ticks_per_usec(adap); 10428 } 10429} 10430 10431/** 10432 * t4_load_cfg - download config file 10433 * @adap: the adapter 10434 * @cfg_data: the cfg text file to write 10435 * @size: text file size 10436 * 10437 * Write the supplied config text file to the card's serial flash. 10438 */ 10439int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 10440{ 10441 int ret, i, n, cfg_addr; 10442 unsigned int addr; 10443 unsigned int flash_cfg_start_sec; 10444 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10445 10446 cfg_addr = t4_flash_cfg_addr(adap); 10447 if (cfg_addr < 0) 10448 return cfg_addr; 10449 10450 addr = cfg_addr; 10451 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10452 10453 if (size > FLASH_CFG_MAX_SIZE) { 10454 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 10455 FLASH_CFG_MAX_SIZE); 10456 return -EFBIG; 10457 } 10458 10459 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 10460 sf_sec_size); 10461 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10462 flash_cfg_start_sec + i - 1); 10463 /* 10464 * If size == 0 then we're simply erasing the FLASH sectors associated 10465 * with the on-adapter Firmware Configuration File. 10466 */ 10467 if (ret || size == 0) 10468 goto out; 10469 10470 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10471 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10472 if ( (size - i) < SF_PAGE_SIZE) 10473 n = size - i; 10474 else 10475 n = SF_PAGE_SIZE; 10476 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 10477 if (ret) 10478 goto out; 10479 10480 addr += SF_PAGE_SIZE; 10481 cfg_data += SF_PAGE_SIZE; 10482 } 10483 10484out: 10485 if (ret) 10486 CH_ERR(adap, "config file %s failed %d\n", 10487 (size == 0 ? "clear" : "download"), ret); 10488 return ret; 10489} 10490 10491/** 10492 * t5_fw_init_extern_mem - initialize the external memory 10493 * @adap: the adapter 10494 * 10495 * Initializes the external memory on T5. 10496 */ 10497int t5_fw_init_extern_mem(struct adapter *adap) 10498{ 10499 u32 params[1], val[1]; 10500 int ret; 10501 10502 if (!is_t5(adap)) 10503 return 0; 10504 10505 val[0] = 0xff; /* Initialize all MCs */ 10506 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10507 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 10508 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 10509 FW_CMD_MAX_TIMEOUT); 10510 10511 return ret; 10512} 10513 10514/* BIOS boot headers */ 10515typedef struct pci_expansion_rom_header { 10516 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10517 u8 reserved[22]; /* Reserved per processor Architecture data */ 10518 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10519} pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 10520 10521/* Legacy PCI Expansion ROM Header */ 10522typedef struct legacy_pci_expansion_rom_header { 10523 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10524 u8 size512; /* Current Image Size in units of 512 bytes */ 10525 u8 initentry_point[4]; 10526 u8 cksum; /* Checksum computed on the entire Image */ 10527 u8 reserved[16]; /* Reserved */ 10528 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 10529} legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 10530 10531/* EFI PCI Expansion ROM Header */ 10532typedef struct efi_pci_expansion_rom_header { 10533 u8 signature[2]; // ROM signature. The value 0xaa55 10534 u8 initialization_size[2]; /* Units 512. Includes this header */ 10535 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 10536 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 10537 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 10538 u8 compression_type[2]; /* Compression type. */ 10539 /* 10540 * Compression type definition 10541 * 0x0: uncompressed 10542 * 0x1: Compressed 10543 * 0x2-0xFFFF: Reserved 10544 */ 10545 u8 reserved[8]; /* Reserved */ 10546 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 10547 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10548} efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 10549 10550/* PCI Data Structure Format */ 10551typedef struct pcir_data_structure { /* PCI Data Structure */ 10552 u8 signature[4]; /* Signature. The string "PCIR" */ 10553 u8 vendor_id[2]; /* Vendor Identification */ 10554 u8 device_id[2]; /* Device Identification */ 10555 u8 vital_product[2]; /* Pointer to Vital Product Data */ 10556 u8 length[2]; /* PCIR Data Structure Length */ 10557 u8 revision; /* PCIR Data Structure Revision */ 10558 u8 class_code[3]; /* Class Code */ 10559 u8 image_length[2]; /* Image Length. Multiple of 512B */ 10560 u8 code_revision[2]; /* Revision Level of Code/Data */ 10561 u8 code_type; /* Code Type. */ 10562 /* 10563 * PCI Expansion ROM Code Types 10564 * 0x00: Intel IA-32, PC-AT compatible. Legacy 10565 * 0x01: Open Firmware standard for PCI. FCODE 10566 * 0x02: Hewlett-Packard PA RISC. HP reserved 10567 * 0x03: EFI Image. EFI 10568 * 0x04-0xFF: Reserved. 10569 */ 10570 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 10571 u8 reserved[2]; /* Reserved */ 10572} pcir_data_t; /* PCI__DATA_STRUCTURE */ 10573 10574/* BOOT constants */ 10575enum { 10576 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 10577 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 10578 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 10579 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 10580 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 10581 VENDOR_ID = 0x1425, /* Vendor ID */ 10582 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 10583}; 10584 10585/* 10586 * modify_device_id - Modifies the device ID of the Boot BIOS image 10587 * @adatper: the device ID to write. 10588 * @boot_data: the boot image to modify. 10589 * 10590 * Write the supplied device ID to the boot BIOS image. 10591 */ 10592static void modify_device_id(int device_id, u8 *boot_data) 10593{ 10594 legacy_pci_exp_rom_header_t *header; 10595 pcir_data_t *pcir_header; 10596 u32 cur_header = 0; 10597 10598 /* 10599 * Loop through all chained images and change the device ID's 10600 */ 10601 while (1) { 10602 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 10603 pcir_header = (pcir_data_t *) &boot_data[cur_header + 10604 le16_to_cpu(*(u16*)header->pcir_offset)]; 10605 10606 /* 10607 * Only modify the Device ID if code type is Legacy or HP. 10608 * 0x00: Okay to modify 10609 * 0x01: FCODE. Do not be modify 10610 * 0x03: Okay to modify 10611 * 0x04-0xFF: Do not modify 10612 */ 10613 if (pcir_header->code_type == 0x00) { 10614 u8 csum = 0; 10615 int i; 10616 10617 /* 10618 * Modify Device ID to match current adatper 10619 */ 10620 *(u16*) pcir_header->device_id = device_id; 10621 10622 /* 10623 * Set checksum temporarily to 0. 10624 * We will recalculate it later. 10625 */ 10626 header->cksum = 0x0; 10627 10628 /* 10629 * Calculate and update checksum 10630 */ 10631 for (i = 0; i < (header->size512 * 512); i++) 10632 csum += (u8)boot_data[cur_header + i]; 10633 10634 /* 10635 * Invert summed value to create the checksum 10636 * Writing new checksum value directly to the boot data 10637 */ 10638 boot_data[cur_header + 7] = -csum; 10639 10640 } else if (pcir_header->code_type == 0x03) { 10641 10642 /* 10643 * Modify Device ID to match current adatper 10644 */ 10645 *(u16*) pcir_header->device_id = device_id; 10646 10647 } 10648 10649 10650 /* 10651 * Check indicator element to identify if this is the last 10652 * image in the ROM. 10653 */ 10654 if (pcir_header->indicator & 0x80) 10655 break; 10656 10657 /* 10658 * Move header pointer up to the next image in the ROM. 10659 */ 10660 cur_header += header->size512 * 512; 10661 } 10662} 10663 10664/* 10665 * t4_load_boot - download boot flash 10666 * @adapter: the adapter 10667 * @boot_data: the boot image to write 10668 * @boot_addr: offset in flash to write boot_data 10669 * @size: image size 10670 * 10671 * Write the supplied boot image to the card's serial flash. 10672 * The boot image has the following sections: a 28-byte header and the 10673 * boot image. 10674 */ 10675int t4_load_boot(struct adapter *adap, u8 *boot_data, 10676 unsigned int boot_addr, unsigned int size) 10677{ 10678 pci_exp_rom_header_t *header; 10679 int pcir_offset ; 10680 pcir_data_t *pcir_header; 10681 int ret, addr; 10682 uint16_t device_id; 10683 unsigned int i; 10684 unsigned int boot_sector = (boot_addr * 1024 ); 10685 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10686 10687 /* 10688 * Make sure the boot image does not encroach on the firmware region 10689 */ 10690 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 10691 CH_ERR(adap, "boot image encroaching on firmware region\n"); 10692 return -EFBIG; 10693 } 10694 10695 /* 10696 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 10697 * and Boot configuration data sections. These 3 boot sections span 10698 * sectors 0 to 7 in flash and live right before the FW image location. 10699 */ 10700 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 10701 sf_sec_size); 10702 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 10703 (boot_sector >> 16) + i - 1); 10704 10705 /* 10706 * If size == 0 then we're simply erasing the FLASH sectors associated 10707 * with the on-adapter option ROM file 10708 */ 10709 if (ret || (size == 0)) 10710 goto out; 10711 10712 /* Get boot header */ 10713 header = (pci_exp_rom_header_t *)boot_data; 10714 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 10715 /* PCIR Data Structure */ 10716 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 10717 10718 /* 10719 * Perform some primitive sanity testing to avoid accidentally 10720 * writing garbage over the boot sectors. We ought to check for 10721 * more but it's not worth it for now ... 10722 */ 10723 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 10724 CH_ERR(adap, "boot image too small/large\n"); 10725 return -EFBIG; 10726 } 10727 10728#ifndef CHELSIO_T4_DIAGS 10729 /* 10730 * Check BOOT ROM header signature 10731 */ 10732 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 10733 CH_ERR(adap, "Boot image missing signature\n"); 10734 return -EINVAL; 10735 } 10736 10737 /* 10738 * Check PCI header signature 10739 */ 10740 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 10741 CH_ERR(adap, "PCI header missing signature\n"); 10742 return -EINVAL; 10743 } 10744 10745 /* 10746 * Check Vendor ID matches Chelsio ID 10747 */ 10748 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 10749 CH_ERR(adap, "Vendor ID missing signature\n"); 10750 return -EINVAL; 10751 } 10752#endif 10753 10754 /* 10755 * Retrieve adapter's device ID 10756 */ 10757 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 10758 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 10759 device_id = device_id & 0xf0ff; 10760 10761 /* 10762 * Check PCIE Device ID 10763 */ 10764 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 10765 /* 10766 * Change the device ID in the Boot BIOS image to match 10767 * the Device ID of the current adapter. 10768 */ 10769 modify_device_id(device_id, boot_data); 10770 } 10771 10772 /* 10773 * Skip over the first SF_PAGE_SIZE worth of data and write it after 10774 * we finish copying the rest of the boot image. This will ensure 10775 * that the BIOS boot header will only be written if the boot image 10776 * was written in full. 10777 */ 10778 addr = boot_sector; 10779 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 10780 addr += SF_PAGE_SIZE; 10781 boot_data += SF_PAGE_SIZE; 10782 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 10783 if (ret) 10784 goto out; 10785 } 10786 10787 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 10788 (const u8 *)header, 0); 10789 10790out: 10791 if (ret) 10792 CH_ERR(adap, "boot image download failed, error %d\n", ret); 10793 return ret; 10794} 10795 10796/* 10797 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 10798 * @adapter: the adapter 10799 * 10800 * Return the address within the flash where the OptionROM Configuration 10801 * is stored, or an error if the device FLASH is too small to contain 10802 * a OptionROM Configuration. 10803 */ 10804static int t4_flash_bootcfg_addr(struct adapter *adapter) 10805{ 10806 /* 10807 * If the device FLASH isn't large enough to hold a Firmware 10808 * Configuration File, return an error. 10809 */ 10810 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 10811 return -ENOSPC; 10812 10813 return FLASH_BOOTCFG_START; 10814} 10815 10816int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 10817{ 10818 int ret, i, n, cfg_addr; 10819 unsigned int addr; 10820 unsigned int flash_cfg_start_sec; 10821 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10822 10823 cfg_addr = t4_flash_bootcfg_addr(adap); 10824 if (cfg_addr < 0) 10825 return cfg_addr; 10826 10827 addr = cfg_addr; 10828 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10829 10830 if (size > FLASH_BOOTCFG_MAX_SIZE) { 10831 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 10832 FLASH_BOOTCFG_MAX_SIZE); 10833 return -EFBIG; 10834 } 10835 10836 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 10837 sf_sec_size); 10838 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10839 flash_cfg_start_sec + i - 1); 10840 10841 /* 10842 * If size == 0 then we're simply erasing the FLASH sectors associated 10843 * with the on-adapter OptionROM Configuration File. 10844 */ 10845 if (ret || size == 0) 10846 goto out; 10847 10848 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10849 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10850 if ( (size - i) < SF_PAGE_SIZE) 10851 n = size - i; 10852 else 10853 n = SF_PAGE_SIZE; 10854 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 10855 if (ret) 10856 goto out; 10857 10858 addr += SF_PAGE_SIZE; 10859 cfg_data += SF_PAGE_SIZE; 10860 } 10861 10862out: 10863 if (ret) 10864 CH_ERR(adap, "boot config data %s failed %d\n", 10865 (size == 0 ? "clear" : "download"), ret); 10866 return ret; 10867} 10868 10869/** 10870 * t4_set_filter_cfg - set up filter mode/mask and ingress config. 10871 * @adap: the adapter 10872 * @mode: a bitmap selecting which optional filter components to enable 10873 * @mask: a bitmap selecting which components to enable in filter mask 10874 * @vnic_mode: the ingress config/vnic mode setting 10875 * 10876 * Sets the filter mode and mask by selecting the optional components to 10877 * enable in filter tuples. Returns 0 on success and a negative error if 10878 * the requested mode needs more bits than are available for optional 10879 * components. The filter mask must be a subset of the filter mode. 10880 */ 10881int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode) 10882{ 10883 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 10884 int i, nbits, rc; 10885 uint32_t param, val; 10886 uint16_t fmode, fmask; 10887 const int maxbits = adap->chip_params->filter_opt_len; 10888 10889 if (mode != -1 || mask != -1) { 10890 if (mode != -1) { 10891 fmode = mode; 10892 nbits = 0; 10893 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10894 if (fmode & (1 << i)) 10895 nbits += width[i]; 10896 } 10897 if (nbits > maxbits) { 10898 CH_ERR(adap, "optional fields in the filter " 10899 "mode (0x%x) add up to %d bits " 10900 "(must be <= %db). Remove some fields and " 10901 "try again.\n", fmode, nbits, maxbits); 10902 return -E2BIG; 10903 } 10904 10905 /* 10906 * Hardware wants the bits to be maxed out. Keep 10907 * setting them until there's no room for more. 10908 */ 10909 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10910 if (fmode & (1 << i)) 10911 continue; 10912 if (nbits + width[i] <= maxbits) { 10913 fmode |= 1 << i; 10914 nbits += width[i]; 10915 if (nbits == maxbits) 10916 break; 10917 } 10918 } 10919 10920 fmask = fmode & adap->params.tp.filter_mask; 10921 if (fmask != adap->params.tp.filter_mask) { 10922 CH_WARN(adap, 10923 "filter mask will be changed from 0x%x to " 10924 "0x%x to comply with the filter mode (0x%x).\n", 10925 adap->params.tp.filter_mask, fmask, fmode); 10926 } 10927 } else { 10928 fmode = adap->params.tp.filter_mode; 10929 fmask = mask; 10930 if ((fmode | fmask) != fmode) { 10931 CH_ERR(adap, 10932 "filter mask (0x%x) must be a subset of " 10933 "the filter mode (0x%x).\n", fmask, fmode); 10934 return -EINVAL; 10935 } 10936 } 10937 10938 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10939 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10940 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 10941 val = V_FW_PARAMS_PARAM_FILTER_MODE(fmode) | 10942 V_FW_PARAMS_PARAM_FILTER_MASK(fmask); 10943 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 10944 &val); 10945 if (rc < 0) 10946 return rc; 10947 } 10948 10949 if (vnic_mode != -1) { 10950 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10951 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10952 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 10953 val = vnic_mode; 10954 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 10955 &val); 10956 if (rc < 0) 10957 return rc; 10958 } 10959 10960 /* Refresh. */ 10961 read_filter_mode_and_ingress_config(adap); 10962 10963 return 0; 10964} 10965 10966/** 10967 * t4_clr_port_stats - clear port statistics 10968 * @adap: the adapter 10969 * @idx: the port index 10970 * 10971 * Clear HW statistics for the given port. 10972 */ 10973void t4_clr_port_stats(struct adapter *adap, int idx) 10974{ 10975 unsigned int i; 10976 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 10977 u32 port_base_addr; 10978 10979 if (is_t4(adap)) 10980 port_base_addr = PORT_BASE(idx); 10981 else 10982 port_base_addr = T5_PORT_BASE(idx); 10983 10984 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 10985 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 10986 t4_write_reg(adap, port_base_addr + i, 0); 10987 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 10988 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 10989 t4_write_reg(adap, port_base_addr + i, 0); 10990 for (i = 0; i < 4; i++) 10991 if (bgmap & (1 << i)) { 10992 t4_write_reg(adap, 10993 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 10994 t4_write_reg(adap, 10995 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 10996 } 10997} 10998 10999/** 11000 * t4_i2c_io - read/write I2C data from adapter 11001 * @adap: the adapter 11002 * @port: Port number if per-port device; <0 if not 11003 * @devid: per-port device ID or absolute device ID 11004 * @offset: byte offset into device I2C space 11005 * @len: byte length of I2C space data 11006 * @buf: buffer in which to return I2C data for read 11007 * buffer which holds the I2C data for write 11008 * @write: if true, do a write; else do a read 11009 * Reads/Writes the I2C data from/to the indicated device and location. 11010 */ 11011int t4_i2c_io(struct adapter *adap, unsigned int mbox, 11012 int port, unsigned int devid, 11013 unsigned int offset, unsigned int len, 11014 u8 *buf, bool write) 11015{ 11016 struct fw_ldst_cmd ldst_cmd, ldst_rpl; 11017 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data); 11018 int ret = 0; 11019 11020 if (len > I2C_PAGE_SIZE) 11021 return -EINVAL; 11022 11023 /* Dont allow reads that spans multiple pages */ 11024 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE) 11025 return -EINVAL; 11026 11027 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 11028 ldst_cmd.op_to_addrspace = 11029 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11030 F_FW_CMD_REQUEST | 11031 (write ? F_FW_CMD_WRITE : F_FW_CMD_READ) | 11032 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C)); 11033 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 11034 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port); 11035 ldst_cmd.u.i2c.did = devid; 11036 11037 while (len > 0) { 11038 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max; 11039 11040 ldst_cmd.u.i2c.boffset = offset; 11041 ldst_cmd.u.i2c.blen = i2c_len; 11042 11043 if (write) 11044 memcpy(ldst_cmd.u.i2c.data, buf, i2c_len); 11045 11046 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd), 11047 write ? NULL : &ldst_rpl); 11048 if (ret) 11049 break; 11050 11051 if (!write) 11052 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len); 11053 offset += i2c_len; 11054 buf += i2c_len; 11055 len -= i2c_len; 11056 } 11057 11058 return ret; 11059} 11060 11061int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 11062 int port, unsigned int devid, 11063 unsigned int offset, unsigned int len, 11064 u8 *buf) 11065{ 11066 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false); 11067} 11068 11069int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 11070 int port, unsigned int devid, 11071 unsigned int offset, unsigned int len, 11072 u8 *buf) 11073{ 11074 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true); 11075} 11076 11077/** 11078 * t4_sge_ctxt_rd - read an SGE context through FW 11079 * @adap: the adapter 11080 * @mbox: mailbox to use for the FW command 11081 * @cid: the context id 11082 * @ctype: the context type 11083 * @data: where to store the context data 11084 * 11085 * Issues a FW command through the given mailbox to read an SGE context. 11086 */ 11087int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 11088 enum ctxt_type ctype, u32 *data) 11089{ 11090 int ret; 11091 struct fw_ldst_cmd c; 11092 11093 if (ctype == CTXT_EGRESS) 11094 ret = FW_LDST_ADDRSPC_SGE_EGRC; 11095 else if (ctype == CTXT_INGRESS) 11096 ret = FW_LDST_ADDRSPC_SGE_INGC; 11097 else if (ctype == CTXT_FLM) 11098 ret = FW_LDST_ADDRSPC_SGE_FLMC; 11099 else 11100 ret = FW_LDST_ADDRSPC_SGE_CONMC; 11101 11102 memset(&c, 0, sizeof(c)); 11103 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11104 F_FW_CMD_REQUEST | F_FW_CMD_READ | 11105 V_FW_LDST_CMD_ADDRSPACE(ret)); 11106 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 11107 c.u.idctxt.physid = cpu_to_be32(cid); 11108 11109 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11110 if (ret == 0) { 11111 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 11112 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 11113 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 11114 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 11115 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 11116 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 11117 } 11118 return ret; 11119} 11120 11121/** 11122 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 11123 * @adap: the adapter 11124 * @cid: the context id 11125 * @ctype: the context type 11126 * @data: where to store the context data 11127 * 11128 * Reads an SGE context directly, bypassing FW. This is only for 11129 * debugging when FW is unavailable. 11130 */ 11131int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 11132 u32 *data) 11133{ 11134 int i, ret; 11135 11136 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 11137 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 11138 if (!ret) 11139 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 11140 *data++ = t4_read_reg(adap, i); 11141 return ret; 11142} 11143 11144int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 11145 int sleep_ok) 11146{ 11147 struct fw_sched_cmd cmd; 11148 11149 memset(&cmd, 0, sizeof(cmd)); 11150 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11151 F_FW_CMD_REQUEST | 11152 F_FW_CMD_WRITE); 11153 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11154 11155 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 11156 cmd.u.config.type = type; 11157 cmd.u.config.minmaxen = minmaxen; 11158 11159 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11160 NULL, sleep_ok); 11161} 11162 11163int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 11164 int rateunit, int ratemode, int channel, int cl, 11165 int minrate, int maxrate, int weight, int pktsize, 11166 int burstsize, int sleep_ok) 11167{ 11168 struct fw_sched_cmd cmd; 11169 11170 memset(&cmd, 0, sizeof(cmd)); 11171 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11172 F_FW_CMD_REQUEST | 11173 F_FW_CMD_WRITE); 11174 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11175 11176 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11177 cmd.u.params.type = type; 11178 cmd.u.params.level = level; 11179 cmd.u.params.mode = mode; 11180 cmd.u.params.ch = channel; 11181 cmd.u.params.cl = cl; 11182 cmd.u.params.unit = rateunit; 11183 cmd.u.params.rate = ratemode; 11184 cmd.u.params.min = cpu_to_be32(minrate); 11185 cmd.u.params.max = cpu_to_be32(maxrate); 11186 cmd.u.params.weight = cpu_to_be16(weight); 11187 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11188 cmd.u.params.burstsize = cpu_to_be16(burstsize); 11189 11190 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11191 NULL, sleep_ok); 11192} 11193 11194int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 11195 unsigned int maxrate, int sleep_ok) 11196{ 11197 struct fw_sched_cmd cmd; 11198 11199 memset(&cmd, 0, sizeof(cmd)); 11200 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11201 F_FW_CMD_REQUEST | 11202 F_FW_CMD_WRITE); 11203 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11204 11205 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11206 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11207 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 11208 cmd.u.params.ch = channel; 11209 cmd.u.params.rate = ratemode; /* REL or ABS */ 11210 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 11211 11212 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11213 NULL, sleep_ok); 11214} 11215 11216int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 11217 int weight, int sleep_ok) 11218{ 11219 struct fw_sched_cmd cmd; 11220 11221 if (weight < 0 || weight > 100) 11222 return -EINVAL; 11223 11224 memset(&cmd, 0, sizeof(cmd)); 11225 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11226 F_FW_CMD_REQUEST | 11227 F_FW_CMD_WRITE); 11228 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11229 11230 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11231 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11232 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 11233 cmd.u.params.ch = channel; 11234 cmd.u.params.cl = cl; 11235 cmd.u.params.weight = cpu_to_be16(weight); 11236 11237 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11238 NULL, sleep_ok); 11239} 11240 11241int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 11242 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 11243{ 11244 struct fw_sched_cmd cmd; 11245 11246 memset(&cmd, 0, sizeof(cmd)); 11247 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11248 F_FW_CMD_REQUEST | 11249 F_FW_CMD_WRITE); 11250 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11251 11252 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11253 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11254 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 11255 cmd.u.params.mode = mode; 11256 cmd.u.params.ch = channel; 11257 cmd.u.params.cl = cl; 11258 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 11259 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 11260 cmd.u.params.max = cpu_to_be32(maxrate); 11261 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11262 11263 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11264 NULL, sleep_ok); 11265} 11266 11267/* 11268 * t4_config_watchdog - configure (enable/disable) a watchdog timer 11269 * @adapter: the adapter 11270 * @mbox: mailbox to use for the FW command 11271 * @pf: the PF owning the queue 11272 * @vf: the VF owning the queue 11273 * @timeout: watchdog timeout in ms 11274 * @action: watchdog timer / action 11275 * 11276 * There are separate watchdog timers for each possible watchdog 11277 * action. Configure one of the watchdog timers by setting a non-zero 11278 * timeout. Disable a watchdog timer by using a timeout of zero. 11279 */ 11280int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 11281 unsigned int pf, unsigned int vf, 11282 unsigned int timeout, unsigned int action) 11283{ 11284 struct fw_watchdog_cmd wdog; 11285 unsigned int ticks; 11286 11287 /* 11288 * The watchdog command expects a timeout in units of 10ms so we need 11289 * to convert it here (via rounding) and force a minimum of one 10ms 11290 * "tick" if the timeout is non-zero but the conversion results in 0 11291 * ticks. 11292 */ 11293 ticks = (timeout + 5)/10; 11294 if (timeout && !ticks) 11295 ticks = 1; 11296 11297 memset(&wdog, 0, sizeof wdog); 11298 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 11299 F_FW_CMD_REQUEST | 11300 F_FW_CMD_WRITE | 11301 V_FW_PARAMS_CMD_PFN(pf) | 11302 V_FW_PARAMS_CMD_VFN(vf)); 11303 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 11304 wdog.timeout = cpu_to_be32(ticks); 11305 wdog.action = cpu_to_be32(action); 11306 11307 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 11308} 11309 11310int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 11311{ 11312 struct fw_devlog_cmd devlog_cmd; 11313 int ret; 11314 11315 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11316 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11317 F_FW_CMD_REQUEST | F_FW_CMD_READ); 11318 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11319 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11320 sizeof(devlog_cmd), &devlog_cmd); 11321 if (ret) 11322 return ret; 11323 11324 *level = devlog_cmd.level; 11325 return 0; 11326} 11327 11328int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 11329{ 11330 struct fw_devlog_cmd devlog_cmd; 11331 11332 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11333 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11334 F_FW_CMD_REQUEST | 11335 F_FW_CMD_WRITE); 11336 devlog_cmd.level = level; 11337 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11338 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11339 sizeof(devlog_cmd), &devlog_cmd); 11340} 11341 11342int t4_configure_add_smac(struct adapter *adap) 11343{ 11344 unsigned int param, val; 11345 int ret = 0; 11346 11347 adap->params.smac_add_support = 0; 11348 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11349 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_ADD_SMAC)); 11350 /* Query FW to check if FW supports adding source mac address 11351 * to TCAM feature or not. 11352 * If FW returns 1, driver can use this feature and driver need to send 11353 * FW_PARAMS_PARAM_DEV_ADD_SMAC write command with value 1 to 11354 * enable adding smac to TCAM. 11355 */ 11356 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11357 if (ret) 11358 return ret; 11359 11360 if (val == 1) { 11361 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 11362 ¶m, &val); 11363 if (!ret) 11364 /* Firmware allows adding explicit TCAM entries. 11365 * Save this internally. 11366 */ 11367 adap->params.smac_add_support = 1; 11368 } 11369 11370 return ret; 11371} 11372 11373int t4_configure_ringbb(struct adapter *adap) 11374{ 11375 unsigned int param, val; 11376 int ret = 0; 11377 11378 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11379 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RING_BACKBONE)); 11380 /* Query FW to check if FW supports ring switch feature or not. 11381 * If FW returns 1, driver can use this feature and driver need to send 11382 * FW_PARAMS_PARAM_DEV_RING_BACKBONE write command with value 1 to 11383 * enable the ring backbone configuration. 11384 */ 11385 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11386 if (ret < 0) { 11387 CH_ERR(adap, "Querying FW using Ring backbone params command failed, err=%d\n", 11388 ret); 11389 goto out; 11390 } 11391 11392 if (val != 1) { 11393 CH_ERR(adap, "FW doesnot support ringbackbone features\n"); 11394 goto out; 11395 } 11396 11397 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11398 if (ret < 0) { 11399 CH_ERR(adap, "Could not set Ringbackbone, err= %d\n", 11400 ret); 11401 goto out; 11402 } 11403 11404out: 11405 return ret; 11406} 11407 11408/* 11409 * t4_set_vlan_acl - Set a VLAN id for the specified VF 11410 * @adapter: the adapter 11411 * @mbox: mailbox to use for the FW command 11412 * @vf: one of the VFs instantiated by the specified PF 11413 * @vlan: The vlanid to be set 11414 * 11415 */ 11416int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 11417 u16 vlan) 11418{ 11419 struct fw_acl_vlan_cmd vlan_cmd; 11420 unsigned int enable; 11421 11422 enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0); 11423 memset(&vlan_cmd, 0, sizeof(vlan_cmd)); 11424 vlan_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_VLAN_CMD) | 11425 F_FW_CMD_REQUEST | 11426 F_FW_CMD_WRITE | 11427 F_FW_CMD_EXEC | 11428 V_FW_ACL_VLAN_CMD_PFN(adap->pf) | 11429 V_FW_ACL_VLAN_CMD_VFN(vf)); 11430 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd)); 11431 /* Drop all packets that donot match vlan id */ 11432 vlan_cmd.dropnovlan_fm = (enable 11433 ? (F_FW_ACL_VLAN_CMD_DROPNOVLAN | 11434 F_FW_ACL_VLAN_CMD_FM) 11435 : 0); 11436 if (enable != 0) { 11437 vlan_cmd.nvlan = 1; 11438 vlan_cmd.vlanid[0] = cpu_to_be16(vlan); 11439 } 11440 11441 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL); 11442} 11443 11444/** 11445 * t4_del_mac - Removes the exact-match filter for a MAC address 11446 * @adap: the adapter 11447 * @mbox: mailbox to use for the FW command 11448 * @viid: the VI id 11449 * @addr: the MAC address value 11450 * @smac: if true, delete from only the smac region of MPS 11451 * 11452 * Modifies an exact-match filter and sets it to the new MAC address if 11453 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11454 * latter case the address is added persistently if @persist is %true. 11455 * 11456 * Returns a negative error number or the index of the filter with the new 11457 * MAC value. Note that this index may differ from @idx. 11458 */ 11459int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11460 const u8 *addr, bool smac) 11461{ 11462 int ret; 11463 struct fw_vi_mac_cmd c; 11464 struct fw_vi_mac_exact *p = c.u.exact; 11465 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11466 11467 memset(&c, 0, sizeof(c)); 11468 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11469 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11470 V_FW_VI_MAC_CMD_VIID(viid)); 11471 c.freemacs_to_len16 = cpu_to_be32( 11472 V_FW_CMD_LEN16(1) | 11473 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11474 11475 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11476 p->valid_to_idx = cpu_to_be16( 11477 F_FW_VI_MAC_CMD_VALID | 11478 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 11479 11480 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11481 if (ret == 0) { 11482 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11483 if (ret < max_mac_addr) 11484 return -ENOMEM; 11485 } 11486 11487 return ret; 11488} 11489 11490/** 11491 * t4_add_mac - Adds an exact-match filter for a MAC address 11492 * @adap: the adapter 11493 * @mbox: mailbox to use for the FW command 11494 * @viid: the VI id 11495 * @idx: index of existing filter for old value of MAC address, or -1 11496 * @addr: the new MAC address value 11497 * @persist: whether a new MAC allocation should be persistent 11498 * @add_smt: if true also add the address to the HW SMT 11499 * @smac: if true, update only the smac region of MPS 11500 * 11501 * Modifies an exact-match filter and sets it to the new MAC address if 11502 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11503 * latter case the address is added persistently if @persist is %true. 11504 * 11505 * Returns a negative error number or the index of the filter with the new 11506 * MAC value. Note that this index may differ from @idx. 11507 */ 11508int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11509 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac) 11510{ 11511 int ret, mode; 11512 struct fw_vi_mac_cmd c; 11513 struct fw_vi_mac_exact *p = c.u.exact; 11514 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11515 11516 if (idx < 0) /* new allocation */ 11517 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 11518 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 11519 11520 memset(&c, 0, sizeof(c)); 11521 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11522 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11523 V_FW_VI_MAC_CMD_VIID(viid)); 11524 c.freemacs_to_len16 = cpu_to_be32( 11525 V_FW_CMD_LEN16(1) | 11526 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11527 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 11528 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 11529 V_FW_VI_MAC_CMD_IDX(idx)); 11530 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11531 11532 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11533 if (ret == 0) { 11534 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11535 if (ret >= max_mac_addr) 11536 return -ENOMEM; 11537 if (smt_idx) { 11538 /* Does fw supports returning smt_idx? */ 11539 if (adap->params.viid_smt_extn_support) 11540 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 11541 else { 11542 /* In T4/T5, SMT contains 256 SMAC entries 11543 * organized in 128 rows of 2 entries each. 11544 * In T6, SMT contains 256 SMAC entries in 11545 * 256 rows. 11546 */ 11547 if (chip_id(adap) <= CHELSIO_T5) 11548 *smt_idx = ((viid & M_FW_VIID_VIN) << 1); 11549 else 11550 *smt_idx = (viid & M_FW_VIID_VIN); 11551 } 11552 } 11553 } 11554 11555 return ret; 11556} 11557