1/*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2010 Broadcom Corporation 4 * 5 * This file was derived from the sbconfig.h header distributed with 6 * Broadcom's initial brcm80211 Linux driver release, as 7 * contributed to the Linux staging repository. 8 * 9 * Permission to use, copy, modify, and/or distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 16 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 18 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 19 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 * $FreeBSD$ 22 */ 23 24#ifndef _BHND_SIBA_SIBAREG_ 25#define _BHND_SIBA_SIBAREG_ 26 27#include <dev/bhnd/bhndreg.h> 28 29/* 30 * Broadcom SIBA Configuration Space Registers. 31 * 32 * Backplane configuration registers common to siba(4) core register 33 * blocks. 34 */ 35 36/** 37 * Extract a config attribute by applying _MASK and _SHIFT defines. 38 * 39 * @param _reg The register value containing the desired attribute 40 * @param _attr The BCMA EROM attribute name (e.g. ENTRY_ISVALID), to be 41 * concatenated with the `SB` prefix and `_MASK`/`_SHIFT` suffixes. 42 */ 43#define SIBA_REG_GET(_entry, _attr) \ 44 ((_entry & SIBA_ ## _attr ## _MASK) \ 45 >> SIBA_ ## _attr ## _SHIFT) 46 47#define SIBA_ENUM_ADDR BHND_DEFAULT_CHIPC_ADDR /**< enumeration space */ 48#define SIBA_ENUM_SIZE 0x00100000 /**< size of the enumeration space */ 49#define SIBA_CORE_SIZE BHND_DEFAULT_CORE_SIZE /**< per-core register block size */ 50#define SIBA_MAX_INTR 32 /**< maximum number of backplane interrupt vectors */ 51#define SIBA_MAX_CORES \ 52 (SIBA_ENUM_SIZE/SIBA_CORE_SIZE) /**< Maximum number of cores */ 53 54/** Evaluates to the bus address offset of the @p idx core register block */ 55#define SIBA_CORE_OFFSET(idx) ((idx) * SIBA_CORE_SIZE) 56 57/** Evaluates to the bus address of the @p idx core register block */ 58#define SIBA_CORE_ADDR(idx) (SIBA_ENUM_ADDR + SIBA_CORE_OFFSET(idx)) 59 60/* 61 * Sonics configuration registers are mapped to each core's enumeration 62 * space, at the end of the 4kb device register block, in reverse 63 * order: 64 * 65 * [0x0000-0x0dff] core registers 66 * [0x0e00-0x0eff] SIBA_R1 registers (sonics >= 2.3) 67 * [0x0f00-0x0fff] SIBA_R0 registers 68 */ 69 70#define SIBA_CFG0_OFFSET 0xf00 /**< first configuration block */ 71#define SIBA_CFG1_OFFSET 0xe00 /**< second configuration block (sonics >= 2.3) */ 72#define SIBA_CFG_SIZE 0x100 /**< cfg register block size */ 73 74/* Return the SIBA_CORE_ADDR-relative offset for the given siba configuration 75 * register block; configuration blocks are allocated starting at 76 * SIBA_CFG0_OFFSET, growing downwards. */ 77#define SIBA_CFG_OFFSET(_n) (SIBA_CFG0_OFFSET - ((_n) * SIBA_CFG_SIZE)) 78 79/* Return the SIBA_CORE_ADDR-relative offset for a SIBA_CFG* register. */ 80#define SB0_REG_ABS(off) ((off) + SIBA_CFG0_OFFSET) 81#define SB1_REG_ABS(off) ((off) + SIBA_CFG1_OFFSET) 82 83/* SIBA_CFG0 registers */ 84#define SIBA_CFG0_IPSFLAG 0x08 /**< initiator port ocp slave flag */ 85#define SIBA_CFG0_TPSFLAG 0x18 /**< target port ocp slave flag */ 86#define SIBA_CFG0_TMERRLOGA 0x48 /**< sonics >= 2.3 */ 87#define SIBA_CFG0_TMERRLOG 0x50 /**< sonics >= 2.3 */ 88#define SIBA_CFG0_ADMATCH3 0x60 /**< address match3 */ 89#define SIBA_CFG0_ADMATCH2 0x68 /**< address match2 */ 90#define SIBA_CFG0_ADMATCH1 0x70 /**< address match1 */ 91#define SIBA_CFG0_IMSTATE 0x90 /**< initiator agent state */ 92#define SIBA_CFG0_INTVEC 0x94 /**< interrupt mask */ 93#define SIBA_CFG0_TMSTATELOW 0x98 /**< target state */ 94#define SIBA_CFG0_TMSTATEHIGH 0x9c /**< target state */ 95#define SIBA_CFG0_BWA0 0xa0 /**< bandwidth allocation table0 */ 96#define SIBA_CFG0_IMCONFIGLOW 0xa8 /**< initiator configuration */ 97#define SIBA_CFG0_IMCONFIGHIGH 0xac /**< initiator configuration */ 98#define SIBA_CFG0_ADMATCH0 0xb0 /**< address match0 */ 99#define SIBA_CFG0_TMCONFIGLOW 0xb8 /**< target configuration */ 100#define SIBA_CFG0_TMCONFIGHIGH 0xbc /**< target configuration */ 101#define SIBA_CFG0_BCONFIG 0xc0 /**< broadcast configuration */ 102#define SIBA_CFG0_BSTATE 0xc8 /**< broadcast state */ 103#define SIBA_CFG0_ACTCNFG 0xd8 /**< activate configuration */ 104#define SIBA_CFG0_FLAGST 0xe8 /**< current sbflags */ 105#define SIBA_CFG0_IDLOW 0xf8 /**< identification */ 106#define SIBA_CFG0_IDHIGH 0xfc /**< identification */ 107 108/* SIBA_CFG1 registers (sonics >= 2.3) */ 109#define SIBA_CFG1_IMERRLOGA 0xa8 /**< (sonics >= 2.3) */ 110#define SIBA_CFG1_IMERRLOG 0xb0 /**< sbtmerrlog (sonics >= 2.3) */ 111#define SIBA_CFG1_TMPORTCONNID0 0xd8 /**< sonics >= 2.3 */ 112#define SIBA_CFG1_TMPORTLOCK0 0xf8 /**< sonics >= 2.3 */ 113 114/* sbipsflag */ 115#define SIBA_IPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */ 116#define SIBA_IPS_INT1_SHIFT 0 117#define SIBA_IPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */ 118#define SIBA_IPS_INT2_SHIFT 8 119#define SIBA_IPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */ 120#define SIBA_IPS_INT3_SHIFT 16 121#define SIBA_IPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */ 122#define SIBA_IPS_INT4_SHIFT 24 123 124#define SIBA_IPS_INT_SHIFT(_i) ((_i - 1) * 8) 125#define SIBA_IPS_INT_MASK(_i) (SIBA_IPS_INT1_MASK << SIBA_IPS_INT_SHIFT(_i)) 126 127/* sbtpsflag */ 128#define SIBA_TPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */ 129#define SIBA_TPS_NUM0_SHIFT 0 130#define SIBA_TPS_F0EN0 0x40 /* interrupt is always sent on the backplane */ 131 132/* sbtmerrlog */ 133#define SIBA_TMEL_CM 0x00000007 /* command */ 134#define SIBA_TMEL_CI 0x0000ff00 /* connection id */ 135#define SIBA_TMEL_EC 0x0f000000 /* error code */ 136#define SIBA_TMEL_ME 0x80000000 /* multiple error */ 137 138/* sbimstate */ 139#define SIBA_IM_PC 0xf /* pipecount */ 140#define SIBA_IM_AP_MASK 0x30 /* arbitration policy */ 141#define SIBA_IM_AP_BOTH 0x00 /* use both timeslaces and token */ 142#define SIBA_IM_AP_TS 0x10 /* use timesliaces only */ 143#define SIBA_IM_AP_TK 0x20 /* use token only */ 144#define SIBA_IM_AP_RSV 0x30 /* reserved */ 145#define SIBA_IM_IBE 0x20000 /* inbanderror */ 146#define SIBA_IM_TO 0x40000 /* timeout */ 147#define SIBA_IM_BY 0x01800000 /* busy (sonics >= 2.3) */ 148#define SIBA_IM_RJ 0x02000000 /* reject (sonics >= 2.3) */ 149 150/* sbtmstatelow */ 151#define SIBA_TML_RESET 0x0001 /* reset */ 152#define SIBA_TML_REJ_MASK 0x0006 /* reject field */ 153#define SIBA_TML_REJ 0x0002 /* reject */ 154#define SIBA_TML_TMPREJ 0x0004 /* temporary reject, for error recovery */ 155#define SIBA_TML_SICF_MASK 0xFFFF0000 /* core IOCTL flags */ 156#define SIBA_TML_SICF_SHIFT 16 157 158/* sbtmstatehigh */ 159#define SIBA_TMH_SERR 0x0001 /* serror */ 160#define SIBA_TMH_INT 0x0002 /* interrupt */ 161#define SIBA_TMH_BUSY 0x0004 /* busy */ 162#define SIBA_TMH_TO 0x0020 /* timeout (sonics >= 2.3) */ 163#define SIBA_TMH_SISF_MASK 0xFFFF0000 /* core IOST flags */ 164#define SIBA_TMH_SISF_SHIFT 16 165 166/* sbbwa0 */ 167#define SIBA_BWA_TAB0_MASK 0xffff /* lookup table 0 */ 168#define SIBA_BWA_TAB1_MASK 0xffff /* lookup table 1 */ 169#define SIBA_BWA_TAB1_SHIFT 16 170 171/* sbimconfiglow */ 172#define SIBA_IMCL_STO_MASK 0x7 /* service timeout */ 173#define SIBA_IMCL_RTO_MASK 0x70 /* request timeout */ 174#define SIBA_IMCL_RTO_SHIFT 4 175#define SIBA_IMCL_CID_MASK 0xff0000 /* connection id */ 176#define SIBA_IMCL_CID_SHIFT 16 177 178/* sbimconfighigh */ 179#define SIBA_IMCH_IEM_MASK 0xc /* inband error mode */ 180#define SIBA_IMCH_TEM_MASK 0x30 /* timeout error mode */ 181#define SIBA_IMCH_TEM_SHIFT 4 182#define SIBA_IMCH_BEM_MASK 0xc0 /* bus error mode */ 183#define SIBA_IMCH_BEM_SHIFT 6 184 185/* sbadmatch0-4 */ 186#define SIBA_AM_TYPE_MASK 0x3 /* address type */ 187#define SIBA_AM_TYPE_SHIFT 0x0 188#define SIBA_AM_AD64 0x4 /* reserved */ 189#define SIBA_AM_ADINT0_MASK 0xf8 /* type0 size */ 190#define SIBA_AM_ADINT0_SHIFT 3 191#define SIBA_AM_ADINT1_MASK 0x1f8 /* type1 size */ 192#define SIBA_AM_ADINT1_SHIFT 3 193#define SIBA_AM_ADINT2_MASK 0x1f8 /* type2 size */ 194#define SIBA_AM_ADINT2_SHIFT 3 195#define SIBA_AM_ADEN 0x400 /* enable */ 196#define SIBA_AM_ADNEG 0x800 /* negative decode */ 197#define SIBA_AM_BASE0_MASK 0xffffff00 /* type0 base address */ 198#define SIBA_AM_BASE0_SHIFT 8 199#define SIBA_AM_BASE1_MASK 0xfffff000 /* type1 base address for the core */ 200#define SIBA_AM_BASE1_SHIFT 12 201#define SIBA_AM_BASE2_MASK 0xffff0000 /* type2 base address for the core */ 202#define SIBA_AM_BASE2_SHIFT 16 203 204/* sbtmconfiglow */ 205#define SIBA_TMCL_CD_MASK 0xff /* clock divide */ 206#define SIBA_TMCL_CO_MASK 0xf800 /* clock offset */ 207#define SIBA_TMCL_CO_SHIFT 11 208#define SIBA_TMCL_IF_MASK 0xfc0000 /* interrupt flags */ 209#define SIBA_TMCL_IF_SHIFT 18 210#define SIBA_TMCL_IM_MASK 0x3000000 /* interrupt mode */ 211#define SIBA_TMCL_IM_SHIFT 24 212 213/* sbtmconfighigh */ 214#define SIBA_TMCH_BM_MASK 0x3 /* busy mode */ 215#define SIBA_TMCH_RM_MASK 0x3 /* retry mode */ 216#define SIBA_TMCH_RM_SHIFT 2 217#define SIBA_TMCH_SM_MASK 0x30 /* stop mode */ 218#define SIBA_TMCH_SM_SHIFT 4 219#define SIBA_TMCH_EM_MASK 0x300 /* sb error mode */ 220#define SIBA_TMCH_EM_SHIFT 8 221#define SIBA_TMCH_IM_MASK 0xc00 /* int mode */ 222#define SIBA_TMCH_IM_SHIFT 10 223 224/* sbbconfig */ 225#define SIBA_BC_LAT_MASK 0x3 /* sb latency */ 226#define SIBA_BC_MAX0_MASK 0xf0000 /* maxccntr0 */ 227#define SIBA_BC_MAX0_SHIFT 16 228#define SIBA_BC_MAX1_MASK 0xf00000 /* maxccntr1 */ 229#define SIBA_BC_MAX1_SHIFT 20 230 231/* sbbstate */ 232#define SIBA_BS_SRD 0x1 /* st reg disable */ 233#define SIBA_BS_HRD 0x2 /* hold reg disable */ 234 235/* sbidlow */ 236#define SIBA_IDL_CS_MASK 0x3 /* config space */ 237#define SIBA_IDL_CS_SHIFT 0 238#define SIBA_IDL_NRADDR_MASK 0x38 /* # address ranges supported */ 239#define SIBA_IDL_NRADDR_SHIFT 3 240#define SIBA_IDL_SYNCH 0x40 /* sync */ 241#define SIBA_IDL_INIT 0x80 /* initiator */ 242#define SIBA_IDL_MINLAT_MASK 0xf00 /* minimum backplane latency */ 243#define SIBA_IDL_MINLAT_SHIFT 8 244#define SIBA_IDL_MAXLAT_MASK 0xf000 /* maximum backplane latency */ 245#define SIBA_IDL_MAXLAT_SHIFT 12 246#define SIBA_IDL_FIRST_MASK 0x10000 /* this initiator is first */ 247#define SIBA_IDL_FIRST_SHIFT 16 248#define SIBA_IDL_CW_MASK 0xc0000 /* cycle counter width */ 249#define SIBA_IDL_CW_SHIFT 18 250#define SIBA_IDL_TP_MASK 0xf00000 /* target ports */ 251#define SIBA_IDL_TP_SHIFT 20 252#define SIBA_IDL_IP_MASK 0xf000000 /* initiator ports */ 253#define SIBA_IDL_IP_SHIFT 24 254#define SIBA_IDL_SBREV_MASK 0xf0000000 /* sonics backplane revision code */ 255#define SIBA_IDL_SBREV_SHIFT 28 256#define SIBA_IDL_SBREV_2_2 0x0 /* version 2.2 or earlier */ 257#define SIBA_IDL_SBREV_2_3 0x1 /* version 2.3 */ 258 259/* sbidhigh */ 260#define SIBA_IDH_RC_MASK 0x000f /* revision code */ 261#define SIBA_IDH_RCE_MASK 0x7000 /* revision code extension field */ 262#define SIBA_IDH_RCE_SHIFT 8 263#define SIBA_IDH_DEVICE_MASK 0x8ff0 /* core code */ 264#define SIBA_IDH_DEVICE_SHIFT 4 265#define SIBA_IDH_VENDOR_MASK 0xffff0000 /* vendor code */ 266#define SIBA_IDH_VENDOR_SHIFT 16 267 268#define SIBA_IDH_CORE_REV(sbidh) \ 269 (SIBA_REG_GET((sbidh), IDH_RCE) | ((sbidh) & SIBA_IDH_RC_MASK)) 270 271#define SIBA_COMMIT 0xfd8 /* update buffered registers value */ 272 273#endif /* _BHND_SIBA_SIBAREG_ */ 274