1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5 * Copyright (c) 2010 Broadcom Corporation 6 * All rights reserved. 7 * 8 * This file is derived from the sbchipc.h header contributed by Broadcom 9 * to to the Linux staging repository, as well as later revisions of sbchipc.h 10 * distributed with the Asus RT-N16 firmware source code release. 11 * 12 * Permission to use, copy, modify, and/or distribute this software for any 13 * purpose with or without fee is hereby granted, provided that the above 14 * copyright notice and this permission notice appear in all copies. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 17 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 20 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 21 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 22 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 23 * 24 * $FreeBSD$ 25 */ 26 27#ifndef _BHND_CORES_PMU_BHND_PMUREG_H_ 28#define _BHND_CORES_PMU_BHND_PMUREG_H_ 29 30#define BHND_PMU_GET_FLAG(_value, _flag) \ 31 (((_value) & _flag) != 0) 32#define BHND_PMU_GET_BITS(_value, _field) \ 33 (((_value) & _field ## _MASK) >> _field ## _SHIFT) 34#define BHND_PMU_SET_BITS(_value, _field) \ 35 (((_value) << _field ## _SHIFT) & _field ## _MASK) 36 37#define BHND_PMU_ILP_CLOCK 32000 /**< default ILP freq */ 38#define BHND_PMU_ALP_CLOCK 20000000 /**< default ALP freq */ 39#define BHND_PMU_HT_CLOCK 80000000 /**< default HT freq */ 40 41/** 42 * Common per-core clock control/status register available on PMU-equipped 43 * devices. 44 */ 45#define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */ 46 47/* 48 * BHND_CLK_CTL_ST register 49 * 50 * Clock Mode Name Description 51 * High Throughput (HT) Full bandwidth, low latency. Generally supplied 52 * from PLL. 53 * Active Low Power (ALP) Register access, low speed DMA. 54 * Idle Low Power (ILP) No interconnect activity, or if long latency 55 * is permitted. 56 */ 57#define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */ 58#define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */ 59#define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */ 60#define BHND_CCS_FORCE_MASK 0x0000000F 61 62#define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */ 63#define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */ 64#define BHND_CCS_AREQ_MASK 0x00000018 65 66#define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */ 67 68#define BHND_CCS_ERSRC_REQ_MASK 0x00000700 /**< external resource requests */ 69#define BHND_CCS_ERSRC_REQ_SHIFT 8 70#define BHND_CCS_ERSRC_MAX 2 /**< maximum ERSRC value (corresponding to bits 0-2) */ 71 72#define BHND_CCS_ALPAVAIL 0x00010000 /**< ALP is available */ 73#define BHND_CCS_HTAVAIL 0x00020000 /**< HT is available */ 74#define BHND_CCS_AVAIL_MASK 0x00030000 75 76#define BHND_CCS_BP_ON_APL 0x00040000 /**< RO: Backplane is running on ALP clock */ 77#define BHND_CCS_BP_ON_HT 0x00080000 /**< RO: Backplane is running on HT clock */ 78#define BHND_CCS_ERSRC_STS_MASK 0x07000000 /**< external resource status */ 79#define BHND_CCS_ERSRC_STS_SHIFT 24 80 81#define BHND_CCS0_HTAVAIL 0x00010000 /**< HT avail in chipc and pcmcia on 4328a0 */ 82#define BHND_CCS0_ALPAVAIL 0x00020000 /**< ALP avail in chipc and pcmcia on 4328a0 */ 83 84/* PMU registers */ 85#define BHND_PMU_CTRL 0x600 86#define BHND_PMU_CTRL_ILP_DIV_MASK 0xffff0000 87#define BHND_PMU_CTRL_ILP_DIV_SHIFT 16 88#define BHND_PMU_CTRL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */ 89#define BHND_PMU_CTRL_NOILP_ON_WAIT 0x00000200 /* rev 1 */ 90#define BHND_PMU_CTRL_HT_REQ_EN 0x00000100 91#define BHND_PMU_CTRL_ALP_REQ_EN 0x00000080 92#define BHND_PMU_CTRL_XTALFREQ_MASK 0x0000007c 93#define BHND_PMU_CTRL_XTALFREQ_SHIFT 2 94#define BHND_PMU_CTRL_ILP_DIV_EN 0x00000002 95#define BHND_PMU_CTRL_LPO_SEL 0x00000001 96#define BHND_PMU_CAP 0x604 97#define BHND_PMU_CAP_REV_MASK 0x000000ff 98#define BHND_PMU_CAP_REV_SHIFT 0 99#define BHND_PMU_CAP_RC_MASK 0x00001f00 100#define BHND_PMU_CAP_RC_SHIFT 8 101#define BHND_PMU_CAP_RC_MAX \ 102 (BHND_PMU_CAP_RC_MASK >> BHND_PMU_CAP_RC_SHIFT) 103#define BHND_PMU_CAP_TC_MASK 0x0001e000 104#define BHND_PMU_CAP_TC_SHIFT 13 105#define BHND_PMU_CAP_PC_MASK 0x001e0000 106#define BHND_PMU_CAP_PC_SHIFT 17 107#define BHND_PMU_CAP_VC_MASK 0x01e00000 108#define BHND_PMU_CAP_VC_SHIFT 21 109#define BHND_PMU_CAP_CC_MASK 0x1e000000 110#define BHND_PMU_CAP_CC_SHIFT 25 111#define BHND_PMU_CAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */ 112#define BHND_PMU_CAP5_PC_SHIFT 17 113#define BHND_PMU_CAP5_VC_MASK 0x07c00000 114#define BHND_PMU_CAP5_VC_SHIFT 22 115#define BHND_PMU_CAP5_CC_MASK 0xf8000000 116#define BHND_PMU_CAP5_CC_SHIFT 27 117#define BHND_PMU_ST 0x608 118#define BHND_PMU_ST_EXTLPOAVAIL 0x0100 119#define BHND_PMU_ST_WDRESET 0x0080 120#define BHND_PMU_ST_INTPEND 0x0040 121#define BHND_PMU_ST_SBCLKST 0x0030 122#define BHND_PMU_ST_SBCLKST_ILP 0x0010 123#define BHND_PMU_ST_SBCLKST_ALP 0x0020 124#define BHND_PMU_ST_SBCLKST_HT 0x0030 125#define BHND_PMU_ST_ALPAVAIL 0x0008 126#define BHND_PMU_ST_HTAVAIL 0x0004 127#define BHND_PMU_ST_RESINIT 0x0003 128#define BHND_PMU_RES_STATE 0x60c 129#define BHND_PMU_RES_PENDING 0x610 130#define BHND_PMU_TIMER 0x614 131#define BHND_PMU_MIN_RES_MASK 0x618 132#define BHND_PMU_MAX_RES_MASK 0x61c 133#define BHND_PMU_RES_TABLE_SEL 0x620 134#define BHND_PMU_RES_DEP_MASK 0x624 135#define BHND_PMU_RES_UPDN_TIMER 0x628 136#define BHND_PMU_RES_UPDN_UPTME_MASK 0xFF00 137#define BHND_PMU_RES_UPDN_UPTME_SHIFT 8 138#define BHND_PMU_RES_TIMER 0x62C 139#define BHND_PMU_CLKSTRETCH 0x630 140#define BHND_PMU_CSTRETCH_HT 0xffff0000 141#define BHND_PMU_CSTRETCH_ALP 0x0000ffff 142#define BHND_PMU_WATCHDOG 0x634 143#define BHND_PMU_GPIOSEL 0x638 /* pmu rev >= 1 ? */ 144#define BHND_PMU_GPIOEN 0x63C /* pmu rev >= 1 ? */ 145#define BHND_PMU_RES_REQ_TIMER_SEL 0x640 146#define BHND_PMU_RES_REQ_TIMER 0x644 147#define BHND_PMU_RRQT_TIME_MASK 0x03ff 148#define BHND_PMU_RRQT_INTEN 0x0400 149#define BHND_PMU_RRQT_REQ_ACTIVE 0x0800 150#define BHND_PMU_RRQT_ALP_REQ 0x1000 151#define BHND_PMU_RRQT_HT_REQ 0x2000 152#define BHND_PMU_RES_REQ_MASK 0x648 153#define BHND_PMU_CHIP_CONTROL_ADDR 0x650 154#define BHND_PMU_CHIP_CONTROL_DATA 0x654 155#define BHND_PMU_REG_CONTROL_ADDR 0x658 156#define BHND_PMU_REG_CONTROL_DATA 0x65C 157#define BHND_PMU_PLL_CONTROL_ADDR 0x660 158#define BHND_PMU_PLL_CONTROL_DATA 0x664 159#define BHND_PMU_STRAPOPT 0x668 /* chipc rev >= 28 */ 160#define BHND_PMU_XTALFREQ 0x66C /* pmu rev >= 10 */ 161 162/* PMU resource bit position */ 163#define BHND_PMURES_BIT(bit) (1 << (bit)) 164 165/* PMU resource number limit */ 166#define BHND_PMU_RESNUM_MAX 30 167 168/* PMU chip control0 register */ 169#define BHND_PMU_CHIPCTL0 0 170 171/* PMU chip control1 register */ 172#define BHND_PMU_CHIPCTL1 1 173#define BHND_PMU_CC1_RXC_DLL_BYPASS 0x00010000 174 175#define BHND_PMU_CC1_IF_TYPE_MASK 0x00000030 176#define BHND_PMU_CC1_IF_TYPE_RMII 0x00000000 177#define BHND_PMU_CC1_IF_TYPE_MII 0x00000010 178#define BHND_PMU_CC1_IF_TYPE_RGMII 0x00000020 179 180#define BHND_PMU_CC1_SW_TYPE_MASK 0x000000c0 181#define BHND_PMU_CC1_SW_TYPE_EPHY 0x00000000 182#define BHND_PMU_CC1_SW_TYPE_EPHYMII 0x00000040 183#define BHND_PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 184#define BHND_PMU_CC1_SW_TYPE_RGMII 0x000000c0 185 186/* PMU corerev and chip specific PLL controls. 187 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number 188 * to differentiate different PLLs controlled by the same PMU rev. 189 */ 190 191/* pllcontrol registers */ 192/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ 193#define BHND_PMU0_PLL0_PLLCTL0 0 194#define BHND_PMU0_PLL0_PC0_PDIV_MASK 1 195#define BHND_PMU0_PLL0_PC0_PDIV_FREQ 25000 196#define BHND_PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 197#define BHND_PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 198#define BHND_PMU0_PLL0_PC0_DIV_ARM_BASE 8 199 200/* PC0_DIV_ARM for PLLOUT_ARM */ 201#define BHND_PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 202#define BHND_PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 203#define BHND_PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 204#define BHND_PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ 205#define BHND_PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 206#define BHND_PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 207#define BHND_PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 208#define BHND_PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 209 210/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ 211#define BHND_PMU0_PLL0_PLLCTL1 1 212#define BHND_PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 213#define BHND_PMU0_PLL0_PC1_WILD_INT_SHIFT 28 214#define BHND_PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 215#define BHND_PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 216#define BHND_PMU0_PLL0_PC1_STOP_MOD 0x00000040 217 218/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ 219#define BHND_PMU0_PLL0_PLLCTL2 2 220#define BHND_PMU0_PLL0_PC2_WILD_INT_MASK 0xf0 221#define BHND_PMU0_PLL0_PC2_WILD_INT_SHIFT 4 222 223/* pllcontrol registers */ 224/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 225#define BHND_PMU1_PLL0_PLLCTL0 0 226#define BHND_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 227#define BHND_PMU1_PLL0_PC0_P1DIV_SHIFT 20 228#define BHND_PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 229#define BHND_PMU1_PLL0_PC0_P2DIV_SHIFT 24 230#define BHND_PMU1_PLL0_PC0_BYPASS_SDMOD_MASK 0x10000000 231#define BHND_PMU1_PLL0_PC0_BYPASS_SDMOD_SHIFT 28 232 233/* m<x>div */ 234#define BHND_PMU1_PLL0_PLLCTL1 1 235#define BHND_PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff 236#define BHND_PMU1_PLL0_PC1_M1DIV_SHIFT 0 237#define BHND_PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 238#define BHND_PMU1_PLL0_PC1_M2DIV_SHIFT 8 239#define BHND_PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 240#define BHND_PMU1_PLL0_PC1_M3DIV_SHIFT 16 241#define BHND_PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 242#define BHND_PMU1_PLL0_PC1_M4DIV_SHIFT 24 243 244#define BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 245#define BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 246#define BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 247 248/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 249#define BHND_PMU1_PLL0_PLLCTL2 2 250#define BHND_PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff 251#define BHND_PMU1_PLL0_PC2_M5DIV_SHIFT 0 252#define BHND_PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 253#define BHND_PMU1_PLL0_PC2_M6DIV_SHIFT 8 254#define BHND_PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 255#define BHND_PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 256#define BHND_PMU1_PLL0_PC2_NDIV_MODE_INT 0 257#define BHND_PMU1_PLL0_PC2_NDIV_MODE_MASH 1 258#define BHND_PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */ 259#define BHND_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 260#define BHND_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 261 262/* ndiv_frac */ 263#define BHND_PMU1_PLL0_PLLCTL3 3 264#define BHND_PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff 265#define BHND_PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 266 267/* pll_ctrl */ 268#define BHND_PMU1_PLL0_PLLCTL4 4 269#define BHND_PMU1_PLL0_PC4_KVCO_XS_MASK 0x38000000 270#define BHND_PMU1_PLL0_PC4_KVCO_XS_SHIFT 27 271 272/* pll_ctrl, vco_rng, clkdrive_ch<x> */ 273#define BHND_PMU1_PLL0_PLLCTL5 5 274#define BHND_PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 275#define BHND_PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 276#define BHND_PMU1_PLL0_PC5_PLL_CTRL_37_32_MASK 0x0000003f 277#define BHND_PMU1_PLL0_PC5_PLL_CTRL_37_32_SHIFT 0 278#define BHND_PMU1_PLL0_PC5_VCO_RNG_MASK 0x000000C0 279#define BHND_PMU1_PLL0_PC5_VCO_RNG_SHIFT 6 280 281/* PMU rev 2 control words */ 282#define BHND_PMU2_PHY_PLL_PLLCTL 4 283#define BHND_PMU2_SI_PLL_PLLCTL 10 284 285/* PMU rev 2 */ 286/* pllcontrol registers */ 287/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 288#define BHND_PMU2_PLL_PLLCTL0 0 289#define BHND_PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 290#define BHND_PMU2_PLL_PC0_P1DIV_SHIFT 20 291#define BHND_PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 292#define BHND_PMU2_PLL_PC0_P2DIV_SHIFT 24 293 294/* m<x>div */ 295#define BHND_PMU2_PLL_PLLCTL1 1 296#define BHND_PMU2_PLL_PC1_M1DIV_MASK 0x000000ff 297#define BHND_PMU2_PLL_PC1_M1DIV_SHIFT 0 298#define BHND_PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 299#define BHND_PMU2_PLL_PC1_M2DIV_SHIFT 8 300#define BHND_PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 301#define BHND_PMU2_PLL_PC1_M3DIV_SHIFT 16 302#define BHND_PMU2_PLL_PC1_M4DIV_MASK 0xff000000 303#define BHND_PMU2_PLL_PC1_M4DIV_SHIFT 24 304 305/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 306#define BHND_PMU2_PLL_PLLCTL2 2 307#define BHND_PMU2_PLL_PC2_M5DIV_MASK 0x000000ff 308#define BHND_PMU2_PLL_PC2_M5DIV_SHIFT 0 309#define BHND_PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 310#define BHND_PMU2_PLL_PC2_M6DIV_SHIFT 8 311#define BHND_PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 312#define BHND_PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 313#define BHND_PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 314#define BHND_PMU2_PLL_PC2_NDIV_INT_SHIFT 20 315 316/* ndiv_frac */ 317#define BHND_PMU2_PLL_PLLCTL3 3 318#define BHND_PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff 319#define BHND_PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 320 321/* pll_ctrl */ 322#define BHND_PMU2_PLL_PLLCTL4 4 323 324/* pll_ctrl, vco_rng, clkdrive_ch<x> */ 325#define BHND_PMU2_PLL_PLLCTL5 5 326#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 327#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 328#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 329#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 330#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 331#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 332#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 333#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 334#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 335#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 336#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 337#define BHND_PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 338 339/* PMU rev 5 (& 6) */ 340#define BHND_PMU5_PLL_P1P2_OFF 0 341#define BHND_PMU5_PLL_P1_MASK 0x0f000000 342#define BHND_PMU5_PLL_P1_SHIFT 24 343#define BHND_PMU5_PLL_P2_MASK 0x00f00000 344#define BHND_PMU5_PLL_P2_SHIFT 20 345#define BHND_PMU5_PLL_M14_OFF 1 346#define BHND_PMU5_PLL_MDIV_MASK 0x000000ff 347#define BHND_PMU5_PLL_MDIV_WIDTH 8 348#define BHND_PMU5_PLL_NM5_OFF 2 349#define BHND_PMU5_PLL_NDIV_MASK 0xfff00000 350#define BHND_PMU5_PLL_NDIV_SHIFT 20 351#define BHND_PMU5_PLL_NDIV_MODE_MASK 0x000e0000 352#define BHND_PMU5_PLL_NDIV_MODE_SHIFT 17 353#define BHND_PMU5_PLL_FMAB_OFF 3 354#define BHND_PMU5_PLL_MRAT_MASK 0xf0000000 355#define BHND_PMU5_PLL_MRAT_SHIFT 28 356#define BHND_PMU5_PLL_ABRAT_MASK 0x08000000 357#define BHND_PMU5_PLL_ABRAT_SHIFT 27 358#define BHND_PMU5_PLL_FDIV_MASK 0x07ffffff 359#define BHND_PMU5_PLL_PLLCTL_OFF 4 360#define BHND_PMU5_PLL_PCHI_OFF 5 361#define BHND_PMU5_PLL_PCHI_MASK 0x0000003f 362 363/* pmu XtalFreqRatio */ 364#define BHND_PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF 365#define BHND_PMU_XTALFREQ_REG_ILPCTR_SHIFT 0 366#define BHND_PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 367#define BHND_PMU_XTALFREQ_REG_MEASURE_SHIFT 31 368 369/* Divider allocation in 4716/47162/5356/5357 */ 370#define BHND_PMU5_MAINPLL_CPU 1 371#define BHND_PMU5_MAINPLL_MEM 2 372#define BHND_PMU5_MAINPLL_SI 3 373 374/* PMU rev 6 (BCM4706/Northstar) */ 375#define BHND_PMU4706_MAINPLL_PLL0 0 376#define BHND_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */ 377#define BHND_PMU6_4706_PROC_P1DIV_MASK 0x000f0000 378#define BHND_PMU6_4706_PROC_P1DIV_SHIFT 16 379#define BHND_PMU6_4706_PROC_P2DIV_MASK 0x0000f000 380#define BHND_PMU6_4706_PROC_P2DIV_SHIFT 12 381#define BHND_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8 382#define BHND_PMU6_4706_PROC_NDIV_INT_SHIFT 3 383#define BHND_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007 384#define BHND_PMU6_4706_PROC_NDIV_MODE_SHIFT 0 385 386/* Divider allocation in 4706 */ 387#define BHND_PMU6_MAINPLL_CPU 1 388#define BHND_PMU6_MAINPLL_MEM 2 389#define BHND_PMU6_MAINPLL_SI 3 390 391/* PMU7 (?) */ 392#define BHND_PMU7_PLL_PLLCTL7 7 393#define BHND_PMU7_PLL_PLLCTL8 8 394#define BHND_PMU7_PLL_PLLCTL11 11 395 396/* PLL usage in 4716/47162 */ 397#define BHND_PMU4716_MAINPLL_PLL0 12 398 399/* PLL usage in 5356/5357 */ 400#define BHND_PMU5356_MAINPLL_PLL0 0 401#define BHND_PMU5357_MAINPLL_PLL0 0 402 403/* 4716/47162 PMU resources */ 404#define BHND_PMU_RES4716_PROC_PLL_ON 0x00000040 405#define BHND_PMU_RES4716_PROC_HT_AVAIL 0x00000080 406 407/* 4716/4717/4718 chip-specific CHIPCTRL PMU register bits */ 408#define BHND_PMU_CCTRL471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared with pflash */ 409 410/* 5354 PMU resources */ 411#define BHND_PMU_RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ 412#define BHND_PMU_RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ 413#define BHND_PMU_RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ 414#define BHND_PMU_RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ 415#define BHND_PMU_RES5354_ILP_REQUEST 4 /* 0x00010 */ 416#define BHND_PMU_RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ 417#define BHND_PMU_RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ 418#define BHND_PMU_RES5354_ROM_SWITCH 7 /* 0x00080 */ 419#define BHND_PMU_RES5354_PA_REF_LDO 8 /* 0x00100 */ 420#define BHND_PMU_RES5354_RADIO_LDO 9 /* 0x00200 */ 421#define BHND_PMU_RES5354_AFE_LDO 10 /* 0x00400 */ 422#define BHND_PMU_RES5354_PLL_LDO 11 /* 0x00800 */ 423#define BHND_PMU_RES5354_BG_FILTBYP 12 /* 0x01000 */ 424#define BHND_PMU_RES5354_TX_FILTBYP 13 /* 0x02000 */ 425#define BHND_PMU_RES5354_RX_FILTBYP 14 /* 0x04000 */ 426#define BHND_PMU_RES5354_XTAL_PU 15 /* 0x08000 */ 427#define BHND_PMU_RES5354_XTAL_EN 16 /* 0x10000 */ 428#define BHND_PMU_RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ 429#define BHND_PMU_RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ 430#define BHND_PMU_RES5354_BB_PLL_PU 19 /* 0x80000 */ 431 432/* 5357 chip-specific CHIPCTRL register bits */ 433#define BHND_PMU_CCTRL5357_EXTPA (1<<14) /* extPA in CHIPCTRL1, bit 14 */ 434#define BHND_PMU_CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in CHIPCTRL1, bit 15 */ 435 436/* 4328 PMU resources */ 437#define BHND_PMU_RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ 438#define BHND_PMU_RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ 439#define BHND_PMU_RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ 440#define BHND_PMU_RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ 441#define BHND_PMU_RES4328_ILP_REQUEST 4 /* 0x00010 */ 442#define BHND_PMU_RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ 443#define BHND_PMU_RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ 444#define BHND_PMU_RES4328_ROM_SWITCH 7 /* 0x00080 */ 445#define BHND_PMU_RES4328_PA_REF_LDO 8 /* 0x00100 */ 446#define BHND_PMU_RES4328_RADIO_LDO 9 /* 0x00200 */ 447#define BHND_PMU_RES4328_AFE_LDO 10 /* 0x00400 */ 448#define BHND_PMU_RES4328_PLL_LDO 11 /* 0x00800 */ 449#define BHND_PMU_RES4328_BG_FILTBYP 12 /* 0x01000 */ 450#define BHND_PMU_RES4328_TX_FILTBYP 13 /* 0x02000 */ 451#define BHND_PMU_RES4328_RX_FILTBYP 14 /* 0x04000 */ 452#define BHND_PMU_RES4328_XTAL_PU 15 /* 0x08000 */ 453#define BHND_PMU_RES4328_XTAL_EN 16 /* 0x10000 */ 454#define BHND_PMU_RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ 455#define BHND_PMU_RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ 456#define BHND_PMU_RES4328_BB_PLL_PU 19 /* 0x80000 */ 457 458/* 4325 A0/A1 PMU resources */ 459#define BHND_PMU_RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ 460#define BHND_PMU_RES4325_CBUCK_BURST 1 /* 0x00000002 */ 461#define BHND_PMU_RES4325_CBUCK_PWM 2 /* 0x00000004 */ 462#define BHND_PMU_RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ 463#define BHND_PMU_RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ 464#define BHND_PMU_RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ 465#define BHND_PMU_RES4325_ILP_REQUEST 6 /* 0x00000040 */ 466#define BHND_PMU_RES4325_ABUCK_BURST 7 /* 0x00000080 */ 467#define BHND_PMU_RES4325_ABUCK_PWM 8 /* 0x00000100 */ 468#define BHND_PMU_RES4325_LNLDO1_PU 9 /* 0x00000200 */ 469#define BHND_PMU_RES4325_OTP_PU 10 /* 0x00000400 */ 470#define BHND_PMU_RES4325_LNLDO3_PU 11 /* 0x00000800 */ 471#define BHND_PMU_RES4325_LNLDO4_PU 12 /* 0x00001000 */ 472#define BHND_PMU_RES4325_XTAL_PU 13 /* 0x00002000 */ 473#define BHND_PMU_RES4325_ALP_AVAIL 14 /* 0x00004000 */ 474#define BHND_PMU_RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ 475#define BHND_PMU_RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ 476#define BHND_PMU_RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 477#define BHND_PMU_RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 478#define BHND_PMU_RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ 479#define BHND_PMU_RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 480#define BHND_PMU_RES4325_HT_AVAIL 21 /* 0x00200000 */ 481 482/* 4325 B0/C0 PMU resources */ 483#define BHND_PMU_RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */ 484#define BHND_PMU_RES4325B0_CBUCK_BURST 2 /* 0x00000004 */ 485#define BHND_PMU_RES4325B0_CBUCK_PWM 3 /* 0x00000008 */ 486#define BHND_PMU_RES4325B0_CLDO_PU 4 /* 0x00000010 */ 487 488/* 4325 C1 PMU resources */ 489#define BHND_PMU_RES4325C1_LNLDO2_PU 12 /* 0x00001000 */ 490 491/* 4325 PMU resources */ 492#define BHND_PMU_RES4329_RESERVED0 0 /* 0x00000001 */ 493#define BHND_PMU_RES4329_CBUCK_LPOM 1 /* 0x00000002 */ 494#define BHND_PMU_RES4329_CBUCK_BURST 2 /* 0x00000004 */ 495#define BHND_PMU_RES4329_CBUCK_PWM 3 /* 0x00000008 */ 496#define BHND_PMU_RES4329_CLDO_PU 4 /* 0x00000010 */ 497#define BHND_PMU_RES4329_PALDO_PU 5 /* 0x00000020 */ 498#define BHND_PMU_RES4329_ILP_REQUEST 6 /* 0x00000040 */ 499#define BHND_PMU_RES4329_RESERVED7 7 /* 0x00000080 */ 500#define BHND_PMU_RES4329_RESERVED8 8 /* 0x00000100 */ 501#define BHND_PMU_RES4329_LNLDO1_PU 9 /* 0x00000200 */ 502#define BHND_PMU_RES4329_OTP_PU 10 /* 0x00000400 */ 503#define BHND_PMU_RES4329_RESERVED11 11 /* 0x00000800 */ 504#define BHND_PMU_RES4329_LNLDO2_PU 12 /* 0x00001000 */ 505#define BHND_PMU_RES4329_XTAL_PU 13 /* 0x00002000 */ 506#define BHND_PMU_RES4329_ALP_AVAIL 14 /* 0x00004000 */ 507#define BHND_PMU_RES4329_RX_PWRSW_PU 15 /* 0x00008000 */ 508#define BHND_PMU_RES4329_TX_PWRSW_PU 16 /* 0x00010000 */ 509#define BHND_PMU_RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 510#define BHND_PMU_RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 511#define BHND_PMU_RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */ 512#define BHND_PMU_RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 513#define BHND_PMU_RES4329_HT_AVAIL 21 /* 0x00200000 */ 514 515/* 4312 PMU resources (all PMU chips with little memory constraint) */ 516#define BHND_PMU_RES4312_SWITCHER_BURST 0 /* 0x00000001 */ 517#define BHND_PMU_RES4312_SWITCHER_PWM 1 /* 0x00000002 */ 518#define BHND_PMU_RES4312_PA_REF_LDO 2 /* 0x00000004 */ 519#define BHND_PMU_RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ 520#define BHND_PMU_RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ 521#define BHND_PMU_RES4312_RADIO_LDO 5 /* 0x00000020 */ 522#define BHND_PMU_RES4312_ILP_REQUEST 6 /* 0x00000040 */ 523#define BHND_PMU_RES4312_BG_FILTBYP 7 /* 0x00000080 */ 524#define BHND_PMU_RES4312_TX_FILTBYP 8 /* 0x00000100 */ 525#define BHND_PMU_RES4312_RX_FILTBYP 9 /* 0x00000200 */ 526#define BHND_PMU_RES4312_XTAL_PU 10 /* 0x00000400 */ 527#define BHND_PMU_RES4312_ALP_AVAIL 11 /* 0x00000800 */ 528#define BHND_PMU_RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ 529#define BHND_PMU_RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ 530#define BHND_PMU_RES4312_HT_AVAIL 14 /* 0x00004000 */ 531 532/* 4322 PMU resources */ 533#define BHND_PMU_RES4322_RF_LDO 0 534#define BHND_PMU_RES4322_ILP_REQUEST 1 535#define BHND_PMU_RES4322_XTAL_PU 2 536#define BHND_PMU_RES4322_ALP_AVAIL 3 537#define BHND_PMU_RES4322_SI_PLL_ON 4 538#define BHND_PMU_RES4322_HT_SI_AVAIL 5 539#define BHND_PMU_RES4322_PHY_PLL_ON 6 540#define BHND_PMU_RES4322_HT_PHY_AVAIL 7 541#define BHND_PMU_RES4322_OTP_PU 8 542 543/* 43224 chip-specific CHIPCTRL register bits */ 544#define BHND_PMU_CCTRL43224_GPIO_TOGGLE 0x8000 545#define BHND_PMU_CCTRL43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ 546#define BHND_PMU_CCTRL43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ 547 548/* 43236 PMU resources */ 549#define BHND_PMU_RES43236_REGULATOR 0 550#define BHND_PMU_RES43236_ILP_REQUEST 1 551#define BHND_PMU_RES43236_XTAL_PU 2 552#define BHND_PMU_RES43236_ALP_AVAIL 3 553#define BHND_PMU_RES43236_SI_PLL_ON 4 554#define BHND_PMU_RES43236_HT_SI_AVAIL 5 555 556/* 43236 chip-specific CHIPCTRL register bits */ 557#define BHND_PMU_CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */ 558#define BHND_PMU_CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 559#define BHND_PMU_CCTRL43236_EXT_LNA (1<<2) /* 0 disable */ 560#define BHND_PMU_CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ 561#define BHND_PMU_CCTRL43236_GSIO (1<<4) /* 0 disable */ 562 563/* 4331 PMU resources */ 564#define BHND_PMU_RES4331_REGULATOR 0 565#define BHND_PMU_RES4331_ILP_REQUEST 1 566#define BHND_PMU_RES4331_XTAL_PU 2 567#define BHND_PMU_RES4331_ALP_AVAIL 3 568#define BHND_PMU_RES4331_SI_PLL_ON 4 569#define BHND_PMU_RES4331_HT_SI_AVAIL 5 570 571/* 4315 PMU resources */ 572#define BHND_PMU_RES4315_CBUCK_LPOM 1 /* 0x00000002 */ 573#define BHND_PMU_RES4315_CBUCK_BURST 2 /* 0x00000004 */ 574#define BHND_PMU_RES4315_CBUCK_PWM 3 /* 0x00000008 */ 575#define BHND_PMU_RES4315_CLDO_PU 4 /* 0x00000010 */ 576#define BHND_PMU_RES4315_PALDO_PU 5 /* 0x00000020 */ 577#define BHND_PMU_RES4315_ILP_REQUEST 6 /* 0x00000040 */ 578#define BHND_PMU_RES4315_LNLDO1_PU 9 /* 0x00000200 */ 579#define BHND_PMU_RES4315_OTP_PU 10 /* 0x00000400 */ 580#define BHND_PMU_RES4315_LNLDO2_PU 12 /* 0x00001000 */ 581#define BHND_PMU_RES4315_XTAL_PU 13 /* 0x00002000 */ 582#define BHND_PMU_RES4315_ALP_AVAIL 14 /* 0x00004000 */ 583#define BHND_PMU_RES4315_RX_PWRSW_PU 15 /* 0x00008000 */ 584#define BHND_PMU_RES4315_TX_PWRSW_PU 16 /* 0x00010000 */ 585#define BHND_PMU_RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 586#define BHND_PMU_RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 587#define BHND_PMU_RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */ 588#define BHND_PMU_RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 589#define BHND_PMU_RES4315_HT_AVAIL 21 /* 0x00200000 */ 590 591/* 4319 PMU resources */ 592#define BHND_PMU_RES4319_CBUCK_LPOM 1 /* 0x00000002 */ 593#define BHND_PMU_RES4319_CBUCK_BURST 2 /* 0x00000004 */ 594#define BHND_PMU_RES4319_CBUCK_PWM 3 /* 0x00000008 */ 595#define BHND_PMU_RES4319_CLDO_PU 4 /* 0x00000010 */ 596#define BHND_PMU_RES4319_PALDO_PU 5 /* 0x00000020 */ 597#define BHND_PMU_RES4319_ILP_REQUEST 6 /* 0x00000040 */ 598#define BHND_PMU_RES4319_LNLDO1_PU 9 /* 0x00000200 */ 599#define BHND_PMU_RES4319_OTP_PU 10 /* 0x00000400 */ 600#define BHND_PMU_RES4319_LNLDO2_PU 12 /* 0x00001000 */ 601#define BHND_PMU_RES4319_XTAL_PU 13 /* 0x00002000 */ 602#define BHND_PMU_RES4319_ALP_AVAIL 14 /* 0x00004000 */ 603#define BHND_PMU_RES4319_RX_PWRSW_PU 15 /* 0x00008000 */ 604#define BHND_PMU_RES4319_TX_PWRSW_PU 16 /* 0x00010000 */ 605#define BHND_PMU_RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 606#define BHND_PMU_RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 607#define BHND_PMU_RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ 608#define BHND_PMU_RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 609#define BHND_PMU_RES4319_HT_AVAIL 21 /* 0x00200000 */ 610 611/* 4319 chip-specific CHIPCTL register bits */ 612#define BHND_PMU1_PLL0_CHIPCTL0 0 613#define BHND_PMU1_PLL0_CHIPCTL1 1 614#define BHND_PMU1_PLL0_CHIPCTL2 2 615#define BHND_PMU_CCTRL4319USB_XTAL_SEL_MASK 0x00180000 616#define BHND_PMU_CCTRL4319USB_XTAL_SEL_SHIFT 19 617#define BHND_PMU_CCTRL4319USB_48MHZ_PLL_SEL 1 618#define BHND_PMU_CCTRL4319USB_24MHZ_PLL_SEL 2 619 620/* 4336 PMU resources */ 621#define BHND_PMU_RES4336_CBUCK_LPOM 0 622#define BHND_PMU_RES4336_CBUCK_BURST 1 623#define BHND_PMU_RES4336_CBUCK_LP_PWM 2 624#define BHND_PMU_RES4336_CBUCK_PWM 3 625#define BHND_PMU_RES4336_CLDO_PU 4 626#define BHND_PMU_RES4336_DIS_INT_RESET_PD 5 627#define BHND_PMU_RES4336_ILP_REQUEST 6 628#define BHND_PMU_RES4336_LNLDO_PU 7 629#define BHND_PMU_RES4336_LDO3P3_PU 8 630#define BHND_PMU_RES4336_OTP_PU 9 631#define BHND_PMU_RES4336_XTAL_PU 10 632#define BHND_PMU_RES4336_ALP_AVAIL 11 633#define BHND_PMU_RES4336_RADIO_PU 12 634#define BHND_PMU_RES4336_BG_PU 13 635#define BHND_PMU_RES4336_VREG1p4_PU_PU 14 636#define BHND_PMU_RES4336_AFE_PWRSW_PU 15 637#define BHND_PMU_RES4336_RX_PWRSW_PU 16 638#define BHND_PMU_RES4336_TX_PWRSW_PU 17 639#define BHND_PMU_RES4336_BB_PWRSW_PU 18 640#define BHND_PMU_RES4336_SYNTH_PWRSW_PU 19 641#define BHND_PMU_RES4336_MISC_PWRSW_PU 20 642#define BHND_PMU_RES4336_LOGEN_PWRSW_PU 21 643#define BHND_PMU_RES4336_BBPLL_PWRSW_PU 22 644#define BHND_PMU_RES4336_MACPHY_CLKAVAIL 23 645#define BHND_PMU_RES4336_HT_AVAIL 24 646#define BHND_PMU_RES4336_RSVD 25 647 648/* 4330 resources */ 649#define BHND_PMU_RES4330_CBUCK_LPOM 0 650#define BHND_PMU_RES4330_CBUCK_BURST 1 651#define BHND_PMU_RES4330_CBUCK_LP_PWM 2 652#define BHND_PMU_RES4330_CBUCK_PWM 3 653#define BHND_PMU_RES4330_CLDO_PU 4 654#define BHND_PMU_RES4330_DIS_INT_RESET_PD 5 655#define BHND_PMU_RES4330_ILP_REQUEST 6 656#define BHND_PMU_RES4330_LNLDO_PU 7 657#define BHND_PMU_RES4330_LDO3P3_PU 8 658#define BHND_PMU_RES4330_OTP_PU 9 659#define BHND_PMU_RES4330_XTAL_PU 10 660#define BHND_PMU_RES4330_ALP_AVAIL 11 661#define BHND_PMU_RES4330_RADIO_PU 12 662#define BHND_PMU_RES4330_BG_PU 13 663#define BHND_PMU_RES4330_VREG1p4_PU_PU 14 664#define BHND_PMU_RES4330_AFE_PWRSW_PU 15 665#define BHND_PMU_RES4330_RX_PWRSW_PU 16 666#define BHND_PMU_RES4330_TX_PWRSW_PU 17 667#define BHND_PMU_RES4330_BB_PWRSW_PU 18 668#define BHND_PMU_RES4330_SYNTH_PWRSW_PU 19 669#define BHND_PMU_RES4330_MISC_PWRSW_PU 20 670#define BHND_PMU_RES4330_LOGEN_PWRSW_PU 21 671#define BHND_PMU_RES4330_BBPLL_PWRSW_PU 22 672#define BHND_PMU_RES4330_MACPHY_CLKAVAIL 23 673#define BHND_PMU_RES4330_HT_AVAIL 24 674#define BHND_PMU_RES4330_5gRX_PWRSW_PU 25 675#define BHND_PMU_RES4330_5gTX_PWRSW_PU 26 676#define BHND_PMU_RES4330_5g_LOGEN_PWRSW_PU 27 677 678/* 4313 resources */ 679#define BHND_PMU_RES4313_BB_PU_RSRC 0 680#define BHND_PMU_RES4313_ILP_REQ_RSRC 1 681#define BHND_PMU_RES4313_XTAL_PU_RSRC 2 682#define BHND_PMU_RES4313_ALP_AVAIL_RSRC 3 683#define BHND_PMU_RES4313_RADIO_PU_RSRC 4 684#define BHND_PMU_RES4313_BG_PU_RSRC 5 685#define BHND_PMU_RES4313_VREG1P4_PU_RSRC 6 686#define BHND_PMU_RES4313_AFE_PWRSW_RSRC 7 687#define BHND_PMU_RES4313_RX_PWRSW_RSRC 8 688#define BHND_PMU_RES4313_TX_PWRSW_RSRC 9 689#define BHND_PMU_RES4313_BB_PWRSW_RSRC 10 690#define BHND_PMU_RES4313_SYNTH_PWRSW_RSRC 11 691#define BHND_PMU_RES4313_MISC_PWRSW_RSRC 12 692#define BHND_PMU_RES4313_BB_PLL_PWRSW_RSRC 13 693#define BHND_PMU_RES4313_HT_AVAIL_RSRC 14 694#define BHND_PMU_RES4313_MACPHY_CLK_AVAIL_RSRC 15 695 696/* 4313 chip-specific CHIPCTRL register bits */ 697#define BHND_PMU_CCTRL4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ 698 699/* 43228 resources */ 700#define BHND_PMU_RES43228_NOT_USED 0 701#define BHND_PMU_RES43228_ILP_REQUEST 1 702#define BHND_PMU_RES43228_XTAL_PU 2 703#define BHND_PMU_RES43228_ALP_AVAIL 3 704#define BHND_PMU_RES43228_PLL_EN 4 705#define BHND_PMU_RES43228_HT_PHY_AVAIL 5 706 707/* 708* Maximum delay for the PMU state transition in us. 709* This is an upper bound intended for spinwaits etc. 710*/ 711#define BHND_PMU_MAX_TRANSITION_DLY 15000 712 713/* PMU resource up transition time in ILP cycles */ 714#define BHND_PMURES_UP_TRANSITION 2 715 716#endif /* _BHND_CORES_PMU_BHND_PMUREG_H_ */ 717