1/*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21#ifndef _DEV_ATH_AR5416PHY_H_ 22#define _DEV_ATH_AR5416PHY_H_ 23 24#include "ar5212/ar5212phy.h" 25 26#define AR_BT_COEX_MODE 0x8170 27#define AR_BT_TIME_EXTEND 0x000000ff 28#define AR_BT_TIME_EXTEND_S 0 29#define AR_BT_TXSTATE_EXTEND 0x00000100 30#define AR_BT_TXSTATE_EXTEND_S 8 31#define AR_BT_TX_FRAME_EXTEND 0x00000200 32#define AR_BT_TX_FRAME_EXTEND_S 9 33#define AR_BT_MODE 0x00000c00 34#define AR_BT_MODE_S 10 35#define AR_BT_QUIET 0x00001000 36#define AR_BT_QUIET_S 12 37#define AR_BT_QCU_THRESH 0x0001e000 38#define AR_BT_QCU_THRESH_S 13 39#define AR_BT_RX_CLEAR_POLARITY 0x00020000 40#define AR_BT_RX_CLEAR_POLARITY_S 17 41#define AR_BT_PRIORITY_TIME 0x00fc0000 42#define AR_BT_PRIORITY_TIME_S 18 43#define AR_BT_FIRST_SLOT_TIME 0xff000000 44#define AR_BT_FIRST_SLOT_TIME_S 24 45 46#define AR_BT_COEX_WEIGHT 0x8174 47#define AR_BT_BT_WGHT 0x0000ffff 48#define AR_BT_BT_WGHT_S 0 49#define AR_BT_WL_WGHT 0xffff0000 50#define AR_BT_WL_WGHT_S 16 51 52#define AR_BT_COEX_MODE2 0x817c 53#define AR_BT_BCN_MISS_THRESH 0x000000ff 54#define AR_BT_BCN_MISS_THRESH_S 0 55#define AR_BT_BCN_MISS_CNT 0x0000ff00 56#define AR_BT_BCN_MISS_CNT_S 8 57#define AR_BT_HOLD_RX_CLEAR 0x00010000 58#define AR_BT_HOLD_RX_CLEAR_S 16 59#define AR_BT_DISABLE_BT_ANT 0x00100000 60#define AR_BT_DISABLE_BT_ANT_S 20 61 62#define AR_PHY_SPECTRAL_SCAN 0x9910 63#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 64#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 65#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 66#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 67#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 68#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 69#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 70#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 71 72/* Scan count and Short repeat flags are different for Kiwi and Merlin */ 73#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 74#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 75#define AR_PHY_SPECTRAL_SCAN_COUNT_KIWI 0x0FFF0000 76#define AR_PHY_SPECTRAL_SCAN_COUNT_KIWI_S 16 77 78#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 79#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 80#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI 0x10000000 81#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI_S 28 82 83/* 84 * Kiwi only, bit 30 is used to set the error type, if set it is 0x5 (HAL_PHYERR_RADAR) 85 * Else it is 38 (new error type) 86 */ 87#define AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT_KIWI 0x40000000 /* Spectral Error select bit mask */ 88#define AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT_KIWI_S 30 /* Spectral Error select bit 30 */ 89 90#define AR_PHY_SPECTRAL_SCAN_PRIORITY_SELECT_KIWI 0x20000000 /* Spectral Error select bit mask */ 91#define AR_PHY_SPECTRAL_SCAN_PRIORITY_SELECT_SELECT_KIWI_S 29 /* Spectral Error select bit 30 */ 92 93/* For AR_PHY_RADAR0 */ 94#define AR_PHY_RADAR_0_FFT_ENA 0x80000000 95 96#define AR_PHY_RADAR_EXT 0x9940 97#define AR_PHY_RADAR_EXT_ENA 0x00004000 98 99#define AR_PHY_RADAR_1 0x9958 100#define AR_PHY_RADAR_1_BIN_THRESH_SELECT 0x07000000 101#define AR_PHY_RADAR_1_BIN_THRESH_SELECT_S 24 102#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 103#define AR_PHY_RADAR_1_USE_FIR128 0x00400000 104#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 105#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 106#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 107#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 108#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 109#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 110#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 111#define AR_PHY_RADAR_1_MAXLEN 0x000000FF 112#define AR_PHY_RADAR_1_MAXLEN_S 0 113 114#define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */ 115#define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */ 116 117#define RFSILENT_BB 0x00002000 /* shush bb */ 118#define AR_PHY_RESTART 0x9970 /* restart */ 119#define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */ 120#define AR_PHY_RESTART_DIV_GC_S 18 121 122/* PLL settling times */ 123#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 124#define HT40_CHANNEL_CENTER_SHIFT 10 /* MHz */ 125 126#define AR_PHY_RFBUS_REQ 0x997C 127#define AR_PHY_RFBUS_REQ_EN 0x00000001 128 129#define AR_2040_MODE 0x8318 130#define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca 131 132#define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */ 133#define AR_PHY_FC_DYN2040_EN 0x00000004 /* Enable dyn 20/40 mode */ 134#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */ 135#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/ 136#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */ 137#define AR_PHY_FC_HT_EN 0x00000040 /* ht enable */ 138#define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ 139#define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ 140#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ 141#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800 142 143#define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */ 144#define AR_PHY_TIMING2_USE_FORCE 0x00001000 145#define AR_PHY_TIMING2_FORCE_VAL 0x00000fff 146 147#define AR_PHY_TIMING_CTRL4_CHAIN(_i) \ 148 (AR_PHY_TIMING_CTRL4 + ((_i) << 12)) 149#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 /* perform calibration */ 150#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */ 151#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */ 152#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */ 153#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */ 154#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */ 155#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */ 156#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ 157 158#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 159#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 /* Enable spur filter */ 160#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 161#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 162 163#define AR_PHY_ADC_SERIAL_CTL 0x9830 164#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 165#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 166 167#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00 168#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 169#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F 170#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 171 172#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000 173#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 174#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000 175#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 176#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0 177#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 178#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F 179#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 180 181#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 182#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 183#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 184#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 185 186#define AR_PHY_SEARCH_START_DELAY 0x9918 /* search start delay */ 187 188#define AR_PHY_EXT_CCA 0x99bc 189#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00 190#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 191#define AR_PHY_EXT_MINCCA_PWR 0xFF800000 192#define AR_PHY_EXT_MINCCA_PWR_S 23 193#define AR_PHY_EXT_CCA_THRESH62 0x007F0000 194#define AR_PHY_EXT_CCA_THRESH62_S 16 195 196#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 197#define AR9280_PHY_EXT_MINCCA_PWR_S 16 198 199#define AR_PHY_HALFGI 0x99D0 /* Timing control 3 */ 200#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0 201#define AR_PHY_HALFGI_DSC_MAN_S 4 202#define AR_PHY_HALFGI_DSC_EXP 0x0000000F 203#define AR_PHY_HALFGI_DSC_EXP_S 0 204 205#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 206 207#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec 208#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000 209 210#define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */ 211#define AR_PHY_REFCLKDLY 0x99f4 212#define AR_PHY_REFCLKPD 0x99f8 213 214#define AR_PHY_CALMODE 0x99f0 215/* Calibration Types */ 216#define AR_PHY_CALMODE_IQ 0x00000000 217#define AR_PHY_CALMODE_ADC_GAIN 0x00000001 218#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 219#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 220/* Calibration results */ 221#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) 222#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) 223#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) 224/* This is AR9130 and later */ 225#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) 226 227/* 228 * AR5416 still uses AR_PHY(263) for current RSSI; 229 * AR9130 and later uses AR_PHY(271). 230 */ 231#define AR9130_PHY_CURRENT_RSSI 0x9c3c /* rssi of current frame rx'd */ 232 233#define AR_PHY_CCA 0x9864 234#define AR_PHY_MINCCA_PWR 0x0FF80000 235#define AR_PHY_MINCCA_PWR_S 19 236#define AR9280_PHY_MINCCA_PWR 0x1FF00000 237#define AR9280_PHY_MINCCA_PWR_S 20 238#define AR9280_PHY_CCA_THRESH62 0x000FF000 239#define AR9280_PHY_CCA_THRESH62_S 12 240 241#define AR_PHY_CH1_CCA 0xa864 242#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000 243#define AR_PHY_CH1_MINCCA_PWR_S 19 244#define AR_PHY_CCA_THRESH62 0x0007F000 245#define AR_PHY_CCA_THRESH62_S 12 246#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000 247#define AR9280_PHY_CH1_MINCCA_PWR_S 20 248 249#define AR_PHY_CH2_CCA 0xb864 250#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000 251#define AR_PHY_CH2_MINCCA_PWR_S 19 252 253#define AR_PHY_CH1_EXT_CCA 0xa9bc 254#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 255#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 256#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 257#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16 258 259#define AR_PHY_CH2_EXT_CCA 0xb9bc 260#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 261#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 262 263#define AR_PHY_RX_CHAINMASK 0x99a4 264 265#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) 266#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 267#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 268#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 269 270#define AR_PHY_EXT_CCA0 0x99b8 271#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF 272#define AR_PHY_EXT_CCA0_THRESH62_S 0 273 274#define AR_PHY_CH1_EXT_CCA 0xa9bc 275#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 276#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 277 278#define AR_PHY_CH2_EXT_CCA 0xb9bc 279#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 280#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 281#define AR_PHY_ANALOG_SWAP 0xa268 282#define AR_PHY_SWAP_ALT_CHAIN 0x00000040 283#define AR_PHY_CAL_CHAINMASK 0xa39c 284 285#define AR_PHY_SWITCH_CHAIN_0 0x9960 286#define AR_PHY_SWITCH_COM 0x9964 287 288#define AR_PHY_RF_CTL2 0x9824 289#define AR_PHY_TX_FRAME_TO_DATA_START 0x000000FF 290#define AR_PHY_TX_FRAME_TO_DATA_START_S 0 291#define AR_PHY_TX_FRAME_TO_PA_ON 0x0000FF00 292#define AR_PHY_TX_FRAME_TO_PA_ON_S 8 293 294#define AR_PHY_RF_CTL3 0x9828 295#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 296#define AR_PHY_TX_END_TO_A2_RX_ON_S 16 297 298#define AR_PHY_RF_CTL4 0x9834 299#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000 300#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 301#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000 302#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 303#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00 304#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 305#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF 306#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 307 308#define AR_PHY_SYNTH_CONTROL 0x9874 309 310#define AR_PHY_FORCE_CLKEN_CCK 0xA22C 311#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 312 313#define AR_PHY_POWER_TX_SUB 0xA3C8 314#define AR_PHY_POWER_TX_RATE5 0xA38C 315#define AR_PHY_POWER_TX_RATE6 0xA390 316#define AR_PHY_POWER_TX_RATE7 0xA3CC 317#define AR_PHY_POWER_TX_RATE8 0xA3D0 318#define AR_PHY_POWER_TX_RATE9 0xA3D4 319 320#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 321#define AR_PHY_TPCRG1_PD_GAIN_1_S 16 322#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 323#define AR_PHY_TPCRG1_PD_GAIN_2_S 18 324#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 325#define AR_PHY_TPCRG1_PD_GAIN_3_S 20 326 327#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 328#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 329 330#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 331#define AR_PHY_MASK2_M_31_45 0xa3a4 332#define AR_PHY_MASK2_M_16_30 0xa3a8 333#define AR_PHY_MASK2_M_00_15 0xa3ac 334#define AR_PHY_MASK2_P_15_01 0xa3b8 335#define AR_PHY_MASK2_P_30_16 0xa3bc 336#define AR_PHY_MASK2_P_45_31 0xa3c0 337#define AR_PHY_MASK2_P_61_45 0xa3c4 338 339#define AR_PHY_SPUR_REG 0x994c 340#define AR_PHY_SFCORR_EXT 0x99c0 341#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F 342#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 343#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 344#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 345#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 346#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 347#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 348#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 349#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 350 351/* enable vit puncture per rate, 8 bits, lsb is low rate */ 352#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) 353#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 354 355#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ 356#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) /* use mask1 or mask2, one per rate */ 357#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 358#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 359#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F 360#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 361 362#define AR_PHY_PILOT_MASK_01_30 0xa3b0 363#define AR_PHY_PILOT_MASK_31_60 0xa3b4 364 365#define AR_PHY_CHANNEL_MASK_01_30 0x99d4 366#define AR_PHY_CHANNEL_MASK_31_60 0x99d8 367 368#define AR_PHY_CL_CAL_CTL 0xA358 /* carrier leak cal control */ 369#define AR_PHY_CL_CAL_ENABLE 0x00000002 370#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 371 372/* empirically determined "good" CCA value ranges from atheros */ 373#define AR_PHY_CCA_NOM_VAL_5416_2GHZ -90 374#define AR_PHY_CCA_NOM_VAL_5416_5GHZ -100 375#define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ -100 376#define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ -110 377#define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ -80 378#define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ -90 379 380/* ar9280 specific? */ 381#define AR_PHY_XPA_CFG 0xA3D8 382#define AR_PHY_FORCE_XPA_CFG 0x000000001 383#define AR_PHY_FORCE_XPA_CFG_S 0 384 385#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C 386#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2 387 388#define AR_PHY_TX_PWRCTRL9 0xa27C 389#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00 390#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 391#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 392#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31 393 394#define AR_PHY_MODE_ASYNCFIFO 0x80 /* Enable async fifo */ 395 396#endif /* _DEV_ATH_AR5416PHY_H_ */ 397