1/*-
2 * SPDX-License-Identifier: ISC
3 *
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 * $FreeBSD$
20 */
21#ifndef _ATH_AH_EEPROM_V1_H_
22#define _ATH_AH_EEPROM_V1_H_
23
24#include "ah_eeprom.h"
25
26/*
27 * EEPROM defines for Version 1 Crete EEPROM.
28 *
29 * The EEPROM is segmented into three sections:
30 *
31 *    PCI/Cardbus default configuration settings
32 *    Cardbus CIS tuples and vendor-specific data
33 *    Atheros-specific data
34 *
35 * EEPROM entries are read 32-bits at a time through the PCI bus
36 * interface but are all 16-bit values.
37 *
38 * Access to the Atheros-specific data is controlled by protection
39 * bits and the data is checksum'd.  The driver reads the Atheros
40 * data from the EEPROM at attach and caches it in its private state.
41 * This data includes the local regulatory domain, channel calibration
42 * settings, and phy-related configuration settings.
43 */
44#define	AR_EEPROM_MAC(i)	(0x1f-(i))/* MAC address word */
45#define	AR_EEPROM_MAGIC		0x3d	/* magic number */
46#define AR_EEPROM_PROTECT	0x3f	/* Atheros segment protect register */
47#define	AR_EEPROM_PROTOTECT_WP_128_191	0x80
48#define AR_EEPROM_REG_DOMAIN	0xbf	/* Current regulatory domain register */
49#define AR_EEPROM_ATHEROS_BASE	0xc0	/* Base of Atheros-specific data */
50#define AR_EEPROM_ATHEROS_MAX	64	/* 64x2=128 bytes of EEPROM settings */
51#define	AR_EEPROM_ATHEROS(n)	(AR_EEPROM_ATHEROS_BASE+(n))
52#define	AR_EEPROM_VERSION	AR_EEPROM_ATHEROS(1)
53#define AR_EEPROM_ATHEROS_TP_SETTINGS	0x09	/* Transmit power settings */
54#define AR_REG_DOMAINS_MAX	4	/* # of Regulatory Domains */
55#define AR_CHANNELS_MAX		5	/* # of Channel calibration groups */
56#define AR_TP_SETTINGS_SIZE	11	/* # locations/Channel group */
57#define AR_TP_SCALING_ENTRIES	11	/* # entries in transmit power dBm->pcdac */
58
59/*
60 * NB: we store the rfsilent select+polarity data packed
61 *     with the encoding used in later parts so values
62 *     returned to applications are consistent.
63 */
64#define AR_EEPROM_RFSILENT_GPIO_SEL	0x001c
65#define AR_EEPROM_RFSILENT_GPIO_SEL_S	2
66#define AR_EEPROM_RFSILENT_POLARITY	0x0002
67#define AR_EEPROM_RFSILENT_POLARITY_S	1
68
69#define AR_I2DBM(x)	((uint8_t)((x * 2) + 3))
70
71/*
72 * Transmit power and channel calibration settings.
73 */
74struct tpcMap {
75	uint8_t		pcdac[AR_TP_SCALING_ENTRIES];
76	uint8_t		gainF[AR_TP_SCALING_ENTRIES];
77	uint8_t		rate36;
78	uint8_t		rate48;
79	uint8_t		rate54;
80	uint8_t		regdmn[AR_REG_DOMAINS_MAX];
81};
82
83/*
84 * Information retrieved from EEPROM.
85 */
86typedef struct {
87	uint16_t	ee_version;		/* Version field */
88	uint16_t	ee_protect;		/* EEPROM protect field */
89	uint16_t	ee_antenna;		/* Antenna Settings */
90	uint16_t	ee_biasCurrents;	/* OB, DB */
91	uint8_t		ee_thresh62;		/* thresh62 */
92	uint8_t		ee_xlnaOn;		/* External LNA timing */
93	uint8_t		ee_xpaOff;		/* Extern output stage timing */
94	uint8_t		ee_xpaOn;		/* Extern output stage timing */
95	uint8_t		ee_rfKill;		/* Single low bit signalling if RF Kill is implemented */
96	uint8_t		ee_devType;		/* Type: PCI, miniPCI, CB */
97	uint8_t		ee_regDomain[AR_REG_DOMAINS_MAX];
98						/* calibrated reg domains */
99	struct tpcMap	ee_tpc[AR_CHANNELS_MAX];
100} HAL_EEPROM_v1;
101#endif /* _ATH_AH_EEPROM_V1_H_ */
102