1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011-2012 Robert N. M. Watson 5 * All rights reserved. 6 * 7 * This software was developed by SRI International and the University of 8 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 9 * ("CTSRD"), as part of the DARPA CRASH research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD$"); 35 36#include <sys/param.h> 37#include <sys/bus.h> 38#include <sys/cons.h> 39#include <sys/endian.h> 40#include <sys/kdb.h> 41#include <sys/kernel.h> 42#include <sys/lock.h> 43#include <sys/mutex.h> 44#include <sys/reboot.h> 45#include <sys/sysctl.h> 46#include <sys/systm.h> 47#include <sys/tty.h> 48 49#include <ddb/ddb.h> 50 51#include <dev/altera/jtag_uart/altera_jtag_uart.h> 52 53devclass_t altera_jtag_uart_devclass; 54 55static SYSCTL_NODE(_hw, OID_AUTO, altera_jtag_uart, 56 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 57 "Altera JTAG UART configuration knobs"); 58 59/* 60 * One-byte buffer as we can't check whether the UART is readable without 61 * actually reading from it, synchronised by a spinlock; this lock also 62 * synchronises access to the I/O ports for non-atomic sequences. These 63 * symbols are public so that the TTY layer can use them when working on an 64 * instance of the UART that is also a low-level console. 65 */ 66char aju_cons_buffer_data; 67int aju_cons_buffer_valid; 68int aju_cons_jtag_present; 69u_int aju_cons_jtag_missed; 70struct mtx aju_cons_lock; 71 72/* 73 * Low-level console driver functions. 74 */ 75static cn_probe_t aju_cnprobe; 76static cn_init_t aju_cninit; 77static cn_term_t aju_cnterm; 78static cn_getc_t aju_cngetc; 79static cn_putc_t aju_cnputc; 80static cn_grab_t aju_cngrab; 81static cn_ungrab_t aju_cnungrab; 82 83/* 84 * JTAG sets the ALTERA_JTAG_UART_CONTROL_AC bit whenever it accesses the 85 * FIFO. This allows us to (sort of) tell when JTAG is present, so that we 86 * can adopt lossy, rather than blocking, behaviour when JTAG isn't there. 87 * When it is present, we do full flow control. This delay is how long we 88 * wait to see if JTAG has really disappeared when finding a full buffer and 89 * no AC bit set. 90 */ 91#define ALTERA_JTAG_UART_AC_POLL_DELAY 10000 92static u_int altera_jtag_uart_ac_poll_delay = 93 ALTERA_JTAG_UART_AC_POLL_DELAY; 94SYSCTL_UINT(_hw_altera_jtag_uart, OID_AUTO, ac_poll_delay, 95 CTLFLAG_RW, &altera_jtag_uart_ac_poll_delay, 0, 96 "Maximum delay waiting for JTAG present flag when buffer is full"); 97 98/* 99 * I/O routines lifted from Deimos. This is not only MIPS-specific, but also 100 * BERI-specific, as we're hard coding the address at which we expect to 101 * find the Altera JTAG UART and using it unconditionally. We use these 102 * low-level routines so that we can perform console I/O long before newbus 103 * has initialised and devices have attached. The TTY layer of the driver 104 * knows about this, and uses the console-layer spinlock instead of the 105 * TTY-layer lock to avoid confusion between layers for the console UART. 106 * 107 * XXXRW: The only place this inter-layer behaviour breaks down is if the 108 * low-level console is used for polled read while the TTY driver is also 109 * looking for input. Probably we should also share buffers between layers. 110 */ 111#define MIPS_XKPHYS_UNCACHED_BASE 0x9000000000000000 112 113typedef uint64_t paddr_t; 114typedef uint64_t vaddr_t; 115 116static inline vaddr_t 117mips_phys_to_uncached(paddr_t phys) 118{ 119 120 return (phys | MIPS_XKPHYS_UNCACHED_BASE); 121} 122 123static inline uint32_t 124mips_ioread_uint32(vaddr_t vaddr) 125{ 126 uint32_t v; 127 128 __asm__ __volatile__ ("lw %0, 0(%1)" : "=r" (v) : "r" (vaddr)); 129 return (v); 130} 131 132static inline void 133mips_iowrite_uint32(vaddr_t vaddr, uint32_t v) 134{ 135 136 __asm__ __volatile__ ("sw %0, 0(%1)" : : "r" (v), "r" (vaddr)); 137} 138 139/* 140 * Little-endian versions of 32-bit I/O routines. 141 */ 142static inline uint32_t 143mips_ioread_uint32le(vaddr_t vaddr) 144{ 145 146 return (le32toh(mips_ioread_uint32(vaddr))); 147} 148 149static inline void 150mips_iowrite_uint32le(vaddr_t vaddr, uint32_t v) 151{ 152 153 mips_iowrite_uint32(vaddr, htole32(v)); 154} 155 156/* 157 * Low-level read and write register routines; the Altera UART is little 158 * endian, so we byte swap 32-bit reads and writes. 159 */ 160static inline uint32_t 161aju_cons_data_read(void) 162{ 163 164 return (mips_ioread_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 165 ALTERA_JTAG_UART_DATA_OFF))); 166} 167 168static inline void 169aju_cons_data_write(uint32_t v) 170{ 171 172 mips_iowrite_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 173 ALTERA_JTAG_UART_DATA_OFF), v); 174} 175 176static inline uint32_t 177aju_cons_control_read(void) 178{ 179 180 return (mips_ioread_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 181 ALTERA_JTAG_UART_CONTROL_OFF))); 182} 183 184static inline void 185aju_cons_control_write(uint32_t v) 186{ 187 188 mips_iowrite_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 189 ALTERA_JTAG_UART_CONTROL_OFF), v); 190} 191 192/* 193 * Slightly higher-level routines aware of buffering and flow control. 194 */ 195static int 196aju_cons_readable(void) 197{ 198 uint32_t v; 199 200 AJU_CONSOLE_LOCK_ASSERT(); 201 202 if (aju_cons_buffer_valid) 203 return (1); 204 v = aju_cons_data_read(); 205 if ((v & ALTERA_JTAG_UART_DATA_RVALID) != 0) { 206 aju_cons_buffer_valid = 1; 207 aju_cons_buffer_data = (v & ALTERA_JTAG_UART_DATA_DATA); 208 return (1); 209 } 210 return (0); 211} 212 213static void 214aju_cons_write(char ch) 215{ 216 uint32_t v; 217 218 AJU_CONSOLE_LOCK_ASSERT(); 219 220 /* 221 * The flow control logic here is somewhat subtle: we want to wait for 222 * write buffer space only while JTAG is present. However, we can't 223 * directly ask if JTAG is present -- just whether it's been seen 224 * since we last cleared the ALTERA_JTAG_UART_CONTROL_AC bit. As 225 * such, implement a polling loop in which we both wait for space and 226 * try to decide whether JTAG has disappeared on us. We will have to 227 * wait one complete polling delay to detect that JTAG has gone away, 228 * but otherwise shouldn't wait any further once it has gone. And we 229 * had to wait for buffer space anyway, if it was there. 230 * 231 * If JTAG is spotted, reset the TTY-layer miss counter so console- 232 * layer clearing of the bit doesn't trigger a TTY-layer 233 * disconnection. 234 * 235 * XXXRW: Notice the inherent race with hardware: in clearing the 236 * bit, we may race with hardware setting the same bit. This can 237 * cause real-world reliability problems due to lost output on the 238 * console. 239 */ 240 v = aju_cons_control_read(); 241 if (v & ALTERA_JTAG_UART_CONTROL_AC) { 242 aju_cons_jtag_present = 1; 243 aju_cons_jtag_missed = 0; 244 v &= ~ALTERA_JTAG_UART_CONTROL_AC; 245 aju_cons_control_write(v); 246 } 247 while ((v & ALTERA_JTAG_UART_CONTROL_WSPACE) == 0) { 248 if (!aju_cons_jtag_present) 249 return; 250 DELAY(altera_jtag_uart_ac_poll_delay); 251 v = aju_cons_control_read(); 252 if (v & ALTERA_JTAG_UART_CONTROL_AC) { 253 aju_cons_jtag_present = 1; 254 v &= ~ALTERA_JTAG_UART_CONTROL_AC; 255 aju_cons_control_write(v); 256 } else 257 aju_cons_jtag_present = 0; 258 } 259 aju_cons_data_write(ch); 260} 261 262static char 263aju_cons_read(void) 264{ 265 266 AJU_CONSOLE_LOCK_ASSERT(); 267 268 while (!aju_cons_readable()); 269 aju_cons_buffer_valid = 0; 270 return (aju_cons_buffer_data); 271} 272 273/* 274 * Implementation of a FreeBSD low-level, polled console driver. 275 */ 276static void 277aju_cnprobe(struct consdev *cp) 278{ 279 280 sprintf(cp->cn_name, "%s%d", AJU_TTYNAME, 0); 281 cp->cn_pri = (boothowto & RB_SERIAL) ? CN_REMOTE : CN_NORMAL; 282} 283 284static void 285aju_cninit(struct consdev *cp) 286{ 287 uint32_t v; 288 289 AJU_CONSOLE_LOCK_INIT(); 290 291 AJU_CONSOLE_LOCK(); 292 v = aju_cons_control_read(); 293 v &= ~ALTERA_JTAG_UART_CONTROL_AC; 294 aju_cons_control_write(v); 295 AJU_CONSOLE_UNLOCK(); 296} 297 298static void 299aju_cnterm(struct consdev *cp) 300{ 301 302} 303 304static int 305aju_cngetc(struct consdev *cp) 306{ 307 int ret; 308 309 AJU_CONSOLE_LOCK(); 310 ret = aju_cons_read(); 311 AJU_CONSOLE_UNLOCK(); 312 return (ret); 313} 314 315static void 316aju_cnputc(struct consdev *cp, int c) 317{ 318 319 AJU_CONSOLE_LOCK(); 320 aju_cons_write(c); 321 AJU_CONSOLE_UNLOCK(); 322} 323 324static void 325aju_cngrab(struct consdev *cp) 326{ 327 328} 329 330static void 331aju_cnungrab(struct consdev *cp) 332{ 333 334} 335 336CONSOLE_DRIVER(aju); 337