1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Bjoern A. Zeeb 5 * All rights reserved. 6 * 7 * This software was developed by SRI International and the University of 8 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249) 9 * ("MRC2"), as part of the DARPA MRC research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35#ifndef _DEV_IF_ATSEREG_H 36#define _DEV_IF_ATSEREG_H 37 38#include <dev/xdma/xdma.h> 39 40#define ATSE_VENDOR 0x6af7 41#define ATSE_DEVICE 0x00bd 42 43/* See hints file/fdt for ctrl port and Avalon FIFO addresses. */ 44 45/* Section 3. Parameter Settings. */ 46/* 47 * This is a lot of options that affect the way things are synthesized. 48 * We cannot really make them all hints and most of them might be stale. 49 */ 50 51/* 3-1 Core Configuration */ 52#if 0 53static const char *atse_core_core_variation[] = { 54 [0] = "10/100/1000 Mbps Ethernet MAC only", 55 [1] = "10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII PCS", 56 [2] = "1000BASE-X/SGMII PCS only", 57 [3] = "1000 Mbps Small MAC", 58 [4] = "10/100 Mbps Small MAC", 59 NULL 60}; 61static const char *atse_core_interface[] = { 62 [0] = "MII", /* Core variation 4. */ 63 [1] = "GMII", /* Core variation 3. */ 64 [2] = "RGMII", /* Core variation 0,1,3. */ 65 [3] = "MII/GMII", /* Core variation 0,1. */ 66 NULL 67}; 68#endif 69#define CORE_CORE_VARIATION 1 /* atse_core_core_variation[] */ 70#define CORE_INTERFACE 3 /* atse_core_interface[] */ 71#define CORE_USE_INTERNAL_FIFO 1 72#define CORE_NUMBER_OF_PORTS 1 /* Internal FIFO count. */ 73#define CORE_USE_TRANSCEIVER_BLOCK 1 /* SGMII PCS transceiver: 74 * LVDS I/O. */ 75 76/* 3-2 MAC Options. */ 77/* Ethernet MAC Options. */ 78#define MAC_ENABLE_10_100_HDX_SUPPORT 0 79#define MAC_ENABLE_RG_G_MII_LOOPBACK 0 80#define MAC_ENABLE_SUPL_MAC_UCAST_ADDR 0 /* Supplementary MAC unicast. */ 81#define MAC_INCLUDE_STATISTICS_COUNTERS 0 82#define MAC_STATISTICS_COUNTERS_64BIT 0 83#define MAC_INCLUDE_MC_HASHTABLE 0 /* Multicast. */ 84#define MAC_ALIGN_PKTHDR_32BIT 1 85#define MAC_ENABLE_FDX_FLOW_CTRL 0 86#define MAC_ENABLE_VLAN_DETECTION 0 /* VLAN and stacked VLANs. */ 87#define MAC_ENABLE_MAGIC_PKT_DETECTION 0 88/* MDIO Module. */ 89#define MAC_MDIO_INCLUDE_MDIO_MODULE 1 90#define MAC_MDIO_HOST_CLOCK_DIVISOR 40 /* Not just On/Off. */ 91 92/* 3-4 FIFO Options. */ 93/* Width and Memory Type. */ 94#if 0 95static char *fifo_memory_block[] = { 96 [0] = "M4K", 97 [1] = "M9K", 98 [2] = "M144K", 99 [3] = "MRAM", 100 [4] = "AUTO", 101 NULL 102}; 103#endif 104#define FIFO_MEMORY_BLOCK 4 105#define FIFO_WITDH 32 /* Other: 8 bits. */ 106/* Depth. */ 107#define FIFO_DEPTH_TX 2048 /* 64 .. 64k, 2048x32bits. */ 108#define FIFO_DEPTH_RX 2048 /* 64 .. 64k, 2048x32bits. */ 109 110#define ATSE_TX_LIST_CNT 5 /* Certainly not bufferbloat. */ 111 112/* 3-4 PCS/Transceiver Options */ 113/* PCS Options. */ 114#define PCS_TXRX_PHY_ID 0x00000000 /* 32 bits */ 115#define PCS_TXRX_ENABLE_SGMII_BRIDGE 0 116/* Transceiver Options. */ 117#define PCS_TXRX_EXP_POWER_DOWN_SIGNAL 0 /* Export power down signal. */ 118#define PCS_TXRX_ENABLE_DYNAMIC_RECONF 0 /* Dynamic trans. reconfig. */ 119#define PCS_TXRX_STARTING_CHANNEL 0 /* 0..284. */ 120 121/* -------------------------------------------------------------------------- */ 122 123/* XXX more values based on the bitmaps provided. Cleanup. */ 124/* See regs above. */ 125#define AVALON_FIFO_TX_BLOCK_DIAGRAM 0 126#define AVALON_FIFO_TX_BLOCK_DIAGRAM_SHOW_SIGANLS 0 127#define AVALON_FIFO_TX_PARAM_SINGLE_RESET_MODE 0 128#define AVALON_FIFO_TX_BASIC_OPTS_DEPTH 16 129#define AVALON_FIFO_TX_BASIC_OPTS_ALLOW_BACKPRESSURE 1 130#define AVALON_FIFO_TX_BASIC_OPTS_CLOCK_SETTING "Single Clock Mode" 131#define AVALON_FIFO_TX_BASIC_OPTS_FIFO_IMPL "Construct FIFO from embedded memory blocks" 132#define AVALON_FIFO_TX_STATUS_PORT_CREATE_STATUS_INT_FOR_INPUT 1 133#define AVALON_FIFO_TX_STATUS_PORT_CREATE_STATUS_INT_FOR_OUTPUT 0 134#define AVALON_FIFO_TX_STATUS_PORT_ENABLE_IRQ_FOR_STATUS_PORT 1 135#define AVALON_FIFO_TX_INPUT_TYPE "AVALONMM_WRITE" 136#define AVALON_FIFO_TX_OUTPUT_TYPE "AVALONST_SOURCE" 137#define AVALON_FIFO_TX_AVALON_MM_PORT_SETTINGS_DATA_WIDTH "" 138#define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_BITS_PER_SYMBOL 8 139#define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_SYM_PER_BEAT 4 140#define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_ERROR_WIDTH 1 141#define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_CHANNEL_WIDTH 0 142#define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_ENABLE_PACKET_DATA 1 143 144#define AVALON_FIFO_RX_BLOCK_DIAGRAM 0 145#define AVALON_FIFO_RX_BLOCK_DIAGRAM_SHOW_SIGNALS 0 146#define AVALON_FIFO_RX_PARAM_SINGLE_RESET_MODE 0 147#define AVALON_FIFO_RX_BASIC_OPTS_DEPTH 16 148#define AVALON_FIFO_RX_BASIC_OPTS_ALLOW_BACKPRESSURE 1 149#define AVALON_FIFO_RX_BASIC_OPTS_CLOCK_SETTING "Single Clock Mode" 150#define AVALON_FIFO_RX_BASIC_OPTS_FIFO_IMPL "Construct FIFO from embedded memory blocks" 151#define AVALON_FIFO_RX_STATUS_PORT_CREATE_STATUS_INT_FOR_INPUT 1 152#define AVALON_FIFO_RX_STATUS_PORT_CREATE_STATUS_INT_FOR_OUTPUT 0 153#define AVALON_FIFO_RX_STATUS_PORT_ENABLE_IRQ_FOR_STATUS_PORT 1 154#define AVALON_FIFO_RX_INPUT_TYPE "AVALONST_SINK" 155#define AVALON_FIFO_RX_OUTPUT_TYPE "AVALONMM_READ" 156#define AVALON_FIFO_RX_AVALON_MM_PORT_SETTINGS_DATA_WIDTH "" 157#define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_BITS_PER_SYMBOL 8 158#define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_SYM_PER_BEAT 4 159#define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_ERROR_WIDTH 6 160#define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_CHANNEL_WIDTH 0 161#define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_ENABLE_PACKET_DATA 1 162 163/* -------------------------------------------------------------------------- */ 164 165/* 5. Configuration Register Space. */ 166 167/* 5-1, MAC Configuration Register Space; Dword offsets. */ 168/* 0x00 - 0x17, Base Configuration. */ 169#define BASE_CONFIG_REV 0x00 /* ro, IP Core ver. */ 170#define BASE_CFG_REV_VER_MASK 0x0000FFFF 171#define BASE_CFG_REV_CUST_VERSION__MASK 0xFFFF0000 172 173#define BASE_CFG_SCRATCH 0x01 /* rw, 0 */ 174 175#define BASE_CFG_COMMAND_CONFIG 0x02 /* rw, 0 */ 176#define BASE_CFG_COMMAND_CONFIG_TX_ENA (1<<0) /* rw */ 177#define BASE_CFG_COMMAND_CONFIG_RX_ENA (1<<1) /* rw */ 178#define BASE_CFG_COMMAND_CONFIG_XON_GEN (1<<2) /* rw */ 179#define BASE_CFG_COMMAND_CONFIG_ETH_SPEED (1<<3) /* rw */ 180#define BASE_CFG_COMMAND_CONFIG_PROMIS_EN (1<<4) /* rw */ 181#define BASE_CFG_COMMAND_CONFIG_PAD_EN (1<<5) /* rw */ 182#define BASE_CFG_COMMAND_CONFIG_CRC_FWD (1<<6) /* rw */ 183#define BASE_CFG_COMMAND_CONFIG_PAUSE_FWD (1<<7) /* rw */ 184#define BASE_CFG_COMMAND_CONFIG_PAUSE_IGNORE (1<<8) /* rw */ 185#define BASE_CFG_COMMAND_CONFIG_TX_ADDR_INS (1<<9) /* rw */ 186#define BASE_CFG_COMMAND_CONFIG_HD_ENA (1<<10) /* rw */ 187#define BASE_CFG_COMMAND_CONFIG_EXCESS_COL (1<<11) /* ro */ 188#define BASE_CFG_COMMAND_CONFIG_LATE_COL (1<<12) /* ro */ 189#define BASE_CFG_COMMAND_CONFIG_SW_RESET (1<<13) /* rw */ 190#define BASE_CFG_COMMAND_CONFIG_MHASH_SEL (1<<14) /* rw */ 191#define BASE_CFG_COMMAND_CONFIG_LOOP_ENA (1<<15) /* rw */ 192#define BASE_CFG_COMMAND_CONFIG_TX_ADDR_SEL (1<<16|1<<17|1<<18) /* rw */ 193#define BASE_CFG_COMMAND_CONFIG_MAGIC_ENA (1<<19) /* rw */ 194#define BASE_CFG_COMMAND_CONFIG_SLEEP (1<<20) /* rw */ 195#define BASE_CFG_COMMAND_CONFIG_WAKEUP (1<<21) /* ro */ 196#define BASE_CFG_COMMAND_CONFIG_XOFF_GEN (1<<22) /* rw */ 197#define BASE_CFG_COMMAND_CONFIG_CNTL_FRM_ENA (1<<23) /* rw */ 198#define BASE_CFG_COMMAND_CONFIG_NO_LGTH_CHECK (1<<24) /* rw */ 199#define BASE_CFG_COMMAND_CONFIG_ENA_10 (1<<25) /* rw */ 200#define BASE_CFG_COMMAND_CONFIG_RX_ERR_DISC (1<<26) /* rw */ 201#define BASE_CFG_COMMAND_CONFIG_DISABLE_READ_TIMEOUT (1<<27) /* rw */ 202 /* 28-30 Reserved. */ /* - */ 203#define BASE_CFG_COMMAND_CONFIG_CNT_RESET (1<<31) /* rw */ 204 205#define BASE_CFG_MAC_0 0x03 /* rw, 0 */ 206#define BASE_CFG_MAC_1 0x04 /* rw, 0 */ 207#define BASE_CFG_FRM_LENGTH 0x05 /* rw/ro, 1518 */ 208#define BASE_CFG_PAUSE_QUANT 0x06 /* rw, 0 */ 209#define BASE_CFG_RX_SECTION_EMPTY 0x07 /* rw/ro, 0 */ 210#define BASE_CFG_RX_SECTION_FULL 0x08 /* rw/ro, 0 */ 211#define BASE_CFG_TX_SECTION_EMPTY 0x09 /* rw/ro, 0 */ 212#define BASE_CFG_TX_SECTION_FULL 0x0A /* rw/ro, 0 */ 213#define BASE_CFG_RX_ALMOST_EMPTY 0x0B /* rw/ro, 0 */ 214#define BASE_CFG_RX_ALMOST_FULL 0x0C /* rw/ro, 0 */ 215#define BASE_CFG_TX_ALMOST_EMPTY 0x0D /* rw/ro, 0 */ 216#define BASE_CFG_TX_ALMOST_FULL 0x0E /* rw/ro, 0 */ 217#define BASE_CFG_MDIO_ADDR0 0x0F /* rw, 0 */ 218#define BASE_CFG_MDIO_ADDR1 0x10 /* rw, 1 */ 219#define BASE_CFG_HOLDOFF_QUANT 0x11 /* rw, 0xFFFF */ 220/* 0x12-0x16 Reserved. */ /* -, 0 */ 221#define BASE_CFG_TX_IPG_LENGTH 0x17 /* rw, 0 */ 222 223/* 0x18 - 0x38, Statistics Counters. */ 224#define STATS_A_MAC_ID_0 0x18 /* ro */ 225#define STATS_A_MAC_ID_1 0x19 /* ro */ 226#define STATS_A_FRAMES_TX_OK 0x1A /* ro */ 227#define STATS_A_FRAMES_RX_OK 0x1B /* ro */ 228#define STATS_A_FCS_ERRORS 0x1C /* ro */ 229#define STATS_A_ALIGNMENT_ERRORS 0x1D /* ro */ 230#define STATS_A_OCTETS_TX_OK 0x1E /* ro */ 231#define STATS_A_OCTETS_RX_OK 0x1F /* ro */ 232#define STATS_A_TX_PAUSE_MAX_CTRL_FRAME 0x20 /* ro */ 233#define STATS_A_RX_PAUSE_MAX_CTRL_FRAME 0x21 /* ro */ 234#define STATS_IF_IN_ERRORS 0x22 /* ro */ 235#define STATS_IF_OUT_ERRORS 0x23 /* ro */ 236#define STATS_IF_IN_UCAST_PKTS 0x24 /* ro */ 237#define STATS_IF_IN_MULTICAST_PKTS 0x25 /* ro */ 238#define STATS_IF_IN_BROADCAST_PKTS 0x26 /* ro */ 239#define STATS_IF_OUT_DISCARDS 0x27 /* ro */ 240#define STATS_IF_OUT_UCAST_PKTS 0x28 /* ro */ 241#define STATS_IF_OUT_MULTICAST_PKTS 0x29 /* ro */ 242#define STATS_IF_OUT_BROADCAST_PKTS 0x2A /* ro */ 243#define STATS_ETHER_STATS_DROP_EVENT 0x2B /* ro */ 244#define STATS_ETHER_STATS_OCTETS 0x2C /* ro */ 245#define STATS_ETHER_STATS_PKTS 0x2D /* ro */ 246#define STATS_ETHER_STATS_USIZE_PKTS 0x2E /* ro */ 247#define STATS_ETHER_STATS_OSIZE_PKTS 0x2F /* ro */ 248#define STATS_ETHER_STATS_PKTS_64_OCTETS 0x30 /* ro */ 249#define STATS_ETHER_STATS_PKTS_65_TO_127_OCTETS 0x31 /* ro */ 250#define STATS_ETHER_STATS_PKTS_128_TO_255_OCTETS 0x32 /* ro */ 251#define STATS_ETHER_STATS_PKTS_256_TO_511_OCTETS 0x33 /* ro */ 252#define STATS_ETHER_STATS_PKTS_512_TO_1023_OCTETS 0x34 /* ro */ 253#define STATS_ETHER_STATS_PKTS_1024_TO_1518_OCTETS 0x35 /* ro */ 254#define STATS_ETHER_STATS_PKTS_1519_TO_X_OCTETS 0x36 /* ro */ 255#define STATS_ETHER_STATS_JABBERS 0x37 /* ro */ 256#define STATS_ETHER_STATS_FRAGMENTS 0x38 /* ro */ 257 /* 0x39, Reserved. */ /* - */ 258 259/* 0x3A, Transmit Command. */ 260#define TX_CMD_STAT 0x3A /* rw */ 261#define TX_CMD_STAT_OMIT_CRC (1<<17) 262#define TX_CMD_STAT_TX_SHIFT16 (1<<18) 263 264/* 0x3B, Receive Command. */ 265#define RX_CMD_STAT 0x3B /* rw */ 266#define RX_CMD_STAT_RX_SHIFT16 (1<<25) 267 268/* 0x3C - 0x3E, Extended Statistics Counters. */ 269#define ESTATS_MSB_A_OCTETS_TX_OK 0x3C /* ro */ 270#define ESTATS_MSB_A_OCTETS_RX_OK 0x3D /* ro */ 271#define ESTATS_MSB_ETHER_STATS_OCTETS 0x3E /* ro */ 272 273/* 0x3F, Reserved. */ 274 275/* 0x40 - 0x7F, Multicast Hash Table. */ 276#define MHASH_START 0x40 277#define MHASH_LEN 0x3F 278 279/* 0x80 - 0x9F, MDIO Space 0 or PCS Function Configuration. */ 280#define MDIO_0_START 0x80 281 282/* The following are offsets to the first PCS register at 0x80. */ 283/* See sys/dev/mii/mii.h. */ 284#define PCS_CONTROL 0x00 /* rw */ 285 /* Bits 0:4, Reserved. */ /* - */ 286#define PCS_CONTROL_UNIDIRECTIONAL_ENABLE (1<<5) /* rw */ 287#define PCS_CONTROL_SPEED_SELECTION (1<<6|1<<13) /* ro */ 288#define PCS_CONTROL_COLLISION_TEST (1<<7) /* ro */ 289#define PCS_CONTROL_DUPLEX_MODE (1<<8) /* ro */ 290#define PCS_CONTROL_RESTART_AUTO_NEGOTIATION (1<<9) /* rw */ 291#define PCS_CONTROL_ISOLATE (1<<10) /* rw */ 292#define PCS_CONTROL_POWERDOWN (1<<11) /* rw */ 293#define PCS_CONTROL_AUTO_NEGOTIATION_ENABLE (1<<12) /* rw */ 294 /* See bit 6 above. */ /* ro */ 295#define PCS_CONTROL_LOOPBACK (1<<14) /* rw */ 296#define PCS_CONTROL_RESET (1<<15) /* rw */ 297 298#define PCS_STATUS 0x01 /* ro */ 299#define PCS_STATUS_EXTENDED_CAPABILITY (1<<0) /* ro */ 300#define PCS_STATUS_JABBER_DETECT (1<<1) /* -, 0 */ 301#define PCS_STATUS_LINK_STATUS (1<<2) /* ro */ 302#define PCS_STATUS_AUTO_NEGOTIATION_ABILITY (1<<3) /* ro */ 303#define PCS_STATUS_REMOTE_FAULT (1<<4) /* -, 0 */ 304#define PCS_STATUS_AUTO_NEGOTIATION_COMPLETE (1<<5) /* ro */ 305#define PCS_STATUS_MF_PREAMBLE_SUPPRESSION (1<<6) /* -, 0 */ 306#define PCS_STATUS_UNIDIRECTIONAL_ABILITY (1<<7) /* ro */ 307#define PCS_STATUS_EXTENDED_STATUS (1<<8) /* -, 0 */ 308#define PCS_STATUS_100BASET2_HALF_DUPLEX (1<<9) /* ro */ 309#define PCS_STATUS_100BASET2_FULL_DUPLEX (1<<10) /* ro */ 310#define PCS_STATUS_10MBPS_HALF_DUPLEX (1<<11) /* ro */ 311#define PCS_STATUS_10MBPS_FULL_DUPLEX (1<<12) /* ro */ 312#define PCS_STATUS_100BASE_X_HALF_DUPLEX (1<<13) /* ro */ 313#define PCS_STATUS_100BASE_X_FULL_DUPLEX (1<<14) /* ro */ 314#define PCS_STATUS_100BASE_T4 (1<<15) /* ro */ 315 316#define PCS_PHY_IDENTIFIER_0 0x02 /* ro */ 317#define PCS_PHY_IDENTIFIER_1 0x03 /* ro */ 318 319#define PCS_DEV_ABILITY 0x04 /* rw */ 320 /* 1000BASE-X */ 321 /* Bits 0:4, Reserved. */ /* - */ 322#define PCS_DEV_ABILITY_1000BASE_X_FD (1<<5) /* rw */ 323#define PCS_DEV_ABILITY_1000BASE_X_HD (1<<6) /* rw */ 324#define PCS_DEV_ABILITY_1000BASE_X_PS1 (1<<7) /* rw */ 325#define PCS_DEV_ABILITY_1000BASE_X_PS2 (1<<8) /* rw */ 326 /* Bits 9:11, Reserved. */ /* - */ 327#define PCS_DEV_ABILITY_1000BASE_X_RF1 (1<<12) /* rw */ 328#define PCS_DEV_ABILITY_1000BASE_X_RF2 (1<<13) /* rw */ 329#define PCS_DEV_ABILITY_1000BASE_X_ACK (1<<14) /* rw */ 330#define PCS_DEV_ABILITY_1000BASE_X_NP (1<<15) /* rw */ 331 332#define PCS_PARTNER_ABILITY 0x05 /* ro */ 333 /* 1000BASE-X */ 334 /* Bits 0:4, Reserved. */ /* - */ 335#define PCS_PARTNER_ABILITY_1000BASE_X_FD (1<<5) /* ro */ 336#define PCS_PARTNER_ABILITY_1000BASE_X_HD (1<<6) /* ro */ 337#define PCS_PARTNER_ABILITY_1000BASE_X_PS1 (1<<7) /* ro */ 338#define PCS_PARTNER_ABILITY_1000BASE_X_PS2 (1<<8) /* ro */ 339 /* Bits 9:11, Reserved. */ /* - */ 340#define PCS_PARTNER_ABILITY_1000BASE_X_RF1 (1<<12) /* ro */ 341#define PCS_PARTNER_ABILITY_1000BASE_X_RF2 (1<<13) /* ro */ 342#define PCS_PARTNER_ABILITY_1000BASE_X_ACK (1<<14) /* ro */ 343#define PCS_PARTNER_ABILITY_1000BASE_X_NP (1<<15) /* ro */ 344 /* SGMII */ 345 /* Bits 0:9, Reserved. */ /* - */ 346#define PCS_PARTNER_ABILITY_SGMII_COPPER_SPEED0 (1<<10) /* ro */ 347#define PCS_PARTNER_ABILITY_SGMII_COPPER_SPEED1 (1<<11) /* ro */ 348#define PCS_PARTNER_ABILITY_SGMII_COPPER_DUPLEX_STATUS (1<<12) /* ro */ 349 /* Bit 13, Reserved. */ /* - */ 350#define PCS_PARTNER_ABILITY_SGMII_ACK (1<<14) /* ro */ 351#define PCS_PARTNER_ABILITY_SGMII_COPPER_LINK_STATUS (1<<15) /* ro */ 352 353#define PCS_AN_EXPANSION 0x06 /* ro */ 354#define PCS_AN_EXPANSION_LINK_PARTNER_AUTO_NEGOTIATION_ABLE (1<<0) /* ro */ 355#define PCS_AN_EXPANSION_PAGE_RECEIVE (1<<1) /* ro */ 356#define PCS_AN_EXPANSION_NEXT_PAGE_ABLE (1<<2) /* -, 0 */ 357 /* Bits 3:15, Reserved. */ /* - */ 358 359#define PCS_DEVICE_NEXT_PAGE 0x07 /* ro */ 360#define PCS_PARTNER_NEXT_PAGE 0x08 /* ro */ 361#define PCS_MASTER_SLAVE_CNTL 0x09 /* ro */ 362#define PCS_MASTER_SLAVE_STAT 0x0A /* ro */ 363 /* 0x0B - 0x0E, Reserved */ /* - */ 364#define PCS_EXTENDED_STATUS 0x0F /* ro */ 365/* Specific Extended Registers. */ 366#define PCS_EXT_SCRATCH 0x10 /* rw */ 367#define PCS_EXT_REV 0x11 /* ro */ 368#define PCS_EXT_LINK_TIMER_0 0x12 /* rw */ 369#define PCS_EXT_LINK_TIMER_1 0x13 /* rw */ 370#define PCS_EXT_IF_MODE 0x14 /* rw */ 371#define PCS_EXT_IF_MODE_SGMII_ENA (1<<0) /* rw */ 372#define PCS_EXT_IF_MODE_USE_SGMII_AN (1<<1) /* rw */ 373#define PCS_EXT_IF_MODE_SGMII_SPEED1 (1<<2) /* rw */ 374#define PCS_EXT_IF_MODE_SGMII_SPEED0 (1<<3) /* rw */ 375#define PCS_EXT_IF_MODE_SGMII_DUPLEX (1<<4) /* rw */ 376 /* Bits 5:15, Reserved. */ /* - */ 377 378#define PCS_EXT_DISABLE_READ_TIMEOUT 0x15 /* rw */ 379#define PCS_EXT_READ_TIMEOUT 0x16 /* r0 */ 380 /* 0x17-0x1F, Reserved. */ 381 382/* 0xA0 - 0xBF, MDIO Space 1. */ 383#define MDIO_1_START 0xA0 384#define ATSE_BMCR MDIO_1_START 385 386/* 0xC0 - 0xC7, Supplementary Address. */ 387#define SUPPL_ADDR_SMAC_0_0 0xC0 /* rw */ 388#define SUPPL_ADDR_SMAC_0_1 0xC1 /* rw */ 389#define SUPPL_ADDR_SMAC_1_0 0xC2 /* rw */ 390#define SUPPL_ADDR_SMAC_1_1 0xC3 /* rw */ 391#define SUPPL_ADDR_SMAC_2_0 0xC4 /* rw */ 392#define SUPPL_ADDR_SMAC_2_1 0xC5 /* rw */ 393#define SUPPL_ADDR_SMAC_3_0 0xC6 /* rw */ 394#define SUPPL_ADDR_SMAC_3_1 0xC7 /* rw */ 395 396/* 0xC8 - 0xCF, Reserved; set to zero, ignore on read. */ 397/* 0xD7 - 0xFF, Reserved; set to zero, ignore on read. */ 398 399/* -------------------------------------------------------------------------- */ 400 401/* DE4 Intel Strata Flash Ethernet Option Bits area. */ 402/* XXX-BZ this is something a loader will have to handle for us. */ 403#define ALTERA_ETHERNET_OPTION_BITS_OFF 0x00008000 404#define ALTERA_ETHERNET_OPTION_BITS_LEN 0x00007fff 405 406/* -------------------------------------------------------------------------- */ 407 408struct atse_softc { 409 struct ifnet *atse_ifp; 410 struct resource *atse_mem_res; 411 device_t atse_miibus; 412 device_t atse_dev; 413 int atse_unit; 414 int atse_mem_rid; 415 int atse_phy_addr; 416 int atse_if_flags; 417 bus_addr_t atse_bmcr0; 418 bus_addr_t atse_bmcr1; 419 uint32_t atse_flags; 420#define ATSE_FLAGS_LINK 0x00000001 421#define ATSE_FLAGS_ERROR 0x00000002 422#define ATSE_FLAGS_SOP_SEEN 0x00000004 423 uint8_t atse_eth_addr[ETHER_ADDR_LEN]; 424#define ATSE_ETH_ADDR_DEF 0x01 425#define ATSE_ETH_ADDR_SUPP1 0x02 426#define ATSE_ETH_ADDR_SUPP2 0x04 427#define ATSE_ETH_ADDR_SUPP3 0x08 428#define ATSE_ETH_ADDR_SUPP4 0x10 429#define ATSE_ETH_ADDR_ALL 0x1f 430 int16_t atse_rx_cycles; /* POLLING */ 431#define RX_CYCLES_IN_INTR 5 432 uint32_t atse_rx_err[6]; 433#define ATSE_RX_ERR_FIFO_THRES_EOP 0 /* FIFO threshold reached, on EOP. */ 434#define ATSE_RX_ERR_ELEN 1 /* Frame/payload length not valid. */ 435#define ATSE_RX_ERR_CRC32 2 /* CRC-32 error. */ 436#define ATSE_RX_ERR_FIFO_THRES_TRUNC 3 /* FIFO thresh., truncated frame. */ 437#define ATSE_RX_ERR_4 4 /* ? */ 438#define ATSE_RX_ERR_5 5 /* / */ 439#define ATSE_RX_ERR_MAX 6 440 struct callout atse_tick; 441 struct mtx atse_mtx; 442 device_t dev; 443 444 /* xDMA */ 445 xdma_controller_t *xdma_tx; 446 xdma_channel_t *xchan_tx; 447 void *ih_tx; 448 int txcount; 449 450 xdma_controller_t *xdma_rx; 451 xdma_channel_t *xchan_rx; 452 void *ih_rx; 453 454 struct buf_ring *br; 455 struct mtx br_mtx; 456}; 457 458int atse_attach(device_t); 459int atse_detach_dev(device_t); 460void atse_detach_resources(device_t); 461 462int atse_miibus_readreg(device_t, int, int); 463int atse_miibus_writereg(device_t, int, int, int); 464void atse_miibus_statchg(device_t); 465 466extern devclass_t atse_devclass; 467 468#endif /* _DEV_IF_ATSEREG_H */ 469