1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD$"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/endian.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/mbuf.h> 42#include <sys/module.h> 43#include <sys/rman.h> 44#include <sys/queue.h> 45#include <sys/socket.h> 46#include <sys/sockio.h> 47#include <sys/sysctl.h> 48#include <sys/taskqueue.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_llc.h> 57#include <net/if_media.h> 58#include <net/if_types.h> 59#include <net/if_vlan_var.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/ip.h> 64#include <netinet/tcp.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <machine/bus.h> 73#include <machine/in_cksum.h> 74 75#include <dev/ale/if_alereg.h> 76#include <dev/ale/if_alevar.h> 77 78/* "device miibus" required. See GENERIC if you get errors here. */ 79#include "miibus_if.h" 80 81/* For more information about Tx checksum offload issues see ale_encap(). */ 82#define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 83 84MODULE_DEPEND(ale, pci, 1, 1, 1); 85MODULE_DEPEND(ale, ether, 1, 1, 1); 86MODULE_DEPEND(ale, miibus, 1, 1, 1); 87 88/* Tunables. */ 89static int msi_disable = 0; 90static int msix_disable = 0; 91TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 92TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 93 94/* 95 * Devices supported by this driver. 96 */ 97static const struct ale_dev { 98 uint16_t ale_vendorid; 99 uint16_t ale_deviceid; 100 const char *ale_name; 101} ale_devs[] = { 102 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 103 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 104}; 105 106static int ale_attach(device_t); 107static int ale_check_boundary(struct ale_softc *); 108static int ale_detach(device_t); 109static int ale_dma_alloc(struct ale_softc *); 110static void ale_dma_free(struct ale_softc *); 111static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 112static int ale_encap(struct ale_softc *, struct mbuf **); 113static void ale_get_macaddr(struct ale_softc *); 114static void ale_init(void *); 115static void ale_init_locked(struct ale_softc *); 116static void ale_init_rx_pages(struct ale_softc *); 117static void ale_init_tx_ring(struct ale_softc *); 118static void ale_int_task(void *, int); 119static int ale_intr(void *); 120static int ale_ioctl(struct ifnet *, u_long, caddr_t); 121static void ale_mac_config(struct ale_softc *); 122static int ale_miibus_readreg(device_t, int, int); 123static void ale_miibus_statchg(device_t); 124static int ale_miibus_writereg(device_t, int, int, int); 125static int ale_mediachange(struct ifnet *); 126static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 127static void ale_phy_reset(struct ale_softc *); 128static int ale_probe(device_t); 129static void ale_reset(struct ale_softc *); 130static int ale_resume(device_t); 131static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 132 uint32_t, uint32_t *); 133static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 134static int ale_rxeof(struct ale_softc *sc, int); 135static void ale_rxfilter(struct ale_softc *); 136static void ale_rxvlan(struct ale_softc *); 137static void ale_setlinkspeed(struct ale_softc *); 138static void ale_setwol(struct ale_softc *); 139static int ale_shutdown(device_t); 140static void ale_start(struct ifnet *); 141static void ale_start_locked(struct ifnet *); 142static void ale_stats_clear(struct ale_softc *); 143static void ale_stats_update(struct ale_softc *); 144static void ale_stop(struct ale_softc *); 145static void ale_stop_mac(struct ale_softc *); 146static int ale_suspend(device_t); 147static void ale_sysctl_node(struct ale_softc *); 148static void ale_tick(void *); 149static void ale_txeof(struct ale_softc *); 150static void ale_watchdog(struct ale_softc *); 151static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 152static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 153static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 154 155static device_method_t ale_methods[] = { 156 /* Device interface. */ 157 DEVMETHOD(device_probe, ale_probe), 158 DEVMETHOD(device_attach, ale_attach), 159 DEVMETHOD(device_detach, ale_detach), 160 DEVMETHOD(device_shutdown, ale_shutdown), 161 DEVMETHOD(device_suspend, ale_suspend), 162 DEVMETHOD(device_resume, ale_resume), 163 164 /* MII interface. */ 165 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 166 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 167 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 168 169 DEVMETHOD_END 170}; 171 172static driver_t ale_driver = { 173 "ale", 174 ale_methods, 175 sizeof(struct ale_softc) 176}; 177 178static devclass_t ale_devclass; 179 180DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, NULL, NULL); 181MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs, 182 nitems(ale_devs)); 183DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL); 184 185static struct resource_spec ale_res_spec_mem[] = { 186 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 187 { -1, 0, 0 } 188}; 189 190static struct resource_spec ale_irq_spec_legacy[] = { 191 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 192 { -1, 0, 0 } 193}; 194 195static struct resource_spec ale_irq_spec_msi[] = { 196 { SYS_RES_IRQ, 1, RF_ACTIVE }, 197 { -1, 0, 0 } 198}; 199 200static struct resource_spec ale_irq_spec_msix[] = { 201 { SYS_RES_IRQ, 1, RF_ACTIVE }, 202 { -1, 0, 0 } 203}; 204 205static int 206ale_miibus_readreg(device_t dev, int phy, int reg) 207{ 208 struct ale_softc *sc; 209 uint32_t v; 210 int i; 211 212 sc = device_get_softc(dev); 213 214 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 215 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 216 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 217 DELAY(5); 218 v = CSR_READ_4(sc, ALE_MDIO); 219 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 220 break; 221 } 222 223 if (i == 0) { 224 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 225 return (0); 226 } 227 228 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 229} 230 231static int 232ale_miibus_writereg(device_t dev, int phy, int reg, int val) 233{ 234 struct ale_softc *sc; 235 uint32_t v; 236 int i; 237 238 sc = device_get_softc(dev); 239 240 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 241 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 242 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 243 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 244 DELAY(5); 245 v = CSR_READ_4(sc, ALE_MDIO); 246 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 247 break; 248 } 249 250 if (i == 0) 251 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 252 253 return (0); 254} 255 256static void 257ale_miibus_statchg(device_t dev) 258{ 259 struct ale_softc *sc; 260 struct mii_data *mii; 261 struct ifnet *ifp; 262 uint32_t reg; 263 264 sc = device_get_softc(dev); 265 mii = device_get_softc(sc->ale_miibus); 266 ifp = sc->ale_ifp; 267 if (mii == NULL || ifp == NULL || 268 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 269 return; 270 271 sc->ale_flags &= ~ALE_FLAG_LINK; 272 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 273 (IFM_ACTIVE | IFM_AVALID)) { 274 switch (IFM_SUBTYPE(mii->mii_media_active)) { 275 case IFM_10_T: 276 case IFM_100_TX: 277 sc->ale_flags |= ALE_FLAG_LINK; 278 break; 279 case IFM_1000_T: 280 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 281 sc->ale_flags |= ALE_FLAG_LINK; 282 break; 283 default: 284 break; 285 } 286 } 287 288 /* Stop Rx/Tx MACs. */ 289 ale_stop_mac(sc); 290 291 /* Program MACs with resolved speed/duplex/flow-control. */ 292 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 293 ale_mac_config(sc); 294 /* Reenable Tx/Rx MACs. */ 295 reg = CSR_READ_4(sc, ALE_MAC_CFG); 296 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 297 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 298 } 299} 300 301static void 302ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 303{ 304 struct ale_softc *sc; 305 struct mii_data *mii; 306 307 sc = ifp->if_softc; 308 ALE_LOCK(sc); 309 if ((ifp->if_flags & IFF_UP) == 0) { 310 ALE_UNLOCK(sc); 311 return; 312 } 313 mii = device_get_softc(sc->ale_miibus); 314 315 mii_pollstat(mii); 316 ifmr->ifm_status = mii->mii_media_status; 317 ifmr->ifm_active = mii->mii_media_active; 318 ALE_UNLOCK(sc); 319} 320 321static int 322ale_mediachange(struct ifnet *ifp) 323{ 324 struct ale_softc *sc; 325 struct mii_data *mii; 326 struct mii_softc *miisc; 327 int error; 328 329 sc = ifp->if_softc; 330 ALE_LOCK(sc); 331 mii = device_get_softc(sc->ale_miibus); 332 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 333 PHY_RESET(miisc); 334 error = mii_mediachg(mii); 335 ALE_UNLOCK(sc); 336 337 return (error); 338} 339 340static int 341ale_probe(device_t dev) 342{ 343 const struct ale_dev *sp; 344 int i; 345 uint16_t vendor, devid; 346 347 vendor = pci_get_vendor(dev); 348 devid = pci_get_device(dev); 349 sp = ale_devs; 350 for (i = 0; i < nitems(ale_devs); i++) { 351 if (vendor == sp->ale_vendorid && 352 devid == sp->ale_deviceid) { 353 device_set_desc(dev, sp->ale_name); 354 return (BUS_PROBE_DEFAULT); 355 } 356 sp++; 357 } 358 359 return (ENXIO); 360} 361 362static void 363ale_get_macaddr(struct ale_softc *sc) 364{ 365 uint32_t ea[2], reg; 366 int i, vpdc; 367 368 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 369 if ((reg & SPI_VPD_ENB) != 0) { 370 reg &= ~SPI_VPD_ENB; 371 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 372 } 373 374 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 375 /* 376 * PCI VPD capability found, let TWSI reload EEPROM. 377 * This will set ethernet address of controller. 378 */ 379 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 380 TWSI_CTRL_SW_LD_START); 381 for (i = 100; i > 0; i--) { 382 DELAY(1000); 383 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 384 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 385 break; 386 } 387 if (i == 0) 388 device_printf(sc->ale_dev, 389 "reloading EEPROM timeout!\n"); 390 } else { 391 if (bootverbose) 392 device_printf(sc->ale_dev, 393 "PCI VPD capability not found!\n"); 394 } 395 396 ea[0] = CSR_READ_4(sc, ALE_PAR0); 397 ea[1] = CSR_READ_4(sc, ALE_PAR1); 398 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 399 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 400 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 401 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 402 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 403 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 404} 405 406static void 407ale_phy_reset(struct ale_softc *sc) 408{ 409 410 /* Reset magic from Linux. */ 411 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 412 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 413 GPHY_CTRL_PHY_PLL_ON); 414 DELAY(1000); 415 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 416 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 417 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 418 DELAY(1000); 419 420#define ATPHY_DBG_ADDR 0x1D 421#define ATPHY_DBG_DATA 0x1E 422 423 /* Enable hibernation mode. */ 424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 425 ATPHY_DBG_ADDR, 0x0B); 426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 427 ATPHY_DBG_DATA, 0xBC00); 428 /* Set Class A/B for all modes. */ 429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 430 ATPHY_DBG_ADDR, 0x00); 431 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 432 ATPHY_DBG_DATA, 0x02EF); 433 /* Enable 10BT power saving. */ 434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 435 ATPHY_DBG_ADDR, 0x12); 436 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 437 ATPHY_DBG_DATA, 0x4C04); 438 /* Adjust 1000T power. */ 439 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 440 ATPHY_DBG_ADDR, 0x04); 441 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 442 ATPHY_DBG_ADDR, 0x8BBB); 443 /* 10BT center tap voltage. */ 444 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 445 ATPHY_DBG_ADDR, 0x05); 446 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 447 ATPHY_DBG_ADDR, 0x2C46); 448 449#undef ATPHY_DBG_ADDR 450#undef ATPHY_DBG_DATA 451 DELAY(1000); 452} 453 454static int 455ale_attach(device_t dev) 456{ 457 struct ale_softc *sc; 458 struct ifnet *ifp; 459 uint16_t burst; 460 int error, i, msic, msixc, pmc; 461 uint32_t rxf_len, txf_len; 462 463 error = 0; 464 sc = device_get_softc(dev); 465 sc->ale_dev = dev; 466 467 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 468 MTX_DEF); 469 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 470 NET_TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 471 472 /* Map the device. */ 473 pci_enable_busmaster(dev); 474 sc->ale_res_spec = ale_res_spec_mem; 475 sc->ale_irq_spec = ale_irq_spec_legacy; 476 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 477 if (error != 0) { 478 device_printf(dev, "cannot allocate memory resources.\n"); 479 goto fail; 480 } 481 482 /* Set PHY address. */ 483 sc->ale_phyaddr = ALE_PHY_ADDR; 484 485 /* Reset PHY. */ 486 ale_phy_reset(sc); 487 488 /* Reset the ethernet controller. */ 489 ale_reset(sc); 490 491 /* Get PCI and chip id/revision. */ 492 sc->ale_rev = pci_get_revid(dev); 493 if (sc->ale_rev >= 0xF0) { 494 /* L2E Rev. B. AR8114 */ 495 sc->ale_flags |= ALE_FLAG_FASTETHER; 496 } else { 497 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 498 /* L1E AR8121 */ 499 sc->ale_flags |= ALE_FLAG_JUMBO; 500 } else { 501 /* L2E Rev. A. AR8113 */ 502 sc->ale_flags |= ALE_FLAG_FASTETHER; 503 } 504 } 505 /* 506 * All known controllers seems to require 4 bytes alignment 507 * of Tx buffers to make Tx checksum offload with custom 508 * checksum generation method work. 509 */ 510 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 511 /* 512 * All known controllers seems to have issues on Rx checksum 513 * offload for fragmented IP datagrams. 514 */ 515 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 516 /* 517 * Don't use Tx CMB. It is known to cause RRS update failure 518 * under certain circumstances. Typical phenomenon of the 519 * issue would be unexpected sequence number encountered in 520 * Rx handler. 521 */ 522 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 523 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 524 MASTER_CHIP_REV_SHIFT; 525 if (bootverbose) { 526 device_printf(dev, "PCI device revision : 0x%04x\n", 527 sc->ale_rev); 528 device_printf(dev, "Chip id/revision : 0x%04x\n", 529 sc->ale_chip_rev); 530 } 531 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 532 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 533 /* 534 * Uninitialized hardware returns an invalid chip id/revision 535 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 536 */ 537 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 538 rxf_len == 0xFFFFFFF) { 539 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 540 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 541 txf_len, rxf_len); 542 error = ENXIO; 543 goto fail; 544 } 545 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 546 547 /* Allocate IRQ resources. */ 548 msixc = pci_msix_count(dev); 549 msic = pci_msi_count(dev); 550 if (bootverbose) { 551 device_printf(dev, "MSIX count : %d\n", msixc); 552 device_printf(dev, "MSI count : %d\n", msic); 553 } 554 555 /* Prefer MSIX over MSI. */ 556 if (msix_disable == 0 || msi_disable == 0) { 557 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 558 pci_alloc_msix(dev, &msixc) == 0) { 559 if (msixc == ALE_MSIX_MESSAGES) { 560 device_printf(dev, "Using %d MSIX messages.\n", 561 msixc); 562 sc->ale_flags |= ALE_FLAG_MSIX; 563 sc->ale_irq_spec = ale_irq_spec_msix; 564 } else 565 pci_release_msi(dev); 566 } 567 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 568 msic == ALE_MSI_MESSAGES && 569 pci_alloc_msi(dev, &msic) == 0) { 570 if (msic == ALE_MSI_MESSAGES) { 571 device_printf(dev, "Using %d MSI messages.\n", 572 msic); 573 sc->ale_flags |= ALE_FLAG_MSI; 574 sc->ale_irq_spec = ale_irq_spec_msi; 575 } else 576 pci_release_msi(dev); 577 } 578 } 579 580 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 581 if (error != 0) { 582 device_printf(dev, "cannot allocate IRQ resources.\n"); 583 goto fail; 584 } 585 586 /* Get DMA parameters from PCIe device control register. */ 587 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 588 sc->ale_flags |= ALE_FLAG_PCIE; 589 burst = pci_read_config(dev, i + 0x08, 2); 590 /* Max read request size. */ 591 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 592 DMA_CFG_RD_BURST_SHIFT; 593 /* Max payload size. */ 594 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 595 DMA_CFG_WR_BURST_SHIFT; 596 if (bootverbose) { 597 device_printf(dev, "Read request size : %d bytes.\n", 598 128 << ((burst >> 12) & 0x07)); 599 device_printf(dev, "TLP payload size : %d bytes.\n", 600 128 << ((burst >> 5) & 0x07)); 601 } 602 } else { 603 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 604 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 605 } 606 607 /* Create device sysctl node. */ 608 ale_sysctl_node(sc); 609 610 if ((error = ale_dma_alloc(sc)) != 0) 611 goto fail; 612 613 /* Load station address. */ 614 ale_get_macaddr(sc); 615 616 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 617 if (ifp == NULL) { 618 device_printf(dev, "cannot allocate ifnet structure.\n"); 619 error = ENXIO; 620 goto fail; 621 } 622 623 ifp->if_softc = sc; 624 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 625 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 626 ifp->if_ioctl = ale_ioctl; 627 ifp->if_start = ale_start; 628 ifp->if_init = ale_init; 629 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 630 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 631 IFQ_SET_READY(&ifp->if_snd); 632 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 633 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 634 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 635 sc->ale_flags |= ALE_FLAG_PMCAP; 636 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 637 } 638 ifp->if_capenable = ifp->if_capabilities; 639 640 /* Set up MII bus. */ 641 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 642 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 643 MIIF_DOPAUSE); 644 if (error != 0) { 645 device_printf(dev, "attaching PHYs failed\n"); 646 goto fail; 647 } 648 649 ether_ifattach(ifp, sc->ale_eaddr); 650 651 /* VLAN capability setup. */ 652 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 653 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 654 ifp->if_capenable = ifp->if_capabilities; 655 /* 656 * Even though controllers supported by ale(3) have Rx checksum 657 * offload bug the workaround for fragmented frames seemed to 658 * work so far. However it seems Rx checksum offload does not 659 * work under certain conditions. So disable Rx checksum offload 660 * until I find more clue about it but allow users to override it. 661 */ 662 ifp->if_capenable &= ~IFCAP_RXCSUM; 663 664 /* Tell the upper layer(s) we support long frames. */ 665 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 666 667 /* Create local taskq. */ 668 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 669 taskqueue_thread_enqueue, &sc->ale_tq); 670 if (sc->ale_tq == NULL) { 671 device_printf(dev, "could not create taskqueue.\n"); 672 ether_ifdetach(ifp); 673 error = ENXIO; 674 goto fail; 675 } 676 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 677 device_get_nameunit(sc->ale_dev)); 678 679 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 680 msic = ALE_MSIX_MESSAGES; 681 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 682 msic = ALE_MSI_MESSAGES; 683 else 684 msic = 1; 685 for (i = 0; i < msic; i++) { 686 error = bus_setup_intr(dev, sc->ale_irq[i], 687 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 688 &sc->ale_intrhand[i]); 689 if (error != 0) 690 break; 691 } 692 if (error != 0) { 693 device_printf(dev, "could not set up interrupt handler.\n"); 694 taskqueue_free(sc->ale_tq); 695 sc->ale_tq = NULL; 696 ether_ifdetach(ifp); 697 goto fail; 698 } 699 700fail: 701 if (error != 0) 702 ale_detach(dev); 703 704 return (error); 705} 706 707static int 708ale_detach(device_t dev) 709{ 710 struct ale_softc *sc; 711 struct ifnet *ifp; 712 int i, msic; 713 714 sc = device_get_softc(dev); 715 716 ifp = sc->ale_ifp; 717 if (device_is_attached(dev)) { 718 ether_ifdetach(ifp); 719 ALE_LOCK(sc); 720 ale_stop(sc); 721 ALE_UNLOCK(sc); 722 callout_drain(&sc->ale_tick_ch); 723 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 724 } 725 726 if (sc->ale_tq != NULL) { 727 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 728 taskqueue_free(sc->ale_tq); 729 sc->ale_tq = NULL; 730 } 731 732 if (sc->ale_miibus != NULL) { 733 device_delete_child(dev, sc->ale_miibus); 734 sc->ale_miibus = NULL; 735 } 736 bus_generic_detach(dev); 737 ale_dma_free(sc); 738 739 if (ifp != NULL) { 740 if_free(ifp); 741 sc->ale_ifp = NULL; 742 } 743 744 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 745 msic = ALE_MSIX_MESSAGES; 746 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 747 msic = ALE_MSI_MESSAGES; 748 else 749 msic = 1; 750 for (i = 0; i < msic; i++) { 751 if (sc->ale_intrhand[i] != NULL) { 752 bus_teardown_intr(dev, sc->ale_irq[i], 753 sc->ale_intrhand[i]); 754 sc->ale_intrhand[i] = NULL; 755 } 756 } 757 758 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 759 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 760 pci_release_msi(dev); 761 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 762 mtx_destroy(&sc->ale_mtx); 763 764 return (0); 765} 766 767#define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 768 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 769 770#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 771 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 772 773static void 774ale_sysctl_node(struct ale_softc *sc) 775{ 776 struct sysctl_ctx_list *ctx; 777 struct sysctl_oid_list *child, *parent; 778 struct sysctl_oid *tree; 779 struct ale_hw_stats *stats; 780 int error; 781 782 stats = &sc->ale_stats; 783 ctx = device_get_sysctl_ctx(sc->ale_dev); 784 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 785 786 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 787 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_rx_mod, 788 0, sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 789 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 790 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_tx_mod, 791 0, sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 792 /* Pull in device tunables. */ 793 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 794 error = resource_int_value(device_get_name(sc->ale_dev), 795 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 796 if (error == 0) { 797 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 798 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 799 device_printf(sc->ale_dev, "int_rx_mod value out of " 800 "range; using default: %d\n", 801 ALE_IM_RX_TIMER_DEFAULT); 802 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 803 } 804 } 805 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 806 error = resource_int_value(device_get_name(sc->ale_dev), 807 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 808 if (error == 0) { 809 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 810 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 811 device_printf(sc->ale_dev, "int_tx_mod value out of " 812 "range; using default: %d\n", 813 ALE_IM_TX_TIMER_DEFAULT); 814 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 815 } 816 } 817 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 818 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 819 &sc->ale_process_limit, 0, sysctl_hw_ale_proc_limit, "I", 820 "max number of Rx events to process"); 821 /* Pull in device tunables. */ 822 sc->ale_process_limit = ALE_PROC_DEFAULT; 823 error = resource_int_value(device_get_name(sc->ale_dev), 824 device_get_unit(sc->ale_dev), "process_limit", 825 &sc->ale_process_limit); 826 if (error == 0) { 827 if (sc->ale_process_limit < ALE_PROC_MIN || 828 sc->ale_process_limit > ALE_PROC_MAX) { 829 device_printf(sc->ale_dev, 830 "process_limit value out of range; " 831 "using default: %d\n", ALE_PROC_DEFAULT); 832 sc->ale_process_limit = ALE_PROC_DEFAULT; 833 } 834 } 835 836 /* Misc statistics. */ 837 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 838 &stats->reset_brk_seq, 839 "Controller resets due to broken Rx sequnce number"); 840 841 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 842 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ATE statistics"); 843 parent = SYSCTL_CHILDREN(tree); 844 845 /* Rx statistics. */ 846 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 847 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 848 child = SYSCTL_CHILDREN(tree); 849 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 850 &stats->rx_frames, "Good frames"); 851 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 852 &stats->rx_bcast_frames, "Good broadcast frames"); 853 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 854 &stats->rx_mcast_frames, "Good multicast frames"); 855 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 856 &stats->rx_pause_frames, "Pause control frames"); 857 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 858 &stats->rx_control_frames, "Control frames"); 859 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 860 &stats->rx_crcerrs, "CRC errors"); 861 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 862 &stats->rx_lenerrs, "Frames with length mismatched"); 863 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 864 &stats->rx_bytes, "Good octets"); 865 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 866 &stats->rx_bcast_bytes, "Good broadcast octets"); 867 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 868 &stats->rx_mcast_bytes, "Good multicast octets"); 869 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 870 &stats->rx_runts, "Too short frames"); 871 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 872 &stats->rx_fragments, "Fragmented frames"); 873 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 874 &stats->rx_pkts_64, "64 bytes frames"); 875 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 876 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 877 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 878 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 879 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 880 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 881 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 882 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 883 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 884 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 885 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 886 &stats->rx_pkts_1519_max, "1519 to max frames"); 887 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 888 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 889 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 890 &stats->rx_fifo_oflows, "FIFO overflows"); 891 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 892 &stats->rx_rrs_errs, "Return status write-back errors"); 893 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 894 &stats->rx_alignerrs, "Alignment errors"); 895 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 896 &stats->rx_pkts_filtered, 897 "Frames dropped due to address filtering"); 898 899 /* Tx statistics. */ 900 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 901 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 902 child = SYSCTL_CHILDREN(tree); 903 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 904 &stats->tx_frames, "Good frames"); 905 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 906 &stats->tx_bcast_frames, "Good broadcast frames"); 907 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 908 &stats->tx_mcast_frames, "Good multicast frames"); 909 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 910 &stats->tx_pause_frames, "Pause control frames"); 911 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 912 &stats->tx_control_frames, "Control frames"); 913 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 914 &stats->tx_excess_defer, "Frames with excessive derferrals"); 915 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 916 &stats->tx_excess_defer, "Frames with derferrals"); 917 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 918 &stats->tx_bytes, "Good octets"); 919 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 920 &stats->tx_bcast_bytes, "Good broadcast octets"); 921 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 922 &stats->tx_mcast_bytes, "Good multicast octets"); 923 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 924 &stats->tx_pkts_64, "64 bytes frames"); 925 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 926 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 927 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 928 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 929 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 930 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 931 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 932 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 933 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 934 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 935 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 936 &stats->tx_pkts_1519_max, "1519 to max frames"); 937 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 938 &stats->tx_single_colls, "Single collisions"); 939 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 940 &stats->tx_multi_colls, "Multiple collisions"); 941 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 942 &stats->tx_late_colls, "Late collisions"); 943 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 944 &stats->tx_excess_colls, "Excessive collisions"); 945 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 946 &stats->tx_underrun, "FIFO underruns"); 947 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 948 &stats->tx_desc_underrun, "Descriptor write-back errors"); 949 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 950 &stats->tx_lenerrs, "Frames with length mismatched"); 951 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 952 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 953} 954 955#undef ALE_SYSCTL_STAT_ADD32 956#undef ALE_SYSCTL_STAT_ADD64 957 958struct ale_dmamap_arg { 959 bus_addr_t ale_busaddr; 960}; 961 962static void 963ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 964{ 965 struct ale_dmamap_arg *ctx; 966 967 if (error != 0) 968 return; 969 970 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 971 972 ctx = (struct ale_dmamap_arg *)arg; 973 ctx->ale_busaddr = segs[0].ds_addr; 974} 975 976/* 977 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 978 * which specifies high address region of DMA blocks. Therefore these 979 * blocks should have the same high address of given 4GB address 980 * space(i.e. crossing 4GB boundary is not allowed). 981 */ 982static int 983ale_check_boundary(struct ale_softc *sc) 984{ 985 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 986 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 987 988 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 989 sc->ale_pagesize; 990 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 991 sc->ale_pagesize; 992 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 993 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 994 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 995 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 996 997 if ((ALE_ADDR_HI(tx_ring_end) != 998 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 999 (ALE_ADDR_HI(rx_page_end[0]) != 1000 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 1001 (ALE_ADDR_HI(rx_page_end[1]) != 1002 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 1003 (ALE_ADDR_HI(tx_cmb_end) != 1004 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 1005 (ALE_ADDR_HI(rx_cmb_end[0]) != 1006 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 1007 (ALE_ADDR_HI(rx_cmb_end[1]) != 1008 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 1009 return (EFBIG); 1010 1011 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 1012 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 1013 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 1014 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 1015 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 1016 return (EFBIG); 1017 1018 return (0); 1019} 1020 1021static int 1022ale_dma_alloc(struct ale_softc *sc) 1023{ 1024 struct ale_txdesc *txd; 1025 bus_addr_t lowaddr; 1026 struct ale_dmamap_arg ctx; 1027 int error, guard_size, i; 1028 1029 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1030 guard_size = ALE_JUMBO_FRAMELEN; 1031 else 1032 guard_size = ALE_MAX_FRAMELEN; 1033 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1034 ALE_RX_PAGE_ALIGN); 1035 lowaddr = BUS_SPACE_MAXADDR; 1036again: 1037 /* Create parent DMA tag. */ 1038 error = bus_dma_tag_create( 1039 bus_get_dma_tag(sc->ale_dev), /* parent */ 1040 1, 0, /* alignment, boundary */ 1041 lowaddr, /* lowaddr */ 1042 BUS_SPACE_MAXADDR, /* highaddr */ 1043 NULL, NULL, /* filter, filterarg */ 1044 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1045 0, /* nsegments */ 1046 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1047 0, /* flags */ 1048 NULL, NULL, /* lockfunc, lockarg */ 1049 &sc->ale_cdata.ale_parent_tag); 1050 if (error != 0) { 1051 device_printf(sc->ale_dev, 1052 "could not create parent DMA tag.\n"); 1053 goto fail; 1054 } 1055 1056 /* Create DMA tag for Tx descriptor ring. */ 1057 error = bus_dma_tag_create( 1058 sc->ale_cdata.ale_parent_tag, /* parent */ 1059 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1060 BUS_SPACE_MAXADDR, /* lowaddr */ 1061 BUS_SPACE_MAXADDR, /* highaddr */ 1062 NULL, NULL, /* filter, filterarg */ 1063 ALE_TX_RING_SZ, /* maxsize */ 1064 1, /* nsegments */ 1065 ALE_TX_RING_SZ, /* maxsegsize */ 1066 0, /* flags */ 1067 NULL, NULL, /* lockfunc, lockarg */ 1068 &sc->ale_cdata.ale_tx_ring_tag); 1069 if (error != 0) { 1070 device_printf(sc->ale_dev, 1071 "could not create Tx ring DMA tag.\n"); 1072 goto fail; 1073 } 1074 1075 /* Create DMA tag for Rx pages. */ 1076 for (i = 0; i < ALE_RX_PAGES; i++) { 1077 error = bus_dma_tag_create( 1078 sc->ale_cdata.ale_parent_tag, /* parent */ 1079 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1080 BUS_SPACE_MAXADDR, /* lowaddr */ 1081 BUS_SPACE_MAXADDR, /* highaddr */ 1082 NULL, NULL, /* filter, filterarg */ 1083 sc->ale_pagesize, /* maxsize */ 1084 1, /* nsegments */ 1085 sc->ale_pagesize, /* maxsegsize */ 1086 0, /* flags */ 1087 NULL, NULL, /* lockfunc, lockarg */ 1088 &sc->ale_cdata.ale_rx_page[i].page_tag); 1089 if (error != 0) { 1090 device_printf(sc->ale_dev, 1091 "could not create Rx page %d DMA tag.\n", i); 1092 goto fail; 1093 } 1094 } 1095 1096 /* Create DMA tag for Tx coalescing message block. */ 1097 error = bus_dma_tag_create( 1098 sc->ale_cdata.ale_parent_tag, /* parent */ 1099 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1100 BUS_SPACE_MAXADDR, /* lowaddr */ 1101 BUS_SPACE_MAXADDR, /* highaddr */ 1102 NULL, NULL, /* filter, filterarg */ 1103 ALE_TX_CMB_SZ, /* maxsize */ 1104 1, /* nsegments */ 1105 ALE_TX_CMB_SZ, /* maxsegsize */ 1106 0, /* flags */ 1107 NULL, NULL, /* lockfunc, lockarg */ 1108 &sc->ale_cdata.ale_tx_cmb_tag); 1109 if (error != 0) { 1110 device_printf(sc->ale_dev, 1111 "could not create Tx CMB DMA tag.\n"); 1112 goto fail; 1113 } 1114 1115 /* Create DMA tag for Rx coalescing message block. */ 1116 for (i = 0; i < ALE_RX_PAGES; i++) { 1117 error = bus_dma_tag_create( 1118 sc->ale_cdata.ale_parent_tag, /* parent */ 1119 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1120 BUS_SPACE_MAXADDR, /* lowaddr */ 1121 BUS_SPACE_MAXADDR, /* highaddr */ 1122 NULL, NULL, /* filter, filterarg */ 1123 ALE_RX_CMB_SZ, /* maxsize */ 1124 1, /* nsegments */ 1125 ALE_RX_CMB_SZ, /* maxsegsize */ 1126 0, /* flags */ 1127 NULL, NULL, /* lockfunc, lockarg */ 1128 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1129 if (error != 0) { 1130 device_printf(sc->ale_dev, 1131 "could not create Rx page %d CMB DMA tag.\n", i); 1132 goto fail; 1133 } 1134 } 1135 1136 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1137 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1138 (void **)&sc->ale_cdata.ale_tx_ring, 1139 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1140 &sc->ale_cdata.ale_tx_ring_map); 1141 if (error != 0) { 1142 device_printf(sc->ale_dev, 1143 "could not allocate DMA'able memory for Tx ring.\n"); 1144 goto fail; 1145 } 1146 ctx.ale_busaddr = 0; 1147 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1148 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1149 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1150 if (error != 0 || ctx.ale_busaddr == 0) { 1151 device_printf(sc->ale_dev, 1152 "could not load DMA'able memory for Tx ring.\n"); 1153 goto fail; 1154 } 1155 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1156 1157 /* Rx pages. */ 1158 for (i = 0; i < ALE_RX_PAGES; i++) { 1159 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1160 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1161 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1162 &sc->ale_cdata.ale_rx_page[i].page_map); 1163 if (error != 0) { 1164 device_printf(sc->ale_dev, 1165 "could not allocate DMA'able memory for " 1166 "Rx page %d.\n", i); 1167 goto fail; 1168 } 1169 ctx.ale_busaddr = 0; 1170 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1171 sc->ale_cdata.ale_rx_page[i].page_map, 1172 sc->ale_cdata.ale_rx_page[i].page_addr, 1173 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1174 if (error != 0 || ctx.ale_busaddr == 0) { 1175 device_printf(sc->ale_dev, 1176 "could not load DMA'able memory for " 1177 "Rx page %d.\n", i); 1178 goto fail; 1179 } 1180 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1181 } 1182 1183 /* Tx CMB. */ 1184 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1185 (void **)&sc->ale_cdata.ale_tx_cmb, 1186 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1187 &sc->ale_cdata.ale_tx_cmb_map); 1188 if (error != 0) { 1189 device_printf(sc->ale_dev, 1190 "could not allocate DMA'able memory for Tx CMB.\n"); 1191 goto fail; 1192 } 1193 ctx.ale_busaddr = 0; 1194 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1195 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1196 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1197 if (error != 0 || ctx.ale_busaddr == 0) { 1198 device_printf(sc->ale_dev, 1199 "could not load DMA'able memory for Tx CMB.\n"); 1200 goto fail; 1201 } 1202 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1203 1204 /* Rx CMB. */ 1205 for (i = 0; i < ALE_RX_PAGES; i++) { 1206 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1207 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1208 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1209 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1210 if (error != 0) { 1211 device_printf(sc->ale_dev, "could not allocate " 1212 "DMA'able memory for Rx page %d CMB.\n", i); 1213 goto fail; 1214 } 1215 ctx.ale_busaddr = 0; 1216 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1217 sc->ale_cdata.ale_rx_page[i].cmb_map, 1218 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1219 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1220 if (error != 0 || ctx.ale_busaddr == 0) { 1221 device_printf(sc->ale_dev, "could not load DMA'able " 1222 "memory for Rx page %d CMB.\n", i); 1223 goto fail; 1224 } 1225 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1226 } 1227 1228 /* 1229 * Tx descriptors/RXF0/CMB DMA blocks share the same 1230 * high address region of 64bit DMA address space. 1231 */ 1232 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1233 (error = ale_check_boundary(sc)) != 0) { 1234 device_printf(sc->ale_dev, "4GB boundary crossed, " 1235 "switching to 32bit DMA addressing mode.\n"); 1236 ale_dma_free(sc); 1237 /* 1238 * Limit max allowable DMA address space to 32bit 1239 * and try again. 1240 */ 1241 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1242 goto again; 1243 } 1244 1245 /* 1246 * Create Tx buffer parent tag. 1247 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1248 * needs separate parent DMA tag as parent DMA address space 1249 * could be restricted to be within 32bit address space by 1250 * 4GB boundary crossing. 1251 */ 1252 error = bus_dma_tag_create( 1253 bus_get_dma_tag(sc->ale_dev), /* parent */ 1254 1, 0, /* alignment, boundary */ 1255 BUS_SPACE_MAXADDR, /* lowaddr */ 1256 BUS_SPACE_MAXADDR, /* highaddr */ 1257 NULL, NULL, /* filter, filterarg */ 1258 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1259 0, /* nsegments */ 1260 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1261 0, /* flags */ 1262 NULL, NULL, /* lockfunc, lockarg */ 1263 &sc->ale_cdata.ale_buffer_tag); 1264 if (error != 0) { 1265 device_printf(sc->ale_dev, 1266 "could not create parent buffer DMA tag.\n"); 1267 goto fail; 1268 } 1269 1270 /* Create DMA tag for Tx buffers. */ 1271 error = bus_dma_tag_create( 1272 sc->ale_cdata.ale_buffer_tag, /* parent */ 1273 1, 0, /* alignment, boundary */ 1274 BUS_SPACE_MAXADDR, /* lowaddr */ 1275 BUS_SPACE_MAXADDR, /* highaddr */ 1276 NULL, NULL, /* filter, filterarg */ 1277 ALE_TSO_MAXSIZE, /* maxsize */ 1278 ALE_MAXTXSEGS, /* nsegments */ 1279 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1280 0, /* flags */ 1281 NULL, NULL, /* lockfunc, lockarg */ 1282 &sc->ale_cdata.ale_tx_tag); 1283 if (error != 0) { 1284 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1285 goto fail; 1286 } 1287 1288 /* Create DMA maps for Tx buffers. */ 1289 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1290 txd = &sc->ale_cdata.ale_txdesc[i]; 1291 txd->tx_m = NULL; 1292 txd->tx_dmamap = NULL; 1293 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1294 &txd->tx_dmamap); 1295 if (error != 0) { 1296 device_printf(sc->ale_dev, 1297 "could not create Tx dmamap.\n"); 1298 goto fail; 1299 } 1300 } 1301 1302fail: 1303 return (error); 1304} 1305 1306static void 1307ale_dma_free(struct ale_softc *sc) 1308{ 1309 struct ale_txdesc *txd; 1310 int i; 1311 1312 /* Tx buffers. */ 1313 if (sc->ale_cdata.ale_tx_tag != NULL) { 1314 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1315 txd = &sc->ale_cdata.ale_txdesc[i]; 1316 if (txd->tx_dmamap != NULL) { 1317 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1318 txd->tx_dmamap); 1319 txd->tx_dmamap = NULL; 1320 } 1321 } 1322 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1323 sc->ale_cdata.ale_tx_tag = NULL; 1324 } 1325 /* Tx descriptor ring. */ 1326 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1327 if (sc->ale_cdata.ale_tx_ring_paddr != 0) 1328 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1329 sc->ale_cdata.ale_tx_ring_map); 1330 if (sc->ale_cdata.ale_tx_ring != NULL) 1331 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1332 sc->ale_cdata.ale_tx_ring, 1333 sc->ale_cdata.ale_tx_ring_map); 1334 sc->ale_cdata.ale_tx_ring_paddr = 0; 1335 sc->ale_cdata.ale_tx_ring = NULL; 1336 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1337 sc->ale_cdata.ale_tx_ring_tag = NULL; 1338 } 1339 /* Rx page block. */ 1340 for (i = 0; i < ALE_RX_PAGES; i++) { 1341 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1342 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0) 1343 bus_dmamap_unload( 1344 sc->ale_cdata.ale_rx_page[i].page_tag, 1345 sc->ale_cdata.ale_rx_page[i].page_map); 1346 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1347 bus_dmamem_free( 1348 sc->ale_cdata.ale_rx_page[i].page_tag, 1349 sc->ale_cdata.ale_rx_page[i].page_addr, 1350 sc->ale_cdata.ale_rx_page[i].page_map); 1351 sc->ale_cdata.ale_rx_page[i].page_paddr = 0; 1352 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1353 bus_dma_tag_destroy( 1354 sc->ale_cdata.ale_rx_page[i].page_tag); 1355 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1356 } 1357 } 1358 /* Rx CMB. */ 1359 for (i = 0; i < ALE_RX_PAGES; i++) { 1360 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1361 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0) 1362 bus_dmamap_unload( 1363 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1364 sc->ale_cdata.ale_rx_page[i].cmb_map); 1365 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1366 bus_dmamem_free( 1367 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1368 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1369 sc->ale_cdata.ale_rx_page[i].cmb_map); 1370 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0; 1371 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1372 bus_dma_tag_destroy( 1373 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1374 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1375 } 1376 } 1377 /* Tx CMB. */ 1378 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1379 if (sc->ale_cdata.ale_tx_cmb_paddr != 0) 1380 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1381 sc->ale_cdata.ale_tx_cmb_map); 1382 if (sc->ale_cdata.ale_tx_cmb != NULL) 1383 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1384 sc->ale_cdata.ale_tx_cmb, 1385 sc->ale_cdata.ale_tx_cmb_map); 1386 sc->ale_cdata.ale_tx_cmb_paddr = 0; 1387 sc->ale_cdata.ale_tx_cmb = NULL; 1388 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1389 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1390 } 1391 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1392 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1393 sc->ale_cdata.ale_buffer_tag = NULL; 1394 } 1395 if (sc->ale_cdata.ale_parent_tag != NULL) { 1396 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1397 sc->ale_cdata.ale_parent_tag = NULL; 1398 } 1399} 1400 1401static int 1402ale_shutdown(device_t dev) 1403{ 1404 1405 return (ale_suspend(dev)); 1406} 1407 1408/* 1409 * Note, this driver resets the link speed to 10/100Mbps by 1410 * restarting auto-negotiation in suspend/shutdown phase but we 1411 * don't know whether that auto-negotiation would succeed or not 1412 * as driver has no control after powering off/suspend operation. 1413 * If the renegotiation fail WOL may not work. Running at 1Gbps 1414 * will draw more power than 375mA at 3.3V which is specified in 1415 * PCI specification and that would result in complete 1416 * shutdowning power to ethernet controller. 1417 * 1418 * TODO 1419 * Save current negotiated media speed/duplex/flow-control to 1420 * softc and restore the same link again after resuming. PHY 1421 * handling such as power down/resetting to 100Mbps may be better 1422 * handled in suspend method in phy driver. 1423 */ 1424static void 1425ale_setlinkspeed(struct ale_softc *sc) 1426{ 1427 struct mii_data *mii; 1428 int aneg, i; 1429 1430 mii = device_get_softc(sc->ale_miibus); 1431 mii_pollstat(mii); 1432 aneg = 0; 1433 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1434 (IFM_ACTIVE | IFM_AVALID)) { 1435 switch IFM_SUBTYPE(mii->mii_media_active) { 1436 case IFM_10_T: 1437 case IFM_100_TX: 1438 return; 1439 case IFM_1000_T: 1440 aneg++; 1441 break; 1442 default: 1443 break; 1444 } 1445 } 1446 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1447 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1448 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1449 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1450 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1451 DELAY(1000); 1452 if (aneg != 0) { 1453 /* 1454 * Poll link state until ale(4) get a 10/100Mbps link. 1455 */ 1456 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1457 mii_pollstat(mii); 1458 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1459 == (IFM_ACTIVE | IFM_AVALID)) { 1460 switch (IFM_SUBTYPE( 1461 mii->mii_media_active)) { 1462 case IFM_10_T: 1463 case IFM_100_TX: 1464 ale_mac_config(sc); 1465 return; 1466 default: 1467 break; 1468 } 1469 } 1470 ALE_UNLOCK(sc); 1471 pause("alelnk", hz); 1472 ALE_LOCK(sc); 1473 } 1474 if (i == MII_ANEGTICKS_GIGE) 1475 device_printf(sc->ale_dev, 1476 "establishing a link failed, WOL may not work!"); 1477 } 1478 /* 1479 * No link, force MAC to have 100Mbps, full-duplex link. 1480 * This is the last resort and may/may not work. 1481 */ 1482 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1483 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1484 ale_mac_config(sc); 1485} 1486 1487static void 1488ale_setwol(struct ale_softc *sc) 1489{ 1490 struct ifnet *ifp; 1491 uint32_t reg, pmcs; 1492 uint16_t pmstat; 1493 int pmc; 1494 1495 ALE_LOCK_ASSERT(sc); 1496 1497 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1498 /* Disable WOL. */ 1499 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1500 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1501 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1502 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1503 /* Force PHY power down. */ 1504 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1505 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1506 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1507 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1508 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1509 return; 1510 } 1511 1512 ifp = sc->ale_ifp; 1513 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1514 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1515 ale_setlinkspeed(sc); 1516 } 1517 1518 pmcs = 0; 1519 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1520 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1521 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1522 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1523 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1524 MAC_CFG_BCAST); 1525 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1526 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1527 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1528 reg |= MAC_CFG_RX_ENB; 1529 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1530 1531 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1532 /* WOL disabled, PHY power down. */ 1533 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1534 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1535 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1536 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1537 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1538 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1539 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1540 GPHY_CTRL_PWDOWN_HW); 1541 } 1542 /* Request PME. */ 1543 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1544 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1545 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1546 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1547 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1548} 1549 1550static int 1551ale_suspend(device_t dev) 1552{ 1553 struct ale_softc *sc; 1554 1555 sc = device_get_softc(dev); 1556 1557 ALE_LOCK(sc); 1558 ale_stop(sc); 1559 ale_setwol(sc); 1560 ALE_UNLOCK(sc); 1561 1562 return (0); 1563} 1564 1565static int 1566ale_resume(device_t dev) 1567{ 1568 struct ale_softc *sc; 1569 struct ifnet *ifp; 1570 int pmc; 1571 uint16_t pmstat; 1572 1573 sc = device_get_softc(dev); 1574 1575 ALE_LOCK(sc); 1576 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1577 /* Disable PME and clear PME status. */ 1578 pmstat = pci_read_config(sc->ale_dev, 1579 pmc + PCIR_POWER_STATUS, 2); 1580 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1581 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1582 pci_write_config(sc->ale_dev, 1583 pmc + PCIR_POWER_STATUS, pmstat, 2); 1584 } 1585 } 1586 /* Reset PHY. */ 1587 ale_phy_reset(sc); 1588 ifp = sc->ale_ifp; 1589 if ((ifp->if_flags & IFF_UP) != 0) { 1590 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1591 ale_init_locked(sc); 1592 } 1593 ALE_UNLOCK(sc); 1594 1595 return (0); 1596} 1597 1598static int 1599ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1600{ 1601 struct ale_txdesc *txd, *txd_last; 1602 struct tx_desc *desc; 1603 struct mbuf *m; 1604 struct ip *ip; 1605 struct tcphdr *tcp; 1606 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1607 bus_dmamap_t map; 1608 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1609 int error, i, nsegs, prod, si; 1610 1611 ALE_LOCK_ASSERT(sc); 1612 1613 M_ASSERTPKTHDR((*m_head)); 1614 1615 m = *m_head; 1616 ip = NULL; 1617 tcp = NULL; 1618 cflags = vtag = 0; 1619 ip_off = poff = 0; 1620 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1621 /* 1622 * AR81xx requires offset of TCP/UDP payload in its Tx 1623 * descriptor to perform hardware Tx checksum offload. 1624 * Additionally, TSO requires IP/TCP header size and 1625 * modification of IP/TCP header in order to make TSO 1626 * engine work. This kind of operation takes many CPU 1627 * cycles on FreeBSD so fast host CPU is required to 1628 * get smooth TSO performance. 1629 */ 1630 struct ether_header *eh; 1631 1632 if (M_WRITABLE(m) == 0) { 1633 /* Get a writable copy. */ 1634 m = m_dup(*m_head, M_NOWAIT); 1635 /* Release original mbufs. */ 1636 m_freem(*m_head); 1637 if (m == NULL) { 1638 *m_head = NULL; 1639 return (ENOBUFS); 1640 } 1641 *m_head = m; 1642 } 1643 1644 /* 1645 * Buggy-controller requires 4 byte aligned Tx buffer 1646 * to make custom checksum offload work. 1647 */ 1648 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1649 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1650 (mtod(m, intptr_t) & 3) != 0) { 1651 m = m_defrag(*m_head, M_NOWAIT); 1652 if (m == NULL) { 1653 m_freem(*m_head); 1654 *m_head = NULL; 1655 return (ENOBUFS); 1656 } 1657 *m_head = m; 1658 } 1659 1660 ip_off = sizeof(struct ether_header); 1661 m = m_pullup(m, ip_off); 1662 if (m == NULL) { 1663 *m_head = NULL; 1664 return (ENOBUFS); 1665 } 1666 eh = mtod(m, struct ether_header *); 1667 /* 1668 * Check if hardware VLAN insertion is off. 1669 * Additional check for LLC/SNAP frame? 1670 */ 1671 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1672 ip_off = sizeof(struct ether_vlan_header); 1673 m = m_pullup(m, ip_off); 1674 if (m == NULL) { 1675 *m_head = NULL; 1676 return (ENOBUFS); 1677 } 1678 } 1679 m = m_pullup(m, ip_off + sizeof(struct ip)); 1680 if (m == NULL) { 1681 *m_head = NULL; 1682 return (ENOBUFS); 1683 } 1684 ip = (struct ip *)(mtod(m, char *) + ip_off); 1685 poff = ip_off + (ip->ip_hl << 2); 1686 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1687 /* 1688 * XXX 1689 * AR81xx requires the first descriptor should 1690 * not include any TCP playload for TSO case. 1691 * (i.e. ethernet header + IP + TCP header only) 1692 * m_pullup(9) above will ensure this too. 1693 * However it's not correct if the first mbuf 1694 * of the chain does not use cluster. 1695 */ 1696 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1697 if (m == NULL) { 1698 *m_head = NULL; 1699 return (ENOBUFS); 1700 } 1701 ip = (struct ip *)(mtod(m, char *) + ip_off); 1702 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1703 m = m_pullup(m, poff + (tcp->th_off << 2)); 1704 if (m == NULL) { 1705 *m_head = NULL; 1706 return (ENOBUFS); 1707 } 1708 /* 1709 * AR81xx requires IP/TCP header size and offset as 1710 * well as TCP pseudo checksum which complicates 1711 * TSO configuration. I guess this comes from the 1712 * adherence to Microsoft NDIS Large Send 1713 * specification which requires insertion of 1714 * pseudo checksum by upper stack. The pseudo 1715 * checksum that NDIS refers to doesn't include 1716 * TCP payload length so ale(4) should recompute 1717 * the pseudo checksum here. Hopefully this wouldn't 1718 * be much burden on modern CPUs. 1719 * Reset IP checksum and recompute TCP pseudo 1720 * checksum as NDIS specification said. 1721 */ 1722 ip->ip_sum = 0; 1723 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1724 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1725 } 1726 *m_head = m; 1727 } 1728 1729 si = prod = sc->ale_cdata.ale_tx_prod; 1730 txd = &sc->ale_cdata.ale_txdesc[prod]; 1731 txd_last = txd; 1732 map = txd->tx_dmamap; 1733 1734 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1735 *m_head, txsegs, &nsegs, 0); 1736 if (error == EFBIG) { 1737 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1738 if (m == NULL) { 1739 m_freem(*m_head); 1740 *m_head = NULL; 1741 return (ENOMEM); 1742 } 1743 *m_head = m; 1744 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1745 *m_head, txsegs, &nsegs, 0); 1746 if (error != 0) { 1747 m_freem(*m_head); 1748 *m_head = NULL; 1749 return (error); 1750 } 1751 } else if (error != 0) 1752 return (error); 1753 if (nsegs == 0) { 1754 m_freem(*m_head); 1755 *m_head = NULL; 1756 return (EIO); 1757 } 1758 1759 /* Check descriptor overrun. */ 1760 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1761 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1762 return (ENOBUFS); 1763 } 1764 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1765 1766 m = *m_head; 1767 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1768 /* Request TSO and set MSS. */ 1769 cflags |= ALE_TD_TSO; 1770 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1771 /* Set IP/TCP header size. */ 1772 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1773 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1774 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1775 /* 1776 * AR81xx supports Tx custom checksum offload feature 1777 * that offloads single 16bit checksum computation. 1778 * So you can choose one among IP, TCP and UDP. 1779 * Normally driver sets checksum start/insertion 1780 * position from the information of TCP/UDP frame as 1781 * TCP/UDP checksum takes more time than that of IP. 1782 * However it seems that custom checksum offload 1783 * requires 4 bytes aligned Tx buffers due to hardware 1784 * bug. 1785 * AR81xx also supports explicit Tx checksum computation 1786 * if it is told that the size of IP header and TCP 1787 * header(for UDP, the header size does not matter 1788 * because it's fixed length). However with this scheme 1789 * TSO does not work so you have to choose one either 1790 * TSO or explicit Tx checksum offload. I chosen TSO 1791 * plus custom checksum offload with work-around which 1792 * will cover most common usage for this consumer 1793 * ethernet controller. The work-around takes a lot of 1794 * CPU cycles if Tx buffer is not aligned on 4 bytes 1795 * boundary, though. 1796 */ 1797 cflags |= ALE_TD_CXSUM; 1798 /* Set checksum start offset. */ 1799 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1800 /* Set checksum insertion position of TCP/UDP. */ 1801 cflags |= ((poff + m->m_pkthdr.csum_data) << 1802 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1803 } 1804 1805 /* Configure VLAN hardware tag insertion. */ 1806 if ((m->m_flags & M_VLANTAG) != 0) { 1807 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1808 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1809 cflags |= ALE_TD_INSERT_VLAN_TAG; 1810 } 1811 1812 i = 0; 1813 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1814 /* 1815 * Make sure the first fragment contains 1816 * only ethernet and IP/TCP header with options. 1817 */ 1818 hdrlen = poff + (tcp->th_off << 2); 1819 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1820 desc->addr = htole64(txsegs[i].ds_addr); 1821 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1822 desc->flags = htole32(cflags); 1823 sc->ale_cdata.ale_tx_cnt++; 1824 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1825 if (m->m_len - hdrlen > 0) { 1826 /* Handle remaining payload of the first fragment. */ 1827 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1828 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1829 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1830 vtag); 1831 desc->flags = htole32(cflags); 1832 sc->ale_cdata.ale_tx_cnt++; 1833 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1834 } 1835 i = 1; 1836 } 1837 for (; i < nsegs; i++) { 1838 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1839 desc->addr = htole64(txsegs[i].ds_addr); 1840 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1841 desc->flags = htole32(cflags); 1842 sc->ale_cdata.ale_tx_cnt++; 1843 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1844 } 1845 /* Update producer index. */ 1846 sc->ale_cdata.ale_tx_prod = prod; 1847 /* Set TSO header on the first descriptor. */ 1848 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1849 desc = &sc->ale_cdata.ale_tx_ring[si]; 1850 desc->flags |= htole32(ALE_TD_TSO_HDR); 1851 } 1852 1853 /* Finally set EOP on the last descriptor. */ 1854 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1855 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1856 desc->flags |= htole32(ALE_TD_EOP); 1857 1858 /* Swap dmamap of the first and the last. */ 1859 txd = &sc->ale_cdata.ale_txdesc[prod]; 1860 map = txd_last->tx_dmamap; 1861 txd_last->tx_dmamap = txd->tx_dmamap; 1862 txd->tx_dmamap = map; 1863 txd->tx_m = m; 1864 1865 /* Sync descriptors. */ 1866 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1867 sc->ale_cdata.ale_tx_ring_map, 1868 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1869 1870 return (0); 1871} 1872 1873static void 1874ale_start(struct ifnet *ifp) 1875{ 1876 struct ale_softc *sc; 1877 1878 sc = ifp->if_softc; 1879 ALE_LOCK(sc); 1880 ale_start_locked(ifp); 1881 ALE_UNLOCK(sc); 1882} 1883 1884static void 1885ale_start_locked(struct ifnet *ifp) 1886{ 1887 struct ale_softc *sc; 1888 struct mbuf *m_head; 1889 int enq; 1890 1891 sc = ifp->if_softc; 1892 1893 ALE_LOCK_ASSERT(sc); 1894 1895 /* Reclaim transmitted frames. */ 1896 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1897 ale_txeof(sc); 1898 1899 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1900 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1901 return; 1902 1903 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1904 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1905 if (m_head == NULL) 1906 break; 1907 /* 1908 * Pack the data into the transmit ring. If we 1909 * don't have room, set the OACTIVE flag and wait 1910 * for the NIC to drain the ring. 1911 */ 1912 if (ale_encap(sc, &m_head)) { 1913 if (m_head == NULL) 1914 break; 1915 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1916 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1917 break; 1918 } 1919 1920 enq++; 1921 /* 1922 * If there's a BPF listener, bounce a copy of this frame 1923 * to him. 1924 */ 1925 ETHER_BPF_MTAP(ifp, m_head); 1926 } 1927 1928 if (enq > 0) { 1929 /* Kick. */ 1930 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1931 sc->ale_cdata.ale_tx_prod); 1932 /* Set a timeout in case the chip goes out to lunch. */ 1933 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1934 } 1935} 1936 1937static void 1938ale_watchdog(struct ale_softc *sc) 1939{ 1940 struct ifnet *ifp; 1941 1942 ALE_LOCK_ASSERT(sc); 1943 1944 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1945 return; 1946 1947 ifp = sc->ale_ifp; 1948 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1949 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1950 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1951 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1952 ale_init_locked(sc); 1953 return; 1954 } 1955 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1956 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1957 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1958 ale_init_locked(sc); 1959 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1960 ale_start_locked(ifp); 1961} 1962 1963static int 1964ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1965{ 1966 struct ale_softc *sc; 1967 struct ifreq *ifr; 1968 struct mii_data *mii; 1969 int error, mask; 1970 1971 sc = ifp->if_softc; 1972 ifr = (struct ifreq *)data; 1973 error = 0; 1974 switch (cmd) { 1975 case SIOCSIFMTU: 1976 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1977 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1978 ifr->ifr_mtu > ETHERMTU)) 1979 error = EINVAL; 1980 else if (ifp->if_mtu != ifr->ifr_mtu) { 1981 ALE_LOCK(sc); 1982 ifp->if_mtu = ifr->ifr_mtu; 1983 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1984 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1985 ale_init_locked(sc); 1986 } 1987 ALE_UNLOCK(sc); 1988 } 1989 break; 1990 case SIOCSIFFLAGS: 1991 ALE_LOCK(sc); 1992 if ((ifp->if_flags & IFF_UP) != 0) { 1993 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1994 if (((ifp->if_flags ^ sc->ale_if_flags) 1995 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1996 ale_rxfilter(sc); 1997 } else { 1998 ale_init_locked(sc); 1999 } 2000 } else { 2001 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2002 ale_stop(sc); 2003 } 2004 sc->ale_if_flags = ifp->if_flags; 2005 ALE_UNLOCK(sc); 2006 break; 2007 case SIOCADDMULTI: 2008 case SIOCDELMULTI: 2009 ALE_LOCK(sc); 2010 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2011 ale_rxfilter(sc); 2012 ALE_UNLOCK(sc); 2013 break; 2014 case SIOCSIFMEDIA: 2015 case SIOCGIFMEDIA: 2016 mii = device_get_softc(sc->ale_miibus); 2017 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2018 break; 2019 case SIOCSIFCAP: 2020 ALE_LOCK(sc); 2021 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2022 if ((mask & IFCAP_TXCSUM) != 0 && 2023 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2024 ifp->if_capenable ^= IFCAP_TXCSUM; 2025 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2026 ifp->if_hwassist |= ALE_CSUM_FEATURES; 2027 else 2028 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 2029 } 2030 if ((mask & IFCAP_RXCSUM) != 0 && 2031 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2032 ifp->if_capenable ^= IFCAP_RXCSUM; 2033 if ((mask & IFCAP_TSO4) != 0 && 2034 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2035 ifp->if_capenable ^= IFCAP_TSO4; 2036 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2037 ifp->if_hwassist |= CSUM_TSO; 2038 else 2039 ifp->if_hwassist &= ~CSUM_TSO; 2040 } 2041 2042 if ((mask & IFCAP_WOL_MCAST) != 0 && 2043 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2044 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2045 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2046 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2047 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2048 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2049 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2050 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2051 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2052 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2053 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2054 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2055 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2056 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2057 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2058 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2059 ale_rxvlan(sc); 2060 } 2061 ALE_UNLOCK(sc); 2062 VLAN_CAPABILITIES(ifp); 2063 break; 2064 default: 2065 error = ether_ioctl(ifp, cmd, data); 2066 break; 2067 } 2068 2069 return (error); 2070} 2071 2072static void 2073ale_mac_config(struct ale_softc *sc) 2074{ 2075 struct mii_data *mii; 2076 uint32_t reg; 2077 2078 ALE_LOCK_ASSERT(sc); 2079 2080 mii = device_get_softc(sc->ale_miibus); 2081 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2082 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2083 MAC_CFG_SPEED_MASK); 2084 /* Reprogram MAC with resolved speed/duplex. */ 2085 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2086 case IFM_10_T: 2087 case IFM_100_TX: 2088 reg |= MAC_CFG_SPEED_10_100; 2089 break; 2090 case IFM_1000_T: 2091 reg |= MAC_CFG_SPEED_1000; 2092 break; 2093 } 2094 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2095 reg |= MAC_CFG_FULL_DUPLEX; 2096 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2097 reg |= MAC_CFG_TX_FC; 2098 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2099 reg |= MAC_CFG_RX_FC; 2100 } 2101 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2102} 2103 2104static void 2105ale_stats_clear(struct ale_softc *sc) 2106{ 2107 struct smb sb; 2108 uint32_t *reg; 2109 int i; 2110 2111 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2112 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2113 i += sizeof(uint32_t); 2114 } 2115 /* Read Tx statistics. */ 2116 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2117 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2118 i += sizeof(uint32_t); 2119 } 2120} 2121 2122static void 2123ale_stats_update(struct ale_softc *sc) 2124{ 2125 struct ale_hw_stats *stat; 2126 struct smb sb, *smb; 2127 struct ifnet *ifp; 2128 uint32_t *reg; 2129 int i; 2130 2131 ALE_LOCK_ASSERT(sc); 2132 2133 ifp = sc->ale_ifp; 2134 stat = &sc->ale_stats; 2135 smb = &sb; 2136 2137 /* Read Rx statistics. */ 2138 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2139 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2140 i += sizeof(uint32_t); 2141 } 2142 /* Read Tx statistics. */ 2143 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2144 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2145 i += sizeof(uint32_t); 2146 } 2147 2148 /* Rx stats. */ 2149 stat->rx_frames += smb->rx_frames; 2150 stat->rx_bcast_frames += smb->rx_bcast_frames; 2151 stat->rx_mcast_frames += smb->rx_mcast_frames; 2152 stat->rx_pause_frames += smb->rx_pause_frames; 2153 stat->rx_control_frames += smb->rx_control_frames; 2154 stat->rx_crcerrs += smb->rx_crcerrs; 2155 stat->rx_lenerrs += smb->rx_lenerrs; 2156 stat->rx_bytes += smb->rx_bytes; 2157 stat->rx_runts += smb->rx_runts; 2158 stat->rx_fragments += smb->rx_fragments; 2159 stat->rx_pkts_64 += smb->rx_pkts_64; 2160 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2161 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2162 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2163 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2164 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2165 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2166 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2167 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2168 stat->rx_rrs_errs += smb->rx_rrs_errs; 2169 stat->rx_alignerrs += smb->rx_alignerrs; 2170 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2171 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2172 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2173 2174 /* Tx stats. */ 2175 stat->tx_frames += smb->tx_frames; 2176 stat->tx_bcast_frames += smb->tx_bcast_frames; 2177 stat->tx_mcast_frames += smb->tx_mcast_frames; 2178 stat->tx_pause_frames += smb->tx_pause_frames; 2179 stat->tx_excess_defer += smb->tx_excess_defer; 2180 stat->tx_control_frames += smb->tx_control_frames; 2181 stat->tx_deferred += smb->tx_deferred; 2182 stat->tx_bytes += smb->tx_bytes; 2183 stat->tx_pkts_64 += smb->tx_pkts_64; 2184 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2185 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2186 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2187 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2188 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2189 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2190 stat->tx_single_colls += smb->tx_single_colls; 2191 stat->tx_multi_colls += smb->tx_multi_colls; 2192 stat->tx_late_colls += smb->tx_late_colls; 2193 stat->tx_excess_colls += smb->tx_excess_colls; 2194 stat->tx_underrun += smb->tx_underrun; 2195 stat->tx_desc_underrun += smb->tx_desc_underrun; 2196 stat->tx_lenerrs += smb->tx_lenerrs; 2197 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2198 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2199 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2200 2201 /* Update counters in ifnet. */ 2202 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2203 2204 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2205 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2206 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2207 2208 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 2209 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 2210 2211 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2212 2213 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2214 smb->rx_crcerrs + smb->rx_lenerrs + 2215 smb->rx_runts + smb->rx_pkts_truncated + 2216 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2217 smb->rx_alignerrs); 2218} 2219 2220static int 2221ale_intr(void *arg) 2222{ 2223 struct ale_softc *sc; 2224 uint32_t status; 2225 2226 sc = (struct ale_softc *)arg; 2227 2228 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2229 if ((status & ALE_INTRS) == 0) 2230 return (FILTER_STRAY); 2231 /* Disable interrupts. */ 2232 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2233 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2234 2235 return (FILTER_HANDLED); 2236} 2237 2238static void 2239ale_int_task(void *arg, int pending) 2240{ 2241 struct ale_softc *sc; 2242 struct ifnet *ifp; 2243 uint32_t status; 2244 int more; 2245 2246 sc = (struct ale_softc *)arg; 2247 2248 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2249 ALE_LOCK(sc); 2250 if (sc->ale_morework != 0) 2251 status |= INTR_RX_PKT; 2252 if ((status & ALE_INTRS) == 0) 2253 goto done; 2254 2255 /* Acknowledge interrupts but still disable interrupts. */ 2256 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2257 2258 ifp = sc->ale_ifp; 2259 more = 0; 2260 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2261 more = ale_rxeof(sc, sc->ale_process_limit); 2262 if (more == EAGAIN) 2263 sc->ale_morework = 1; 2264 else if (more == EIO) { 2265 sc->ale_stats.reset_brk_seq++; 2266 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2267 ale_init_locked(sc); 2268 ALE_UNLOCK(sc); 2269 return; 2270 } 2271 2272 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2273 if ((status & INTR_DMA_RD_TO_RST) != 0) 2274 device_printf(sc->ale_dev, 2275 "DMA read error! -- resetting\n"); 2276 if ((status & INTR_DMA_WR_TO_RST) != 0) 2277 device_printf(sc->ale_dev, 2278 "DMA write error! -- resetting\n"); 2279 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2280 ale_init_locked(sc); 2281 ALE_UNLOCK(sc); 2282 return; 2283 } 2284 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2285 ale_start_locked(ifp); 2286 } 2287 2288 if (more == EAGAIN || 2289 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2290 ALE_UNLOCK(sc); 2291 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2292 return; 2293 } 2294 2295done: 2296 ALE_UNLOCK(sc); 2297 2298 /* Re-enable interrupts. */ 2299 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2300} 2301 2302static void 2303ale_txeof(struct ale_softc *sc) 2304{ 2305 struct ifnet *ifp; 2306 struct ale_txdesc *txd; 2307 uint32_t cons, prod; 2308 int prog; 2309 2310 ALE_LOCK_ASSERT(sc); 2311 2312 ifp = sc->ale_ifp; 2313 2314 if (sc->ale_cdata.ale_tx_cnt == 0) 2315 return; 2316 2317 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2318 sc->ale_cdata.ale_tx_ring_map, 2319 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2320 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2321 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2322 sc->ale_cdata.ale_tx_cmb_map, 2323 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2324 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2325 } else 2326 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2327 cons = sc->ale_cdata.ale_tx_cons; 2328 /* 2329 * Go through our Tx list and free mbufs for those 2330 * frames which have been transmitted. 2331 */ 2332 for (prog = 0; cons != prod; prog++, 2333 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2334 if (sc->ale_cdata.ale_tx_cnt <= 0) 2335 break; 2336 prog++; 2337 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2338 sc->ale_cdata.ale_tx_cnt--; 2339 txd = &sc->ale_cdata.ale_txdesc[cons]; 2340 if (txd->tx_m != NULL) { 2341 /* Reclaim transmitted mbufs. */ 2342 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2343 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2344 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2345 txd->tx_dmamap); 2346 m_freem(txd->tx_m); 2347 txd->tx_m = NULL; 2348 } 2349 } 2350 2351 if (prog > 0) { 2352 sc->ale_cdata.ale_tx_cons = cons; 2353 /* 2354 * Unarm watchdog timer only when there is no pending 2355 * Tx descriptors in queue. 2356 */ 2357 if (sc->ale_cdata.ale_tx_cnt == 0) 2358 sc->ale_watchdog_timer = 0; 2359 } 2360} 2361 2362static void 2363ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2364 uint32_t length, uint32_t *prod) 2365{ 2366 struct ale_rx_page *rx_page; 2367 2368 rx_page = *page; 2369 /* Update consumer position. */ 2370 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2371 ALE_RX_PAGE_ALIGN); 2372 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2373 /* 2374 * End of Rx page reached, let hardware reuse 2375 * this page. 2376 */ 2377 rx_page->cons = 0; 2378 *rx_page->cmb_addr = 0; 2379 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2380 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2381 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2382 RXF_VALID); 2383 /* Switch to alternate Rx page. */ 2384 sc->ale_cdata.ale_rx_curp ^= 1; 2385 rx_page = *page = 2386 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2387 /* Page flipped, sync CMB and Rx page. */ 2388 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2389 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2390 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2391 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2392 /* Sync completed, cache updated producer index. */ 2393 *prod = *rx_page->cmb_addr; 2394 } 2395} 2396 2397/* 2398 * It seems that AR81xx controller can compute partial checksum. 2399 * The partial checksum value can be used to accelerate checksum 2400 * computation for fragmented TCP/UDP packets. Upper network stack 2401 * already takes advantage of the partial checksum value in IP 2402 * reassembly stage. But I'm not sure the correctness of the 2403 * partial hardware checksum assistance due to lack of data sheet. 2404 * In addition, the Rx feature of controller that requires copying 2405 * for every frames effectively nullifies one of most nice offload 2406 * capability of controller. 2407 */ 2408static void 2409ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2410{ 2411 struct ifnet *ifp; 2412 struct ip *ip; 2413 char *p; 2414 2415 ifp = sc->ale_ifp; 2416 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2417 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2418 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2419 2420 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2421 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2422 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2423 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2424 m->m_pkthdr.csum_flags |= 2425 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2426 m->m_pkthdr.csum_data = 0xffff; 2427 } 2428 } else { 2429 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2430 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2431 p = mtod(m, char *); 2432 p += ETHER_HDR_LEN; 2433 if ((status & ALE_RD_802_3) != 0) 2434 p += LLC_SNAPFRAMELEN; 2435 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2436 (status & ALE_RD_VLAN) != 0) 2437 p += ETHER_VLAN_ENCAP_LEN; 2438 ip = (struct ip *)p; 2439 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2440 return; 2441 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2442 CSUM_PSEUDO_HDR; 2443 m->m_pkthdr.csum_data = 0xffff; 2444 } 2445 } 2446 /* 2447 * Don't mark bad checksum for TCP/UDP frames 2448 * as fragmented frames may always have set 2449 * bad checksummed bit of frame status. 2450 */ 2451} 2452 2453/* Process received frames. */ 2454static int 2455ale_rxeof(struct ale_softc *sc, int count) 2456{ 2457 struct ale_rx_page *rx_page; 2458 struct rx_rs *rs; 2459 struct ifnet *ifp; 2460 struct mbuf *m; 2461 uint32_t length, prod, seqno, status, vtags; 2462 int prog; 2463 2464 ifp = sc->ale_ifp; 2465 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2466 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2467 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2468 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2469 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2470 /* 2471 * Don't directly access producer index as hardware may 2472 * update it while Rx handler is in progress. It would 2473 * be even better if there is a way to let hardware 2474 * know how far driver processed its received frames. 2475 * Alternatively, hardware could provide a way to disable 2476 * CMB updates until driver acknowledges the end of CMB 2477 * access. 2478 */ 2479 prod = *rx_page->cmb_addr; 2480 for (prog = 0; prog < count; prog++) { 2481 if (rx_page->cons >= prod) 2482 break; 2483 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2484 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2485 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2486 /* 2487 * Normally I believe this should not happen unless 2488 * severe driver bug or corrupted memory. However 2489 * it seems to happen under certain conditions which 2490 * is triggered by abrupt Rx events such as initiation 2491 * of bulk transfer of remote host. It's not easy to 2492 * reproduce this and I doubt it could be related 2493 * with FIFO overflow of hardware or activity of Tx 2494 * CMB updates. I also remember similar behaviour 2495 * seen on RealTek 8139 which uses resembling Rx 2496 * scheme. 2497 */ 2498 if (bootverbose) 2499 device_printf(sc->ale_dev, 2500 "garbled seq: %u, expected: %u -- " 2501 "resetting!\n", seqno, 2502 sc->ale_cdata.ale_rx_seqno); 2503 return (EIO); 2504 } 2505 /* Frame received. */ 2506 sc->ale_cdata.ale_rx_seqno++; 2507 length = ALE_RX_BYTES(le32toh(rs->length)); 2508 status = le32toh(rs->flags); 2509 if ((status & ALE_RD_ERROR) != 0) { 2510 /* 2511 * We want to pass the following frames to upper 2512 * layer regardless of error status of Rx return 2513 * status. 2514 * 2515 * o IP/TCP/UDP checksum is bad. 2516 * o frame length and protocol specific length 2517 * does not match. 2518 */ 2519 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2520 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2521 ALE_RD_TRUNC)) != 0) { 2522 ale_rx_update_page(sc, &rx_page, length, &prod); 2523 continue; 2524 } 2525 } 2526 /* 2527 * m_devget(9) is major bottle-neck of ale(4)(It comes 2528 * from hardware limitation). For jumbo frames we could 2529 * get a slightly better performance if driver use 2530 * m_getjcl(9) with proper buffer size argument. However 2531 * that would make code more complicated and I don't 2532 * think users would expect good Rx performance numbers 2533 * on these low-end consumer ethernet controller. 2534 */ 2535 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2536 ETHER_ALIGN, ifp, NULL); 2537 if (m == NULL) { 2538 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2539 ale_rx_update_page(sc, &rx_page, length, &prod); 2540 continue; 2541 } 2542 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2543 (status & ALE_RD_IPV4) != 0) 2544 ale_rxcsum(sc, m, status); 2545 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2546 (status & ALE_RD_VLAN) != 0) { 2547 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2548 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2549 m->m_flags |= M_VLANTAG; 2550 } 2551 2552 /* Pass it to upper layer. */ 2553 ALE_UNLOCK(sc); 2554 (*ifp->if_input)(ifp, m); 2555 ALE_LOCK(sc); 2556 2557 ale_rx_update_page(sc, &rx_page, length, &prod); 2558 } 2559 2560 return (count > 0 ? 0 : EAGAIN); 2561} 2562 2563static void 2564ale_tick(void *arg) 2565{ 2566 struct ale_softc *sc; 2567 struct mii_data *mii; 2568 2569 sc = (struct ale_softc *)arg; 2570 2571 ALE_LOCK_ASSERT(sc); 2572 2573 mii = device_get_softc(sc->ale_miibus); 2574 mii_tick(mii); 2575 ale_stats_update(sc); 2576 /* 2577 * Reclaim Tx buffers that have been transferred. It's not 2578 * needed here but it would release allocated mbuf chains 2579 * faster and limit the maximum delay to a hz. 2580 */ 2581 ale_txeof(sc); 2582 ale_watchdog(sc); 2583 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2584} 2585 2586static void 2587ale_reset(struct ale_softc *sc) 2588{ 2589 uint32_t reg; 2590 int i; 2591 2592 /* Initialize PCIe module. From Linux. */ 2593 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2594 2595 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2596 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2597 DELAY(10); 2598 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2599 break; 2600 } 2601 if (i == 0) 2602 device_printf(sc->ale_dev, "master reset timeout!\n"); 2603 2604 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2605 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2606 break; 2607 DELAY(10); 2608 } 2609 2610 if (i == 0) 2611 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2612} 2613 2614static void 2615ale_init(void *xsc) 2616{ 2617 struct ale_softc *sc; 2618 2619 sc = (struct ale_softc *)xsc; 2620 ALE_LOCK(sc); 2621 ale_init_locked(sc); 2622 ALE_UNLOCK(sc); 2623} 2624 2625static void 2626ale_init_locked(struct ale_softc *sc) 2627{ 2628 struct ifnet *ifp; 2629 struct mii_data *mii; 2630 uint8_t eaddr[ETHER_ADDR_LEN]; 2631 bus_addr_t paddr; 2632 uint32_t reg, rxf_hi, rxf_lo; 2633 2634 ALE_LOCK_ASSERT(sc); 2635 2636 ifp = sc->ale_ifp; 2637 mii = device_get_softc(sc->ale_miibus); 2638 2639 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2640 return; 2641 /* 2642 * Cancel any pending I/O. 2643 */ 2644 ale_stop(sc); 2645 /* 2646 * Reset the chip to a known state. 2647 */ 2648 ale_reset(sc); 2649 /* Initialize Tx descriptors, DMA memory blocks. */ 2650 ale_init_rx_pages(sc); 2651 ale_init_tx_ring(sc); 2652 2653 /* Reprogram the station address. */ 2654 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2655 CSR_WRITE_4(sc, ALE_PAR0, 2656 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2657 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2658 /* 2659 * Clear WOL status and disable all WOL feature as WOL 2660 * would interfere Rx operation under normal environments. 2661 */ 2662 CSR_READ_4(sc, ALE_WOL_CFG); 2663 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2664 /* 2665 * Set Tx descriptor/RXF0/CMB base addresses. They share 2666 * the same high address part of DMAable region. 2667 */ 2668 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2669 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2670 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2671 CSR_WRITE_4(sc, ALE_TPD_CNT, 2672 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2673 /* Set Rx page base address, note we use single queue. */ 2674 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2675 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2676 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2677 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2678 /* Set Tx/Rx CMB addresses. */ 2679 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2680 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2681 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2682 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2683 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2684 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2685 /* Mark RXF0 is valid. */ 2686 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2687 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2688 /* 2689 * No need to initialize RFX1/RXF2/RXF3. We don't use 2690 * multi-queue yet. 2691 */ 2692 2693 /* Set Rx page size, excluding guard frame size. */ 2694 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2695 /* Tell hardware that we're ready to load DMA blocks. */ 2696 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2697 2698 /* Set Rx/Tx interrupt trigger threshold. */ 2699 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2700 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2701 /* 2702 * XXX 2703 * Set interrupt trigger timer, its purpose and relation 2704 * with interrupt moderation mechanism is not clear yet. 2705 */ 2706 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2707 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2708 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2709 2710 /* Configure interrupt moderation timer. */ 2711 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2712 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2713 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2714 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2715 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2716 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2717 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2718 reg |= MASTER_IM_RX_TIMER_ENB; 2719 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2720 reg |= MASTER_IM_TX_TIMER_ENB; 2721 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2722 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2723 2724 /* Set Maximum frame size of controller. */ 2725 if (ifp->if_mtu < ETHERMTU) 2726 sc->ale_max_frame_size = ETHERMTU; 2727 else 2728 sc->ale_max_frame_size = ifp->if_mtu; 2729 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2730 ETHER_CRC_LEN; 2731 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2732 /* Configure IPG/IFG parameters. */ 2733 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2734 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2735 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2736 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2737 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2738 /* Set parameters for half-duplex media. */ 2739 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2740 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2741 HDPX_CFG_LCOL_MASK) | 2742 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2743 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2744 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2745 HDPX_CFG_ABEBT_MASK) | 2746 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2747 HDPX_CFG_JAMIPG_MASK)); 2748 2749 /* Configure Tx jumbo frame parameters. */ 2750 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2751 if (ifp->if_mtu < ETHERMTU) 2752 reg = sc->ale_max_frame_size; 2753 else if (ifp->if_mtu < 6 * 1024) 2754 reg = (sc->ale_max_frame_size * 2) / 3; 2755 else 2756 reg = sc->ale_max_frame_size / 2; 2757 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2758 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2759 TX_JUMBO_THRESH_UNIT_SHIFT); 2760 } 2761 /* Configure TxQ. */ 2762 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2763 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2764 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2765 TXQ_CFG_TPD_BURST_MASK; 2766 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2767 2768 /* Configure Rx jumbo frame & flow control parameters. */ 2769 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2770 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2771 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2772 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2773 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2774 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2775 RX_JUMBO_LKAH_MASK)); 2776 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2777 rxf_hi = (reg * 7) / 10; 2778 rxf_lo = (reg * 3)/ 10; 2779 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2780 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2781 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2782 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2783 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2784 } 2785 2786 /* Disable RSS. */ 2787 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2788 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2789 2790 /* Configure RxQ. */ 2791 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2792 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2793 2794 /* Configure DMA parameters. */ 2795 reg = 0; 2796 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2797 reg |= DMA_CFG_TXCMB_ENB; 2798 CSR_WRITE_4(sc, ALE_DMA_CFG, 2799 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2800 sc->ale_dma_rd_burst | reg | 2801 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2802 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2803 DMA_CFG_RD_DELAY_CNT_MASK) | 2804 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2805 DMA_CFG_WR_DELAY_CNT_MASK)); 2806 2807 /* 2808 * Hardware can be configured to issue SMB interrupt based 2809 * on programmed interval. Since there is a callout that is 2810 * invoked for every hz in driver we use that instead of 2811 * relying on periodic SMB interrupt. 2812 */ 2813 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2814 /* Clear MAC statistics. */ 2815 ale_stats_clear(sc); 2816 2817 /* 2818 * Configure Tx/Rx MACs. 2819 * - Auto-padding for short frames. 2820 * - Enable CRC generation. 2821 * Actual reconfiguration of MAC for resolved speed/duplex 2822 * is followed after detection of link establishment. 2823 * AR81xx always does checksum computation regardless of 2824 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2825 * cause Rx handling issue for fragmented IP datagrams due 2826 * to silicon bug. 2827 */ 2828 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2829 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2830 MAC_CFG_PREAMBLE_MASK); 2831 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2832 reg |= MAC_CFG_SPEED_10_100; 2833 else 2834 reg |= MAC_CFG_SPEED_1000; 2835 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2836 2837 /* Set up the receive filter. */ 2838 ale_rxfilter(sc); 2839 ale_rxvlan(sc); 2840 2841 /* Acknowledge all pending interrupts and clear it. */ 2842 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2843 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2844 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2845 2846 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2847 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2848 2849 sc->ale_flags &= ~ALE_FLAG_LINK; 2850 /* Switch to the current media. */ 2851 mii_mediachg(mii); 2852 2853 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2854} 2855 2856static void 2857ale_stop(struct ale_softc *sc) 2858{ 2859 struct ifnet *ifp; 2860 struct ale_txdesc *txd; 2861 uint32_t reg; 2862 int i; 2863 2864 ALE_LOCK_ASSERT(sc); 2865 /* 2866 * Mark the interface down and cancel the watchdog timer. 2867 */ 2868 ifp = sc->ale_ifp; 2869 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2870 sc->ale_flags &= ~ALE_FLAG_LINK; 2871 callout_stop(&sc->ale_tick_ch); 2872 sc->ale_watchdog_timer = 0; 2873 ale_stats_update(sc); 2874 /* Disable interrupts. */ 2875 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2876 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2877 /* Disable queue processing and DMA. */ 2878 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2879 reg &= ~TXQ_CFG_ENB; 2880 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2881 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2882 reg &= ~RXQ_CFG_ENB; 2883 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2884 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2885 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2886 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2887 DELAY(1000); 2888 /* Stop Rx/Tx MACs. */ 2889 ale_stop_mac(sc); 2890 /* Disable interrupts which might be touched in taskq handler. */ 2891 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2892 2893 /* 2894 * Free TX mbufs still in the queues. 2895 */ 2896 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2897 txd = &sc->ale_cdata.ale_txdesc[i]; 2898 if (txd->tx_m != NULL) { 2899 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2900 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2901 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2902 txd->tx_dmamap); 2903 m_freem(txd->tx_m); 2904 txd->tx_m = NULL; 2905 } 2906 } 2907} 2908 2909static void 2910ale_stop_mac(struct ale_softc *sc) 2911{ 2912 uint32_t reg; 2913 int i; 2914 2915 ALE_LOCK_ASSERT(sc); 2916 2917 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2918 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2919 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2920 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2921 } 2922 2923 for (i = ALE_TIMEOUT; i > 0; i--) { 2924 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2925 if (reg == 0) 2926 break; 2927 DELAY(10); 2928 } 2929 if (i == 0) 2930 device_printf(sc->ale_dev, 2931 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2932} 2933 2934static void 2935ale_init_tx_ring(struct ale_softc *sc) 2936{ 2937 struct ale_txdesc *txd; 2938 int i; 2939 2940 ALE_LOCK_ASSERT(sc); 2941 2942 sc->ale_cdata.ale_tx_prod = 0; 2943 sc->ale_cdata.ale_tx_cons = 0; 2944 sc->ale_cdata.ale_tx_cnt = 0; 2945 2946 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2947 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2948 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2949 txd = &sc->ale_cdata.ale_txdesc[i]; 2950 txd->tx_m = NULL; 2951 } 2952 *sc->ale_cdata.ale_tx_cmb = 0; 2953 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2954 sc->ale_cdata.ale_tx_cmb_map, 2955 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2956 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2957 sc->ale_cdata.ale_tx_ring_map, 2958 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2959} 2960 2961static void 2962ale_init_rx_pages(struct ale_softc *sc) 2963{ 2964 struct ale_rx_page *rx_page; 2965 int i; 2966 2967 ALE_LOCK_ASSERT(sc); 2968 2969 sc->ale_morework = 0; 2970 sc->ale_cdata.ale_rx_seqno = 0; 2971 sc->ale_cdata.ale_rx_curp = 0; 2972 2973 for (i = 0; i < ALE_RX_PAGES; i++) { 2974 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2975 bzero(rx_page->page_addr, sc->ale_pagesize); 2976 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2977 rx_page->cons = 0; 2978 *rx_page->cmb_addr = 0; 2979 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2980 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2981 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2982 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2983 } 2984} 2985 2986static void 2987ale_rxvlan(struct ale_softc *sc) 2988{ 2989 struct ifnet *ifp; 2990 uint32_t reg; 2991 2992 ALE_LOCK_ASSERT(sc); 2993 2994 ifp = sc->ale_ifp; 2995 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2996 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2997 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2998 reg |= MAC_CFG_VLAN_TAG_STRIP; 2999 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3000} 3001 3002static u_int 3003ale_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3004{ 3005 uint32_t crc, *mchash = arg; 3006 3007 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 3008 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3009 3010 return (1); 3011} 3012 3013static void 3014ale_rxfilter(struct ale_softc *sc) 3015{ 3016 struct ifnet *ifp; 3017 uint32_t mchash[2]; 3018 uint32_t rxcfg; 3019 3020 ALE_LOCK_ASSERT(sc); 3021 3022 ifp = sc->ale_ifp; 3023 3024 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3025 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3026 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3027 rxcfg |= MAC_CFG_BCAST; 3028 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3029 if ((ifp->if_flags & IFF_PROMISC) != 0) 3030 rxcfg |= MAC_CFG_PROMISC; 3031 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3032 rxcfg |= MAC_CFG_ALLMULTI; 3033 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3034 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3035 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3036 return; 3037 } 3038 3039 /* Program new filter. */ 3040 bzero(mchash, sizeof(mchash)); 3041 if_foreach_llmaddr(ifp, ale_hash_maddr, &mchash); 3042 3043 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3044 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3045 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3046} 3047 3048static int 3049sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3050{ 3051 int error, value; 3052 3053 if (arg1 == NULL) 3054 return (EINVAL); 3055 value = *(int *)arg1; 3056 error = sysctl_handle_int(oidp, &value, 0, req); 3057 if (error || req->newptr == NULL) 3058 return (error); 3059 if (value < low || value > high) 3060 return (EINVAL); 3061 *(int *)arg1 = value; 3062 3063 return (0); 3064} 3065 3066static int 3067sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3068{ 3069 return (sysctl_int_range(oidp, arg1, arg2, req, 3070 ALE_PROC_MIN, ALE_PROC_MAX)); 3071} 3072 3073static int 3074sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3075{ 3076 3077 return (sysctl_int_range(oidp, arg1, arg2, req, 3078 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3079} 3080