1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-eoi-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon eoi. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision: 69515 $<hr> 50 * 51 */ 52#ifndef __CVMX_EOI_DEFS_H__ 53#define __CVMX_EOI_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_EOI_BIST_CTL_STA CVMX_EOI_BIST_CTL_STA_FUNC() 57static inline uint64_t CVMX_EOI_BIST_CTL_STA_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60 cvmx_warn("CVMX_EOI_BIST_CTL_STA not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x0001180013000118ull); 62} 63#else 64#define CVMX_EOI_BIST_CTL_STA (CVMX_ADD_IO_SEG(0x0001180013000118ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_EOI_CTL_STA CVMX_EOI_CTL_STA_FUNC() 68static inline uint64_t CVMX_EOI_CTL_STA_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 71 cvmx_warn("CVMX_EOI_CTL_STA not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x0001180013000000ull); 73} 74#else 75#define CVMX_EOI_CTL_STA (CVMX_ADD_IO_SEG(0x0001180013000000ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78#define CVMX_EOI_DEF_STA0 CVMX_EOI_DEF_STA0_FUNC() 79static inline uint64_t CVMX_EOI_DEF_STA0_FUNC(void) 80{ 81 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 82 cvmx_warn("CVMX_EOI_DEF_STA0 not supported on this chip\n"); 83 return CVMX_ADD_IO_SEG(0x0001180013000020ull); 84} 85#else 86#define CVMX_EOI_DEF_STA0 (CVMX_ADD_IO_SEG(0x0001180013000020ull)) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89#define CVMX_EOI_DEF_STA1 CVMX_EOI_DEF_STA1_FUNC() 90static inline uint64_t CVMX_EOI_DEF_STA1_FUNC(void) 91{ 92 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 93 cvmx_warn("CVMX_EOI_DEF_STA1 not supported on this chip\n"); 94 return CVMX_ADD_IO_SEG(0x0001180013000028ull); 95} 96#else 97#define CVMX_EOI_DEF_STA1 (CVMX_ADD_IO_SEG(0x0001180013000028ull)) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100#define CVMX_EOI_DEF_STA2 CVMX_EOI_DEF_STA2_FUNC() 101static inline uint64_t CVMX_EOI_DEF_STA2_FUNC(void) 102{ 103 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 104 cvmx_warn("CVMX_EOI_DEF_STA2 not supported on this chip\n"); 105 return CVMX_ADD_IO_SEG(0x0001180013000030ull); 106} 107#else 108#define CVMX_EOI_DEF_STA2 (CVMX_ADD_IO_SEG(0x0001180013000030ull)) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111#define CVMX_EOI_ECC_CTL CVMX_EOI_ECC_CTL_FUNC() 112static inline uint64_t CVMX_EOI_ECC_CTL_FUNC(void) 113{ 114 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 115 cvmx_warn("CVMX_EOI_ECC_CTL not supported on this chip\n"); 116 return CVMX_ADD_IO_SEG(0x0001180013000110ull); 117} 118#else 119#define CVMX_EOI_ECC_CTL (CVMX_ADD_IO_SEG(0x0001180013000110ull)) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122#define CVMX_EOI_ENDOR_BISTR_CTL_STA CVMX_EOI_ENDOR_BISTR_CTL_STA_FUNC() 123static inline uint64_t CVMX_EOI_ENDOR_BISTR_CTL_STA_FUNC(void) 124{ 125 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 126 cvmx_warn("CVMX_EOI_ENDOR_BISTR_CTL_STA not supported on this chip\n"); 127 return CVMX_ADD_IO_SEG(0x0001180013000120ull); 128} 129#else 130#define CVMX_EOI_ENDOR_BISTR_CTL_STA (CVMX_ADD_IO_SEG(0x0001180013000120ull)) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133#define CVMX_EOI_ENDOR_CLK_CTL CVMX_EOI_ENDOR_CLK_CTL_FUNC() 134static inline uint64_t CVMX_EOI_ENDOR_CLK_CTL_FUNC(void) 135{ 136 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 137 cvmx_warn("CVMX_EOI_ENDOR_CLK_CTL not supported on this chip\n"); 138 return CVMX_ADD_IO_SEG(0x0001180013000038ull); 139} 140#else 141#define CVMX_EOI_ENDOR_CLK_CTL (CVMX_ADD_IO_SEG(0x0001180013000038ull)) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144#define CVMX_EOI_ENDOR_CTL CVMX_EOI_ENDOR_CTL_FUNC() 145static inline uint64_t CVMX_EOI_ENDOR_CTL_FUNC(void) 146{ 147 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 148 cvmx_warn("CVMX_EOI_ENDOR_CTL not supported on this chip\n"); 149 return CVMX_ADD_IO_SEG(0x0001180013000100ull); 150} 151#else 152#define CVMX_EOI_ENDOR_CTL (CVMX_ADD_IO_SEG(0x0001180013000100ull)) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155#define CVMX_EOI_INT_ENA CVMX_EOI_INT_ENA_FUNC() 156static inline uint64_t CVMX_EOI_INT_ENA_FUNC(void) 157{ 158 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 159 cvmx_warn("CVMX_EOI_INT_ENA not supported on this chip\n"); 160 return CVMX_ADD_IO_SEG(0x0001180013000010ull); 161} 162#else 163#define CVMX_EOI_INT_ENA (CVMX_ADD_IO_SEG(0x0001180013000010ull)) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166#define CVMX_EOI_INT_STA CVMX_EOI_INT_STA_FUNC() 167static inline uint64_t CVMX_EOI_INT_STA_FUNC(void) 168{ 169 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 170 cvmx_warn("CVMX_EOI_INT_STA not supported on this chip\n"); 171 return CVMX_ADD_IO_SEG(0x0001180013000008ull); 172} 173#else 174#define CVMX_EOI_INT_STA (CVMX_ADD_IO_SEG(0x0001180013000008ull)) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177#define CVMX_EOI_IO_DRV CVMX_EOI_IO_DRV_FUNC() 178static inline uint64_t CVMX_EOI_IO_DRV_FUNC(void) 179{ 180 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 181 cvmx_warn("CVMX_EOI_IO_DRV not supported on this chip\n"); 182 return CVMX_ADD_IO_SEG(0x0001180013000018ull); 183} 184#else 185#define CVMX_EOI_IO_DRV (CVMX_ADD_IO_SEG(0x0001180013000018ull)) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188#define CVMX_EOI_THROTTLE_CTL CVMX_EOI_THROTTLE_CTL_FUNC() 189static inline uint64_t CVMX_EOI_THROTTLE_CTL_FUNC(void) 190{ 191 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 192 cvmx_warn("CVMX_EOI_THROTTLE_CTL not supported on this chip\n"); 193 return CVMX_ADD_IO_SEG(0x0001180013000108ull); 194} 195#else 196#define CVMX_EOI_THROTTLE_CTL (CVMX_ADD_IO_SEG(0x0001180013000108ull)) 197#endif 198 199/** 200 * cvmx_eoi_bist_ctl_sta 201 * 202 * EOI_BIST_CTL_STA = EOI BIST Status Register 203 * 204 * Description: 205 * This register control EOI memory BIST and contains the bist result of EOI memories. 206 */ 207union cvmx_eoi_bist_ctl_sta { 208 uint64_t u64; 209 struct cvmx_eoi_bist_ctl_sta_s { 210#ifdef __BIG_ENDIAN_BITFIELD 211 uint64_t reserved_18_63 : 46; 212 uint64_t clear_bist : 1; /**< Clear BIST on the HCLK memories */ 213 uint64_t start_bist : 1; /**< Starts BIST on the HCLK memories during 0-to-1 214 transition. */ 215 uint64_t reserved_3_15 : 13; 216 uint64_t stdf : 1; /**< STDF Bist Status. */ 217 uint64_t ppaf : 1; /**< PPAF Bist Status. */ 218 uint64_t lddf : 1; /**< LDDF Bist Status. */ 219#else 220 uint64_t lddf : 1; 221 uint64_t ppaf : 1; 222 uint64_t stdf : 1; 223 uint64_t reserved_3_15 : 13; 224 uint64_t start_bist : 1; 225 uint64_t clear_bist : 1; 226 uint64_t reserved_18_63 : 46; 227#endif 228 } s; 229 struct cvmx_eoi_bist_ctl_sta_s cnf71xx; 230}; 231typedef union cvmx_eoi_bist_ctl_sta cvmx_eoi_bist_ctl_sta_t; 232 233/** 234 * cvmx_eoi_ctl_sta 235 * 236 * EOI_CTL_STA = EOI Configure Control Reigster 237 * This register configures EOI. 238 */ 239union cvmx_eoi_ctl_sta { 240 uint64_t u64; 241 struct cvmx_eoi_ctl_sta_s { 242#ifdef __BIG_ENDIAN_BITFIELD 243 uint64_t reserved_13_63 : 51; 244 uint64_t ppaf_wm : 5; /**< Number of entries when PP Access FIFO will assert 245 full (back pressure) */ 246 uint64_t reserved_5_7 : 3; 247 uint64_t busy : 1; /**< 1: EOI is busy; 0: EOI is idle */ 248 uint64_t rwam : 2; /**< Rread Write Aribitration Mode: 249 - 10: Reads have higher priority 250 - 01: Writes have higher priority 251 00,11: Round-Robin between Reads and Writes */ 252 uint64_t ena : 1; /**< When reset, all the inbound DMA accesses will be 253 drop and all the outbound read response and write 254 commits will be drop. It must be set to 1'b1 for 255 normal access. */ 256 uint64_t reset : 1; /**< EOI block Software Reset. */ 257#else 258 uint64_t reset : 1; 259 uint64_t ena : 1; 260 uint64_t rwam : 2; 261 uint64_t busy : 1; 262 uint64_t reserved_5_7 : 3; 263 uint64_t ppaf_wm : 5; 264 uint64_t reserved_13_63 : 51; 265#endif 266 } s; 267 struct cvmx_eoi_ctl_sta_s cnf71xx; 268}; 269typedef union cvmx_eoi_ctl_sta cvmx_eoi_ctl_sta_t; 270 271/** 272 * cvmx_eoi_def_sta0 273 * 274 * Note: Working settings tabulated for each corner. 275 * ================================ 276 * Corner pctl nctl 277 * =============================== 278 * 1 26 22 279 * 2 30 28 280 * 3 32 31 281 * 4 23 19 282 * 5 27 24 283 * 6 29 27 284 * 7 21 17 285 * 8 25 22 286 * 9 27 24 287 * 10 29 24 288 * 11 34 31 289 * 12 36 35 290 * 13 26 21 291 * 14 31 27 292 * 15 33 30 293 * 16 23 18 294 * 17 28 24 295 * 18 30 27 296 * 19 21 17 297 * 20 27 25 298 * 21 29 28 299 * 22 21 17 300 * 23 25 22 301 * 24 27 25 302 * 25 19 15 303 * 26 23 20 304 * 27 25 22 305 * 28 24 24 306 * 29 28 31 307 * 30 30 35 308 * 31 21 21 309 * 32 25 27 310 * 33 27 30 311 * 34 19 18 312 * 35 23 24 313 * 36 25 27 314 * 37 29 19 315 * 38 33 25 316 * 39 36 28 317 * 40 25 17 318 * 41 30 22 319 * 42 32 25 320 * 43 23 15 321 * 44 27 20 322 * 45 29 22 323 * =============================== 324 * 325 * EOI_DEF_STA0 = EOI Defect Status Register 0 326 * 327 * Register to hold repairout 0/1/2 328 */ 329union cvmx_eoi_def_sta0 { 330 uint64_t u64; 331 struct cvmx_eoi_def_sta0_s { 332#ifdef __BIG_ENDIAN_BITFIELD 333 uint64_t reserved_54_63 : 10; 334 uint64_t rout2 : 18; /**< Repairout2 */ 335 uint64_t rout1 : 18; /**< Repairout1 */ 336 uint64_t rout0 : 18; /**< Repairout0 */ 337#else 338 uint64_t rout0 : 18; 339 uint64_t rout1 : 18; 340 uint64_t rout2 : 18; 341 uint64_t reserved_54_63 : 10; 342#endif 343 } s; 344 struct cvmx_eoi_def_sta0_s cnf71xx; 345}; 346typedef union cvmx_eoi_def_sta0 cvmx_eoi_def_sta0_t; 347 348/** 349 * cvmx_eoi_def_sta1 350 * 351 * EOI_DEF_STA1 = EOI Defect Status Register 1 352 * 353 * Register to hold repairout 3/4/5 354 */ 355union cvmx_eoi_def_sta1 { 356 uint64_t u64; 357 struct cvmx_eoi_def_sta1_s { 358#ifdef __BIG_ENDIAN_BITFIELD 359 uint64_t reserved_54_63 : 10; 360 uint64_t rout5 : 18; /**< Repairout5 */ 361 uint64_t rout4 : 18; /**< Repairout4 */ 362 uint64_t rout3 : 18; /**< Repairout3 */ 363#else 364 uint64_t rout3 : 18; 365 uint64_t rout4 : 18; 366 uint64_t rout5 : 18; 367 uint64_t reserved_54_63 : 10; 368#endif 369 } s; 370 struct cvmx_eoi_def_sta1_s cnf71xx; 371}; 372typedef union cvmx_eoi_def_sta1 cvmx_eoi_def_sta1_t; 373 374/** 375 * cvmx_eoi_def_sta2 376 * 377 * EOI_DEF_STA2 = EOI Defect Status Register 2 378 * 379 * Register to hold repairout 6 and toomanydefects. 380 */ 381union cvmx_eoi_def_sta2 { 382 uint64_t u64; 383 struct cvmx_eoi_def_sta2_s { 384#ifdef __BIG_ENDIAN_BITFIELD 385 uint64_t reserved_25_63 : 39; 386 uint64_t toomany : 1; /**< Toomanydefects */ 387 uint64_t reserved_18_23 : 6; 388 uint64_t rout6 : 18; /**< Repairout6 */ 389#else 390 uint64_t rout6 : 18; 391 uint64_t reserved_18_23 : 6; 392 uint64_t toomany : 1; 393 uint64_t reserved_25_63 : 39; 394#endif 395 } s; 396 struct cvmx_eoi_def_sta2_s cnf71xx; 397}; 398typedef union cvmx_eoi_def_sta2 cvmx_eoi_def_sta2_t; 399 400/** 401 * cvmx_eoi_ecc_ctl 402 * 403 * EOI_ECC_CTL = EOI ECC Control Register 404 * 405 * Description: 406 * This register enables ECC for each individual internal memory that requires ECC. For debug purpose, it can also 407 * control 1 or 2 bits be flipped in the ECC data. 408 */ 409union cvmx_eoi_ecc_ctl { 410 uint64_t u64; 411 struct cvmx_eoi_ecc_ctl_s { 412#ifdef __BIG_ENDIAN_BITFIELD 413 uint64_t reserved_3_63 : 61; 414 uint64_t rben : 1; /**< 1: ECC Enable for read buffer 415 - 0: ECC Enable for instruction buffer */ 416 uint64_t rbsf : 2; /**< read buffer ecc syndrome flip 417 2'b00 : No Error Generation 418 2'b10, 2'b01: Flip 1 bit 419 2'b11 : Flip 2 bits */ 420#else 421 uint64_t rbsf : 2; 422 uint64_t rben : 1; 423 uint64_t reserved_3_63 : 61; 424#endif 425 } s; 426 struct cvmx_eoi_ecc_ctl_s cnf71xx; 427}; 428typedef union cvmx_eoi_ecc_ctl cvmx_eoi_ecc_ctl_t; 429 430/** 431 * cvmx_eoi_endor_bistr_ctl_sta 432 * 433 * EOI_ENDOR_BISTR_CTL_STA = EOI BIST/BISR Control Status Register 434 * 435 * Description: 436 * This register the bist result of EOI memories. 437 */ 438union cvmx_eoi_endor_bistr_ctl_sta { 439 uint64_t u64; 440 struct cvmx_eoi_endor_bistr_ctl_sta_s { 441#ifdef __BIG_ENDIAN_BITFIELD 442 uint64_t reserved_10_63 : 54; 443 uint64_t bisr_done : 1; /**< Endor DSP Memroy Bisr Done Status: 1 - done; 444 0 - Not done. */ 445 uint64_t failed : 1; /**< Bist/Bisr Status: 1 - failed; 0 - Not failed. */ 446 uint64_t reserved_3_7 : 5; 447 uint64_t bisr_hr : 1; /**< BISR Hardrepair */ 448 uint64_t bisr_dir : 1; /**< BISR Direction: 0 = input repair packets; 449 1 = output defect packets. */ 450 uint64_t start_bist : 1; /**< Start Bist */ 451#else 452 uint64_t start_bist : 1; 453 uint64_t bisr_dir : 1; 454 uint64_t bisr_hr : 1; 455 uint64_t reserved_3_7 : 5; 456 uint64_t failed : 1; 457 uint64_t bisr_done : 1; 458 uint64_t reserved_10_63 : 54; 459#endif 460 } s; 461 struct cvmx_eoi_endor_bistr_ctl_sta_s cnf71xx; 462}; 463typedef union cvmx_eoi_endor_bistr_ctl_sta cvmx_eoi_endor_bistr_ctl_sta_t; 464 465/** 466 * cvmx_eoi_endor_clk_ctl 467 * 468 * EOI_ENDOR_CLK_CTL = EOI Endor Clock Control 469 * 470 * Register control the generation of Endor DSP and HAB clocks. 471 */ 472union cvmx_eoi_endor_clk_ctl { 473 uint64_t u64; 474 struct cvmx_eoi_endor_clk_ctl_s { 475#ifdef __BIG_ENDIAN_BITFIELD 476 uint64_t reserved_28_63 : 36; 477 uint64_t habclk_sel : 1; /**< HAB CLK select 478 0x0: HAB CLK select from PHY_PLL output from HAB PS 479 0x1: HAB CLK select from DDR_PLL output from HAB PS */ 480 uint64_t reserved_26_26 : 1; 481 uint64_t dsp_div_reset : 1; /**< DSP postscalar divider reset */ 482 uint64_t dsp_ps_en : 3; /**< DSP postscalar divide ratio 483 Determines the DSP CK speed. 484 0x0 : Divide DSP PLL output by 1 485 0x1 : Divide DSP PLL output by 2 486 0x2 : Divide DSP PLL output by 3 487 0x3 : Divide DSP PLL output by 4 488 0x4 : Divide DSP PLL output by 6 489 0x5 : Divide DSP PLL output by 8 490 0x6 : Divide DSP PLL output by 12 491 0x7 : Divide DSP PLL output by 12 492 DSP_PS_EN is not used when DSP_DIV_RESET = 1 */ 493 uint64_t hab_div_reset : 1; /**< HAB postscalar divider reset */ 494 uint64_t hab_ps_en : 3; /**< HAB postscalar divide ratio 495 Determines the LMC CK speed. 496 0x0 : Divide HAB PLL output by 1 497 0x1 : Divide HAB PLL output by 2 498 0x2 : Divide HAB PLL output by 3 499 0x3 : Divide HAB PLL output by 4 500 0x4 : Divide HAB PLL output by 6 501 0x5 : Divide HAB PLL output by 8 502 0x6 : Divide HAB PLL output by 12 503 0x7 : Divide HAB PLL output by 12 504 HAB_PS_EN is not used when HAB_DIV_RESET = 1 */ 505 uint64_t diffamp : 4; /**< PLL diffamp input transconductance */ 506 uint64_t cps : 3; /**< PLL charge-pump current */ 507 uint64_t cpb : 3; /**< PLL charge-pump current */ 508 uint64_t reset_n : 1; /**< PLL reset */ 509 uint64_t clkf : 7; /**< Multiply reference by CLKF 510 32 <= CLKF <= 64 511 PHY PLL frequency = 50 * CLKF 512 min = 1.6 GHz, max = 3.2 GHz */ 513#else 514 uint64_t clkf : 7; 515 uint64_t reset_n : 1; 516 uint64_t cpb : 3; 517 uint64_t cps : 3; 518 uint64_t diffamp : 4; 519 uint64_t hab_ps_en : 3; 520 uint64_t hab_div_reset : 1; 521 uint64_t dsp_ps_en : 3; 522 uint64_t dsp_div_reset : 1; 523 uint64_t reserved_26_26 : 1; 524 uint64_t habclk_sel : 1; 525 uint64_t reserved_28_63 : 36; 526#endif 527 } s; 528 struct cvmx_eoi_endor_clk_ctl_s cnf71xx; 529}; 530typedef union cvmx_eoi_endor_clk_ctl cvmx_eoi_endor_clk_ctl_t; 531 532/** 533 * cvmx_eoi_endor_ctl 534 * 535 * EOI_ENDOR_CTL_STA = Endor Control Reigster 536 * This register controls Endor phy reset and access. 537 */ 538union cvmx_eoi_endor_ctl { 539 uint64_t u64; 540 struct cvmx_eoi_endor_ctl_s { 541#ifdef __BIG_ENDIAN_BITFIELD 542 uint64_t reserved_12_63 : 52; 543 uint64_t r_emod : 2; /**< Endian format for data read from the L2C. 544 IN: A-B-C-D-E-F-G-H 545 OUT0: A-B-C-D-E-F-G-H 546 OUT1: H-G-F-E-D-C-B-A 547 OUT2: D-C-B-A-H-G-F-E 548 OUT3: E-F-G-H-A-B-C-D */ 549 uint64_t w_emod : 2; /**< Endian format for data written the L2C. 550 IN: A-B-C-D-E-F-G-H 551 OUT0: A-B-C-D-E-F-G-H 552 OUT1: H-G-F-E-D-C-B-A 553 OUT2: D-C-B-A-H-G-F-E 554 OUT3: E-F-G-H-A-B-C-D */ 555 uint64_t inv_rsl_ra2 : 1; /**< Invert RSL CSR read address bit 2. */ 556 uint64_t inv_rsl_wa2 : 1; /**< Invert RSL CSR write address bit 2. */ 557 uint64_t inv_pp_ra2 : 1; /**< Invert PP CSR read address bit 2. */ 558 uint64_t inv_pp_wa2 : 1; /**< Invert PP CSR write address bit 2. */ 559 uint64_t reserved_1_3 : 3; 560 uint64_t reset : 1; /**< Endor block software reset. After hardware reset, 561 this bit is set to 1'b1 which put Endor into reset 562 state. Software must clear this bit to use Endor. */ 563#else 564 uint64_t reset : 1; 565 uint64_t reserved_1_3 : 3; 566 uint64_t inv_pp_wa2 : 1; 567 uint64_t inv_pp_ra2 : 1; 568 uint64_t inv_rsl_wa2 : 1; 569 uint64_t inv_rsl_ra2 : 1; 570 uint64_t w_emod : 2; 571 uint64_t r_emod : 2; 572 uint64_t reserved_12_63 : 52; 573#endif 574 } s; 575 struct cvmx_eoi_endor_ctl_s cnf71xx; 576}; 577typedef union cvmx_eoi_endor_ctl cvmx_eoi_endor_ctl_t; 578 579/** 580 * cvmx_eoi_int_ena 581 * 582 * EOI_INT_ENA = EOI Interrupt Enable Register 583 * 584 * Register to enable individual interrupt source in corresponding to EOI_INT_STA 585 */ 586union cvmx_eoi_int_ena { 587 uint64_t u64; 588 struct cvmx_eoi_int_ena_s { 589#ifdef __BIG_ENDIAN_BITFIELD 590 uint64_t reserved_2_63 : 62; 591 uint64_t rb_dbe : 1; /**< Read Buffer ECC DBE */ 592 uint64_t rb_sbe : 1; /**< Read Buffer ECC SBE */ 593#else 594 uint64_t rb_sbe : 1; 595 uint64_t rb_dbe : 1; 596 uint64_t reserved_2_63 : 62; 597#endif 598 } s; 599 struct cvmx_eoi_int_ena_s cnf71xx; 600}; 601typedef union cvmx_eoi_int_ena cvmx_eoi_int_ena_t; 602 603/** 604 * cvmx_eoi_int_sta 605 * 606 * EOI_INT_STA = EOI Interrupt Status Register 607 * 608 * Summary of different bits of RSL interrupt status. 609 */ 610union cvmx_eoi_int_sta { 611 uint64_t u64; 612 struct cvmx_eoi_int_sta_s { 613#ifdef __BIG_ENDIAN_BITFIELD 614 uint64_t reserved_2_63 : 62; 615 uint64_t rb_dbe : 1; /**< Read Buffer ECC DBE */ 616 uint64_t rb_sbe : 1; /**< Read Buffer ECC SBE */ 617#else 618 uint64_t rb_sbe : 1; 619 uint64_t rb_dbe : 1; 620 uint64_t reserved_2_63 : 62; 621#endif 622 } s; 623 struct cvmx_eoi_int_sta_s cnf71xx; 624}; 625typedef union cvmx_eoi_int_sta cvmx_eoi_int_sta_t; 626 627/** 628 * cvmx_eoi_io_drv 629 * 630 * EOI_IO_DRV = EOI Endor IO Drive Control 631 * 632 * Register to control Endor Phy IOs 633 */ 634union cvmx_eoi_io_drv { 635 uint64_t u64; 636 struct cvmx_eoi_io_drv_s { 637#ifdef __BIG_ENDIAN_BITFIELD 638 uint64_t reserved_24_63 : 40; 639 uint64_t rfif_p : 6; /**< RFIF output driver P-Mos control */ 640 uint64_t rfif_n : 6; /**< RFIF output driver N-Mos control */ 641 uint64_t gpo_p : 6; /**< GPO output driver P-Mos control */ 642 uint64_t gpo_n : 6; /**< GPO output driver N-Mos control */ 643#else 644 uint64_t gpo_n : 6; 645 uint64_t gpo_p : 6; 646 uint64_t rfif_n : 6; 647 uint64_t rfif_p : 6; 648 uint64_t reserved_24_63 : 40; 649#endif 650 } s; 651 struct cvmx_eoi_io_drv_s cnf71xx; 652}; 653typedef union cvmx_eoi_io_drv cvmx_eoi_io_drv_t; 654 655/** 656 * cvmx_eoi_throttle_ctl 657 * 658 * EOI_THROTTLE_CTL = EOI THROTTLE Control Reigster 659 * This register controls number of outstanding EOI loads to L2C . It is in phy_clock domain. 660 */ 661union cvmx_eoi_throttle_ctl { 662 uint64_t u64; 663 struct cvmx_eoi_throttle_ctl_s { 664#ifdef __BIG_ENDIAN_BITFIELD 665 uint64_t reserved_21_63 : 43; 666 uint64_t std : 5; /**< Number of outstanding store data accepted by EOI on 667 AXI before backpressure ADMA. The value must be from 668 from 16 to 31 inclusively. */ 669 uint64_t reserved_10_15 : 6; 670 uint64_t stc : 2; /**< Number of outstanding L2C store command accepted by 671 EOI on AXI before backpressure ADMA. The value must be 672 from 1 to 3 inclusively. */ 673 uint64_t reserved_4_7 : 4; 674 uint64_t ldc : 4; /**< Number of outstanding L2C loads. The value must be 675 from 1 to 8 inclusively. */ 676#else 677 uint64_t ldc : 4; 678 uint64_t reserved_4_7 : 4; 679 uint64_t stc : 2; 680 uint64_t reserved_10_15 : 6; 681 uint64_t std : 5; 682 uint64_t reserved_21_63 : 43; 683#endif 684 } s; 685 struct cvmx_eoi_throttle_ctl_s cnf71xx; 686}; 687typedef union cvmx_eoi_throttle_ctl cvmx_eoi_throttle_ctl_t; 688 689#endif 690