1/* 2 * Copyright 2008-2012 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 34#ifndef __FSL_FMAN_MEMAC_H 35#define __FSL_FMAN_MEMAC_H 36 37#include "common/general.h" 38#include "fsl_enet.h" 39 40 41#define MEMAC_NUM_OF_PADDRS 7 /* Num of additional exact match MAC adr regs */ 42 43/* Control and Configuration Register (COMMAND_CONFIG) */ 44#define CMD_CFG_MG 0x80000000 /* 00 Magic Packet detection */ 45#define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */ 46#define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */ 47#define CMD_CFG_SFD_ANY 0x00200000 /* 10 Disable SFD check */ 48#define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */ 49#define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */ 50#define CMD_CFG_SEND_IDLE 0x00010000 /* 15 Force idle generation */ 51#define CMD_CFG_CNT_FRM_EN 0x00002000 /* 18 Control frame rx enable */ 52#define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */ 53#define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */ 54#define CMD_CFG_LOOPBACK_EN 0x00000400 /* 21 XGMII/GMII loopback enable */ 55#define CMD_CFG_TX_ADDR_INS 0x00000200 /* 22 Tx source MAC addr insertion */ 56#define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */ 57#define CMD_CFG_PAUSE_FWD 0x00000080 /* 24 Terminate/frwd Pause frames */ 58#define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */ 59#define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */ 60#define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */ 61#define CMD_CFG_WAN_MODE 0x00000008 /* 28 WAN mode enable */ 62#define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */ 63#define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */ 64 65/* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */ 66#define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000 67#define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF 68#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000 69#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000 70#define TX_FIFO_SECTIONS_TX_EMPTY_PFC_10G 0x00360000 71#define TX_FIFO_SECTIONS_TX_EMPTY_PFC_1G 0x00040000 72#define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019 73#define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020 74#define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x00000060 75 76#define GET_TX_EMPTY_DEFAULT_VALUE(_val) \ 77_val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \ 78((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \ 79 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) : \ 80 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G)); 81 82#define GET_TX_EMPTY_PFC_VALUE(_val) \ 83_val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \ 84((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \ 85 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_PFC_10G) : \ 86 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_PFC_1G)); 87 88/* Interface Mode Register (IF_MODE) */ 89#define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */ 90#define IF_MODE_XGMII 0x00000000 /* 30-31 XGMII (10G) interface */ 91#define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */ 92#define IF_MODE_RGMII 0x00000004 93#define IF_MODE_RGMII_AUTO 0x00008000 94#define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */ 95#define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */ 96#define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */ 97#define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */ 98#define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */ 99#define IF_MODE_HD 0x00000040 /* Half duplex operation */ 100 101/* Hash table Control Register (HASHTABLE_CTRL) */ 102#define HASH_CTRL_MCAST_SHIFT 26 103#define HASH_CTRL_MCAST_EN 0x00000100 /* 23 Mcast frame rx for hash */ 104#define HASH_CTRL_ADDR_MASK 0x0000003F /* 26-31 Hash table address code */ 105 106#define GROUP_ADDRESS 0x0000010000000000LL /* MAC mcast indication */ 107#define HASH_TABLE_SIZE 64 /* Hash tbl size */ 108 109/* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */ 110#define MEMAC_TX_IPG_LENGTH_MASK 0x0000003F 111 112/* Statistics Configuration Register (STATN_CONFIG) */ 113#define STATS_CFG_CLR 0x00000004 /* 29 Reset all counters */ 114#define STATS_CFG_CLR_ON_RD 0x00000002 /* 30 Clear on read */ 115#define STATS_CFG_SATURATE 0x00000001 /* 31 Saturate at the maximum val */ 116 117/* Interrupt Mask Register (IMASK) */ 118#define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */ 119#define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */ 120#define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */ 121#define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */ 122 123#define MEMAC_ALL_ERRS_IMASK \ 124 ((uint32_t)(MEMAC_IMASK_TSECC_ER | \ 125 MEMAC_IMASK_TECC_ER | \ 126 MEMAC_IMASK_RECC_ER | \ 127 MEMAC_IMASK_MGI)) 128 129#define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */ 130#define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */ 131#define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */ 132#define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */ 133#define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error */ 134#define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */ 135#define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ 136#define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */ 137#define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */ 138#define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */ 139#define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */ 140#define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */ 141#define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */ 142#define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */ 143#define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */ 144#define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */ 145#define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */ 146 147enum memac_counters { 148 E_MEMAC_COUNTER_R64, 149 E_MEMAC_COUNTER_R127, 150 E_MEMAC_COUNTER_R255, 151 E_MEMAC_COUNTER_R511, 152 E_MEMAC_COUNTER_R1023, 153 E_MEMAC_COUNTER_R1518, 154 E_MEMAC_COUNTER_R1519X, 155 E_MEMAC_COUNTER_RFRG, 156 E_MEMAC_COUNTER_RJBR, 157 E_MEMAC_COUNTER_RDRP, 158 E_MEMAC_COUNTER_RALN, 159 E_MEMAC_COUNTER_TUND, 160 E_MEMAC_COUNTER_ROVR, 161 E_MEMAC_COUNTER_RXPF, 162 E_MEMAC_COUNTER_TXPF, 163 E_MEMAC_COUNTER_ROCT, 164 E_MEMAC_COUNTER_RMCA, 165 E_MEMAC_COUNTER_RBCA, 166 E_MEMAC_COUNTER_RPKT, 167 E_MEMAC_COUNTER_RUCA, 168 E_MEMAC_COUNTER_RERR, 169 E_MEMAC_COUNTER_TOCT, 170 E_MEMAC_COUNTER_TMCA, 171 E_MEMAC_COUNTER_TBCA, 172 E_MEMAC_COUNTER_TUCA, 173 E_MEMAC_COUNTER_TERR 174}; 175 176#define DEFAULT_PAUSE_QUANTA 0xf000 177#define DEFAULT_FRAME_LENGTH 0x600 178#define DEFAULT_TX_IPG_LENGTH 12 179 180/* 181 * memory map 182 */ 183 184struct mac_addr { 185 uint32_t mac_addr_l; /* Lower 32 bits of 48-bit MAC address */ 186 uint32_t mac_addr_u; /* Upper 16 bits of 48-bit MAC address */ 187}; 188 189struct memac_regs { 190 /* General Control and Status */ 191 uint32_t res0000[2]; 192 uint32_t command_config; /* 0x008 Ctrl and cfg */ 193 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */ 194 uint32_t maxfrm; /* 0x014 Max frame length */ 195 uint32_t res0018[1]; 196 uint32_t rx_fifo_sections; /* Receive FIFO configuration reg */ 197 uint32_t tx_fifo_sections; /* Transmit FIFO configuration reg */ 198 uint32_t res0024[2]; 199 uint32_t hashtable_ctrl; /* 0x02C Hash table control */ 200 uint32_t res0030[4]; 201 uint32_t ievent; /* 0x040 Interrupt event */ 202 uint32_t tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */ 203 uint32_t res0048; 204 uint32_t imask; /* 0x04C Interrupt mask */ 205 uint32_t res0050; 206 uint32_t pause_quanta[4]; /* 0x054 Pause quanta */ 207 uint32_t pause_thresh[4]; /* 0x064 Pause quanta threshold */ 208 uint32_t rx_pause_status; /* 0x074 Receive pause status */ 209 uint32_t res0078[2]; 210 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS]; /* 0x80-0x0B4 mac padr */ 211 uint32_t lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */ 212 uint32_t sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */ 213 uint32_t res00c0[8]; 214 uint32_t statn_config; /* 0x0E0 Statistics configuration */ 215 uint32_t res00e4[7]; 216 /* Rx Statistics Counter */ 217 uint32_t reoct_l; 218 uint32_t reoct_u; 219 uint32_t roct_l; 220 uint32_t roct_u; 221 uint32_t raln_l; 222 uint32_t raln_u; 223 uint32_t rxpf_l; 224 uint32_t rxpf_u; 225 uint32_t rfrm_l; 226 uint32_t rfrm_u; 227 uint32_t rfcs_l; 228 uint32_t rfcs_u; 229 uint32_t rvlan_l; 230 uint32_t rvlan_u; 231 uint32_t rerr_l; 232 uint32_t rerr_u; 233 uint32_t ruca_l; 234 uint32_t ruca_u; 235 uint32_t rmca_l; 236 uint32_t rmca_u; 237 uint32_t rbca_l; 238 uint32_t rbca_u; 239 uint32_t rdrp_l; 240 uint32_t rdrp_u; 241 uint32_t rpkt_l; 242 uint32_t rpkt_u; 243 uint32_t rund_l; 244 uint32_t rund_u; 245 uint32_t r64_l; 246 uint32_t r64_u; 247 uint32_t r127_l; 248 uint32_t r127_u; 249 uint32_t r255_l; 250 uint32_t r255_u; 251 uint32_t r511_l; 252 uint32_t r511_u; 253 uint32_t r1023_l; 254 uint32_t r1023_u; 255 uint32_t r1518_l; 256 uint32_t r1518_u; 257 uint32_t r1519x_l; 258 uint32_t r1519x_u; 259 uint32_t rovr_l; 260 uint32_t rovr_u; 261 uint32_t rjbr_l; 262 uint32_t rjbr_u; 263 uint32_t rfrg_l; 264 uint32_t rfrg_u; 265 uint32_t rcnp_l; 266 uint32_t rcnp_u; 267 uint32_t rdrntp_l; 268 uint32_t rdrntp_u; 269 uint32_t res01d0[12]; 270 /* Tx Statistics Counter */ 271 uint32_t teoct_l; 272 uint32_t teoct_u; 273 uint32_t toct_l; 274 uint32_t toct_u; 275 uint32_t res0210[2]; 276 uint32_t txpf_l; 277 uint32_t txpf_u; 278 uint32_t tfrm_l; 279 uint32_t tfrm_u; 280 uint32_t tfcs_l; 281 uint32_t tfcs_u; 282 uint32_t tvlan_l; 283 uint32_t tvlan_u; 284 uint32_t terr_l; 285 uint32_t terr_u; 286 uint32_t tuca_l; 287 uint32_t tuca_u; 288 uint32_t tmca_l; 289 uint32_t tmca_u; 290 uint32_t tbca_l; 291 uint32_t tbca_u; 292 uint32_t res0258[2]; 293 uint32_t tpkt_l; 294 uint32_t tpkt_u; 295 uint32_t tund_l; 296 uint32_t tund_u; 297 uint32_t t64_l; 298 uint32_t t64_u; 299 uint32_t t127_l; 300 uint32_t t127_u; 301 uint32_t t255_l; 302 uint32_t t255_u; 303 uint32_t t511_l; 304 uint32_t t511_u; 305 uint32_t t1023_l; 306 uint32_t t1023_u; 307 uint32_t t1518_l; 308 uint32_t t1518_u; 309 uint32_t t1519x_l; 310 uint32_t t1519x_u; 311 uint32_t res02a8[6]; 312 uint32_t tcnp_l; 313 uint32_t tcnp_u; 314 uint32_t res02c8[14]; 315 /* Line Interface Control */ 316 uint32_t if_mode; /* 0x300 Interface Mode Control */ 317 uint32_t if_status; /* 0x304 Interface Status */ 318 uint32_t res0308[14]; 319 /* HiGig/2 */ 320 uint32_t hg_config; /* 0x340 Control and cfg */ 321 uint32_t res0344[3]; 322 uint32_t hg_pause_quanta; /* 0x350 Pause quanta */ 323 uint32_t res0354[3]; 324 uint32_t hg_pause_thresh; /* 0x360 Pause quanta threshold */ 325 uint32_t res0364[3]; 326 uint32_t hgrx_pause_status; /* 0x370 Receive pause status */ 327 uint32_t hg_fifos_status; /* 0x374 fifos status */ 328 uint32_t rhm; /* 0x378 rx messages counter */ 329 uint32_t thm; /* 0x37C tx messages counter */ 330}; 331 332struct memac_cfg { 333 bool reset_on_init; 334 bool rx_error_discard; 335 bool pause_ignore; 336 bool pause_forward_enable; 337 bool no_length_check_enable; 338 bool cmd_frame_enable; 339 bool send_idle_enable; 340 bool wan_mode_enable; 341 bool promiscuous_mode_enable; 342 bool tx_addr_ins_enable; 343 bool loopback_enable; 344 bool lgth_check_nostdr; 345 bool time_stamp_enable; 346 bool pad_enable; 347 bool phy_tx_ena_on; 348 bool rx_sfd_any; 349 bool rx_pbl_fwd; 350 bool tx_pbl_fwd; 351 bool debug_mode; 352 bool wake_on_lan; 353 uint16_t max_frame_length; 354 uint16_t pause_quanta; 355 uint32_t tx_ipg_length; 356}; 357 358 359/** 360 * fman_memac_defconfig() - Get default MEMAC configuration 361 * @cfg: pointer to configuration structure. 362 * 363 * Call this function to obtain a default set of configuration values for 364 * initializing MEMAC. The user can overwrite any of the values before calling 365 * fman_memac_init(), if specific configuration needs to be applied. 366 */ 367void fman_memac_defconfig(struct memac_cfg *cfg); 368 369int fman_memac_init(struct memac_regs *regs, 370 struct memac_cfg *cfg, 371 enum enet_interface enet_interface, 372 enum enet_speed enet_speed, 373 bool slow_10g_if, 374 uint32_t exceptions); 375 376void fman_memac_enable(struct memac_regs *regs, bool apply_rx, bool apply_tx); 377 378void fman_memac_disable(struct memac_regs *regs, bool apply_rx, bool apply_tx); 379 380void fman_memac_set_promiscuous(struct memac_regs *regs, bool val); 381 382void fman_memac_add_addr_in_paddr(struct memac_regs *regs, 383 uint8_t *adr, 384 uint8_t paddr_num); 385 386void fman_memac_clear_addr_in_paddr(struct memac_regs *regs, 387 uint8_t paddr_num); 388 389uint64_t fman_memac_get_counter(struct memac_regs *regs, 390 enum memac_counters reg_name); 391 392void fman_memac_set_tx_pause_frames(struct memac_regs *regs, 393 uint8_t priority, uint16_t pauseTime, uint16_t threshTime); 394 395uint16_t fman_memac_get_max_frame_len(struct memac_regs *regs); 396 397void fman_memac_set_exception(struct memac_regs *regs, uint32_t val, 398 bool enable); 399 400void fman_memac_reset_stat(struct memac_regs *regs); 401 402void fman_memac_reset(struct memac_regs *regs); 403 404void fman_memac_reset_filter_table(struct memac_regs *regs); 405 406void fman_memac_set_hash_table_entry(struct memac_regs *regs, uint32_t crc); 407 408void fman_memac_set_hash_table(struct memac_regs *regs, uint32_t val); 409 410void fman_memac_set_rx_ignore_pause_frames(struct memac_regs *regs, 411 bool enable); 412 413void fman_memac_set_wol(struct memac_regs *regs, bool enable); 414 415uint32_t fman_memac_get_event(struct memac_regs *regs, uint32_t ev_mask); 416 417void fman_memac_ack_event(struct memac_regs *regs, uint32_t ev_mask); 418 419uint32_t fman_memac_get_interrupt_mask(struct memac_regs *regs); 420 421void fman_memac_adjust_link(struct memac_regs *regs, 422 enum enet_interface iface_mode, 423 enum enet_speed speed, bool full_dx); 424 425 426 427#endif /*__FSL_FMAN_MEMAC_H*/ 428