1/*
2 * Copyright 2008-2012 Freescale Semiconductor Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *     * Redistributions of source code must retain the above copyright
7 *       notice, this list of conditions and the following disclaimer.
8 *     * Redistributions in binary form must reproduce the above copyright
9 *       notice, this list of conditions and the following disclaimer in the
10 *       documentation and/or other materials provided with the distribution.
11 *     * Neither the name of Freescale Semiconductor nor the
12 *       names of its contributors may be used to endorse or promote products
13 *       derived from this software without specific prior written permission.
14 *
15 *
16 * ALTERNATIVELY, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") as published by the Free Software
18 * Foundation, either version 2 of that License or (at your option) any
19 * later version.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33
34/**************************************************************************//**
35 @File          core_ext.h
36
37 @Description   Generic interface to basic core operations.
38
39                The system integrator must ensure that this interface is
40                mapped to a specific core implementation, by including the
41                appropriate header file.
42*//***************************************************************************/
43#ifndef __CORE_EXT_H
44#define __CORE_EXT_H
45
46#ifdef CONFIG_FMAN_ARM
47#include "arm_ext.h"
48#include <linux/smp.h>
49#else
50#ifdef NCSW_PPC_CORE
51#include "ppc_ext.h"
52#elif defined(NCSW_VXWORKS)
53#include "core_vxw_ext.h"
54#else
55#error "Core is not defined!"
56#endif /* NCSW_CORE */
57
58#if (!defined(CORE_IS_LITTLE_ENDIAN) && !defined(CORE_IS_BIG_ENDIAN))
59#error "Must define core as little-endian or big-endian!"
60#endif /* (!defined(CORE_IS_LITTLE_ENDIAN) && ... */
61
62#ifndef CORE_CACHELINE_SIZE
63#error "Must define the core cache-line size!"
64#endif /* !CORE_CACHELINE_SIZE */
65
66#endif /* CONFIG_FMAN_ARM */
67
68
69/**************************************************************************//**
70 @Function      CORE_GetId
71
72 @Description   Returns the core ID in the system.
73
74 @Return        Core ID.
75*//***************************************************************************/
76uint32_t CORE_GetId(void);
77
78/**************************************************************************//**
79 @Function      CORE_MemoryBarrier
80
81 @Description   This routine will cause the core to stop executing any commands
82                until all previous memory read/write commands are completely out
83                of the core's pipeline.
84
85 @Return        None.
86*//***************************************************************************/
87void CORE_MemoryBarrier(void);
88#define fsl_mem_core_barrier() CORE_MemoryBarrier()
89
90#endif /* __CORE_EXT_H */
91