1/*
2 * Copyright 2008-2012 Freescale Semiconductor Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *     * Redistributions of source code must retain the above copyright
7 *       notice, this list of conditions and the following disclaimer.
8 *     * Redistributions in binary form must reproduce the above copyright
9 *       notice, this list of conditions and the following disclaimer in the
10 *       documentation and/or other materials provided with the distribution.
11 *     * Neither the name of Freescale Semiconductor nor the
12 *       names of its contributors may be used to endorse or promote products
13 *       derived from this software without specific prior written permission.
14 *
15 *
16 * ALTERNATIVELY, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") as published by the Free Software
18 * Foundation, either version 2 of that License or (at your option) any
19 * later version.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33
34
35#include "error_ext.h"
36#include "std_ext.h"
37#include "fm_mac.h"
38#include "tgec.h"
39#include "xx_ext.h"
40
41#include "fm_common.h"
42
43
44/*****************************************************************************/
45t_Error TGEC_MII_WritePhyReg(t_Handle   h_Tgec,
46                             uint8_t    phyAddr,
47                             uint8_t    reg,
48                             uint16_t   data)
49{
50    t_Tgec                  *p_Tgec = (t_Tgec *)h_Tgec;
51    t_TgecMiiAccessMemMap   *p_MiiAccess;
52    uint32_t                cfgStatusReg;
53
54    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
55    SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
56
57    p_MiiAccess = p_Tgec->p_MiiMemMap;
58
59    /* Configure MII */
60    cfgStatusReg  = GET_UINT32(p_MiiAccess->mdio_cfg_status);
61    cfgStatusReg &= ~MIIMCOM_DIV_MASK;
62     /* (one half of fm clock => 2.5Mhz) */
63    cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT);
64    WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg);
65
66    while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
67        XX_UDelay (1);
68
69    WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
70
71    WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
72
73    CORE_MemoryBarrier();
74
75    while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
76        XX_UDelay (1);
77
78    WRITE_UINT32(p_MiiAccess->mdio_data, data);
79
80    CORE_MemoryBarrier();
81
82    while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
83        XX_UDelay (1);
84
85    return E_OK;
86}
87
88/*****************************************************************************/
89t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec,
90                            uint8_t  phyAddr,
91                            uint8_t  reg,
92                            uint16_t *p_Data)
93{
94    t_Tgec                  *p_Tgec = (t_Tgec *)h_Tgec;
95    t_TgecMiiAccessMemMap   *p_MiiAccess;
96    uint32_t                cfgStatusReg;
97
98    SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
99    SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
100
101    p_MiiAccess = p_Tgec->p_MiiMemMap;
102
103    /* Configure MII */
104    cfgStatusReg  = GET_UINT32(p_MiiAccess->mdio_cfg_status);
105    cfgStatusReg &= ~MIIMCOM_DIV_MASK;
106     /* (one half of fm clock => 2.5Mhz) */
107    cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT);
108    WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg);
109
110    while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
111        XX_UDelay (1);
112
113    WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
114
115    WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
116
117    CORE_MemoryBarrier();
118
119    while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
120        XX_UDelay (1);
121
122    WRITE_UINT32(p_MiiAccess->mdio_command, (uint32_t)(phyAddr | MIIMCOM_READ_CYCLE));
123
124    CORE_MemoryBarrier();
125
126    while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
127        XX_UDelay (1);
128
129    *p_Data =  (uint16_t)GET_UINT32(p_MiiAccess->mdio_data);
130
131    cfgStatusReg  = GET_UINT32(p_MiiAccess->mdio_cfg_status);
132
133    if (cfgStatusReg & MIIMIND_READ_ERROR)
134        RETURN_ERROR(MINOR, E_INVALID_VALUE,
135                     ("Read Error: phyAddr 0x%x, dev 0x%x, reg 0x%x, cfgStatusReg 0x%x",
136                      ((phyAddr & 0xe0)>>5), (phyAddr & 0x1f), reg, cfgStatusReg));
137
138    return E_OK;
139}
140