1/******************************************************************************
2
3 � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
4 All rights reserved.
5
6 This is proprietary source code of Freescale Semiconductor Inc.,
7 and its use is subject to the NetComm Device Drivers EULA.
8 The copyright notice above does not evidence any actual or intended
9 publication of such source code.
10
11 ALTERNATIVELY, redistribution and use in source and binary forms, with
12 or without modification, are permitted provided that the following
13 conditions are met:
14     * Redistributions of source code must retain the above copyright
15       notice, this list of conditions and the following disclaimer.
16     * Redistributions in binary form must reproduce the above copyright
17       notice, this list of conditions and the following disclaimer in the
18       documentation and/or other materials provided with the distribution.
19     * Neither the name of Freescale Semiconductor nor the
20       names of its contributors may be used to endorse or promote products
21       derived from this software without specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34
35 **************************************************************************/
36/******************************************************************************
37 @File          bman_private.h
38
39 @Description   BM header
40*//***************************************************************************/
41#ifndef __BMAN_PRIV_H
42#define __BMAN_PRIV_H
43
44#include "fsl_bman.h"
45
46#define __ERR_MODULE__  MODULE_BM
47
48#if defined(DEBUG) || !defined(DISABLE_ASSERTIONS)
49/* Optionally compile-in assertion-checking */
50#define BM_CHECKING
51#endif /* defined(DEBUG) || ... */
52
53/* TODO: NB, we currently assume that CORE_MemoryBarier() and lwsync() imply compiler barriers
54 * and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or
55 * execution reordering with respect to other code/instructions that manipulate
56 * the same cacheline. */
57
58#define dcbf(addr)  \
59    do { \
60        __asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \
61    } while(0)
62
63#ifdef CORE_E500MC
64#define dcbt_ro(addr)   \
65    do { \
66        __asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \
67    } while(0)
68
69#define dcbt_rw(addr)   \
70    do { \
71        __asm__ __volatile__ ("dcbtst 0, %0" : : "r" (addr)); \
72    } while(0)
73
74#define dcbzl(p) \
75    do { \
76        __asm__ __volatile__ ("dcbzl 0,%0" : : "r" (p)); \
77    } while(0)
78
79#define dcbz_64(p) \
80    do { \
81        dcbzl(p); \
82    } while (0)
83
84#define dcbf_64(p) \
85    do { \
86        dcbf(p); \
87    } while (0)
88
89/* Commonly used combo */
90#define dcbit_ro(p) \
91    do { \
92        dcbi(p); \
93        dcbt_ro(p); \
94    } while (0)
95
96#else
97
98#define dcbt_ro(p) \
99    do { \
100        __asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \
101        lwsync(); \
102    } while(0)
103#define dcbz(p) \
104    do { \
105        __asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)); \
106    } while (0)
107#define dcbz_64(p) \
108    do { \
109        dcbz((char *)p + 32); \
110        dcbz(p);    \
111    } while (0)
112#define dcbf_64(p) \
113    do { \
114        dcbf((char *)p + 32); \
115        dcbf(p); \
116    } while (0)
117/* Commonly used combo */
118#define dcbit_ro(p) \
119    do { \
120        dcbi(p); \
121        dcbi((char *)p + 32); \
122        dcbt_ro(p); \
123        dcbt_ro((char *)p + 32); \
124    } while (0)
125
126#endif /* CORE_E500MC */
127
128#define dcbi(p) dcbf(p)
129
130struct bm_addr {
131    void  *addr_ce;    /* cache-enabled */
132    void  *addr_ci;    /* cache-inhibited */
133};
134
135/* RCR state */
136struct bm_rcr {
137    struct bm_rcr_entry *ring, *cursor;
138    uint8_t ci, available, ithresh, vbit;
139#ifdef BM_CHECKING
140    uint32_t busy;
141    e_BmPortalProduceMode pmode;
142    e_BmPortalRcrConsumeMode cmode;
143#endif /* BM_CHECKING */
144};
145
146/* MC state */
147struct bm_mc {
148    struct bm_mc_command *cr;
149    struct bm_mc_result *rr;
150    uint8_t rridx, vbit;
151#ifdef BM_CHECKING
152    enum {
153        /* Can only be _mc_start()ed */
154        mc_idle,
155        /* Can only be _mc_commit()ed or _mc_abort()ed */
156        mc_user,
157        /* Can only be _mc_retry()ed */
158        mc_hw
159    } state;
160#endif /* BM_CHECKING */
161};
162
163/********************/
164/* Portal structure */
165/********************/
166
167struct bm_portal {
168    struct bm_addr addr;
169    struct bm_rcr rcr;
170    struct bm_mc mc;
171};
172
173
174#endif /* __BMAN_PRIV_H */
175