1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33#ifndef _ENA_ETH_IO_H_ 34#define _ENA_ETH_IO_H_ 35 36enum ena_eth_io_l3_proto_index { 37 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0, 38 ENA_ETH_IO_L3_PROTO_IPV4 = 8, 39 ENA_ETH_IO_L3_PROTO_IPV6 = 11, 40 ENA_ETH_IO_L3_PROTO_FCOE = 21, 41 ENA_ETH_IO_L3_PROTO_ROCE = 22, 42}; 43 44enum ena_eth_io_l4_proto_index { 45 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0, 46 ENA_ETH_IO_L4_PROTO_TCP = 12, 47 ENA_ETH_IO_L4_PROTO_UDP = 13, 48 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23, 49}; 50 51struct ena_eth_io_tx_desc { 52 /* 15:0 : length - Buffer length in bytes, must 53 * include any packet trailers that the ENA supposed 54 * to update like End-to-End CRC, Authentication GMAC 55 * etc. This length must not include the 56 * 'Push_Buffer' length. This length must not include 57 * the 4-byte added in the end for 802.3 Ethernet FCS 58 * 21:16 : req_id_hi - Request ID[15:10] 59 * 22 : reserved22 - MBZ 60 * 23 : meta_desc - MBZ 61 * 24 : phase 62 * 25 : reserved1 - MBZ 63 * 26 : first - Indicates first descriptor in 64 * transaction 65 * 27 : last - Indicates last descriptor in 66 * transaction 67 * 28 : comp_req - Indicates whether completion 68 * should be posted, after packet is transmitted. 69 * Valid only for first descriptor 70 * 30:29 : reserved29 - MBZ 71 * 31 : reserved31 - MBZ 72 */ 73 uint32_t len_ctrl; 74 75 /* 3:0 : l3_proto_idx - L3 protocol. This field 76 * required when l3_csum_en,l3_csum or tso_en are set. 77 * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and 78 * DF flags of the IPv4 header is 0. Otherwise must 79 * be set to 1 80 * 6:5 : reserved5 81 * 7 : tso_en - Enable TSO, For TCP only. 82 * 12:8 : l4_proto_idx - L4 protocol. This field need 83 * to be set when l4_csum_en or tso_en are set. 84 * 13 : l3_csum_en - enable IPv4 header checksum. 85 * 14 : l4_csum_en - enable TCP/UDP checksum. 86 * 15 : ethernet_fcs_dis - when set, the controller 87 * will not append the 802.3 Ethernet Frame Check 88 * Sequence to the packet 89 * 16 : reserved16 90 * 17 : l4_csum_partial - L4 partial checksum. when 91 * set to 0, the ENA calculates the L4 checksum, 92 * where the Destination Address required for the 93 * TCP/UDP pseudo-header is taken from the actual 94 * packet L3 header. when set to 1, the ENA doesn't 95 * calculate the sum of the pseudo-header, instead, 96 * the checksum field of the L4 is used instead. When 97 * TSO enabled, the checksum of the pseudo-header 98 * must not include the tcp length field. L4 partial 99 * checksum should be used for IPv6 packet that 100 * contains Routing Headers. 101 * 20:18 : reserved18 - MBZ 102 * 21 : reserved21 - MBZ 103 * 31:22 : req_id_lo - Request ID[9:0] 104 */ 105 uint32_t meta_ctrl; 106 107 uint32_t buff_addr_lo; 108 109 /* address high and header size 110 * 15:0 : addr_hi - Buffer Pointer[47:32] 111 * 23:16 : reserved16_w2 112 * 31:24 : header_length - Header length. For Low 113 * Latency Queues, this fields indicates the number 114 * of bytes written to the headers' memory. For 115 * normal queues, if packet is TCP or UDP, and longer 116 * than max_header_size, then this field should be 117 * set to the sum of L4 header offset and L4 header 118 * size(without options), otherwise, this field 119 * should be set to 0. For both modes, this field 120 * must not exceed the max_header_size. 121 * max_header_size value is reported by the Max 122 * Queues Feature descriptor 123 */ 124 uint32_t buff_addr_hi_hdr_sz; 125}; 126 127struct ena_eth_io_tx_meta_desc { 128 /* 9:0 : req_id_lo - Request ID[9:0] 129 * 11:10 : reserved10 - MBZ 130 * 12 : reserved12 - MBZ 131 * 13 : reserved13 - MBZ 132 * 14 : ext_valid - if set, offset fields in Word2 133 * are valid Also MSS High in Word 0 and bits [31:24] 134 * in Word 3 135 * 15 : reserved15 136 * 19:16 : mss_hi 137 * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1: 138 * Extended Metadata Descriptor 139 * 21 : meta_store - Store extended metadata in queue 140 * cache 141 * 22 : reserved22 - MBZ 142 * 23 : meta_desc - MBO 143 * 24 : phase 144 * 25 : reserved25 - MBZ 145 * 26 : first - Indicates first descriptor in 146 * transaction 147 * 27 : last - Indicates last descriptor in 148 * transaction 149 * 28 : comp_req - Indicates whether completion 150 * should be posted, after packet is transmitted. 151 * Valid only for first descriptor 152 * 30:29 : reserved29 - MBZ 153 * 31 : reserved31 - MBZ 154 */ 155 uint32_t len_ctrl; 156 157 /* 5:0 : req_id_hi 158 * 31:6 : reserved6 - MBZ 159 */ 160 uint32_t word1; 161 162 /* 7:0 : l3_hdr_len 163 * 15:8 : l3_hdr_off 164 * 21:16 : l4_hdr_len_in_words - counts the L4 header 165 * length in words. there is an explicit assumption 166 * that L4 header appears right after L3 header and 167 * L4 offset is based on l3_hdr_off+l3_hdr_len 168 * 31:22 : mss_lo 169 */ 170 uint32_t word2; 171 172 uint32_t reserved; 173}; 174 175struct ena_eth_io_tx_cdesc { 176 /* Request ID[15:0] */ 177 uint16_t req_id; 178 179 uint8_t status; 180 181 /* flags 182 * 0 : phase 183 * 7:1 : reserved1 184 */ 185 uint8_t flags; 186 187 uint16_t sub_qid; 188 189 uint16_t sq_head_idx; 190}; 191 192struct ena_eth_io_rx_desc { 193 /* In bytes. 0 means 64KB */ 194 uint16_t length; 195 196 /* MBZ */ 197 uint8_t reserved2; 198 199 /* 0 : phase 200 * 1 : reserved1 - MBZ 201 * 2 : first - Indicates first descriptor in 202 * transaction 203 * 3 : last - Indicates last descriptor in transaction 204 * 4 : comp_req 205 * 5 : reserved5 - MBO 206 * 7:6 : reserved6 - MBZ 207 */ 208 uint8_t ctrl; 209 210 uint16_t req_id; 211 212 /* MBZ */ 213 uint16_t reserved6; 214 215 uint32_t buff_addr_lo; 216 217 uint16_t buff_addr_hi; 218 219 /* MBZ */ 220 uint16_t reserved16_w3; 221}; 222 223/* 4-word format Note: all ethernet parsing information are valid only when 224 * last=1 225 */ 226struct ena_eth_io_rx_cdesc_base { 227 /* 4:0 : l3_proto_idx 228 * 6:5 : src_vlan_cnt 229 * 7 : reserved7 - MBZ 230 * 12:8 : l4_proto_idx 231 * 13 : l3_csum_err - when set, either the L3 232 * checksum error detected, or, the controller didn't 233 * validate the checksum. This bit is valid only when 234 * l3_proto_idx indicates IPv4 packet 235 * 14 : l4_csum_err - when set, either the L4 236 * checksum error detected, or, the controller didn't 237 * validate the checksum. This bit is valid only when 238 * l4_proto_idx indicates TCP/UDP packet, and, 239 * ipv4_frag is not set. This bit is valid only when 240 * l4_csum_checked below is set. 241 * 15 : ipv4_frag - Indicates IPv4 fragmented packet 242 * 16 : l4_csum_checked - L4 checksum was verified 243 * (could be OK or error), when cleared the status of 244 * checksum is unknown 245 * 23:17 : reserved17 - MBZ 246 * 24 : phase 247 * 25 : l3_csum2 - second checksum engine result 248 * 26 : first - Indicates first descriptor in 249 * transaction 250 * 27 : last - Indicates last descriptor in 251 * transaction 252 * 29:28 : reserved28 253 * 30 : buffer - 0: Metadata descriptor. 1: Buffer 254 * Descriptor was used 255 * 31 : reserved31 256 */ 257 uint32_t status; 258 259 uint16_t length; 260 261 uint16_t req_id; 262 263 /* 32-bit hash result */ 264 uint32_t hash; 265 266 uint16_t sub_qid; 267 268 uint8_t offset; 269 270 uint8_t reserved; 271}; 272 273/* 8-word format */ 274struct ena_eth_io_rx_cdesc_ext { 275 struct ena_eth_io_rx_cdesc_base base; 276 277 uint32_t buff_addr_lo; 278 279 uint16_t buff_addr_hi; 280 281 uint16_t reserved16; 282 283 uint32_t reserved_w6; 284 285 uint32_t reserved_w7; 286}; 287 288struct ena_eth_io_intr_reg { 289 /* 14:0 : rx_intr_delay 290 * 29:15 : tx_intr_delay 291 * 30 : intr_unmask 292 * 31 : reserved 293 */ 294 uint32_t intr_control; 295}; 296 297struct ena_eth_io_numa_node_cfg_reg { 298 /* 7:0 : numa 299 * 30:8 : reserved 300 * 31 : enabled 301 */ 302 uint32_t numa_cfg; 303}; 304 305/* tx_desc */ 306#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0) 307#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16 308#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16) 309#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23 310#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23) 311#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24 312#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24) 313#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26 314#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26) 315#define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27 316#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27) 317#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28 318#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28) 319#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0) 320#define ENA_ETH_IO_TX_DESC_DF_SHIFT 4 321#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4) 322#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7 323#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7) 324#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8 325#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8) 326#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13 327#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13) 328#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14 329#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14) 330#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15 331#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15) 332#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17 333#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17) 334#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22 335#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22) 336#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0) 337#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24 338#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24) 339 340/* tx_meta_desc */ 341#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0) 342#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14 343#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14) 344#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16 345#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16) 346#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20 347#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20) 348#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21 349#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21) 350#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23 351#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23) 352#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24 353#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24) 354#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26 355#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26) 356#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27 357#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27) 358#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28 359#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28) 360#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0) 361#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0) 362#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8 363#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8) 364#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16 365#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16) 366#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22 367#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22) 368 369/* tx_cdesc */ 370#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) 371 372/* rx_desc */ 373#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) 374#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2 375#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2) 376#define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3 377#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3) 378#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4 379#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4) 380 381/* rx_cdesc_base */ 382#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0) 383#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5 384#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5) 385#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8 386#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8) 387#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13 388#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13) 389#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14 390#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14) 391#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15 392#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15) 393#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16 394#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16) 395#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24 396#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24) 397#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25 398#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25) 399#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26 400#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26) 401#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27 402#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27) 403#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30 404#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30) 405 406/* intr_reg */ 407#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0) 408#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15 409#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15) 410#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30 411#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30) 412 413/* numa_node_cfg_reg */ 414#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0) 415#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31 416#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31) 417 418#if !defined(DEFS_LINUX_MAINLINE) 419static inline uint32_t get_ena_eth_io_tx_desc_length(const struct ena_eth_io_tx_desc *p) 420{ 421 return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK; 422} 423 424static inline void set_ena_eth_io_tx_desc_length(struct ena_eth_io_tx_desc *p, uint32_t val) 425{ 426 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK; 427} 428 429static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(const struct ena_eth_io_tx_desc *p) 430{ 431 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT; 432} 433 434static inline void set_ena_eth_io_tx_desc_req_id_hi(struct ena_eth_io_tx_desc *p, uint32_t val) 435{ 436 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK; 437} 438 439static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(const struct ena_eth_io_tx_desc *p) 440{ 441 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT; 442} 443 444static inline void set_ena_eth_io_tx_desc_meta_desc(struct ena_eth_io_tx_desc *p, uint32_t val) 445{ 446 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_DESC_META_DESC_MASK; 447} 448 449static inline uint32_t get_ena_eth_io_tx_desc_phase(const struct ena_eth_io_tx_desc *p) 450{ 451 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_DESC_PHASE_SHIFT; 452} 453 454static inline void set_ena_eth_io_tx_desc_phase(struct ena_eth_io_tx_desc *p, uint32_t val) 455{ 456 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_DESC_PHASE_MASK; 457} 458 459static inline uint32_t get_ena_eth_io_tx_desc_first(const struct ena_eth_io_tx_desc *p) 460{ 461 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_DESC_FIRST_SHIFT; 462} 463 464static inline void set_ena_eth_io_tx_desc_first(struct ena_eth_io_tx_desc *p, uint32_t val) 465{ 466 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_DESC_FIRST_MASK; 467} 468 469static inline uint32_t get_ena_eth_io_tx_desc_last(const struct ena_eth_io_tx_desc *p) 470{ 471 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK) >> ENA_ETH_IO_TX_DESC_LAST_SHIFT; 472} 473 474static inline void set_ena_eth_io_tx_desc_last(struct ena_eth_io_tx_desc *p, uint32_t val) 475{ 476 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_DESC_LAST_MASK; 477} 478 479static inline uint32_t get_ena_eth_io_tx_desc_comp_req(const struct ena_eth_io_tx_desc *p) 480{ 481 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT; 482} 483 484static inline void set_ena_eth_io_tx_desc_comp_req(struct ena_eth_io_tx_desc *p, uint32_t val) 485{ 486 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK; 487} 488 489static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(const struct ena_eth_io_tx_desc *p) 490{ 491 return p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; 492} 493 494static inline void set_ena_eth_io_tx_desc_l3_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val) 495{ 496 p->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; 497} 498 499static inline uint32_t get_ena_eth_io_tx_desc_DF(const struct ena_eth_io_tx_desc *p) 500{ 501 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK) >> ENA_ETH_IO_TX_DESC_DF_SHIFT; 502} 503 504static inline void set_ena_eth_io_tx_desc_DF(struct ena_eth_io_tx_desc *p, uint32_t val) 505{ 506 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_DF_SHIFT) & ENA_ETH_IO_TX_DESC_DF_MASK; 507} 508 509static inline uint32_t get_ena_eth_io_tx_desc_tso_en(const struct ena_eth_io_tx_desc *p) 510{ 511 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK) >> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT; 512} 513 514static inline void set_ena_eth_io_tx_desc_tso_en(struct ena_eth_io_tx_desc *p, uint32_t val) 515{ 516 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) & ENA_ETH_IO_TX_DESC_TSO_EN_MASK; 517} 518 519static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(const struct ena_eth_io_tx_desc *p) 520{ 521 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT; 522} 523 524static inline void set_ena_eth_io_tx_desc_l4_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val) 525{ 526 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK; 527} 528 529static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(const struct ena_eth_io_tx_desc *p) 530{ 531 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT; 532} 533 534static inline void set_ena_eth_io_tx_desc_l3_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val) 535{ 536 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK; 537} 538 539static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(const struct ena_eth_io_tx_desc *p) 540{ 541 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT; 542} 543 544static inline void set_ena_eth_io_tx_desc_l4_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val) 545{ 546 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK; 547} 548 549static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(const struct ena_eth_io_tx_desc *p) 550{ 551 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK) >> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT; 552} 553 554static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(struct ena_eth_io_tx_desc *p, uint32_t val) 555{ 556 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT) & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK; 557} 558 559static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(const struct ena_eth_io_tx_desc *p) 560{ 561 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT; 562} 563 564static inline void set_ena_eth_io_tx_desc_l4_csum_partial(struct ena_eth_io_tx_desc *p, uint32_t val) 565{ 566 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK; 567} 568 569static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(const struct ena_eth_io_tx_desc *p) 570{ 571 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT; 572} 573 574static inline void set_ena_eth_io_tx_desc_req_id_lo(struct ena_eth_io_tx_desc *p, uint32_t val) 575{ 576 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK; 577} 578 579static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(const struct ena_eth_io_tx_desc *p) 580{ 581 return p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; 582} 583 584static inline void set_ena_eth_io_tx_desc_addr_hi(struct ena_eth_io_tx_desc *p, uint32_t val) 585{ 586 p->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; 587} 588 589static inline uint32_t get_ena_eth_io_tx_desc_header_length(const struct ena_eth_io_tx_desc *p) 590{ 591 return (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK) >> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT; 592} 593 594static inline void set_ena_eth_io_tx_desc_header_length(struct ena_eth_io_tx_desc *p, uint32_t val) 595{ 596 p->buff_addr_hi_hdr_sz |= (val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK; 597} 598 599static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(const struct ena_eth_io_tx_meta_desc *p) 600{ 601 return p->len_ctrl & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; 602} 603 604static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 605{ 606 p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; 607} 608 609static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(const struct ena_eth_io_tx_meta_desc *p) 610{ 611 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK) >> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT; 612} 613 614static inline void set_ena_eth_io_tx_meta_desc_ext_valid(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 615{ 616 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT) & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK; 617} 618 619static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi(const struct ena_eth_io_tx_meta_desc *p) 620{ 621 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT; 622} 623 624static inline void set_ena_eth_io_tx_meta_desc_mss_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 625{ 626 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK; 627} 628 629static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(const struct ena_eth_io_tx_meta_desc *p) 630{ 631 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK) >> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT; 632} 633 634static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 635{ 636 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT) & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK; 637} 638 639static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(const struct ena_eth_io_tx_meta_desc *p) 640{ 641 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK) >> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT; 642} 643 644static inline void set_ena_eth_io_tx_meta_desc_meta_store(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 645{ 646 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK; 647} 648 649static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(const struct ena_eth_io_tx_meta_desc *p) 650{ 651 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT; 652} 653 654static inline void set_ena_eth_io_tx_meta_desc_meta_desc(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 655{ 656 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK; 657} 658 659static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(const struct ena_eth_io_tx_meta_desc *p) 660{ 661 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT; 662} 663 664static inline void set_ena_eth_io_tx_meta_desc_phase(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 665{ 666 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_META_DESC_PHASE_MASK; 667} 668 669static inline uint32_t get_ena_eth_io_tx_meta_desc_first(const struct ena_eth_io_tx_meta_desc *p) 670{ 671 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT; 672} 673 674static inline void set_ena_eth_io_tx_meta_desc_first(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 675{ 676 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_META_DESC_FIRST_MASK; 677} 678 679static inline uint32_t get_ena_eth_io_tx_meta_desc_last(const struct ena_eth_io_tx_meta_desc *p) 680{ 681 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK) >> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT; 682} 683 684static inline void set_ena_eth_io_tx_meta_desc_last(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 685{ 686 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_META_DESC_LAST_MASK; 687} 688 689static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(const struct ena_eth_io_tx_meta_desc *p) 690{ 691 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT; 692} 693 694static inline void set_ena_eth_io_tx_meta_desc_comp_req(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 695{ 696 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK; 697} 698 699static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(const struct ena_eth_io_tx_meta_desc *p) 700{ 701 return p->word1 & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; 702} 703 704static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 705{ 706 p->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; 707} 708 709static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(const struct ena_eth_io_tx_meta_desc *p) 710{ 711 return p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; 712} 713 714static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 715{ 716 p->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; 717} 718 719static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(const struct ena_eth_io_tx_meta_desc *p) 720{ 721 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK) >> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT; 722} 723 724static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 725{ 726 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK; 727} 728 729static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(const struct ena_eth_io_tx_meta_desc *p) 730{ 731 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK) >> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT; 732} 733 734static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 735{ 736 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK; 737} 738 739static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(const struct ena_eth_io_tx_meta_desc *p) 740{ 741 return (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT; 742} 743 744static inline void set_ena_eth_io_tx_meta_desc_mss_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 745{ 746 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK; 747} 748 749static inline uint8_t get_ena_eth_io_tx_cdesc_phase(const struct ena_eth_io_tx_cdesc *p) 750{ 751 return p->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK; 752} 753 754static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p, uint8_t val) 755{ 756 p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK; 757} 758 759static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p) 760{ 761 return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK; 762} 763 764static inline void set_ena_eth_io_rx_desc_phase(struct ena_eth_io_rx_desc *p, uint8_t val) 765{ 766 p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK; 767} 768 769static inline uint8_t get_ena_eth_io_rx_desc_first(const struct ena_eth_io_rx_desc *p) 770{ 771 return (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK) >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT; 772} 773 774static inline void set_ena_eth_io_rx_desc_first(struct ena_eth_io_rx_desc *p, uint8_t val) 775{ 776 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT) & ENA_ETH_IO_RX_DESC_FIRST_MASK; 777} 778 779static inline uint8_t get_ena_eth_io_rx_desc_last(const struct ena_eth_io_rx_desc *p) 780{ 781 return (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK) >> ENA_ETH_IO_RX_DESC_LAST_SHIFT; 782} 783 784static inline void set_ena_eth_io_rx_desc_last(struct ena_eth_io_rx_desc *p, uint8_t val) 785{ 786 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT) & ENA_ETH_IO_RX_DESC_LAST_MASK; 787} 788 789static inline uint8_t get_ena_eth_io_rx_desc_comp_req(const struct ena_eth_io_rx_desc *p) 790{ 791 return (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT; 792} 793 794static inline void set_ena_eth_io_rx_desc_comp_req(struct ena_eth_io_rx_desc *p, uint8_t val) 795{ 796 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK; 797} 798 799static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) 800{ 801 return p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; 802} 803 804static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 805{ 806 p->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; 807} 808 809static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(const struct ena_eth_io_rx_cdesc_base *p) 810{ 811 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT; 812} 813 814static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 815{ 816 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK; 817} 818 819static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) 820{ 821 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT; 822} 823 824static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 825{ 826 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK; 827} 828 829static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(const struct ena_eth_io_rx_cdesc_base *p) 830{ 831 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT; 832} 833 834static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 835{ 836 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK; 837} 838 839static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(const struct ena_eth_io_rx_cdesc_base *p) 840{ 841 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT; 842} 843 844static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 845{ 846 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK; 847} 848 849static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(const struct ena_eth_io_rx_cdesc_base *p) 850{ 851 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT; 852} 853 854static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 855{ 856 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK; 857} 858 859static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_checked(const struct ena_eth_io_rx_cdesc_base *p) 860{ 861 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT; 862} 863 864static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_checked(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 865{ 866 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK; 867} 868 869static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p) 870{ 871 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT; 872} 873 874static inline void set_ena_eth_io_rx_cdesc_base_phase(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 875{ 876 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK; 877} 878 879static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(const struct ena_eth_io_rx_cdesc_base *p) 880{ 881 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT; 882} 883 884static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 885{ 886 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK; 887} 888 889static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(const struct ena_eth_io_rx_cdesc_base *p) 890{ 891 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT; 892} 893 894static inline void set_ena_eth_io_rx_cdesc_base_first(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 895{ 896 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK; 897} 898 899static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(const struct ena_eth_io_rx_cdesc_base *p) 900{ 901 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT; 902} 903 904static inline void set_ena_eth_io_rx_cdesc_base_last(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 905{ 906 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK; 907} 908 909static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(const struct ena_eth_io_rx_cdesc_base *p) 910{ 911 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT; 912} 913 914static inline void set_ena_eth_io_rx_cdesc_base_buffer(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 915{ 916 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK; 917} 918 919static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(const struct ena_eth_io_intr_reg *p) 920{ 921 return p->intr_control & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 922} 923 924static inline void set_ena_eth_io_intr_reg_rx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val) 925{ 926 p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 927} 928 929static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(const struct ena_eth_io_intr_reg *p) 930{ 931 return (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK) >> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT; 932} 933 934static inline void set_ena_eth_io_intr_reg_tx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val) 935{ 936 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; 937} 938 939static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(const struct ena_eth_io_intr_reg *p) 940{ 941 return (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK) >> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT; 942} 943 944static inline void set_ena_eth_io_intr_reg_intr_unmask(struct ena_eth_io_intr_reg *p, uint32_t val) 945{ 946 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT) & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; 947} 948 949static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(const struct ena_eth_io_numa_node_cfg_reg *p) 950{ 951 return p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK; 952} 953 954static inline void set_ena_eth_io_numa_node_cfg_reg_numa(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val) 955{ 956 p->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK; 957} 958 959static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(const struct ena_eth_io_numa_node_cfg_reg *p) 960{ 961 return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK) >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT; 962} 963 964static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val) 965{ 966 p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT) & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK; 967} 968 969#endif /* !defined(DEFS_LINUX_MAINLINE) */ 970#endif /* _ENA_ETH_IO_H_ */ 971