1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9	model = "Phytec phyFLEX-i.MX6 Quad";
10	compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
11
12	memory@10000000 {
13		device_type = "memory";
14		reg = <0x10000000 0x80000000>;
15	};
16
17	regulators {
18		compatible = "simple-bus";
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		reg_usb_otg_vbus: regulator@0 {
23			compatible = "regulator-fixed";
24			reg = <0>;
25			regulator-name = "usb_otg_vbus";
26			regulator-min-microvolt = <5000000>;
27			regulator-max-microvolt = <5000000>;
28			gpio = <&gpio4 15 0>;
29			enable-active-high;
30		};
31
32		reg_usb_h1_vbus: regulator@1 {
33			compatible = "regulator-fixed";
34			reg = <1>;
35			regulator-name = "usb_h1_vbus";
36			regulator-min-microvolt = <5000000>;
37			regulator-max-microvolt = <5000000>;
38			gpio = <&gpio1 0 0>;
39			enable-active-high;
40		};
41	};
42
43	gpio_leds: leds {
44		compatible = "gpio-leds";
45
46		green {
47			label = "phyflex:green";
48			gpios = <&gpio1 30 0>;
49		};
50
51		red {
52			label = "phyflex:red";
53			gpios = <&gpio2 31 0>;
54		};
55	};
56};
57
58&audmux {
59	pinctrl-names = "default";
60	pinctrl-0 = <&pinctrl_audmux>;
61	status = "disabled";
62};
63
64&can1 {
65	pinctrl-names = "default";
66	pinctrl-0 = <&pinctrl_flexcan1>;
67	status = "disabled";
68};
69
70&ecspi3 {
71	pinctrl-names = "default";
72	pinctrl-0 = <&pinctrl_ecspi3>;
73	status = "okay";
74	cs-gpios = <&gpio4 24 0>;
75
76	som_flash: flash@0 {
77		compatible = "m25p80", "jedec,spi-nor";
78		spi-max-frequency = <20000000>;
79		reg = <0>;
80	};
81};
82
83&fec {
84	pinctrl-names = "default";
85	pinctrl-0 = <&pinctrl_enet>;
86	phy-handle = <&ethphy>;
87	phy-mode = "rgmii";
88	phy-reset-duration = <10>; /* in msecs */
89	phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
90	phy-supply = <&vdd_eth_io_reg>;
91	status = "disabled";
92
93	fec_mdio: mdio {
94		#address-cells = <1>;
95		#size-cells = <0>;
96
97		ethphy: ethernet-phy@0 {
98			compatible = "ethernet-phy-ieee802.3-c22";
99			reg = <0>;
100			txc-skew-ps = <1680>;
101			rxc-skew-ps = <1860>;
102		};
103	};
104};
105
106&gpmi {
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_gpmi_nand>;
109	nand-on-flash-bbt;
110	status = "okay";
111};
112
113&i2c1 {
114	pinctrl-names = "default";
115	pinctrl-0 = <&pinctrl_i2c1>;
116	status = "okay";
117
118	som_eeprom: eeprom@50 {
119		compatible = "atmel,24c32";
120		reg = <0x50>;
121	};
122
123	pmic@58 {
124		compatible = "dlg,da9063";
125		reg = <0x58>;
126		interrupt-parent = <&gpio2>;
127		interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
128		interrupt-controller;
129
130		regulators {
131			vddcore_reg: bcore1 {
132				regulator-min-microvolt = <730000>;
133				regulator-max-microvolt = <1380000>;
134				regulator-always-on;
135			};
136
137			vddsoc_reg: bcore2 {
138				regulator-min-microvolt = <730000>;
139				regulator-max-microvolt = <1380000>;
140				regulator-always-on;
141			};
142
143			vdd_ddr3_reg: bpro {
144				regulator-min-microvolt = <1500000>;
145				regulator-max-microvolt = <1500000>;
146				regulator-always-on;
147			};
148
149			vdd_3v3_reg: bperi {
150				regulator-min-microvolt = <3300000>;
151				regulator-max-microvolt = <3300000>;
152				regulator-always-on;
153			};
154
155			vdd_buckmem_reg: bmem {
156				regulator-min-microvolt = <3300000>;
157				regulator-max-microvolt = <3300000>;
158				regulator-always-on;
159			};
160
161			vdd_eth_reg: bio {
162				regulator-min-microvolt = <1200000>;
163				regulator-max-microvolt = <1200000>;
164				regulator-always-on;
165			};
166
167			vdd_eth_io_reg: ldo4 {
168				regulator-min-microvolt = <2500000>;
169				regulator-max-microvolt = <2500000>;
170				regulator-always-on;
171			};
172
173			vdd_mx6_snvs_reg: ldo5 {
174				regulator-min-microvolt = <3000000>;
175				regulator-max-microvolt = <3000000>;
176				regulator-always-on;
177			};
178
179			vdd_3v3_pmic_io_reg: ldo6 {
180				regulator-min-microvolt = <3300000>;
181				regulator-max-microvolt = <3300000>;
182				regulator-always-on;
183			};
184
185			vdd_sd0_reg: ldo9 {
186				regulator-min-microvolt = <3300000>;
187				regulator-max-microvolt = <3300000>;
188			};
189
190			vdd_sd1_reg: ldo10 {
191				regulator-min-microvolt = <3300000>;
192				regulator-max-microvolt = <3300000>;
193			};
194
195			vdd_mx6_high_reg: ldo11 {
196				regulator-min-microvolt = <3000000>;
197				regulator-max-microvolt = <3000000>;
198				regulator-always-on;
199			};
200		};
201	};
202};
203
204&i2c2 {
205	pinctrl-names = "default";
206	pinctrl-0 = <&pinctrl_i2c2>;
207	clock-frequency = <100000>;
208};
209
210&i2c3 {
211	pinctrl-names = "default";
212	pinctrl-0 = <&pinctrl_i2c3>;
213	clock-frequency = <100000>;
214};
215
216&iomuxc {
217	pinctrl-names = "default";
218	pinctrl-0 = <&pinctrl_hog>;
219
220	imx6q-phytec-pfla02 {
221		pinctrl_hog: hoggrp {
222			fsl,pins = <
223				MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
224				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
225				MX6QDL_PAD_SD4_DAT1__GPIO2_IO09  0x80000000 /* PMIC interrupt */
226				MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
227				MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
228			>;
229		};
230
231		pinctrl_ecspi3: ecspi3grp {
232			fsl,pins = <
233				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
234				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
235				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
236			>;
237		};
238
239		pinctrl_enet: enetgrp {
240			fsl,pins = <
241				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
242				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
243				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
244				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
245				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
246				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
247				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
248				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
249				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
250				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
251				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
252				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
253				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
254				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
255				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
256				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
257			>;
258		};
259
260		pinctrl_flexcan1: flexcan1grp {
261			fsl,pins = <
262				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b0
263				MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
264			>;
265		};
266
267		pinctrl_gpmi_nand: gpminandgrp {
268			fsl,pins = <
269				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
270				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
271				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
272				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
273				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
274				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
275				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
276				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
277				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
278				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
279				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
280				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
281				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
282				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
283				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
284				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
285				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
286			>;
287		};
288
289		pinctrl_i2c1: i2c1grp {
290			fsl,pins = <
291				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
292				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
293			>;
294		};
295
296		pinctrl_i2c2: i2c2grp {
297			fsl,pins = <
298				MX6QDL_PAD_EIM_EB2__I2C2_SCL		0x4001b8b1
299				MX6QDL_PAD_EIM_D16__I2C2_SDA		0x4001b8b1
300			>;
301		};
302
303		pinctrl_i2c3: i2c3grp {
304			fsl,pins = <
305				MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
306				MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b8b1
307			>;
308		};
309
310		pinctrl_pcie: pciegrp {
311			fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
312		};
313
314		pinctrl_uart3: uart3grp {
315			fsl,pins = <
316				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
317				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
318				MX6QDL_PAD_EIM_D30__UART3_RTS_B		0x1b0b1
319				MX6QDL_PAD_EIM_D31__UART3_CTS_B		0x1b0b1
320			>;
321		};
322
323		pinctrl_uart4: uart4grp {
324			fsl,pins = <
325				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
326				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
327			>;
328		};
329
330		pinctrl_usbh1: usbh1grp {
331			fsl,pins = <
332				MX6QDL_PAD_GPIO_0__USB_H1_PWR		0x80000000
333			>;
334		};
335
336		pinctrl_usbotg: usbotggrp {
337			fsl,pins = <
338				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
339				MX6QDL_PAD_KEY_COL4__USB_OTG_OC		0x1b0b0
340				MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x80000000
341			>;
342		};
343
344		pinctrl_usdhc2: usdhc2grp {
345			fsl,pins = <
346				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
347				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
348				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
349				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
350				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
351				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
352			>;
353		};
354
355		pinctrl_usdhc3: usdhc3grp {
356			fsl,pins = <
357				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
358				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
359				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
360				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
361				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
362				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
363			>;
364		};
365
366		pinctrl_usdhc3_cdwp: usdhc3cdwp {
367			fsl,pins = <
368				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
369				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
370			>;
371		};
372
373		pinctrl_audmux: audmuxgrp {
374			fsl,pins = <
375				MX6QDL_PAD_DISP0_DAT16__AUD5_TXC	0x130b0
376				MX6QDL_PAD_DISP0_DAT17__AUD5_TXD	0x110b0
377				MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS	0x130b0
378				MX6QDL_PAD_DISP0_DAT19__AUD5_RXD	0x130b0
379			>;
380		};
381	};
382};
383
384&pcie {
385	pinctrl-names = "default";
386	pinctrl-0 = <&pinctrl_pcie>;
387	reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
388	status = "disabled";
389};
390
391&reg_arm {
392	vin-supply = <&vddcore_reg>;
393};
394
395&reg_pu {
396	vin-supply = <&vddsoc_reg>;
397};
398
399&reg_soc {
400	vin-supply = <&vddsoc_reg>;
401};
402
403&uart3 {
404	pinctrl-names = "default";
405	pinctrl-0 = <&pinctrl_uart3>;
406	status = "disabled";
407};
408
409&uart4 {
410	pinctrl-names = "default";
411	pinctrl-0 = <&pinctrl_uart4>;
412	status = "disabled";
413};
414
415&usbh1 {
416	vbus-supply = <&reg_usb_h1_vbus>;
417	pinctrl-names = "default";
418	pinctrl-0 = <&pinctrl_usbh1>;
419	status = "disabled";
420};
421
422&usbotg {
423	vbus-supply = <&reg_usb_otg_vbus>;
424	pinctrl-names = "default";
425	pinctrl-0 = <&pinctrl_usbotg>;
426	disable-over-current;
427	status = "disabled";
428};
429
430&usdhc2 {
431	pinctrl-names = "default";
432	pinctrl-0 = <&pinctrl_usdhc2>;
433	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
434	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
435	status = "disabled";
436};
437
438&usdhc3 {
439	pinctrl-names = "default";
440	pinctrl-0 = <&pinctrl_usdhc3
441		     &pinctrl_usdhc3_cdwp>;
442	cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
443	wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
444	status = "disabled";
445};
446