1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8
9/ {
10	/* these are used by bootloader for disabling nodes */
11	aliases {
12		led0 = &led0;
13		led1 = &led1;
14		nand = &gpmi;
15		usb0 = &usbh1;
16		usb1 = &usbotg;
17	};
18
19	chosen {
20		stdout-path = &uart2;
21	};
22
23	gpio-keys {
24		compatible = "gpio-keys";
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		user-pb {
29			label = "user_pb";
30			gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
31			linux,code = <BTN_0>;
32		};
33
34		user-pb1x {
35			label = "user_pb1x";
36			linux,code = <BTN_1>;
37			interrupt-parent = <&gsc>;
38			interrupts = <0>;
39		};
40
41		key-erased {
42			label = "key-erased";
43			linux,code = <BTN_2>;
44			interrupt-parent = <&gsc>;
45			interrupts = <1>;
46		};
47
48		eeprom-wp {
49			label = "eeprom_wp";
50			linux,code = <BTN_3>;
51			interrupt-parent = <&gsc>;
52			interrupts = <2>;
53		};
54
55		tamper {
56			label = "tamper";
57			linux,code = <BTN_4>;
58			interrupt-parent = <&gsc>;
59			interrupts = <5>;
60		};
61
62		switch-hold {
63			label = "switch_hold";
64			linux,code = <BTN_5>;
65			interrupt-parent = <&gsc>;
66			interrupts = <7>;
67		};
68	};
69
70	leds {
71		compatible = "gpio-leds";
72		pinctrl-names = "default";
73		pinctrl-0 = <&pinctrl_gpio_leds>;
74
75		led0: user1 {
76			label = "user1";
77			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
78			default-state = "on";
79			linux,default-trigger = "heartbeat";
80		};
81
82		led1: user2 {
83			label = "user2";
84			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
85			default-state = "off";
86		};
87	};
88
89	memory@10000000 {
90		device_type = "memory";
91		reg = <0x10000000 0x20000000>;
92	};
93
94	pps {
95		compatible = "pps-gpio";
96		pinctrl-names = "default";
97		pinctrl-0 = <&pinctrl_pps>;
98		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
99		status = "okay";
100	};
101
102	reg_3p3v: regulator-3p3v {
103		compatible = "regulator-fixed";
104		regulator-name = "3P3V";
105		regulator-min-microvolt = <3300000>;
106		regulator-max-microvolt = <3300000>;
107		regulator-always-on;
108	};
109
110	reg_5p0v: regulator-5p0v {
111		compatible = "regulator-fixed";
112		regulator-name = "5P0V";
113		regulator-min-microvolt = <5000000>;
114		regulator-max-microvolt = <5000000>;
115		regulator-always-on;
116	};
117
118	reg_usb_otg_vbus: regulator-usb-otg-vbus {
119		compatible = "regulator-fixed";
120		regulator-name = "usb_otg_vbus";
121		regulator-min-microvolt = <5000000>;
122		regulator-max-microvolt = <5000000>;
123		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
124		enable-active-high;
125	};
126};
127
128&fec {
129	pinctrl-names = "default";
130	pinctrl-0 = <&pinctrl_enet>;
131	phy-mode = "rgmii-id";
132	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
133	status = "okay";
134};
135
136&gpmi {
137	pinctrl-names = "default";
138	pinctrl-0 = <&pinctrl_gpmi_nand>;
139	status = "okay";
140};
141
142&hdmi {
143	ddc-i2c-bus = <&i2c3>;
144	status = "okay";
145};
146
147&i2c1 {
148	clock-frequency = <100000>;
149	pinctrl-names = "default";
150	pinctrl-0 = <&pinctrl_i2c1>;
151	status = "okay";
152
153	gsc: gsc@20 {
154		compatible = "gw,gsc";
155		reg = <0x20>;
156		interrupt-parent = <&gpio1>;
157		interrupts = <4 GPIO_ACTIVE_LOW>;
158		interrupt-controller;
159		#interrupt-cells = <1>;
160		#size-cells = <0>;
161
162		adc {
163			compatible = "gw,gsc-adc";
164			#address-cells = <1>;
165			#size-cells = <0>;
166
167			channel@0 {
168				gw,mode = <0>;
169				reg = <0x00>;
170				label = "temp";
171			};
172
173			channel@2 {
174				gw,mode = <1>;
175				reg = <0x02>;
176				label = "vdd_vin";
177			};
178
179			channel@5 {
180				gw,mode = <1>;
181				reg = <0x05>;
182				label = "vdd_3p3";
183			};
184
185			channel@8 {
186				gw,mode = <1>;
187				reg = <0x08>;
188				label = "vdd_bat";
189			};
190
191			channel@b {
192				gw,mode = <1>;
193				reg = <0x0b>;
194				label = "vdd_5p0";
195			};
196
197			channel@e {
198				gw,mode = <1>;
199				reg = <0xe>;
200				label = "vdd_arm";
201			};
202
203			channel@11 {
204				gw,mode = <1>;
205				reg = <0x11>;
206				label = "vdd_soc";
207			};
208
209			channel@14 {
210				gw,mode = <1>;
211				reg = <0x14>;
212				label = "vdd_3p0";
213			};
214
215			channel@17 {
216				gw,mode = <1>;
217				reg = <0x17>;
218				label = "vdd_1p5";
219			};
220
221			channel@1d {
222				gw,mode = <1>;
223				reg = <0x1d>;
224				label = "vdd_1p8";
225			};
226
227			channel@20 {
228				gw,mode = <1>;
229				reg = <0x20>;
230				label = "vdd_an1";
231			};
232
233			channel@23 {
234				gw,mode = <1>;
235				reg = <0x23>;
236				label = "vdd_2p5";
237			};
238		};
239	};
240
241	gsc_gpio: gpio@23 {
242		compatible = "nxp,pca9555";
243		reg = <0x23>;
244		gpio-controller;
245		#gpio-cells = <2>;
246		interrupt-parent = <&gsc>;
247		interrupts = <4>;
248	};
249
250	eeprom@50 {
251		compatible = "atmel,24c02";
252		reg = <0x50>;
253		pagesize = <16>;
254	};
255
256	eeprom@51 {
257		compatible = "atmel,24c02";
258		reg = <0x51>;
259		pagesize = <16>;
260	};
261
262	eeprom@52 {
263		compatible = "atmel,24c02";
264		reg = <0x52>;
265		pagesize = <16>;
266	};
267
268	eeprom@53 {
269		compatible = "atmel,24c02";
270		reg = <0x53>;
271		pagesize = <16>;
272	};
273
274	ds1672@68 {
275		compatible = "dallas,ds1672";
276		reg = <0x68>;
277	};
278};
279
280&i2c2 {
281	clock-frequency = <100000>;
282	pinctrl-names = "default";
283	pinctrl-0 = <&pinctrl_i2c2>;
284	status = "okay";
285};
286
287&i2c3 {
288	clock-frequency = <100000>;
289	pinctrl-names = "default";
290	pinctrl-0 = <&pinctrl_i2c3>;
291	status = "okay";
292
293	gpio@20 {
294		compatible = "nxp,pca9555";
295		reg = <0x20>;
296		gpio-controller;
297		#gpio-cells = <2>;
298	};
299
300	adc@48 {
301		compatible = "ti,ads1015";
302		reg = <0x48>;
303		#address-cells = <1>;
304		#size-cells = <0>;
305
306		channel@4 {
307			reg = <4>;
308			ti,gain = <0>;
309			ti,datarate = <5>;
310		};
311
312		channel@5 {
313			reg = <5>;
314			ti,gain = <0>;
315			ti,datarate = <5>;
316		};
317
318		channel@6 {
319			reg = <6>;
320			ti,gain = <0>;
321			ti,datarate = <5>;
322		};
323	};
324};
325
326&pcie {
327	pinctrl-names = "default";
328	pinctrl-0 = <&pinctrl_pcie>;
329	reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
330	status = "okay";
331};
332
333&pwm2 {
334	pinctrl-names = "default";
335	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
336	status = "disabled";
337};
338
339&pwm3 {
340	pinctrl-names = "default";
341	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
342	status = "disabled";
343};
344
345&pwm4 {
346	pinctrl-names = "default";
347	pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
348	status = "disabled";
349};
350
351&uart1 {
352	pinctrl-names = "default";
353	pinctrl-0 = <&pinctrl_uart1>;
354	status = "okay";
355};
356
357&uart2 {
358	pinctrl-names = "default";
359	pinctrl-0 = <&pinctrl_uart2>;
360	status = "okay";
361};
362
363&uart3 {
364	pinctrl-names = "default";
365	pinctrl-0 = <&pinctrl_uart3>;
366	status = "okay";
367};
368
369&uart5 {
370	pinctrl-names = "default";
371	pinctrl-0 = <&pinctrl_uart5>;
372	status = "okay";
373};
374
375&usbotg {
376	vbus-supply = <&reg_usb_otg_vbus>;
377	pinctrl-names = "default";
378	pinctrl-0 = <&pinctrl_usbotg>;
379	disable-over-current;
380	status = "okay";
381};
382
383&usbh1 {
384	status = "okay";
385};
386
387&wdog1 {
388	pinctrl-names = "default";
389	pinctrl-0 = <&pinctrl_wdog>;
390	fsl,ext-reset-output;
391};
392
393&iomuxc {
394	pinctrl_enet: enetgrp {
395		fsl,pins = <
396			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
397			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
398			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
399			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
400			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
401			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
402			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
403			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
404			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
405			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
406			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
407			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
408			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
409			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
410			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
411			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
412			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x1b0b0
413		>;
414	};
415
416	pinctrl_gpio_leds: gpioledsgrp {
417		fsl,pins = <
418			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
419			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
420		>;
421	};
422
423	pinctrl_gpmi_nand: gpminandgrp {
424		fsl,pins = <
425			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
426			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
427			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
428			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
429			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
430			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
431			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
432			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
433			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
434			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
435			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
436			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
437			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
438			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
439			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
440		>;
441	};
442
443	pinctrl_i2c1: i2c1grp {
444		fsl,pins = <
445			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
446			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
447			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x0001b0b0
448		>;
449	};
450
451	pinctrl_i2c2: i2c2grp {
452		fsl,pins = <
453			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
454			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
455		>;
456	};
457
458	pinctrl_i2c3: i2c3grp {
459		fsl,pins = <
460			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
461			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
462			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1b0b0
463			MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b0
464		>;
465	};
466
467	pinctrl_pcie: pciegrp {
468		fsl,pins = <
469			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x1b0b0
470		>;
471	};
472
473	pinctrl_pps: ppsgrp {
474		fsl,pins = <
475			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
476		>;
477	};
478
479	pinctrl_pwm2: pwm2grp {
480		fsl,pins = <
481			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
482		>;
483	};
484
485	pinctrl_pwm3: pwm3grp {
486		fsl,pins = <
487			MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
488		>;
489	};
490
491	pinctrl_pwm4: pwm4grp {
492		fsl,pins = <
493			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
494		>;
495	};
496
497	pinctrl_uart1: uart1grp {
498		fsl,pins = <
499			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
500			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
501		>;
502	};
503
504	pinctrl_uart2: uart2grp {
505		fsl,pins = <
506			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
507			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
508		>;
509	};
510
511	pinctrl_uart3: uart3grp {
512		fsl,pins = <
513			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
514			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
515		>;
516	};
517
518	pinctrl_uart5: uart5grp {
519		fsl,pins = <
520			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
521			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
522		>;
523	};
524
525	pinctrl_usbotg: usbotggrp {
526		fsl,pins = <
527			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
528			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0
529		>;
530	};
531
532	pinctrl_wdog: wdoggrp {
533		fsl,pins = <
534			MX6QDL_PAD_DISP0_DAT8__WDOG1_B		0x1b0b0
535		>;
536	};
537};
538