1/* 2 * Copyright 2017 Gateworks Corporation 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/gpio/gpio.h> 49#include <dt-bindings/input/linux-event-codes.h> 50 51/ { 52 chosen { 53 stdout-path = &uart2; 54 }; 55 56 backlight { 57 compatible = "pwm-backlight"; 58 pwms = <&pwm1 0 5000000>; 59 brightness-levels = < 60 0 1 2 3 4 5 6 7 8 9 61 10 11 12 13 14 15 16 17 18 19 62 20 21 22 23 24 25 26 27 28 29 63 30 31 32 33 34 35 36 37 38 39 64 40 41 42 43 44 45 46 47 48 49 65 50 51 52 53 54 55 56 57 58 59 66 60 61 62 63 64 65 66 67 68 69 67 70 71 72 73 74 75 76 77 78 79 68 80 81 82 83 84 85 86 87 88 89 69 90 91 92 93 94 95 96 97 98 99 70 100 71 >; 72 default-brightness-level = <100>; 73 }; 74 75 gpio-keys { 76 compatible = "gpio-keys"; 77 #address-cells = <1>; 78 #size-cells = <0>; 79 80 user-pb { 81 label = "user_pb"; 82 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 83 linux,code = <BTN_0>; 84 }; 85 86 user-pb1x { 87 label = "user_pb1x"; 88 linux,code = <BTN_1>; 89 interrupt-parent = <&gsc>; 90 interrupts = <0>; 91 }; 92 93 key-erased { 94 label = "key-erased"; 95 linux,code = <BTN_2>; 96 interrupt-parent = <&gsc>; 97 interrupts = <1>; 98 }; 99 100 eeprom-wp { 101 label = "eeprom_wp"; 102 linux,code = <BTN_3>; 103 interrupt-parent = <&gsc>; 104 interrupts = <2>; 105 }; 106 107 tamper { 108 label = "tamper"; 109 linux,code = <BTN_4>; 110 interrupt-parent = <&gsc>; 111 interrupts = <5>; 112 }; 113 114 switch-hold { 115 label = "switch_hold"; 116 linux,code = <BTN_5>; 117 interrupt-parent = <&gsc>; 118 interrupts = <7>; 119 }; 120 }; 121 122 leds { 123 compatible = "gpio-leds"; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_gpio_leds>; 126 127 led0: user1 { 128 label = "user1"; 129 gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 130 default-state = "off"; 131 }; 132 }; 133 134 memory@10000000 { 135 device_type = "memory"; 136 reg = <0x10000000 0x40000000>; 137 }; 138 139 reg_5p0v: regulator-5p0v { 140 compatible = "regulator-fixed"; 141 regulator-name = "5P0V"; 142 regulator-min-microvolt = <5000000>; 143 regulator-max-microvolt = <5000000>; 144 regulator-always-on; 145 }; 146 147 reg_3p3v: regulator-3p3v { 148 compatible = "regulator-fixed"; 149 regulator-name = "3P3V"; 150 regulator-min-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>; 152 regulator-always-on; 153 }; 154 155 reg_2p5v: regulator-2p5v { 156 compatible = "regulator-fixed"; 157 regulator-name = "2P5V"; 158 regulator-min-microvolt = <2500000>; 159 regulator-max-microvolt = <2500000>; 160 regulator-always-on; 161 }; 162 163 reg_usb_h1_vbus: regulator-usb-h1-vbus { 164 compatible = "regulator-fixed"; 165 regulator-name = "usb_h1_vbus"; 166 regulator-min-microvolt = <5000000>; 167 regulator-max-microvolt = <5000000>; 168 gpio = <&gpio3 30 0>; 169 enable-active-high; 170 }; 171 172 reg_usb_otg_vbus: regulator-usb-otg-vbus { 173 compatible = "regulator-fixed"; 174 regulator-name = "usb_otg_vbus"; 175 regulator-min-microvolt = <5000000>; 176 regulator-max-microvolt = <5000000>; 177 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; 178 enable-active-high; 179 }; 180 181 reg_12p0: regulator-12p0v { 182 compatible = "regulator-fixed"; 183 regulator-name = "12P0V"; 184 regulator-min-microvolt = <12000000>; 185 regulator-max-microvolt = <12000000>; 186 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 187 enable-active-high; 188 }; 189 190 sound { 191 compatible = "fsl,imx-audio-tlv320"; 192 model = "imx-tlv320"; 193 ssi-controller = <&ssi1>; 194 audio-codec = <&tlv320aic3105>; 195 /* routing of sink, source */ 196 audio-routing = 197 /* TLV320 LINE1L pin <-> Mic Jack connector */ 198 "LINE1L", "Mic Jack", 199 /* board Headphone Jack <-> HPOUT */ 200 "Headphone Jack", "HPLOUT", 201 "Headphone Jack", "HPROUT", 202 "Mic Jack", "Mic Bias"; 203 mux-int-port = <1>; 204 mux-ext-port = <6>; 205 }; 206}; 207 208&audmux { 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_audmux>; 211 status = "okay"; 212}; 213 214&clks { 215 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 216 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 217 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 218 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 219}; 220 221&fec { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_enet>; 224 phy-mode = "rgmii-id"; 225 status = "okay"; 226}; 227 228&i2c1 { 229 clock-frequency = <100000>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_i2c1>; 232 status = "okay"; 233 234 gsc: gsc@20 { 235 compatible = "gw,gsc"; 236 reg = <0x20>; 237 interrupt-parent = <&gpio1>; 238 interrupts = <4 GPIO_ACTIVE_LOW>; 239 interrupt-controller; 240 #interrupt-cells = <1>; 241 #size-cells = <0>; 242 243 adc { 244 compatible = "gw,gsc-adc"; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 248 channel@0 { 249 gw,mode = <0>; 250 reg = <0x00>; 251 label = "temp"; 252 }; 253 254 channel@2 { 255 gw,mode = <1>; 256 reg = <0x02>; 257 label = "vdd_vin"; 258 }; 259 260 channel@5 { 261 gw,mode = <1>; 262 reg = <0x05>; 263 label = "vdd_3p3"; 264 }; 265 266 channel@8 { 267 gw,mode = <1>; 268 reg = <0x08>; 269 label = "vdd_bat"; 270 }; 271 272 channel@b { 273 gw,mode = <1>; 274 reg = <0x0b>; 275 label = "vdd_5p0"; 276 }; 277 278 channel@e { 279 gw,mode = <1>; 280 reg = <0xe>; 281 label = "vdd_arm"; 282 }; 283 284 channel@11 { 285 gw,mode = <1>; 286 reg = <0x11>; 287 label = "vdd_soc"; 288 }; 289 290 channel@14 { 291 gw,mode = <1>; 292 reg = <0x14>; 293 label = "vdd_3p0"; 294 }; 295 296 channel@17 { 297 gw,mode = <1>; 298 reg = <0x17>; 299 label = "vdd_1p5"; 300 }; 301 302 channel@1d { 303 gw,mode = <1>; 304 reg = <0x1d>; 305 label = "vdd_1p8"; 306 }; 307 308 channel@20 { 309 gw,mode = <1>; 310 reg = <0x20>; 311 label = "vdd_an1"; 312 }; 313 314 channel@23 { 315 gw,mode = <1>; 316 reg = <0x23>; 317 label = "vdd_2p5"; 318 }; 319 }; 320 }; 321 322 gsc_gpio: gpio@23 { 323 compatible = "nxp,pca9555"; 324 reg = <0x23>; 325 gpio-controller; 326 #gpio-cells = <2>; 327 interrupt-parent = <&gsc>; 328 interrupts = <4>; 329 }; 330 331 eeprom1: eeprom@50 { 332 compatible = "atmel,24c02"; 333 reg = <0x50>; 334 pagesize = <16>; 335 }; 336 337 eeprom2: eeprom@51 { 338 compatible = "atmel,24c02"; 339 reg = <0x51>; 340 pagesize = <16>; 341 }; 342 343 eeprom3: eeprom@52 { 344 compatible = "atmel,24c02"; 345 reg = <0x52>; 346 pagesize = <16>; 347 }; 348 349 eeprom4: eeprom@53 { 350 compatible = "atmel,24c02"; 351 reg = <0x53>; 352 pagesize = <16>; 353 }; 354 355 dts1672: rtc@68 { 356 compatible = "dallas,ds1672"; 357 reg = <0x68>; 358 }; 359}; 360 361&i2c2 { 362 clock-frequency = <400000>; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&pinctrl_i2c2>; 365 status = "okay"; 366 367 ltc3676: pmic@3c { 368 compatible = "lltc,ltc3676"; 369 reg = <0x3c>; 370 interrupt-parent = <&gpio1>; 371 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 372 373 regulators { 374 /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */ 375 reg_1p8v: sw1 { 376 regulator-name = "vdd1p8"; 377 regulator-min-microvolt = <1033310>; 378 regulator-max-microvolt = <2004000>; 379 lltc,fb-voltage-divider = <301000 200000>; 380 regulator-ramp-delay = <7000>; 381 regulator-boot-on; 382 regulator-always-on; 383 }; 384 385 /* VDD_DDR (1+R1/R2 = 2.105) */ 386 reg_vdd_ddr: sw2 { 387 regulator-name = "vddddr"; 388 regulator-min-microvolt = <868310>; 389 regulator-max-microvolt = <1684000>; 390 lltc,fb-voltage-divider = <221000 200000>; 391 regulator-ramp-delay = <7000>; 392 regulator-boot-on; 393 regulator-always-on; 394 }; 395 396 /* VDD_ARM (1+R1/R2 = 1.635) */ 397 reg_vdd_arm: sw3 { 398 regulator-name = "vddarm"; 399 regulator-min-microvolt = <674400>; 400 regulator-max-microvolt = <1308000>; 401 lltc,fb-voltage-divider = <127000 200000>; 402 regulator-ramp-delay = <7000>; 403 regulator-boot-on; 404 regulator-always-on; 405 linux,phandle = <®_vdd_arm>; 406 }; 407 408 /* VDD_SOC (1+R1/R2 = 1.635) */ 409 reg_vdd_soc: sw4 { 410 regulator-name = "vddsoc"; 411 regulator-min-microvolt = <674400>; 412 regulator-max-microvolt = <1308000>; 413 lltc,fb-voltage-divider = <127000 200000>; 414 regulator-ramp-delay = <7000>; 415 regulator-boot-on; 416 regulator-always-on; 417 linux,phandle = <®_vdd_soc>; 418 }; 419 420 /* VDD_1P0 (1+R1/R2 = 1.38): */ 421 reg_1p0v: ldo2 { 422 regulator-name = "vdd1p0"; 423 regulator-min-microvolt = <1002777>; 424 regulator-max-microvolt = <1002777>; 425 lltc,fb-voltage-divider = <100000 261000>; 426 regulator-boot-on; 427 regulator-always-on; 428 }; 429 430 /* VDD_HIGH (1+R1/R2 = 4.17) */ 431 reg_3p0v: ldo4 { 432 regulator-name = "vdd3p0"; 433 regulator-min-microvolt = <3023250>; 434 regulator-max-microvolt = <3023250>; 435 lltc,fb-voltage-divider = <634000 200000>; 436 regulator-boot-on; 437 regulator-always-on; 438 }; 439 }; 440 }; 441}; 442 443&i2c3 { 444 clock-frequency = <400000>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pinctrl_i2c3>; 447 status = "okay"; 448 449 tlv320aic3105: codec@18 { 450 compatible = "ti,tlv320aic3x"; 451 reg = <0x18>; 452 reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; 453 clocks = <&clks IMX6QDL_CLK_CKO>; 454 ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ 455 /* Regulators */ 456 DRVDD-supply = <®_3p3v>; 457 AVDD-supply = <®_3p3v>; 458 IOVDD-supply = <®_3p3v>; 459 DVDD-supply = <®_1p8v>; 460 }; 461 462 accelerometer@1d { 463 compatible = "fsl,mma8451"; 464 reg = <0x1d>; 465 interrupt-parent = <&gpio7>; 466 interrupts = <11 IRQ_TYPE_EDGE_RISING>; 467 interrupt-names = "INT2"; 468 }; 469 470 /* headphone detect */ 471 ts3a227e@3b { 472 compatible = "ti,ts3a227e"; 473 reg = <0x3b>; 474 interrupt-parent = <&gpio5>; 475 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 476 ti,micbias = <4>; /* 2.5V micbias */ 477 }; 478}; 479 480&ldb { 481 status = "okay"; 482 483 lvds-channel@0 { 484 fsl,data-mapping = "spwg"; 485 fsl,data-width = <18>; 486 status = "okay"; 487 488 display-timings { 489 native-mode = <&timing0>; 490 timing0: g101evn010 { 491 clock-frequency = <68930000>; 492 hactive = <1280>; 493 vactive = <800>; 494 hback-porch = <220>; 495 hfront-porch = <40>; 496 vback-porch = <21>; 497 vfront-porch = <7>; 498 hsync-len = <60>; 499 vsync-len = <10>; 500 }; 501 }; 502 }; 503}; 504 505&pwm1 { 506 #pwm-cells = <2>; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&pinctrl_pwm1>; 509 status = "okay"; 510}; 511 512&ssi1 { 513 status = "okay"; 514}; 515 516&uart1 { 517 pinctrl-names = "default"; 518 pinctrl-0 = <&pinctrl_uart1>; 519 status = "okay"; 520}; 521 522&uart2 { 523 pinctrl-names = "default"; 524 pinctrl-0 = <&pinctrl_uart2>; 525 status = "okay"; 526}; 527 528&usbotg { 529 vbus-supply = <®_usb_otg_vbus>; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&pinctrl_usbotg>; 532 disable-over-current; 533 status = "okay"; 534}; 535 536&usbh1 { 537 vbus-supply = <®_usb_h1_vbus>; 538 status = "okay"; 539}; 540 541&usdhc1 { 542 pinctrl-names = "default"; 543 pinctrl-0 = <&pinctrl_usdhc1_200mhz>; 544 vmmc-supply = <®_3p3v>; 545 non-removable; 546 bus-width = <4>; 547 status = "okay"; 548}; 549 550&usdhc2 { 551 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 552 pinctrl-0 = <&pinctrl_usdhc2>; 553 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 554 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 555 cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 556 vmmc-supply = <®_3p3v>; 557 max-frequency = <100000000>; 558 status = "okay"; 559}; 560 561&usdhc3 { 562 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 563 pinctrl-0 = <&pinctrl_usdhc3>; 564 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 565 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 566 non-removable; 567 vmmc-supply = <®_3p3v>; 568 keep-power-in-suspend; 569 status = "okay"; 570}; 571 572&wdog1 { 573 pinctrl-names = "default"; 574 pinctrl-0 = <&pinctrl_wdog>; 575 fsl,ext-reset-output; 576}; 577 578&iomuxc { 579 pinctrl_audmux: audmuxgrp { 580 fsl,pins = < 581 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 582 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 583 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 584 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 585 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */ 586 >; 587 }; 588 589 pinctrl_enet: enetgrp { 590 fsl,pins = < 591 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 592 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 593 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 594 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 595 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 596 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 597 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 598 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 599 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 600 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 601 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 602 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 603 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 604 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 605 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 606 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 607 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */ 608 >; 609 }; 610 611 pinctrl_gpio_leds: gpioledsgrp { 612 fsl,pins = < 613 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 614 >; 615 }; 616 617 pinctrl_i2c1: i2c1grp { 618 fsl,pins = < 619 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 620 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 621 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 622 >; 623 }; 624 625 pinctrl_i2c2: i2c2grp { 626 fsl,pins = < 627 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 628 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 629 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 630 >; 631 }; 632 633 pinctrl_i2c3: i2c3grp { 634 fsl,pins = < 635 /* I2C3 */ 636 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 637 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 638 639 /* Headphone Detect */ 640 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */ 641 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */ 642 643 /* Codec */ 644 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */ 645 646 /* Touch Controller */ 647 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */ 648 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */ 649 650 /* Stow Sensor */ 651 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */ 652 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */ 653 >; 654 }; 655 656 pinctrl_pwm1: pwm1grp { 657 fsl,pins = < 658 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 659 >; 660 }; 661 662 pinctrl_uart1: uart1grp { 663 fsl,pins = < 664 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 665 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 666 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */ 667 >; 668 }; 669 670 pinctrl_uart2: uart2grp { 671 fsl,pins = < 672 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 673 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 674 >; 675 }; 676 677 pinctrl_usbotg: usbotggrp { 678 fsl,pins = < 679 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 680 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */ 681 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 682 >; 683 }; 684 685 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 686 fsl,pins = < 687 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */ 688 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */ 689 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */ 690 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */ 691 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */ 692 693 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 694 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9 695 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 696 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 697 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 698 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 699 >; 700 }; 701 702 pinctrl_usdhc2: usdhc2grp { 703 fsl,pins = < 704 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 705 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 706 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 707 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 708 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 709 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 710 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */ 711 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059 712 >; 713 }; 714 715 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 716 fsl,pins = < 717 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 718 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 719 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 720 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 721 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 722 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 723 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */ 724 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9 725 >; 726 }; 727 728 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 729 fsl,pins = < 730 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 731 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 732 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 733 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 734 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 735 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 736 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */ 737 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9 738 >; 739 }; 740 741 pinctrl_usdhc3: usdhc3grp { 742 fsl,pins = < 743 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 744 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 745 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 746 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 747 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 748 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 749 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 750 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 751 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 752 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 753 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 754 >; 755 }; 756 757 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 758 fsl,pins = < 759 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 760 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 761 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 762 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 763 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 764 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 765 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 766 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 767 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 768 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 769 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 770 >; 771 }; 772 773 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 774 fsl,pins = < 775 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 776 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 777 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 778 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 779 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 780 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 781 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 782 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 783 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 784 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 785 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 786 >; 787 }; 788 789 pinctrl_wdog: wdoggrp { 790 fsl,pins = < 791 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 792 >; 793 }; 794}; 795