1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2013 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8 9/ { 10 /* these are used by bootloader for disabling nodes */ 11 aliases { 12 led0 = &led0; 13 led1 = &led1; 14 led2 = &led2; 15 nand = &gpmi; 16 ssi0 = &ssi1; 17 usb0 = &usbh1; 18 usb1 = &usbotg; 19 }; 20 21 chosen { 22 bootargs = "console=ttymxc1,115200"; 23 }; 24 25 backlight { 26 compatible = "pwm-backlight"; 27 pwms = <&pwm4 0 5000000>; 28 brightness-levels = <0 4 8 16 32 64 128 255>; 29 default-brightness-level = <7>; 30 }; 31 32 gpio-keys { 33 compatible = "gpio-keys"; 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 user-pb { 38 label = "user_pb"; 39 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 40 linux,code = <BTN_0>; 41 }; 42 43 user-pb1x { 44 label = "user_pb1x"; 45 linux,code = <BTN_1>; 46 interrupt-parent = <&gsc>; 47 interrupts = <0>; 48 }; 49 50 key-erased { 51 label = "key-erased"; 52 linux,code = <BTN_2>; 53 interrupt-parent = <&gsc>; 54 interrupts = <1>; 55 }; 56 57 eeprom-wp { 58 label = "eeprom_wp"; 59 linux,code = <BTN_3>; 60 interrupt-parent = <&gsc>; 61 interrupts = <2>; 62 }; 63 64 tamper { 65 label = "tamper"; 66 linux,code = <BTN_4>; 67 interrupt-parent = <&gsc>; 68 interrupts = <5>; 69 }; 70 71 switch-hold { 72 label = "switch_hold"; 73 linux,code = <BTN_5>; 74 interrupt-parent = <&gsc>; 75 interrupts = <7>; 76 }; 77 }; 78 79 leds { 80 compatible = "gpio-leds"; 81 pinctrl-names = "default"; 82 pinctrl-0 = <&pinctrl_gpio_leds>; 83 84 led0: user1 { 85 label = "user1"; 86 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 87 default-state = "on"; 88 linux,default-trigger = "heartbeat"; 89 }; 90 91 led1: user2 { 92 label = "user2"; 93 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 94 default-state = "off"; 95 }; 96 97 led2: user3 { 98 label = "user3"; 99 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 100 default-state = "off"; 101 }; 102 }; 103 104 memory@10000000 { 105 device_type = "memory"; 106 reg = <0x10000000 0x20000000>; 107 }; 108 109 pps { 110 compatible = "pps-gpio"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pinctrl_pps>; 113 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 114 status = "okay"; 115 }; 116 117 reg_1p0v: regulator-1p0v { 118 compatible = "regulator-fixed"; 119 regulator-name = "1P0V"; 120 regulator-min-microvolt = <1000000>; 121 regulator-max-microvolt = <1000000>; 122 regulator-always-on; 123 }; 124 125 reg_3p3v: regulator-3p3v { 126 compatible = "regulator-fixed"; 127 regulator-name = "3P3V"; 128 regulator-min-microvolt = <3300000>; 129 regulator-max-microvolt = <3300000>; 130 regulator-always-on; 131 }; 132 133 reg_5p0v: regulator-5p0v { 134 compatible = "regulator-fixed"; 135 regulator-name = "5P0V"; 136 regulator-min-microvolt = <5000000>; 137 regulator-max-microvolt = <5000000>; 138 regulator-always-on; 139 }; 140 141 reg_usb_otg_vbus: regulator-usb-otg-vbus { 142 compatible = "regulator-fixed"; 143 regulator-name = "usb_otg_vbus"; 144 regulator-min-microvolt = <5000000>; 145 regulator-max-microvolt = <5000000>; 146 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 147 enable-active-high; 148 }; 149 150 sound { 151 compatible = "fsl,imx6q-ventana-sgtl5000", 152 "fsl,imx-audio-sgtl5000"; 153 model = "sgtl5000-audio"; 154 ssi-controller = <&ssi1>; 155 audio-codec = <&codec>; 156 audio-routing = 157 "MIC_IN", "Mic Jack", 158 "Mic Jack", "Mic Bias", 159 "Headphone Jack", "HP_OUT"; 160 mux-int-port = <1>; 161 mux-ext-port = <4>; 162 }; 163}; 164 165&audmux { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_audmux>; 168 status = "okay"; 169}; 170 171&can1 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_flexcan1>; 174 status = "okay"; 175}; 176 177&clks { 178 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 179 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 180 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 181 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 182}; 183 184&ecspi3 { 185 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_ecspi3>; 188 status = "okay"; 189}; 190 191&fec { 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_enet>; 194 phy-mode = "rgmii-id"; 195 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 196 status = "okay"; 197}; 198 199&gpmi { 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_gpmi_nand>; 202 status = "okay"; 203}; 204 205&hdmi { 206 ddc-i2c-bus = <&i2c3>; 207 status = "okay"; 208}; 209 210&i2c1 { 211 clock-frequency = <100000>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_i2c1>; 214 status = "okay"; 215 216 gsc: gsc@20 { 217 compatible = "gw,gsc"; 218 reg = <0x20>; 219 interrupt-parent = <&gpio1>; 220 interrupts = <4 GPIO_ACTIVE_LOW>; 221 interrupt-controller; 222 #interrupt-cells = <1>; 223 #size-cells = <0>; 224 225 adc { 226 compatible = "gw,gsc-adc"; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 230 channel@0 { 231 gw,mode = <0>; 232 reg = <0x00>; 233 label = "temp"; 234 }; 235 236 channel@2 { 237 gw,mode = <1>; 238 reg = <0x02>; 239 label = "vdd_vin"; 240 }; 241 242 channel@5 { 243 gw,mode = <1>; 244 reg = <0x05>; 245 label = "vdd_3p3"; 246 }; 247 248 channel@8 { 249 gw,mode = <1>; 250 reg = <0x08>; 251 label = "vdd_bat"; 252 }; 253 254 channel@b { 255 gw,mode = <1>; 256 reg = <0x0b>; 257 label = "vdd_5p0"; 258 }; 259 260 channel@e { 261 gw,mode = <1>; 262 reg = <0xe>; 263 label = "vdd_arm"; 264 }; 265 266 channel@11 { 267 gw,mode = <1>; 268 reg = <0x11>; 269 label = "vdd_soc"; 270 }; 271 272 channel@14 { 273 gw,mode = <1>; 274 reg = <0x14>; 275 label = "vdd_3p0"; 276 }; 277 278 channel@17 { 279 gw,mode = <1>; 280 reg = <0x17>; 281 label = "vdd_1p5"; 282 }; 283 284 channel@1d { 285 gw,mode = <1>; 286 reg = <0x1d>; 287 label = "vdd_1p8"; 288 }; 289 290 channel@20 { 291 gw,mode = <1>; 292 reg = <0x20>; 293 label = "vdd_1p0"; 294 }; 295 296 channel@23 { 297 gw,mode = <1>; 298 reg = <0x23>; 299 label = "vdd_2p5"; 300 }; 301 302 channel@29 { 303 gw,mode = <1>; 304 reg = <0x29>; 305 label = "vdd_an1"; 306 }; 307 }; 308 }; 309 310 gsc_gpio: gpio@23 { 311 compatible = "nxp,pca9555"; 312 reg = <0x23>; 313 gpio-controller; 314 #gpio-cells = <2>; 315 interrupt-parent = <&gsc>; 316 interrupts = <4>; 317 }; 318 319 eeprom1: eeprom@50 { 320 compatible = "atmel,24c02"; 321 reg = <0x50>; 322 pagesize = <16>; 323 }; 324 325 eeprom2: eeprom@51 { 326 compatible = "atmel,24c02"; 327 reg = <0x51>; 328 pagesize = <16>; 329 }; 330 331 eeprom3: eeprom@52 { 332 compatible = "atmel,24c02"; 333 reg = <0x52>; 334 pagesize = <16>; 335 }; 336 337 eeprom4: eeprom@53 { 338 compatible = "atmel,24c02"; 339 reg = <0x53>; 340 pagesize = <16>; 341 }; 342 343 rtc: ds1672@68 { 344 compatible = "dallas,ds1672"; 345 reg = <0x68>; 346 }; 347}; 348 349&i2c2 { 350 clock-frequency = <100000>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_i2c2>; 353 status = "okay"; 354 355 ltc3676: pmic@3c { 356 compatible = "lltc,ltc3676"; 357 reg = <0x3c>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pinctrl_pmic>; 360 interrupt-parent = <&gpio1>; 361 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 362 363 regulators { 364 /* VDD_SOC (1+R1/R2 = 1.635) */ 365 reg_vdd_soc: sw1 { 366 regulator-name = "vddsoc"; 367 regulator-min-microvolt = <674400>; 368 regulator-max-microvolt = <1308000>; 369 lltc,fb-voltage-divider = <127000 200000>; 370 regulator-ramp-delay = <7000>; 371 regulator-boot-on; 372 regulator-always-on; 373 }; 374 375 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ 376 reg_1p8v: sw2 { 377 regulator-name = "vdd1p8"; 378 regulator-min-microvolt = <1033310>; 379 regulator-max-microvolt = <2004000>; 380 lltc,fb-voltage-divider = <301000 200000>; 381 regulator-ramp-delay = <7000>; 382 regulator-boot-on; 383 regulator-always-on; 384 }; 385 386 /* VDD_ARM (1+R1/R2 = 1.635) */ 387 reg_vdd_arm: sw3 { 388 regulator-name = "vddarm"; 389 regulator-min-microvolt = <674400>; 390 regulator-max-microvolt = <1308000>; 391 lltc,fb-voltage-divider = <127000 200000>; 392 regulator-ramp-delay = <7000>; 393 regulator-boot-on; 394 regulator-always-on; 395 }; 396 397 /* VDD_DDR (1+R1/R2 = 2.105) */ 398 reg_vdd_ddr: sw4 { 399 regulator-name = "vddddr"; 400 regulator-min-microvolt = <868310>; 401 regulator-max-microvolt = <1684000>; 402 lltc,fb-voltage-divider = <221000 200000>; 403 regulator-ramp-delay = <7000>; 404 regulator-boot-on; 405 regulator-always-on; 406 }; 407 408 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 409 reg_2p5v: ldo2 { 410 regulator-name = "vdd2p5"; 411 regulator-min-microvolt = <2490375>; 412 regulator-max-microvolt = <2490375>; 413 lltc,fb-voltage-divider = <487000 200000>; 414 regulator-boot-on; 415 regulator-always-on; 416 }; 417 418 /* VDD_AUD_1P8: Audio codec */ 419 reg_aud_1p8v: ldo3 { 420 regulator-name = "vdd1p8"; 421 regulator-min-microvolt = <1800000>; 422 regulator-max-microvolt = <1800000>; 423 regulator-boot-on; 424 }; 425 426 /* VDD_HIGH (1+R1/R2 = 4.17) */ 427 reg_3p0v: ldo4 { 428 regulator-name = "vdd3p0"; 429 regulator-min-microvolt = <3023250>; 430 regulator-max-microvolt = <3023250>; 431 lltc,fb-voltage-divider = <634000 200000>; 432 regulator-boot-on; 433 regulator-always-on; 434 }; 435 }; 436 }; 437}; 438 439&i2c3 { 440 clock-frequency = <100000>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&pinctrl_i2c3>; 443 status = "okay"; 444 445 codec: sgtl5000@a { 446 compatible = "fsl,sgtl5000"; 447 reg = <0x0a>; 448 clocks = <&clks IMX6QDL_CLK_CKO>; 449 VDDA-supply = <®_1p8v>; 450 VDDIO-supply = <®_3p3v>; 451 }; 452 453 touchscreen: egalax_ts@4 { 454 compatible = "eeti,egalax_ts"; 455 reg = <0x04>; 456 interrupt-parent = <&gpio7>; 457 interrupts = <12 2>; 458 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; 459 }; 460 461 accel@1e { 462 compatible = "nxp,fxos8700"; 463 reg = <0x1e>; 464 }; 465}; 466 467&ldb { 468 status = "okay"; 469 470 lvds-channel@0 { 471 fsl,data-mapping = "spwg"; 472 fsl,data-width = <18>; 473 status = "okay"; 474 475 display-timings { 476 native-mode = <&timing0>; 477 timing0: hsd100pxn1 { 478 clock-frequency = <65000000>; 479 hactive = <1024>; 480 vactive = <768>; 481 hback-porch = <220>; 482 hfront-porch = <40>; 483 vback-porch = <21>; 484 vfront-porch = <7>; 485 hsync-len = <60>; 486 vsync-len = <10>; 487 }; 488 }; 489 }; 490}; 491 492&pcie { 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pinctrl_pcie>; 495 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; 496 status = "okay"; 497}; 498 499&pwm2 { 500 pinctrl-names = "default"; 501 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 502 status = "disabled"; 503}; 504 505&pwm3 { 506 pinctrl-names = "default"; 507 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 508 status = "disabled"; 509}; 510 511&pwm4 { 512 #pwm-cells = <2>; 513 pinctrl-names = "default"; 514 pinctrl-0 = <&pinctrl_pwm4>; 515 status = "okay"; 516}; 517 518&ssi1 { 519 status = "okay"; 520}; 521 522&uart1 { 523 pinctrl-names = "default"; 524 pinctrl-0 = <&pinctrl_uart1>; 525 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 526 status = "okay"; 527}; 528 529&uart2 { 530 pinctrl-names = "default"; 531 pinctrl-0 = <&pinctrl_uart2>; 532 status = "okay"; 533}; 534 535&uart5 { 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_uart5>; 538 status = "okay"; 539}; 540 541&usbotg { 542 vbus-supply = <®_usb_otg_vbus>; 543 pinctrl-names = "default"; 544 pinctrl-0 = <&pinctrl_usbotg>; 545 disable-over-current; 546 status = "okay"; 547}; 548 549&usbh1 { 550 status = "okay"; 551}; 552 553&usdhc3 { 554 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 555 pinctrl-0 = <&pinctrl_usdhc3>; 556 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 557 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 558 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 559 vmmc-supply = <®_3p3v>; 560 no-1-8-v; /* firmware will remove if board revision supports */ 561 status = "okay"; 562}; 563 564&wdog1 { 565 pinctrl-names = "default"; 566 pinctrl-0 = <&pinctrl_wdog>; 567 fsl,ext-reset-output; 568}; 569 570&iomuxc { 571 pinctrl_audmux: audmuxgrp { 572 fsl,pins = < 573 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 574 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 575 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 576 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 577 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 578 >; 579 }; 580 581 pinctrl_ecspi3: escpi3grp { 582 fsl,pins = < 583 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 584 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 585 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 586 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 587 >; 588 }; 589 590 pinctrl_enet: enetgrp { 591 fsl,pins = < 592 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 593 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 594 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 595 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 596 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 597 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 598 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 599 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 600 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 601 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 602 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 603 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 604 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 605 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 606 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 607 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 608 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ 609 >; 610 }; 611 612 pinctrl_flexcan1: flexcan1grp { 613 fsl,pins = < 614 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 615 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 616 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ 617 >; 618 }; 619 620 pinctrl_gpio_leds: gpioledsgrp { 621 fsl,pins = < 622 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 623 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 624 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 625 >; 626 }; 627 628 pinctrl_gpmi_nand: gpminandgrp { 629 fsl,pins = < 630 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 631 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 632 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 633 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 634 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 635 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 636 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 637 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 638 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 639 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 640 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 641 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 642 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 643 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 644 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 645 >; 646 }; 647 648 pinctrl_i2c1: i2c1grp { 649 fsl,pins = < 650 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 651 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 652 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 653 >; 654 }; 655 656 pinctrl_i2c2: i2c2grp { 657 fsl,pins = < 658 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 659 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 660 >; 661 }; 662 663 pinctrl_i2c3: i2c3grp { 664 fsl,pins = < 665 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 666 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 667 >; 668 }; 669 670 pinctrl_pcie: pciegrp { 671 fsl,pins = < 672 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ 673 >; 674 }; 675 676 pinctrl_pmic: pmicgrp { 677 fsl,pins = < 678 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 679 >; 680 }; 681 682 pinctrl_pps: ppsgrp { 683 fsl,pins = < 684 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 685 >; 686 }; 687 688 pinctrl_pwm2: pwm2grp { 689 fsl,pins = < 690 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 691 >; 692 }; 693 694 pinctrl_pwm3: pwm3grp { 695 fsl,pins = < 696 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 697 >; 698 }; 699 700 pinctrl_pwm4: pwm4grp { 701 fsl,pins = < 702 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 703 >; 704 }; 705 706 pinctrl_uart1: uart1grp { 707 fsl,pins = < 708 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 709 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 710 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 711 >; 712 }; 713 714 pinctrl_uart2: uart2grp { 715 fsl,pins = < 716 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 717 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 718 >; 719 }; 720 721 pinctrl_uart5: uart5grp { 722 fsl,pins = < 723 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 724 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 725 >; 726 }; 727 728 pinctrl_usbotg: usbotggrp { 729 fsl,pins = < 730 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 731 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 732 >; 733 }; 734 735 pinctrl_usdhc3: usdhc3grp { 736 fsl,pins = < 737 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 738 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 739 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 740 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 741 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 742 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 743 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 744 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 745 >; 746 }; 747 748 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 749 fsl,pins = < 750 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 751 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 752 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 753 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 754 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 755 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 756 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 757 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 758 >; 759 }; 760 761 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 762 fsl,pins = < 763 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 764 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 765 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 766 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 767 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 768 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 769 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 770 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 771 >; 772 }; 773 774 pinctrl_wdog: wdoggrp { 775 fsl,pins = < 776 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 777 >; 778 }; 779}; 780